31143 lines
1.8 MiB
31143 lines
1.8 MiB
; --------------------------------------------------------------------------------
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; @Title: GD32H7xx On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2025-06-30 NEJ
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; @Manufacturer: GigaDevice - GigaDevice Semiconductor Inc.
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; @Doc: Generated (TRACE32, build: 180251.), based on:
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; GD32H75E.svd (GD32H75E_DFP.1.1.0), GD32H7xx.svd (GD32H7xx_DFP.1.4.0)
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; @Core: Cortex-M7F
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; @Chip: GD32H7*
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; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pergd32h7xx.per 19683 2025-07-02 13:23:49Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M7F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 28. " DISFPUISSOPT ,DISFPUISSOPT" "No,Yes"
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bitfld.long 0x00 27. " DISCRITAXIRUW ,Disables critical AXI read-under-write" "No,Yes"
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bitfld.long 0x00 26. " DISDYNADD ,Disables dynamic allocation of ADD and SUB instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 21.--25. " DISISSCH1 ,DISISSCH1" "Normal,Not issued in ch1,,,,,,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
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bitfld.long 0x00 16.--20. " DISDI ,DISDI" "Normal,ch1,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
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bitfld.long 0x00 15. " DISCRITAXIRUR ,Disables critical AXI read-under-read" "No,Yes"
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textline " "
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bitfld.long 0x00 14. " DISBTACALLOC ,DISBTACALLOC" "No,Yes"
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bitfld.long 0x00 13. " DISBTACREAD ,DISBTACREAD" "No,Yes"
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bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
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textline " "
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bitfld.long 0x00 11. " DISRAMODE ,Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions" "No,Yes"
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bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
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textline ""
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group.long 0x10++0x03
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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group.long 0x14++0x07
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line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x04 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,ARMv7-M"
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newline
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC27=Cortex-M7"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,On writes, makes the NMI exception active. On reads, indicates the state of the exception" "Inactive,Active"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes, sets the PendSV exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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textline " "
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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textline " "
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,Writing 1 to this bit causes a local system reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,Determines whether the exception entry sequence guarantees 8-byte stack frame alignment, adjusting the SP if necessary before saving state" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise data access faults on handlers running at priority -1 or priority -2" "Lockup,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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bitfld.long 0x10 0. " NONBASETHRDENA ,Controls whether the processor can enter Thread mode at an execution priority level other than base level" "Disabled,Enabled"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,MemManage" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall status" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault status" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage status" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault status" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick status" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV status" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor status" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall status" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault status" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault status" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage status" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x13
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line.long 0x00 "HFSR,HardFault Status Register"
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eventfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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eventfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
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eventfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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eventfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not occurred,Occurred"
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eventfld.long 0x04 3. " VCATCH ,Indicates triggering of a Vector catch" "Not occurred,Occurred"
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eventfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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eventfld.long 0x04 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not occurred,Occurred"
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eventfld.long 0x04 0. " HALTED ,Indicates a debug event generated by a C_HALT or C_STEP request or a step request triggered by setting DEMCR.MON_STEP to 1" "Not occurred,Occurred"
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line.long 0x08 "MMFAR,MemManage Fault Address Register"
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line.long 0x0C "BFAR,BusFault Address Register"
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line.long 0x10 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Denied,Privileged,,Full"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Triggered Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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tree "Memory System"
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width 10.
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rgroup.long 0xD78++0x0B
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line.long 0x00 "CLIDR,Cache Level ID Register"
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bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,level 2,?..."
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bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,level 2,?..."
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bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,?..."
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textline " "
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bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
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bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
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bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
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textline " "
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bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
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bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
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bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
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line.long 0x04 "CTR,Cache Type Register"
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bitfld.long 0x04 29.--31. " FORMAT ,Indicates the implemented CTR format" ",,,,ARMv7,?..."
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bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
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bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
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textline " "
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bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "CCSIDR,Cache Size ID Register"
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bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
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bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
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bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
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textline " "
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bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
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hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
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hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
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textline " "
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bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
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group.long 0xD84++0x03
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line.long 0x00 "CSSELR,Cache Size Selection Register"
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bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,?..."
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bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data,Instruction"
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wgroup.long 0xF50++0x03
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line.long 0x00 "ICIALLU,Instruction cache invalidate all to Point of Unification"
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wgroup.long 0xF58++0x1F
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line.long 0x00 "ICIMVAU,Instruction cache invalidate by address to PoU"
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line.long 0x04 "DCIMVAC,Data cache invalidate by address to Point of Coherency (PoC)"
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line.long 0x08 "DCISW,Data cache invalidate by set/way"
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line.long 0x0C "DCCMVAU,Data cache by address to PoU"
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line.long 0x10 "DCCMVAC,Data cache clean by address to PoC"
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line.long 0x14 "DCCSW,Data cache clean by set/way"
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line.long 0x18 "DCCIMVAC,Data cache clean and invalidate by address to PoC"
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line.long 0x1C "DCCISW,Data cache clean and invalidate by set/way"
|
|
group.long 0xF90++0x13
|
|
line.long 0x00 "ITCMCR,Instruction Tightly-Coupled Memory Control Register"
|
|
bitfld.long 0x00 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
|
|
bitfld.long 0x00 2. " RETEN ,Retry phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTCMCR,Data Tightly-Coupled Memory Control Register"
|
|
bitfld.long 0x04 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
|
|
bitfld.long 0x04 2. " RETEN ,Retry phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x08 "AHBPCR,AHBP control register"
|
|
bitfld.long 0x08 1.--3. " SZ ,AHBP size" "AHBP disabled,64 MB,128 MB,256 MB,512 MB,?..."
|
|
bitfld.long 0x08 0. " EN ,AHBP enable" "Disabled,Enabled"
|
|
line.long 0x0C "CACR,L1 Cache Control Register"
|
|
bitfld.long 0x0C 2. " FORCEWT ,Enables Force Write-through in the data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " ECCDIS ,Disables ECC in the instruction and data cache" "No,Yes"
|
|
bitfld.long 0x0C 0. " SIWT ,Enables limited cache coherency usage" "Disabled,Enabled"
|
|
line.long 0x10 "AHBSCR,AHB Slave Control Register"
|
|
bitfld.long 0x10 11.--15. " INITCOUNT ,Fairness counter initialization value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x10 2.--10. 1. " TPRI ,Threshold execution priority for AHBS traffic demotion"
|
|
bitfld.long 0x10 0.--1. " CTL ,AHBS prioritization control" "AHBS,Software,AHBSCR.INITCOUNT,AHBSPRI"
|
|
group.long 0xFA8++0x03
|
|
line.long 0x00 "ABFSR,Auxiliary Bus Fault Status Register"
|
|
bitfld.long 0x00 8.--9. " AXIMTYPE ,Indicates the type of fault on the AXIM interface" "OKAY,EXOKAY,SLVERR,DECERR"
|
|
bitfld.long 0x00 4. " EPPB ,Asynchronous fault on EPPB interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " AXIM ,Asynchronous fault on AXIM interface" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AHBP ,Asynchronous fault on AHBP interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " DTCM ,Asynchronous fault on DTCM interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ITCM ,Asynchronous fault on ITCM interface" "Not occurred,Occurred"
|
|
group.long 0xFB0++0x03
|
|
line.long 0x00 "IEBR0,Instruction Error bank Register 0"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFB4++0x03
|
|
line.long 0x00 "IEBR1,Instruction Error bank Register 1"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFB8++0x03
|
|
line.long 0x00 "DEBR0,Data Error bank Register 0"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFBC++0x03
|
|
line.long 0x00 "DEBR1,Data Error bank Register 1"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
tree.end
|
|
tree "Feature Registers"
|
|
width 10.
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
|
|
hgroup.long 0xD4C++0x03
|
|
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
|
|
bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
|
|
hgroup.long 0xD54++0x03
|
|
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x13
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
|
|
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
tree "CoreSight Identification Registers"
|
|
width 6.
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM7F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x0B
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
newline
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
|
|
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
newline
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
newline
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
newline
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
newline
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x0
|
|
tree "ADC0"
|
|
base ad:0x40012400
|
|
group.long 0x0++0x53
|
|
line.long 0x0 "STAT,Status register"
|
|
bitfld.long 0x0 31. "WDE2,Analog watchdog 2 event flag" "0,1"
|
|
bitfld.long 0x0 30. "WDE1,Analog watchdog 1 event flag" "0,1"
|
|
bitfld.long 0x0 5. "ROVF,Regular data register overflow" "0,1"
|
|
bitfld.long 0x0 4. "STRC,Start flag of regular channel group" "0,1"
|
|
bitfld.long 0x0 3. "STIC,Start flag of inserted channel group" "0,1"
|
|
bitfld.long 0x0 2. "EOIC,End of inserted group conversion flag" "0,1"
|
|
bitfld.long 0x0 1. "EOC,End of group conversion flag" "0,1"
|
|
bitfld.long 0x0 0. "WDE0,Analog watchdog0 event flag" "0,1"
|
|
line.long 0x4 "CTL0,Control register 0"
|
|
bitfld.long 0x4 31. "WDE2IE,Interrupt enable for WDE2" "0,1"
|
|
bitfld.long 0x4 30. "WDE1IE,Interrupt enable for WDE1" "0,1"
|
|
bitfld.long 0x4 26. "ROVFIE,Interrupt enable for ROVF" "0,1"
|
|
bitfld.long 0x4 24.--25. "DRES,ADC data resolution for ADC0/ADC1" "0,1,2,3"
|
|
bitfld.long 0x4 23. "RWD0EN,Regular channel analog watchdog0 enable" "0,1"
|
|
bitfld.long 0x4 22. "IWD0EN,Inserted channel analog watchdog0 enable" "0,1"
|
|
bitfld.long 0x4 13.--15. "DISNUM,Number of conversions in discontinuous mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "DISIC,Discontinuous mode on inserted channels" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DISRC,Discontinuous mode on regular channels" "0,1"
|
|
bitfld.long 0x4 10. "ICA,Inserted channel group convert automatically" "0,1"
|
|
bitfld.long 0x4 9. "WD0SC,When in scan mode analog watchdog0 is effective on a single channel" "0,1"
|
|
bitfld.long 0x4 8. "SM,Scan mode" "0,1"
|
|
bitfld.long 0x4 7. "EOICIE,Interrupt enable for EOIC" "0,1"
|
|
bitfld.long 0x4 6. "WDE0IE,Interrupt enable for WDE0" "0,1"
|
|
bitfld.long 0x4 5. "EOCIE,Interrupt enable for EOC" "0,1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "WD0CHSEL,Analog watchdog0 channel select"
|
|
line.long 0x8 "CTL1,Control register 1"
|
|
bitfld.long 0x8 30. "SWRCST,Software start on regular channel" "0,1"
|
|
bitfld.long 0x8 28.--29. "ETMRC,External trigger mode for regular channel" "0,1,2,3"
|
|
bitfld.long 0x8 27. "CALMOD,ADC calibration mode (for ADC0/1)" "0,1"
|
|
bitfld.long 0x8 22. "SWICST,Software start on inserted channel" "0,1"
|
|
bitfld.long 0x8 20.--21. "ETMIC,External trigger mode for inserted channel" "0,1,2,3"
|
|
bitfld.long 0x8 12. "HPDFCFG,HPDF mode configuration" "0,1"
|
|
bitfld.long 0x8 11. "DAL,Data alignment" "0,1"
|
|
bitfld.long 0x8 10. "EOCM,End of conversion mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DDM,DMA disable mode" "0,1"
|
|
bitfld.long 0x8 8. "DMA,DMA request enable" "0,1"
|
|
bitfld.long 0x8 4.--6. "CALNUM,Calibration Times" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "RSTCLB,Reset calibration" "0,1"
|
|
bitfld.long 0x8 2. "CLB,ADC calibration" "0,1"
|
|
bitfld.long 0x8 1. "CTN,Continuous mode" "0,1"
|
|
bitfld.long 0x8 0. "ADCON,ADC ON" "0,1"
|
|
line.long 0xC "IOFF0,Inserted channel data offset registe 0"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "IOFF,Data offset for inserted channel x For ADC0/ADC1 are IOFF[23:0] for ADC2 is IOFF[11:0]"
|
|
line.long 0x10 "IOFF1,Inserted channel data offset registe 1"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "IOFF,Data offset for inserted channel x For ADC0/ADC1 are IOFF[23:0] for ADC2 is IOFF[11:0]"
|
|
line.long 0x14 "IOFF2,Inserted channel data offset registe 2"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "IOFF,Data offset for inserted channel x For ADC0/ADC1 are IOFF[23:0] for ADC2 is IOFF[11:0]"
|
|
line.long 0x18 "IOFF3,Inserted channel data offset registe 3"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. "IOFF,Data offset for inserted channel x For ADC0/ADC1 are IOFF[23:0] for ADC2 is IOFF[11:0]"
|
|
line.long 0x1C "WDHT0,Watchdog high threshold register0"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. "WDHT0,Analog watchdog0 high threshold For ADC0/ADC1 are WDHT0[23:0] for ADC2 is WDHT0[11:0]"
|
|
line.long 0x20 "WDLT0,Watchdog low threshold register0"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. "WDLT0,Analog watchdog low threshold"
|
|
line.long 0x24 "RSQ0,Regular sequence register 0"
|
|
hexmask.long.byte 0x24 20.--23. 1. "RL,Regular channel group length"
|
|
hexmask.long.word 0x24 5.--14. 1. "RSMP15,Regular channel sample time"
|
|
hexmask.long.byte 0x24 0.--4. 1. "RSQ15,refer to RSQ0[4:0] description"
|
|
line.long 0x28 "RSQ1,Regular sequence register 1"
|
|
hexmask.long.word 0x28 21.--30. 1. "RSMP14,Regular channel sample time"
|
|
hexmask.long.byte 0x28 16.--20. 1. "RSQ14,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x28 5.--14. 1. "RSMP13,Regular channel sample time"
|
|
hexmask.long.byte 0x28 0.--4. 1. "RSQ13,refer to RSQ0[4:0] description"
|
|
line.long 0x2C "RSQ2,Regular sequence register 2"
|
|
hexmask.long.word 0x2C 21.--30. 1. "RSMP12,Regular channel sample time"
|
|
hexmask.long.byte 0x2C 16.--20. 1. "RSQ12,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x2C 5.--14. 1. "RSMP11,Regular channel sample time"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "RSQ11,refer to RSQ0[4:0] description"
|
|
line.long 0x30 "RSQ3,Regular sequence register 3"
|
|
hexmask.long.word 0x30 21.--30. 1. "RSMP10,Regular channel sample time"
|
|
hexmask.long.byte 0x30 16.--20. 1. "RSQ10,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x30 5.--14. 1. "RSMP9,Regular channel sample time"
|
|
hexmask.long.byte 0x30 0.--4. 1. "RSQ9,refer to RSQ0[4:0] description"
|
|
line.long 0x34 "RSQ4,Regular sequence register 4"
|
|
hexmask.long.word 0x34 21.--30. 1. "RSMP8,Regular channel sample time"
|
|
hexmask.long.byte 0x34 16.--20. 1. "RSQ8,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x34 5.--14. 1. "RSMP7,Regular channel sample time"
|
|
hexmask.long.byte 0x34 0.--4. 1. "RSQ7,refer to RSQ0[4:0] description"
|
|
line.long 0x38 "RSQ5,Regular sequence register 5"
|
|
hexmask.long.word 0x38 21.--30. 1. "RSMP6,Regular channel sample time"
|
|
hexmask.long.byte 0x38 16.--20. 1. "RSQ6,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x38 5.--14. 1. "RSMP5,Regular channel sample time"
|
|
hexmask.long.byte 0x38 0.--4. 1. "RSQ5,refer to RSQ0[4:0] description"
|
|
line.long 0x3C "RSQ6,Regular sequence register 6"
|
|
hexmask.long.word 0x3C 21.--30. 1. "RSMP4,Regular channel sample time"
|
|
hexmask.long.byte 0x3C 16.--20. 1. "RSQ4,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x3C 5.--14. 1. "RSMP3,Regular channel sample time"
|
|
hexmask.long.byte 0x3C 0.--4. 1. "RSQ3,refer to RSQ0[4:0] description"
|
|
line.long 0x40 "RSQ7,Regular sequence register 7"
|
|
hexmask.long.word 0x40 21.--30. 1. "RSMP2,Regular channel sample time"
|
|
hexmask.long.byte 0x40 16.--20. 1. "RSQ2,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x40 5.--14. 1. "RSMP1,Regular channel sample time"
|
|
hexmask.long.byte 0x40 0.--4. 1. "RSQ1,refer to RSQ0[4:0] description"
|
|
line.long 0x44 "RSQ8,Regular sequence register 8"
|
|
hexmask.long.word 0x44 5.--14. 1. "RSMP0,Regular channel sample time"
|
|
hexmask.long.byte 0x44 0.--4. 1. "RSQ0,The channel number (0"
|
|
line.long 0x48 "ISQ0,Inserted sequence register 0"
|
|
bitfld.long 0x48 20.--21. "IL,Inserted channel group length" "0,1,2,3"
|
|
hexmask.long.word 0x48 5.--14. 1. "ISMP3,Inserted channel sample time"
|
|
hexmask.long.byte 0x48 0.--4. 1. "ISQ3,refer to ISQ0[4:0] description"
|
|
line.long 0x4C "ISQ1,Inserted sequence register 1"
|
|
hexmask.long.word 0x4C 21.--30. 1. "ISMP2,Inserted channel sample time"
|
|
hexmask.long.byte 0x4C 16.--20. 1. "ISQ2,refer to ISQ0[4:0] description"
|
|
hexmask.long.word 0x4C 5.--14. 1. "ISMP1,Inserted channel sample time"
|
|
hexmask.long.byte 0x4C 0.--4. 1. "ISQ1,refer to ISQ0[4:0] description"
|
|
line.long 0x50 "ISQ2,Inserted sequence register 2"
|
|
hexmask.long.word 0x50 5.--14. 1. "ISMP0,Inserted channel sample time"
|
|
hexmask.long.byte 0x50 0.--4. 1. "ISQ0,The channel number (0"
|
|
rgroup.long 0x54++0x13
|
|
line.long 0x0 "IDATA0,Inserted data registe 0"
|
|
hexmask.long 0x0 0.--31. 1. "IDATAn,Inserted number n conversion data"
|
|
line.long 0x4 "IDATA1,Inserted data registe 1"
|
|
hexmask.long 0x4 0.--31. 1. "IDATAn,Inserted number n conversion data"
|
|
line.long 0x8 "IDATA2,Inserted data registe 2"
|
|
hexmask.long 0x8 0.--31. 1. "IDATAn,Inserted number n conversion data"
|
|
line.long 0xC "IDATA3,Inserted data registe 3"
|
|
hexmask.long 0xC 0.--31. 1. "IDATAn,Inserted number n conversion data"
|
|
line.long 0x10 "RDATA,Regular data register"
|
|
hexmask.long 0x10 0.--31. 1. "RDATA,Regular channel data"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "OVSCR,Oversample control register"
|
|
hexmask.long.word 0x0 16.--25. 1. "OVSR,Oversampling ratio"
|
|
bitfld.long 0x0 9. "TOVS,Triggered Oversampling" "0,1"
|
|
hexmask.long.byte 0x0 5.--8. 1. "OVSS,Oversampling shift"
|
|
bitfld.long 0x0 0. "OVSEN,Oversampler Enable" "0,1"
|
|
group.long 0xA0++0x1B
|
|
line.long 0x0 "WD1SR,Watchdog 1 Channel Selection Register"
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "AWD1CS,Analog watchdog 1 channel selection"
|
|
line.long 0x4 "WD2SR,Watchdog 2 Channel Selection Register"
|
|
hexmask.long.tbyte 0x4 0.--21. 1. "AWD2CS,Analog watchdog 2 channel selection"
|
|
line.long 0x8 "WDHT1,Watchdog high threshold register1"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "WDHT1,Analog watchdog 1 high threshold"
|
|
line.long 0xC "WDLT1,Watchdog low threshold register1"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "WDLT1,Analog watchdog 1 low threshold"
|
|
line.long 0x10 "WDHT2,Watchdog high threshold register2"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "WDHT2,Analog watchdog 2 high threshold"
|
|
line.long 0x14 "WDLT2,Watchdog low threshold register2"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "WDLT2,Analog watchdog 2 low threshold"
|
|
line.long 0x18 "DIFCTL,Differential mode control registe"
|
|
hexmask.long.tbyte 0x18 0.--21. 1. "DIFCTL,Differential mode for channel 21"
|
|
rgroup.long 0x300++0x3
|
|
line.long 0x0 "SSTAT,Summary status register"
|
|
bitfld.long 0x0 23. "ADC2_ROVF,This bit is the mirror image of the ROVF bit of ADC2" "0,1"
|
|
bitfld.long 0x0 22. "ADC2_STRC,This bit is the mirror image of the STRC bit of ADC2" "0,1"
|
|
bitfld.long 0x0 21. "ADC2_STIC,This bit is the mirror image of the STIC bit of ADC2" "0,1"
|
|
bitfld.long 0x0 18. "ADC2_WDE2,This bit is the mirror image of the WDE2 bit of ADC2" "0,1"
|
|
bitfld.long 0x0 17. "ADC2_WDE1,This bit is the mirror image of the WDE1 bit of ADC2" "0,1"
|
|
bitfld.long 0x0 16. "ADC2_WDE0,This bit is the mirror image of the WDE0 bit of ADC2" "0,1"
|
|
bitfld.long 0x0 15. "ADC1_ROVF,This bit is the mirror image of the ROVF bit of ADC1" "0,1"
|
|
bitfld.long 0x0 14. "ADC1_STRC,This bit is the mirror image of the STRC bit of ADC1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ADC1_EOC,This bit is the mirror image of the EOC bit of ADC1" "0,1"
|
|
bitfld.long 0x0 10. "ADC1_WDE2,This bit is the mirror image of the WDE2 bit of ADC1" "0,1"
|
|
bitfld.long 0x0 9. "ADC1_WDE1,This bit is the mirror image of the WDE1 bit of ADC1" "0,1"
|
|
bitfld.long 0x0 8. "ADC1_WDE0,This bit is the mirror image of the WDE0 bit of ADC1" "0,1"
|
|
bitfld.long 0x0 7. "ADC0_ROVF,This bit is the mirror image of the ROVF bit of ADC0" "0,1"
|
|
bitfld.long 0x0 6. "ADC0_STRC,This bit is the mirror image of the STRC bit of ADC0" "0,1"
|
|
bitfld.long 0x0 3. "ADC0_EOC,This bit is the mirror image of the EOC bit of ADC0" "0,1"
|
|
bitfld.long 0x0 2. "ADC0_WDE2,This bit is the mirror image of the WDE2 bit of ADC0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ADC0_WDE1,This bit is the mirror image of the WDE1 bit of ADC0" "0,1"
|
|
bitfld.long 0x0 0. "ADC0_WDE0,This bit is the mirror image of the WDE0 bit of ADC0" "0,1"
|
|
group.long 0x304++0x3
|
|
line.long 0x0 "SYNCCTL,Sync control register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "ADCCK,ADC clock prescaler"
|
|
hexmask.long.byte 0x0 16.--19. 1. "ADCSCK,ADC sync clock mode"
|
|
bitfld.long 0x0 14.--15. "SYNCDMA,ADC sync DMA mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 13. "SYNCDDM,ADC sync DMA disable mode" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SYNCDLY,ADC sync delay"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SYNCM,ADC sync mode"
|
|
rgroup.long 0x308++0x7
|
|
line.long 0x0 "SYNCDATA0,Sync regular data register0"
|
|
hexmask.long.word 0x0 16.--31. 1. "SYNCDATA1,Regular data1(slave adc regular data) in ADC sync mode"
|
|
hexmask.long.word 0x0 0.--15. 1. "SYNCDATA0,Regular data0 (master adc regular data) in ADC sync mode"
|
|
line.long 0x4 "SYNCDATA1,Sync regular data register 1"
|
|
hexmask.long 0x4 0.--31. 1. "SYNCDATA,which is selected from the regular data(master/slave) of the ADCs in turn"
|
|
tree.end
|
|
tree "ADC1"
|
|
base ad:0x40012800
|
|
group.long 0x0++0x53
|
|
line.long 0x0 "STAT,Status register"
|
|
bitfld.long 0x0 31. "WDE2,Analog watchdog 2 event flag" "0,1"
|
|
bitfld.long 0x0 30. "WDE1,Analog watchdog 1 event flag" "0,1"
|
|
bitfld.long 0x0 5. "ROVF,Regular data register overflow" "0,1"
|
|
bitfld.long 0x0 4. "STRC,Start flag of regular channel group" "0,1"
|
|
bitfld.long 0x0 3. "STIC,Start flag of inserted channel group" "0,1"
|
|
bitfld.long 0x0 2. "EOIC,End of inserted group conversion flag" "0,1"
|
|
bitfld.long 0x0 1. "EOC,End of group conversion flag" "0,1"
|
|
bitfld.long 0x0 0. "WDE0,Analog watchdog0 event flag" "0,1"
|
|
line.long 0x4 "CTL0,Control register 0"
|
|
bitfld.long 0x4 31. "WDE2IE,Interrupt enable for WDE2" "0,1"
|
|
bitfld.long 0x4 30. "WDE1IE,Interrupt enable for WDE1" "0,1"
|
|
bitfld.long 0x4 26. "ROVFIE,Interrupt enable for ROVF" "0,1"
|
|
bitfld.long 0x4 24.--25. "DRES,ADC data resolution for ADC0/ADC1" "0,1,2,3"
|
|
bitfld.long 0x4 23. "RWD0EN,Regular channel analog watchdog0 enable" "0,1"
|
|
bitfld.long 0x4 22. "IWD0EN,Inserted channel analog watchdog0 enable" "0,1"
|
|
bitfld.long 0x4 13.--15. "DISNUM,Number of conversions in discontinuous mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "DISIC,Discontinuous mode on inserted channels" "0,1"
|
|
bitfld.long 0x4 11. "DISRC,Discontinuous mode on regular channels" "0,1"
|
|
bitfld.long 0x4 10. "ICA,Inserted channel group convert automatically" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "WD0SC,When in scan mode analog watchdog0 is effective on a single channel" "0,1"
|
|
bitfld.long 0x4 8. "SM,Scan mode" "0,1"
|
|
bitfld.long 0x4 7. "EOICIE,Interrupt enable for EOIC" "0,1"
|
|
bitfld.long 0x4 6. "WDE0IE,Interrupt enable for WDE0" "0,1"
|
|
bitfld.long 0x4 5. "EOCIE,Interrupt enable for EOC" "0,1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "WD0CHSEL,Analog watchdog0 channel select"
|
|
line.long 0x8 "CTL1,Control register 1"
|
|
bitfld.long 0x8 30. "SWRCST,Software start on regular channel" "0,1"
|
|
bitfld.long 0x8 28.--29. "ETMRC,External trigger mode for regular channel" "0,1,2,3"
|
|
bitfld.long 0x8 27. "CALMOD,ADC calibration mode (for ADC0/1)" "0,1"
|
|
bitfld.long 0x8 25. "VBATEN,This bit can be set or cleared by software in ADC2" "0,1"
|
|
bitfld.long 0x8 24. "INREFEN,This bit can be set or cleared by software in ADC2" "0,1"
|
|
bitfld.long 0x8 22. "SWICST,Software start on inserted channel" "0,1"
|
|
bitfld.long 0x8 20.--21. "ETMIC,External trigger mode for inserted channel" "0,1,2,3"
|
|
bitfld.long 0x8 12. "HPDFCFG,HPDF mode configuration" "0,1"
|
|
bitfld.long 0x8 11. "DAL,Data alignment" "0,1"
|
|
bitfld.long 0x8 10. "EOCM,End of conversion mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DDM,DMA disable mode" "0,1"
|
|
bitfld.long 0x8 8. "DMA,DMA request enable" "0,1"
|
|
bitfld.long 0x8 4.--6. "CALNUM,Calibration Times" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "RSTCLB,Reset calibration" "0,1"
|
|
bitfld.long 0x8 2. "CLB,ADC calibration" "0,1"
|
|
bitfld.long 0x8 1. "CTN,Continuous mode" "0,1"
|
|
bitfld.long 0x8 0. "ADCON,ADC ON" "0,1"
|
|
line.long 0xC "IOFF0,Inserted channel data offset registe 0"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "IOFF,Data offset for inserted channel x For ADC0/ADC1 are IOFF[23:0] for ADC2 is IOFF[11:0]"
|
|
line.long 0x10 "IOFF1,Inserted channel data offset registe 1"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "IOFF,Data offset for inserted channel x For ADC0/ADC1 are IOFF[23:0] for ADC2 is IOFF[11:0]"
|
|
line.long 0x14 "IOFF2,Inserted channel data offset registe 2"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "IOFF,Data offset for inserted channel x For ADC0/ADC1 are IOFF[23:0] for ADC2 is IOFF[11:0]"
|
|
line.long 0x18 "IOFF3,Inserted channel data offset registe 3"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. "IOFF,Data offset for inserted channel x For ADC0/ADC1 are IOFF[23:0] for ADC2 is IOFF[11:0]"
|
|
line.long 0x1C "WDHT0,Watchdog high threshold register0"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. "WDHT0,Analog watchdog0 high threshold For ADC0/ADC1 are WDHT0[23:0] for ADC2 is WDHT0[11:0]"
|
|
line.long 0x20 "WDLT0,Watchdog low threshold register0"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. "WDLT0,Analog watchdog low threshold"
|
|
line.long 0x24 "RSQ0,Regular sequence register 0"
|
|
hexmask.long.byte 0x24 20.--23. 1. "RL,Regular channel group length"
|
|
hexmask.long.word 0x24 5.--14. 1. "RSMP15,Regular channel sample time"
|
|
hexmask.long.byte 0x24 0.--4. 1. "RSQ15,refer to RSQ0[4:0] description"
|
|
line.long 0x28 "RSQ1,Regular sequence register 1"
|
|
hexmask.long.word 0x28 21.--30. 1. "RSMP14,Regular channel sample time"
|
|
hexmask.long.byte 0x28 16.--20. 1. "RSQ14,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x28 5.--14. 1. "RSMP13,Regular channel sample time"
|
|
hexmask.long.byte 0x28 0.--4. 1. "RSQ13,refer to RSQ0[4:0] description"
|
|
line.long 0x2C "RSQ2,Regular sequence register 2"
|
|
hexmask.long.word 0x2C 21.--30. 1. "RSMP12,Regular channel sample time"
|
|
hexmask.long.byte 0x2C 16.--20. 1. "RSQ12,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x2C 5.--14. 1. "RSMP11,Regular channel sample time"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "RSQ11,refer to RSQ0[4:0] description"
|
|
line.long 0x30 "RSQ3,Regular sequence register 3"
|
|
hexmask.long.word 0x30 21.--30. 1. "RSMP10,Regular channel sample time"
|
|
hexmask.long.byte 0x30 16.--20. 1. "RSQ10,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x30 5.--14. 1. "RSMP9,Regular channel sample time"
|
|
hexmask.long.byte 0x30 0.--4. 1. "RSQ9,refer to RSQ0[4:0] description"
|
|
line.long 0x34 "RSQ4,Regular sequence register 4"
|
|
hexmask.long.word 0x34 21.--30. 1. "RSMP8,Regular channel sample time"
|
|
hexmask.long.byte 0x34 16.--20. 1. "RSQ8,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x34 5.--14. 1. "RSMP7,Regular channel sample time"
|
|
hexmask.long.byte 0x34 0.--4. 1. "RSQ7,refer to RSQ0[4:0] description"
|
|
line.long 0x38 "RSQ5,Regular sequence register 5"
|
|
hexmask.long.word 0x38 21.--30. 1. "RSMP6,Regular channel sample time"
|
|
hexmask.long.byte 0x38 16.--20. 1. "RSQ6,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x38 5.--14. 1. "RSMP5,Regular channel sample time"
|
|
hexmask.long.byte 0x38 0.--4. 1. "RSQ5,refer to RSQ0[4:0] description"
|
|
line.long 0x3C "RSQ6,Regular sequence register 6"
|
|
hexmask.long.word 0x3C 21.--30. 1. "RSMP4,Regular channel sample time"
|
|
hexmask.long.byte 0x3C 16.--20. 1. "RSQ4,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x3C 5.--14. 1. "RSMP3,Regular channel sample time"
|
|
hexmask.long.byte 0x3C 0.--4. 1. "RSQ3,refer to RSQ0[4:0] description"
|
|
line.long 0x40 "RSQ7,Regular sequence register 7"
|
|
hexmask.long.word 0x40 21.--30. 1. "RSMP2,Regular channel sample time"
|
|
hexmask.long.byte 0x40 16.--20. 1. "RSQ2,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x40 5.--14. 1. "RSMP1,Regular channel sample time"
|
|
hexmask.long.byte 0x40 0.--4. 1. "RSQ1,refer to RSQ0[4:0] description"
|
|
line.long 0x44 "RSQ8,Regular sequence register 8"
|
|
hexmask.long.word 0x44 5.--14. 1. "RSMP0,Regular channel sample time"
|
|
hexmask.long.byte 0x44 0.--4. 1. "RSQ0,The channel number (0"
|
|
line.long 0x48 "ISQ0,Inserted sequence register 0"
|
|
bitfld.long 0x48 20.--21. "IL,Inserted channel group length" "0,1,2,3"
|
|
hexmask.long.word 0x48 5.--14. 1. "ISMP3,Inserted channel sample time"
|
|
hexmask.long.byte 0x48 0.--4. 1. "ISQ3,refer to ISQ0[4:0] description"
|
|
line.long 0x4C "ISQ1,Inserted sequence register 1"
|
|
hexmask.long.word 0x4C 21.--30. 1. "ISMP2,Inserted channel sample time"
|
|
hexmask.long.byte 0x4C 16.--20. 1. "ISQ2,refer to ISQ0[4:0] description"
|
|
hexmask.long.word 0x4C 5.--14. 1. "ISMP1,Inserted channel sample time"
|
|
hexmask.long.byte 0x4C 0.--4. 1. "ISQ1,refer to ISQ0[4:0] description"
|
|
line.long 0x50 "ISQ2,Inserted sequence register 2"
|
|
hexmask.long.word 0x50 5.--14. 1. "ISMP0,Inserted channel sample time"
|
|
hexmask.long.byte 0x50 0.--4. 1. "ISQ0,The channel number (0"
|
|
rgroup.long 0x54++0x13
|
|
line.long 0x0 "IDATA0,Inserted data registe 0"
|
|
hexmask.long 0x0 0.--31. 1. "IDATAn,Inserted number n conversion data"
|
|
line.long 0x4 "IDATA1,Inserted data registe 1"
|
|
hexmask.long 0x4 0.--31. 1. "IDATAn,Inserted number n conversion data"
|
|
line.long 0x8 "IDATA2,Inserted data registe 2"
|
|
hexmask.long 0x8 0.--31. 1. "IDATAn,Inserted number n conversion data"
|
|
line.long 0xC "IDATA3,Inserted data registe 3"
|
|
hexmask.long 0xC 0.--31. 1. "IDATAn,Inserted number n conversion data"
|
|
line.long 0x10 "RDATA,Regular data register"
|
|
hexmask.long 0x10 0.--31. 1. "RDATA,Regular channel data"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "OVSCR,Oversample control register"
|
|
hexmask.long.word 0x0 16.--25. 1. "OVSR,Oversampling ratio"
|
|
bitfld.long 0x0 9. "TOVS,Triggered Oversampling" "0,1"
|
|
hexmask.long.byte 0x0 5.--8. 1. "OVSS,Oversampling shift"
|
|
bitfld.long 0x0 0. "OVSEN,Oversampler Enable" "0,1"
|
|
group.long 0xA0++0x1B
|
|
line.long 0x0 "WD1SR,Watchdog 1 Channel Selection Register"
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "AWD1CS,Analog watchdog 1 channel selection"
|
|
line.long 0x4 "WD2SR,Watchdog 2 Channel Selection Register"
|
|
hexmask.long.tbyte 0x4 0.--21. 1. "AWD2CS,Analog watchdog 2 channel selection"
|
|
line.long 0x8 "WDHT1,Watchdog high threshold register1"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "WDHT1,Analog watchdog 1 high threshold"
|
|
line.long 0xC "WDLT1,Watchdog low threshold register1"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "WDLT1,Analog watchdog 1 low threshold"
|
|
line.long 0x10 "WDHT2,Watchdog high threshold register2"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "WDHT2,Analog watchdog 2 high threshold"
|
|
line.long 0x14 "WDLT2,Watchdog low threshold register2"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "WDLT2,Analog watchdog 2 low threshold"
|
|
line.long 0x18 "DIFCTL,Differential mode control registe"
|
|
hexmask.long.tbyte 0x18 0.--21. 1. "DIFCTL,Differential mode for channel 21"
|
|
tree.end
|
|
tree "ADC2"
|
|
base ad:0x40012C00
|
|
group.long 0x0++0x53
|
|
line.long 0x0 "STAT,Status register"
|
|
bitfld.long 0x0 31. "WDE2,Analog watchdog 2 event flag" "0,1"
|
|
bitfld.long 0x0 30. "WDE1,Analog watchdog 1 event flag" "0,1"
|
|
bitfld.long 0x0 5. "ROVF,Regular data register overflow" "0,1"
|
|
bitfld.long 0x0 4. "STRC,Start flag of regular channel group" "0,1"
|
|
bitfld.long 0x0 3. "STIC,Start flag of inserted channel group" "0,1"
|
|
bitfld.long 0x0 2. "EOIC,End of inserted group conversion flag" "0,1"
|
|
bitfld.long 0x0 1. "EOC,End of group conversion flag" "0,1"
|
|
bitfld.long 0x0 0. "WDE0,Analog watchdog0 event flag" "0,1"
|
|
line.long 0x4 "CTL0,Control register 0"
|
|
bitfld.long 0x4 31. "WDE2IE,Interrupt enable for WDE2" "0,1"
|
|
bitfld.long 0x4 30. "WDE1IE,Interrupt enable for WDE1" "0,1"
|
|
bitfld.long 0x4 26. "ROVFIE,Interrupt enable for ROVF" "0,1"
|
|
bitfld.long 0x4 24.--25. "DRES,ADC data resolution for ADC0/ADC1" "0,1,2,3"
|
|
bitfld.long 0x4 23. "RWD0EN,Regular channel analog watchdog0 enable" "0,1"
|
|
bitfld.long 0x4 22. "IWD0EN,Inserted channel analog watchdog0 enable" "0,1"
|
|
bitfld.long 0x4 13.--15. "DISNUM,Number of conversions in discontinuous mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "DISIC,Discontinuous mode on inserted channels" "0,1"
|
|
bitfld.long 0x4 11. "DISRC,Discontinuous mode on regular channels" "0,1"
|
|
bitfld.long 0x4 10. "ICA,Inserted channel group convert automatically" "0,1"
|
|
bitfld.long 0x4 9. "WD0SC,When in scan mode analog watchdog0 is effective on a single channel" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SM,Scan mode" "0,1"
|
|
bitfld.long 0x4 7. "EOICIE,Interrupt enable for EOIC" "0,1"
|
|
bitfld.long 0x4 6. "WDE0IE,Interrupt enable for WDE0" "0,1"
|
|
bitfld.long 0x4 5. "EOCIE,Interrupt enable for EOC" "0,1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "WD0CHSEL,Analog watchdog0 channel select"
|
|
line.long 0x8 "CTL1,Control register 1"
|
|
bitfld.long 0x8 31. "TSVEN2,Channel_20 high-precision temperature sensor enable of ADC2" "0,1"
|
|
bitfld.long 0x8 30. "SWRCST,Software start on regular channel" "0,1"
|
|
bitfld.long 0x8 28.--29. "ETMRC,External trigger mode for regular channel" "0,1,2,3"
|
|
bitfld.long 0x8 25. "VBATEN,Channel_17 enable of ADC2" "0,1"
|
|
bitfld.long 0x8 24. "INREFEN,Channel_19 enable of ADC2" "0,1"
|
|
bitfld.long 0x8 23. "TSVEN1,Channel_18 enable of ADC2" "0,1"
|
|
bitfld.long 0x8 22. "SWICST,Software start on inserted channel" "0,1"
|
|
bitfld.long 0x8 20.--21. "ETMIC,External trigger mode for inserted channel" "0,1,2,3"
|
|
bitfld.long 0x8 12. "HPDFCFG,HPDF mode configuration" "0,1"
|
|
bitfld.long 0x8 11. "DAL,Data alignment" "0,1"
|
|
bitfld.long 0x8 10. "EOCM,End of conversion mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DDM,DMA disable mode" "0,1"
|
|
bitfld.long 0x8 8. "DMA,DMA request enable" "0,1"
|
|
bitfld.long 0x8 4.--6. "CALNUM,Calibration Times" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "RSTCLB,Reset calibration" "0,1"
|
|
bitfld.long 0x8 2. "CLB,ADC calibration" "0,1"
|
|
bitfld.long 0x8 1. "CTN,Continuous mode" "0,1"
|
|
bitfld.long 0x8 0. "ADCON,ADC ON" "0,1"
|
|
line.long 0xC "IOFF0,Inserted channel data offset registe 0"
|
|
hexmask.long.word 0xC 0.--11. 1. "IOFF,Data offset for inserted channel x For ADC0/ADC1 are IOFF[23:0] for ADC2 is IOFF[11:0]"
|
|
line.long 0x10 "IOFF1,Inserted channel data offset registe 1"
|
|
hexmask.long.word 0x10 0.--11. 1. "IOFF,Data offset for inserted channel x For ADC0/ADC1 are IOFF[23:0] for ADC2 is IOFF[11:0]"
|
|
line.long 0x14 "IOFF2,Inserted channel data offset registe 2"
|
|
hexmask.long.word 0x14 0.--11. 1. "IOFF,Data offset for inserted channel x For ADC0/ADC1 are IOFF[23:0] for ADC2 is IOFF[11:0]"
|
|
line.long 0x18 "IOFF3,Inserted channel data offset registe 3"
|
|
hexmask.long.word 0x18 0.--11. 1. "IOFF,Data offset for inserted channel x For ADC0/ADC1 are IOFF[23:0] for ADC2 is IOFF[11:0]"
|
|
line.long 0x1C "WDHT0,Watchdog high threshold register0"
|
|
hexmask.long.word 0x1C 0.--11. 1. "WDHT0,Analog watchdog0 high threshold For ADC0/ADC1 are WDHT0[23:0] for ADC2 is WDHT0[11:0]"
|
|
line.long 0x20 "WDLT0,Watchdog low threshold register0"
|
|
hexmask.long.word 0x20 0.--11. 1. "WDLT0,Analog watchdog low threshold"
|
|
line.long 0x24 "RSQ0,Regular sequence register 0"
|
|
hexmask.long.byte 0x24 20.--23. 1. "RL,Regular channel group length"
|
|
hexmask.long.word 0x24 5.--14. 1. "RSMP15,Regular channel sample time"
|
|
hexmask.long.byte 0x24 0.--4. 1. "RSQ15,refer to RSQ0[4:0] description"
|
|
line.long 0x28 "RSQ1,Regular sequence register 1"
|
|
hexmask.long.word 0x28 21.--30. 1. "RSMP14,Regular channel sample time"
|
|
hexmask.long.byte 0x28 16.--20. 1. "RSQ14,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x28 5.--14. 1. "RSMP13,Regular channel sample time"
|
|
hexmask.long.byte 0x28 0.--4. 1. "RSQ13,refer to RSQ0[4:0] description"
|
|
line.long 0x2C "RSQ2,Regular sequence register 2"
|
|
hexmask.long.word 0x2C 21.--30. 1. "RSMP12,Regular channel sample time"
|
|
hexmask.long.byte 0x2C 16.--20. 1. "RSQ12,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x2C 5.--14. 1. "RSMP11,Regular channel sample time"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "RSQ11,refer to RSQ0[4:0] description"
|
|
line.long 0x30 "RSQ3,Regular sequence register 3"
|
|
hexmask.long.word 0x30 21.--30. 1. "RSMP10,Regular channel sample time"
|
|
hexmask.long.byte 0x30 16.--20. 1. "RSQ10,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x30 5.--14. 1. "RSMP9,Regular channel sample time"
|
|
hexmask.long.byte 0x30 0.--4. 1. "RSQ9,refer to RSQ0[4:0] description"
|
|
line.long 0x34 "RSQ4,Regular sequence register 4"
|
|
hexmask.long.word 0x34 21.--30. 1. "RSMP8,Regular channel sample time"
|
|
hexmask.long.byte 0x34 16.--20. 1. "RSQ8,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x34 5.--14. 1. "RSMP7,Regular channel sample time"
|
|
hexmask.long.byte 0x34 0.--4. 1. "RSQ7,refer to RSQ0[4:0] description"
|
|
line.long 0x38 "RSQ5,Regular sequence register 5"
|
|
hexmask.long.word 0x38 21.--30. 1. "RSMP6,Regular channel sample time"
|
|
hexmask.long.byte 0x38 16.--20. 1. "RSQ6,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x38 5.--14. 1. "RSMP5,Regular channel sample time"
|
|
hexmask.long.byte 0x38 0.--4. 1. "RSQ5,refer to RSQ0[4:0] description"
|
|
line.long 0x3C "RSQ6,Regular sequence register 6"
|
|
hexmask.long.word 0x3C 21.--30. 1. "RSMP4,Regular channel sample time"
|
|
hexmask.long.byte 0x3C 16.--20. 1. "RSQ4,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x3C 5.--14. 1. "RSMP3,Regular channel sample time"
|
|
hexmask.long.byte 0x3C 0.--4. 1. "RSQ3,refer to RSQ0[4:0] description"
|
|
line.long 0x40 "RSQ7,Regular sequence register 7"
|
|
hexmask.long.word 0x40 21.--30. 1. "RSMP2,Regular channel sample time"
|
|
hexmask.long.byte 0x40 16.--20. 1. "RSQ2,refer to RSQ0[4:0] description"
|
|
hexmask.long.word 0x40 5.--14. 1. "RSMP1,Regular channel sample time"
|
|
hexmask.long.byte 0x40 0.--4. 1. "RSQ1,refer to RSQ0[4:0] description"
|
|
line.long 0x44 "RSQ8,Regular sequence register 8"
|
|
hexmask.long.word 0x44 5.--14. 1. "RSMP0,Regular channel sample time"
|
|
hexmask.long.byte 0x44 0.--4. 1. "RSQ0,The channel number (0"
|
|
line.long 0x48 "ISQ0,Inserted sequence register 0"
|
|
bitfld.long 0x48 20.--21. "IL,Inserted channel group length" "0,1,2,3"
|
|
hexmask.long.word 0x48 5.--14. 1. "ISMP3,Inserted channel sample time"
|
|
hexmask.long.byte 0x48 0.--4. 1. "ISQ3,refer to ISQ0[4:0] description"
|
|
line.long 0x4C "ISQ1,Inserted sequence register 1"
|
|
hexmask.long.word 0x4C 21.--30. 1. "ISMP2,Inserted channel sample time"
|
|
hexmask.long.byte 0x4C 16.--20. 1. "ISQ2,refer to ISQ0[4:0] description"
|
|
hexmask.long.word 0x4C 5.--14. 1. "ISMP1,Inserted channel sample time"
|
|
hexmask.long.byte 0x4C 0.--4. 1. "ISQ1,refer to ISQ0[4:0] description"
|
|
line.long 0x50 "ISQ2,Inserted sequence register 2"
|
|
hexmask.long.word 0x50 5.--14. 1. "ISMP0,Inserted channel sample time"
|
|
hexmask.long.byte 0x50 0.--4. 1. "ISQ0,The channel number (0"
|
|
rgroup.long 0x54++0x13
|
|
line.long 0x0 "IDATA0,Inserted data registe 0"
|
|
hexmask.long.word 0x0 0.--15. 1. "IDATAn,Inserted number n conversion data"
|
|
line.long 0x4 "IDATA1,Inserted data registe 1"
|
|
hexmask.long.word 0x4 0.--15. 1. "IDATAn,Inserted number n conversion data"
|
|
line.long 0x8 "IDATA2,Inserted data registe 2"
|
|
hexmask.long.word 0x8 0.--15. 1. "IDATAn,Inserted number n conversion data"
|
|
line.long 0xC "IDATA3,Inserted data registe 3"
|
|
hexmask.long.word 0xC 0.--15. 1. "IDATAn,Inserted number n conversion data"
|
|
line.long 0x10 "RDATA,Regular data register"
|
|
hexmask.long.word 0x10 0.--15. 1. "RDATA,Regular channel data"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "OVSCR,Oversample control register"
|
|
hexmask.long.word 0x0 16.--25. 1. "OVSR,Oversampling ratio"
|
|
bitfld.long 0x0 9. "TOVS,Triggered Oversampling" "0,1"
|
|
hexmask.long.byte 0x0 5.--8. 1. "OVSS,Oversampling shift"
|
|
bitfld.long 0x0 0. "OVSEN,Oversampler Enable" "0,1"
|
|
group.long 0xA0++0x1B
|
|
line.long 0x0 "WD1SR,Watchdog 1 Channel Selection Register"
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "AWD1CS,Analog watchdog 1 channel selection"
|
|
line.long 0x4 "WD2SR,Watchdog 2 Channel Selection Register"
|
|
hexmask.long.tbyte 0x4 0.--21. 1. "AWD2CS,Analog watchdog 2 channel selection"
|
|
line.long 0x8 "WDHT1,Watchdog high threshold register1"
|
|
hexmask.long.word 0x8 0.--11. 1. "WDHT1,Analog watchdog 1 high threshold"
|
|
line.long 0xC "WDLT1,Watchdog low threshold register1"
|
|
hexmask.long.word 0xC 0.--11. 1. "WDLT1,Analog watchdog 1 low threshold"
|
|
line.long 0x10 "WDHT2,Watchdog high threshold register2"
|
|
hexmask.long.word 0x10 0.--11. 1. "WDHT2,Analog watchdog 2 high threshold"
|
|
line.long 0x14 "WDLT2,Watchdog low threshold register2"
|
|
hexmask.long.word 0x14 0.--11. 1. "WDLT2,Analog watchdog 2 low threshold"
|
|
line.long 0x18 "DIFCTL,Differential mode control registe"
|
|
hexmask.long.tbyte 0x18 0.--21. 1. "DIFCTL,Differential mode for channel 21"
|
|
group.long 0x304++0x3
|
|
line.long 0x0 "SYNCCTL,Sync control register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "ADCCK,ADC clock prescaler"
|
|
hexmask.long.byte 0x0 16.--19. 1. "ADCSCK,ADC sync clock mode"
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
tree "AXI (AXI Interconnect)"
|
|
base ad:0x51000000
|
|
rgroup.long 0x1FD0++0x3
|
|
line.long 0x0 "PERIPH_ID4,AXI peripheral ID4 register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CNT4KB,4KB count"
|
|
hexmask.long.byte 0x0 0.--3. 1. "JEP106CCODE,JEP106 continuation code"
|
|
rgroup.long 0x1FE0++0x1F
|
|
line.long 0x0 "PERIPH_ID0,AXI peripheral ID0 register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PARTNUM,Part number[7:0]"
|
|
line.long 0x4 "PERIPH_ID1,AXI peripheral ID1 register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "JEP106ID,JEP106 Identity[3:0]"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PARTNUM,Part number[11:8]"
|
|
line.long 0x8 "PERIPH_ID2,AXI peripheral ID2 register"
|
|
hexmask.long.byte 0x8 4.--7. 1. "PARTREV,Part revision"
|
|
bitfld.long 0x8 3. "JEP106CF,JEP106 code flag" "0,1"
|
|
bitfld.long 0x8 0.--2. "JEP106ID,Part number[11:8]" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "PERIPH_ID3,AXI peripheral ID3 register"
|
|
hexmask.long.byte 0xC 4.--7. 1. "CUSTREV,Customer version"
|
|
hexmask.long.byte 0xC 0.--3. 1. "CUSTMOD,Customer modification"
|
|
line.long 0x10 "COMP_ID0,AXI componet ID0 register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PREAMB,Preamble bits"
|
|
line.long 0x14 "COMP_ID1,AXI componet ID1 register"
|
|
hexmask.long.byte 0x14 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x14 0.--3. 1. "PARTNUM,Preamble bits"
|
|
line.long 0x18 "COMP_ID2,AXI componet ID2 register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "PREAMB,Preamble bits"
|
|
line.long 0x1C "COMP_ID3,AXI componet ID3 register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PREAMB,Preamble bits"
|
|
group.long 0x2008++0x3
|
|
line.long 0x0 "MP0BM_ISS_CTL,AXI Master Port 0 bus matrix issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override target write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override target read issuing function" "0,1"
|
|
group.long 0x3008++0x3
|
|
line.long 0x0 "MP1BM_ISS_CTL,AXI Master Port 1 bus matrix issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override target write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override target read issuing function" "0,1"
|
|
group.long 0x4008++0x3
|
|
line.long 0x0 "MP2BM_ISS_CTL,AXI Master Port 2 bus matrix issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override target write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override target read issuing function" "0,1"
|
|
group.long 0x5008++0x3
|
|
line.long 0x0 "MP3BM_ISS_CTL,AXI Master Port 3 bus matrix issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override target write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override target read issuing function" "0,1"
|
|
group.long 0x6008++0x3
|
|
line.long 0x0 "MP4BM_ISS_CTL,AXI Master Port 4 bus matrix issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override target write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override target read issuing function" "0,1"
|
|
group.long 0x7008++0x3
|
|
line.long 0x0 "MP5BM_ISS_CTL,AXI Master Port 5 bus matrix issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override target write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override target read issuing function" "0,1"
|
|
group.long 0x8008++0x3
|
|
line.long 0x0 "MP6BM_ISS_CTL,AXI Master Port 6 bus matrix issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override target write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override target read issuing function" "0,1"
|
|
group.long 0x9008++0x3
|
|
line.long 0x0 "MP7BM_ISS_CTL,AXI Master Port 7 bus matrix issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override target write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override target read issuing function" "0,1"
|
|
group.long 0x2024++0x3
|
|
line.long 0x0 "MP0BM_CTL,AXI Master Port 0 bus matrix functionality control regist"
|
|
bitfld.long 0x0 0. "BPDIS,Beats packing function disable configure" "0,1"
|
|
group.long 0x3024++0x3
|
|
line.long 0x0 "MP1BM_CTL,AXI Master Port 1 bus matrix functionality control regist"
|
|
bitfld.long 0x0 0. "BPDIS,Beats packing function disable configure" "0,1"
|
|
group.long 0x8024++0x3
|
|
line.long 0x0 "MP6BM_CTL,AXI Master Port 6 bus matrix functionality control regist"
|
|
bitfld.long 0x0 0. "BPDIS,Beats packing function disable configure" "0,1"
|
|
group.long 0x9024++0x3
|
|
line.long 0x0 "MP7BM_CTL,AXI Master Port 7 bus matrix functionality control regist"
|
|
bitfld.long 0x0 0. "BPDIS,Beats packing function disable configure" "0,1"
|
|
group.long 0x202C++0x3
|
|
line.long 0x0 "MP0_LB_CTL,AXI Master Port 0 long burst functionality control regist"
|
|
bitfld.long 0x0 0. "LBEN,Control long burst function" "0,1"
|
|
group.long 0x302C++0x3
|
|
line.long 0x0 "MP1_LB_CTL,AXI Master Port 1 long burst functionality control regist"
|
|
bitfld.long 0x0 0. "LBEN,Control long burst function" "0,1"
|
|
group.long 0x2108++0x3
|
|
line.long 0x0 "MP0_ISS_CTL,AXI Master Port 0 issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override AMIB write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override AMIB read issuing function" "0,1"
|
|
group.long 0x3108++0x3
|
|
line.long 0x0 "MP1_ISS_CTL,AXI Master Port 1 issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override AMIB write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override AMIB read issuing function" "0,1"
|
|
group.long 0x8108++0x3
|
|
line.long 0x0 "MP6_ISS_CTL,AXI Master Port 6 issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override AMIB write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override AMIB read issuing function" "0,1"
|
|
group.long 0x9108++0x3
|
|
line.long 0x0 "MP7_ISS_CTL,AXI Master Port 7 issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override AMIB write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override AMIB read issuing function" "0,1"
|
|
group.long 0x42024++0x3
|
|
line.long 0x0 "SP0_CTL,AXI Slave Port 0 functionality control regist"
|
|
bitfld.long 0x0 0. "TRANSALT,Transaction alteration configure" "0,1"
|
|
group.long 0x43024++0x3
|
|
line.long 0x0 "SP1_CTL,AXI Slave Port 1 functionality control regist"
|
|
bitfld.long 0x0 0. "TRANSALT,Transaction alteration configure" "0,1"
|
|
group.long 0x44024++0x3
|
|
line.long 0x0 "SP2_CTL,AXI Slave Port 2 functionality control regist"
|
|
bitfld.long 0x0 0. "TRANSALT,Transaction alteration configure" "0,1"
|
|
group.long 0x42028++0x3
|
|
line.long 0x0 "SP0_AHBISS_CTL,AXI Slave Port 0 AHB issuing functionality control regist"
|
|
bitfld.long 0x0 1. "RD_AHB_ISSOV,Converts AHB-Lite read transaction to single beat AXI transaction" "0,1"
|
|
bitfld.long 0x0 0. "WR_AHB_ISSOV,Converts AHB-Lite write transaction to single beat AXI transaction" "0,1"
|
|
group.long 0x43028++0x3
|
|
line.long 0x0 "SP1_AHBISS_CTL,AXI Slave Port 1 AHB issuing functionality control regist"
|
|
bitfld.long 0x0 1. "RD_AHB_ISSOV,Converts AHB-Lite read transaction to single beat AXI transaction" "0,1"
|
|
bitfld.long 0x0 0. "WR_AHB_ISSOV,Converts AHB-Lite write transaction to single beat AXI transaction" "0,1"
|
|
group.long 0x44028++0x3
|
|
line.long 0x0 "SP2_AHBISS_CTL,AXI Slave Port 2 AHB issuing functionality control regist"
|
|
bitfld.long 0x0 1. "RD_AHB_ISSOV,Converts AHB-Lite read transaction to single beat AXI transaction" "0,1"
|
|
bitfld.long 0x0 0. "WR_AHB_ISSOV,Converts AHB-Lite write transaction to single beat AXI transaction" "0,1"
|
|
group.long 0x42100++0x3
|
|
line.long 0x0 "SP0_RDQOS_CTL,AXI Slave Port 0 read QOS control regist"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RDQOS,Read channel QoS configure"
|
|
group.long 0x43100++0x3
|
|
line.long 0x0 "SP1_RDQOS_CTL,AXI Slave Port 1 read QOS control regist"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RDQOS,Read channel QoS configure"
|
|
group.long 0x44100++0x3
|
|
line.long 0x0 "SP2_RDQOS_CTL,AXI Slave Port 2 read QOS control regist"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RDQOS,Read channel QoS configure"
|
|
group.long 0x45100++0x3
|
|
line.long 0x0 "SP3_RDQOS_CTL,AXI Slave Port 3 read QOS control regist"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RDQOS,Read channel QoS configure"
|
|
group.long 0x46100++0x3
|
|
line.long 0x0 "SP4_RDQOS_CTL,AXI Slave Port 4 read QOS control regist"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RDQOS,Read channel QoS configure"
|
|
group.long 0x47100++0x3
|
|
line.long 0x0 "SP5_RDQOS_CTL,AXI Slave Port 5 read QOS control regist"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RDQOS,Read channel QoS configure"
|
|
group.long 0x42104++0x3
|
|
line.long 0x0 "SP0_WRQOS_CTL,AXI Slave Port 0 write QOS control regist"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WRQOS,Write channel QoS configure"
|
|
group.long 0x43104++0x3
|
|
line.long 0x0 "SP1_WRQOS_CTL,AXI Slave Port 1 write QOS control regist"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WRQOS,Write channel QoS configure"
|
|
group.long 0x44104++0x3
|
|
line.long 0x0 "SP2_WRQOS_CTL,AXI Slave Port 2 write QOS control regist"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WRQOS,Write channel QoS configure"
|
|
group.long 0x45104++0x3
|
|
line.long 0x0 "SP3_WRQOS_CTL,AXI Slave Port 3 write QOS control regist"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WRQOS,Write channel QoS configure"
|
|
group.long 0x46104++0x3
|
|
line.long 0x0 "SP4_WRQOS_CTL,AXI Slave Port 4 write QOS control regist"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WRQOS,Write channel QoS configure"
|
|
group.long 0x47104++0x3
|
|
line.long 0x0 "SP5_WRQOS_CTL,AXI Slave Port 5 write QOS control regist"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WRQOS,Write channel QoS configure"
|
|
group.long 0x42108++0x3
|
|
line.long 0x0 "SP0_ISS_CTL,AXI Slave Port 0 issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override ASIB write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override ASIB read issuing function" "0,1"
|
|
group.long 0x43108++0x3
|
|
line.long 0x0 "SP1_ISS_CTL,AXI Slave Port 1 issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override ASIB write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override ASIB read issuing function" "0,1"
|
|
group.long 0x44108++0x3
|
|
line.long 0x0 "SP2_ISS_CTL,AXI Slave Port 2 issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override ASIB write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override ASIB read issuing function" "0,1"
|
|
group.long 0x45108++0x3
|
|
line.long 0x0 "SP3_ISS_CTL,AXI Slave Port 3 issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override ASIB write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override ASIB read issuing function" "0,1"
|
|
group.long 0x46108++0x3
|
|
line.long 0x0 "SP4_ISS_CTL,AXI Slave Port 4 issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override ASIB write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override ASIB read issuing function" "0,1"
|
|
group.long 0x47108++0x3
|
|
line.long 0x0 "SP5_ISS_CTL,AXI Slave Port 5 issuing functionality control regist"
|
|
bitfld.long 0x0 1. "WR_ISSOV,Override ASIB write issuing function" "0,1"
|
|
bitfld.long 0x0 0. "RD_ISSOV,Override ASIB read issuing function" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "CAN (Controller Area Network)"
|
|
base ad:0x0
|
|
tree "CAN0"
|
|
base ad:0x4001A000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 31. "CANDIS,CAN disable" "0,1"
|
|
bitfld.long 0x0 30. "INAMOD,Inactive mode enable" "0,1"
|
|
bitfld.long 0x0 29. "RFEN,Rx FIFO enable" "0,1"
|
|
bitfld.long 0x0 28. "HALT,Halt CAN" "0,1"
|
|
rbitfld.long 0x0 27. "NRDY,Not ready" "0,1"
|
|
bitfld.long 0x0 25. "SWRST,Software reset" "0,1"
|
|
bitfld.long 0x0 24. "INAS,Inactive mode state" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SLPS,This bit is only valid when CAN_sleep mode is enabled" "0,1"
|
|
bitfld.long 0x0 21. "WERREN,Error warning enable" "0,1"
|
|
rbitfld.long 0x0 20. "LPS,Low power state" "0,1"
|
|
bitfld.long 0x0 19. "PNEN,Pretended Networking mode enable" "0,1"
|
|
rbitfld.long 0x0 18. "PNS,Pretended Networking state" "0,1"
|
|
bitfld.long 0x0 17. "SRDIS,Self reception disable" "0,1"
|
|
bitfld.long 0x0 16. "RPFQEN,Rx private filters enable Rx mailbox queue enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x0 14. "PNMOD,Pretended Networking mode selection" "0,1"
|
|
bitfld.long 0x0 13. "LAPRIOEN,Local arbitration priority enable" "0,1"
|
|
bitfld.long 0x0 12. "MST,Mailbox stop transmission" "0,1"
|
|
bitfld.long 0x0 11. "FDEN,CAN FD operation enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "FS,Format selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--4. 1. "MSZ,Memory size"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
rbitfld.long 0x4 15. "BOIE,Bus off interrupt enable" "0,1"
|
|
bitfld.long 0x4 14. "ERRSIE,Error summary interrupt enable" "0,1"
|
|
bitfld.long 0x4 12. "LSCMOD,Loopback and silent communication mode" "0,1"
|
|
bitfld.long 0x4 11. "TWERRIE,Tx error warning interrupt enable" "0,1"
|
|
bitfld.long 0x4 10. "RWERRIE,Rx error warning interrupt enable" "0,1"
|
|
bitfld.long 0x4 7. "BSPMOD,Bit sampling mode" "0,1"
|
|
bitfld.long 0x4 6. "ABORDIS,Automatic Bus off recovery not enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TSYNC,Time synchronization enable" "0,1"
|
|
bitfld.long 0x4 4. "MTO,Mailbox transmission order" "0,1"
|
|
bitfld.long 0x4 3. "MMOD,Monitor mode" "0,1"
|
|
line.long 0x8 "TIMER,Timer register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "RMPUBF,Receive mailbox public filter register"
|
|
hexmask.long 0x0 0.--31. 1. "MFDx,Mailbox filter data"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "ERR0,Error register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "REFCNT,Receive error counter for data phase of FD frames"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TEFCNT,Transmit error count for the data phase of FD frames"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RECNT,Receive error count defined by the CAN standard"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TECNT,Transmit error count defined by the CAN standard"
|
|
line.long 0x4 "ERR1,Error register 1"
|
|
rbitfld.long 0x4 31. "BRFERR,Bit recessive error in data phase of FD frames" "0,1"
|
|
rbitfld.long 0x4 30. "BDFERR,Bit dominant error in data phase of FD frames" "0,1"
|
|
rbitfld.long 0x4 28. "CRCFERR,CRC error in data phase of FD frames" "0,1"
|
|
rbitfld.long 0x4 27. "FMFERR,Form error in data phase of FD frames" "0,1"
|
|
rbitfld.long 0x4 26. "STFFERR,Form error in data phase of FD frames" "0,1"
|
|
bitfld.long 0x4 21. "ERROVR,Error overrun" "0,1"
|
|
bitfld.long 0x4 20. "ERRFSF,Error summary flag for data phase of FD frames" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "BORF,Bus off recovery flag" "0,1"
|
|
rbitfld.long 0x4 18. "SYN,Synchronization flag" "0,1"
|
|
bitfld.long 0x4 17. "TWERRIF,Tx error warning interrupt flag" "0,1"
|
|
bitfld.long 0x4 16. "RWERRIF,Rx error warning interrupt flag" "0,1"
|
|
rbitfld.long 0x4 15. "BRERR,Bit recessive error for all format frames" "0,1"
|
|
rbitfld.long 0x4 14. "BDERR,Bit dominant error for all format frames" "0,1"
|
|
rbitfld.long 0x4 13. "ACKERR,ACK error" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 12. "CRCERR,CRC error" "0,1"
|
|
rbitfld.long 0x4 11. "FMERR,Form error" "0,1"
|
|
rbitfld.long 0x4 10. "STFERR,Stuff error" "0,1"
|
|
rbitfld.long 0x4 9. "TWERRF,Tx error warning flag" "0,1"
|
|
rbitfld.long 0x4 8. "RWERRF,Rx error warning flag" "0,1"
|
|
rbitfld.long 0x4 7. "IDLEF,IDLE flag" "0,1"
|
|
rbitfld.long 0x4 6. "TS,Transmitting state" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 4.--5. "ERRSI,Error state indicator" "0,1,2,3"
|
|
rbitfld.long 0x4 3. "RS,Receiving state" "0,1"
|
|
bitfld.long 0x4 2. "BOF,Bus off flag" "0,1"
|
|
bitfld.long 0x4 1. "ERRSF,Error summary flag" "0,1"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "INTEN,Interrupt enable register"
|
|
hexmask.long 0x0 0.--31. 1. "MIEx,Message transmission and reception interrupt enable"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "STAT,Status register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "MSx,Mailbox x state"
|
|
bitfld.long 0x0 7. "MS7_RFO,Mailbox 7 state / Rx FIFO overflow" "0,1"
|
|
bitfld.long 0x0 6. "MS6_RFW,Mailbox 6 state / Rx FIFO warning" "0,1"
|
|
bitfld.long 0x0 5. "MS5_RFNE,Mailbox 5 state / Rx FIFO not empty" "0,1"
|
|
bitfld.long 0x0 4. "MS4_RES,Mailbox 4 state / Reserved" "0,1"
|
|
bitfld.long 0x0 3. "MS3_RES,Mailbox 3 state / Reserved" "0,1"
|
|
bitfld.long 0x0 2. "MS2_RES,Mailbox 2 state / Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MS1_RES,Mailbox 1 state / Reserved" "0,1"
|
|
bitfld.long 0x0 0. "MS0_RFC,Mailbox 3 state / Clear Rx FIFO bit" "0,1"
|
|
line.long 0x4 "CTL2,Control register 2"
|
|
bitfld.long 0x4 31. "ERRFSIE,Error summary interrupt enable bit for data phase of FD frames" "0,1"
|
|
bitfld.long 0x4 30. "BORIE,Bus off recovery interrupt enable" "0,1"
|
|
hexmask.long.byte 0x4 24.--27. 1. "RFFN,Rx FIFO filter number"
|
|
hexmask.long.byte 0x4 19.--23. 1. "ASD,Arbitration start delay"
|
|
bitfld.long 0x4 18. "RFO,Receive filter order" "0,1"
|
|
bitfld.long 0x4 17. "RRFRMS,Remote request frame is stored" "0,1"
|
|
bitfld.long 0x4 16. "IDERTR_RMF,IDE and RTR field filter type for Rx mailbox reception" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "ITSRC,Internal counter source" "0,1"
|
|
bitfld.long 0x4 14. "PREEN,Protocol exception detection enable by CAN standard" "0,1"
|
|
bitfld.long 0x4 12. "ISO,ISO CAN FD" "0,1"
|
|
bitfld.long 0x4 11. "EFDIS,Edge filtering disable" "0,1"
|
|
bitfld.long 0x4 0. "WERRIE,Write error interrupt enable" "0,1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "CRCC,CRC for classical frame register"
|
|
hexmask.long.byte 0x0 16.--20. 1. "ANTM,Associated number of mailbox for transmitting the CRCTC[14:0] value"
|
|
hexmask.long.word 0x0 0.--14. 1. "CRCTC,Transmitted CRC value for classical frames"
|
|
line.long 0x4 "RFIFOPUBF,Receive FIFO public filter register"
|
|
hexmask.long 0x4 0.--31. 1. "FFDx,Rx FIFO filter data"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "RFIFOIFMN,Receive FIFO identifier filter matching number register"
|
|
hexmask.long.word 0x0 0.--8. 1. "IDFMN,Identifier filter matching number"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "BT,Bit timing register"
|
|
hexmask.long.word 0x0 21.--30. 1. "BAUDPSC,Baud rate prescaler"
|
|
hexmask.long.byte 0x0 16.--20. 1. "SJW,Resynchronization jump width"
|
|
hexmask.long.byte 0x0 10.--15. 1. "PTS,Propagation time segment"
|
|
hexmask.long.byte 0x0 5.--9. 1. "PBS1,Phase buffer segment 1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PBS2,Phase buffer segment 2"
|
|
group.long 0x880++0x7F
|
|
line.long 0x0 "RFIFOMPF0,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x0 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x4 "RFIFOMPF1,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x4 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x8 "RFIFOMPF2,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x8 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0xC "RFIFOMPF3,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0xC 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x10 "RFIFOMPF4,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x10 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x14 "RFIFOMPF5,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x14 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x18 "RFIFOMPF6,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x18 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x1C "RFIFOMPF7,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x1C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x20 "RFIFOMPF8,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x20 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x24 "RFIFOMPF9,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x24 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x28 "RFIFOMPF10,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x28 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x2C "RFIFOMPF11,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x2C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x30 "RFIFOMPF12,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x30 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x34 "RFIFOMPF13,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x34 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x38 "RFIFOMPF14,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x38 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x3C "RFIFOMPF15,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x3C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x40 "RFIFOMPF16,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x40 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x44 "RFIFOMPF17,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x44 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x48 "RFIFOMPF18,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x48 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x4C "RFIFOMPF19,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x4C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x50 "RFIFOMPF20,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x50 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x54 "RFIFOMPF21,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x54 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x58 "RFIFOMPF22,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x58 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x5C "RFIFOMPF23,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x5C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x60 "RFIFOMPF24,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x60 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x64 "RFIFOMPF25,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x64 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x68 "RFIFOMPF26,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x68 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x6C "RFIFOMPF27,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x6C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x70 "RFIFOMPF28,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x70 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x74 "RFIFOMPF29,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x74 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x78 "RFIFOMPF30,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x78 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x7C "RFIFOMPF31,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x7C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
group.long 0xB00++0x27
|
|
line.long 0x0 "PN_CTL0,CAN_sleep mode control register 0"
|
|
bitfld.long 0x0 17. "WTOIE,Wakeup timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 16. "WMIE,Wakeup match interrupt enable" "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "NMM,Number of messages matching times"
|
|
bitfld.long 0x0 4.--5. "DATAFT,DATA field filtering type in CAN_sleep mode" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "IDFT,ID field filtering type in CAN_sleep mode" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "FFT,Frame filtering type in CAN_sleep mode" "0,1,2,3"
|
|
line.long 0x4 "PN_TO,CAN_sleep mode timeout register"
|
|
hexmask.long.word 0x4 0.--15. 1. "WTO,Wakeup timeout"
|
|
line.long 0x8 "PN_STAT,CAN_sleep mode status register"
|
|
bitfld.long 0x8 17. "WTOS,Wakeup timeout flag status" "0,1"
|
|
bitfld.long 0x8 16. "WMS,Wakeup match flag status" "0,1"
|
|
hexmask.long.byte 0x8 8.--15. 1. "MMCNT,Matching message counter in CAN_sleep mode"
|
|
rbitfld.long 0x8 7. "MMCNTS,Matching message counter state" "0,1"
|
|
line.long 0xC "PN_EID0,CAN_sleep mode expected identifier 0 register"
|
|
bitfld.long 0xC 30. "EIDE,Expected IDE in CAN_sleep mode" "0,1"
|
|
bitfld.long 0xC 29. "ERTR,Expected RTR in CAN_sleep mode" "0,1"
|
|
hexmask.long 0xC 0.--28. 1. "EIDF_ELT,Expected ID field / expected ID low threshold in CAN_sleep mode"
|
|
line.long 0x10 "PN_EDLC,CAN_sleep mode expected DLC register"
|
|
hexmask.long.byte 0x10 16.--19. 1. "DLCELT,DLC expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x10 0.--3. 1. "DLCEHT,DLC expected high threshold in CAN_sleep mode"
|
|
line.long 0x14 "PN_EDL0,CAN_sleep mode expected data low 0 register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DB0ELT,Data byte 0 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x14 16.--23. 1. "DB1ELT,Data byte 1 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DB2ELT,Data byte 2 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DB3ELT,Data byte 3 expected low threshold in CAN_sleep mode"
|
|
line.long 0x18 "PN_EDL1,CAN_sleep mode expected data low 1 register"
|
|
hexmask.long.byte 0x18 24.--31. 1. "DB4ELT,Data byte 4 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x18 16.--23. 1. "DB5ELT,Data byte 5 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x18 8.--15. 1. "DB6ELT,Data byte 6 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x18 0.--7. 1. "DB7ELT,Data byte 7 expected low threshold in CAN_sleep mode"
|
|
line.long 0x1C "IFEID1,CAN_sleep mode identifier filter / expected identifier 1 register"
|
|
bitfld.long 0x1C 30. "IDEFD,IDE filter data in CAN_sleep mode" "0,1"
|
|
bitfld.long 0x1C 29. "RTRFD,RTR filter data in CAN_sleep mode" "0,1"
|
|
hexmask.long 0x1C 0.--28. 1. "IDFD_EHT,ID filter data / ID expected high threshold in CAN_sleep mode"
|
|
line.long 0x20 "PN_DF0EDH0,CAN_sleep mode data 0 filter / expected data high 0 register"
|
|
hexmask.long.byte 0x20 24.--31. 1. "DB0FD_EHT,Data byte 0 filter data / Data byte 0 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x20 16.--23. 1. "DB1FD_EHT,Data byte 1 filter data / Data byte 1 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x20 8.--15. 1. "DB2FD_EHT,Data byte 3 filter data / Data byte 3 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x20 0.--7. 1. "DB3FD_EHT,Data byte 3 filter data / Data byte 3 expected high threshold in CAN_sleep mode"
|
|
line.long 0x24 "PN_DF1EDH1,CAN_sleep mode data 1 filter / expected data high 1 register"
|
|
hexmask.long.byte 0x24 24.--31. 1. "DB4FD_EHT,Data byte 4 filter data / Data byte 4 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x24 16.--23. 1. "DB5FD_EHT,Data byte 5 filter data / Data byte 5 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x24 8.--15. 1. "DB6FD_EHT,Data byte 6 filter data / Data byte 6 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x24 0.--7. 1. "DB7FD_EHT,Data byte 7 filter data / Data byte 7 expected high threshold in CAN_sleep mode"
|
|
rgroup.long 0xB40++0x3
|
|
line.long 0x0 "RWM0CS,CAN_sleep mode received wakeup mailbox x control status information register"
|
|
bitfld.long 0x0 22. "RSRR,Received SRR bit" "0,1"
|
|
bitfld.long 0x0 21. "RIDE,Received IDE bit" "0,1"
|
|
bitfld.long 0x0 20. "RRTR,Received RTR bit" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "RDLC,Received DLC bits"
|
|
rgroup.long 0xB50++0x3
|
|
line.long 0x0 "RWM1CS,CAN_sleep mode received wakeup mailbox x control status information register"
|
|
bitfld.long 0x0 22. "RSRR,Received SRR bit" "0,1"
|
|
bitfld.long 0x0 21. "RIDE,Received IDE bit" "0,1"
|
|
bitfld.long 0x0 20. "RRTR,Received RTR bit" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "RDLC,Received DLC bits"
|
|
rgroup.long 0xB60++0x3
|
|
line.long 0x0 "RWM2CS,CAN_sleep mode received wakeup mailbox x control status information register"
|
|
bitfld.long 0x0 22. "RSRR,Received SRR bit" "0,1"
|
|
bitfld.long 0x0 21. "RIDE,Received IDE bit" "0,1"
|
|
bitfld.long 0x0 20. "RRTR,Received RTR bit" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "RDLC,Received DLC bits"
|
|
rgroup.long 0xB70++0x3
|
|
line.long 0x0 "RWM3CS,CAN_sleep mode received wakeup mailbox x control status information register"
|
|
bitfld.long 0x0 22. "RSRR,Received SRR bit" "0,1"
|
|
bitfld.long 0x0 21. "RIDE,Received IDE bit" "0,1"
|
|
bitfld.long 0x0 20. "RRTR,Received RTR bit" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "RDLC,Received DLC bits"
|
|
rgroup.long 0xB44++0x3
|
|
line.long 0x0 "PN_RWM0I,CAN_sleep mode received wakeup mailbox x identifier register"
|
|
hexmask.long 0x0 0.--28. 1. "RID,Received ID bits"
|
|
rgroup.long 0xB54++0x3
|
|
line.long 0x0 "PN_RWM1I,CAN_sleep mode received wakeup mailbox x identifier register"
|
|
hexmask.long 0x0 0.--28. 1. "RID,Received ID bits"
|
|
rgroup.long 0xB64++0x3
|
|
line.long 0x0 "PN_RWM2I,CAN_sleep mode received wakeup mailbox x identifier register"
|
|
hexmask.long 0x0 0.--28. 1. "RID,Received ID bits"
|
|
rgroup.long 0xB74++0x3
|
|
line.long 0x0 "PN_RWM3I,CAN_sleep mode received wakeup mailbox x identifier register"
|
|
hexmask.long 0x0 0.--28. 1. "RID,Received ID bits"
|
|
rgroup.long 0xB48++0x3
|
|
line.long 0x0 "RWM0D0,CAN_sleep mode received wakeup mailbox x data 0 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB0,Received data byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB1,Received data byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB2,Received data byte 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB3,Received data byte 3"
|
|
rgroup.long 0xB58++0x3
|
|
line.long 0x0 "RWM1D0,CAN_sleep mode received wakeup mailbox x data 0 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB0,Received data byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB1,Received data byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB2,Received data byte 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB3,Received data byte 3"
|
|
rgroup.long 0xB68++0x3
|
|
line.long 0x0 "RWM2D0,CAN_sleep mode received wakeup mailbox x data 0 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB0,Received data byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB1,Received data byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB2,Received data byte 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB3,Received data byte 3"
|
|
rgroup.long 0xB78++0x3
|
|
line.long 0x0 "RWM3D0,CAN_sleep mode received wakeup mailbox x data 0 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB0,Received data byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB1,Received data byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB2,Received data byte 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB3,Received data byte 3"
|
|
rgroup.long 0xB4C++0x3
|
|
line.long 0x0 "RWM0D1,CAN_sleep mode received wakeup mailbox x data 1 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB4,Received data byte 4"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB5,Received data byte 5"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB6,Received data byte 6"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB7,Received data byte 7"
|
|
rgroup.long 0xB5C++0x3
|
|
line.long 0x0 "RWM1D1,CAN_sleep mode received wakeup mailbox x data 1 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB4,Received data byte 4"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB5,Received data byte 5"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB6,Received data byte 6"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB7,Received data byte 7"
|
|
rgroup.long 0xB6C++0x3
|
|
line.long 0x0 "RWM2D1,CAN_sleep mode received wakeup mailbox x data 1 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB4,Received data byte 4"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB5,Received data byte 5"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB6,Received data byte 6"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB7,Received data byte 7"
|
|
rgroup.long 0xB7C++0x3
|
|
line.long 0x0 "RWM3D1,CAN_sleep mode received wakeup mailbox x data 1 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB4,Received data byte 4"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB5,Received data byte 5"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB6,Received data byte 6"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB7,Received data byte 7"
|
|
group.long 0xC00++0xB
|
|
line.long 0x0 "FDCTL,FD control register"
|
|
bitfld.long 0x0 31. "BRSEN,Bit rate of data switch enable" "0,1"
|
|
bitfld.long 0x0 16.--17. "MDSZ,Mailbox data size" "0,1,2,3"
|
|
bitfld.long 0x0 15. "TDCEN,Transmitter delay compensation enable" "0,1"
|
|
bitfld.long 0x0 14. "TDCS,Transmitter delay compensation status" "0,1"
|
|
hexmask.long.byte 0x0 8.--12. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TDCV,Transmitter delay compensation value"
|
|
line.long 0x4 "FDBT,FD bit timing register"
|
|
hexmask.long.word 0x4 20.--29. 1. "DBAUDPSC,Baud rate prescaler for data bit time"
|
|
bitfld.long 0x4 16.--18. "DSJW,Resynchronization jump width for data bit time" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 10.--14. 1. "DPTS,Propagation time segment for data bit time"
|
|
bitfld.long 0x4 5.--7. "DPBS1,Phase buffer segment 1 for data bit time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "DPBS2,Phase buffer segment 2 for data bit time" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CRCCFD,CRC for classical and FD frame register"
|
|
hexmask.long.byte 0x8 24.--28. 1. "ANTM,Associated number of mailbox for transmitting the CRCTCI[20:0] value"
|
|
hexmask.long.tbyte 0x8 0.--20. 1. "CRCTCI,Transmitted CRC value for classical and ISO / non-ISO FD frames"
|
|
tree.end
|
|
tree "CAN1"
|
|
base ad:0x4001B000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 31. "CANDIS,CAN disable" "0,1"
|
|
bitfld.long 0x0 30. "INAMOD,Inactive mode enable" "0,1"
|
|
bitfld.long 0x0 29. "RFEN,Rx FIFO enable" "0,1"
|
|
bitfld.long 0x0 28. "HALT,Halt CAN" "0,1"
|
|
rbitfld.long 0x0 27. "NRDY,Not ready" "0,1"
|
|
bitfld.long 0x0 25. "SWRST,Software reset" "0,1"
|
|
bitfld.long 0x0 24. "INAS,Inactive mode state" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SLPS,This bit is only valid when CAN_sleep mode is enabled" "0,1"
|
|
bitfld.long 0x0 21. "WERREN,Error warning enable" "0,1"
|
|
rbitfld.long 0x0 20. "LPS,Low power state" "0,1"
|
|
bitfld.long 0x0 19. "PNEN,Pretended Networking mode enable" "0,1"
|
|
rbitfld.long 0x0 18. "PNS,Pretended Networking state" "0,1"
|
|
bitfld.long 0x0 17. "SRDIS,Self reception disable" "0,1"
|
|
bitfld.long 0x0 16. "RPFQEN,Rx private filters enable Rx mailbox queue enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x0 14. "PNMOD,Pretended Networking mode selection" "0,1"
|
|
bitfld.long 0x0 13. "LAPRIOEN,Local arbitration priority enable" "0,1"
|
|
bitfld.long 0x0 12. "MST,Mailbox stop transmission" "0,1"
|
|
bitfld.long 0x0 11. "FDEN,CAN FD operation enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "FS,Format selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--4. 1. "MSZ,Memory size"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
rbitfld.long 0x4 15. "BOIE,Bus off interrupt enable" "0,1"
|
|
bitfld.long 0x4 14. "ERRSIE,Error summary interrupt enable" "0,1"
|
|
bitfld.long 0x4 12. "LSCMOD,Loopback and silent communication mode" "0,1"
|
|
bitfld.long 0x4 11. "TWERRIE,Tx error warning interrupt enable" "0,1"
|
|
bitfld.long 0x4 10. "RWERRIE,Rx error warning interrupt enable" "0,1"
|
|
bitfld.long 0x4 7. "BSPMOD,Bit sampling mode" "0,1"
|
|
bitfld.long 0x4 6. "ABORDIS,Automatic Bus off recovery not enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TSYNC,Time synchronization enable" "0,1"
|
|
bitfld.long 0x4 4. "MTO,Mailbox transmission order" "0,1"
|
|
bitfld.long 0x4 3. "MMOD,Monitor mode" "0,1"
|
|
line.long 0x8 "TIMER,Timer register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "RMPUBF,Receive mailbox public filter register"
|
|
hexmask.long 0x0 0.--31. 1. "MFDx,Mailbox filter data"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "ERR0,Error register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "REFCNT,Receive error counter for data phase of FD frames"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TEFCNT,Transmit error count for the data phase of FD frames"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RECNT,Receive error count defined by the CAN standard"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TECNT,Transmit error count defined by the CAN standard"
|
|
line.long 0x4 "ERR1,Error register 1"
|
|
rbitfld.long 0x4 31. "BRFERR,Bit recessive error in data phase of FD frames" "0,1"
|
|
rbitfld.long 0x4 30. "BDFERR,Bit dominant error in data phase of FD frames" "0,1"
|
|
rbitfld.long 0x4 28. "CRCFERR,CRC error in data phase of FD frames" "0,1"
|
|
rbitfld.long 0x4 27. "FMFERR,Form error in data phase of FD frames" "0,1"
|
|
rbitfld.long 0x4 26. "STFFERR,Form error in data phase of FD frames" "0,1"
|
|
bitfld.long 0x4 21. "ERROVR,Error overrun" "0,1"
|
|
bitfld.long 0x4 20. "ERRFSF,Error summary flag for data phase of FD frames" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "BORF,Bus off recovery flag" "0,1"
|
|
rbitfld.long 0x4 18. "SYN,Synchronization flag" "0,1"
|
|
bitfld.long 0x4 17. "TWERRIF,Tx error warning interrupt flag" "0,1"
|
|
bitfld.long 0x4 16. "RWERRIF,Rx error warning interrupt flag" "0,1"
|
|
rbitfld.long 0x4 15. "BRERR,Bit recessive error for all format frames" "0,1"
|
|
rbitfld.long 0x4 14. "BDERR,Bit dominant error for all format frames" "0,1"
|
|
rbitfld.long 0x4 13. "ACKERR,ACK error" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 12. "CRCERR,CRC error" "0,1"
|
|
rbitfld.long 0x4 11. "FMERR,Form error" "0,1"
|
|
rbitfld.long 0x4 10. "STFERR,Stuff error" "0,1"
|
|
rbitfld.long 0x4 9. "TWERRF,Tx error warning flag" "0,1"
|
|
rbitfld.long 0x4 8. "RWERRF,Rx error warning flag" "0,1"
|
|
rbitfld.long 0x4 7. "IDLEF,IDLE flag" "0,1"
|
|
rbitfld.long 0x4 6. "TS,Transmitting state" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 4.--5. "ERRSI,Error state indicator" "0,1,2,3"
|
|
rbitfld.long 0x4 3. "RS,Receiving state" "0,1"
|
|
bitfld.long 0x4 2. "BOF,Bus off flag" "0,1"
|
|
bitfld.long 0x4 1. "ERRSF,Error summary flag" "0,1"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "INTEN,Interrupt enable register"
|
|
hexmask.long 0x0 0.--31. 1. "MIEx,Message transmission and reception interrupt enable"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "STAT,Status register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "MSx,Mailbox x state"
|
|
bitfld.long 0x0 7. "MS7_RFO,Mailbox 7 state / Rx FIFO overflow" "0,1"
|
|
bitfld.long 0x0 6. "MS6_RFW,Mailbox 6 state / Rx FIFO warning" "0,1"
|
|
bitfld.long 0x0 5. "MS5_RFNE,Mailbox 5 state / Rx FIFO not empty" "0,1"
|
|
bitfld.long 0x0 4. "MS4_RES,Mailbox 4 state / Reserved" "0,1"
|
|
bitfld.long 0x0 3. "MS3_RES,Mailbox 3 state / Reserved" "0,1"
|
|
bitfld.long 0x0 2. "MS2_RES,Mailbox 2 state / Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MS1_RES,Mailbox 1 state / Reserved" "0,1"
|
|
bitfld.long 0x0 0. "MS0_RFC,Mailbox 3 state / Clear Rx FIFO bit" "0,1"
|
|
line.long 0x4 "CTL2,Control register 2"
|
|
bitfld.long 0x4 31. "ERRFSIE,Error summary interrupt enable bit for data phase of FD frames" "0,1"
|
|
bitfld.long 0x4 30. "BORIE,Bus off recovery interrupt enable" "0,1"
|
|
hexmask.long.byte 0x4 24.--27. 1. "RFFN,Rx FIFO filter number"
|
|
hexmask.long.byte 0x4 19.--23. 1. "ASD,Arbitration start delay"
|
|
bitfld.long 0x4 18. "RFO,Receive filter order" "0,1"
|
|
bitfld.long 0x4 17. "RRFRMS,Remote request frame is stored" "0,1"
|
|
bitfld.long 0x4 16. "IDERTR_RMF,IDE and RTR field filter type for Rx mailbox reception" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "ITSRC,Internal counter source" "0,1"
|
|
bitfld.long 0x4 14. "PREEN,Protocol exception detection enable by CAN standard" "0,1"
|
|
bitfld.long 0x4 12. "ISO,ISO CAN FD" "0,1"
|
|
bitfld.long 0x4 11. "EFDIS,Edge filtering disable" "0,1"
|
|
bitfld.long 0x4 0. "WERRIE,Write error interrupt enable" "0,1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "CRCC,CRC for classical frame register"
|
|
hexmask.long.byte 0x0 16.--20. 1. "ANTM,Associated number of mailbox for transmitting the CRCTC[14:0] value"
|
|
hexmask.long.word 0x0 0.--14. 1. "CRCTC,Transmitted CRC value for classical frames"
|
|
line.long 0x4 "RFIFOPUBF,Receive FIFO public filter register"
|
|
hexmask.long 0x4 0.--31. 1. "FFDx,Rx FIFO filter data"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "RFIFOIFMN,Receive FIFO identifier filter matching number register"
|
|
hexmask.long.word 0x0 0.--8. 1. "IDFMN,Identifier filter matching number"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "BT,Bit timing register"
|
|
hexmask.long.word 0x0 21.--30. 1. "BAUDPSC,Baud rate prescaler"
|
|
hexmask.long.byte 0x0 16.--20. 1. "SJW,Resynchronization jump width"
|
|
hexmask.long.byte 0x0 10.--15. 1. "PTS,Propagation time segment"
|
|
hexmask.long.byte 0x0 5.--9. 1. "PBS1,Phase buffer segment 1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PBS2,Phase buffer segment 2"
|
|
group.long 0x880++0x7F
|
|
line.long 0x0 "RFIFOMPF0,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x0 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x4 "RFIFOMPF1,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x4 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x8 "RFIFOMPF2,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x8 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0xC "RFIFOMPF3,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0xC 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x10 "RFIFOMPF4,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x10 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x14 "RFIFOMPF5,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x14 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x18 "RFIFOMPF6,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x18 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x1C "RFIFOMPF7,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x1C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x20 "RFIFOMPF8,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x20 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x24 "RFIFOMPF9,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x24 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x28 "RFIFOMPF10,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x28 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x2C "RFIFOMPF11,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x2C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x30 "RFIFOMPF12,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x30 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x34 "RFIFOMPF13,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x34 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x38 "RFIFOMPF14,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x38 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x3C "RFIFOMPF15,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x3C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x40 "RFIFOMPF16,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x40 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x44 "RFIFOMPF17,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x44 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x48 "RFIFOMPF18,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x48 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x4C "RFIFOMPF19,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x4C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x50 "RFIFOMPF20,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x50 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x54 "RFIFOMPF21,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x54 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x58 "RFIFOMPF22,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x58 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x5C "RFIFOMPF23,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x5C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x60 "RFIFOMPF24,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x60 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x64 "RFIFOMPF25,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x64 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x68 "RFIFOMPF26,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x68 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x6C "RFIFOMPF27,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x6C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x70 "RFIFOMPF28,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x70 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x74 "RFIFOMPF29,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x74 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x78 "RFIFOMPF30,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x78 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x7C "RFIFOMPF31,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x7C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
group.long 0xB00++0x27
|
|
line.long 0x0 "PN_CTL0,CAN_sleep mode control register 0"
|
|
bitfld.long 0x0 17. "WTOIE,Wakeup timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 16. "WMIE,Wakeup match interrupt enable" "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "NMM,Number of messages matching times"
|
|
bitfld.long 0x0 4.--5. "DATAFT,DATA field filtering type in CAN_sleep mode" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "IDFT,ID field filtering type in CAN_sleep mode" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "FFT,Frame filtering type in CAN_sleep mode" "0,1,2,3"
|
|
line.long 0x4 "PN_TO,CAN_sleep mode timeout register"
|
|
hexmask.long.word 0x4 0.--15. 1. "WTO,Wakeup timeout"
|
|
line.long 0x8 "PN_STAT,CAN_sleep mode status register"
|
|
bitfld.long 0x8 17. "WTOS,Wakeup timeout flag status" "0,1"
|
|
bitfld.long 0x8 16. "WMS,Wakeup match flag status" "0,1"
|
|
hexmask.long.byte 0x8 8.--15. 1. "MMCNT,Matching message counter in CAN_sleep mode"
|
|
rbitfld.long 0x8 7. "MMCNTS,Matching message counter state" "0,1"
|
|
line.long 0xC "PN_EID0,CAN_sleep mode expected identifier 0 register"
|
|
bitfld.long 0xC 30. "EIDE,Expected IDE in CAN_sleep mode" "0,1"
|
|
bitfld.long 0xC 29. "ERTR,Expected RTR in CAN_sleep mode" "0,1"
|
|
hexmask.long 0xC 0.--28. 1. "EIDF_ELT,Expected ID field / expected ID low threshold in CAN_sleep mode"
|
|
line.long 0x10 "PN_EDLC,CAN_sleep mode expected DLC register"
|
|
hexmask.long.byte 0x10 16.--19. 1. "DLCELT,DLC expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x10 0.--3. 1. "DLCEHT,DLC expected high threshold in CAN_sleep mode"
|
|
line.long 0x14 "PN_EDL0,CAN_sleep mode expected data low 0 register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DB0ELT,Data byte 0 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x14 16.--23. 1. "DB1ELT,Data byte 1 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DB2ELT,Data byte 2 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DB3ELT,Data byte 3 expected low threshold in CAN_sleep mode"
|
|
line.long 0x18 "PN_EDL1,CAN_sleep mode expected data low 1 register"
|
|
hexmask.long.byte 0x18 24.--31. 1. "DB4ELT,Data byte 4 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x18 16.--23. 1. "DB5ELT,Data byte 5 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x18 8.--15. 1. "DB6ELT,Data byte 6 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x18 0.--7. 1. "DB7ELT,Data byte 7 expected low threshold in CAN_sleep mode"
|
|
line.long 0x1C "IFEID1,CAN_sleep mode identifier filter / expected identifier 1 register"
|
|
bitfld.long 0x1C 30. "IDEFD,IDE filter data in CAN_sleep mode" "0,1"
|
|
bitfld.long 0x1C 29. "RTRFD,RTR filter data in CAN_sleep mode" "0,1"
|
|
hexmask.long 0x1C 0.--28. 1. "IDFD_EHT,ID filter data / ID expected high threshold in CAN_sleep mode"
|
|
line.long 0x20 "PN_DF0EDH0,CAN_sleep mode data 0 filter / expected data high 0 register"
|
|
hexmask.long.byte 0x20 24.--31. 1. "DB0FD_EHT,Data byte 0 filter data / Data byte 0 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x20 16.--23. 1. "DB1FD_EHT,Data byte 1 filter data / Data byte 1 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x20 8.--15. 1. "DB2FD_EHT,Data byte 3 filter data / Data byte 3 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x20 0.--7. 1. "DB3FD_EHT,Data byte 3 filter data / Data byte 3 expected high threshold in CAN_sleep mode"
|
|
line.long 0x24 "PN_DF1EDH1,CAN_sleep mode data 1 filter / expected data high 1 register"
|
|
hexmask.long.byte 0x24 24.--31. 1. "DB4FD_EHT,Data byte 4 filter data / Data byte 4 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x24 16.--23. 1. "DB5FD_EHT,Data byte 5 filter data / Data byte 5 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x24 8.--15. 1. "DB6FD_EHT,Data byte 6 filter data / Data byte 6 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x24 0.--7. 1. "DB7FD_EHT,Data byte 7 filter data / Data byte 7 expected high threshold in CAN_sleep mode"
|
|
rgroup.long 0xB40++0x3
|
|
line.long 0x0 "RWM0CS,CAN_sleep mode received wakeup mailbox x control status information register"
|
|
bitfld.long 0x0 22. "RSRR,Received SRR bit" "0,1"
|
|
bitfld.long 0x0 21. "RIDE,Received IDE bit" "0,1"
|
|
bitfld.long 0x0 20. "RRTR,Received RTR bit" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "RDLC,Received DLC bits"
|
|
rgroup.long 0xB50++0x3
|
|
line.long 0x0 "RWM1CS,CAN_sleep mode received wakeup mailbox x control status information register"
|
|
bitfld.long 0x0 22. "RSRR,Received SRR bit" "0,1"
|
|
bitfld.long 0x0 21. "RIDE,Received IDE bit" "0,1"
|
|
bitfld.long 0x0 20. "RRTR,Received RTR bit" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "RDLC,Received DLC bits"
|
|
rgroup.long 0xB60++0x3
|
|
line.long 0x0 "RWM2CS,CAN_sleep mode received wakeup mailbox x control status information register"
|
|
bitfld.long 0x0 22. "RSRR,Received SRR bit" "0,1"
|
|
bitfld.long 0x0 21. "RIDE,Received IDE bit" "0,1"
|
|
bitfld.long 0x0 20. "RRTR,Received RTR bit" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "RDLC,Received DLC bits"
|
|
rgroup.long 0xB70++0x3
|
|
line.long 0x0 "RWM3CS,CAN_sleep mode received wakeup mailbox x control status information register"
|
|
bitfld.long 0x0 22. "RSRR,Received SRR bit" "0,1"
|
|
bitfld.long 0x0 21. "RIDE,Received IDE bit" "0,1"
|
|
bitfld.long 0x0 20. "RRTR,Received RTR bit" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "RDLC,Received DLC bits"
|
|
rgroup.long 0xB44++0x3
|
|
line.long 0x0 "PN_RWM0I,CAN_sleep mode received wakeup mailbox x identifier register"
|
|
hexmask.long 0x0 0.--28. 1. "RID,Received ID bits"
|
|
rgroup.long 0xB54++0x3
|
|
line.long 0x0 "PN_RWM1I,CAN_sleep mode received wakeup mailbox x identifier register"
|
|
hexmask.long 0x0 0.--28. 1. "RID,Received ID bits"
|
|
rgroup.long 0xB64++0x3
|
|
line.long 0x0 "PN_RWM2I,CAN_sleep mode received wakeup mailbox x identifier register"
|
|
hexmask.long 0x0 0.--28. 1. "RID,Received ID bits"
|
|
rgroup.long 0xB74++0x3
|
|
line.long 0x0 "PN_RWM3I,CAN_sleep mode received wakeup mailbox x identifier register"
|
|
hexmask.long 0x0 0.--28. 1. "RID,Received ID bits"
|
|
rgroup.long 0xB48++0x3
|
|
line.long 0x0 "RWM0D0,CAN_sleep mode received wakeup mailbox x data 0 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB0,Received data byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB1,Received data byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB2,Received data byte 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB3,Received data byte 3"
|
|
rgroup.long 0xB58++0x3
|
|
line.long 0x0 "RWM1D0,CAN_sleep mode received wakeup mailbox x data 0 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB0,Received data byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB1,Received data byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB2,Received data byte 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB3,Received data byte 3"
|
|
rgroup.long 0xB68++0x3
|
|
line.long 0x0 "RWM2D0,CAN_sleep mode received wakeup mailbox x data 0 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB0,Received data byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB1,Received data byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB2,Received data byte 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB3,Received data byte 3"
|
|
rgroup.long 0xB78++0x3
|
|
line.long 0x0 "RWM3D0,CAN_sleep mode received wakeup mailbox x data 0 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB0,Received data byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB1,Received data byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB2,Received data byte 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB3,Received data byte 3"
|
|
rgroup.long 0xB4C++0x3
|
|
line.long 0x0 "RWM0D1,CAN_sleep mode received wakeup mailbox x data 1 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB4,Received data byte 4"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB5,Received data byte 5"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB6,Received data byte 6"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB7,Received data byte 7"
|
|
rgroup.long 0xB5C++0x3
|
|
line.long 0x0 "RWM1D1,CAN_sleep mode received wakeup mailbox x data 1 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB4,Received data byte 4"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB5,Received data byte 5"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB6,Received data byte 6"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB7,Received data byte 7"
|
|
rgroup.long 0xB6C++0x3
|
|
line.long 0x0 "RWM2D1,CAN_sleep mode received wakeup mailbox x data 1 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB4,Received data byte 4"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB5,Received data byte 5"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB6,Received data byte 6"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB7,Received data byte 7"
|
|
rgroup.long 0xB7C++0x3
|
|
line.long 0x0 "RWM3D1,CAN_sleep mode received wakeup mailbox x data 1 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB4,Received data byte 4"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB5,Received data byte 5"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB6,Received data byte 6"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB7,Received data byte 7"
|
|
group.long 0xC00++0xB
|
|
line.long 0x0 "FDCTL,FD control register"
|
|
bitfld.long 0x0 31. "BRSEN,Bit rate of data switch enable" "0,1"
|
|
bitfld.long 0x0 16.--17. "MDSZ,Mailbox data size" "0,1,2,3"
|
|
bitfld.long 0x0 15. "TDCEN,Transmitter delay compensation enable" "0,1"
|
|
bitfld.long 0x0 14. "TDCS,Transmitter delay compensation status" "0,1"
|
|
hexmask.long.byte 0x0 8.--12. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TDCV,Transmitter delay compensation value"
|
|
line.long 0x4 "FDBT,FD bit timing register"
|
|
hexmask.long.word 0x4 20.--29. 1. "DBAUDPSC,Baud rate prescaler for data bit time"
|
|
bitfld.long 0x4 16.--18. "DSJW,Resynchronization jump width for data bit time" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 10.--14. 1. "DPTS,Propagation time segment for data bit time"
|
|
bitfld.long 0x4 5.--7. "DPBS1,Phase buffer segment 1 for data bit time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "DPBS2,Phase buffer segment 2 for data bit time" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CRCCFD,CRC for classical and FD frame register"
|
|
hexmask.long.byte 0x8 24.--28. 1. "ANTM,Associated number of mailbox for transmitting the CRCTCI[20:0] value"
|
|
hexmask.long.tbyte 0x8 0.--20. 1. "CRCTCI,Transmitted CRC value for classical and ISO / non-ISO FD frames"
|
|
tree.end
|
|
tree "CAN2"
|
|
base ad:0x4001C000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 31. "CANDIS,CAN disable" "0,1"
|
|
bitfld.long 0x0 30. "INAMOD,Inactive mode enable" "0,1"
|
|
bitfld.long 0x0 29. "RFEN,Rx FIFO enable" "0,1"
|
|
bitfld.long 0x0 28. "HALT,Halt CAN" "0,1"
|
|
rbitfld.long 0x0 27. "NRDY,Not ready" "0,1"
|
|
bitfld.long 0x0 25. "SWRST,Software reset" "0,1"
|
|
bitfld.long 0x0 24. "INAS,Inactive mode state" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SLPS,This bit is only valid when CAN_sleep mode is enabled" "0,1"
|
|
bitfld.long 0x0 21. "WERREN,Error warning enable" "0,1"
|
|
rbitfld.long 0x0 20. "LPS,Low power state" "0,1"
|
|
bitfld.long 0x0 19. "PNEN,Pretended Networking mode enable" "0,1"
|
|
rbitfld.long 0x0 18. "PNS,Pretended Networking state" "0,1"
|
|
bitfld.long 0x0 17. "SRDIS,Self reception disable" "0,1"
|
|
bitfld.long 0x0 16. "RPFQEN,Rx private filters enable Rx mailbox queue enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x0 14. "PNMOD,Pretended Networking mode selection" "0,1"
|
|
bitfld.long 0x0 13. "LAPRIOEN,Local arbitration priority enable" "0,1"
|
|
bitfld.long 0x0 12. "MST,Mailbox stop transmission" "0,1"
|
|
bitfld.long 0x0 11. "FDEN,CAN FD operation enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "FS,Format selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--4. 1. "MSZ,Memory size"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
rbitfld.long 0x4 15. "BOIE,Bus off interrupt enable" "0,1"
|
|
bitfld.long 0x4 14. "ERRSIE,Error summary interrupt enable" "0,1"
|
|
bitfld.long 0x4 12. "LSCMOD,Loopback and silent communication mode" "0,1"
|
|
bitfld.long 0x4 11. "TWERRIE,Tx error warning interrupt enable" "0,1"
|
|
bitfld.long 0x4 10. "RWERRIE,Rx error warning interrupt enable" "0,1"
|
|
bitfld.long 0x4 7. "BSPMOD,Bit sampling mode" "0,1"
|
|
bitfld.long 0x4 6. "ABORDIS,Automatic Bus off recovery not enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TSYNC,Time synchronization enable" "0,1"
|
|
bitfld.long 0x4 4. "MTO,Mailbox transmission order" "0,1"
|
|
bitfld.long 0x4 3. "MMOD,Monitor mode" "0,1"
|
|
line.long 0x8 "TIMER,Timer register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "RMPUBF,Receive mailbox public filter register"
|
|
hexmask.long 0x0 0.--31. 1. "MFDx,Mailbox filter data"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "ERR0,Error register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "REFCNT,Receive error counter for data phase of FD frames"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TEFCNT,Transmit error count for the data phase of FD frames"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RECNT,Receive error count defined by the CAN standard"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TECNT,Transmit error count defined by the CAN standard"
|
|
line.long 0x4 "ERR1,Error register 1"
|
|
rbitfld.long 0x4 31. "BRFERR,Bit recessive error in data phase of FD frames" "0,1"
|
|
rbitfld.long 0x4 30. "BDFERR,Bit dominant error in data phase of FD frames" "0,1"
|
|
rbitfld.long 0x4 28. "CRCFERR,CRC error in data phase of FD frames" "0,1"
|
|
rbitfld.long 0x4 27. "FMFERR,Form error in data phase of FD frames" "0,1"
|
|
rbitfld.long 0x4 26. "STFFERR,Form error in data phase of FD frames" "0,1"
|
|
bitfld.long 0x4 21. "ERROVR,Error overrun" "0,1"
|
|
bitfld.long 0x4 20. "ERRFSF,Error summary flag for data phase of FD frames" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "BORF,Bus off recovery flag" "0,1"
|
|
rbitfld.long 0x4 18. "SYN,Synchronization flag" "0,1"
|
|
bitfld.long 0x4 17. "TWERRIF,Tx error warning interrupt flag" "0,1"
|
|
bitfld.long 0x4 16. "RWERRIF,Rx error warning interrupt flag" "0,1"
|
|
rbitfld.long 0x4 15. "BRERR,Bit recessive error for all format frames" "0,1"
|
|
rbitfld.long 0x4 14. "BDERR,Bit dominant error for all format frames" "0,1"
|
|
rbitfld.long 0x4 13. "ACKERR,ACK error" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 12. "CRCERR,CRC error" "0,1"
|
|
rbitfld.long 0x4 11. "FMERR,Form error" "0,1"
|
|
rbitfld.long 0x4 10. "STFERR,Stuff error" "0,1"
|
|
rbitfld.long 0x4 9. "TWERRF,Tx error warning flag" "0,1"
|
|
rbitfld.long 0x4 8. "RWERRF,Rx error warning flag" "0,1"
|
|
rbitfld.long 0x4 7. "IDLEF,IDLE flag" "0,1"
|
|
rbitfld.long 0x4 6. "TS,Transmitting state" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 4.--5. "ERRSI,Error state indicator" "0,1,2,3"
|
|
rbitfld.long 0x4 3. "RS,Receiving state" "0,1"
|
|
bitfld.long 0x4 2. "BOF,Bus off flag" "0,1"
|
|
bitfld.long 0x4 1. "ERRSF,Error summary flag" "0,1"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "INTEN,Interrupt enable register"
|
|
hexmask.long 0x0 0.--31. 1. "MIEx,Message transmission and reception interrupt enable"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "STAT,Status register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "MSx,Mailbox x state"
|
|
bitfld.long 0x0 7. "MS7_RFO,Mailbox 7 state / Rx FIFO overflow" "0,1"
|
|
bitfld.long 0x0 6. "MS6_RFW,Mailbox 6 state / Rx FIFO warning" "0,1"
|
|
bitfld.long 0x0 5. "MS5_RFNE,Mailbox 5 state / Rx FIFO not empty" "0,1"
|
|
bitfld.long 0x0 4. "MS4_RES,Mailbox 4 state / Reserved" "0,1"
|
|
bitfld.long 0x0 3. "MS3_RES,Mailbox 3 state / Reserved" "0,1"
|
|
bitfld.long 0x0 2. "MS2_RES,Mailbox 2 state / Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MS1_RES,Mailbox 1 state / Reserved" "0,1"
|
|
bitfld.long 0x0 0. "MS0_RFC,Mailbox 3 state / Clear Rx FIFO bit" "0,1"
|
|
line.long 0x4 "CTL2,Control register 2"
|
|
bitfld.long 0x4 31. "ERRFSIE,Error summary interrupt enable bit for data phase of FD frames" "0,1"
|
|
bitfld.long 0x4 30. "BORIE,Bus off recovery interrupt enable" "0,1"
|
|
hexmask.long.byte 0x4 24.--27. 1. "RFFN,Rx FIFO filter number"
|
|
hexmask.long.byte 0x4 19.--23. 1. "ASD,Arbitration start delay"
|
|
bitfld.long 0x4 18. "RFO,Receive filter order" "0,1"
|
|
bitfld.long 0x4 17. "RRFRMS,Remote request frame is stored" "0,1"
|
|
bitfld.long 0x4 16. "IDERTR_RMF,IDE and RTR field filter type for Rx mailbox reception" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "ITSRC,Internal counter source" "0,1"
|
|
bitfld.long 0x4 14. "PREEN,Protocol exception detection enable by CAN standard" "0,1"
|
|
bitfld.long 0x4 12. "ISO,ISO CAN FD" "0,1"
|
|
bitfld.long 0x4 11. "EFDIS,Edge filtering disable" "0,1"
|
|
bitfld.long 0x4 0. "WERRIE,Write error interrupt enable" "0,1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "CRCC,CRC for classical frame register"
|
|
hexmask.long.byte 0x0 16.--20. 1. "ANTM,Associated number of mailbox for transmitting the CRCTC[14:0] value"
|
|
hexmask.long.word 0x0 0.--14. 1. "CRCTC,Transmitted CRC value for classical frames"
|
|
line.long 0x4 "RFIFOPUBF,Receive FIFO public filter register"
|
|
hexmask.long 0x4 0.--31. 1. "FFDx,Rx FIFO filter data"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "RFIFOIFMN,Receive FIFO identifier filter matching number register"
|
|
hexmask.long.word 0x0 0.--8. 1. "IDFMN,Identifier filter matching number"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "BT,Bit timing register"
|
|
hexmask.long.word 0x0 21.--30. 1. "BAUDPSC,Baud rate prescaler"
|
|
hexmask.long.byte 0x0 16.--20. 1. "SJW,Resynchronization jump width"
|
|
hexmask.long.byte 0x0 10.--15. 1. "PTS,Propagation time segment"
|
|
hexmask.long.byte 0x0 5.--9. 1. "PBS1,Phase buffer segment 1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PBS2,Phase buffer segment 2"
|
|
group.long 0x880++0x7F
|
|
line.long 0x0 "RFIFOMPF0,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x0 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x4 "RFIFOMPF1,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x4 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x8 "RFIFOMPF2,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x8 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0xC "RFIFOMPF3,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0xC 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x10 "RFIFOMPF4,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x10 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x14 "RFIFOMPF5,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x14 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x18 "RFIFOMPF6,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x18 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x1C "RFIFOMPF7,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x1C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x20 "RFIFOMPF8,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x20 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x24 "RFIFOMPF9,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x24 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x28 "RFIFOMPF10,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x28 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x2C "RFIFOMPF11,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x2C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x30 "RFIFOMPF12,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x30 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x34 "RFIFOMPF13,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x34 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x38 "RFIFOMPF14,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x38 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x3C "RFIFOMPF15,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x3C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x40 "RFIFOMPF16,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x40 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x44 "RFIFOMPF17,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x44 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x48 "RFIFOMPF18,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x48 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x4C "RFIFOMPF19,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x4C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x50 "RFIFOMPF20,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x50 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x54 "RFIFOMPF21,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x54 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x58 "RFIFOMPF22,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x58 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x5C "RFIFOMPF23,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x5C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x60 "RFIFOMPF24,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x60 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x64 "RFIFOMPF25,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x64 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x68 "RFIFOMPF26,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x68 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x6C "RFIFOMPF27,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x6C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x70 "RFIFOMPF28,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x70 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x74 "RFIFOMPF29,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x74 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x78 "RFIFOMPF30,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x78 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
line.long 0x7C "RFIFOMPF31,Receive FIFO/mailbox private filter x register"
|
|
hexmask.long 0x7C 0.--31. 1. "FMFDx,FIFO/mailbox filter data"
|
|
group.long 0xB00++0x27
|
|
line.long 0x0 "PN_CTL0,CAN_sleep mode control register 0"
|
|
bitfld.long 0x0 17. "WTOIE,Wakeup timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 16. "WMIE,Wakeup match interrupt enable" "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "NMM,Number of messages matching times"
|
|
bitfld.long 0x0 4.--5. "DATAFT,DATA field filtering type in CAN_sleep mode" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "IDFT,ID field filtering type in CAN_sleep mode" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "FFT,Frame filtering type in CAN_sleep mode" "0,1,2,3"
|
|
line.long 0x4 "PN_TO,CAN_sleep mode timeout register"
|
|
hexmask.long.word 0x4 0.--15. 1. "WTO,Wakeup timeout"
|
|
line.long 0x8 "PN_STAT,CAN_sleep mode status register"
|
|
bitfld.long 0x8 17. "WTOS,Wakeup timeout flag status" "0,1"
|
|
bitfld.long 0x8 16. "WMS,Wakeup match flag status" "0,1"
|
|
hexmask.long.byte 0x8 8.--15. 1. "MMCNT,Matching message counter in CAN_sleep mode"
|
|
rbitfld.long 0x8 7. "MMCNTS,Matching message counter state" "0,1"
|
|
line.long 0xC "PN_EID0,CAN_sleep mode expected identifier 0 register"
|
|
bitfld.long 0xC 30. "EIDE,Expected IDE in CAN_sleep mode" "0,1"
|
|
bitfld.long 0xC 29. "ERTR,Expected RTR in CAN_sleep mode" "0,1"
|
|
hexmask.long 0xC 0.--28. 1. "EIDF_ELT,Expected ID field / expected ID low threshold in CAN_sleep mode"
|
|
line.long 0x10 "PN_EDLC,CAN_sleep mode expected DLC register"
|
|
hexmask.long.byte 0x10 16.--19. 1. "DLCELT,DLC expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x10 0.--3. 1. "DLCEHT,DLC expected high threshold in CAN_sleep mode"
|
|
line.long 0x14 "PN_EDL0,CAN_sleep mode expected data low 0 register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DB0ELT,Data byte 0 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x14 16.--23. 1. "DB1ELT,Data byte 1 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DB2ELT,Data byte 2 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DB3ELT,Data byte 3 expected low threshold in CAN_sleep mode"
|
|
line.long 0x18 "PN_EDL1,CAN_sleep mode expected data low 1 register"
|
|
hexmask.long.byte 0x18 24.--31. 1. "DB4ELT,Data byte 4 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x18 16.--23. 1. "DB5ELT,Data byte 5 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x18 8.--15. 1. "DB6ELT,Data byte 6 expected low threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x18 0.--7. 1. "DB7ELT,Data byte 7 expected low threshold in CAN_sleep mode"
|
|
line.long 0x1C "IFEID1,CAN_sleep mode identifier filter / expected identifier 1 register"
|
|
bitfld.long 0x1C 30. "IDEFD,IDE filter data in CAN_sleep mode" "0,1"
|
|
bitfld.long 0x1C 29. "RTRFD,RTR filter data in CAN_sleep mode" "0,1"
|
|
hexmask.long 0x1C 0.--28. 1. "IDFD_EHT,ID filter data / ID expected high threshold in CAN_sleep mode"
|
|
line.long 0x20 "PN_DF0EDH0,CAN_sleep mode data 0 filter / expected data high 0 register"
|
|
hexmask.long.byte 0x20 24.--31. 1. "DB0FD_EHT,Data byte 0 filter data / Data byte 0 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x20 16.--23. 1. "DB1FD_EHT,Data byte 1 filter data / Data byte 1 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x20 8.--15. 1. "DB2FD_EHT,Data byte 3 filter data / Data byte 3 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x20 0.--7. 1. "DB3FD_EHT,Data byte 3 filter data / Data byte 3 expected high threshold in CAN_sleep mode"
|
|
line.long 0x24 "PN_DF1EDH1,CAN_sleep mode data 1 filter / expected data high 1 register"
|
|
hexmask.long.byte 0x24 24.--31. 1. "DB4FD_EHT,Data byte 4 filter data / Data byte 4 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x24 16.--23. 1. "DB5FD_EHT,Data byte 5 filter data / Data byte 5 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x24 8.--15. 1. "DB6FD_EHT,Data byte 6 filter data / Data byte 6 expected high threshold in CAN_sleep mode"
|
|
hexmask.long.byte 0x24 0.--7. 1. "DB7FD_EHT,Data byte 7 filter data / Data byte 7 expected high threshold in CAN_sleep mode"
|
|
rgroup.long 0xB40++0x3
|
|
line.long 0x0 "RWM0CS,CAN_sleep mode received wakeup mailbox x control status information register"
|
|
bitfld.long 0x0 22. "RSRR,Received SRR bit" "0,1"
|
|
bitfld.long 0x0 21. "RIDE,Received IDE bit" "0,1"
|
|
bitfld.long 0x0 20. "RRTR,Received RTR bit" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "RDLC,Received DLC bits"
|
|
rgroup.long 0xB50++0x3
|
|
line.long 0x0 "RWM1CS,CAN_sleep mode received wakeup mailbox x control status information register"
|
|
bitfld.long 0x0 22. "RSRR,Received SRR bit" "0,1"
|
|
bitfld.long 0x0 21. "RIDE,Received IDE bit" "0,1"
|
|
bitfld.long 0x0 20. "RRTR,Received RTR bit" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "RDLC,Received DLC bits"
|
|
rgroup.long 0xB60++0x3
|
|
line.long 0x0 "RWM2CS,CAN_sleep mode received wakeup mailbox x control status information register"
|
|
bitfld.long 0x0 22. "RSRR,Received SRR bit" "0,1"
|
|
bitfld.long 0x0 21. "RIDE,Received IDE bit" "0,1"
|
|
bitfld.long 0x0 20. "RRTR,Received RTR bit" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "RDLC,Received DLC bits"
|
|
rgroup.long 0xB70++0x3
|
|
line.long 0x0 "RWM3CS,CAN_sleep mode received wakeup mailbox x control status information register"
|
|
bitfld.long 0x0 22. "RSRR,Received SRR bit" "0,1"
|
|
bitfld.long 0x0 21. "RIDE,Received IDE bit" "0,1"
|
|
bitfld.long 0x0 20. "RRTR,Received RTR bit" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "RDLC,Received DLC bits"
|
|
rgroup.long 0xB44++0x3
|
|
line.long 0x0 "PN_RWM0I,CAN_sleep mode received wakeup mailbox x identifier register"
|
|
hexmask.long 0x0 0.--28. 1. "RID,Received ID bits"
|
|
rgroup.long 0xB54++0x3
|
|
line.long 0x0 "PN_RWM1I,CAN_sleep mode received wakeup mailbox x identifier register"
|
|
hexmask.long 0x0 0.--28. 1. "RID,Received ID bits"
|
|
rgroup.long 0xB64++0x3
|
|
line.long 0x0 "PN_RWM2I,CAN_sleep mode received wakeup mailbox x identifier register"
|
|
hexmask.long 0x0 0.--28. 1. "RID,Received ID bits"
|
|
rgroup.long 0xB74++0x3
|
|
line.long 0x0 "PN_RWM3I,CAN_sleep mode received wakeup mailbox x identifier register"
|
|
hexmask.long 0x0 0.--28. 1. "RID,Received ID bits"
|
|
rgroup.long 0xB48++0x3
|
|
line.long 0x0 "RWM0D0,CAN_sleep mode received wakeup mailbox x data 0 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB0,Received data byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB1,Received data byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB2,Received data byte 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB3,Received data byte 3"
|
|
rgroup.long 0xB58++0x3
|
|
line.long 0x0 "RWM1D0,CAN_sleep mode received wakeup mailbox x data 0 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB0,Received data byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB1,Received data byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB2,Received data byte 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB3,Received data byte 3"
|
|
rgroup.long 0xB68++0x3
|
|
line.long 0x0 "RWM2D0,CAN_sleep mode received wakeup mailbox x data 0 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB0,Received data byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB1,Received data byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB2,Received data byte 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB3,Received data byte 3"
|
|
rgroup.long 0xB78++0x3
|
|
line.long 0x0 "RWM3D0,CAN_sleep mode received wakeup mailbox x data 0 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB0,Received data byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB1,Received data byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB2,Received data byte 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB3,Received data byte 3"
|
|
rgroup.long 0xB4C++0x3
|
|
line.long 0x0 "RWM0D1,CAN_sleep mode received wakeup mailbox x data 1 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB4,Received data byte 4"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB5,Received data byte 5"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB6,Received data byte 6"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB7,Received data byte 7"
|
|
rgroup.long 0xB5C++0x3
|
|
line.long 0x0 "RWM1D1,CAN_sleep mode received wakeup mailbox x data 1 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB4,Received data byte 4"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB5,Received data byte 5"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB6,Received data byte 6"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB7,Received data byte 7"
|
|
rgroup.long 0xB6C++0x3
|
|
line.long 0x0 "RWM2D1,CAN_sleep mode received wakeup mailbox x data 1 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB4,Received data byte 4"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB5,Received data byte 5"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB6,Received data byte 6"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB7,Received data byte 7"
|
|
rgroup.long 0xB7C++0x3
|
|
line.long 0x0 "RWM3D1,CAN_sleep mode received wakeup mailbox x data 1 register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RDB4,Received data byte 4"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDB5,Received data byte 5"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RDB6,Received data byte 6"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDB7,Received data byte 7"
|
|
group.long 0xC00++0xB
|
|
line.long 0x0 "FDCTL,FD control register"
|
|
bitfld.long 0x0 31. "BRSEN,Bit rate of data switch enable" "0,1"
|
|
bitfld.long 0x0 16.--17. "MDSZ,Mailbox data size" "0,1,2,3"
|
|
bitfld.long 0x0 15. "TDCEN,Transmitter delay compensation enable" "0,1"
|
|
bitfld.long 0x0 14. "TDCS,Transmitter delay compensation status" "0,1"
|
|
hexmask.long.byte 0x0 8.--12. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TDCV,Transmitter delay compensation value"
|
|
line.long 0x4 "FDBT,FD bit timing register"
|
|
hexmask.long.word 0x4 20.--29. 1. "DBAUDPSC,Baud rate prescaler for data bit time"
|
|
bitfld.long 0x4 16.--18. "DSJW,Resynchronization jump width for data bit time" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 10.--14. 1. "DPTS,Propagation time segment for data bit time"
|
|
bitfld.long 0x4 5.--7. "DPBS1,Phase buffer segment 1 for data bit time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "DPBS2,Phase buffer segment 2 for data bit time" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CRCCFD,CRC for classical and FD frame register"
|
|
hexmask.long.byte 0x8 24.--28. 1. "ANTM,Associated number of mailbox for transmitting the CRCTCI[20:0] value"
|
|
hexmask.long.tbyte 0x8 0.--20. 1. "CRCTCI,Transmitted CRC value for classical and ISO / non-ISO FD frames"
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
tree "CAU (Cryptographic Acceleration Unit)"
|
|
base ad:0x48021000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,CAU control register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "NBPILB,Number of bytes padding in last block of payload"
|
|
bitfld.long 0x0 19. "ALGM_3,Encryption/decryption algorithm mode bit 3" "0,1"
|
|
bitfld.long 0x0 16.--17. "GCM_CCMPH,GCM CCM phase" "0,1,2,3"
|
|
bitfld.long 0x0 15. "CAUEN,Cryptographic module enable" "0,1"
|
|
bitfld.long 0x0 14. "FFLUSH,FIFO flush" "0,1"
|
|
bitfld.long 0x0 8.--9. "KEYM,AES key size mode configuration" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "DATAM,Data swapping type mode configuration" "0,1,2,3"
|
|
bitfld.long 0x0 3.--5. "ALGM,Encryption/decryption algorithm mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "CAUDIR,CAU direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "KEY_SEL,Key select" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STAT0,CAU status register 0"
|
|
bitfld.long 0x0 4. "BUSY,BUSY flag" "0,1"
|
|
bitfld.long 0x0 3. "OFU,OUT FIFO full flag" "0,1"
|
|
bitfld.long 0x0 2. "ONE,OUT FIFO not empty flag" "0,1"
|
|
bitfld.long 0x0 1. "INF,IN FIFO not full flag" "0,1"
|
|
bitfld.long 0x0 0. "IEM,IN FIFO empty flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "DI,CAU data input register"
|
|
hexmask.long 0x0 0.--31. 1. "DI,Data input"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "DO,CAU data output register"
|
|
hexmask.long 0x0 0.--31. 1. "DO,Data output"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "DMAEN,CAU DMA enable register"
|
|
bitfld.long 0x0 1. "DMAOEN,Out FIFO DMA enable" "0,1"
|
|
bitfld.long 0x0 0. "DMAIEN,In FIFO DMA enable" "0,1"
|
|
line.long 0x4 "INTEN,CAU interrupt enable register"
|
|
bitfld.long 0x4 1. "OINTEN,Out FIFO interrupt enable" "0,1"
|
|
bitfld.long 0x4 0. "IINTEN,In FIFO interrupt enable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "STAT1,CAU interrupt status flag register 1"
|
|
bitfld.long 0x0 1. "OSTA,Out FIFO interrupt flag" "0,1"
|
|
bitfld.long 0x0 0. "ISTA,In FIFO interrupt flag" "0,1"
|
|
line.long 0x4 "INTF,CAU enable interrupt status flag register"
|
|
bitfld.long 0x4 1. "OINTF,Out FIFO enabled interrupt flag" "0,1"
|
|
bitfld.long 0x4 0. "IINTF,In FIFO enabled interrupt flag" "0,1"
|
|
wgroup.long 0x20++0x1F
|
|
line.long 0x0 "KEY0H,CAU key register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY0H,Key for DES TDES AES"
|
|
line.long 0x4 "KEY0L,CAU key register"
|
|
hexmask.long 0x4 0.--31. 1. "KEY0L,Key for DES TDES AES"
|
|
line.long 0x8 "KEY1H,CAU key register"
|
|
hexmask.long 0x8 0.--31. 1. "KEY1H,Key for DES TDES AES"
|
|
line.long 0xC "KEY1L,CAU key register"
|
|
hexmask.long 0xC 0.--31. 1. "KEY1L,Key for DES TDES AES"
|
|
line.long 0x10 "KEY2H,CAU key register"
|
|
hexmask.long 0x10 0.--31. 1. "KEY2H,Key for DES TDES AES"
|
|
line.long 0x14 "KEY2L,CAU key register"
|
|
hexmask.long 0x14 0.--31. 1. "KEY2L,Key for DES TDES AES"
|
|
line.long 0x18 "KEY3H,CAU key register"
|
|
hexmask.long 0x18 0.--31. 1. "KEY3H,Key for DES TDES AES"
|
|
line.long 0x1C "KEY3L,CAU key register"
|
|
hexmask.long 0x1C 0.--31. 1. "KEY3L,Key for DES TDES AES"
|
|
group.long 0x40++0x4F
|
|
line.long 0x0 "IV0H,CAU initialization register"
|
|
hexmask.long 0x0 0.--31. 1. "IV0H,The initialization vector for DES TDES AES"
|
|
line.long 0x4 "IV0L,CAU initialization register"
|
|
hexmask.long 0x4 0.--31. 1. "IV0L,The initialization vector for DES TDES AES"
|
|
line.long 0x8 "IV1H,CAU initialization register"
|
|
hexmask.long 0x8 0.--31. 1. "IV1H,The initialization vector for DES TDES AES"
|
|
line.long 0xC "IV1L,CAU initialization register"
|
|
hexmask.long 0xC 0.--31. 1. "IV1L,The initialization vector for DES TDES AES"
|
|
line.long 0x10 "GCMCCMCTXS0,GCM or CCM mode context switch register 0"
|
|
hexmask.long 0x10 0.--31. 1. "CTX0,The internal status of the CAU core"
|
|
line.long 0x14 "GCMCCMCTXS1,GCM or CCM mode context switch register 1"
|
|
hexmask.long 0x14 0.--31. 1. "CTX1,The internal status of the CAU core"
|
|
line.long 0x18 "GCMCCMCTXS2,GCM or CCM mode context switch register 2"
|
|
hexmask.long 0x18 0.--31. 1. "CTX2,The internal status of the CAU core"
|
|
line.long 0x1C "GCMCCMCTXS3,GCM or CCM mode context switch register 3"
|
|
hexmask.long 0x1C 0.--31. 1. "CTX3,The internal status of the CAU core"
|
|
line.long 0x20 "GCMCCMCTXS4,GCM or CCM mode context switch register 4"
|
|
hexmask.long 0x20 0.--31. 1. "CTX4,The internal status of the CAU core"
|
|
line.long 0x24 "GCMCCMCTXS5,GCM or CCM mode context switch register 5"
|
|
hexmask.long 0x24 0.--31. 1. "CTX5,The internal status of the CAU core"
|
|
line.long 0x28 "GCMCCMCTXS6,GCM or CCM mode context switch register 6"
|
|
hexmask.long 0x28 0.--31. 1. "CTX6,The internal status of the CAU core"
|
|
line.long 0x2C "GCMCCMCTXS7,GCM or CCM mode context switch register 7"
|
|
hexmask.long 0x2C 0.--31. 1. "CTX7,The internal status of the CAU core"
|
|
line.long 0x30 "GCMCTXS0,GCM mode context switch register 0"
|
|
hexmask.long 0x30 0.--31. 1. "CTX0,The internal status of the CAU core"
|
|
line.long 0x34 "GCMCTXS1,GCM mode context switch register 1"
|
|
hexmask.long 0x34 0.--31. 1. "CTX1,The internal status of the CAU core"
|
|
line.long 0x38 "GCMCTXS2,GCM mode context switch register 2"
|
|
hexmask.long 0x38 0.--31. 1. "CTX2,The internal status of the CAU core"
|
|
line.long 0x3C "GCMCTXS3,GCM mode context switch register 3"
|
|
hexmask.long 0x3C 0.--31. 1. "CTX3,The internal status of the CAU core"
|
|
line.long 0x40 "GCMCTXS4,GCM mode context switch register 4"
|
|
hexmask.long 0x40 0.--31. 1. "CTX4,The internal status of the CAU core"
|
|
line.long 0x44 "GCMCTXS5,GCM mode context switch register 5"
|
|
hexmask.long 0x44 0.--31. 1. "CTX5,The internal status of the CAU core"
|
|
line.long 0x48 "GCMCTXS6,GCM mode context switch register 6"
|
|
hexmask.long 0x48 0.--31. 1. "CTX6,The internal status of the CAU core"
|
|
line.long 0x4C "GCMCTXS7,GCM mode context switch register 7"
|
|
hexmask.long 0x4C 0.--31. 1. "CTX7,The internal status of the CAU core"
|
|
tree.end
|
|
endif
|
|
tree "CMP (Comparator)"
|
|
base ad:0x58003800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "STAT,Status register"
|
|
bitfld.long 0x0 17. "CMP1IF,CMP1 interrupt flag" "0,1"
|
|
bitfld.long 0x0 16. "CMP0IF,CMP0 interrupt flag" "0,1"
|
|
rbitfld.long 0x0 1. "CMP1O,CMP1 output" "0,1"
|
|
rbitfld.long 0x0 0. "CMP0O,CMP0 output" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "IFC,Interrupt flag clear register"
|
|
bitfld.long 0x0 17. "CMP1IC,CMP1 interrupt flag clear" "0,1"
|
|
bitfld.long 0x0 16. "CMP0IC,CMP0 interrupt flag clear" "0,1"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "SR,Alternate select register"
|
|
hexmask.long.word 0x0 0.--10. 1. "AFSE,CMP alternate function of output ports select"
|
|
line.long 0x4 "CMP0_CS,CMP0 Control/status register"
|
|
bitfld.long 0x4 31. "CMP0LK,CMP0 lock" "0,1"
|
|
hexmask.long.byte 0x4 24.--27. 1. "CMP0BLK,CMP0 output blanking source"
|
|
bitfld.long 0x4 20. "CMP0PSEL,CMP0_IP input selection" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x4 16.--18. "CMP0MISEL,CMP0_IM internal input selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x4 16.--18. "CMP0MSEL,CMP0_IM internal input selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
bitfld.long 0x4 12.--13. "CMP0M,CMP0 mode" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "CMP0HST,CMP0 hysteresis" "0,1,2,3"
|
|
bitfld.long 0x4 6. "CMP0INTEN,CMP0 interrupt enable" "0,1"
|
|
bitfld.long 0x4 3. "CMP0PL,Polarity of CMP0 output" "0,1"
|
|
bitfld.long 0x4 2. "CMP0SEN,Voltage scaler enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CMP0BEN,Scaler bridge enable bit" "0,1"
|
|
bitfld.long 0x4 0. "CMP0EN,CMP0 enable" "0,1"
|
|
line.long 0x8 "CMP1_CS,CMP1 Control/status register"
|
|
bitfld.long 0x8 31. "CMP1LK,CMP1 lock" "0,1"
|
|
hexmask.long.byte 0x8 24.--27. 1. "CMP1BLK,CMP1 output blanking source"
|
|
bitfld.long 0x8 20. "CMP1PSEL,CMP1_IP input selection" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x8 16.--18. "CMP1MISEL,CMP1_IM internal input selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x8 16.--18. "CMP1MSEL,CMP1_IM internal input selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
bitfld.long 0x8 12.--13. "CMP1M,CMP1 mode" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "CMP1HST,CMP1 hysteresis" "0,1,2,3"
|
|
bitfld.long 0x8 6. "CMP1INTEN,CMP1 interrupt enable" "0,1"
|
|
bitfld.long 0x8 4. "WNDEN,Window mode enable" "0,1"
|
|
bitfld.long 0x8 3. "CMP1PL,Polarity of CMP1 output" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "CMP1SEN,Voltage scaler enable bit" "0,1"
|
|
bitfld.long 0x8 1. "CMP1BEN,Scaler bridge enable bit" "0,1"
|
|
bitfld.long 0x8 0. "CMP1EN,CMP1 enable" "0,1"
|
|
tree.end
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
tree "CPDM (Clock Phase Delay Module)"
|
|
base ad:0x0
|
|
tree "CPDM_SDIO0"
|
|
base ad:0x52008000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 1. "DLSEN,CPDM delay line sample module enable bit" "0,1"
|
|
bitfld.long 0x0 0. "CPDMEN,CPDM enable bit" "0,1"
|
|
line.long 0x4 "CFG,Configuration register"
|
|
rbitfld.long 0x4 31. "DLLENF,Valid mark of delay line length" "0,1"
|
|
hexmask.long.word 0x4 16.--27. 1. "DLLEN,Delay line length"
|
|
hexmask.long.byte 0x4 8.--14. 1. "DLSTCNT,Defines a delay step count for a unit delay UNIT"
|
|
hexmask.long.byte 0x4 0.--3. 1. "CPSEL,Select the phase of the output clock"
|
|
tree.end
|
|
tree "CPDM_SDIO1"
|
|
base ad:0x48022800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 1. "DLSEN,CPDM delay line sample module enable bit" "0,1"
|
|
bitfld.long 0x0 0. "CPDMEN,CPDM enable bit" "0,1"
|
|
line.long 0x4 "CFG,Configuration register"
|
|
rbitfld.long 0x4 31. "DLLENF,Valid mark of delay line length" "0,1"
|
|
hexmask.long.word 0x4 16.--27. 1. "DLLEN,Delay line length"
|
|
hexmask.long.byte 0x4 8.--14. 1. "DLSTCNT,Defines a delay step count for a unit delay UNIT"
|
|
hexmask.long.byte 0x4 0.--3. 1. "CPSEL,Select the phase of the output clock"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "CRC (Cyclic Redundancy Checks Management Unit)"
|
|
base ad:0x58024C00
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "DATA,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,CRC calculation result bits"
|
|
line.long 0x4 "FDATA,Free data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "FDATA,Free data register bits"
|
|
line.long 0x8 "CTL,Control register"
|
|
bitfld.long 0x8 7. "REV_O,Reverse output data value in bit order" "0,1"
|
|
bitfld.long 0x8 5.--6. "REV_I,Reverse type for input date" "0,1,2,3"
|
|
bitfld.long 0x8 3.--4. "PS,Size of polynomial" "0,1,2,3"
|
|
bitfld.long 0x8 0. "RST,Software writes and reads" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "IDATA,Initialization data register"
|
|
hexmask.long 0x0 0.--31. 1. "IDATA,Configurable initial CRC data value"
|
|
line.long 0x4 "POLY,Polynomial register"
|
|
hexmask.long 0x4 0.--31. 1. "POLY,User configurable polynomial value"
|
|
tree.end
|
|
tree "CTC (Clock Trim Controller)"
|
|
base ad:0x40008400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
hexmask.long.byte 0x0 8.--13. 1. "TRIMVALUE,IRC48M trim value"
|
|
bitfld.long 0x0 7. "SWREFPUL,Software reference source sync pulse" "0,1"
|
|
bitfld.long 0x0 6. "AUTOTRIM,Hardware automatically trim mode" "0,1"
|
|
bitfld.long 0x0 5. "CNTEN,CTC counter enable" "0,1"
|
|
bitfld.long 0x0 3. "EREFIE,EREFIF interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "ERRIE,Error (ERRIF) interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CKWARNIE,Clock trim warning (CKWARNIF) interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CKOKIE,Clock trim OK (CKOKIF) interrupt enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 31. "REFPOL,Reference signal source polarity" "0,1"
|
|
bitfld.long 0x4 28.--29. "REFSEL,Reference signal source selection" "0,1,2,3"
|
|
bitfld.long 0x4 24.--26. "REFPSC,Reference signal source prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CKLIM,Clock trim base limit value"
|
|
hexmask.long.word 0x4 0.--15. 1. "RLVALUE,CTC counter reload value"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "STAT,Status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "REFCAP,CTC counter capture when reference sync pulse"
|
|
bitfld.long 0x0 15. "REFDIR,CTC trim counter direction when reference sync pulse" "0,1"
|
|
bitfld.long 0x0 10. "TRIMERR,Trim value error bit" "0,1"
|
|
bitfld.long 0x0 9. "REFMISS,Reference sync pulse miss" "0,1"
|
|
bitfld.long 0x0 8. "CKERR,Clock trim error bit" "0,1"
|
|
bitfld.long 0x0 3. "EREFIF,Expect reference interrupt flag" "0,1"
|
|
bitfld.long 0x0 2. "ERRIF,Error interrupt flag" "0,1"
|
|
bitfld.long 0x0 1. "CKWARNIF,Clock trim warning interrupt flag" "0,1"
|
|
bitfld.long 0x0 0. "CKOKIF,Clock trim OK interrupt flag" "0,1"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "INTC,Interrupt clear register"
|
|
bitfld.long 0x0 3. "EREFIC,EREFIF interrupt clear bit" "0,1"
|
|
bitfld.long 0x0 2. "ERRIC,ERRIF interrupt clear bit" "0,1"
|
|
bitfld.long 0x0 1. "CKWARNIC,CKWARNIF interrupt clear bit" "0,1"
|
|
bitfld.long 0x0 0. "CKOKIC,CKOKIF interrupt clear bit" "0,1"
|
|
tree.end
|
|
tree "DAC (Digital-to-Analog Converter)"
|
|
base ad:0x40007400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 30. "CALEN1,DAC_OUT1 calibration enable" "0,1"
|
|
bitfld.long 0x0 29. "DDUDRIE1,DAC_OUT1 DMA underrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 28. "DDMAEN1,DAC_OUT1 DMA enable" "0,1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DWBW1,DAC_OUT1 noise wave bit width"
|
|
bitfld.long 0x0 22.--23. "DWM1,DAC_OUT1 noise wave mode" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "DTSEL1,DAC_OUT1 trigger selection" "0,1,2,3"
|
|
bitfld.long 0x0 17. "DTEN1,DAC_OUT1 trigger enable" "0,1"
|
|
bitfld.long 0x0 16. "DEN1,DAC_OUT1 enable" "0,1"
|
|
bitfld.long 0x0 14. "CALEN0,DAC_OUT0 calibration enable" "0,1"
|
|
bitfld.long 0x0 13. "DDUDRIE0,DAC_OUT0 DMA underrun interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "DDMAEN0,DAC_OUT0 DMA enable" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DWBW0,DAC_OUT0 noise wave bit width"
|
|
bitfld.long 0x0 6.--7. "DWM0,DAC_OUT0 noise wave mode" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "DTSEL0,DAC_OUT0 trigger selection" "0,1,2,3"
|
|
bitfld.long 0x0 1. "DTEN0,DAC_OUT0 trigger enable" "0,1"
|
|
bitfld.long 0x0 0. "DEN0,DAC_OUT0 enable" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "SWT,Software trigger register"
|
|
bitfld.long 0x0 1. "SWTR1,DAC_OUT1 software trigger cleared by hardware" "0,1"
|
|
bitfld.long 0x0 0. "SWTR0,DAC_OUT0 software trigger cleared by hardware" "0,1"
|
|
group.long 0x8++0x23
|
|
line.long 0x0 "OUT0_R12DH,DAC_OUT0 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x0 0.--11. 1. "OUT0_DH,DAC_OUT0 12-bit right-aligned data"
|
|
line.long 0x4 "OUT0_L12DH,DAC_OUT0 12-bit left-aligned data holding register"
|
|
hexmask.long.word 0x4 4.--15. 1. "OUT0_DH,DAC_OUT0 12-bit left-aligned data"
|
|
line.long 0x8 "OUT0_R8DH,DAC_OUT0 8-bit right-aligned data holding register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "OUT0_DH,DAC_OUT0 8-bit right-aligned data"
|
|
line.long 0xC "OUT1_R12DH,DAC_OUT1 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0xC 0.--11. 1. "OUT1_DH,DAC_OUT1 12-bit right-aligned data"
|
|
line.long 0x10 "OUT1_L12DH,DAC_OUT1 12-bit left-aligned data holding register"
|
|
hexmask.long.word 0x10 4.--15. 1. "OUT1_DH,OUT1_DH[11:0]"
|
|
line.long 0x14 "OUT1_R8DH,DAC_OUT1 8-bit right-aligned data holding register"
|
|
hexmask.long.byte 0x14 0.--7. 1. "OUT1_DH,DAC_OUT1 8-bit right-aligned data"
|
|
line.long 0x18 "DACC_R12DH,DAC concurrent mode 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x18 16.--27. 1. "OUT1_DH,DAC_OUT1 12-bit right-aligned data"
|
|
hexmask.long.word 0x18 0.--11. 1. "OUT0_DH,DAC_OUT0 12-bit right-aligned data"
|
|
line.long 0x1C "DACC_L12DH,DAC concurrent mode 12-bit left-aligned data holding register"
|
|
hexmask.long.word 0x1C 20.--31. 1. "OUT1_DH,DAC_OUT1 12-bit left-aligned data"
|
|
hexmask.long.word 0x1C 4.--15. 1. "OUT0_DH,DAC_OUT0 12-bit left-aligned data"
|
|
line.long 0x20 "DACC_R8DH,DAC concurrent mode 8-bit right-aligned data holding register"
|
|
hexmask.long.byte 0x20 8.--15. 1. "OUT1_DH,DAC_OUT1 8-bit right-aligned data"
|
|
hexmask.long.byte 0x20 0.--7. 1. "OUT0_DH,DAC_OUT0 8-bit right-aligned data"
|
|
rgroup.long 0x2C++0xB
|
|
line.long 0x0 "OUT0_DO,DAC_OUT0 data output register"
|
|
hexmask.long.word 0x0 0.--11. 1. "OUT0_DO,DAC_OUT0 data output"
|
|
line.long 0x4 "OUT1_DO,DAC_OUT1 data output register"
|
|
hexmask.long.word 0x4 0.--11. 1. "OUT1_DO,DAC_OUT1 data output"
|
|
line.long 0x8 "STAT0,DAC Status register 0"
|
|
bitfld.long 0x8 31. "BWT1,This bit will be set after sample and keep mode enable" "0,1"
|
|
bitfld.long 0x8 30. "CALF1,DAC_OUT1 calibration offset flag" "0,1"
|
|
bitfld.long 0x8 29. "DDUDR1,DAC_OUT1 DMA underrun flag set by hardware cleared by software write 1" "0,1"
|
|
bitfld.long 0x8 15. "BWT0,This bit will be set after sample and keep mode enable" "0,1"
|
|
bitfld.long 0x8 14. "CALF0,DAC_OUT0 calibration offset flag" "0,1"
|
|
bitfld.long 0x8 13. "DDUDR0,DAC_OUT0 DMA underrun flag set by hardware cleared by software write 1" "0,1"
|
|
group.long 0x38++0x17
|
|
line.long 0x0 "CALR,DAC calibration Register 1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "OTV1,DAC_OUT1 offset calibration value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "OTV0,DAC_OUT0 offset calibration value"
|
|
line.long 0x4 "MDCR,DAC mode control Register 1"
|
|
bitfld.long 0x4 16.--18. "MODE1,DAC OUT1 mode." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "MODE0,DAC OUT0 mode." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "SKSTR0,DAC sample and keep sample time Register 0"
|
|
hexmask.long.word 0x8 0.--9. 1. "TSAMP0,DAC_OUT0 sample time."
|
|
line.long 0xC "SKSTR1,DAC sample and keep sample time Register 1"
|
|
hexmask.long.word 0xC 0.--9. 1. "TSAMP1,DAC_OUT refresh time (only valid in Sample and hold mode)"
|
|
line.long 0x10 "SKKTR,DAC sample and keep keep time Register"
|
|
hexmask.long.word 0x10 16.--25. 1. "TKEEP1,DAC_OUT1 keep time"
|
|
hexmask.long.word 0x10 0.--9. 1. "TKEEP0,DAC_OUT0 keep time"
|
|
line.long 0x14 "SKRTR,DAC sample and keep refresh time Register"
|
|
hexmask.long.byte 0x14 16.--23. 1. "TREF1,DAC_OUT1 refresh time"
|
|
hexmask.long.byte 0x14 0.--7. 1. "TREF0,DAC_OUT0 refresh time"
|
|
tree.end
|
|
tree "DBG (Debug)"
|
|
base ad:0xE00E1000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ID,ID code register"
|
|
hexmask.long 0x0 0.--31. 1. "ID_CODE,DBG ID code register"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CTL0,Control register0"
|
|
bitfld.long 0x0 20. "TRACECLKEN,Trace port clock enable" "0,1"
|
|
bitfld.long 0x0 18.--19. "TRACE_MODE,Trace pin allocation mode" "0,1,2,3"
|
|
bitfld.long 0x0 2. "STB_HOLD,Standby mode hold bit" "0,1"
|
|
bitfld.long 0x0 1. "DSLP_HOLD,Deep-sleep mode hold bit" "0,1"
|
|
bitfld.long 0x0 0. "SLP_HOLD,Sleep mode hold bit" "0,1"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "CTL1,Control register1"
|
|
bitfld.long 0x0 6. "WWDGT_HOLD,WWDGT hold bit" "0,1"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "CTL2,Control register2"
|
|
bitfld.long 0x0 24. "I2C3_HOLD,I2C3 hold bit" "0,1"
|
|
bitfld.long 0x0 23. "I2C2_HOLD,I2C2 hold bit" "0,1"
|
|
bitfld.long 0x0 22. "I2C1_HOLD,I2C1 hold bit" "0,1"
|
|
bitfld.long 0x0 21. "I2C0_HOLD,I2C0 hold bit" "0,1"
|
|
bitfld.long 0x0 11. "TIMER51_HOLD,TIMER51 hold bit" "0,1"
|
|
bitfld.long 0x0 10. "TIMER50_HOLD,TIMER50 hold bit" "0,1"
|
|
newline
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x0 9. "TIMER31_HOLD,TIMER31 hold bit" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x0 8. "TIMER30_HOLD,TIMER30 hold bit" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 7. "TIMER23_HOLD,TIMER23 hold bit" "0,1"
|
|
bitfld.long 0x0 6. "TIMER22_HOLD,TIMER22 hold bit" "0,1"
|
|
bitfld.long 0x0 5. "TIMER6_HOLD,TIMER6 hold bit" "0,1"
|
|
bitfld.long 0x0 4. "TIMER5_HOLD,TIMER5 hold bit" "0,1"
|
|
bitfld.long 0x0 3. "TIMER4_HOLD,TIMER4 hold bit" "0,1"
|
|
bitfld.long 0x0 2. "TIMER3_HOLD,TIMER3 hold bit" "0,1"
|
|
bitfld.long 0x0 1. "TIMER2_HOLD,TIMER2 hold bit" "0,1"
|
|
bitfld.long 0x0 0. "TIMER1_HOLD,TIMER1 hold bit" "0,1"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "CTL3,Control register3"
|
|
bitfld.long 0x0 23. "TIMER44_HOLD,TIMER44 hold bit" "0,1"
|
|
bitfld.long 0x0 22. "TIMER43_HOLD,TIMER43 hold bit" "0,1"
|
|
bitfld.long 0x0 21. "TIMER42_HOLD,TIMER42 hold bit" "0,1"
|
|
bitfld.long 0x0 20. "TIMER41_HOLD,TIMER41 hold bit" "0,1"
|
|
bitfld.long 0x0 19. "TIMER40_HOLD,TIMER40 hold bit" "0,1"
|
|
bitfld.long 0x0 18. "TIMER16_HOLD,TIMER16 hold bit" "0,1"
|
|
bitfld.long 0x0 17. "TIMER15_HOLD,TIMER15 hold bit" "0,1"
|
|
bitfld.long 0x0 16. "TIMER14_HOLD,TIMER14 hold bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CAN2_HOLD,CAN2 hold bit" "0,1"
|
|
bitfld.long 0x0 3. "CAN1_HOLD,CAN1 hold bit" "0,1"
|
|
bitfld.long 0x0 2. "CAN0_HOLD,CAN0 hold bit" "0,1"
|
|
bitfld.long 0x0 1. "TIMER7_HOLD,TIMER7 hold bit" "0,1"
|
|
bitfld.long 0x0 0. "TIMER0_HOLD,TIMER0 hold bit" "0,1"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "CTL4,Control register4"
|
|
bitfld.long 0x0 18. "FWDGT_HOLD,FWDGT hold bit" "0,1"
|
|
bitfld.long 0x0 16. "RTC_HOLD,RTC hold bit" "0,1"
|
|
tree.end
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
tree "DCI (Digital Camera Interface)"
|
|
base ad:0x48020000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 16. "EVSEN,External vsync enable" "0,1"
|
|
bitfld.long 0x0 15. "AECEN,Automatic error correction enable" "0,1"
|
|
bitfld.long 0x0 14. "DCIEN,DCI Enable" "0,1"
|
|
bitfld.long 0x0 13. "CCMOD,CCIR mode select" "0,1"
|
|
bitfld.long 0x0 12. "CCEN,CCIR enable" "0,1"
|
|
bitfld.long 0x0 10.--11. "DCIF,Digital camera interface format" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "FR,Frame rate" "0,1,2,3"
|
|
bitfld.long 0x0 7. "VPS,Vertical Polarity Selection" "0,1"
|
|
bitfld.long 0x0 6. "HPS,Horizontal Polarity Selection" "0,1"
|
|
bitfld.long 0x0 5. "CKS,Clock Polarity Selection" "0,1"
|
|
bitfld.long 0x0 4. "ESM,Embedded Synchronous Mode" "0,1"
|
|
bitfld.long 0x0 3. "JM,JPEG mode" "0,1"
|
|
bitfld.long 0x0 2. "WDEN,Window Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SNAP,Snapshot mode" "0,1"
|
|
bitfld.long 0x0 0. "CAP,Capture Enable" "0,1"
|
|
rgroup.long 0x4++0x7
|
|
line.long 0x0 "STAT0,Status register 0"
|
|
bitfld.long 0x0 2. "FV,FIFO Valid" "0,1"
|
|
bitfld.long 0x0 1. "VS,VS line status" "0,1"
|
|
bitfld.long 0x0 0. "HS,HS line status" "0,1"
|
|
line.long 0x4 "STAT1,Status register 1"
|
|
bitfld.long 0x4 8. "CCEF,CCIR error flag" "0,1"
|
|
bitfld.long 0x4 7. "COFF,CCIR change of field flag" "0,1"
|
|
bitfld.long 0x4 6. "F1F,CCIR field 1" "0,1"
|
|
bitfld.long 0x4 5. "F0F,CCIR field 0" "0,1"
|
|
bitfld.long 0x4 4. "ELF,End of Line Flag" "0,1"
|
|
bitfld.long 0x4 3. "VSF,Vsync Flag" "0,1"
|
|
bitfld.long 0x4 2. "ESEF,Embedded Synchronous Error Flag" "0,1"
|
|
bitfld.long 0x4 1. "OVRF,FIFO Overrun Flag" "0,1"
|
|
bitfld.long 0x4 0. "EFF,End of Frame Flag" "0,1"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "INTEN,Interrupt enable register"
|
|
bitfld.long 0x0 8. "CCEIE,CCIR error Interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "COFIE,CCIR change of field interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "F1IE,CCIR field 1 interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "F0IE,CCIR field 0 interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "ELIE,End of Line Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "VSIE,Vsync Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "ESEIE,Embedded Synchronous Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "OVRIE,FIFO Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "EFIE,End of Frame Interrupt Enable" "0,1"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "INTF,Interrupt flag register"
|
|
bitfld.long 0x0 8. "CCEIF,CCIR error interrupt flag" "0,1"
|
|
bitfld.long 0x0 7. "COFIF,CCIR change of field interrupt flag" "0,1"
|
|
bitfld.long 0x0 6. "F1IF,CCIR field 1 interrupt flag" "0,1"
|
|
bitfld.long 0x0 5. "F0IF,CCIR field 0 interrupt flag" "0,1"
|
|
bitfld.long 0x0 4. "ELIF,End of Line Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 3. "VSIF,Vsync Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 2. "ESEIF,Embedded Synchronous Error Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 1. "OVRIF,FIFO Overrun Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 0. "EFIF,End of Frame Interrupt Flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "INTC,Interrupt flag clear register"
|
|
bitfld.long 0x0 8. "CCEFC,CCIR error flag clear" "0,1"
|
|
bitfld.long 0x0 7. "COFFC,CCIR change of field flag clear" "0,1"
|
|
bitfld.long 0x0 6. "F1FC,CCIR field 1 interrupt flag clear" "0,1"
|
|
bitfld.long 0x0 5. "F0FC,CCIR field 0 interrupt flag clear" "0,1"
|
|
bitfld.long 0x0 4. "ELFC,End of Line Flag Clear" "0,1"
|
|
bitfld.long 0x0 3. "VSFC,Vsync flag clear" "0,1"
|
|
bitfld.long 0x0 2. "ESEFC,Clear embedded synchronous Error Flag" "0,1"
|
|
bitfld.long 0x0 1. "OVRFC,Clear FIFO Overrun Flag" "0,1"
|
|
bitfld.long 0x0 0. "EFFC,Clear End of Frame Flag" "0,1"
|
|
group.long 0x18++0xF
|
|
line.long 0x0 "SC,Synchronization codes register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "FE,Frame End Code in Embedded Synchronous Mode"
|
|
hexmask.long.byte 0x0 16.--23. 1. "LE,Line End Code in Embedded Synchronous Mode"
|
|
hexmask.long.byte 0x0 8.--15. 1. "LS,Line Start Code in Embedded Synchronous Mode"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FS,Frame Start Code in Embedded Synchronous Mode"
|
|
line.long 0x4 "SCUMSK,Synchronization codes unmask register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "FEM,Frame End Code unMask Bits in Embedded Synchronous Mode"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LEM,Line End Code unMask Bits in Embedded Synchronous Mode"
|
|
hexmask.long.byte 0x4 8.--15. 1. "LSM,Line Start Code unMask Bits in Embedded Synchronous Mode"
|
|
hexmask.long.byte 0x4 0.--7. 1. "FSM,Frame Start Code unMask Bits in Embedded Synchronous Mode"
|
|
line.long 0x8 "CWSPOS,Cropping window start position register"
|
|
hexmask.long.word 0x8 16.--28. 1. "WVSP,Window Vertical Start Position"
|
|
hexmask.long.word 0x8 0.--13. 1. "WHSP,Window Horizontal Start Position"
|
|
line.long 0xC "CWSZ,Cropping window size register"
|
|
hexmask.long.word 0xC 16.--29. 1. "WVSZ,Window Vertical Size"
|
|
hexmask.long.word 0xC 0.--13. 1. "WHSZ,Window Horizontal Size"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "DATA,DATA register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DT3,Pixel Data 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DT2,Pixel Data 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DT1,Pixel Data 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DT0,Pixel Data 0"
|
|
tree.end
|
|
endif
|
|
tree "DMA (Direct Memory Access)"
|
|
base ad:0x0
|
|
tree "DMA0"
|
|
base ad:0x40020000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "INTF0,Interrupt flag register 0"
|
|
bitfld.long 0x0 27. "FTFIF3,Full Transfer finish flag of channel 3" "0,1"
|
|
bitfld.long 0x0 26. "HTFIF3,Half transfer finish flag of channel 3" "0,1"
|
|
bitfld.long 0x0 25. "TAEIF3,Transfer access error flag of channel 3" "0,1"
|
|
bitfld.long 0x0 24. "SDEIF3,Single data mode exception of channel 3" "0,1"
|
|
bitfld.long 0x0 22. "FEEIF3,FIFO error and exception of channel 3" "0,1"
|
|
bitfld.long 0x0 21. "FTFIF2,Full Transfer finish flag of channel 2" "0,1"
|
|
bitfld.long 0x0 20. "HTFIF2,Half transfer finish flag of channel 2" "0,1"
|
|
bitfld.long 0x0 19. "TAEIF2,Transfer access error flag of channel 2" "0,1"
|
|
bitfld.long 0x0 18. "SDEIF2,Single data mode exception of channel 2" "0,1"
|
|
bitfld.long 0x0 16. "FEEIF2,FIFO error and exception of channel 2" "0,1"
|
|
bitfld.long 0x0 11. "FTFIF1,Full Transfer finish flag of channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "HTFIF1,Half transfer finish flag of channel 1" "0,1"
|
|
bitfld.long 0x0 9. "TAEIF1,Transfer access error flag of channel 1" "0,1"
|
|
bitfld.long 0x0 8. "SDEIF1,Single data mode exception of channel 1" "0,1"
|
|
bitfld.long 0x0 6. "FEEIF1,FIFO error and exception of channel 1" "0,1"
|
|
bitfld.long 0x0 5. "FTFIF0,Full Transfer finish flag of channel 0" "0,1"
|
|
bitfld.long 0x0 4. "HTFIF0,Half transfer finish flag of channel 0" "0,1"
|
|
bitfld.long 0x0 3. "TAEIF0,Transfer access error flag of channel 0" "0,1"
|
|
bitfld.long 0x0 2. "SDEIF0,Single data mode exception of channel 0" "0,1"
|
|
bitfld.long 0x0 0. "FEEIF0,FIFO error and exception of channel 0" "0,1"
|
|
line.long 0x4 "INTF1,Interrupt flag register 1"
|
|
bitfld.long 0x4 27. "FTFIF7,Full Transfer finish flag of channel 7" "0,1"
|
|
bitfld.long 0x4 26. "HTFIF7,Half transfer finish flag of channel 7" "0,1"
|
|
bitfld.long 0x4 25. "TAEIF7,Transfer access error flag of channel 7" "0,1"
|
|
bitfld.long 0x4 24. "SDEIF7,Single data mode exception of channel 7" "0,1"
|
|
bitfld.long 0x4 22. "FEEIF7,FIFO error and exception of channel 7" "0,1"
|
|
bitfld.long 0x4 21. "FTFIF6,Full Transfer finish flag of channel 6" "0,1"
|
|
bitfld.long 0x4 20. "HTFIF6,Half transfer finish flag of channel 6" "0,1"
|
|
bitfld.long 0x4 19. "TAEIF6,Transfer access error flag of channel 6" "0,1"
|
|
bitfld.long 0x4 18. "SDEIF6,Single data mode exception of channel 6" "0,1"
|
|
bitfld.long 0x4 16. "FEEIF6,FIFO error and exception of channel 6" "0,1"
|
|
bitfld.long 0x4 11. "FTFIF5,Full Transfer finish flag of channel 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "HTFIF5,Half transfer finish flag of channel 5" "0,1"
|
|
bitfld.long 0x4 9. "TAEIF5,Transfer access error flag of channel 5" "0,1"
|
|
bitfld.long 0x4 8. "SDEIF5,Single data mode exception of channel 5" "0,1"
|
|
bitfld.long 0x4 6. "FEEIF5,FIFO error and exception of channel 5" "0,1"
|
|
bitfld.long 0x4 5. "FTFIF4,Full Transfer finish flag of channel 4" "0,1"
|
|
bitfld.long 0x4 4. "HTFIF4,Half transfer finish flag of channel 4" "0,1"
|
|
bitfld.long 0x4 3. "TAEIF4,Transfer access error flag of channel 4" "0,1"
|
|
bitfld.long 0x4 2. "SDEIF4,Single data mode exception of channel 4" "0,1"
|
|
bitfld.long 0x4 0. "FEEIF4,FIFO error and exception of channel 4" "0,1"
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "INTC0,Interrupt flag clear register 0"
|
|
bitfld.long 0x0 27. "FTFIFC3,Full Transfer finish flag of channel 3" "0,1"
|
|
bitfld.long 0x0 26. "HTFIFC3,Half transfer finish flag of channel 3" "0,1"
|
|
bitfld.long 0x0 25. "TAEIFC3,Transfer access error flag of channel 3" "0,1"
|
|
bitfld.long 0x0 24. "SDEIFC3,Single data mode exception of channel 3" "0,1"
|
|
bitfld.long 0x0 22. "FEEIFC3,FIFO error and exception of channel 3" "0,1"
|
|
bitfld.long 0x0 21. "FTFIFC2,Full Transfer finish flag of channel 2" "0,1"
|
|
bitfld.long 0x0 20. "HTFIFC2,Half transfer finish flag of channel 2" "0,1"
|
|
bitfld.long 0x0 19. "TAEIFC2,Transfer access error flag of channel 2" "0,1"
|
|
bitfld.long 0x0 18. "SDEIFC2,Single data mode exception of channel 2" "0,1"
|
|
bitfld.long 0x0 16. "FEEIFC2,FIFO error and exception of channel 2" "0,1"
|
|
bitfld.long 0x0 11. "FTFIFC1,Full Transfer finish flag of channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "HTFIFC1,Half transfer finish flag of channel 1" "0,1"
|
|
bitfld.long 0x0 9. "TAEIFC1,Transfer access error flag of channel 1" "0,1"
|
|
bitfld.long 0x0 8. "SDEIFC1,Single data mode exception of channel 1" "0,1"
|
|
bitfld.long 0x0 6. "FEEIFC1,FIFO error and exception of channel 1" "0,1"
|
|
bitfld.long 0x0 5. "FTFIFC0,Full Transfer finish flag of channel 0" "0,1"
|
|
bitfld.long 0x0 4. "HTFIFC0,Half transfer finish flag of channel 0" "0,1"
|
|
bitfld.long 0x0 3. "TAEIFC0,Transfer access error flag of channel 0" "0,1"
|
|
bitfld.long 0x0 2. "SDEIFC0,Single data mode exception of channel 0" "0,1"
|
|
bitfld.long 0x0 0. "FEEIFC0,FIFO error and exception of channel 0" "0,1"
|
|
line.long 0x4 "INTC1,Interrupt flag clear register 1"
|
|
bitfld.long 0x4 27. "FTFIFC7,Full Transfer finish flag of channel 7" "0,1"
|
|
bitfld.long 0x4 26. "HTFIFC7,Half transfer finish flag of channel 7" "0,1"
|
|
bitfld.long 0x4 25. "TAEIFC7,Transfer access error flag of channel 7" "0,1"
|
|
bitfld.long 0x4 24. "SDEIFC7,Single data mode exception of channel 7" "0,1"
|
|
bitfld.long 0x4 22. "FEEIFC7,FIFO error and exception of channel 7" "0,1"
|
|
bitfld.long 0x4 21. "FTFIFC6,Full Transfer finish flag of channel 6" "0,1"
|
|
bitfld.long 0x4 20. "HTFIFC6,Half transfer finish flag of channel 6" "0,1"
|
|
bitfld.long 0x4 19. "TAEIFC6,Transfer access error flag of channel 6" "0,1"
|
|
bitfld.long 0x4 18. "SDEIFC6,Single data mode exception of channel 6" "0,1"
|
|
bitfld.long 0x4 16. "FEEIFC6,FIFO error and exception of channel 6" "0,1"
|
|
bitfld.long 0x4 11. "FTFIFC5,Full Transfer finish flag of channel 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "HTFIFC5,Half transfer finish flag of channel 5" "0,1"
|
|
bitfld.long 0x4 9. "TAEIFC5,Transfer access error flag of channel 5" "0,1"
|
|
bitfld.long 0x4 8. "SDEIFC5,Single data mode exception of channel 5" "0,1"
|
|
bitfld.long 0x4 6. "FEEIFC5,FIFO error and exception of channel 5" "0,1"
|
|
bitfld.long 0x4 5. "FTFIFC4,Full Transfer finish flag of channel 4" "0,1"
|
|
bitfld.long 0x4 4. "HTFIFC4,Half transfer finish flag of channel 4" "0,1"
|
|
bitfld.long 0x4 3. "TAEIFC4,Transfer access error flag of channel 4" "0,1"
|
|
bitfld.long 0x4 2. "SDEIFC4,Single data mode exception of channel 4" "0,1"
|
|
bitfld.long 0x4 0. "FEEIFC4,FIFO error and exception of channel 4" "0,1"
|
|
group.long 0x10++0xBF
|
|
line.long 0x0 "CH0CTL,Channel 0 control regist"
|
|
bitfld.long 0x0 23.--24. "MBURST,Transfer burst type of memory" "0,1,2,3"
|
|
bitfld.long 0x0 21.--22. "PBURST,Transfer burst type of peripheral" "0,1,2,3"
|
|
bitfld.long 0x0 19. "MBS,Memory buffer select" "0,1"
|
|
bitfld.long 0x0 18. "SBMEN,Switch-buffer mode enable" "0,1"
|
|
bitfld.long 0x0 16.--17. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 15. "PAIF,Peripheral address increment fixed" "0,1"
|
|
bitfld.long 0x0 13.--14. "MWIDTH,Transfer width of memory" "0,1,2,3"
|
|
bitfld.long 0x0 11.--12. "PWIDTH,Transfer width of peripheral" "0,1,2,3"
|
|
bitfld.long 0x0 10. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x0 9. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x0 8. "CMEN,Circular mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "TM,Transfer mode" "0,1,2,3"
|
|
bitfld.long 0x0 4. "FTFIE,Enable bit for full transfer finish interrupt" "0,1"
|
|
bitfld.long 0x0 3. "HTFIE,Enable bit for half transfer finish interrupt" "0,1"
|
|
bitfld.long 0x0 2. "TAEIE,Enable bit for tranfer access error interrupt" "0,1"
|
|
bitfld.long 0x0 1. "SDEIE,Enable bit for single data mode exception interrupt" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH0CNT,Channel 0 counter regist"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,Transfer counter"
|
|
line.long 0x8 "CH0PADDR,Channel 0 peripheral base address regist"
|
|
hexmask.long 0x8 0.--31. 1. "PADDR,Peripheral base address"
|
|
line.long 0xC "CH0M0ADDR,Channel 0 memory 0 base address regist"
|
|
hexmask.long 0xC 0.--31. 1. "M0ADDR,Memory 0 base address"
|
|
line.long 0x10 "CH0M1ADDR,Channel 0 memory 1 base address regist"
|
|
hexmask.long 0x10 0.--31. 1. "M1ADDR,Memory 1 base address"
|
|
line.long 0x14 "CH0FCTL,Channel 0 FIFO control regist"
|
|
bitfld.long 0x14 7. "FEEIE,Enable bit for FIFO error and exception interrupt" "0,1"
|
|
rbitfld.long 0x14 3.--5. "FCNT,FIFO counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 2. "MDMEN,Multi-data mode enable" "0,1"
|
|
bitfld.long 0x14 0.--1. "FCCV,FIFO counter critical value" "0,1,2,3"
|
|
line.long 0x18 "CH1CTL,Channel 1 control regist"
|
|
bitfld.long 0x18 23.--24. "MBURST,Transfer burst type of memory" "0,1,2,3"
|
|
bitfld.long 0x18 21.--22. "PBURST,Transfer burst type of peripheral" "0,1,2,3"
|
|
bitfld.long 0x18 19. "MBS,Memory buffer select" "0,1"
|
|
bitfld.long 0x18 18. "SBMEN,Switch-buffer mode enable" "0,1"
|
|
bitfld.long 0x18 16.--17. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x18 15. "PAIF,Peripheral address increment fixed" "0,1"
|
|
bitfld.long 0x18 13.--14. "MWIDTH,Transfer width of memory" "0,1,2,3"
|
|
bitfld.long 0x18 11.--12. "PWIDTH,Transfer width of peripheral" "0,1,2,3"
|
|
bitfld.long 0x18 10. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x18 9. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x18 8. "CMEN,Circular mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 6.--7. "TM,Transfer mode" "0,1,2,3"
|
|
bitfld.long 0x18 4. "FTFIE,Enable bit for full transfer finish interrupt" "0,1"
|
|
bitfld.long 0x18 3. "HTFIE,Enable bit for half transfer finish interrupt" "0,1"
|
|
bitfld.long 0x18 2. "TAEIE,Enable bit for tranfer access error interrupt" "0,1"
|
|
bitfld.long 0x18 1. "SDEIE,Enable bit for single data mode exception interrupt" "0,1"
|
|
bitfld.long 0x18 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x1C "CH1CNT,Channel 1 counter regist"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CNT,Transfer counter"
|
|
line.long 0x20 "CH1PADDR,Channel 1 peripheral base address regist"
|
|
hexmask.long 0x20 0.--31. 1. "PADDR,Peripheral base address"
|
|
line.long 0x24 "CH1M0ADDR,Channel 1 memory 0 base address regist"
|
|
hexmask.long 0x24 0.--31. 1. "M0ADDR,Memory 0 base address"
|
|
line.long 0x28 "CH1M1ADDR,Channel 1 memory 1 base address regist"
|
|
hexmask.long 0x28 0.--31. 1. "M1ADDR,Memory 1 base address"
|
|
line.long 0x2C "CH1FCTL,Channel 1 FIFO control regist"
|
|
bitfld.long 0x2C 7. "FEEIE,Enable bit for FIFO error and exception interrupt" "0,1"
|
|
rbitfld.long 0x2C 3.--5. "FCNT,FIFO counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 2. "MDMEN,Multi-data mode enable" "0,1"
|
|
bitfld.long 0x2C 0.--1. "FCCV,FIFO counter critical value" "0,1,2,3"
|
|
line.long 0x30 "CH2CTL,Channel 2 control regist"
|
|
bitfld.long 0x30 23.--24. "MBURST,Transfer burst type of memory" "0,1,2,3"
|
|
bitfld.long 0x30 21.--22. "PBURST,Transfer burst type of peripheral" "0,1,2,3"
|
|
bitfld.long 0x30 19. "MBS,Memory buffer select" "0,1"
|
|
bitfld.long 0x30 18. "SBMEN,Switch-buffer mode enable" "0,1"
|
|
bitfld.long 0x30 16.--17. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x30 15. "PAIF,Peripheral address increment fixed" "0,1"
|
|
bitfld.long 0x30 13.--14. "MWIDTH,Transfer width of memory" "0,1,2,3"
|
|
bitfld.long 0x30 11.--12. "PWIDTH,Transfer width of peripheral" "0,1,2,3"
|
|
bitfld.long 0x30 10. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x30 9. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x30 8. "CMEN,Circular mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x30 6.--7. "TM,Transfer mode" "0,1,2,3"
|
|
bitfld.long 0x30 4. "FTFIE,Enable bit for full transfer finish interrupt" "0,1"
|
|
bitfld.long 0x30 3. "HTFIE,Enable bit for half transfer finish interrupt" "0,1"
|
|
bitfld.long 0x30 2. "TAEIE,Enable bit for tranfer access error interrupt" "0,1"
|
|
bitfld.long 0x30 1. "SDEIE,Enable bit for single data mode exception interrupt" "0,1"
|
|
bitfld.long 0x30 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x34 "CH2CNT,Channel 2 counter regist"
|
|
hexmask.long.word 0x34 0.--15. 1. "CNT,Transfer counter"
|
|
line.long 0x38 "CH2PADDR,Channel 2 peripheral base address regist"
|
|
hexmask.long 0x38 0.--31. 1. "PADDR,Peripheral base address"
|
|
line.long 0x3C "CH2M0ADDR,Channel 2 memory 0 base address regist"
|
|
hexmask.long 0x3C 0.--31. 1. "M0ADDR,Memory 0 base address"
|
|
line.long 0x40 "CH2M1ADDR,Channel 2 memory 1 base address regist"
|
|
hexmask.long 0x40 0.--31. 1. "M1ADDR,Memory 1 base address"
|
|
line.long 0x44 "CH2FCTL,Channel 2 FIFO control regist"
|
|
bitfld.long 0x44 7. "FEEIE,Enable bit for FIFO error and exception interrupt" "0,1"
|
|
rbitfld.long 0x44 3.--5. "FCNT,FIFO counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x44 2. "MDMEN,Multi-data mode enable" "0,1"
|
|
bitfld.long 0x44 0.--1. "FCCV,FIFO counter critical value" "0,1,2,3"
|
|
line.long 0x48 "CH3CTL,Channel 3 control regist"
|
|
bitfld.long 0x48 23.--24. "MBURST,Transfer burst type of memory" "0,1,2,3"
|
|
bitfld.long 0x48 21.--22. "PBURST,Transfer burst type of peripheral" "0,1,2,3"
|
|
bitfld.long 0x48 19. "MBS,Memory buffer select" "0,1"
|
|
bitfld.long 0x48 18. "SBMEN,Switch-buffer mode enable" "0,1"
|
|
bitfld.long 0x48 16.--17. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x48 15. "PAIF,Peripheral address increment fixed" "0,1"
|
|
bitfld.long 0x48 13.--14. "MWIDTH,Transfer width of memory" "0,1,2,3"
|
|
bitfld.long 0x48 11.--12. "PWIDTH,Transfer width of peripheral" "0,1,2,3"
|
|
bitfld.long 0x48 10. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x48 9. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x48 8. "CMEN,Circular mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 6.--7. "TM,Transfer mode" "0,1,2,3"
|
|
bitfld.long 0x48 4. "FTFIE,Enable bit for full transfer finish interrupt" "0,1"
|
|
bitfld.long 0x48 3. "HTFIE,Enable bit for half transfer finish interrupt" "0,1"
|
|
bitfld.long 0x48 2. "TAEIE,Enable bit for tranfer access error interrupt" "0,1"
|
|
bitfld.long 0x48 1. "SDEIE,Enable bit for single data mode exception interrupt" "0,1"
|
|
bitfld.long 0x48 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4C "CH3CNT,Channel 3 counter regist"
|
|
hexmask.long.word 0x4C 0.--15. 1. "CNT,Transfer counter"
|
|
line.long 0x50 "CH3PADDR,Channel 3 peripheral base address regist"
|
|
hexmask.long 0x50 0.--31. 1. "PADDR,Peripheral base address"
|
|
line.long 0x54 "CH3M0ADDR,Channel 3 memory 0 base address regist"
|
|
hexmask.long 0x54 0.--31. 1. "M0ADDR,Memory 0 base address"
|
|
line.long 0x58 "CH3M1ADDR,Channel 3 memory 1 base address regist"
|
|
hexmask.long 0x58 0.--31. 1. "M1ADDR,Memory 1 base address"
|
|
line.long 0x5C "CH3FCTL,Channel 3 FIFO control regist"
|
|
bitfld.long 0x5C 7. "FEEIE,Enable bit for FIFO error and exception interrupt" "0,1"
|
|
rbitfld.long 0x5C 3.--5. "FCNT,FIFO counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x5C 2. "MDMEN,Multi-data mode enable" "0,1"
|
|
bitfld.long 0x5C 0.--1. "FCCV,FIFO counter critical value" "0,1,2,3"
|
|
line.long 0x60 "CH4CTL,Channel 4 control regist"
|
|
bitfld.long 0x60 23.--24. "MBURST,Transfer burst type of memory" "0,1,2,3"
|
|
bitfld.long 0x60 21.--22. "PBURST,Transfer burst type of peripheral" "0,1,2,3"
|
|
bitfld.long 0x60 19. "MBS,Memory buffer select" "0,1"
|
|
bitfld.long 0x60 18. "SBMEN,Switch-buffer mode enable" "0,1"
|
|
bitfld.long 0x60 16.--17. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x60 15. "PAIF,Peripheral address increment fixed" "0,1"
|
|
bitfld.long 0x60 13.--14. "MWIDTH,Transfer width of memory" "0,1,2,3"
|
|
bitfld.long 0x60 11.--12. "PWIDTH,Transfer width of peripheral" "0,1,2,3"
|
|
bitfld.long 0x60 10. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x60 9. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x60 8. "CMEN,Circular mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x60 6.--7. "TM,Transfer mode" "0,1,2,3"
|
|
bitfld.long 0x60 4. "FTFIE,Enable bit for full transfer finish interrupt" "0,1"
|
|
bitfld.long 0x60 3. "HTFIE,Enable bit for half transfer finish interrupt" "0,1"
|
|
bitfld.long 0x60 2. "TAEIE,Enable bit for tranfer access error interrupt" "0,1"
|
|
bitfld.long 0x60 1. "SDEIE,Enable bit for single data mode exception interrupt" "0,1"
|
|
bitfld.long 0x60 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x64 "CH4CNT,Channel 4 counter regist"
|
|
hexmask.long.word 0x64 0.--15. 1. "CNT,Transfer counter"
|
|
line.long 0x68 "CH4PADDR,Channel 4 peripheral base address regist"
|
|
hexmask.long 0x68 0.--31. 1. "PADDR,Peripheral base address"
|
|
line.long 0x6C "CH4M0ADDR,Channel 4 memory 0 base address regist"
|
|
hexmask.long 0x6C 0.--31. 1. "M0ADDR,Memory 0 base address"
|
|
line.long 0x70 "CH4M1ADDR,Channel 4 memory 1 base address regist"
|
|
hexmask.long 0x70 0.--31. 1. "M1ADDR,Memory 1 base address"
|
|
line.long 0x74 "CH4FCTL,Channel 4 FIFO control regist"
|
|
bitfld.long 0x74 7. "FEEIE,Enable bit for FIFO error and exception interrupt" "0,1"
|
|
rbitfld.long 0x74 3.--5. "FCNT,FIFO counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x74 2. "MDMEN,Multi-data mode enable" "0,1"
|
|
bitfld.long 0x74 0.--1. "FCCV,FIFO counter critical value" "0,1,2,3"
|
|
line.long 0x78 "CH5CTL,Channel 5 control regist"
|
|
bitfld.long 0x78 23.--24. "MBURST,Transfer burst type of memory" "0,1,2,3"
|
|
bitfld.long 0x78 21.--22. "PBURST,Transfer burst type of peripheral" "0,1,2,3"
|
|
bitfld.long 0x78 19. "MBS,Memory buffer select" "0,1"
|
|
bitfld.long 0x78 18. "SBMEN,Switch-buffer mode enable" "0,1"
|
|
bitfld.long 0x78 16.--17. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x78 15. "PAIF,Peripheral address increment fixed" "0,1"
|
|
bitfld.long 0x78 13.--14. "MWIDTH,Transfer width of memory" "0,1,2,3"
|
|
bitfld.long 0x78 11.--12. "PWIDTH,Transfer width of peripheral" "0,1,2,3"
|
|
bitfld.long 0x78 10. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x78 9. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x78 8. "CMEN,Circular mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x78 6.--7. "TM,Transfer mode" "0,1,2,3"
|
|
bitfld.long 0x78 4. "FTFIE,Enable bit for full transfer finish interrupt" "0,1"
|
|
bitfld.long 0x78 3. "HTFIE,Enable bit for half transfer finish interrupt" "0,1"
|
|
bitfld.long 0x78 2. "TAEIE,Enable bit for tranfer access error interrupt" "0,1"
|
|
bitfld.long 0x78 1. "SDEIE,Enable bit for single data mode exception interrupt" "0,1"
|
|
bitfld.long 0x78 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x7C "CH5CNT,Channel 5 counter regist"
|
|
hexmask.long.word 0x7C 0.--15. 1. "CNT,Transfer counter"
|
|
line.long 0x80 "CH5PADDR,Channel 5 peripheral base address regist"
|
|
hexmask.long 0x80 0.--31. 1. "PADDR,Peripheral base address"
|
|
line.long 0x84 "CH5M0ADDR,Channel 5 memory 0 base address regist"
|
|
hexmask.long 0x84 0.--31. 1. "M0ADDR,Memory 0 base address"
|
|
line.long 0x88 "CH5M1ADDR,Channel 5 memory 1 base address regist"
|
|
hexmask.long 0x88 0.--31. 1. "M1ADDR,Memory 1 base address"
|
|
line.long 0x8C "CH5FCTL,Channel 5 FIFO control regist"
|
|
bitfld.long 0x8C 7. "FEEIE,Enable bit for FIFO error and exception interrupt" "0,1"
|
|
rbitfld.long 0x8C 3.--5. "FCNT,FIFO counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8C 2. "MDMEN,Multi-data mode enable" "0,1"
|
|
bitfld.long 0x8C 0.--1. "FCCV,FIFO counter critical value" "0,1,2,3"
|
|
line.long 0x90 "CH6CTL,Channel 6 control regist"
|
|
bitfld.long 0x90 23.--24. "MBURST,Transfer burst type of memory" "0,1,2,3"
|
|
bitfld.long 0x90 21.--22. "PBURST,Transfer burst type of peripheral" "0,1,2,3"
|
|
bitfld.long 0x90 19. "MBS,Memory buffer select" "0,1"
|
|
bitfld.long 0x90 18. "SBMEN,Switch-buffer mode enable" "0,1"
|
|
bitfld.long 0x90 16.--17. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x90 15. "PAIF,Peripheral address increment fixed" "0,1"
|
|
bitfld.long 0x90 13.--14. "MWIDTH,Transfer width of memory" "0,1,2,3"
|
|
bitfld.long 0x90 11.--12. "PWIDTH,Transfer width of peripheral" "0,1,2,3"
|
|
bitfld.long 0x90 10. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x90 9. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x90 8. "CMEN,Circular mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x90 6.--7. "TM,Transfer mode" "0,1,2,3"
|
|
bitfld.long 0x90 4. "FTFIE,Enable bit for full transfer finish interrupt" "0,1"
|
|
bitfld.long 0x90 3. "HTFIE,Enable bit for half transfer finish interrupt" "0,1"
|
|
bitfld.long 0x90 2. "TAEIE,Enable bit for tranfer access error interrupt" "0,1"
|
|
bitfld.long 0x90 1. "SDEIE,Enable bit for single data mode exception interrupt" "0,1"
|
|
bitfld.long 0x90 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x94 "CH6CNT,Channel 6 counter regist"
|
|
hexmask.long.word 0x94 0.--15. 1. "CNT,Transfer counter"
|
|
line.long 0x98 "CH6PADDR,Channel 6 peripheral base address regist"
|
|
hexmask.long 0x98 0.--31. 1. "PADDR,Peripheral base address"
|
|
line.long 0x9C "CH6M0ADDR,Channel 6 memory 0 base address regist"
|
|
hexmask.long 0x9C 0.--31. 1. "M0ADDR,Memory 0 base address"
|
|
line.long 0xA0 "CH6M1ADDR,Channel 6 memory 1 base address regist"
|
|
hexmask.long 0xA0 0.--31. 1. "M1ADDR,Memory 1 base address"
|
|
line.long 0xA4 "CH6FCTL,Channel 6 FIFO control regist"
|
|
bitfld.long 0xA4 7. "FEEIE,Enable bit for FIFO error and exception interrupt" "0,1"
|
|
rbitfld.long 0xA4 3.--5. "FCNT,FIFO counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xA4 2. "MDMEN,Multi-data mode enable" "0,1"
|
|
bitfld.long 0xA4 0.--1. "FCCV,FIFO counter critical value" "0,1,2,3"
|
|
line.long 0xA8 "CH7CTL,Channel 7 control regist"
|
|
bitfld.long 0xA8 23.--24. "MBURST,Transfer burst type of memory" "0,1,2,3"
|
|
bitfld.long 0xA8 21.--22. "PBURST,Transfer burst type of peripheral" "0,1,2,3"
|
|
bitfld.long 0xA8 19. "MBS,Memory buffer select" "0,1"
|
|
bitfld.long 0xA8 18. "SBMEN,Switch-buffer mode enable" "0,1"
|
|
bitfld.long 0xA8 16.--17. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0xA8 15. "PAIF,Peripheral address increment fixed" "0,1"
|
|
bitfld.long 0xA8 13.--14. "MWIDTH,Transfer width of memory" "0,1,2,3"
|
|
bitfld.long 0xA8 11.--12. "PWIDTH,Transfer width of peripheral" "0,1,2,3"
|
|
bitfld.long 0xA8 10. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0xA8 9. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0xA8 8. "CMEN,Circular mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0xA8 6.--7. "TM,Transfer mode" "0,1,2,3"
|
|
bitfld.long 0xA8 4. "FTFIE,Enable bit for full transfer finish interrupt" "0,1"
|
|
bitfld.long 0xA8 3. "HTFIE,Enable bit for half transfer finish interrupt" "0,1"
|
|
bitfld.long 0xA8 2. "TAEIE,Enable bit for tranfer access error interrupt" "0,1"
|
|
bitfld.long 0xA8 1. "SDEIE,Enable bit for single data mode exception interrupt" "0,1"
|
|
bitfld.long 0xA8 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0xAC "CH7CNT,Channel 7 counter regist"
|
|
hexmask.long.word 0xAC 0.--15. 1. "CNT,Transfer counter"
|
|
line.long 0xB0 "CH7PADDR,Channel 7 peripheral base address regist"
|
|
hexmask.long 0xB0 0.--31. 1. "PADDR,Peripheral base address"
|
|
line.long 0xB4 "CH7M0ADDR,Channel 7 memory 0 base address regist"
|
|
hexmask.long 0xB4 0.--31. 1. "M0ADDR,Memory 0 base address"
|
|
line.long 0xB8 "CH7M1ADDR,Channel 7 memory 1 base address regist"
|
|
hexmask.long 0xB8 0.--31. 1. "M1ADDR,Memory 1 base address"
|
|
line.long 0xBC "CH7FCTL,Channel 7 FIFO control regist"
|
|
bitfld.long 0xBC 7. "FEEIE,Enable bit for FIFO error and exception interrupt" "0,1"
|
|
rbitfld.long 0xBC 3.--5. "FCNT,FIFO counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xBC 2. "MDMEN,Multi-data mode enable" "0,1"
|
|
bitfld.long 0xBC 0.--1. "FCCV,FIFO counter critical value" "0,1,2,3"
|
|
tree.end
|
|
tree "DMA1"
|
|
base ad:0x40020400
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "INTF0,Interrupt flag register 0"
|
|
bitfld.long 0x0 27. "FTFIF3,Full Transfer finish flag of channel 3" "0,1"
|
|
bitfld.long 0x0 26. "HTFIF3,Half transfer finish flag of channel 3" "0,1"
|
|
bitfld.long 0x0 25. "TAEIF3,Transfer access error flag of channel 3" "0,1"
|
|
bitfld.long 0x0 24. "SDEIF3,Single data mode exception of channel 3" "0,1"
|
|
bitfld.long 0x0 22. "FEEIF3,FIFO error and exception of channel 3" "0,1"
|
|
bitfld.long 0x0 21. "FTFIF2,Full Transfer finish flag of channel 2" "0,1"
|
|
bitfld.long 0x0 20. "HTFIF2,Half transfer finish flag of channel 2" "0,1"
|
|
bitfld.long 0x0 19. "TAEIF2,Transfer access error flag of channel 2" "0,1"
|
|
bitfld.long 0x0 18. "SDEIF2,Single data mode exception of channel 2" "0,1"
|
|
bitfld.long 0x0 16. "FEEIF2,FIFO error and exception of channel 2" "0,1"
|
|
bitfld.long 0x0 11. "FTFIF1,Full Transfer finish flag of channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "HTFIF1,Half transfer finish flag of channel 1" "0,1"
|
|
bitfld.long 0x0 9. "TAEIF1,Transfer access error flag of channel 1" "0,1"
|
|
bitfld.long 0x0 8. "SDEIF1,Single data mode exception of channel 1" "0,1"
|
|
bitfld.long 0x0 6. "FEEIF1,FIFO error and exception of channel 1" "0,1"
|
|
bitfld.long 0x0 5. "FTFIF0,Full Transfer finish flag of channel 0" "0,1"
|
|
bitfld.long 0x0 4. "HTFIF0,Half transfer finish flag of channel 0" "0,1"
|
|
bitfld.long 0x0 3. "TAEIF0,Transfer access error flag of channel 0" "0,1"
|
|
bitfld.long 0x0 2. "SDEIF0,Single data mode exception of channel 0" "0,1"
|
|
bitfld.long 0x0 0. "FEEIF0,FIFO error and exception of channel 0" "0,1"
|
|
line.long 0x4 "INTF1,Interrupt flag register 1"
|
|
bitfld.long 0x4 27. "FTFIF7,Full Transfer finish flag of channel 7" "0,1"
|
|
bitfld.long 0x4 26. "HTFIF7,Half transfer finish flag of channel 7" "0,1"
|
|
bitfld.long 0x4 25. "TAEIF7,Transfer access error flag of channel 7" "0,1"
|
|
bitfld.long 0x4 24. "SDEIF7,Single data mode exception of channel 7" "0,1"
|
|
bitfld.long 0x4 22. "FEEIF7,FIFO error and exception of channel 7" "0,1"
|
|
bitfld.long 0x4 21. "FTFIF6,Full Transfer finish flag of channel 6" "0,1"
|
|
bitfld.long 0x4 20. "HTFIF6,Half transfer finish flag of channel 6" "0,1"
|
|
bitfld.long 0x4 19. "TAEIF6,Transfer access error flag of channel 6" "0,1"
|
|
bitfld.long 0x4 18. "SDEIF6,Single data mode exception of channel 6" "0,1"
|
|
bitfld.long 0x4 16. "FEEIF6,FIFO error and exception of channel 6" "0,1"
|
|
bitfld.long 0x4 11. "FTFIF5,Full Transfer finish flag of channel 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "HTFIF5,Half transfer finish flag of channel 5" "0,1"
|
|
bitfld.long 0x4 9. "TAEIF5,Transfer access error flag of channel 5" "0,1"
|
|
bitfld.long 0x4 8. "SDEIF5,Single data mode exception of channel 5" "0,1"
|
|
bitfld.long 0x4 6. "FEEIF5,FIFO error and exception of channel 5" "0,1"
|
|
bitfld.long 0x4 5. "FTFIF4,Full Transfer finish flag of channel 4" "0,1"
|
|
bitfld.long 0x4 4. "HTFIF4,Half transfer finish flag of channel 4" "0,1"
|
|
bitfld.long 0x4 3. "TAEIF4,Transfer access error flag of channel 4" "0,1"
|
|
bitfld.long 0x4 2. "SDEIF4,Single data mode exception of channel 4" "0,1"
|
|
bitfld.long 0x4 0. "FEEIF4,FIFO error and exception of channel 4" "0,1"
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "INTC0,Interrupt flag clear register 0"
|
|
bitfld.long 0x0 27. "FTFIFC3,Full Transfer finish flag of channel 3" "0,1"
|
|
bitfld.long 0x0 26. "HTFIFC3,Half transfer finish flag of channel 3" "0,1"
|
|
bitfld.long 0x0 25. "TAEIFC3,Transfer access error flag of channel 3" "0,1"
|
|
bitfld.long 0x0 24. "SDEIFC3,Single data mode exception of channel 3" "0,1"
|
|
bitfld.long 0x0 22. "FEEIFC3,FIFO error and exception of channel 3" "0,1"
|
|
bitfld.long 0x0 21. "FTFIFC2,Full Transfer finish flag of channel 2" "0,1"
|
|
bitfld.long 0x0 20. "HTFIFC2,Half transfer finish flag of channel 2" "0,1"
|
|
bitfld.long 0x0 19. "TAEIFC2,Transfer access error flag of channel 2" "0,1"
|
|
bitfld.long 0x0 18. "SDEIFC2,Single data mode exception of channel 2" "0,1"
|
|
bitfld.long 0x0 16. "FEEIFC2,FIFO error and exception of channel 2" "0,1"
|
|
bitfld.long 0x0 11. "FTFIFC1,Full Transfer finish flag of channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "HTFIFC1,Half transfer finish flag of channel 1" "0,1"
|
|
bitfld.long 0x0 9. "TAEIFC1,Transfer access error flag of channel 1" "0,1"
|
|
bitfld.long 0x0 8. "SDEIFC1,Single data mode exception of channel 1" "0,1"
|
|
bitfld.long 0x0 6. "FEEIFC1,FIFO error and exception of channel 1" "0,1"
|
|
bitfld.long 0x0 5. "FTFIFC0,Full Transfer finish flag of channel 0" "0,1"
|
|
bitfld.long 0x0 4. "HTFIFC0,Half transfer finish flag of channel 0" "0,1"
|
|
bitfld.long 0x0 3. "TAEIFC0,Transfer access error flag of channel 0" "0,1"
|
|
bitfld.long 0x0 2. "SDEIFC0,Single data mode exception of channel 0" "0,1"
|
|
bitfld.long 0x0 0. "FEEIFC0,FIFO error and exception of channel 0" "0,1"
|
|
line.long 0x4 "INTC1,Interrupt flag clear register 1"
|
|
bitfld.long 0x4 27. "FTFIFC7,Full Transfer finish flag of channel 7" "0,1"
|
|
bitfld.long 0x4 26. "HTFIFC7,Half transfer finish flag of channel 7" "0,1"
|
|
bitfld.long 0x4 25. "TAEIFC7,Transfer access error flag of channel 7" "0,1"
|
|
bitfld.long 0x4 24. "SDEIFC7,Single data mode exception of channel 7" "0,1"
|
|
bitfld.long 0x4 22. "FEEIFC7,FIFO error and exception of channel 7" "0,1"
|
|
bitfld.long 0x4 21. "FTFIFC6,Full Transfer finish flag of channel 6" "0,1"
|
|
bitfld.long 0x4 20. "HTFIFC6,Half transfer finish flag of channel 6" "0,1"
|
|
bitfld.long 0x4 19. "TAEIFC6,Transfer access error flag of channel 6" "0,1"
|
|
bitfld.long 0x4 18. "SDEIFC6,Single data mode exception of channel 6" "0,1"
|
|
bitfld.long 0x4 16. "FEEIFC6,FIFO error and exception of channel 6" "0,1"
|
|
bitfld.long 0x4 11. "FTFIFC5,Full Transfer finish flag of channel 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "HTFIFC5,Half transfer finish flag of channel 5" "0,1"
|
|
bitfld.long 0x4 9. "TAEIFC5,Transfer access error flag of channel 5" "0,1"
|
|
bitfld.long 0x4 8. "SDEIFC5,Single data mode exception of channel 5" "0,1"
|
|
bitfld.long 0x4 6. "FEEIFC5,FIFO error and exception of channel 5" "0,1"
|
|
bitfld.long 0x4 5. "FTFIFC4,Full Transfer finish flag of channel 4" "0,1"
|
|
bitfld.long 0x4 4. "HTFIFC4,Half transfer finish flag of channel 4" "0,1"
|
|
bitfld.long 0x4 3. "TAEIFC4,Transfer access error flag of channel 4" "0,1"
|
|
bitfld.long 0x4 2. "SDEIFC4,Single data mode exception of channel 4" "0,1"
|
|
bitfld.long 0x4 0. "FEEIFC4,FIFO error and exception of channel 4" "0,1"
|
|
group.long 0x10++0xBF
|
|
line.long 0x0 "CH0CTL,Channel 0 control regist"
|
|
bitfld.long 0x0 23.--24. "MBURST,Transfer burst type of memory" "0,1,2,3"
|
|
bitfld.long 0x0 21.--22. "PBURST,Transfer burst type of peripheral" "0,1,2,3"
|
|
bitfld.long 0x0 19. "MBS,Memory buffer select" "0,1"
|
|
bitfld.long 0x0 18. "SBMEN,Switch-buffer mode enable" "0,1"
|
|
bitfld.long 0x0 16.--17. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 15. "PAIF,Peripheral address increment fixed" "0,1"
|
|
bitfld.long 0x0 13.--14. "MWIDTH,Transfer width of memory" "0,1,2,3"
|
|
bitfld.long 0x0 11.--12. "PWIDTH,Transfer width of peripheral" "0,1,2,3"
|
|
bitfld.long 0x0 10. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x0 9. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x0 8. "CMEN,Circular mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "TM,Transfer mode" "0,1,2,3"
|
|
bitfld.long 0x0 4. "FTFIE,Enable bit for full transfer finish interrupt" "0,1"
|
|
bitfld.long 0x0 3. "HTFIE,Enable bit for half transfer finish interrupt" "0,1"
|
|
bitfld.long 0x0 2. "TAEIE,Enable bit for tranfer access error interrupt" "0,1"
|
|
bitfld.long 0x0 1. "SDEIE,Enable bit for single data mode exception interrupt" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH0CNT,Channel 0 counter regist"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,Transfer counter"
|
|
line.long 0x8 "CH0PADDR,Channel 0 peripheral base address regist"
|
|
hexmask.long 0x8 0.--31. 1. "PADDR,Peripheral base address"
|
|
line.long 0xC "CH0M0ADDR,Channel 0 memory 0 base address regist"
|
|
hexmask.long 0xC 0.--31. 1. "M0ADDR,Memory 0 base address"
|
|
line.long 0x10 "CH0M1ADDR,Channel 0 memory 1 base address regist"
|
|
hexmask.long 0x10 0.--31. 1. "M1ADDR,Memory 1 base address"
|
|
line.long 0x14 "CH0FCTL,Channel 0 FIFO control regist"
|
|
bitfld.long 0x14 7. "FEEIE,Enable bit for FIFO error and exception interrupt" "0,1"
|
|
rbitfld.long 0x14 3.--5. "FCNT,FIFO counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 2. "MDMEN,Multi-data mode enable" "0,1"
|
|
bitfld.long 0x14 0.--1. "FCCV,FIFO counter critical value" "0,1,2,3"
|
|
line.long 0x18 "CH1CTL,Channel 1 control regist"
|
|
bitfld.long 0x18 23.--24. "MBURST,Transfer burst type of memory" "0,1,2,3"
|
|
bitfld.long 0x18 21.--22. "PBURST,Transfer burst type of peripheral" "0,1,2,3"
|
|
bitfld.long 0x18 19. "MBS,Memory buffer select" "0,1"
|
|
bitfld.long 0x18 18. "SBMEN,Switch-buffer mode enable" "0,1"
|
|
bitfld.long 0x18 16.--17. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x18 15. "PAIF,Peripheral address increment fixed" "0,1"
|
|
bitfld.long 0x18 13.--14. "MWIDTH,Transfer width of memory" "0,1,2,3"
|
|
bitfld.long 0x18 11.--12. "PWIDTH,Transfer width of peripheral" "0,1,2,3"
|
|
bitfld.long 0x18 10. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x18 9. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x18 8. "CMEN,Circular mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 6.--7. "TM,Transfer mode" "0,1,2,3"
|
|
bitfld.long 0x18 4. "FTFIE,Enable bit for full transfer finish interrupt" "0,1"
|
|
bitfld.long 0x18 3. "HTFIE,Enable bit for half transfer finish interrupt" "0,1"
|
|
bitfld.long 0x18 2. "TAEIE,Enable bit for tranfer access error interrupt" "0,1"
|
|
bitfld.long 0x18 1. "SDEIE,Enable bit for single data mode exception interrupt" "0,1"
|
|
bitfld.long 0x18 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x1C "CH1CNT,Channel 1 counter regist"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CNT,Transfer counter"
|
|
line.long 0x20 "CH1PADDR,Channel 1 peripheral base address regist"
|
|
hexmask.long 0x20 0.--31. 1. "PADDR,Peripheral base address"
|
|
line.long 0x24 "CH1M0ADDR,Channel 1 memory 0 base address regist"
|
|
hexmask.long 0x24 0.--31. 1. "M0ADDR,Memory 0 base address"
|
|
line.long 0x28 "CH1M1ADDR,Channel 1 memory 1 base address regist"
|
|
hexmask.long 0x28 0.--31. 1. "M1ADDR,Memory 1 base address"
|
|
line.long 0x2C "CH1FCTL,Channel 1 FIFO control regist"
|
|
bitfld.long 0x2C 7. "FEEIE,Enable bit for FIFO error and exception interrupt" "0,1"
|
|
rbitfld.long 0x2C 3.--5. "FCNT,FIFO counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 2. "MDMEN,Multi-data mode enable" "0,1"
|
|
bitfld.long 0x2C 0.--1. "FCCV,FIFO counter critical value" "0,1,2,3"
|
|
line.long 0x30 "CH2CTL,Channel 2 control regist"
|
|
bitfld.long 0x30 23.--24. "MBURST,Transfer burst type of memory" "0,1,2,3"
|
|
bitfld.long 0x30 21.--22. "PBURST,Transfer burst type of peripheral" "0,1,2,3"
|
|
bitfld.long 0x30 19. "MBS,Memory buffer select" "0,1"
|
|
bitfld.long 0x30 18. "SBMEN,Switch-buffer mode enable" "0,1"
|
|
bitfld.long 0x30 16.--17. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x30 15. "PAIF,Peripheral address increment fixed" "0,1"
|
|
bitfld.long 0x30 13.--14. "MWIDTH,Transfer width of memory" "0,1,2,3"
|
|
bitfld.long 0x30 11.--12. "PWIDTH,Transfer width of peripheral" "0,1,2,3"
|
|
bitfld.long 0x30 10. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x30 9. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x30 8. "CMEN,Circular mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x30 6.--7. "TM,Transfer mode" "0,1,2,3"
|
|
bitfld.long 0x30 4. "FTFIE,Enable bit for full transfer finish interrupt" "0,1"
|
|
bitfld.long 0x30 3. "HTFIE,Enable bit for half transfer finish interrupt" "0,1"
|
|
bitfld.long 0x30 2. "TAEIE,Enable bit for tranfer access error interrupt" "0,1"
|
|
bitfld.long 0x30 1. "SDEIE,Enable bit for single data mode exception interrupt" "0,1"
|
|
bitfld.long 0x30 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x34 "CH2CNT,Channel 2 counter regist"
|
|
hexmask.long.word 0x34 0.--15. 1. "CNT,Transfer counter"
|
|
line.long 0x38 "CH2PADDR,Channel 2 peripheral base address regist"
|
|
hexmask.long 0x38 0.--31. 1. "PADDR,Peripheral base address"
|
|
line.long 0x3C "CH2M0ADDR,Channel 2 memory 0 base address regist"
|
|
hexmask.long 0x3C 0.--31. 1. "M0ADDR,Memory 0 base address"
|
|
line.long 0x40 "CH2M1ADDR,Channel 2 memory 1 base address regist"
|
|
hexmask.long 0x40 0.--31. 1. "M1ADDR,Memory 1 base address"
|
|
line.long 0x44 "CH2FCTL,Channel 2 FIFO control regist"
|
|
bitfld.long 0x44 7. "FEEIE,Enable bit for FIFO error and exception interrupt" "0,1"
|
|
rbitfld.long 0x44 3.--5. "FCNT,FIFO counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x44 2. "MDMEN,Multi-data mode enable" "0,1"
|
|
bitfld.long 0x44 0.--1. "FCCV,FIFO counter critical value" "0,1,2,3"
|
|
line.long 0x48 "CH3CTL,Channel 3 control regist"
|
|
bitfld.long 0x48 23.--24. "MBURST,Transfer burst type of memory" "0,1,2,3"
|
|
bitfld.long 0x48 21.--22. "PBURST,Transfer burst type of peripheral" "0,1,2,3"
|
|
bitfld.long 0x48 19. "MBS,Memory buffer select" "0,1"
|
|
bitfld.long 0x48 18. "SBMEN,Switch-buffer mode enable" "0,1"
|
|
bitfld.long 0x48 16.--17. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x48 15. "PAIF,Peripheral address increment fixed" "0,1"
|
|
bitfld.long 0x48 13.--14. "MWIDTH,Transfer width of memory" "0,1,2,3"
|
|
bitfld.long 0x48 11.--12. "PWIDTH,Transfer width of peripheral" "0,1,2,3"
|
|
bitfld.long 0x48 10. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x48 9. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x48 8. "CMEN,Circular mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 6.--7. "TM,Transfer mode" "0,1,2,3"
|
|
bitfld.long 0x48 4. "FTFIE,Enable bit for full transfer finish interrupt" "0,1"
|
|
bitfld.long 0x48 3. "HTFIE,Enable bit for half transfer finish interrupt" "0,1"
|
|
bitfld.long 0x48 2. "TAEIE,Enable bit for tranfer access error interrupt" "0,1"
|
|
bitfld.long 0x48 1. "SDEIE,Enable bit for single data mode exception interrupt" "0,1"
|
|
bitfld.long 0x48 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4C "CH3CNT,Channel 3 counter regist"
|
|
hexmask.long.word 0x4C 0.--15. 1. "CNT,Transfer counter"
|
|
line.long 0x50 "CH3PADDR,Channel 3 peripheral base address regist"
|
|
hexmask.long 0x50 0.--31. 1. "PADDR,Peripheral base address"
|
|
line.long 0x54 "CH3M0ADDR,Channel 3 memory 0 base address regist"
|
|
hexmask.long 0x54 0.--31. 1. "M0ADDR,Memory 0 base address"
|
|
line.long 0x58 "CH3M1ADDR,Channel 3 memory 1 base address regist"
|
|
hexmask.long 0x58 0.--31. 1. "M1ADDR,Memory 1 base address"
|
|
line.long 0x5C "CH3FCTL,Channel 3 FIFO control regist"
|
|
bitfld.long 0x5C 7. "FEEIE,Enable bit for FIFO error and exception interrupt" "0,1"
|
|
rbitfld.long 0x5C 3.--5. "FCNT,FIFO counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x5C 2. "MDMEN,Multi-data mode enable" "0,1"
|
|
bitfld.long 0x5C 0.--1. "FCCV,FIFO counter critical value" "0,1,2,3"
|
|
line.long 0x60 "CH4CTL,Channel 4 control regist"
|
|
bitfld.long 0x60 23.--24. "MBURST,Transfer burst type of memory" "0,1,2,3"
|
|
bitfld.long 0x60 21.--22. "PBURST,Transfer burst type of peripheral" "0,1,2,3"
|
|
bitfld.long 0x60 19. "MBS,Memory buffer select" "0,1"
|
|
bitfld.long 0x60 18. "SBMEN,Switch-buffer mode enable" "0,1"
|
|
bitfld.long 0x60 16.--17. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x60 15. "PAIF,Peripheral address increment fixed" "0,1"
|
|
bitfld.long 0x60 13.--14. "MWIDTH,Transfer width of memory" "0,1,2,3"
|
|
bitfld.long 0x60 11.--12. "PWIDTH,Transfer width of peripheral" "0,1,2,3"
|
|
bitfld.long 0x60 10. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x60 9. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x60 8. "CMEN,Circular mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x60 6.--7. "TM,Transfer mode" "0,1,2,3"
|
|
bitfld.long 0x60 4. "FTFIE,Enable bit for full transfer finish interrupt" "0,1"
|
|
bitfld.long 0x60 3. "HTFIE,Enable bit for half transfer finish interrupt" "0,1"
|
|
bitfld.long 0x60 2. "TAEIE,Enable bit for tranfer access error interrupt" "0,1"
|
|
bitfld.long 0x60 1. "SDEIE,Enable bit for single data mode exception interrupt" "0,1"
|
|
bitfld.long 0x60 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x64 "CH4CNT,Channel 4 counter regist"
|
|
hexmask.long.word 0x64 0.--15. 1. "CNT,Transfer counter"
|
|
line.long 0x68 "CH4PADDR,Channel 4 peripheral base address regist"
|
|
hexmask.long 0x68 0.--31. 1. "PADDR,Peripheral base address"
|
|
line.long 0x6C "CH4M0ADDR,Channel 4 memory 0 base address regist"
|
|
hexmask.long 0x6C 0.--31. 1. "M0ADDR,Memory 0 base address"
|
|
line.long 0x70 "CH4M1ADDR,Channel 4 memory 1 base address regist"
|
|
hexmask.long 0x70 0.--31. 1. "M1ADDR,Memory 1 base address"
|
|
line.long 0x74 "CH4FCTL,Channel 4 FIFO control regist"
|
|
bitfld.long 0x74 7. "FEEIE,Enable bit for FIFO error and exception interrupt" "0,1"
|
|
rbitfld.long 0x74 3.--5. "FCNT,FIFO counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x74 2. "MDMEN,Multi-data mode enable" "0,1"
|
|
bitfld.long 0x74 0.--1. "FCCV,FIFO counter critical value" "0,1,2,3"
|
|
line.long 0x78 "CH5CTL,Channel 5 control regist"
|
|
bitfld.long 0x78 23.--24. "MBURST,Transfer burst type of memory" "0,1,2,3"
|
|
bitfld.long 0x78 21.--22. "PBURST,Transfer burst type of peripheral" "0,1,2,3"
|
|
bitfld.long 0x78 19. "MBS,Memory buffer select" "0,1"
|
|
bitfld.long 0x78 18. "SBMEN,Switch-buffer mode enable" "0,1"
|
|
bitfld.long 0x78 16.--17. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x78 15. "PAIF,Peripheral address increment fixed" "0,1"
|
|
bitfld.long 0x78 13.--14. "MWIDTH,Transfer width of memory" "0,1,2,3"
|
|
bitfld.long 0x78 11.--12. "PWIDTH,Transfer width of peripheral" "0,1,2,3"
|
|
bitfld.long 0x78 10. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x78 9. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x78 8. "CMEN,Circular mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x78 6.--7. "TM,Transfer mode" "0,1,2,3"
|
|
bitfld.long 0x78 4. "FTFIE,Enable bit for full transfer finish interrupt" "0,1"
|
|
bitfld.long 0x78 3. "HTFIE,Enable bit for half transfer finish interrupt" "0,1"
|
|
bitfld.long 0x78 2. "TAEIE,Enable bit for tranfer access error interrupt" "0,1"
|
|
bitfld.long 0x78 1. "SDEIE,Enable bit for single data mode exception interrupt" "0,1"
|
|
bitfld.long 0x78 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x7C "CH5CNT,Channel 5 counter regist"
|
|
hexmask.long.word 0x7C 0.--15. 1. "CNT,Transfer counter"
|
|
line.long 0x80 "CH5PADDR,Channel 5 peripheral base address regist"
|
|
hexmask.long 0x80 0.--31. 1. "PADDR,Peripheral base address"
|
|
line.long 0x84 "CH5M0ADDR,Channel 5 memory 0 base address regist"
|
|
hexmask.long 0x84 0.--31. 1. "M0ADDR,Memory 0 base address"
|
|
line.long 0x88 "CH5M1ADDR,Channel 5 memory 1 base address regist"
|
|
hexmask.long 0x88 0.--31. 1. "M1ADDR,Memory 1 base address"
|
|
line.long 0x8C "CH5FCTL,Channel 5 FIFO control regist"
|
|
bitfld.long 0x8C 7. "FEEIE,Enable bit for FIFO error and exception interrupt" "0,1"
|
|
rbitfld.long 0x8C 3.--5. "FCNT,FIFO counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8C 2. "MDMEN,Multi-data mode enable" "0,1"
|
|
bitfld.long 0x8C 0.--1. "FCCV,FIFO counter critical value" "0,1,2,3"
|
|
line.long 0x90 "CH6CTL,Channel 6 control regist"
|
|
bitfld.long 0x90 23.--24. "MBURST,Transfer burst type of memory" "0,1,2,3"
|
|
bitfld.long 0x90 21.--22. "PBURST,Transfer burst type of peripheral" "0,1,2,3"
|
|
bitfld.long 0x90 19. "MBS,Memory buffer select" "0,1"
|
|
bitfld.long 0x90 18. "SBMEN,Switch-buffer mode enable" "0,1"
|
|
bitfld.long 0x90 16.--17. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x90 15. "PAIF,Peripheral address increment fixed" "0,1"
|
|
bitfld.long 0x90 13.--14. "MWIDTH,Transfer width of memory" "0,1,2,3"
|
|
bitfld.long 0x90 11.--12. "PWIDTH,Transfer width of peripheral" "0,1,2,3"
|
|
bitfld.long 0x90 10. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0x90 9. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0x90 8. "CMEN,Circular mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x90 6.--7. "TM,Transfer mode" "0,1,2,3"
|
|
bitfld.long 0x90 4. "FTFIE,Enable bit for full transfer finish interrupt" "0,1"
|
|
bitfld.long 0x90 3. "HTFIE,Enable bit for half transfer finish interrupt" "0,1"
|
|
bitfld.long 0x90 2. "TAEIE,Enable bit for tranfer access error interrupt" "0,1"
|
|
bitfld.long 0x90 1. "SDEIE,Enable bit for single data mode exception interrupt" "0,1"
|
|
bitfld.long 0x90 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x94 "CH6CNT,Channel 6 counter regist"
|
|
hexmask.long.word 0x94 0.--15. 1. "CNT,Transfer counter"
|
|
line.long 0x98 "CH6PADDR,Channel 6 peripheral base address regist"
|
|
hexmask.long 0x98 0.--31. 1. "PADDR,Peripheral base address"
|
|
line.long 0x9C "CH6M0ADDR,Channel 6 memory 0 base address regist"
|
|
hexmask.long 0x9C 0.--31. 1. "M0ADDR,Memory 0 base address"
|
|
line.long 0xA0 "CH6M1ADDR,Channel 6 memory 1 base address regist"
|
|
hexmask.long 0xA0 0.--31. 1. "M1ADDR,Memory 1 base address"
|
|
line.long 0xA4 "CH6FCTL,Channel 6 FIFO control regist"
|
|
bitfld.long 0xA4 7. "FEEIE,Enable bit for FIFO error and exception interrupt" "0,1"
|
|
rbitfld.long 0xA4 3.--5. "FCNT,FIFO counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xA4 2. "MDMEN,Multi-data mode enable" "0,1"
|
|
bitfld.long 0xA4 0.--1. "FCCV,FIFO counter critical value" "0,1,2,3"
|
|
line.long 0xA8 "CH7CTL,Channel 7 control regist"
|
|
bitfld.long 0xA8 23.--24. "MBURST,Transfer burst type of memory" "0,1,2,3"
|
|
bitfld.long 0xA8 21.--22. "PBURST,Transfer burst type of peripheral" "0,1,2,3"
|
|
bitfld.long 0xA8 19. "MBS,Memory buffer select" "0,1"
|
|
bitfld.long 0xA8 18. "SBMEN,Switch-buffer mode enable" "0,1"
|
|
bitfld.long 0xA8 16.--17. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0xA8 15. "PAIF,Peripheral address increment fixed" "0,1"
|
|
bitfld.long 0xA8 13.--14. "MWIDTH,Transfer width of memory" "0,1,2,3"
|
|
bitfld.long 0xA8 11.--12. "PWIDTH,Transfer width of peripheral" "0,1,2,3"
|
|
bitfld.long 0xA8 10. "MNAGA,Next address generation algorithm of memory" "0,1"
|
|
bitfld.long 0xA8 9. "PNAGA,Next address generation algorithm of peripheral" "0,1"
|
|
bitfld.long 0xA8 8. "CMEN,Circular mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0xA8 6.--7. "TM,Transfer mode" "0,1,2,3"
|
|
bitfld.long 0xA8 4. "FTFIE,Enable bit for full transfer finish interrupt" "0,1"
|
|
bitfld.long 0xA8 3. "HTFIE,Enable bit for half transfer finish interrupt" "0,1"
|
|
bitfld.long 0xA8 2. "TAEIE,Enable bit for tranfer access error interrupt" "0,1"
|
|
bitfld.long 0xA8 1. "SDEIE,Enable bit for single data mode exception interrupt" "0,1"
|
|
bitfld.long 0xA8 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0xAC "CH7CNT,Channel 7 counter regist"
|
|
hexmask.long.word 0xAC 0.--15. 1. "CNT,Transfer counter"
|
|
line.long 0xB0 "CH7PADDR,Channel 7 peripheral base address regist"
|
|
hexmask.long 0xB0 0.--31. 1. "PADDR,Peripheral base address"
|
|
line.long 0xB4 "CH7M0ADDR,Channel 7 memory 0 base address regist"
|
|
hexmask.long 0xB4 0.--31. 1. "M0ADDR,Memory 0 base address"
|
|
line.long 0xB8 "CH7M1ADDR,Channel 7 memory 1 base address regist"
|
|
hexmask.long 0xB8 0.--31. 1. "M1ADDR,Memory 1 base address"
|
|
line.long 0xBC "CH7FCTL,Channel 7 FIFO control regist"
|
|
bitfld.long 0xBC 7. "FEEIE,Enable bit for FIFO error and exception interrupt" "0,1"
|
|
rbitfld.long 0xBC 3.--5. "FCNT,FIFO counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xBC 2. "MDMEN,Multi-data mode enable" "0,1"
|
|
bitfld.long 0xBC 0.--1. "FCCV,FIFO counter critical value" "0,1,2,3"
|
|
tree.end
|
|
tree.end
|
|
tree "DMAMUX (DMA Request Multiplexer)"
|
|
base ad:0x40020800
|
|
group.long 0x0++0x3F
|
|
line.long 0x0 "RM_CH0CFG,Request multiplexer channel 0 configuration regist"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNCID,Synchronization input identification"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBR,Number of DMA requests to forward"
|
|
bitfld.long 0x0 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
|
|
bitfld.long 0x0 16. "SYNCEN,Synchronization enable" "0,1"
|
|
bitfld.long 0x0 9. "EVGEN,Event generation enable" "0,1"
|
|
bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MUXID,Multiplexer input identification"
|
|
line.long 0x4 "RM_CH1CFG,Request multiplexer channel 1 configuration regist"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SYNCID,Synchronization input identification"
|
|
hexmask.long.byte 0x4 19.--23. 1. "NBR,Number of DMA requests to forward"
|
|
bitfld.long 0x4 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
|
|
bitfld.long 0x4 16. "SYNCEN,Synchronization enable" "0,1"
|
|
bitfld.long 0x4 9. "EVGEN,Event generation enable" "0,1"
|
|
bitfld.long 0x4 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "MUXID,Multiplexer input identification"
|
|
line.long 0x8 "RM_CH2CFG,Request multiplexer channel 2 configuration regist"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYNCID,Synchronization input identification"
|
|
hexmask.long.byte 0x8 19.--23. 1. "NBR,Number of DMA requests to forward"
|
|
bitfld.long 0x8 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SYNCEN,Synchronization enable" "0,1"
|
|
bitfld.long 0x8 9. "EVGEN,Event generation enable" "0,1"
|
|
bitfld.long 0x8 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x8 0.--7. 1. "MUXID,Multiplexer input identification"
|
|
line.long 0xC "RM_CH3CFG,Request multiplexer channel 3 configuration regist"
|
|
hexmask.long.byte 0xC 24.--28. 1. "SYNCID,Synchronization input identification"
|
|
hexmask.long.byte 0xC 19.--23. 1. "NBR,Number of DMA requests to forward"
|
|
bitfld.long 0xC 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
|
|
bitfld.long 0xC 16. "SYNCEN,Synchronization enable" "0,1"
|
|
bitfld.long 0xC 9. "EVGEN,Event generation enable" "0,1"
|
|
bitfld.long 0xC 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0xC 0.--7. 1. "MUXID,Multiplexer input identification"
|
|
line.long 0x10 "RM_CH4CFG,Request multiplexer channel 4 configuration regist"
|
|
hexmask.long.byte 0x10 24.--28. 1. "SYNCID,Synchronization input identification"
|
|
hexmask.long.byte 0x10 19.--23. 1. "NBR,Number of DMA requests to forward"
|
|
bitfld.long 0x10 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
|
|
bitfld.long 0x10 16. "SYNCEN,Synchronization enable" "0,1"
|
|
bitfld.long 0x10 9. "EVGEN,Event generation enable" "0,1"
|
|
bitfld.long 0x10 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "MUXID,Multiplexer input identification"
|
|
line.long 0x14 "RM_CH5CFG,Request multiplexer channel 5 configuration regist"
|
|
hexmask.long.byte 0x14 24.--28. 1. "SYNCID,Synchronization input identification"
|
|
hexmask.long.byte 0x14 19.--23. 1. "NBR,Number of DMA requests to forward"
|
|
bitfld.long 0x14 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
|
|
bitfld.long 0x14 16. "SYNCEN,Synchronization enable" "0,1"
|
|
bitfld.long 0x14 9. "EVGEN,Event generation enable" "0,1"
|
|
bitfld.long 0x14 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x14 0.--7. 1. "MUXID,Multiplexer input identification"
|
|
line.long 0x18 "RM_CH6CFG,Request multiplexer channel 6 configuration regist"
|
|
hexmask.long.byte 0x18 24.--28. 1. "SYNCID,Synchronization input identification"
|
|
hexmask.long.byte 0x18 19.--23. 1. "NBR,Number of DMA requests to forward"
|
|
bitfld.long 0x18 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
|
|
bitfld.long 0x18 16. "SYNCEN,Synchronization enable" "0,1"
|
|
bitfld.long 0x18 9. "EVGEN,Event generation enable" "0,1"
|
|
bitfld.long 0x18 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x18 0.--7. 1. "MUXID,Multiplexer input identification"
|
|
line.long 0x1C "RM_CH7CFG,Request multiplexer channel 7 configuration regist"
|
|
hexmask.long.byte 0x1C 24.--28. 1. "SYNCID,Synchronization input identification"
|
|
hexmask.long.byte 0x1C 19.--23. 1. "NBR,Number of DMA requests to forward"
|
|
bitfld.long 0x1C 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
|
|
bitfld.long 0x1C 16. "SYNCEN,Synchronization enable" "0,1"
|
|
bitfld.long 0x1C 9. "EVGEN,Event generation enable" "0,1"
|
|
bitfld.long 0x1C 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "MUXID,Multiplexer input identification"
|
|
line.long 0x20 "RM_CH8CFG,Request multiplexer channel 8 configuration regist"
|
|
hexmask.long.byte 0x20 24.--28. 1. "SYNCID,Synchronization input identification"
|
|
hexmask.long.byte 0x20 19.--23. 1. "NBR,Number of DMA requests to forward"
|
|
bitfld.long 0x20 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
|
|
bitfld.long 0x20 16. "SYNCEN,Synchronization enable" "0,1"
|
|
bitfld.long 0x20 9. "EVGEN,Event generation enable" "0,1"
|
|
bitfld.long 0x20 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x20 0.--7. 1. "MUXID,Multiplexer input identification"
|
|
line.long 0x24 "RM_CH9CFG,Request multiplexer channel 9 configuration regist"
|
|
hexmask.long.byte 0x24 24.--28. 1. "SYNCID,Synchronization input identification"
|
|
hexmask.long.byte 0x24 19.--23. 1. "NBR,Number of DMA requests to forward"
|
|
bitfld.long 0x24 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
|
|
bitfld.long 0x24 16. "SYNCEN,Synchronization enable" "0,1"
|
|
bitfld.long 0x24 9. "EVGEN,Event generation enable" "0,1"
|
|
bitfld.long 0x24 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x24 0.--7. 1. "MUXID,Multiplexer input identification"
|
|
line.long 0x28 "RM_CH10CFG,Request multiplexer channel 10 configuration regist"
|
|
hexmask.long.byte 0x28 24.--28. 1. "SYNCID,Synchronization input identification"
|
|
hexmask.long.byte 0x28 19.--23. 1. "NBR,Number of DMA requests to forward"
|
|
bitfld.long 0x28 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
|
|
bitfld.long 0x28 16. "SYNCEN,Synchronization enable" "0,1"
|
|
bitfld.long 0x28 9. "EVGEN,Event generation enable" "0,1"
|
|
bitfld.long 0x28 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x28 0.--7. 1. "MUXID,Multiplexer input identification"
|
|
line.long 0x2C "RM_CH11CFG,Request multiplexer channel 11 configuration regist"
|
|
hexmask.long.byte 0x2C 24.--28. 1. "SYNCID,Synchronization input identification"
|
|
hexmask.long.byte 0x2C 19.--23. 1. "NBR,Number of DMA requests to forward"
|
|
bitfld.long 0x2C 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
|
|
bitfld.long 0x2C 16. "SYNCEN,Synchronization enable" "0,1"
|
|
bitfld.long 0x2C 9. "EVGEN,Event generation enable" "0,1"
|
|
bitfld.long 0x2C 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "MUXID,Multiplexer input identification"
|
|
line.long 0x30 "RM_CH12CFG,Request multiplexer channel 12 configuration regist"
|
|
hexmask.long.byte 0x30 24.--28. 1. "SYNCID,Synchronization input identification"
|
|
hexmask.long.byte 0x30 19.--23. 1. "NBR,Number of DMA requests to forward"
|
|
bitfld.long 0x30 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
|
|
bitfld.long 0x30 16. "SYNCEN,Synchronization enable" "0,1"
|
|
bitfld.long 0x30 9. "EVGEN,Event generation enable" "0,1"
|
|
bitfld.long 0x30 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x30 0.--7. 1. "MUXID,Multiplexer input identification"
|
|
line.long 0x34 "RM_CH13CFG,Request multiplexer channel 13 configuration regist"
|
|
hexmask.long.byte 0x34 24.--28. 1. "SYNCID,Synchronization input identification"
|
|
hexmask.long.byte 0x34 19.--23. 1. "NBR,Number of DMA requests to forward"
|
|
bitfld.long 0x34 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
|
|
bitfld.long 0x34 16. "SYNCEN,Synchronization enable" "0,1"
|
|
bitfld.long 0x34 9. "EVGEN,Event generation enable" "0,1"
|
|
bitfld.long 0x34 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x34 0.--7. 1. "MUXID,Multiplexer input identification"
|
|
line.long 0x38 "RM_CH14CFG,Request multiplexer channel 14 configuration regist"
|
|
hexmask.long.byte 0x38 24.--28. 1. "SYNCID,Synchronization input identification"
|
|
hexmask.long.byte 0x38 19.--23. 1. "NBR,Number of DMA requests to forward"
|
|
bitfld.long 0x38 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
|
|
bitfld.long 0x38 16. "SYNCEN,Synchronization enable" "0,1"
|
|
bitfld.long 0x38 9. "EVGEN,Event generation enable" "0,1"
|
|
bitfld.long 0x38 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x38 0.--7. 1. "MUXID,Multiplexer input identification"
|
|
line.long 0x3C "RM_CH15CFG,Request multiplexer channel 15 configuration regist"
|
|
hexmask.long.byte 0x3C 24.--28. 1. "SYNCID,Synchronization input identification"
|
|
hexmask.long.byte 0x3C 19.--23. 1. "NBR,Number of DMA requests to forward"
|
|
bitfld.long 0x3C 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
|
|
bitfld.long 0x3C 16. "SYNCEN,Synchronization enable" "0,1"
|
|
bitfld.long 0x3C 9. "EVGEN,Event generation enable" "0,1"
|
|
bitfld.long 0x3C 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "MUXID,Multiplexer input identification"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "RM_INTF,Request multiplexer channel interrupt flag register"
|
|
bitfld.long 0x0 15. "SOIF15,Synchronization overrun event flag of request multiplexer channel 15" "0,1"
|
|
bitfld.long 0x0 14. "SOIF14,Synchronization overrun event flag of request multiplexer channel 14" "0,1"
|
|
bitfld.long 0x0 13. "SOIF13,Synchronization overrun event flag of request multiplexer channel 13" "0,1"
|
|
bitfld.long 0x0 12. "SOIF12,Synchronization overrun event flag of request multiplexer channel 12" "0,1"
|
|
bitfld.long 0x0 11. "SOIF11,Synchronization overrun event flag of request multiplexer channel 11" "0,1"
|
|
bitfld.long 0x0 10. "SOIF10,Synchronization overrun event flag of request multiplexer channel 10" "0,1"
|
|
bitfld.long 0x0 9. "SOIF9,Synchronization overrun event flag of request multiplexer channel 9" "0,1"
|
|
bitfld.long 0x0 8. "SOIF8,Synchronization overrun event flag of request multiplexer channel 8" "0,1"
|
|
bitfld.long 0x0 7. "SOIF7,Synchronization overrun event flag of request multiplexer channel 7" "0,1"
|
|
bitfld.long 0x0 6. "SOIF6,Synchronization overrun event flag of request multiplexer channel 6" "0,1"
|
|
bitfld.long 0x0 5. "SOIF5,Synchronization overrun event flag of request multiplexer channel 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SOIF4,Synchronization overrun event flag of request multiplexer channel 4" "0,1"
|
|
bitfld.long 0x0 3. "SOIF3,Synchronization overrun event flag of request multiplexer channel 3" "0,1"
|
|
bitfld.long 0x0 2. "SOIF2,Synchronization overrun event flag of request multiplexer channel 2" "0,1"
|
|
bitfld.long 0x0 1. "SOIF1,Synchronization overrun event flag of request multiplexer channel 1" "0,1"
|
|
bitfld.long 0x0 0. "SOIF0,Synchronization overrun event flag of request multiplexer channel 0" "0,1"
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "RM_INTC,Request multiplexer channel interrupt flag clear register"
|
|
bitfld.long 0x0 15. "SOIFC15,Clear bit for synchronization overrun event flag of request multiplexer channel 15" "0,1"
|
|
bitfld.long 0x0 14. "SOIFC14,Clear bit for synchronization overrun event flag of request multiplexer channel 14" "0,1"
|
|
bitfld.long 0x0 13. "SOIFC13,Clear bit for synchronization overrun event flag of request multiplexer channel 13" "0,1"
|
|
bitfld.long 0x0 12. "SOIFC12,Clear bit for synchronization overrun event flag of request multiplexer channel 12" "0,1"
|
|
bitfld.long 0x0 11. "SOIFC11,Clear bit for synchronization overrun event flag of request multiplexer channel 11" "0,1"
|
|
bitfld.long 0x0 10. "SOIFC10,Clear bit for synchronization overrun event flag of request multiplexer channel 10" "0,1"
|
|
bitfld.long 0x0 9. "SOIFC9,Clear bit for synchronization overrun event flag of request multiplexer channel 9" "0,1"
|
|
bitfld.long 0x0 8. "SOIFC8,Clear bit for synchronization overrun event flag of request multiplexer channel 8" "0,1"
|
|
bitfld.long 0x0 7. "SOIFC7,Clear bit for synchronization overrun event flag of request multiplexer channel 7" "0,1"
|
|
bitfld.long 0x0 6. "SOIFC6,Clear bit for synchronization overrun event flag of request multiplexer channel 6" "0,1"
|
|
bitfld.long 0x0 5. "SOIFC5,Clear bit for synchronization overrun event flag of request multiplexer channel 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SOIFC4,Clear bit for synchronization overrun event flag of request multiplexer channel 4" "0,1"
|
|
bitfld.long 0x0 3. "SOIFC3,Clear bit for synchronization overrun event flag of request multiplexer channel 3" "0,1"
|
|
bitfld.long 0x0 2. "SOIFC2,Clear bit for synchronization overrun event flag of request multiplexer channel 2" "0,1"
|
|
bitfld.long 0x0 1. "SOIFC1,Clear bit for synchronization overrun event flag of request multiplexer channel 1" "0,1"
|
|
bitfld.long 0x0 0. "SOIFC0,Clear bit for synchronization overrun event flag of request multiplexer channel 0" "0,1"
|
|
group.long 0x100++0x1F
|
|
line.long 0x0 "RG_CH0CFG,Request generator channel 0 configuration regist"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBRG,Number of DMA requests to be generated"
|
|
bitfld.long 0x0 17.--18. "RGTP,DMAMUX request generator trigger polarity" "0,1,2,3"
|
|
bitfld.long 0x0 16. "RGEN,DMAMUX request generator channel x enable" "0,1"
|
|
bitfld.long 0x0 8. "TOIE,Trigger overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TID,Trigger input identification"
|
|
line.long 0x4 "RG_CH1CFG,Request generator channel 1 configuration regist"
|
|
hexmask.long.byte 0x4 19.--23. 1. "NBRG,Number of DMA requests to be generated"
|
|
bitfld.long 0x4 17.--18. "RGTP,DMAMUX request generator trigger polarity" "0,1,2,3"
|
|
bitfld.long 0x4 16. "RGEN,DMAMUX request generator channel x enable" "0,1"
|
|
bitfld.long 0x4 8. "TOIE,Trigger overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "TID,Trigger input identification"
|
|
line.long 0x8 "RG_CH2CFG,Request generator channel 2 configuration regist"
|
|
hexmask.long.byte 0x8 19.--23. 1. "NBRG,Number of DMA requests to be generated"
|
|
bitfld.long 0x8 17.--18. "RGTP,DMAMUX request generator trigger polarity" "0,1,2,3"
|
|
bitfld.long 0x8 16. "RGEN,DMAMUX request generator channel x enable" "0,1"
|
|
bitfld.long 0x8 8. "TOIE,Trigger overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x8 0.--5. 1. "TID,Trigger input identification"
|
|
line.long 0xC "RG_CH3CFG,Request generator channel 3 configuration regist"
|
|
hexmask.long.byte 0xC 19.--23. 1. "NBRG,Number of DMA requests to be generated"
|
|
bitfld.long 0xC 17.--18. "RGTP,DMAMUX request generator trigger polarity" "0,1,2,3"
|
|
bitfld.long 0xC 16. "RGEN,DMAMUX request generator channel x enable" "0,1"
|
|
bitfld.long 0xC 8. "TOIE,Trigger overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0xC 0.--5. 1. "TID,Trigger input identification"
|
|
line.long 0x10 "RG_CH4CFG,Request generator channel 4 configuration regist"
|
|
hexmask.long.byte 0x10 19.--23. 1. "NBRG,Number of DMA requests to be generated"
|
|
bitfld.long 0x10 17.--18. "RGTP,DMAMUX request generator trigger polarity" "0,1,2,3"
|
|
bitfld.long 0x10 16. "RGEN,DMAMUX request generator channel x enable" "0,1"
|
|
bitfld.long 0x10 8. "TOIE,Trigger overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x10 0.--5. 1. "TID,Trigger input identification"
|
|
line.long 0x14 "RG_CH5CFG,Request generator channel 5 configuration regist"
|
|
hexmask.long.byte 0x14 19.--23. 1. "NBRG,Number of DMA requests to be generated"
|
|
bitfld.long 0x14 17.--18. "RGTP,DMAMUX request generator trigger polarity" "0,1,2,3"
|
|
bitfld.long 0x14 16. "RGEN,DMAMUX request generator channel x enable" "0,1"
|
|
bitfld.long 0x14 8. "TOIE,Trigger overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x14 0.--5. 1. "TID,Trigger input identification"
|
|
line.long 0x18 "RG_CH6CFG,Request generator channel 6 configuration regist"
|
|
hexmask.long.byte 0x18 19.--23. 1. "NBRG,Number of DMA requests to be generated"
|
|
bitfld.long 0x18 17.--18. "RGTP,DMAMUX request generator trigger polarity" "0,1,2,3"
|
|
bitfld.long 0x18 16. "RGEN,DMAMUX request generator channel x enable" "0,1"
|
|
bitfld.long 0x18 8. "TOIE,Trigger overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x18 0.--5. 1. "TID,Trigger input identification"
|
|
line.long 0x1C "RG_CH7CFG,Request generator channel 7 configuration regist"
|
|
hexmask.long.byte 0x1C 19.--23. 1. "NBRG,Number of DMA requests to be generated"
|
|
bitfld.long 0x1C 17.--18. "RGTP,DMAMUX request generator trigger polarity" "0,1,2,3"
|
|
bitfld.long 0x1C 16. "RGEN,DMAMUX request generator channel x enable" "0,1"
|
|
bitfld.long 0x1C 8. "TOIE,Trigger overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "TID,Trigger input identification"
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "RG_INTF,Request generator channel interrupt flag register"
|
|
bitfld.long 0x0 7. "TOIF7,Trigger overrun event flag of request generator channel 7" "0,1"
|
|
bitfld.long 0x0 6. "TOIF6,Trigger overrun event flag of request generator channel 6" "0,1"
|
|
bitfld.long 0x0 5. "TOIF5,Trigger overrun event flag of request generator channel 5" "0,1"
|
|
bitfld.long 0x0 4. "TOIF4,Trigger overrun event flag of request generator channel 4" "0,1"
|
|
bitfld.long 0x0 3. "TOIF3,Trigger overrun event flag of request generator channel 3" "0,1"
|
|
bitfld.long 0x0 2. "TOIF2,Trigger overrun event flag of request generator channel 2" "0,1"
|
|
bitfld.long 0x0 1. "TOIF1,Trigger overrun event flag of request generator channel 1" "0,1"
|
|
bitfld.long 0x0 0. "TOIF0,Trigger overrun event flag of request generator channel 0" "0,1"
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "RG_INTC,Rquest generator channel interrupt flag clear register"
|
|
bitfld.long 0x0 7. "TOIFC7,Clear bit for trigger overrun event flag of request generator channel 7" "0,1"
|
|
bitfld.long 0x0 6. "TOIFC6,Clear bit for trigger overrun event flag of request generator channel 6" "0,1"
|
|
bitfld.long 0x0 5. "TOIFC5,Clear bit for trigger overrun event flag of request generator channel 5" "0,1"
|
|
bitfld.long 0x0 4. "TOIFC4,Clear bit for trigger overrun event flag of request generator channel 4" "0,1"
|
|
bitfld.long 0x0 3. "TOIFC3,Clear bit for trigger overrun event flag of request generator channel 3" "0,1"
|
|
bitfld.long 0x0 2. "TOIFC2,Clear bit for trigger overrun event flag of request generator channel 2" "0,1"
|
|
bitfld.long 0x0 1. "TOIFC1,Clear bit for trigger overrun event flag of request generator channel 1" "0,1"
|
|
bitfld.long 0x0 0. "TOIFC0,Clear bit for trigger overrun event flag of request generator channel 0" "0,1"
|
|
tree.end
|
|
tree "EDOUT (Encoder Divided-Output Controller)"
|
|
base ad:0x40018800
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 0. "POL,The active polarity of the B-phase output signal selection" "0,1"
|
|
line.long 0x4 "ENABLE,Enable register"
|
|
bitfld.long 0x4 0. "EDOUTEN,EDOUT enable bit" "0,1"
|
|
line.long 0x8 "LOC,Location register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LOCMAX,This bits set the maximum location value for one rotation"
|
|
line.long 0xC "OCNT,Output counter register"
|
|
hexmask.long.word 0xC 16.--31. 1. "PDC,These bits set the phase difference between the A-phase signal and the B-phase signal for the next carrier cycle"
|
|
hexmask.long.word 0xC 0.--15. 1. "EDGC,These bits set the number of edges of the A-phase signal and the B-phase signal for the next carrier cycle"
|
|
line.long 0x10 "LCNT,Location counter register"
|
|
hexmask.long.word 0x10 0.--15. 1. "LOCCNT,These bits are used to set the current position value"
|
|
line.long 0x14 "ZCR,Z-PHASE configure register"
|
|
bitfld.long 0x14 24. "ZOMD,Z-PHASE output mode" "0,1"
|
|
hexmask.long.byte 0x14 16.--23. 1. "ZOWH,Z-PHASE output width"
|
|
hexmask.long.word 0x14 0.--15. 1. "ZOSP,Z-PHASE output start position"
|
|
tree.end
|
|
tree "EFUSE (Electronic Fuse)"
|
|
base ad:0x40022800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTL,Control register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "AES_KEY_CRC,8-bits CRC calculation result value of AES key bits"
|
|
bitfld.long 0x0 19. "PVIE,Program voltage setting error interrupt enable" "0,1"
|
|
bitfld.long 0x0 18. "RDIE,Read completed interrupt enable" "0,1"
|
|
bitfld.long 0x0 17. "PGIE,Program completed interrupt enable" "0,1"
|
|
bitfld.long 0x0 16. "IAERRIE,Illegal access error interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MPVEN,Monitor program voltage function enable" "0,1"
|
|
bitfld.long 0x0 1. "EFRW,The selection of EFUSE operation" "0,1"
|
|
bitfld.long 0x0 0. "EFSTR,Start EFUSE operation" "0,1"
|
|
line.long 0x4 "ADDR,Address register"
|
|
hexmask.long.byte 0x4 10.--14. 1. "EFSIZE,Read or write EFUSE data size"
|
|
hexmask.long.word 0x4 0.--9. 1. "EFADDR,Read or write EFUSE data start address"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "STAT,Status register"
|
|
bitfld.long 0x0 4. "LDO_RDY,EFUSE LDO ready signal" "0,1"
|
|
bitfld.long 0x0 3. "PVIF,Program voltage setting error flag" "0,1"
|
|
bitfld.long 0x0 2. "RDIF,Read completed flag" "0,1"
|
|
bitfld.long 0x0 1. "PGIF,Program completed flag" "0,1"
|
|
bitfld.long 0x0 0. "IAERRIF,Illegal access error flag" "0,1"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "STATC,Status flag clear register"
|
|
bitfld.long 0x0 3. "PVIC,Clear bit for program voltage setting error interrupt flag" "0,1"
|
|
bitfld.long 0x0 2. "RDIC,Clear bit for read completed interrupt flag" "0,1"
|
|
bitfld.long 0x0 1. "PGIC,Clear bit for program completed interrupt flag" "0,1"
|
|
bitfld.long 0x0 0. "IAERRIC,Clear bit for illegal access error interrupt flag" "0,1"
|
|
line.long 0x4 "USER_CTL,User control register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "SCR_AREA_END,Secure user area end address bits"
|
|
hexmask.long.byte 0x4 16.--23. 1. "SCR_AREA_START,Secure user area start address bits"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x4 14.--15. "ESPI_START_MODE,External SPI flash startup mode" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x4 13. "SCR,Secure mode enable" "0,1"
|
|
bitfld.long 0x4 12. "SPC_H,Configure security protection to level high" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "SPC_L,Configure security protection to level low" "0,1"
|
|
bitfld.long 0x4 10. "JTAGNSW,SW or JTAG debugger select" "0,1"
|
|
bitfld.long 0x4 8.--9. "NDBG,Debugging permission setting" "0,1,2,3"
|
|
bitfld.long 0x4 4. "UDLK,EFUSE_USER_DATAx register lock bit" "0,1"
|
|
bitfld.long 0x4 3. "AESEN,Lock EFUSE_AES_KEYx register and enable AES decrypt function" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "UCLK,Low 16 bits of EFUSE_USER_CTL register lock bit" "0,1"
|
|
bitfld.long 0x4 1. "SCRLK,Secure userarea address lock bit" "0,1"
|
|
bitfld.long 0x4 0. "DPLK,EFUSE_DPx register lock bit" "0,1"
|
|
line.long 0x8 "MCU_RSV,MCU reserved register"
|
|
hexmask.long.byte 0x8 24.--31. 1. "DCRP_AREA_END,DCRP area end address bits"
|
|
hexmask.long.byte 0x8 16.--23. 1. "DCRP_AREA_START,DCRP area start address bits"
|
|
hexmask.long.byte 0x8 10.--15. 1. "MCU_RSV,MCU reserved data"
|
|
bitfld.long 0x8 9. "DCRPLK,DCRP area address lock bit" "0,1"
|
|
bitfld.long 0x8 8. "MCURSVLK,Low 16 bits of EFUSE_MCU_RSV register lock bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "VFIMG,Firmware image verification enable bit" "0,1"
|
|
bitfld.long 0x8 6. "DISLFI,Licensed firmware install ( LFI ) disable" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x8 0. "AESNCAU,AES key for cau configuration bit" "0,1"
|
|
endif
|
|
line.long 0xC "DP0,Debug password register 0"
|
|
sif (cpuis("GD32H75E*"))
|
|
hexmask.long 0xC 0.--31. 1. "DP,EFUSE debug password value."
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
hexmask.long 0xC 0.--31. 1. "DPx,Efuse debug password value"
|
|
endif
|
|
line.long 0x10 "DP1,Debug password register 1"
|
|
sif (cpuis("GD32H75E*"))
|
|
hexmask.long 0x10 0.--31. 1. "DP,EFUSE debug password value."
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
hexmask.long 0x10 0.--31. 1. "DPx,Efuse debug password value"
|
|
endif
|
|
wgroup.long 0x24++0xF
|
|
line.long 0x0 "AES_KEY0,Firmware AES key register 0"
|
|
sif (cpuis("GD32H75E*"))
|
|
hexmask.long 0x0 0.--31. 1. "AESKEY,EFUSE AES key value."
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
hexmask.long 0x0 0.--31. 1. "AESKEYx,Efuse AES key value"
|
|
endif
|
|
line.long 0x4 "AES_KEY1,Firmware AES key register 1"
|
|
sif (cpuis("GD32H75E*"))
|
|
hexmask.long 0x4 0.--31. 1. "AESKEY,EFUSE AES key value."
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
hexmask.long 0x4 0.--31. 1. "AESKEYx,Efuse AES key value"
|
|
endif
|
|
line.long 0x8 "AES_KEY2,Firmware AES key register 2"
|
|
sif (cpuis("GD32H75E*"))
|
|
hexmask.long 0x8 0.--31. 1. "AESKEY,EFUSE AES key value."
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
hexmask.long 0x8 0.--31. 1. "AESKEYx,Efuse AES key value"
|
|
endif
|
|
line.long 0xC "AES_KEY3,Firmware AES key register 3"
|
|
sif (cpuis("GD32H75E*"))
|
|
hexmask.long 0xC 0.--31. 1. "AESKEY,EFUSE AES key value."
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
hexmask.long 0xC 0.--31. 1. "AESKEYx,Efuse AES key value"
|
|
endif
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "USER_DATA0,User data register 0"
|
|
sif (cpuis("GD32H75E*"))
|
|
hexmask.long 0x0 0.--31. 1. "USERDATA,EFUSE USER_DATA value."
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
hexmask.long 0x0 0.--31. 1. "USERDATAx,Efuse USER_DATA value"
|
|
endif
|
|
line.long 0x4 "USER_DATA1,User data register 1"
|
|
sif (cpuis("GD32H75E*"))
|
|
hexmask.long 0x4 0.--31. 1. "USERDATA,EFUSE USER_DATA value."
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
hexmask.long 0x4 0.--31. 1. "USERDATAx,Efuse USER_DATA value"
|
|
endif
|
|
line.long 0x8 "USER_DATA2,User data register 2"
|
|
sif (cpuis("GD32H75E*"))
|
|
hexmask.long 0x8 0.--31. 1. "USERDATA,EFUSE USER_DATA value."
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
hexmask.long 0x8 0.--31. 1. "USERDATAx,Efuse USER_DATA value"
|
|
endif
|
|
line.long 0xC "USER_DATA3,User data register 3"
|
|
sif (cpuis("GD32H75E*"))
|
|
hexmask.long 0xC 0.--31. 1. "USERDATA,EFUSE USER_DATA value."
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
hexmask.long 0xC 0.--31. 1. "USERDATAx,Efuse USER_DATA value"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
tree "ENET (Ethernet)"
|
|
base ad:0x0
|
|
tree "ENET0"
|
|
tree "ENET0_DMA (DMA Controller Operation)"
|
|
base ad:0x40029000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "DMA_BCTL,Ethernet DMA bus control register"
|
|
bitfld.long 0x0 26. "MB,Mixed burst" "0,1"
|
|
bitfld.long 0x0 25. "AA,Address-aligned" "0,1"
|
|
bitfld.long 0x0 24. "FPBL,Four times PGBL mode" "0,1"
|
|
bitfld.long 0x0 23. "UIP,Use independent PGBL" "0,1"
|
|
hexmask.long.byte 0x0 17.--22. 1. "RXDP,Rx DMA PGBL"
|
|
bitfld.long 0x0 16. "FB,Fixed burst" "0,1"
|
|
bitfld.long 0x0 14.--15. "RTPR,RxDMA and TxDMA transfer priority ratio" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--13. 1. "PGBL,Programmable burst length"
|
|
bitfld.long 0x0 7. "DFM,Descriptor format mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 2.--6. 1. "DPSL,Descriptor skip length"
|
|
bitfld.long 0x0 1. "DAB,DMA Arbitration" "0,1"
|
|
bitfld.long 0x0 0. "SWR,Software reset" "0,1"
|
|
line.long 0x4 "DMA_TPEN,Ethernet DMA transmit poll enable register"
|
|
hexmask.long 0x4 0.--31. 1. "TPE,Transmit poll enable"
|
|
line.long 0x8 "DMA_RPEN,Ethernet DMA receive poll enable register"
|
|
hexmask.long 0x8 0.--31. 1. "RPE,Receive poll enable"
|
|
line.long 0xC "DMA_RDTADDR,Ethernet DMA receive descriptor table address register"
|
|
hexmask.long 0xC 0.--31. 1. "SRT,Start address of receive table"
|
|
line.long 0x10 "DMA_TDTADDR,Ethernet DMA transmit descriptor table address register"
|
|
hexmask.long 0x10 0.--31. 1. "STT,Start address of transmit table"
|
|
line.long 0x14 "DMA_STAT,Ethernet DMA status register"
|
|
rbitfld.long 0x14 29. "TST,Time stamp trigger status" "0,1"
|
|
rbitfld.long 0x14 28. "WUM,WUM status" "0,1"
|
|
rbitfld.long 0x14 27. "MSC,MSC status" "0,1"
|
|
rbitfld.long 0x14 23.--25. "EB,Error bits status" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x14 20.--22. "TP,Transmit process state" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x14 17.--19. "RP,Receive process state" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 16. "NI,Normal interrupt summary" "0,1"
|
|
bitfld.long 0x14 15. "AI,Abnormal interrupt summary" "0,1"
|
|
bitfld.long 0x14 14. "ER,Early receive status" "0,1"
|
|
newline
|
|
bitfld.long 0x14 13. "FBE,Fatal bus error status" "0,1"
|
|
bitfld.long 0x14 10. "ET,Early transmit status" "0,1"
|
|
bitfld.long 0x14 9. "RWT,Receive watchdog timeout status" "0,1"
|
|
bitfld.long 0x14 8. "RPS,Receive process stopped status" "0,1"
|
|
bitfld.long 0x14 7. "RBU,Receive buffer unavailable status" "0,1"
|
|
bitfld.long 0x14 6. "RS,Receive status" "0,1"
|
|
bitfld.long 0x14 5. "TU,Transmit underflow status" "0,1"
|
|
bitfld.long 0x14 4. "RO,Receive overflow status" "0,1"
|
|
bitfld.long 0x14 3. "TJT,Transmit jabber timeout status" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "TBU,Transmit buffer unavailable status" "0,1"
|
|
bitfld.long 0x14 1. "TPS,Transmit process stopped status" "0,1"
|
|
bitfld.long 0x14 0. "TS,Transmit status" "0,1"
|
|
line.long 0x18 "DMA_CTL,Ethernet DMA control register"
|
|
bitfld.long 0x18 26. "DTCERFD,Dropping of TCP/IP checksum error frames disable" "0,1"
|
|
bitfld.long 0x18 25. "RSFD,Receive Store-and-Forward" "0,1"
|
|
bitfld.long 0x18 24. "DAFRF,Disable flushing of received frames" "0,1"
|
|
bitfld.long 0x18 21. "TSFD,Transmit Store-and-Forward" "0,1"
|
|
bitfld.long 0x18 20. "FTF,Flush transmit FIFO" "0,1"
|
|
bitfld.long 0x18 14.--16. "TTHC,Transmit threshold control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 13. "STE,Start/stop transmission enable" "0,1"
|
|
bitfld.long 0x18 7. "FERF,Forward error frames" "0,1"
|
|
bitfld.long 0x18 6. "FUF,Forward undersized good frames" "0,1"
|
|
newline
|
|
bitfld.long 0x18 3.--4. "RTHC,Receive threshold control" "0,1,2,3"
|
|
bitfld.long 0x18 2. "OSF,Operate on second frame" "0,1"
|
|
bitfld.long 0x18 1. "SRE,Start/stop receive enable" "0,1"
|
|
line.long 0x1C "DMA_INTEN,Ethernet DMA interrupt enable register"
|
|
bitfld.long 0x1C 16. "NIE,Normal interrupt summary enable" "0,1"
|
|
bitfld.long 0x1C 15. "AIE,Abnormal interrupt summary enable" "0,1"
|
|
bitfld.long 0x1C 14. "ERIE,Early receive interrupt enable" "0,1"
|
|
bitfld.long 0x1C 13. "FBEIE,Fatal bus error interrupt enable" "0,1"
|
|
bitfld.long 0x1C 10. "ETIE,Early transmit interrupt enable" "0,1"
|
|
bitfld.long 0x1C 9. "RWTIE,receive watchdog timeout interrupt enable" "0,1"
|
|
bitfld.long 0x1C 8. "RPSIE,Receive process stopped interrupt enable" "0,1"
|
|
bitfld.long 0x1C 7. "RBUIE,Receive buffer unavailable interrupt enable" "0,1"
|
|
bitfld.long 0x1C 6. "RIE,Receive interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 5. "TUIE,Transmit underflow interrupt enable" "0,1"
|
|
bitfld.long 0x1C 4. "ROIE,Receive overflow interrupt enable" "0,1"
|
|
bitfld.long 0x1C 3. "TJTIE,Transmit jabber timeout interrupt enable" "0,1"
|
|
bitfld.long 0x1C 2. "TBUIE,Transmit buffer unavailable interrupt enable" "0,1"
|
|
bitfld.long 0x1C 1. "TPSIE,Transmit process stopped interrupt enable" "0,1"
|
|
bitfld.long 0x1C 0. "TIE,Transmit interrupt enable" "0,1"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "DMA_MFBOCNT,Ethernet DMA missed frame and buffer overflow counter register"
|
|
hexmask.long.word 0x0 17.--27. 1. "MSFA,Missed frames by the application"
|
|
hexmask.long.word 0x0 0.--15. 1. "MSFC,Missed frames by the controller"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "DMA_RSWDC,Ethernet DMA receive state watchdog counter register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WDCFRS,Watchdog counter for receive status (RS)"
|
|
rgroup.long 0x48++0xF
|
|
line.long 0x0 "DMA_CTDADDR,DMA current transmit descriptor address register"
|
|
hexmask.long 0x0 0.--31. 1. "TDAP,transmit descriptor address pointer"
|
|
line.long 0x4 "DMA_CRDADDR,Ethernet DMA current receive descriptor address register"
|
|
hexmask.long 0x4 0.--31. 1. "RDAP,Receive descriptor address pointer"
|
|
line.long 0x8 "DMA_CTBADDR,Ethernet DMA current transmit buffer address register"
|
|
hexmask.long 0x8 0.--31. 1. "TBAP,Transmit buffer address pointer"
|
|
line.long 0xC "DMA_CRBADDR,Ethernet DMA current receive buffer address register"
|
|
hexmask.long 0xC 0.--31. 1. "RBAP,receive buffer address pointer"
|
|
tree.end
|
|
tree "ENET0_MAC (Media Access Control)"
|
|
base ad:0x40028000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "MAC_CFG,Ethernet MAC configuration register (MAC_CFG)"
|
|
bitfld.long 0x0 25. "TFCD,Type Frame CRC Dropping" "0,1"
|
|
bitfld.long 0x0 23. "WDD,Watchdog disable" "0,1"
|
|
bitfld.long 0x0 22. "JBD,Jabber disable" "0,1"
|
|
bitfld.long 0x0 17.--19. "IGBS,Inter frame gap bit selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16. "CSD,Carrier sense disable" "0,1"
|
|
bitfld.long 0x0 14. "SPD,Fast Ethernet speed" "0,1"
|
|
bitfld.long 0x0 13. "ROD,Receive own disable" "0,1"
|
|
bitfld.long 0x0 12. "LBM,Loopback mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DPM,Duplex mode" "0,1"
|
|
bitfld.long 0x0 10. "IPFCO,IP frame checksum offload" "0,1"
|
|
bitfld.long 0x0 9. "RTD,Retry disable" "0,1"
|
|
bitfld.long 0x0 7. "APCD,Automatic pad/CRC drop" "0,1"
|
|
bitfld.long 0x0 5.--6. "BOL,Back-off limit" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DFC,Deferral check" "0,1"
|
|
bitfld.long 0x0 3. "TEN,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "REN,Receiver enable" "0,1"
|
|
line.long 0x4 "MAC_FRMF,Ethernet MAC frame filter register (MAC_FRMF)"
|
|
bitfld.long 0x4 31. "FAR,Frames all receive" "0,1"
|
|
bitfld.long 0x4 10. "HPFLT,Hash or perfect filter" "0,1"
|
|
bitfld.long 0x4 9. "SAFLT,Source address filter" "0,1"
|
|
bitfld.long 0x4 8. "SAIFLT,Source address inverse filtering" "0,1"
|
|
bitfld.long 0x4 6.--7. "PCFRM,Pass control frames" "0,1,2,3"
|
|
bitfld.long 0x4 5. "BFRMD,Broadcast frames disable" "0,1"
|
|
bitfld.long 0x4 4. "MFD,multicast filter disable" "0,1"
|
|
bitfld.long 0x4 3. "DAIFLT,Destination address inverse filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "HMF,Hash multicast filter" "0,1"
|
|
bitfld.long 0x4 1. "HUF,Hash unicast filter" "0,1"
|
|
bitfld.long 0x4 0. "PM,Promiscuous mode" "0,1"
|
|
line.long 0x8 "MAC_HLH,Ethernet MAC hash list high register"
|
|
hexmask.long 0x8 0.--31. 1. "HLH,Hash list high"
|
|
line.long 0xC "MAC_HLL,Ethernet MAC hash list low register"
|
|
hexmask.long 0xC 0.--31. 1. "HLL,Hash list low"
|
|
line.long 0x10 "MAC_PHY_CTL,Ethernet MAC PHY control register (MAC_PHY_CTL)"
|
|
hexmask.long.byte 0x10 11.--15. 1. "PA,PHY address"
|
|
hexmask.long.byte 0x10 6.--10. 1. "PR,PHY register"
|
|
bitfld.long 0x10 2.--4. "CLR,Clock range" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "PW,PHY write" "0,1"
|
|
bitfld.long 0x10 0. "PB,PHY busy" "0,1"
|
|
line.long 0x14 "MAC_PHY_DATA,Ethernet MAC MII data register (MAC_PHY_DATA)"
|
|
hexmask.long.word 0x14 0.--15. 1. "PD,PHY data"
|
|
line.long 0x18 "MAC_FCTL,Ethernet MAC flow control register (MAC_FCTL)"
|
|
hexmask.long.word 0x18 16.--31. 1. "PTM,Pause time"
|
|
bitfld.long 0x18 7. "DZQP,Disable Zero-quanta pause" "0,1"
|
|
bitfld.long 0x18 4.--5. "PLTS,Pause low threshold" "0,1,2,3"
|
|
bitfld.long 0x18 3. "UPFDT,Unicast pause frame detect" "0,1"
|
|
bitfld.long 0x18 2. "RFCEN,Receive flow control enable" "0,1"
|
|
bitfld.long 0x18 1. "TFCEN,Transmit flow control enable" "0,1"
|
|
bitfld.long 0x18 0. "FLCB_BKPA,Flow control busy/back pressure activate" "0,1"
|
|
line.long 0x1C "MAC_VLT,Ethernet MAC VLAN tag register (MAC_VLT)"
|
|
bitfld.long 0x1C 16. "VLTC,12-bit VLAN tag comparison" "0,1"
|
|
hexmask.long.word 0x1C 0.--15. 1. "VLTI,VLAN tag identifier (for receive frames)"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "MAC_RWFF,Ethernet MAC remote wakeup frame filter register (MAC_RWFF)"
|
|
line.long 0x4 "MAC_WUM,Ethernet MAC wakeup management register (MAC_WUM)"
|
|
bitfld.long 0x4 31. "WUFFRPR,Wakeup frame filter register pointer reset" "0,1"
|
|
bitfld.long 0x4 9. "GU,Global unicast" "0,1"
|
|
bitfld.long 0x4 6. "WUFR,Wakeup frame received" "0,1"
|
|
bitfld.long 0x4 5. "MPKR,Magic packet received" "0,1"
|
|
bitfld.long 0x4 2. "WFEN,Wakeup frame enable" "0,1"
|
|
bitfld.long 0x4 1. "MPEN,Magic Packet enable" "0,1"
|
|
bitfld.long 0x4 0. "PWD,Power down" "0,1"
|
|
rgroup.long 0x34++0x7
|
|
line.long 0x0 "MAC_DBG,Ethernet MAC debug register (MAC_DBG)"
|
|
bitfld.long 0x0 25. "TXFF,TxFIFO Full flag" "0,1"
|
|
bitfld.long 0x0 24. "TXFNE,TxFIFO not empty flag" "0,1"
|
|
bitfld.long 0x0 22. "TXFW,TxFIFO is writing" "0,1"
|
|
bitfld.long 0x0 20.--21. "TXFRS,TxFIFO read operation status" "0,1,2,3"
|
|
bitfld.long 0x0 19. "PCS,Pause condition status" "0,1"
|
|
bitfld.long 0x0 17.--18. "SOMT,Status of MAC transmitter" "0,1,2,3"
|
|
bitfld.long 0x0 16. "MTNI,MAC transmit state not idle" "0,1"
|
|
bitfld.long 0x0 8.--9. "RXFS,RxFIFO state" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 5.--6. "RXFRS,RxFIFO read operation status" "0,1,2,3"
|
|
bitfld.long 0x0 4. "RXFW,RxFIFO is writing" "0,1"
|
|
bitfld.long 0x0 1.--2. "RXAFS,Rx asynchronous FIFO status" "0,1,2,3"
|
|
bitfld.long 0x0 0. "MRNI,MAC receive state not idle" "0,1"
|
|
line.long 0x4 "MAC_INTF,Ethernet MAC interrupt flag register (MAC_INTF)"
|
|
bitfld.long 0x4 9. "TMST,Time stamp trigger status" "0,1"
|
|
bitfld.long 0x4 6. "MSCT,MSC transmit status" "0,1"
|
|
bitfld.long 0x4 5. "MSCR,MSC receive status" "0,1"
|
|
bitfld.long 0x4 4. "MSC,MSC status" "0,1"
|
|
bitfld.long 0x4 3. "WUM,WUM status" "0,1"
|
|
group.long 0x3C++0x23
|
|
line.long 0x0 "MAC_INTMSK,Ethernet MAC interrupt mask register (MAC_INTMSK)"
|
|
bitfld.long 0x0 9. "TMSTIM,Time stamp trigger interrupt mask" "0,1"
|
|
bitfld.long 0x0 3. "WUMIM,WUM interrupt mask" "0,1"
|
|
line.long 0x4 "MAC_ADDR0H,Ethernet MAC address 0 high register (MAC_ADDR0H)"
|
|
bitfld.long 0x4 31. "MO,Always 1" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADDR0H,MAC address0 high"
|
|
line.long 0x8 "MAC_ADDR0L,Ethernet MAC address 0 low register"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR0L,MAC address0 low"
|
|
line.long 0xC "MAC_ADDR1H,Ethernet MAC address 1 high register (MAC_ADDR1H)"
|
|
bitfld.long 0xC 31. "AFE,Address filter enable" "0,1"
|
|
bitfld.long 0xC 30. "SAF,Source address filter" "0,1"
|
|
hexmask.long.byte 0xC 24.--29. 1. "MB,Mask byte"
|
|
hexmask.long.word 0xC 0.--15. 1. "ADDR1H,MAC address1 high"
|
|
line.long 0x10 "MAC_ADDR1L,Ethernet MAC address1 low register"
|
|
hexmask.long 0x10 0.--31. 1. "ADDR1L,MAC address1 low"
|
|
line.long 0x14 "MAC_ADDR2H,Ethernet MAC address 2 high register (MAC_ADDR2H)"
|
|
bitfld.long 0x14 31. "AFE,Address filter enable" "0,1"
|
|
bitfld.long 0x14 30. "SAF,Source address filter" "0,1"
|
|
hexmask.long.byte 0x14 24.--29. 1. "MB,Mask byte"
|
|
hexmask.long.word 0x14 0.--15. 1. "ADDR2H,Ethernet MAC address 2 high register"
|
|
line.long 0x18 "MAC_ADDR2L,Ethernet MAC address 2 low register"
|
|
hexmask.long 0x18 0.--31. 1. "ADDR2L,MAC address2 low"
|
|
line.long 0x1C "MAC_ADDR3H,Ethernet MAC address 3 high register (MAC_ADDR3H)"
|
|
bitfld.long 0x1C 31. "AFE,Address filter enable" "0,1"
|
|
bitfld.long 0x1C 30. "SAF,Source address filter" "0,1"
|
|
hexmask.long.byte 0x1C 24.--29. 1. "MB,Mask byte"
|
|
hexmask.long.word 0x1C 0.--15. 1. "ADDR3H,MAC address3 high"
|
|
line.long 0x20 "MAC_ADDR3L,Ethernet MAC address 3 low register"
|
|
hexmask.long 0x20 0.--31. 1. "ADDR3L,MAC address3 low"
|
|
tree.end
|
|
tree "ENET0_MAC_FCTH (MAC flow control threshold register)"
|
|
base ad:0x40029080
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MAC_FCTH,Ethernet MAC flow control threshold register"
|
|
bitfld.long 0x0 4.--6. "RFD,Threshold of deactive flow control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "RFA,Threshold of active flow control" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "ENET0_MSC (MAC Statistics Counters)"
|
|
base ad:0x40028100
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MSC_CTL,Ethernet MSC control register (MSC_CTL)"
|
|
bitfld.long 0x0 5. "AFHPM,Almost full or half preset mode" "0,1"
|
|
bitfld.long 0x0 4. "PMC,Preset MSC counter" "0,1"
|
|
bitfld.long 0x0 3. "MCFZ,MSC counter freeze" "0,1"
|
|
bitfld.long 0x0 2. "RTOR,Reset on read" "0,1"
|
|
bitfld.long 0x0 1. "CTSR,Counter stop rollover" "0,1"
|
|
bitfld.long 0x0 0. "CTR,Counter reset" "0,1"
|
|
rgroup.long 0x4++0x7
|
|
line.long 0x0 "MSC_RINTF,Ethernet MSC receive interrupt flag register (MSC_RINTF)"
|
|
bitfld.long 0x0 17. "RGUF,Received Good Unicast Frames" "0,1"
|
|
bitfld.long 0x0 6. "RFAE,Received frames alignment error" "0,1"
|
|
bitfld.long 0x0 5. "RFCE,Received frames CRC error" "0,1"
|
|
line.long 0x4 "MSC_TINTF,Ethernet MSC transmit interrupt flag register (MSC_TINTF)"
|
|
bitfld.long 0x4 21. "TGF,Transmitted good frames" "0,1"
|
|
bitfld.long 0x4 15. "TGFMSC,Transmitted good frames more single collision" "0,1"
|
|
bitfld.long 0x4 14. "TGFSC,Transmitted good frames single collision" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "MSC_RINTMSK,Ethernet MSC receive interrupt mask register (MSC_RINTMSK)"
|
|
bitfld.long 0x0 17. "RGUFIM,Received good unicast frames interrupt mask" "0,1"
|
|
bitfld.long 0x0 6. "RFAEIM,Received frames alignment error interrupt mask" "0,1"
|
|
bitfld.long 0x0 5. "RFCEIM,Received frame CRC error interrupt mask" "0,1"
|
|
line.long 0x4 "MSC_TINTMSK,Ethernet MSC transmit interrupt mask register (MSC_TINTMSK)"
|
|
bitfld.long 0x4 21. "TGFIM,Transmitted good frames interrupt mask" "0,1"
|
|
bitfld.long 0x4 15. "TGFMSCIM,Transmitted good frames more single interrupt collision mask" "0,1"
|
|
bitfld.long 0x4 14. "TGFSCIM,Transmitted good frames single collision interrupt mask" "0,1"
|
|
rgroup.long 0x4C++0x7
|
|
line.long 0x0 "MSC_SCCNT,Ethernet MSC transmitted good frames after a single collision counter"
|
|
hexmask.long 0x0 0.--31. 1. "SCC,Transmitted good frames after a single collision counter"
|
|
line.long 0x4 "MSC_MSCCNT,Ethernet MSC transmitted good frames after more than a single collision"
|
|
hexmask.long 0x4 0.--31. 1. "MSCC,Transmitted good frames after more than a single collision counter"
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x0 "MSC_TGFCNT,Ethernet MSC transmitted good frames counter register"
|
|
hexmask.long 0x0 0.--31. 1. "TGF,Transmitted good frames counter"
|
|
rgroup.long 0x94++0x7
|
|
line.long 0x0 "MSC_RFCECNT,Ethernet MSC received frames with CRC error counter register"
|
|
hexmask.long 0x0 0.--31. 1. "RFCER,Received frames with CRC error counter"
|
|
line.long 0x4 "MSC_RFAECNT,Ethernet MSC received frames with alignment error counter register"
|
|
hexmask.long 0x4 0.--31. 1. "RFAER,Received frames with alignment error counter"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "MSC_RGUFCNT,MSC received good unicast frames counter register"
|
|
hexmask.long 0x0 0.--31. 1. "RGUF,Received good unicast frames counter"
|
|
tree.end
|
|
tree "ENET0_PTP (Precision Time Protocol)"
|
|
base ad:0x40028700
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "PTP_TSCTL,Ethernet PTP time stamp control register (PTP_TSCTL)"
|
|
bitfld.long 0x0 18. "MAFEN,MAC address filter enable for PTP frame" "0,1"
|
|
bitfld.long 0x0 16.--17. "CKNT,Clock node type for time stamp" "0,1,2,3"
|
|
bitfld.long 0x0 15. "MNMSEN,Received master node message snapshot enable" "0,1"
|
|
bitfld.long 0x0 14. "ETMSEN,Received event type message snapshot enable" "0,1"
|
|
bitfld.long 0x0 13. "IP4SEN,Received IPv4 snapshot enable" "0,1"
|
|
bitfld.long 0x0 12. "IP6SEN,Received IPv6 snapshot enable" "0,1"
|
|
bitfld.long 0x0 11. "ESEN,Received Ethernet snapshot enable" "0,1"
|
|
bitfld.long 0x0 10. "PFSV,PTP frame snooping version" "0,1"
|
|
bitfld.long 0x0 9. "SCROM,Subsecond counter rollover mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ARFSEN,All received frames snapshot enable" "0,1"
|
|
bitfld.long 0x0 5. "TMSARU,Time stamp addend register update" "0,1"
|
|
bitfld.long 0x0 4. "TMSITEN,Time stamp interrupt trigger enable" "0,1"
|
|
bitfld.long 0x0 3. "TMSSTU,Time stamp system time update" "0,1"
|
|
bitfld.long 0x0 2. "TMSSTI,Time stamp system time initialize" "0,1"
|
|
bitfld.long 0x0 1. "TMSFCU,Time stamp fine or coarse update" "0,1"
|
|
bitfld.long 0x0 0. "TMSEN,Time stamp enable" "0,1"
|
|
line.long 0x4 "PTP_SSINC,Ethernet PTP subsecond increment register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "STMSSI,System time subsecond increment"
|
|
rgroup.long 0x8++0x7
|
|
line.long 0x0 "PTP_TSH,Ethernet PTP time stamp high register"
|
|
hexmask.long 0x0 0.--31. 1. "STMS,System time second"
|
|
line.long 0x4 "PTP_TSL,Ethernet PTP time stamp low register (PTP_TSL)"
|
|
bitfld.long 0x4 31. "STS,System time sign" "0,1"
|
|
hexmask.long 0x4 0.--30. 1. "STMSS,System time subseconds"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "PTP_TSUH,Ethernet PTP time stamp high update register"
|
|
hexmask.long 0x0 0.--31. 1. "TMSUS,Time stamp update second"
|
|
line.long 0x4 "PTP_TSUL,Ethernet PTP time stamp low update register (PTP_TSUL)"
|
|
bitfld.long 0x4 31. "TMSUPNS,Time stamp update positive or negative sign" "0,1"
|
|
hexmask.long 0x4 0.--30. 1. "TMSUSS,Time stamp update subseconds"
|
|
line.long 0x8 "PTP_TSADDEND,Ethernet PTP time stamp addend register"
|
|
hexmask.long 0x8 0.--31. 1. "TMSA,Time stamp addend"
|
|
line.long 0xC "PTP_ETH,Ethernet PTP expected time high register"
|
|
hexmask.long 0xC 0.--31. 1. "ETSH,Expected time stamp high"
|
|
line.long 0x10 "PTP_ETL,Ethernet PTP expected time low register"
|
|
hexmask.long 0x10 0.--31. 1. "ETSL,Expected time stamp low"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "PTP_TSF,Ethernet PTP time stamp flag register"
|
|
bitfld.long 0x0 1. "TTM,Target time match" "0,1"
|
|
bitfld.long 0x0 0. "TSSCO,Timestamp second counter overflow" "0,1"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "PTP_PPSCTL,Ethernet PTP PPS control register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PPSOFC,PPS output frequency configure"
|
|
tree.end
|
|
tree.end
|
|
tree "ENET1"
|
|
tree "ENET1_DMA (DMA Controller Operation)"
|
|
base ad:0x4002B000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "DMA_BCTL,Ethernet DMA bus control register"
|
|
bitfld.long 0x0 26. "MB,Mixed burst" "0,1"
|
|
bitfld.long 0x0 25. "AA,Address-aligned" "0,1"
|
|
bitfld.long 0x0 24. "FPBL,Four times PGBL mode" "0,1"
|
|
bitfld.long 0x0 23. "UIP,Use independent PGBL" "0,1"
|
|
hexmask.long.byte 0x0 17.--22. 1. "RXDP,Rx DMA PGBL"
|
|
bitfld.long 0x0 16. "FB,Fixed burst" "0,1"
|
|
bitfld.long 0x0 14.--15. "RTPR,RxDMA and TxDMA transfer priority ratio" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--13. 1. "PGBL,Programmable burst length"
|
|
bitfld.long 0x0 7. "DFM,Descriptor format mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 2.--6. 1. "DPSL,Descriptor skip length"
|
|
bitfld.long 0x0 1. "DAB,DMA Arbitration" "0,1"
|
|
bitfld.long 0x0 0. "SWR,Software reset" "0,1"
|
|
line.long 0x4 "DMA_TPEN,Ethernet DMA transmit poll enable register"
|
|
hexmask.long 0x4 0.--31. 1. "TPE,Transmit poll enable"
|
|
line.long 0x8 "DMA_RPEN,Ethernet DMA receive poll enable register"
|
|
hexmask.long 0x8 0.--31. 1. "RPE,Receive poll enable"
|
|
line.long 0xC "DMA_RDTADDR,Ethernet DMA receive descriptor table address register"
|
|
hexmask.long 0xC 0.--31. 1. "SRT,Start address of receive table"
|
|
line.long 0x10 "DMA_TDTADDR,Ethernet DMA transmit descriptor table address register"
|
|
hexmask.long 0x10 0.--31. 1. "STT,Start address of transmit table"
|
|
line.long 0x14 "DMA_STAT,Ethernet DMA status register"
|
|
rbitfld.long 0x14 29. "TST,Time stamp trigger status" "0,1"
|
|
rbitfld.long 0x14 28. "WUM,WUM status" "0,1"
|
|
rbitfld.long 0x14 27. "MSC,MSC status" "0,1"
|
|
rbitfld.long 0x14 23.--25. "EB,Error bits status" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x14 20.--22. "TP,Transmit process state" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x14 17.--19. "RP,Receive process state" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 16. "NI,Normal interrupt summary" "0,1"
|
|
bitfld.long 0x14 15. "AI,Abnormal interrupt summary" "0,1"
|
|
bitfld.long 0x14 14. "ER,Early receive status" "0,1"
|
|
newline
|
|
bitfld.long 0x14 13. "FBE,Fatal bus error status" "0,1"
|
|
bitfld.long 0x14 10. "ET,Early transmit status" "0,1"
|
|
bitfld.long 0x14 9. "RWT,Receive watchdog timeout status" "0,1"
|
|
bitfld.long 0x14 8. "RPS,Receive process stopped status" "0,1"
|
|
bitfld.long 0x14 7. "RBU,Receive buffer unavailable status" "0,1"
|
|
bitfld.long 0x14 6. "RS,Receive status" "0,1"
|
|
bitfld.long 0x14 5. "TU,Transmit underflow status" "0,1"
|
|
bitfld.long 0x14 4. "RO,Receive overflow status" "0,1"
|
|
bitfld.long 0x14 3. "TJT,Transmit jabber timeout status" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "TBU,Transmit buffer unavailable status" "0,1"
|
|
bitfld.long 0x14 1. "TPS,Transmit process stopped status" "0,1"
|
|
bitfld.long 0x14 0. "TS,Transmit status" "0,1"
|
|
line.long 0x18 "DMA_CTL,Ethernet DMA control register"
|
|
bitfld.long 0x18 26. "DTCERFD,Dropping of TCP/IP checksum error frames disable" "0,1"
|
|
bitfld.long 0x18 25. "RSFD,Receive Store-and-Forward" "0,1"
|
|
bitfld.long 0x18 24. "DAFRF,Disable flushing of received frames" "0,1"
|
|
bitfld.long 0x18 21. "TSFD,Transmit Store-and-Forward" "0,1"
|
|
bitfld.long 0x18 20. "FTF,Flush transmit FIFO" "0,1"
|
|
bitfld.long 0x18 14.--16. "TTHC,Transmit threshold control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 13. "STE,Start/stop transmission enable" "0,1"
|
|
bitfld.long 0x18 7. "FERF,Forward error frames" "0,1"
|
|
bitfld.long 0x18 6. "FUF,Forward undersized good frames" "0,1"
|
|
newline
|
|
bitfld.long 0x18 3.--4. "RTHC,Receive threshold control" "0,1,2,3"
|
|
bitfld.long 0x18 2. "OSF,Operate on second frame" "0,1"
|
|
bitfld.long 0x18 1. "SRE,Start/stop receive enable" "0,1"
|
|
line.long 0x1C "DMA_INTEN,Ethernet DMA interrupt enable register"
|
|
bitfld.long 0x1C 16. "NIE,Normal interrupt summary enable" "0,1"
|
|
bitfld.long 0x1C 15. "AIE,Abnormal interrupt summary enable" "0,1"
|
|
bitfld.long 0x1C 14. "ERIE,Early receive interrupt enable" "0,1"
|
|
bitfld.long 0x1C 13. "FBEIE,Fatal bus error interrupt enable" "0,1"
|
|
bitfld.long 0x1C 10. "ETIE,Early transmit interrupt enable" "0,1"
|
|
bitfld.long 0x1C 9. "RWTIE,receive watchdog timeout interrupt enable" "0,1"
|
|
bitfld.long 0x1C 8. "RPSIE,Receive process stopped interrupt enable" "0,1"
|
|
bitfld.long 0x1C 7. "RBUIE,Receive buffer unavailable interrupt enable" "0,1"
|
|
bitfld.long 0x1C 6. "RIE,Receive interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 5. "TUIE,Transmit underflow interrupt enable" "0,1"
|
|
bitfld.long 0x1C 4. "ROIE,Receive overflow interrupt enable" "0,1"
|
|
bitfld.long 0x1C 3. "TJTIE,Transmit jabber timeout interrupt enable" "0,1"
|
|
bitfld.long 0x1C 2. "TBUIE,Transmit buffer unavailable interrupt enable" "0,1"
|
|
bitfld.long 0x1C 1. "TPSIE,Transmit process stopped interrupt enable" "0,1"
|
|
bitfld.long 0x1C 0. "TIE,Transmit interrupt enable" "0,1"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "DMA_MFBOCNT,Ethernet DMA missed frame and buffer overflow counter register"
|
|
hexmask.long.word 0x0 17.--27. 1. "MSFA,Missed frames by the application"
|
|
hexmask.long.word 0x0 0.--15. 1. "MSFC,Missed frames by the controller"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "DMA_RSWDC,Ethernet DMA receive state watchdog counter register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WDCFRS,Watchdog counter for receive status (RS)"
|
|
rgroup.long 0x48++0xF
|
|
line.long 0x0 "DMA_CTDADDR,DMA current transmit descriptor address register"
|
|
hexmask.long 0x0 0.--31. 1. "TDAP,transmit descriptor address pointer"
|
|
line.long 0x4 "DMA_CRDADDR,Ethernet DMA current receive descriptor address register"
|
|
hexmask.long 0x4 0.--31. 1. "RDAP,Receive descriptor address pointer"
|
|
line.long 0x8 "DMA_CTBADDR,Ethernet DMA current transmit buffer address register"
|
|
hexmask.long 0x8 0.--31. 1. "TBAP,Transmit buffer address pointer"
|
|
line.long 0xC "DMA_CRBADDR,Ethernet DMA current receive buffer address register"
|
|
hexmask.long 0xC 0.--31. 1. "RBAP,receive buffer address pointer"
|
|
tree.end
|
|
tree "ENET1_MAC (Media Access Control)"
|
|
base ad:0x4002A000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "MAC_CFG,Ethernet MAC configuration register (MAC_CFG)"
|
|
bitfld.long 0x0 25. "TFCD,Type Frame CRC Dropping" "0,1"
|
|
bitfld.long 0x0 23. "WDD,Watchdog disable" "0,1"
|
|
bitfld.long 0x0 22. "JBD,Jabber disable" "0,1"
|
|
bitfld.long 0x0 17.--19. "IGBS,Inter frame gap bit selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16. "CSD,Carrier sense disable" "0,1"
|
|
bitfld.long 0x0 14. "SPD,Fast Ethernet speed" "0,1"
|
|
bitfld.long 0x0 13. "ROD,Receive own disable" "0,1"
|
|
bitfld.long 0x0 12. "LBM,Loopback mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DPM,Duplex mode" "0,1"
|
|
bitfld.long 0x0 10. "IPFCO,IP frame checksum offload" "0,1"
|
|
bitfld.long 0x0 9. "RTD,Retry disable" "0,1"
|
|
bitfld.long 0x0 7. "APCD,Automatic pad/CRC drop" "0,1"
|
|
bitfld.long 0x0 5.--6. "BOL,Back-off limit" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DFC,Deferral check" "0,1"
|
|
bitfld.long 0x0 3. "TEN,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "REN,Receiver enable" "0,1"
|
|
line.long 0x4 "MAC_FRMF,Ethernet MAC frame filter register (MAC_FRMF)"
|
|
bitfld.long 0x4 31. "FAR,Frames all receive" "0,1"
|
|
bitfld.long 0x4 10. "HPFLT,Hash or perfect filter" "0,1"
|
|
bitfld.long 0x4 9. "SAFLT,Source address filter" "0,1"
|
|
bitfld.long 0x4 8. "SAIFLT,Source address inverse filtering" "0,1"
|
|
bitfld.long 0x4 6.--7. "PCFRM,Pass control frames" "0,1,2,3"
|
|
bitfld.long 0x4 5. "BFRMD,Broadcast frames disable" "0,1"
|
|
bitfld.long 0x4 4. "MFD,multicast filter disable" "0,1"
|
|
bitfld.long 0x4 3. "DAIFLT,Destination address inverse filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "HMF,Hash multicast filter" "0,1"
|
|
bitfld.long 0x4 1. "HUF,Hash unicast filter" "0,1"
|
|
bitfld.long 0x4 0. "PM,Promiscuous mode" "0,1"
|
|
line.long 0x8 "MAC_HLH,Ethernet MAC hash list high register"
|
|
hexmask.long 0x8 0.--31. 1. "HLH,Hash list high"
|
|
line.long 0xC "MAC_HLL,Ethernet MAC hash list low register"
|
|
hexmask.long 0xC 0.--31. 1. "HLL,Hash list low"
|
|
line.long 0x10 "MAC_PHY_CTL,Ethernet MAC PHY control register (MAC_PHY_CTL)"
|
|
hexmask.long.byte 0x10 11.--15. 1. "PA,PHY address"
|
|
hexmask.long.byte 0x10 6.--10. 1. "PR,PHY register"
|
|
bitfld.long 0x10 2.--4. "CLR,Clock range" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "PW,PHY write" "0,1"
|
|
bitfld.long 0x10 0. "PB,PHY busy" "0,1"
|
|
line.long 0x14 "MAC_PHY_DATA,Ethernet MAC MII data register (MAC_PHY_DATA)"
|
|
hexmask.long.word 0x14 0.--15. 1. "PD,PHY data"
|
|
line.long 0x18 "MAC_FCTL,Ethernet MAC flow control register (MAC_FCTL)"
|
|
hexmask.long.word 0x18 16.--31. 1. "PTM,Pause time"
|
|
bitfld.long 0x18 7. "DZQP,Disable Zero-quanta pause" "0,1"
|
|
bitfld.long 0x18 4.--5. "PLTS,Pause low threshold" "0,1,2,3"
|
|
bitfld.long 0x18 3. "UPFDT,Unicast pause frame detect" "0,1"
|
|
bitfld.long 0x18 2. "RFCEN,Receive flow control enable" "0,1"
|
|
bitfld.long 0x18 1. "TFCEN,Transmit flow control enable" "0,1"
|
|
bitfld.long 0x18 0. "FLCB_BKPA,Flow control busy/back pressure activate" "0,1"
|
|
line.long 0x1C "MAC_VLT,Ethernet MAC VLAN tag register (MAC_VLT)"
|
|
bitfld.long 0x1C 16. "VLTC,12-bit VLAN tag comparison" "0,1"
|
|
hexmask.long.word 0x1C 0.--15. 1. "VLTI,VLAN tag identifier (for receive frames)"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "MAC_RWFF,Ethernet MAC remote wakeup frame filter register (MAC_RWFF)"
|
|
line.long 0x4 "MAC_WUM,Ethernet MAC wakeup management register (MAC_WUM)"
|
|
bitfld.long 0x4 31. "WUFFRPR,Wakeup frame filter register pointer reset" "0,1"
|
|
bitfld.long 0x4 9. "GU,Global unicast" "0,1"
|
|
bitfld.long 0x4 6. "WUFR,Wakeup frame received" "0,1"
|
|
bitfld.long 0x4 5. "MPKR,Magic packet received" "0,1"
|
|
bitfld.long 0x4 2. "WFEN,Wakeup frame enable" "0,1"
|
|
bitfld.long 0x4 1. "MPEN,Magic Packet enable" "0,1"
|
|
bitfld.long 0x4 0. "PWD,Power down" "0,1"
|
|
rgroup.long 0x34++0x7
|
|
line.long 0x0 "MAC_DBG,Ethernet MAC debug register (MAC_DBG)"
|
|
bitfld.long 0x0 25. "TXFF,TxFIFO Full flag" "0,1"
|
|
bitfld.long 0x0 24. "TXFNE,TxFIFO not empty flag" "0,1"
|
|
bitfld.long 0x0 22. "TXFW,TxFIFO is writing" "0,1"
|
|
bitfld.long 0x0 20.--21. "TXFRS,TxFIFO read operation status" "0,1,2,3"
|
|
bitfld.long 0x0 19. "PCS,Pause condition status" "0,1"
|
|
bitfld.long 0x0 17.--18. "SOMT,Status of MAC transmitter" "0,1,2,3"
|
|
bitfld.long 0x0 16. "MTNI,MAC transmit state not idle" "0,1"
|
|
bitfld.long 0x0 8.--9. "RXFS,RxFIFO state" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 5.--6. "RXFRS,RxFIFO read operation status" "0,1,2,3"
|
|
bitfld.long 0x0 4. "RXFW,RxFIFO is writing" "0,1"
|
|
bitfld.long 0x0 1.--2. "RXAFS,Rx asynchronous FIFO status" "0,1,2,3"
|
|
bitfld.long 0x0 0. "MRNI,MAC receive state not idle" "0,1"
|
|
line.long 0x4 "MAC_INTF,Ethernet MAC interrupt flag register (MAC_INTF)"
|
|
bitfld.long 0x4 9. "TMST,Time stamp trigger status" "0,1"
|
|
bitfld.long 0x4 6. "MSCT,MSC transmit status" "0,1"
|
|
bitfld.long 0x4 5. "MSCR,MSC receive status" "0,1"
|
|
bitfld.long 0x4 4. "MSC,MSC status" "0,1"
|
|
bitfld.long 0x4 3. "WUM,WUM status" "0,1"
|
|
group.long 0x3C++0x23
|
|
line.long 0x0 "MAC_INTMSK,Ethernet MAC interrupt mask register (MAC_INTMSK)"
|
|
bitfld.long 0x0 9. "TMSTIM,Time stamp trigger interrupt mask" "0,1"
|
|
bitfld.long 0x0 3. "WUMIM,WUM interrupt mask" "0,1"
|
|
line.long 0x4 "MAC_ADDR0H,Ethernet MAC address 0 high register (MAC_ADDR0H)"
|
|
bitfld.long 0x4 31. "MO,Always 1" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADDR0H,MAC address0 high"
|
|
line.long 0x8 "MAC_ADDR0L,Ethernet MAC address 0 low register"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR0L,MAC address0 low"
|
|
line.long 0xC "MAC_ADDR1H,Ethernet MAC address 1 high register (MAC_ADDR1H)"
|
|
bitfld.long 0xC 31. "AFE,Address filter enable" "0,1"
|
|
bitfld.long 0xC 30. "SAF,Source address filter" "0,1"
|
|
hexmask.long.byte 0xC 24.--29. 1. "MB,Mask byte"
|
|
hexmask.long.word 0xC 0.--15. 1. "ADDR1H,MAC address1 high"
|
|
line.long 0x10 "MAC_ADDR1L,Ethernet MAC address1 low register"
|
|
hexmask.long 0x10 0.--31. 1. "ADDR1L,MAC address1 low"
|
|
line.long 0x14 "MAC_ADDR2H,Ethernet MAC address 2 high register (MAC_ADDR2H)"
|
|
bitfld.long 0x14 31. "AFE,Address filter enable" "0,1"
|
|
bitfld.long 0x14 30. "SAF,Source address filter" "0,1"
|
|
hexmask.long.byte 0x14 24.--29. 1. "MB,Mask byte"
|
|
hexmask.long.word 0x14 0.--15. 1. "ADDR2H,Ethernet MAC address 2 high register"
|
|
line.long 0x18 "MAC_ADDR2L,Ethernet MAC address 2 low register"
|
|
hexmask.long 0x18 0.--31. 1. "ADDR2L,MAC address2 low"
|
|
line.long 0x1C "MAC_ADDR3H,Ethernet MAC address 3 high register (MAC_ADDR3H)"
|
|
bitfld.long 0x1C 31. "AFE,Address filter enable" "0,1"
|
|
bitfld.long 0x1C 30. "SAF,Source address filter" "0,1"
|
|
hexmask.long.byte 0x1C 24.--29. 1. "MB,Mask byte"
|
|
hexmask.long.word 0x1C 0.--15. 1. "ADDR3H,MAC address3 high"
|
|
line.long 0x20 "MAC_ADDR3L,Ethernet MAC address 3 low register"
|
|
hexmask.long 0x20 0.--31. 1. "ADDR3L,MAC address3 low"
|
|
tree.end
|
|
tree "ENET1_MAC_FCTH (MAC flow control threshold register)"
|
|
base ad:0x4002B080
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MAC_FCTH,Ethernet MAC flow control threshold register"
|
|
bitfld.long 0x0 4.--6. "RFD,Threshold of deactive flow control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "RFA,Threshold of active flow control" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "ENET1_MSC (MAC Statistics Counters)"
|
|
base ad:0x4002A100
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MSC_CTL,Ethernet MSC control register (MSC_CTL)"
|
|
bitfld.long 0x0 5. "AFHPM,Almost full or half preset mode" "0,1"
|
|
bitfld.long 0x0 4. "PMC,Preset MSC counter" "0,1"
|
|
bitfld.long 0x0 3. "MCFZ,MSC counter freeze" "0,1"
|
|
bitfld.long 0x0 2. "RTOR,Reset on read" "0,1"
|
|
bitfld.long 0x0 1. "CTSR,Counter stop rollover" "0,1"
|
|
bitfld.long 0x0 0. "CTR,Counter reset" "0,1"
|
|
rgroup.long 0x4++0x7
|
|
line.long 0x0 "MSC_RINTF,Ethernet MSC receive interrupt flag register (MSC_RINTF)"
|
|
bitfld.long 0x0 17. "RGUF,Received Good Unicast Frames" "0,1"
|
|
bitfld.long 0x0 6. "RFAE,Received frames alignment error" "0,1"
|
|
bitfld.long 0x0 5. "RFCE,Received frames CRC error" "0,1"
|
|
line.long 0x4 "MSC_TINTF,Ethernet MSC transmit interrupt flag register (MSC_TINTF)"
|
|
bitfld.long 0x4 21. "TGF,Transmitted good frames" "0,1"
|
|
bitfld.long 0x4 15. "TGFMSC,Transmitted good frames more single collision" "0,1"
|
|
bitfld.long 0x4 14. "TGFSC,Transmitted good frames single collision" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "MSC_RINTMSK,Ethernet MSC receive interrupt mask register (MSC_RINTMSK)"
|
|
bitfld.long 0x0 17. "RGUFIM,Received good unicast frames interrupt mask" "0,1"
|
|
bitfld.long 0x0 6. "RFAEIM,Received frames alignment error interrupt mask" "0,1"
|
|
bitfld.long 0x0 5. "RFCEIM,Received frame CRC error interrupt mask" "0,1"
|
|
line.long 0x4 "MSC_TINTMSK,Ethernet MSC transmit interrupt mask register (MSC_TINTMSK)"
|
|
bitfld.long 0x4 21. "TGFIM,Transmitted good frames interrupt mask" "0,1"
|
|
bitfld.long 0x4 15. "TGFMSCIM,Transmitted good frames more single interrupt collision mask" "0,1"
|
|
bitfld.long 0x4 14. "TGFSCIM,Transmitted good frames single collision interrupt mask" "0,1"
|
|
rgroup.long 0x4C++0x7
|
|
line.long 0x0 "MSC_SCCNT,Ethernet MSC transmitted good frames after a single collision counter"
|
|
hexmask.long 0x0 0.--31. 1. "SCC,Transmitted good frames after a single collision counter"
|
|
line.long 0x4 "MSC_MSCCNT,Ethernet MSC transmitted good frames after more than a single collision"
|
|
hexmask.long 0x4 0.--31. 1. "MSCC,Transmitted good frames after more than a single collision counter"
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x0 "MSC_TGFCNT,Ethernet MSC transmitted good frames counter register"
|
|
hexmask.long 0x0 0.--31. 1. "TGF,Transmitted good frames counter"
|
|
rgroup.long 0x94++0x7
|
|
line.long 0x0 "MSC_RFCECNT,Ethernet MSC received frames with CRC error counter register"
|
|
hexmask.long 0x0 0.--31. 1. "RFCER,Received frames with CRC error counter"
|
|
line.long 0x4 "MSC_RFAECNT,Ethernet MSC received frames with alignment error counter register"
|
|
hexmask.long 0x4 0.--31. 1. "RFAER,Received frames with alignment error counter"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "MSC_RGUFCNT,MSC received good unicast frames counter register"
|
|
hexmask.long 0x0 0.--31. 1. "RGUF,Received good unicast frames counter"
|
|
tree.end
|
|
tree "ENET1_PTP (Precision Time Protocol)"
|
|
base ad:0x4002A700
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "PTP_TSCTL,Ethernet PTP time stamp control register (PTP_TSCTL)"
|
|
bitfld.long 0x0 18. "MAFEN,MAC address filter enable for PTP frame" "0,1"
|
|
bitfld.long 0x0 16.--17. "CKNT,Clock node type for time stamp" "0,1,2,3"
|
|
bitfld.long 0x0 15. "MNMSEN,Received master node message snapshot enable" "0,1"
|
|
bitfld.long 0x0 14. "ETMSEN,Received event type message snapshot enable" "0,1"
|
|
bitfld.long 0x0 13. "IP4SEN,Received IPv4 snapshot enable" "0,1"
|
|
bitfld.long 0x0 12. "IP6SEN,Received IPv6 snapshot enable" "0,1"
|
|
bitfld.long 0x0 11. "ESEN,Received Ethernet snapshot enable" "0,1"
|
|
bitfld.long 0x0 10. "PFSV,PTP frame snooping version" "0,1"
|
|
bitfld.long 0x0 9. "SCROM,Subsecond counter rollover mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ARFSEN,All received frames snapshot enable" "0,1"
|
|
bitfld.long 0x0 5. "TMSARU,Time stamp addend register update" "0,1"
|
|
bitfld.long 0x0 4. "TMSITEN,Time stamp interrupt trigger enable" "0,1"
|
|
bitfld.long 0x0 3. "TMSSTU,Time stamp system time update" "0,1"
|
|
bitfld.long 0x0 2. "TMSSTI,Time stamp system time initialize" "0,1"
|
|
bitfld.long 0x0 1. "TMSFCU,Time stamp fine or coarse update" "0,1"
|
|
bitfld.long 0x0 0. "TMSEN,Time stamp enable" "0,1"
|
|
line.long 0x4 "PTP_SSINC,Ethernet PTP subsecond increment register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "STMSSI,System time subsecond increment"
|
|
rgroup.long 0x8++0x7
|
|
line.long 0x0 "PTP_TSH,Ethernet PTP time stamp high register"
|
|
hexmask.long 0x0 0.--31. 1. "STMS,System time second"
|
|
line.long 0x4 "PTP_TSL,Ethernet PTP time stamp low register (PTP_TSL)"
|
|
bitfld.long 0x4 31. "STS,System time sign" "0,1"
|
|
hexmask.long 0x4 0.--30. 1. "STMSS,System time subseconds"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "PTP_TSUH,Ethernet PTP time stamp high update register"
|
|
hexmask.long 0x0 0.--31. 1. "TMSUS,Time stamp update second"
|
|
line.long 0x4 "PTP_TSUL,Ethernet PTP time stamp low update register (PTP_TSUL)"
|
|
bitfld.long 0x4 31. "TMSUPNS,Time stamp update positive or negative sign" "0,1"
|
|
hexmask.long 0x4 0.--30. 1. "TMSUSS,Time stamp update subseconds"
|
|
line.long 0x8 "PTP_TSADDEND,Ethernet PTP time stamp addend register"
|
|
hexmask.long 0x8 0.--31. 1. "TMSA,Time stamp addend"
|
|
line.long 0xC "PTP_ETH,Ethernet PTP expected time high register"
|
|
hexmask.long 0xC 0.--31. 1. "ETSH,Expected time stamp high"
|
|
line.long 0x10 "PTP_ETL,Ethernet PTP expected time low register"
|
|
hexmask.long 0x10 0.--31. 1. "ETSL,Expected time stamp low"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "PTP_TSF,Ethernet PTP time stamp flag register"
|
|
bitfld.long 0x0 1. "TTM,Target time match" "0,1"
|
|
bitfld.long 0x0 0. "TSSCO,Timestamp second counter overflow" "0,1"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "PTP_PPSCTL,Ethernet PTP PPS control register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PPSOFC,PPS output frequency configure"
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "EXMC (External Memory Controller)"
|
|
base ad:0x52004000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SNCTL0,SRAM/NOR flash control registe 0"
|
|
bitfld.long 0x0 24.--25. "BKREMAP,Bank remap" "0,1,2,3"
|
|
bitfld.long 0x0 20. "CCK,Consecutive Clock" "0,1"
|
|
bitfld.long 0x0 19. "SYNCWR,Synchronous write" "0,1"
|
|
bitfld.long 0x0 16.--18. "CPS,CRAM page size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15. "ASYNCWTEN,Asynchronous wait enable" "0,1"
|
|
bitfld.long 0x0 14. "EXMODEN,Extended mode enable" "0,1"
|
|
bitfld.long 0x0 13. "NRWTEN,NWAIT signal enable" "0,1"
|
|
bitfld.long 0x0 12. "WREN,Write enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "NRWTCFG,NWAIT signal configuration only work in synchronous mode" "0,1"
|
|
bitfld.long 0x0 9. "NRWTPOL,NWAIT signal polarity" "0,1"
|
|
bitfld.long 0x0 8. "SBRSTEN,Synchronous burst enable" "0,1"
|
|
bitfld.long 0x0 6. "NREN,NOR Flash access enable" "0,1"
|
|
bitfld.long 0x0 4.--5. "NRW,NOR region memory data bus width" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "NRTP,NOR region memory type" "0,1,2,3"
|
|
bitfld.long 0x0 1. "NRMUX,NOR region memory address/data multiplexing" "0,1"
|
|
bitfld.long 0x0 0. "NRBKEN,NOR region enable" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "SNCTL1,SRAM/NOR flash control registe 1"
|
|
bitfld.long 0x0 24.--25. "BKREMAP,Bank remap" "0,1,2,3"
|
|
bitfld.long 0x0 20. "CCK,Consecutive Clock" "0,1"
|
|
bitfld.long 0x0 19. "SYNCWR,Synchronous write" "0,1"
|
|
bitfld.long 0x0 16.--18. "CPS,CRAM page size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15. "ASYNCWAIT,Asynchronous wait" "0,1"
|
|
bitfld.long 0x0 14. "EXMODEN,Extended mode enable" "0,1"
|
|
bitfld.long 0x0 13. "NRWTEN,NWAIT signal enable" "0,1"
|
|
bitfld.long 0x0 12. "WREN,Write enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "NRWTCFG,NWAIT signal configuration only work in synchronous mode" "0,1"
|
|
bitfld.long 0x0 9. "NRWTPOL,NWAIT signal polarity" "0,1"
|
|
bitfld.long 0x0 8. "SBRSTEN,Synchronous burst enable" "0,1"
|
|
bitfld.long 0x0 6. "NREN,NOR Flash access enable" "0,1"
|
|
bitfld.long 0x0 4.--5. "NRW,NOR region memory data bus width" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "NRTP,NOR region memory type" "0,1,2,3"
|
|
bitfld.long 0x0 1. "NRMUX,NOR region memory address/data multiplexing" "0,1"
|
|
bitfld.long 0x0 0. "NRBKEN,NOR region enable" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "SNCTL2,SRAM/NOR flash control registe 2"
|
|
bitfld.long 0x0 24.--25. "BKREMAP,Bank remap" "0,1,2,3"
|
|
bitfld.long 0x0 20. "CCK,Consecutive Clock" "0,1"
|
|
bitfld.long 0x0 19. "SYNCWR,Synchronous write" "0,1"
|
|
bitfld.long 0x0 16.--18. "CPS,CRAM page size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15. "ASYNCWAIT,Asynchronous wait" "0,1"
|
|
bitfld.long 0x0 14. "EXMODEN,Extended mode enable" "0,1"
|
|
bitfld.long 0x0 13. "NRWTEN,NWAIT signal enable" "0,1"
|
|
bitfld.long 0x0 12. "WREN,Write enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "NRWTCFG,NWAIT signal configuration only work in synchronous mode" "0,1"
|
|
bitfld.long 0x0 9. "NRWTPOL,NWAIT signal polarity" "0,1"
|
|
bitfld.long 0x0 8. "SBRSTEN,Synchronous burst enable" "0,1"
|
|
bitfld.long 0x0 6. "NREN,NOR Flash access enable" "0,1"
|
|
bitfld.long 0x0 4.--5. "NRW,NOR region memory data bus width" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "NRTP,NOR region memory type" "0,1,2,3"
|
|
bitfld.long 0x0 1. "NRMUX,NOR region memory address/data multiplexing" "0,1"
|
|
bitfld.long 0x0 0. "NRBKEN,NOR region enable" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "SNCTL3,SRAM/NOR flash control registe 3"
|
|
bitfld.long 0x0 24.--25. "BKREMAP,Bank remap" "0,1,2,3"
|
|
bitfld.long 0x0 20. "CCK,Consecutive Clock" "0,1"
|
|
bitfld.long 0x0 19. "SYNCWR,Synchronous write" "0,1"
|
|
bitfld.long 0x0 16.--18. "CPS,CRAM page size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15. "ASYNCWAIT,Asynchronous wait" "0,1"
|
|
bitfld.long 0x0 14. "EXMODEN,Extended mode enable" "0,1"
|
|
bitfld.long 0x0 13. "NRWTEN,NWAIT signal enable" "0,1"
|
|
bitfld.long 0x0 12. "WREN,Write enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "NRWTCFG,NWAIT signal configuration only work in synchronous mode" "0,1"
|
|
bitfld.long 0x0 9. "NRWTPOL,NWAIT signal polarity" "0,1"
|
|
bitfld.long 0x0 8. "SBRSTEN,Synchronous burst enable" "0,1"
|
|
bitfld.long 0x0 6. "NREN,NOR Flash access enable" "0,1"
|
|
bitfld.long 0x0 4.--5. "NRW,NOR region memory data bus width" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "NRTP,NOR region memory type" "0,1,2,3"
|
|
bitfld.long 0x0 1. "NRMUX,NOR region memory address/data multiplexing" "0,1"
|
|
bitfld.long 0x0 0. "NRBKEN,NOR region enable" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "SNTCFG0,SRAM/NOR flash timing configuration registe 0"
|
|
bitfld.long 0x0 28.--29. "ASYNCMOD,Asynchronous access mode" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DLAT,Data latency for NOR Flash"
|
|
hexmask.long.byte 0x0 20.--23. 1. "CKDIV,Synchronous clock divide ratio"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BUSLAT,Bus latency"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DSET,Data setup time"
|
|
hexmask.long.byte 0x0 4.--7. 1. "AHLD,Address hold time"
|
|
hexmask.long.byte 0x0 0.--3. 1. "ASET,Address setup time"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "SNTCFG1,SRAM/NOR flash timing configuration registe 1"
|
|
bitfld.long 0x0 28.--29. "ASYNCMOD,Asynchronous access mode" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DLAT,Data latency for NOR Flash"
|
|
hexmask.long.byte 0x0 20.--23. 1. "CKDIV,Synchronous clock divide ratio"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BUSLAT,Bus latency"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DSET,Data setup time"
|
|
hexmask.long.byte 0x0 4.--7. 1. "AHLD,Address hold time"
|
|
hexmask.long.byte 0x0 0.--3. 1. "ASET,Address setup time"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "SNTCFG2,SRAM/NOR flash timing configuration registe 2"
|
|
bitfld.long 0x0 28.--29. "ASYNCMOD,Asynchronous access mode" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DLAT,Data latency for NOR Flash"
|
|
hexmask.long.byte 0x0 20.--23. 1. "CKDIV,Synchronous clock divide ratio"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BUSLAT,Bus latency"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DSET,Data setup time"
|
|
hexmask.long.byte 0x0 4.--7. 1. "AHLD,Address hold time"
|
|
hexmask.long.byte 0x0 0.--3. 1. "ASET,Address setup time"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "SNTCFG3,SRAM/NOR flash timing configuration registe 3"
|
|
bitfld.long 0x0 28.--29. "ASYNCMOD,Asynchronous access mode" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DLAT,Data latency for NOR Flash"
|
|
hexmask.long.byte 0x0 20.--23. 1. "CKDIV,Synchronous clock divide ratio"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BUSLAT,Bus latency"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DSET,Data setup time"
|
|
hexmask.long.byte 0x0 4.--7. 1. "AHLD,Address hold time"
|
|
hexmask.long.byte 0x0 0.--3. 1. "ASET,Address setup time"
|
|
group.long 0x104++0x3
|
|
line.long 0x0 "SNWTCFG0,SRAM/NOR flash write timing configuration registe 0"
|
|
bitfld.long 0x0 28.--29. "WASYNCMOD,Asynchronous access mode" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "WBUSLAT,Bus latency"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WDSET,Data setup time"
|
|
hexmask.long.byte 0x0 4.--7. 1. "WAHLD,Address hold time"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WASET,Address setup time"
|
|
group.long 0x10C++0x3
|
|
line.long 0x0 "SNWTCFG1,SRAM/NOR flash write timing configuration registe 1"
|
|
bitfld.long 0x0 28.--29. "WASYNCMOD,Asynchronous access mode" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "WBUSLAT,Bus latency"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WDSET,Data setup time"
|
|
hexmask.long.byte 0x0 4.--7. 1. "WAHLD,Address hold time"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WASET,Address setup time"
|
|
group.long 0x114++0x3
|
|
line.long 0x0 "SNWTCFG2,SRAM/NOR flash write timing configuration registe 2"
|
|
bitfld.long 0x0 28.--29. "WASYNCMOD,Asynchronous access mode" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "WBUSLAT,Bus latency"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WDSET,Data setup time"
|
|
hexmask.long.byte 0x0 4.--7. 1. "WAHLD,Address hold time"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WASET,Address setup time"
|
|
group.long 0x11C++0x3
|
|
line.long 0x0 "SNWTCFG3,SRAM/NOR flash write timing configuration registe 3"
|
|
bitfld.long 0x0 28.--29. "WASYNCMOD,Asynchronous access mode" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "WBUSLAT,Bus latency"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WDSET,Data setup time"
|
|
hexmask.long.byte 0x0 4.--7. 1. "WAHLD,Address hold time"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WASET,Address setup time"
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "NCTL,NAND flash control registers"
|
|
bitfld.long 0x0 17.--19. "ECCSZ,ECC size" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 13.--16. 1. "ATR,ALE to RE delay"
|
|
hexmask.long.byte 0x0 9.--12. 1. "CTR,CLE to RE delay"
|
|
bitfld.long 0x0 6. "ECCEN,ECC enable" "0,1"
|
|
bitfld.long 0x0 4.--5. "NDW,NAND bank memory data bus width" "0,1,2,3"
|
|
bitfld.long 0x0 3. "NDTP,NAND bank memory type" "0,1"
|
|
bitfld.long 0x0 2. "NDBKEN,NAND bank enable" "0,1"
|
|
bitfld.long 0x0 1. "NDWTEN,Wait function enable" "0,1"
|
|
line.long 0x4 "NINTEN,NAND flash interrupt enable registers"
|
|
bitfld.long 0x4 6. "FFEPT,FIFO empty flag" "0,1"
|
|
bitfld.long 0x4 5. "INTFEN,Interrupt falling edge detection enable" "0,1"
|
|
bitfld.long 0x4 4. "INTHEN,Interrupt high-level detection enable" "0,1"
|
|
bitfld.long 0x4 3. "INTREN,Interrupt rising edge detection enable bit" "0,1"
|
|
bitfld.long 0x4 2. "INTFS,Interrupt falling edge status" "0,1"
|
|
bitfld.long 0x4 1. "INTHS,Interrupt high-level status" "0,1"
|
|
bitfld.long 0x4 0. "INTRS,Interrupt rising edge status" "0,1"
|
|
line.long 0x8 "NCTCFG,NAND flash common space timing configuration registers"
|
|
hexmask.long.byte 0x8 24.--31. 1. "COMHIZ,Common memory data bus HiZ time"
|
|
hexmask.long.byte 0x8 16.--23. 1. "COMHLD,Common memory hold time"
|
|
hexmask.long.byte 0x8 8.--15. 1. "COMWAIT,Common memory wait time"
|
|
hexmask.long.byte 0x8 0.--7. 1. "COMSET,Common memory setup time"
|
|
line.long 0xC "NATCFG,NAND flash attribute space timing configuration registers"
|
|
hexmask.long.byte 0xC 24.--31. 1. "ATTHIZ,Attribute memory data bus HiZ time"
|
|
hexmask.long.byte 0xC 16.--23. 1. "ATTHLD,Attribute memory hold time"
|
|
hexmask.long.byte 0xC 8.--15. 1. "ATTWAIT,Attribute memory wait time"
|
|
hexmask.long.byte 0xC 0.--7. 1. "ATTSET,Attribute memory setup time"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "NECC,NAND flash ECC registers"
|
|
hexmask.long 0x0 0.--31. 1. "ECC,ECC result"
|
|
group.long 0x140++0x17
|
|
line.long 0x0 "SDCTL0,SDRAM control registe 0"
|
|
bitfld.long 0x0 13.--14. "PIPED,Pipeline delay" "0,1,2,3"
|
|
bitfld.long 0x0 12. "BRSTRD,Burst read" "0,1"
|
|
bitfld.long 0x0 10.--11. "SDCLK,SDRAM clock configuration" "0,1,2,3"
|
|
bitfld.long 0x0 9. "WPEN,Write protection enable" "0,1"
|
|
bitfld.long 0x0 7.--8. "CL,CAS Latency" "0,1,2,3"
|
|
bitfld.long 0x0 6. "NBK,Number of banks" "0,1"
|
|
bitfld.long 0x0 4.--5. "SDW,SDRAM data bus width" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "RAW,Row address bit width" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CAW,Column address bit width" "0,1,2,3"
|
|
line.long 0x4 "SDCTL1,SDRAM control registe 1"
|
|
bitfld.long 0x4 13.--14. "PIPED,Pipeline delay" "0,1,2,3"
|
|
bitfld.long 0x4 12. "BRSTRD,Burst read" "0,1"
|
|
bitfld.long 0x4 10.--11. "SDCLK,SDRAM clock configuration" "0,1,2,3"
|
|
bitfld.long 0x4 9. "WPEN,Write protection enable" "0,1"
|
|
bitfld.long 0x4 7.--8. "CL,CAS Latency" "0,1,2,3"
|
|
bitfld.long 0x4 6. "NBK,Number of banks" "0,1"
|
|
bitfld.long 0x4 4.--5. "SDW,SDRAM data bus width" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "RAW,Row address bit width" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "CAW,Column address bit width" "0,1,2,3"
|
|
line.long 0x8 "SDTCFG0,SDRAM timing configuration registe 0"
|
|
hexmask.long.byte 0x8 24.--27. 1. "RCD,Row to column delay"
|
|
hexmask.long.byte 0x8 20.--23. 1. "RPD,Row precharge delay"
|
|
hexmask.long.byte 0x8 16.--19. 1. "WRD,Write recovery delay"
|
|
hexmask.long.byte 0x8 12.--15. 1. "ARFD,Auto refresh delay"
|
|
hexmask.long.byte 0x8 8.--11. 1. "RASD,Row address select delay"
|
|
hexmask.long.byte 0x8 4.--7. 1. "XSRD,Exit Self-refresh delay"
|
|
hexmask.long.byte 0x8 0.--3. 1. "LMRD,Load Mode Register Delay"
|
|
line.long 0xC "SDTCFG1,SDRAM timing configuration registe 1"
|
|
hexmask.long.byte 0xC 24.--27. 1. "RCD,Row to column delay"
|
|
hexmask.long.byte 0xC 20.--23. 1. "RPD,Row precharge delay"
|
|
hexmask.long.byte 0xC 16.--19. 1. "WRD,Write recovery delay"
|
|
hexmask.long.byte 0xC 12.--15. 1. "ARFD,Auto refresh delay"
|
|
hexmask.long.byte 0xC 8.--11. 1. "RASD,Row address select delay"
|
|
hexmask.long.byte 0xC 4.--7. 1. "XSRD,Exit Self-refresh delay"
|
|
hexmask.long.byte 0xC 0.--3. 1. "LMRD,Load Mode Register Delay"
|
|
line.long 0x10 "SDCMD,SDRAM command register"
|
|
hexmask.long.word 0x10 9.--21. 1. "MRC,Mode register content"
|
|
hexmask.long.byte 0x10 5.--8. 1. "NARF,Number of successive Auto-refresh"
|
|
bitfld.long 0x10 4. "DS0,Device select 0" "0,1"
|
|
bitfld.long 0x10 3. "DS1,Device select 1" "0,1"
|
|
bitfld.long 0x10 0.--2. "CMD,Command" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "SDARI,SDRAM auto-refresh interval register"
|
|
bitfld.long 0x14 14. "REIE,Refresh error interrupt Enable" "0,1"
|
|
hexmask.long.word 0x14 1.--13. 1. "ARINTV,Auto-Refresh Interval"
|
|
bitfld.long 0x14 0. "REC,Refresh error flag clear" "0,1"
|
|
rgroup.long 0x158++0x3
|
|
line.long 0x0 "SDSTAT,SDRAM status register"
|
|
bitfld.long 0x0 5. "NRDY,Not Ready status" "0,1"
|
|
bitfld.long 0x0 3.--4. "STA1,Device1 status" "0,1,2,3"
|
|
bitfld.long 0x0 1.--2. "STA0,Device 0 status" "0,1,2,3"
|
|
bitfld.long 0x0 0. "REIF,Refresh error interrupt flag" "0,1"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "SDRSCTL,SDRAM read sample control register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "SDSC,Select the delayed sample clock of read data"
|
|
bitfld.long 0x0 1. "SSCR,Select sample cycle of read data" "0,1"
|
|
bitfld.long 0x0 0. "RSEN,Read sample enable" "0,1"
|
|
tree.end
|
|
tree "EXTI (External Interrupt/Event Controller)"
|
|
base ad:0x58000000
|
|
group.long 0x0++0x2F
|
|
line.long 0x0 "INTEN0,Interrupt enable register 0(EXTI_INTEN0)"
|
|
bitfld.long 0x0 31. "INTEN31,Enable Interrupt on line 31" "0,1"
|
|
bitfld.long 0x0 30. "INTEN30,Enable Interrupt on line 30" "0,1"
|
|
bitfld.long 0x0 29. "INTEN29,Enable Interrupt on line 29" "0,1"
|
|
bitfld.long 0x0 28. "INTEN28,Enable Interrupt on line 28" "0,1"
|
|
bitfld.long 0x0 27. "INTEN27,Enable Interrupt on line 27" "0,1"
|
|
bitfld.long 0x0 26. "INTEN26,Enable Interrupt on line 26" "0,1"
|
|
bitfld.long 0x0 25. "INTEN25,Enable Interrupt on line 25" "0,1"
|
|
bitfld.long 0x0 24. "INTEN24,Enable Interrupt on line 24" "0,1"
|
|
bitfld.long 0x0 23. "INTEN23,Enable Interrupt on line 23" "0,1"
|
|
bitfld.long 0x0 22. "INTEN22,Enable Interrupt on line 22" "0,1"
|
|
bitfld.long 0x0 21. "INTEN21,Enable Interrupt on line 21" "0,1"
|
|
bitfld.long 0x0 20. "INTEN20,Enable Interrupt on line 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "INTEN19,Enable Interrupt on line 19" "0,1"
|
|
bitfld.long 0x0 18. "INTEN18,Enable Interrupt on line 18" "0,1"
|
|
bitfld.long 0x0 17. "INTEN17,Enable Interrupt on line 17" "0,1"
|
|
bitfld.long 0x0 16. "INTEN16,Enable Interrupt on line 16" "0,1"
|
|
bitfld.long 0x0 15. "INTEN15,Enable Interrupt on line 15" "0,1"
|
|
bitfld.long 0x0 14. "INTEN14,Enable Interrupt on line 14" "0,1"
|
|
bitfld.long 0x0 13. "INTEN13,Enable Interrupt on line 13" "0,1"
|
|
bitfld.long 0x0 12. "INTEN12,Enable Interrupt on line 12" "0,1"
|
|
bitfld.long 0x0 11. "INTEN11,Enable Interrupt on line 11" "0,1"
|
|
bitfld.long 0x0 10. "INTEN10,Enable Interrupt on line 10" "0,1"
|
|
bitfld.long 0x0 9. "INTEN9,Enable Interrupt on line 9" "0,1"
|
|
bitfld.long 0x0 8. "INTEN8,Enable Interrupt on line 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "INTEN7,Enable Interrupt on line 7" "0,1"
|
|
bitfld.long 0x0 6. "INTEN6,Enable Interrupt on line 6" "0,1"
|
|
bitfld.long 0x0 5. "INTEN5,Enable Interrupt on line 5" "0,1"
|
|
bitfld.long 0x0 4. "INTEN4,Enable Interrupt on line 4" "0,1"
|
|
bitfld.long 0x0 3. "INTEN3,Enable Interrupt on line 3" "0,1"
|
|
bitfld.long 0x0 2. "INTEN2,Enable Interrupt on line 2" "0,1"
|
|
bitfld.long 0x0 1. "INTEN1,Enable Interrupt on line 1" "0,1"
|
|
bitfld.long 0x0 0. "INTEN0,Enable Interrupt on line 0" "0,1"
|
|
line.long 0x4 "EVEN0,Event enable register 0 (EXTI_EVEN0)"
|
|
bitfld.long 0x4 31. "EVEN31,Enable Event on line 31" "0,1"
|
|
bitfld.long 0x4 30. "EVEN30,Enable Event on line 30" "0,1"
|
|
bitfld.long 0x4 29. "EVEN29,Enable Event on line 29" "0,1"
|
|
bitfld.long 0x4 28. "EVEN28,Enable Event on line 28" "0,1"
|
|
bitfld.long 0x4 27. "EVEN27,Enable Event on line 27" "0,1"
|
|
bitfld.long 0x4 26. "EVEN26,Enable Event on line 26" "0,1"
|
|
bitfld.long 0x4 25. "EVEN25,Enable Event on line 25" "0,1"
|
|
bitfld.long 0x4 24. "EVEN24,Enable Event on line 24" "0,1"
|
|
bitfld.long 0x4 23. "EVEN23,Enable Event on line 23" "0,1"
|
|
bitfld.long 0x4 22. "EVEN22,Enable Event on line 22" "0,1"
|
|
bitfld.long 0x4 21. "EVEN21,Enable Event on line 21" "0,1"
|
|
bitfld.long 0x4 20. "EVEN20,Enable Event on line 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "EVEN19,Enable Event on line 19" "0,1"
|
|
bitfld.long 0x4 18. "EVEN18,Enable Event on line 18" "0,1"
|
|
bitfld.long 0x4 17. "EVEN17,Enable Event on line 17" "0,1"
|
|
bitfld.long 0x4 16. "EVEN16,Enable Event on line 16" "0,1"
|
|
bitfld.long 0x4 15. "EVEN15,Enable Event on line 15" "0,1"
|
|
bitfld.long 0x4 14. "EVEN14,Enable Event on line 14" "0,1"
|
|
bitfld.long 0x4 13. "EVEN13,Enable Event on line 13" "0,1"
|
|
bitfld.long 0x4 12. "EVEN12,Enable Event on line 12" "0,1"
|
|
bitfld.long 0x4 11. "EVEN11,Enable Event on line 11" "0,1"
|
|
bitfld.long 0x4 10. "EVEN10,Enable Event on line 10" "0,1"
|
|
bitfld.long 0x4 9. "EVEN9,Enable Event on line 9" "0,1"
|
|
bitfld.long 0x4 8. "EVEN8,Enable Event on line 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "EVEN7,Enable Event on line 7" "0,1"
|
|
bitfld.long 0x4 6. "EVEN6,Enable Event on line 6" "0,1"
|
|
bitfld.long 0x4 5. "EVEN5,Enable Event on line 5" "0,1"
|
|
bitfld.long 0x4 4. "EVEN4,Enable Event on line 4" "0,1"
|
|
bitfld.long 0x4 3. "EVEN3,Enable Event on line 3" "0,1"
|
|
bitfld.long 0x4 2. "EVEN2,Enable Event on line 2" "0,1"
|
|
bitfld.long 0x4 1. "EVEN1,Enable Event on line 1" "0,1"
|
|
bitfld.long 0x4 0. "EVEN0,Enable Event on line 0" "0,1"
|
|
line.long 0x8 "RTEN0,Rising Edge Trigger Enable register 0"
|
|
bitfld.long 0x8 31. "RTEN31,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 30. "RTEN30,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 29. "RTEN29,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 28. "RTEN28,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 27. "RTEN27,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 26. "RTEN26,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 25. "RTEN25,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 24. "RTEN24,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 23. "RTEN23,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 22. "RTEN22,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 21. "RTEN21,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 20. "RTEN20,Rising edge trigger enable of" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "RTEN19,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 18. "RTEN18,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 17. "RTEN17,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 16. "RTEN16,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 15. "RTEN15,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 14. "RTEN14,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 13. "RTEN13,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 12. "RTEN12,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 11. "RTEN11,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 10. "RTEN10,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 9. "RTEN9,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 8. "RTEN8,Rising edge trigger enable of" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "RTEN7,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 6. "RTEN6,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 5. "RTEN5,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 4. "RTEN4,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 3. "RTEN3,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 2. "RTEN2,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 1. "RTEN1,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x8 0. "RTEN0,Rising edge trigger enable of" "0,1"
|
|
line.long 0xC "FTEN0,Falling Egde Trigger Enable register 0"
|
|
bitfld.long 0xC 31. "FTEN31,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 30. "FTEN30,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 29. "FTEN29,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 28. "FTEN28,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 27. "FTEN27,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 26. "FTEN26,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 25. "FTEN25,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 24. "FTEN24,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 23. "FTEN23,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 22. "FTEN22,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 21. "FTEN21,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 20. "FTEN20,Falling edge trigger enable of" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "FTEN19,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 18. "FTEN18,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 17. "FTEN17,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 16. "FTEN16,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 15. "FTEN15,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 14. "FTEN14,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 13. "FTEN13,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 12. "FTEN12,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 11. "FTEN11,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 10. "FTEN10,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 9. "FTEN9,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 8. "FTEN8,Falling edge trigger enable of" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "FTEN7,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 6. "FTEN6,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 5. "FTEN5,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 4. "FTEN4,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 3. "FTEN3,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 2. "FTEN2,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 1. "FTEN1,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0xC 0. "FTEN0,Falling edge trigger enable of" "0,1"
|
|
line.long 0x10 "SWIEV0,Software interrupt event register"
|
|
bitfld.long 0x10 31. "SWIEV31,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 30. "SWIEV30,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 29. "SWIEV29,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 28. "SWIEV28,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 27. "SWIEV27,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 26. "SWIEV26,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 25. "SWIEV25,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 24. "SWIEV24,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 23. "SWIEV23,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 22. "SWIEV22,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 21. "SWIEV21,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 20. "SWIEV20,Interrupt/Event software trigger on line" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. "SWIEV19,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 18. "SWIEV18,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 17. "SWIEV17,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 16. "SWIEV16,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 15. "SWIEV15,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 14. "SWIEV14,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 13. "SWIEV13,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 12. "SWIEV12,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 11. "SWIEV11,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 10. "SWIEV10,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 9. "SWIEV9,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 8. "SWIEV8,Interrupt/Event software trigger on line" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "SWIEV7,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 6. "SWIEV6,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 5. "SWIEV5,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 4. "SWIEV4,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 3. "SWIEV3,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 2. "SWIEV2,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 1. "SWIEV1,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x10 0. "SWIEV0,Interrupt/Event software trigger on line" "0,1"
|
|
line.long 0x14 "PD0,Pending register (EXTI_PD0)"
|
|
bitfld.long 0x14 31. "PD31,Interrupt pending status of line 31" "0,1"
|
|
bitfld.long 0x14 30. "PD30,Interrupt pending status of line 30" "0,1"
|
|
bitfld.long 0x14 29. "PD29,Interrupt pending status of line 29" "0,1"
|
|
bitfld.long 0x14 28. "PD28,Interrupt pending status of line 28" "0,1"
|
|
bitfld.long 0x14 27. "PD27,Interrupt pending status of line 27" "0,1"
|
|
bitfld.long 0x14 26. "PD26,Interrupt pending status of line 26" "0,1"
|
|
bitfld.long 0x14 25. "PD25,Interrupt pending status of line 25" "0,1"
|
|
bitfld.long 0x14 24. "PD24,Interrupt pending status of line 24" "0,1"
|
|
bitfld.long 0x14 23. "PD23,Interrupt pending status of line 23" "0,1"
|
|
bitfld.long 0x14 22. "PD22,Interrupt pending status of line 22" "0,1"
|
|
bitfld.long 0x14 21. "PD21,Interrupt pending status of line 21" "0,1"
|
|
bitfld.long 0x14 20. "PD20,Interrupt pending status of line 20" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. "PD19,Interrupt pending status of line 19" "0,1"
|
|
bitfld.long 0x14 18. "PD18,Interrupt pending status of line 18" "0,1"
|
|
bitfld.long 0x14 17. "PD17,Interrupt pending status of line 17" "0,1"
|
|
bitfld.long 0x14 16. "PD16,Interrupt pending status of line 16" "0,1"
|
|
bitfld.long 0x14 15. "PD15,Interrupt pending status of line 15" "0,1"
|
|
bitfld.long 0x14 14. "PD14,Interrupt pending status of line 14" "0,1"
|
|
bitfld.long 0x14 13. "PD13,Interrupt pending status of line 13" "0,1"
|
|
bitfld.long 0x14 12. "PD12,Interrupt pending status of line 12" "0,1"
|
|
bitfld.long 0x14 11. "PD11,Interrupt pending status of line 11" "0,1"
|
|
bitfld.long 0x14 10. "PD10,Interrupt pending status of line 10" "0,1"
|
|
bitfld.long 0x14 9. "PD9,Interrupt pending status of line 9" "0,1"
|
|
bitfld.long 0x14 8. "PD8,Interrupt pending status of line 8" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "PD7,Interrupt pending status of line 7" "0,1"
|
|
bitfld.long 0x14 6. "PD6,Interrupt pending status of line 6" "0,1"
|
|
bitfld.long 0x14 5. "PD5,Interrupt pending status of line 5" "0,1"
|
|
bitfld.long 0x14 4. "PD4,Interrupt pending status of line 4" "0,1"
|
|
bitfld.long 0x14 3. "PD3,Interrupt pending status of line 3" "0,1"
|
|
bitfld.long 0x14 2. "PD2,Interrupt pending status of line 2" "0,1"
|
|
bitfld.long 0x14 1. "PD1,Interrupt pending status of line 1" "0,1"
|
|
bitfld.long 0x14 0. "PD0,Interrupt pending status of line 0" "0,1"
|
|
line.long 0x18 "INTEN1,Interrupt enable register 0"
|
|
bitfld.long 0x18 5. "INTEN37,Enable Interrupt on line 37" "0,1"
|
|
bitfld.long 0x18 4. "INTEN36,Enable Interrupt on line 36" "0,1"
|
|
bitfld.long 0x18 3. "INTEN35,Enable Interrupt on line 35" "0,1"
|
|
bitfld.long 0x18 2. "INTEN34,Enable Interrupt on line 34" "0,1"
|
|
bitfld.long 0x18 1. "INTEN33,Enable Interrupt on line 33" "0,1"
|
|
bitfld.long 0x18 0. "INTEN32,Enable Interrupt on line 32" "0,1"
|
|
line.long 0x1C "EVEN1,Event enable register 1 (EXTI_EVEN1)"
|
|
bitfld.long 0x1C 5. "EVEN37,Enable Event on line 37" "0,1"
|
|
bitfld.long 0x1C 4. "EVEN36,Enable Event on line 36" "0,1"
|
|
bitfld.long 0x1C 3. "EVEN35,Enable Event on line 35" "0,1"
|
|
bitfld.long 0x1C 2. "EVEN34,Enable Event on line 34" "0,1"
|
|
bitfld.long 0x1C 1. "EVEN33,Enable Event on line 33" "0,1"
|
|
bitfld.long 0x1C 0. "EVEN32,Enable Event on line 32" "0,1"
|
|
line.long 0x20 "RTEN1,Rising Edge Trigger Enable register 1"
|
|
bitfld.long 0x20 5. "RTEN37,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x20 4. "RTEN36,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x20 3. "RTEN35,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x20 2. "RTEN34,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x20 1. "RTEN33,Rising edge trigger enable of" "0,1"
|
|
bitfld.long 0x20 0. "RTEN32,Rising edge trigger enable of" "0,1"
|
|
line.long 0x24 "FTEN1,Falling Egde Trigger Enable register 1"
|
|
bitfld.long 0x24 5. "FTEN37,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0x24 4. "FTEN36,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0x24 3. "FTEN35,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0x24 2. "FTEN34,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0x24 1. "FTEN33,Falling edge trigger enable of" "0,1"
|
|
bitfld.long 0x24 0. "FTEN32,Falling edge trigger enable of" "0,1"
|
|
line.long 0x28 "SWIEV1,Software interrupt event register"
|
|
bitfld.long 0x28 5. "SWIEV37,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x28 4. "SWIEV36,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x28 3. "SWIEV35,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x28 2. "SWIEV34,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x28 1. "SWIEV33,Interrupt/Event software trigger on line" "0,1"
|
|
bitfld.long 0x28 0. "SWIEV32,Interrupt/Event software trigger on line" "0,1"
|
|
line.long 0x2C "PD1,Pending register (EXTI_PD1)"
|
|
bitfld.long 0x2C 5. "PD37,Interrupt pending status of line 37" "0,1"
|
|
bitfld.long 0x2C 4. "PD36,Interrupt pending status of line 36" "0,1"
|
|
bitfld.long 0x2C 3. "PD35,Interrupt pending status of line 35" "0,1"
|
|
bitfld.long 0x2C 2. "PD34,Interrupt pending status of line 34" "0,1"
|
|
bitfld.long 0x2C 1. "PD33,Interrupt pending status of line 33" "0,1"
|
|
bitfld.long 0x2C 0. "PD32,Interrupt pending status of line 32" "0,1"
|
|
tree.end
|
|
tree "FAC (Filter Arithmetic Accelerator)"
|
|
base ad:0x48024800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "X0BCFG,FAC X0 buffer configure register"
|
|
bitfld.long 0x0 24.--25. "X0_WBFF,Buffer full flag of watermark" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--15. 1. "X0B_SIZE,X0 buffer size the number of feed-forward taps"
|
|
hexmask.long.byte 0x0 0.--7. 1. "X0B_ADDR,X0 buffer base address"
|
|
line.long 0x4 "X1BCFG,FAC X1 buffer configure register"
|
|
hexmask.long.byte 0x4 8.--15. 1. "X1B_SIZE,X1 buffer size"
|
|
hexmask.long.byte 0x4 0.--7. 1. "X1B_ADDR,X1 buffer base address"
|
|
line.long 0x8 "YBCFG,FAC Y buffer configure register"
|
|
bitfld.long 0x8 24.--25. "Y_WBEF,Buffer empty flag of watermark" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--15. 1. "YB_SIZE,Y buffer size"
|
|
hexmask.long.byte 0x8 0.--7. 1. "YB_ADDR,Y buffer base address"
|
|
line.long 0xC "PARACFG,FAC Parameter configure register"
|
|
bitfld.long 0xC 31. "EXE,Execution" "0,1"
|
|
hexmask.long.byte 0xC 24.--30. 1. "FUN,Function"
|
|
hexmask.long.byte 0xC 16.--23. 1. "IPR,Input parameter IPR"
|
|
hexmask.long.byte 0xC 8.--15. 1. "IPQ,Input parameter IPQ"
|
|
hexmask.long.byte 0xC 0.--7. 1. "IPP,Input parameter IPP"
|
|
line.long 0x10 "CTL,FAC Control register"
|
|
bitfld.long 0x10 16. "RST,Reset FAC unit" "0,1"
|
|
bitfld.long 0x10 15. "CPEN,Clipping enable" "0,1"
|
|
bitfld.long 0x10 14. "FLTEN,Floating point format enable" "0,1"
|
|
bitfld.long 0x10 9. "DWEN,DMA write channel enable" "0,1"
|
|
bitfld.long 0x10 8. "DREN,DMA read channel enable" "0,1"
|
|
bitfld.long 0x10 5. "GSTEIE,Gain saturation error interrupt enable" "0,1"
|
|
bitfld.long 0x10 4. "STEIE,Saturation error interrupt enable" "0,1"
|
|
bitfld.long 0x10 3. "UFEIE,Underflow error interrupt enable" "0,1"
|
|
bitfld.long 0x10 2. "OFEIE,Overflow error interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "WIE,Write interrupt enable" "0,1"
|
|
bitfld.long 0x10 0. "RIE,Read interrupt enable" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "STAT,FAC Status register"
|
|
bitfld.long 0x0 11. "GSTEF,Gain saturation error flag it is set when gain exceed range" "0,1"
|
|
bitfld.long 0x0 10. "STEF,Saturation error flag" "0,1"
|
|
bitfld.long 0x0 9. "UFEF,Underflow error flag" "0,1"
|
|
bitfld.long 0x0 8. "OFEF,Overflow error flag" "0,1"
|
|
bitfld.long 0x0 1. "X0BFF,X0 buffer full flag" "0,1"
|
|
bitfld.long 0x0 0. "YBEF,Y buffer empty flag" "0,1"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "WDATA,FAC write data register"
|
|
hexmask.long 0x0 0.--31. 1. "WDATA,Write data"
|
|
line.long 0x4 "RDATA,FAC read data register"
|
|
hexmask.long 0x4 0.--31. 1. "RDATA,Read data"
|
|
tree.end
|
|
tree "FMC (Flash Memory Controller)"
|
|
base ad:0x52002000
|
|
wgroup.long 0x4++0x7
|
|
line.long 0x0 "KEY,Unlock key register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,FMC_CTL unlock register"
|
|
line.long 0x4 "OBKEY,Option byte unlock key register"
|
|
hexmask.long 0x4 0.--31. 1. "OBKEY,These bits are only be written by software."
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "CTL,Control register"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x0 26. "ECCDETIE,Two bit errors detect interrupt enable" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x0 25. "ECCCORIE,One bit error correct interrupt enable" "0,1"
|
|
endif
|
|
bitfld.long 0x0 24. "RSERRIE,Read secure error interrupt enable." "0,1"
|
|
bitfld.long 0x0 23. "RPERRIE,Read protection error interrupt enable" "0,1"
|
|
bitfld.long 0x0 18. "PGSERRIE,Program sequence error interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "WPERRIE,Erase/program protection error interrupt enable" "0,1"
|
|
bitfld.long 0x0 16. "ENDIE,End of operation interrupt enable" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x0 7. "START,Send erase command to FMC" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x0 7. "START,Send erase command to FMC" "0,1"
|
|
bitfld.long 0x0 0. "LK,FMC_CTL lock bit" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 4. "PGCHEN,Check programming area enable" "0,1"
|
|
bitfld.long 0x0 3. "MER,Mass erase command bit" "0,1"
|
|
bitfld.long 0x0 2. "SER,Sector erase command bit" "0,1"
|
|
bitfld.long 0x0 1. "PG,Main Flash program command bit" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x0 0. "LK,FMC_CTL lock bit" "0,1"
|
|
endif
|
|
line.long 0x4 "STAT,Status register"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x4 31. "FECCF,Flash ECC function flag" "0,1"
|
|
endif
|
|
bitfld.long 0x4 30. "OBMERR,Option byte modify error flag ." "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x4 26. "ECCDET,Two bit errors detect flag" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x4 25. "ECCCOR,One bit error detected and correct flag" "0,1"
|
|
endif
|
|
bitfld.long 0x4 24. "RSERR,Read secure error flag bit." "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "RPERR,Read protection error flag bit." "0,1"
|
|
bitfld.long 0x4 18. "PGSERR,Program sequence error flag bit." "0,1"
|
|
bitfld.long 0x4 17. "WPERR,Erase/program protection error flag bit." "0,1"
|
|
bitfld.long 0x4 16. "ENDF,End of operation flag bit." "0,1"
|
|
rbitfld.long 0x4 0. "BUSY,The Flash is busy bit" "0,1"
|
|
line.long 0x8 "ADDR,Address register"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Flash erase command address bits"
|
|
line.long 0xC "OBCTL,Option byte control register"
|
|
bitfld.long 0xC 30. "OBMERRIE,Option byte modify error interrupt enable." "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0xC 1. "OBSTART,Send option byte change command to FMC bit" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0xC 1. "OBSTART,Send option byte change command to FMC bit." "0,1"
|
|
bitfld.long 0xC 0. "OBLK,FMC_OBCTL lock bit" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0xC 0. "OBLK,FMC_OBCTL lock bit" "0,1"
|
|
endif
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "OBSTAT0_EFT,Option byte status register 0"
|
|
bitfld.long 0x0 29. "IOSPDOPEN,Allowed enable status bit for I/O speed optimization at low-voltage." "0,1"
|
|
bitfld.long 0x0 24. "DTCM1ECCEN,DTCM1 ECC function enable status bit" "0,1"
|
|
bitfld.long 0x0 23. "DTCM0ECCEN,DTCM0 ECC function enable status bit" "0,1"
|
|
bitfld.long 0x0 22. "ITCMECCEN,ITCM ECC function enable status bit" "0,1"
|
|
bitfld.long 0x0 21. "SCR,Secure mode status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "FWDGSPD_STDBY,FWDGT suspend option in standby mode status bit" "0,1"
|
|
bitfld.long 0x0 17. "FWDGSPD_DPSLP,FWDGT suspend option in deepsleep mode status bit" "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "SPC,Security protection level option byte status bits"
|
|
bitfld.long 0x0 7. "nRST_STDBY,Option byte standby reset status bit" "0,1"
|
|
bitfld.long 0x0 6. "nRST_DPSLP,Option byte deepsleep reset status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "nWDG_HW,Watchdog status bit" "0,1"
|
|
bitfld.long 0x0 2.--3. "BOR_TH,BOR threshold status bits" "0,1,2,3"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "OBSTAT0_MDF,Option byte status register 0"
|
|
bitfld.long 0x0 29. "IOSPDOPEN,Allowed enable configuration bit for I/O speed optimization at low-voltage." "0,1"
|
|
bitfld.long 0x0 24. "DTCM1ECCEN,DTCM1 ECC function enable configuration bit" "0,1"
|
|
bitfld.long 0x0 23. "DTCM0ECCEN,DTCM0 ECC function enable configuration bit" "0,1"
|
|
bitfld.long 0x0 22. "ITCMECCEN,ITCM ECC function enable configuration bit" "0,1"
|
|
bitfld.long 0x0 21. "SCR,Secure mode configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "FWDGSPD_STDBY,FWDGT suspend option in standby mode configuration bit" "0,1"
|
|
bitfld.long 0x0 17. "FWDGSPD_DPSLP,FWDGT suspend option in deepsleep mode configuration bit" "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "SPC,Security protection level option configuration bits"
|
|
bitfld.long 0x0 7. "nRST_STDBY,Option byte standby reset configuration bit" "0,1"
|
|
bitfld.long 0x0 6. "nRST_DPSLP,Option byte deepsleep reset configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "nWDG_HW,Watchdog configuration bit" "0,1"
|
|
bitfld.long 0x0 2.--3. "BOR_TH,BOR threshold configuration bits" "0,1,2,3"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "DCRPADDR_EFT,DCRP address register"
|
|
bitfld.long 0x0 31. "DCRP_EREN,DCRP area erase enable status bit." "0,1"
|
|
hexmask.long.word 0x0 16.--26. 1. "DCRP_AREA_END,DCRP area end address status bits"
|
|
hexmask.long.word 0x0 0.--10. 1. "DCRP_AREA_START,DCRP area start address status bits"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "DCRPADDR_MDF,DCRP address register"
|
|
bitfld.long 0x0 31. "DCRP_EREN,DCRP area erase enable configuration bit." "0,1"
|
|
hexmask.long.word 0x0 16.--26. 1. "DCRP_AREA_END,DCRP area end address configuration bits"
|
|
hexmask.long.word 0x0 0.--10. 1. "DCRP_AREA_START,DCRP area start address configuration bits"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "SCRADDR_EFT,Secure address register"
|
|
bitfld.long 0x0 31. "SCR_EREN,Secure user area erase enable option status bit." "0,1"
|
|
hexmask.long.word 0x0 16.--26. 1. "SCR_AREA_END,Secure user area end address status bits"
|
|
hexmask.long.word 0x0 0.--10. 1. "SCR_AREA_START,Secure user area start address status bits"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "SCRADDR_MDF,Secure address register"
|
|
bitfld.long 0x0 31. "SCR_EREN,Secure user area erase enable option configuration bit." "0,1"
|
|
hexmask.long.word 0x0 16.--26. 1. "SCR_AREA_END,Secure user area end address configuration bits"
|
|
hexmask.long.word 0x0 0.--10. 1. "SCR_AREA_START,Secure user area start address configuration bits"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "WP_EFT,Erase/program protection register"
|
|
sif (cpuis("GD32H75E*"))
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "WP,Sector erase/program protection option status bit"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
hexmask.long 0x0 0.--29. 1. "WP,Sector erase/program protection option status bit"
|
|
endif
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "WP_MDF,Erase/program protection register"
|
|
sif (cpuis("GD32H75E*"))
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "WP,Sector erase/program protection option configuration bit"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
hexmask.long 0x0 0.--29. 1. "WP,Sector erase/program protection option configuration bit"
|
|
endif
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "BTADDR_EFT,Boot address register"
|
|
hexmask.long.word 0x0 16.--31. 1. "BOOT_ADDR1,Boot address 1 status bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "BOOT_ADDR0,Boot address 0 status bits"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "BTADDR_MDF,Boot address register"
|
|
hexmask.long.word 0x0 16.--31. 1. "BOOT_ADDR1,Boot address 1 configuration bits."
|
|
hexmask.long.word 0x0 0.--15. 1. "BOOT_ADDR0,Boot address 0 configuration bits."
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "OBSTAT1_EFT,Option byte status register 1"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA,User defined option byte data status value"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTCM_SZ_SHRRAM,DTCM size of shared RAM status bits."
|
|
hexmask.long.byte 0x0 0.--3. 1. "ITCM_SZ_SHRRAM,ITCM size of shared RAM status bits."
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "OBSTAT1_MDF,Option byte status register 1"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA,User defined option byte data configuration value"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTCM_SZ_SHRRAM,DTCM size of shared RAM configuration bits."
|
|
hexmask.long.byte 0x0 0.--3. 1. "ITCM_SZ_SHRRAM,ITCM size of shared RAM configuration bits."
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "NODEC,NO-RTDEC area register"
|
|
hexmask.long.word 0x0 16.--26. 1. "NODEC_AREA_END,NO-RTDEC area end address"
|
|
hexmask.long.word 0x0 0.--10. 1. "NODEC_AREA_START,No-RTDEC area start address"
|
|
rgroup.long 0x68++0xB
|
|
line.long 0x0 "AESIV0_EFT,AES IV regist 0"
|
|
hexmask.long 0x0 0.--31. 1. "AESIV,AES initialization vector status value"
|
|
line.long 0x4 "AESIV1_EFT,AES IV regist 1"
|
|
hexmask.long 0x4 0.--31. 1. "AESIV,AES initialization vector status value"
|
|
line.long 0x8 "AESIV2_EFT,AES IV regist 2"
|
|
hexmask.long 0x8 0.--31. 1. "AESIV,AES initialization vector status value"
|
|
group.long 0x74++0xB
|
|
line.long 0x0 "AESIV0_MDF,AES IV regist 0"
|
|
sif (cpuis("GD32H75E*"))
|
|
hexmask.long 0x0 0.--31. 1. "AESIV,AES initialization vector configuration value"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
hexmask.long 0x0 0.--31. 1. "AESIV,AES initialization vector configuration value"
|
|
endif
|
|
line.long 0x4 "AESIV1_MDF,AES IV regist 1"
|
|
sif (cpuis("GD32H75E*"))
|
|
hexmask.long 0x4 0.--31. 1. "AESIV,AES initialization vector configuration value"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
hexmask.long 0x4 0.--31. 1. "AESIV,AES initialization vector status value"
|
|
endif
|
|
line.long 0x8 "AESIV2_MDF,AES IV regist 2"
|
|
sif (cpuis("GD32H75E*"))
|
|
hexmask.long 0x8 0.--31. 1. "AESIV,AES initialization vector configuration value"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
hexmask.long 0x8 0.--31. 1. "AESIV,AES initialization vector status value"
|
|
endif
|
|
rgroup.long 0x100++0x7
|
|
line.long 0x0 "PID0,Product ID register 0"
|
|
sif (cpuis("GD32H75E*"))
|
|
hexmask.long 0x0 0.--31. 1. "PID,Product reserved ID code register x"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
hexmask.long 0x0 0.--31. 1. "PID0,Product reserved ID code register x"
|
|
endif
|
|
line.long 0x4 "PID1,Product ID register 1"
|
|
sif (cpuis("GD32H75E*"))
|
|
hexmask.long 0x4 0.--31. 1. "PID,Product reserved ID code register x"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
hexmask.long 0x4 0.--31. 1. "PID1,Product reserved ID code register x"
|
|
endif
|
|
tree.end
|
|
tree "FWDGT (Free Watchdog Timer)"
|
|
base ad:0x58004800
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMD,Key value"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "PSC,Prescaler register"
|
|
bitfld.long 0x0 0.--2. "PSC,Prescaler divider" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RLD,Reload register"
|
|
hexmask.long.word 0x4 0.--11. 1. "RLD,Watchdog counter reload"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "STAT,Status register"
|
|
bitfld.long 0x0 2. "WUD,Watchdog counter window value" "0,1"
|
|
bitfld.long 0x0 1. "RUD,Watchdog counter reload value" "0,1"
|
|
bitfld.long 0x0 0. "PUD,Watchdog prescaler value" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "WND,Window register"
|
|
hexmask.long.word 0x0 0.--11. 1. "WND,Watchdog counter window"
|
|
tree.end
|
|
tree "GPIO (General Purpose I/Os)"
|
|
base ad:0x0
|
|
tree "GPIOA"
|
|
base ad:0x58020000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTL,GPIO port control register"
|
|
bitfld.long 0x0 30.--31. "CTL15,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "CTL14,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "CTL13,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "CTL12,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "CTL11,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "CTL10,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "CTL9,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "CTL8,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "CTL7,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CTL6,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "CTL5,Port x configuration bits (x =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CTL4,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "CTL3,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "CTL2,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "CTL1,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CTL0,Port x configuration bits (x =" "0,1,2,3"
|
|
line.long 0x4 "OMODE,GPIO port output mode register"
|
|
bitfld.long 0x4 15. "OM15,Port 15 output mode bit" "0,1"
|
|
bitfld.long 0x4 14. "OM14,Port 14 output mode bit" "0,1"
|
|
bitfld.long 0x4 13. "OM13,Port 13 output mode bit" "0,1"
|
|
bitfld.long 0x4 12. "OM12,Port 12 output mode bit" "0,1"
|
|
bitfld.long 0x4 11. "OM11,Port 11 output mode bit" "0,1"
|
|
bitfld.long 0x4 10. "OM10,Port 10 output mode bit" "0,1"
|
|
bitfld.long 0x4 9. "OM9,Port 9 output mode bit" "0,1"
|
|
bitfld.long 0x4 8. "OM8,Port 8 output mode bit" "0,1"
|
|
bitfld.long 0x4 7. "OM7,Port 7 output mode bit" "0,1"
|
|
bitfld.long 0x4 6. "OM6,Port 6 output mode bit" "0,1"
|
|
bitfld.long 0x4 5. "OM5,Port 5 output mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "OM4,Port 4 output mode bit" "0,1"
|
|
bitfld.long 0x4 3. "OM3,Port 3 output mode bit" "0,1"
|
|
bitfld.long 0x4 2. "OM2,Port 2 output mode bit" "0,1"
|
|
bitfld.long 0x4 1. "OM1,Port 1 output mode bit" "0,1"
|
|
bitfld.long 0x4 0. "OM0,Port 0 output mode bit" "0,1"
|
|
line.long 0x8 "OSPD,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPD15,Port 15 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPD14,Port 14 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPD13,Port 13 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPD12,Port 12 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPD11,Port 11 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPD10,Port 10 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPD9,Port 9 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPD8,Port 8 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPD7,Port 7 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPD6,Port 6 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "OSPD5,Port 5 output max speed bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "OSPD4,Port 4 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPD3,Port 3 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPD2,Port 2 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPD1,Port 1 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPD0,Port 0 output max speed bits" "0,1,2,3"
|
|
line.long 0xC "PUD,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUD15,Port 15 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUD14,Port 14 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUD13,Port 13 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUD12,Port 12 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUD11,Port 11 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUD10,Port 10 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUD9,Port 9 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUD8,Port 8 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUD7,Port 7 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUD6,Port 6 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUD5,Port 5 pull-up or pull-down bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "PUD4,Port 4 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUD3,Port 3 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUD2,Port 2 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUD1,Port 1 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUD0,Port 0 pull-up or pull-down bits" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "ISTAT,GPIO port input status register"
|
|
bitfld.long 0x0 15. "ISTAT15,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 14. "ISTAT14,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 13. "ISTAT13,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 12. "ISTAT12,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 11. "ISTAT11,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 10. "ISTAT10,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 9. "ISTAT9,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 8. "ISTAT8,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 7. "ISTAT7,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 6. "ISTAT6,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 5. "ISTAT5,Port input status (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ISTAT4,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 3. "ISTAT3,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 2. "ISTAT2,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 1. "ISTAT1,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 0. "ISTAT0,Port input status (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "OCTL,GPIO port output control register"
|
|
bitfld.long 0x0 15. "OCTL15,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 14. "OCTL14,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 13. "OCTL13,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 12. "OCTL12,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 11. "OCTL11,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 10. "OCTL10,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 9. "OCTL9,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 8. "OCTL8,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 7. "OCTL7,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 6. "OCTL6,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 5. "OCTL5,Port output control (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "OCTL4,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 3. "OCTL3,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 2. "OCTL2,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 1. "OCTL1,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 0. "OCTL0,Port output control (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BOP,GPIO port bit operate register"
|
|
bitfld.long 0x0 31. "CR15,Port Clear bit 15" "0,1"
|
|
bitfld.long 0x0 30. "CR14,Port Clear bit 14" "0,1"
|
|
bitfld.long 0x0 29. "CR13,Port Clear bit 13" "0,1"
|
|
bitfld.long 0x0 28. "CR12,Port Clear bit 12" "0,1"
|
|
bitfld.long 0x0 27. "CR11,Port Clear bit 11" "0,1"
|
|
bitfld.long 0x0 26. "CR10,Port Clear bit 10" "0,1"
|
|
bitfld.long 0x0 25. "CR9,Port Clear bit 9" "0,1"
|
|
bitfld.long 0x0 24. "CR8,Port Clear bit 8" "0,1"
|
|
bitfld.long 0x0 23. "CR7,Port Clear bit 7" "0,1"
|
|
bitfld.long 0x0 22. "CR6,Port Clear bit 6" "0,1"
|
|
bitfld.long 0x0 21. "CR5,Port Clear bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "CR4,Port Clear bit 4" "0,1"
|
|
bitfld.long 0x0 19. "CR3,Port Clear bit 3" "0,1"
|
|
bitfld.long 0x0 18. "CR2,Port Clear bit 2" "0,1"
|
|
bitfld.long 0x0 17. "CR1,Port Clear bit 1" "0,1"
|
|
bitfld.long 0x0 16. "CR0,Port Clear bit 0" "0,1"
|
|
bitfld.long 0x0 15. "BOP15,Port Set bit 15" "0,1"
|
|
bitfld.long 0x0 14. "BOP14,Port Set bit 14" "0,1"
|
|
bitfld.long 0x0 13. "BOP13,Port Set bit 13" "0,1"
|
|
bitfld.long 0x0 12. "BOP12,Port Set bit 12" "0,1"
|
|
bitfld.long 0x0 11. "BOP11,Port Set bit 11" "0,1"
|
|
bitfld.long 0x0 10. "BOP10,Port Set bit 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "BOP9,Port Set bit 9" "0,1"
|
|
bitfld.long 0x0 8. "BOP8,Port Set bit 8" "0,1"
|
|
bitfld.long 0x0 7. "BOP7,Port Set bit 7" "0,1"
|
|
bitfld.long 0x0 6. "BOP6,Port Set bit 6" "0,1"
|
|
bitfld.long 0x0 5. "BOP5,Port Set bit 5" "0,1"
|
|
bitfld.long 0x0 4. "BOP4,Port Set bit 4" "0,1"
|
|
bitfld.long 0x0 3. "BOP3,Port Set bit 3" "0,1"
|
|
bitfld.long 0x0 2. "BOP2,Port Set bit 2" "0,1"
|
|
bitfld.long 0x0 1. "BOP1,Port Set bit 1" "0,1"
|
|
bitfld.long 0x0 0. "BOP0,Port Set bit 0" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LOCK,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LKK,Lock sequence key" "0,1"
|
|
bitfld.long 0x0 15. "LK15,Port Lock bit 15" "0,1"
|
|
bitfld.long 0x0 14. "LK14,Port Lock bit 14" "0,1"
|
|
bitfld.long 0x0 13. "LK13,Port Lock bit 13" "0,1"
|
|
bitfld.long 0x0 12. "LK12,Port Lock bit 12" "0,1"
|
|
bitfld.long 0x0 11. "LK11,Port Lock bit 11" "0,1"
|
|
bitfld.long 0x0 10. "LK10,Port Lock bit 10" "0,1"
|
|
bitfld.long 0x0 9. "LK9,Port Lock bit 9" "0,1"
|
|
bitfld.long 0x0 8. "LK8,Port Lock bit 8" "0,1"
|
|
bitfld.long 0x0 7. "LK7,Port Lock bit 7" "0,1"
|
|
bitfld.long 0x0 6. "LK6,Port Lock bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LK5,Port Lock bit 5" "0,1"
|
|
bitfld.long 0x0 4. "LK4,Port Lock bit 4" "0,1"
|
|
bitfld.long 0x0 3. "LK3,Port Lock bit 3" "0,1"
|
|
bitfld.long 0x0 2. "LK2,Port Lock bit 2" "0,1"
|
|
bitfld.long 0x0 1. "LK1,Port Lock bit 1" "0,1"
|
|
bitfld.long 0x0 0. "LK0,Port Lock bit 0" "0,1"
|
|
line.long 0x4 "AFSEL0,GPIO alternate function selected register 0"
|
|
hexmask.long.byte 0x4 28.--31. 1. "SEL7,Port 7 alternate function selected"
|
|
hexmask.long.byte 0x4 24.--27. 1. "SEL6,Port 6 alternate function selected"
|
|
hexmask.long.byte 0x4 20.--23. 1. "SEL5,Port 5 alternate function selected"
|
|
hexmask.long.byte 0x4 16.--19. 1. "SEL4,Port 4 alternate function selected"
|
|
hexmask.long.byte 0x4 12.--15. 1. "SEL3,Port 3 alternate function selected"
|
|
hexmask.long.byte 0x4 8.--11. 1. "SEL2,Port 2 alternate function selected"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SEL1,Port 1 alternate function selected"
|
|
hexmask.long.byte 0x4 0.--3. 1. "SEL0,Port 0 alternate function selected"
|
|
line.long 0x8 "AFSEL1,GPIO alternate function selected register 1"
|
|
hexmask.long.byte 0x8 28.--31. 1. "SEL15,Port 15 alternate function selected"
|
|
hexmask.long.byte 0x8 24.--27. 1. "SEL14,Port 14 alternate function selected"
|
|
hexmask.long.byte 0x8 20.--23. 1. "SEL13,Port 13 alternate function selected"
|
|
hexmask.long.byte 0x8 16.--19. 1. "SEL12,Port 12 alternate function selected"
|
|
hexmask.long.byte 0x8 12.--15. 1. "SEL11,Port 11 alternate function selected"
|
|
hexmask.long.byte 0x8 8.--11. 1. "SEL10,Port 10 alternate function selected"
|
|
hexmask.long.byte 0x8 4.--7. 1. "SEL9,Port 9 alternate function selected"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SEL8,Port 8 alternate function selected"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "BC,Bit clear register"
|
|
bitfld.long 0x0 15. "CR15,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 14. "CR14,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 13. "CR13,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 12. "CR12,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 11. "CR11,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 10. "CR10,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 9. "CR9,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 8. "CR8,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 7. "CR7,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 6. "CR6,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 5. "CR5,Port cleat bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CR4,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 3. "CR3,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 2. "CR2,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 1. "CR1,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 0. "CR0,Port cleat bit" "0,1"
|
|
line.long 0x4 "TG,Port bit toggle register"
|
|
bitfld.long 0x4 15. "TG15,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 14. "TG14,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 13. "TG13,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 12. "TG12,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 11. "TG11,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 10. "TG10,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 9. "TG9,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 8. "TG8,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 7. "TG7,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 6. "TG6,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 5. "TG5,Port toggle bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TG4,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 3. "TG3,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 2. "TG2,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 1. "TG1,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 0. "TG0,Port toggle bit" "0,1"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "IFL,Input filtering regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FLPRD1,Filter sampling period for GPIO8 to GPIO15:"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FLPRD0,Filter sampling period for GPIO1 to GPIO7:"
|
|
line.long 0x4 "IFTP,Input filtering type regist"
|
|
bitfld.long 0x4 30.--31. "IFTP15,Pin 15 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "IFTP14,Pin 14 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "IFTP13,Pin 13 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "IFTP12,Pin 12 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "IFTP11,Pin 11 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "IFTP10,Pin 10 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "IFTP9,Pin 9 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "IFTP8,Pin 8 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "IFTP7,Pin 7 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "IFTP6,Pin 6 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "IFTP5,Pin 5 input filtering type bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "IFTP4,Pin 4 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "IFTP3,Pin 3 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "IFTP2,Pin 2 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "IFTP1,Pin 1 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "IFTP0,Pin 0 input filtering type bits" "0,1,2,3"
|
|
tree.end
|
|
tree "GPIOB"
|
|
base ad:0x58020400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTL,GPIO port control register"
|
|
bitfld.long 0x0 30.--31. "CTL15,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "CTL14,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "CTL13,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "CTL12,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "CTL11,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "CTL10,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "CTL9,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "CTL8,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "CTL7,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CTL6,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "CTL5,Port x configuration bits (x =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CTL4,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "CTL3,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "CTL2,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "CTL1,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CTL0,Port x configuration bits (x =" "0,1,2,3"
|
|
line.long 0x4 "OMODE,GPIO port output mode register"
|
|
bitfld.long 0x4 15. "OM15,Port 15 output mode bit" "0,1"
|
|
bitfld.long 0x4 14. "OM14,Port 14 output mode bit" "0,1"
|
|
bitfld.long 0x4 13. "OM13,Port 13 output mode bit" "0,1"
|
|
bitfld.long 0x4 12. "OM12,Port 12 output mode bit" "0,1"
|
|
bitfld.long 0x4 11. "OM11,Port 11 output mode bit" "0,1"
|
|
bitfld.long 0x4 10. "OM10,Port 10 output mode bit" "0,1"
|
|
bitfld.long 0x4 9. "OM9,Port 9 output mode bit" "0,1"
|
|
bitfld.long 0x4 8. "OM8,Port 8 output mode bit" "0,1"
|
|
bitfld.long 0x4 7. "OM7,Port 7 output mode bit" "0,1"
|
|
bitfld.long 0x4 6. "OM6,Port 6 output mode bit" "0,1"
|
|
bitfld.long 0x4 5. "OM5,Port 5 output mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "OM4,Port 4 output mode bit" "0,1"
|
|
bitfld.long 0x4 3. "OM3,Port 3 output mode bit" "0,1"
|
|
bitfld.long 0x4 2. "OM2,Port 2 output mode bit" "0,1"
|
|
bitfld.long 0x4 1. "OM1,Port 1 output mode bit" "0,1"
|
|
bitfld.long 0x4 0. "OM0,Port 0 output mode bit" "0,1"
|
|
line.long 0x8 "OSPD,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPD15,Port 15 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPD14,Port 14 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPD13,Port 13 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPD12,Port 12 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPD11,Port 11 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPD10,Port 10 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPD9,Port 9 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPD8,Port 8 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPD7,Port 7 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPD6,Port 6 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "OSPD5,Port 5 output max speed bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "OSPD4,Port 4 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPD3,Port 3 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPD2,Port 2 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPD1,Port 1 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPD0,Port 0 output max speed bits" "0,1,2,3"
|
|
line.long 0xC "PUD,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUD15,Port 15 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUD14,Port 14 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUD13,Port 13 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUD12,Port 12 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUD11,Port 11 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUD10,Port 10 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUD9,Port 9 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUD8,Port 8 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUD7,Port 7 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUD6,Port 6 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUD5,Port 5 pull-up or pull-down bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "PUD4,Port 4 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUD3,Port 3 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUD2,Port 2 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUD1,Port 1 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUD0,Port 0 pull-up or pull-down bits" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "ISTAT,GPIO port input status register"
|
|
bitfld.long 0x0 15. "ISTAT15,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 14. "ISTAT14,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 13. "ISTAT13,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 12. "ISTAT12,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 11. "ISTAT11,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 10. "ISTAT10,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 9. "ISTAT9,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 8. "ISTAT8,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 7. "ISTAT7,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 6. "ISTAT6,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 5. "ISTAT5,Port input status (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ISTAT4,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 3. "ISTAT3,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 2. "ISTAT2,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 1. "ISTAT1,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 0. "ISTAT0,Port input status (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "OCTL,GPIO port output control register"
|
|
bitfld.long 0x0 15. "OCTL15,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 14. "OCTL14,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 13. "OCTL13,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 12. "OCTL12,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 11. "OCTL11,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 10. "OCTL10,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 9. "OCTL9,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 8. "OCTL8,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 7. "OCTL7,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 6. "OCTL6,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 5. "OCTL5,Port output control (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "OCTL4,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 3. "OCTL3,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 2. "OCTL2,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 1. "OCTL1,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 0. "OCTL0,Port output control (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BOP,GPIO port bit operate register"
|
|
bitfld.long 0x0 31. "CR15,Port Clear bit 15" "0,1"
|
|
bitfld.long 0x0 30. "CR14,Port Clear bit 14" "0,1"
|
|
bitfld.long 0x0 29. "CR13,Port Clear bit 13" "0,1"
|
|
bitfld.long 0x0 28. "CR12,Port Clear bit 12" "0,1"
|
|
bitfld.long 0x0 27. "CR11,Port Clear bit 11" "0,1"
|
|
bitfld.long 0x0 26. "CR10,Port Clear bit 10" "0,1"
|
|
bitfld.long 0x0 25. "CR9,Port Clear bit 9" "0,1"
|
|
bitfld.long 0x0 24. "CR8,Port Clear bit 8" "0,1"
|
|
bitfld.long 0x0 23. "CR7,Port Clear bit 7" "0,1"
|
|
bitfld.long 0x0 22. "CR6,Port Clear bit 6" "0,1"
|
|
bitfld.long 0x0 21. "CR5,Port Clear bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "CR4,Port Clear bit 4" "0,1"
|
|
bitfld.long 0x0 19. "CR3,Port Clear bit 3" "0,1"
|
|
bitfld.long 0x0 18. "CR2,Port Clear bit 2" "0,1"
|
|
bitfld.long 0x0 17. "CR1,Port Clear bit 1" "0,1"
|
|
bitfld.long 0x0 16. "CR0,Port Clear bit 0" "0,1"
|
|
bitfld.long 0x0 15. "BOP15,Port Set bit 15" "0,1"
|
|
bitfld.long 0x0 14. "BOP14,Port Set bit 14" "0,1"
|
|
bitfld.long 0x0 13. "BOP13,Port Set bit 13" "0,1"
|
|
bitfld.long 0x0 12. "BOP12,Port Set bit 12" "0,1"
|
|
bitfld.long 0x0 11. "BOP11,Port Set bit 11" "0,1"
|
|
bitfld.long 0x0 10. "BOP10,Port Set bit 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "BOP9,Port Set bit 9" "0,1"
|
|
bitfld.long 0x0 8. "BOP8,Port Set bit 8" "0,1"
|
|
bitfld.long 0x0 7. "BOP7,Port Set bit 7" "0,1"
|
|
bitfld.long 0x0 6. "BOP6,Port Set bit 6" "0,1"
|
|
bitfld.long 0x0 5. "BOP5,Port Set bit 5" "0,1"
|
|
bitfld.long 0x0 4. "BOP4,Port Set bit 4" "0,1"
|
|
bitfld.long 0x0 3. "BOP3,Port Set bit 3" "0,1"
|
|
bitfld.long 0x0 2. "BOP2,Port Set bit 2" "0,1"
|
|
bitfld.long 0x0 1. "BOP1,Port Set bit 1" "0,1"
|
|
bitfld.long 0x0 0. "BOP0,Port Set bit 0" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LOCK,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LKK,Lock sequence key" "0,1"
|
|
bitfld.long 0x0 15. "LK15,Port Lock bit 15" "0,1"
|
|
bitfld.long 0x0 14. "LK14,Port Lock bit 14" "0,1"
|
|
bitfld.long 0x0 13. "LK13,Port Lock bit 13" "0,1"
|
|
bitfld.long 0x0 12. "LK12,Port Lock bit 12" "0,1"
|
|
bitfld.long 0x0 11. "LK11,Port Lock bit 11" "0,1"
|
|
bitfld.long 0x0 10. "LK10,Port Lock bit 10" "0,1"
|
|
bitfld.long 0x0 9. "LK9,Port Lock bit 9" "0,1"
|
|
bitfld.long 0x0 8. "LK8,Port Lock bit 8" "0,1"
|
|
bitfld.long 0x0 7. "LK7,Port Lock bit 7" "0,1"
|
|
bitfld.long 0x0 6. "LK6,Port Lock bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LK5,Port Lock bit 5" "0,1"
|
|
bitfld.long 0x0 4. "LK4,Port Lock bit 4" "0,1"
|
|
bitfld.long 0x0 3. "LK3,Port Lock bit 3" "0,1"
|
|
bitfld.long 0x0 2. "LK2,Port Lock bit 2" "0,1"
|
|
bitfld.long 0x0 1. "LK1,Port Lock bit 1" "0,1"
|
|
bitfld.long 0x0 0. "LK0,Port Lock bit 0" "0,1"
|
|
line.long 0x4 "AFSEL0,GPIO alternate function selected register 0"
|
|
hexmask.long.byte 0x4 28.--31. 1. "SEL7,Port 7 alternate function selected"
|
|
hexmask.long.byte 0x4 24.--27. 1. "SEL6,Port 6 alternate function selected"
|
|
hexmask.long.byte 0x4 20.--23. 1. "SEL5,Port 5 alternate function selected"
|
|
hexmask.long.byte 0x4 16.--19. 1. "SEL4,Port 4 alternate function selected"
|
|
hexmask.long.byte 0x4 12.--15. 1. "SEL3,Port 3 alternate function selected"
|
|
hexmask.long.byte 0x4 8.--11. 1. "SEL2,Port 2 alternate function selected"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SEL1,Port 1 alternate function selected"
|
|
hexmask.long.byte 0x4 0.--3. 1. "SEL0,Port 0 alternate function selected"
|
|
line.long 0x8 "AFSEL1,GPIO alternate function selected register 1"
|
|
hexmask.long.byte 0x8 28.--31. 1. "SEL15,Port 15 alternate function selected"
|
|
hexmask.long.byte 0x8 24.--27. 1. "SEL14,Port 14 alternate function selected"
|
|
hexmask.long.byte 0x8 20.--23. 1. "SEL13,Port 13 alternate function selected"
|
|
hexmask.long.byte 0x8 16.--19. 1. "SEL12,Port 12 alternate function selected"
|
|
hexmask.long.byte 0x8 12.--15. 1. "SEL11,Port 11 alternate function selected"
|
|
hexmask.long.byte 0x8 8.--11. 1. "SEL10,Port 10 alternate function selected"
|
|
hexmask.long.byte 0x8 4.--7. 1. "SEL9,Port 9 alternate function selected"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SEL8,Port 8 alternate function selected"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "BC,Bit clear register"
|
|
bitfld.long 0x0 15. "CR15,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 14. "CR14,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 13. "CR13,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 12. "CR12,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 11. "CR11,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 10. "CR10,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 9. "CR9,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 8. "CR8,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 7. "CR7,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 6. "CR6,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 5. "CR5,Port cleat bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CR4,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 3. "CR3,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 2. "CR2,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 1. "CR1,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 0. "CR0,Port cleat bit" "0,1"
|
|
line.long 0x4 "TG,Port bit toggle register"
|
|
bitfld.long 0x4 15. "TG15,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 14. "TG14,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 13. "TG13,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 12. "TG12,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 11. "TG11,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 10. "TG10,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 9. "TG9,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 8. "TG8,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 7. "TG7,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 6. "TG6,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 5. "TG5,Port toggle bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TG4,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 3. "TG3,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 2. "TG2,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 1. "TG1,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 0. "TG0,Port toggle bit" "0,1"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "IFL,Input filtering regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FLPRD1,Filter sampling period for GPIO8 to GPIO15:"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FLPRD0,Filter sampling period for GPIO1 to GPIO7:"
|
|
line.long 0x4 "IFTP,Input filtering type regist"
|
|
bitfld.long 0x4 30.--31. "IFTP15,Pin 15 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "IFTP14,Pin 14 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "IFTP13,Pin 13 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "IFTP12,Pin 12 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "IFTP11,Pin 11 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "IFTP10,Pin 10 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "IFTP9,Pin 9 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "IFTP8,Pin 8 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "IFTP7,Pin 7 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "IFTP6,Pin 6 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "IFTP5,Pin 5 input filtering type bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "IFTP4,Pin 4 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "IFTP3,Pin 3 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "IFTP2,Pin 2 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "IFTP1,Pin 1 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "IFTP0,Pin 0 input filtering type bits" "0,1,2,3"
|
|
tree.end
|
|
tree "GPIOC"
|
|
base ad:0x58020800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTL,GPIO port control register"
|
|
bitfld.long 0x0 30.--31. "CTL15,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "CTL14,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "CTL13,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "CTL12,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "CTL11,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "CTL10,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "CTL9,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "CTL8,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "CTL7,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CTL6,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "CTL5,Port x configuration bits (x =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CTL4,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "CTL3,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "CTL2,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "CTL1,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CTL0,Port x configuration bits (x =" "0,1,2,3"
|
|
line.long 0x4 "OMODE,GPIO port output mode register"
|
|
bitfld.long 0x4 15. "OM15,Port 15 output mode bit" "0,1"
|
|
bitfld.long 0x4 14. "OM14,Port 14 output mode bit" "0,1"
|
|
bitfld.long 0x4 13. "OM13,Port 13 output mode bit" "0,1"
|
|
bitfld.long 0x4 12. "OM12,Port 12 output mode bit" "0,1"
|
|
bitfld.long 0x4 11. "OM11,Port 11 output mode bit" "0,1"
|
|
bitfld.long 0x4 10. "OM10,Port 10 output mode bit" "0,1"
|
|
bitfld.long 0x4 9. "OM9,Port 9 output mode bit" "0,1"
|
|
bitfld.long 0x4 8. "OM8,Port 8 output mode bit" "0,1"
|
|
bitfld.long 0x4 7. "OM7,Port 7 output mode bit" "0,1"
|
|
bitfld.long 0x4 6. "OM6,Port 6 output mode bit" "0,1"
|
|
bitfld.long 0x4 5. "OM5,Port 5 output mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "OM4,Port 4 output mode bit" "0,1"
|
|
bitfld.long 0x4 3. "OM3,Port 3 output mode bit" "0,1"
|
|
bitfld.long 0x4 2. "OM2,Port 2 output mode bit" "0,1"
|
|
bitfld.long 0x4 1. "OM1,Port 1 output mode bit" "0,1"
|
|
bitfld.long 0x4 0. "OM0,Port 0 output mode bit" "0,1"
|
|
line.long 0x8 "OSPD,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPD15,Port 15 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPD14,Port 14 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPD13,Port 13 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPD12,Port 12 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPD11,Port 11 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPD10,Port 10 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPD9,Port 9 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPD8,Port 8 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPD7,Port 7 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPD6,Port 6 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "OSPD5,Port 5 output max speed bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "OSPD4,Port 4 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPD3,Port 3 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPD2,Port 2 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPD1,Port 1 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPD0,Port 0 output max speed bits" "0,1,2,3"
|
|
line.long 0xC "PUD,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUD15,Port 15 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUD14,Port 14 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUD13,Port 13 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUD12,Port 12 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUD11,Port 11 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUD10,Port 10 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUD9,Port 9 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUD8,Port 8 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUD7,Port 7 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUD6,Port 6 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUD5,Port 5 pull-up or pull-down bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "PUD4,Port 4 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUD3,Port 3 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUD2,Port 2 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUD1,Port 1 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUD0,Port 0 pull-up or pull-down bits" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "ISTAT,GPIO port input status register"
|
|
bitfld.long 0x0 15. "ISTAT15,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 14. "ISTAT14,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 13. "ISTAT13,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 12. "ISTAT12,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 11. "ISTAT11,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 10. "ISTAT10,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 9. "ISTAT9,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 8. "ISTAT8,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 7. "ISTAT7,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 6. "ISTAT6,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 5. "ISTAT5,Port input status (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ISTAT4,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 3. "ISTAT3,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 2. "ISTAT2,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 1. "ISTAT1,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 0. "ISTAT0,Port input status (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "OCTL,GPIO port output control register"
|
|
bitfld.long 0x0 15. "OCTL15,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 14. "OCTL14,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 13. "OCTL13,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 12. "OCTL12,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 11. "OCTL11,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 10. "OCTL10,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 9. "OCTL9,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 8. "OCTL8,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 7. "OCTL7,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 6. "OCTL6,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 5. "OCTL5,Port output control (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "OCTL4,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 3. "OCTL3,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 2. "OCTL2,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 1. "OCTL1,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 0. "OCTL0,Port output control (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BOP,GPIO port bit operate register"
|
|
bitfld.long 0x0 31. "CR15,Port Clear bit 15" "0,1"
|
|
bitfld.long 0x0 30. "CR14,Port Clear bit 14" "0,1"
|
|
bitfld.long 0x0 29. "CR13,Port Clear bit 13" "0,1"
|
|
bitfld.long 0x0 28. "CR12,Port Clear bit 12" "0,1"
|
|
bitfld.long 0x0 27. "CR11,Port Clear bit 11" "0,1"
|
|
bitfld.long 0x0 26. "CR10,Port Clear bit 10" "0,1"
|
|
bitfld.long 0x0 25. "CR9,Port Clear bit 9" "0,1"
|
|
bitfld.long 0x0 24. "CR8,Port Clear bit 8" "0,1"
|
|
bitfld.long 0x0 23. "CR7,Port Clear bit 7" "0,1"
|
|
bitfld.long 0x0 22. "CR6,Port Clear bit 6" "0,1"
|
|
bitfld.long 0x0 21. "CR5,Port Clear bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "CR4,Port Clear bit 4" "0,1"
|
|
bitfld.long 0x0 19. "CR3,Port Clear bit 3" "0,1"
|
|
bitfld.long 0x0 18. "CR2,Port Clear bit 2" "0,1"
|
|
bitfld.long 0x0 17. "CR1,Port Clear bit 1" "0,1"
|
|
bitfld.long 0x0 16. "CR0,Port Clear bit 0" "0,1"
|
|
bitfld.long 0x0 15. "BOP15,Port Set bit 15" "0,1"
|
|
bitfld.long 0x0 14. "BOP14,Port Set bit 14" "0,1"
|
|
bitfld.long 0x0 13. "BOP13,Port Set bit 13" "0,1"
|
|
bitfld.long 0x0 12. "BOP12,Port Set bit 12" "0,1"
|
|
bitfld.long 0x0 11. "BOP11,Port Set bit 11" "0,1"
|
|
bitfld.long 0x0 10. "BOP10,Port Set bit 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "BOP9,Port Set bit 9" "0,1"
|
|
bitfld.long 0x0 8. "BOP8,Port Set bit 8" "0,1"
|
|
bitfld.long 0x0 7. "BOP7,Port Set bit 7" "0,1"
|
|
bitfld.long 0x0 6. "BOP6,Port Set bit 6" "0,1"
|
|
bitfld.long 0x0 5. "BOP5,Port Set bit 5" "0,1"
|
|
bitfld.long 0x0 4. "BOP4,Port Set bit 4" "0,1"
|
|
bitfld.long 0x0 3. "BOP3,Port Set bit 3" "0,1"
|
|
bitfld.long 0x0 2. "BOP2,Port Set bit 2" "0,1"
|
|
bitfld.long 0x0 1. "BOP1,Port Set bit 1" "0,1"
|
|
bitfld.long 0x0 0. "BOP0,Port Set bit 0" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LOCK,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LKK,Lock sequence key" "0,1"
|
|
bitfld.long 0x0 15. "LK15,Port Lock bit 15" "0,1"
|
|
bitfld.long 0x0 14. "LK14,Port Lock bit 14" "0,1"
|
|
bitfld.long 0x0 13. "LK13,Port Lock bit 13" "0,1"
|
|
bitfld.long 0x0 12. "LK12,Port Lock bit 12" "0,1"
|
|
bitfld.long 0x0 11. "LK11,Port Lock bit 11" "0,1"
|
|
bitfld.long 0x0 10. "LK10,Port Lock bit 10" "0,1"
|
|
bitfld.long 0x0 9. "LK9,Port Lock bit 9" "0,1"
|
|
bitfld.long 0x0 8. "LK8,Port Lock bit 8" "0,1"
|
|
bitfld.long 0x0 7. "LK7,Port Lock bit 7" "0,1"
|
|
bitfld.long 0x0 6. "LK6,Port Lock bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LK5,Port Lock bit 5" "0,1"
|
|
bitfld.long 0x0 4. "LK4,Port Lock bit 4" "0,1"
|
|
bitfld.long 0x0 3. "LK3,Port Lock bit 3" "0,1"
|
|
bitfld.long 0x0 2. "LK2,Port Lock bit 2" "0,1"
|
|
bitfld.long 0x0 1. "LK1,Port Lock bit 1" "0,1"
|
|
bitfld.long 0x0 0. "LK0,Port Lock bit 0" "0,1"
|
|
line.long 0x4 "AFSEL0,GPIO alternate function selected register 0"
|
|
hexmask.long.byte 0x4 28.--31. 1. "SEL7,Port 7 alternate function selected"
|
|
hexmask.long.byte 0x4 24.--27. 1. "SEL6,Port 6 alternate function selected"
|
|
hexmask.long.byte 0x4 20.--23. 1. "SEL5,Port 5 alternate function selected"
|
|
hexmask.long.byte 0x4 16.--19. 1. "SEL4,Port 4 alternate function selected"
|
|
hexmask.long.byte 0x4 12.--15. 1. "SEL3,Port 3 alternate function selected"
|
|
hexmask.long.byte 0x4 8.--11. 1. "SEL2,Port 2 alternate function selected"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SEL1,Port 1 alternate function selected"
|
|
hexmask.long.byte 0x4 0.--3. 1. "SEL0,Port 0 alternate function selected"
|
|
line.long 0x8 "AFSEL1,GPIO alternate function selected register 1"
|
|
hexmask.long.byte 0x8 28.--31. 1. "SEL15,Port 15 alternate function selected"
|
|
hexmask.long.byte 0x8 24.--27. 1. "SEL14,Port 14 alternate function selected"
|
|
hexmask.long.byte 0x8 20.--23. 1. "SEL13,Port 13 alternate function selected"
|
|
hexmask.long.byte 0x8 16.--19. 1. "SEL12,Port 12 alternate function selected"
|
|
hexmask.long.byte 0x8 12.--15. 1. "SEL11,Port 11 alternate function selected"
|
|
hexmask.long.byte 0x8 8.--11. 1. "SEL10,Port 10 alternate function selected"
|
|
hexmask.long.byte 0x8 4.--7. 1. "SEL9,Port 9 alternate function selected"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SEL8,Port 8 alternate function selected"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "BC,Bit clear register"
|
|
bitfld.long 0x0 15. "CR15,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 14. "CR14,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 13. "CR13,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 12. "CR12,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 11. "CR11,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 10. "CR10,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 9. "CR9,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 8. "CR8,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 7. "CR7,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 6. "CR6,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 5. "CR5,Port cleat bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CR4,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 3. "CR3,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 2. "CR2,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 1. "CR1,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 0. "CR0,Port cleat bit" "0,1"
|
|
line.long 0x4 "TG,Port bit toggle register"
|
|
bitfld.long 0x4 15. "TG15,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 14. "TG14,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 13. "TG13,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 12. "TG12,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 11. "TG11,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 10. "TG10,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 9. "TG9,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 8. "TG8,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 7. "TG7,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 6. "TG6,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 5. "TG5,Port toggle bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TG4,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 3. "TG3,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 2. "TG2,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 1. "TG1,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 0. "TG0,Port toggle bit" "0,1"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "IFL,Input filtering regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FLPRD1,Filter sampling period for GPIO8 to GPIO15:"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FLPRD0,Filter sampling period for GPIO1 to GPIO7:"
|
|
line.long 0x4 "IFTP,Input filtering type regist"
|
|
bitfld.long 0x4 30.--31. "IFTP15,Pin 15 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "IFTP14,Pin 14 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "IFTP13,Pin 13 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "IFTP12,Pin 12 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "IFTP11,Pin 11 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "IFTP10,Pin 10 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "IFTP9,Pin 9 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "IFTP8,Pin 8 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "IFTP7,Pin 7 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "IFTP6,Pin 6 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "IFTP5,Pin 5 input filtering type bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "IFTP4,Pin 4 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "IFTP3,Pin 3 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "IFTP2,Pin 2 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "IFTP1,Pin 1 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "IFTP0,Pin 0 input filtering type bits" "0,1,2,3"
|
|
tree.end
|
|
tree "GPIOD"
|
|
base ad:0x58020C00
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTL,GPIO port control register"
|
|
bitfld.long 0x0 30.--31. "CTL15,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "CTL14,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "CTL13,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "CTL12,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "CTL11,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "CTL10,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "CTL9,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "CTL8,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "CTL7,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CTL6,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "CTL5,Port x configuration bits (x =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CTL4,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "CTL3,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "CTL2,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "CTL1,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CTL0,Port x configuration bits (x =" "0,1,2,3"
|
|
line.long 0x4 "OMODE,GPIO port output mode register"
|
|
bitfld.long 0x4 15. "OM15,Port 15 output mode bit" "0,1"
|
|
bitfld.long 0x4 14. "OM14,Port 14 output mode bit" "0,1"
|
|
bitfld.long 0x4 13. "OM13,Port 13 output mode bit" "0,1"
|
|
bitfld.long 0x4 12. "OM12,Port 12 output mode bit" "0,1"
|
|
bitfld.long 0x4 11. "OM11,Port 11 output mode bit" "0,1"
|
|
bitfld.long 0x4 10. "OM10,Port 10 output mode bit" "0,1"
|
|
bitfld.long 0x4 9. "OM9,Port 9 output mode bit" "0,1"
|
|
bitfld.long 0x4 8. "OM8,Port 8 output mode bit" "0,1"
|
|
bitfld.long 0x4 7. "OM7,Port 7 output mode bit" "0,1"
|
|
bitfld.long 0x4 6. "OM6,Port 6 output mode bit" "0,1"
|
|
bitfld.long 0x4 5. "OM5,Port 5 output mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "OM4,Port 4 output mode bit" "0,1"
|
|
bitfld.long 0x4 3. "OM3,Port 3 output mode bit" "0,1"
|
|
bitfld.long 0x4 2. "OM2,Port 2 output mode bit" "0,1"
|
|
bitfld.long 0x4 1. "OM1,Port 1 output mode bit" "0,1"
|
|
bitfld.long 0x4 0. "OM0,Port 0 output mode bit" "0,1"
|
|
line.long 0x8 "OSPD,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPD15,Port 15 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPD14,Port 14 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPD13,Port 13 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPD12,Port 12 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPD11,Port 11 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPD10,Port 10 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPD9,Port 9 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPD8,Port 8 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPD7,Port 7 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPD6,Port 6 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "OSPD5,Port 5 output max speed bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "OSPD4,Port 4 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPD3,Port 3 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPD2,Port 2 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPD1,Port 1 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPD0,Port 0 output max speed bits" "0,1,2,3"
|
|
line.long 0xC "PUD,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUD15,Port 15 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUD14,Port 14 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUD13,Port 13 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUD12,Port 12 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUD11,Port 11 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUD10,Port 10 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUD9,Port 9 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUD8,Port 8 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUD7,Port 7 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUD6,Port 6 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUD5,Port 5 pull-up or pull-down bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "PUD4,Port 4 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUD3,Port 3 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUD2,Port 2 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUD1,Port 1 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUD0,Port 0 pull-up or pull-down bits" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "ISTAT,GPIO port input status register"
|
|
bitfld.long 0x0 15. "ISTAT15,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 14. "ISTAT14,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 13. "ISTAT13,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 12. "ISTAT12,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 11. "ISTAT11,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 10. "ISTAT10,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 9. "ISTAT9,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 8. "ISTAT8,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 7. "ISTAT7,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 6. "ISTAT6,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 5. "ISTAT5,Port input status (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ISTAT4,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 3. "ISTAT3,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 2. "ISTAT2,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 1. "ISTAT1,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 0. "ISTAT0,Port input status (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "OCTL,GPIO port output control register"
|
|
bitfld.long 0x0 15. "OCTL15,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 14. "OCTL14,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 13. "OCTL13,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 12. "OCTL12,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 11. "OCTL11,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 10. "OCTL10,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 9. "OCTL9,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 8. "OCTL8,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 7. "OCTL7,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 6. "OCTL6,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 5. "OCTL5,Port output control (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "OCTL4,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 3. "OCTL3,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 2. "OCTL2,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 1. "OCTL1,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 0. "OCTL0,Port output control (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BOP,GPIO port bit operate register"
|
|
bitfld.long 0x0 31. "CR15,Port Clear bit 15" "0,1"
|
|
bitfld.long 0x0 30. "CR14,Port Clear bit 14" "0,1"
|
|
bitfld.long 0x0 29. "CR13,Port Clear bit 13" "0,1"
|
|
bitfld.long 0x0 28. "CR12,Port Clear bit 12" "0,1"
|
|
bitfld.long 0x0 27. "CR11,Port Clear bit 11" "0,1"
|
|
bitfld.long 0x0 26. "CR10,Port Clear bit 10" "0,1"
|
|
bitfld.long 0x0 25. "CR9,Port Clear bit 9" "0,1"
|
|
bitfld.long 0x0 24. "CR8,Port Clear bit 8" "0,1"
|
|
bitfld.long 0x0 23. "CR7,Port Clear bit 7" "0,1"
|
|
bitfld.long 0x0 22. "CR6,Port Clear bit 6" "0,1"
|
|
bitfld.long 0x0 21. "CR5,Port Clear bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "CR4,Port Clear bit 4" "0,1"
|
|
bitfld.long 0x0 19. "CR3,Port Clear bit 3" "0,1"
|
|
bitfld.long 0x0 18. "CR2,Port Clear bit 2" "0,1"
|
|
bitfld.long 0x0 17. "CR1,Port Clear bit 1" "0,1"
|
|
bitfld.long 0x0 16. "CR0,Port Clear bit 0" "0,1"
|
|
bitfld.long 0x0 15. "BOP15,Port Set bit 15" "0,1"
|
|
bitfld.long 0x0 14. "BOP14,Port Set bit 14" "0,1"
|
|
bitfld.long 0x0 13. "BOP13,Port Set bit 13" "0,1"
|
|
bitfld.long 0x0 12. "BOP12,Port Set bit 12" "0,1"
|
|
bitfld.long 0x0 11. "BOP11,Port Set bit 11" "0,1"
|
|
bitfld.long 0x0 10. "BOP10,Port Set bit 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "BOP9,Port Set bit 9" "0,1"
|
|
bitfld.long 0x0 8. "BOP8,Port Set bit 8" "0,1"
|
|
bitfld.long 0x0 7. "BOP7,Port Set bit 7" "0,1"
|
|
bitfld.long 0x0 6. "BOP6,Port Set bit 6" "0,1"
|
|
bitfld.long 0x0 5. "BOP5,Port Set bit 5" "0,1"
|
|
bitfld.long 0x0 4. "BOP4,Port Set bit 4" "0,1"
|
|
bitfld.long 0x0 3. "BOP3,Port Set bit 3" "0,1"
|
|
bitfld.long 0x0 2. "BOP2,Port Set bit 2" "0,1"
|
|
bitfld.long 0x0 1. "BOP1,Port Set bit 1" "0,1"
|
|
bitfld.long 0x0 0. "BOP0,Port Set bit 0" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LOCK,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LKK,Lock sequence key" "0,1"
|
|
bitfld.long 0x0 15. "LK15,Port Lock bit 15" "0,1"
|
|
bitfld.long 0x0 14. "LK14,Port Lock bit 14" "0,1"
|
|
bitfld.long 0x0 13. "LK13,Port Lock bit 13" "0,1"
|
|
bitfld.long 0x0 12. "LK12,Port Lock bit 12" "0,1"
|
|
bitfld.long 0x0 11. "LK11,Port Lock bit 11" "0,1"
|
|
bitfld.long 0x0 10. "LK10,Port Lock bit 10" "0,1"
|
|
bitfld.long 0x0 9. "LK9,Port Lock bit 9" "0,1"
|
|
bitfld.long 0x0 8. "LK8,Port Lock bit 8" "0,1"
|
|
bitfld.long 0x0 7. "LK7,Port Lock bit 7" "0,1"
|
|
bitfld.long 0x0 6. "LK6,Port Lock bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LK5,Port Lock bit 5" "0,1"
|
|
bitfld.long 0x0 4. "LK4,Port Lock bit 4" "0,1"
|
|
bitfld.long 0x0 3. "LK3,Port Lock bit 3" "0,1"
|
|
bitfld.long 0x0 2. "LK2,Port Lock bit 2" "0,1"
|
|
bitfld.long 0x0 1. "LK1,Port Lock bit 1" "0,1"
|
|
bitfld.long 0x0 0. "LK0,Port Lock bit 0" "0,1"
|
|
line.long 0x4 "AFSEL0,GPIO alternate function selected register 0"
|
|
hexmask.long.byte 0x4 28.--31. 1. "SEL7,Port 7 alternate function selected"
|
|
hexmask.long.byte 0x4 24.--27. 1. "SEL6,Port 6 alternate function selected"
|
|
hexmask.long.byte 0x4 20.--23. 1. "SEL5,Port 5 alternate function selected"
|
|
hexmask.long.byte 0x4 16.--19. 1. "SEL4,Port 4 alternate function selected"
|
|
hexmask.long.byte 0x4 12.--15. 1. "SEL3,Port 3 alternate function selected"
|
|
hexmask.long.byte 0x4 8.--11. 1. "SEL2,Port 2 alternate function selected"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SEL1,Port 1 alternate function selected"
|
|
hexmask.long.byte 0x4 0.--3. 1. "SEL0,Port 0 alternate function selected"
|
|
line.long 0x8 "AFSEL1,GPIO alternate function selected register 1"
|
|
hexmask.long.byte 0x8 28.--31. 1. "SEL15,Port 15 alternate function selected"
|
|
hexmask.long.byte 0x8 24.--27. 1. "SEL14,Port 14 alternate function selected"
|
|
hexmask.long.byte 0x8 20.--23. 1. "SEL13,Port 13 alternate function selected"
|
|
hexmask.long.byte 0x8 16.--19. 1. "SEL12,Port 12 alternate function selected"
|
|
hexmask.long.byte 0x8 12.--15. 1. "SEL11,Port 11 alternate function selected"
|
|
hexmask.long.byte 0x8 8.--11. 1. "SEL10,Port 10 alternate function selected"
|
|
hexmask.long.byte 0x8 4.--7. 1. "SEL9,Port 9 alternate function selected"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SEL8,Port 8 alternate function selected"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "BC,Bit clear register"
|
|
bitfld.long 0x0 15. "CR15,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 14. "CR14,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 13. "CR13,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 12. "CR12,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 11. "CR11,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 10. "CR10,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 9. "CR9,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 8. "CR8,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 7. "CR7,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 6. "CR6,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 5. "CR5,Port cleat bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CR4,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 3. "CR3,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 2. "CR2,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 1. "CR1,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 0. "CR0,Port cleat bit" "0,1"
|
|
line.long 0x4 "TG,Port bit toggle register"
|
|
bitfld.long 0x4 15. "TG15,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 14. "TG14,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 13. "TG13,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 12. "TG12,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 11. "TG11,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 10. "TG10,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 9. "TG9,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 8. "TG8,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 7. "TG7,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 6. "TG6,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 5. "TG5,Port toggle bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TG4,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 3. "TG3,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 2. "TG2,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 1. "TG1,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 0. "TG0,Port toggle bit" "0,1"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "IFL,Input filtering regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FLPRD1,Filter sampling period for GPIO8 to GPIO15:"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FLPRD0,Filter sampling period for GPIO1 to GPIO7:"
|
|
line.long 0x4 "IFTP,Input filtering type regist"
|
|
bitfld.long 0x4 30.--31. "IFTP15,Pin 15 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "IFTP14,Pin 14 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "IFTP13,Pin 13 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "IFTP12,Pin 12 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "IFTP11,Pin 11 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "IFTP10,Pin 10 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "IFTP9,Pin 9 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "IFTP8,Pin 8 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "IFTP7,Pin 7 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "IFTP6,Pin 6 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "IFTP5,Pin 5 input filtering type bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "IFTP4,Pin 4 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "IFTP3,Pin 3 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "IFTP2,Pin 2 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "IFTP1,Pin 1 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "IFTP0,Pin 0 input filtering type bits" "0,1,2,3"
|
|
tree.end
|
|
tree "GPIOE"
|
|
base ad:0x58021000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTL,GPIO port control register"
|
|
bitfld.long 0x0 30.--31. "CTL15,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "CTL14,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "CTL13,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "CTL12,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "CTL11,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "CTL10,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "CTL9,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "CTL8,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "CTL7,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CTL6,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "CTL5,Port x configuration bits (x =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CTL4,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "CTL3,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "CTL2,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "CTL1,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CTL0,Port x configuration bits (x =" "0,1,2,3"
|
|
line.long 0x4 "OMODE,GPIO port output mode register"
|
|
bitfld.long 0x4 15. "OM15,Port 15 output mode bit" "0,1"
|
|
bitfld.long 0x4 14. "OM14,Port 14 output mode bit" "0,1"
|
|
bitfld.long 0x4 13. "OM13,Port 13 output mode bit" "0,1"
|
|
bitfld.long 0x4 12. "OM12,Port 12 output mode bit" "0,1"
|
|
bitfld.long 0x4 11. "OM11,Port 11 output mode bit" "0,1"
|
|
bitfld.long 0x4 10. "OM10,Port 10 output mode bit" "0,1"
|
|
bitfld.long 0x4 9. "OM9,Port 9 output mode bit" "0,1"
|
|
bitfld.long 0x4 8. "OM8,Port 8 output mode bit" "0,1"
|
|
bitfld.long 0x4 7. "OM7,Port 7 output mode bit" "0,1"
|
|
bitfld.long 0x4 6. "OM6,Port 6 output mode bit" "0,1"
|
|
bitfld.long 0x4 5. "OM5,Port 5 output mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "OM4,Port 4 output mode bit" "0,1"
|
|
bitfld.long 0x4 3. "OM3,Port 3 output mode bit" "0,1"
|
|
bitfld.long 0x4 2. "OM2,Port 2 output mode bit" "0,1"
|
|
bitfld.long 0x4 1. "OM1,Port 1 output mode bit" "0,1"
|
|
bitfld.long 0x4 0. "OM0,Port 0 output mode bit" "0,1"
|
|
line.long 0x8 "OSPD,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPD15,Port 15 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPD14,Port 14 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPD13,Port 13 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPD12,Port 12 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPD11,Port 11 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPD10,Port 10 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPD9,Port 9 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPD8,Port 8 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPD7,Port 7 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPD6,Port 6 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "OSPD5,Port 5 output max speed bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "OSPD4,Port 4 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPD3,Port 3 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPD2,Port 2 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPD1,Port 1 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPD0,Port 0 output max speed bits" "0,1,2,3"
|
|
line.long 0xC "PUD,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUD15,Port 15 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUD14,Port 14 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUD13,Port 13 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUD12,Port 12 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUD11,Port 11 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUD10,Port 10 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUD9,Port 9 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUD8,Port 8 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUD7,Port 7 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUD6,Port 6 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUD5,Port 5 pull-up or pull-down bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "PUD4,Port 4 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUD3,Port 3 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUD2,Port 2 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUD1,Port 1 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUD0,Port 0 pull-up or pull-down bits" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "ISTAT,GPIO port input status register"
|
|
bitfld.long 0x0 15. "ISTAT15,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 14. "ISTAT14,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 13. "ISTAT13,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 12. "ISTAT12,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 11. "ISTAT11,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 10. "ISTAT10,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 9. "ISTAT9,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 8. "ISTAT8,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 7. "ISTAT7,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 6. "ISTAT6,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 5. "ISTAT5,Port input status (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ISTAT4,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 3. "ISTAT3,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 2. "ISTAT2,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 1. "ISTAT1,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 0. "ISTAT0,Port input status (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "OCTL,GPIO port output control register"
|
|
bitfld.long 0x0 15. "OCTL15,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 14. "OCTL14,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 13. "OCTL13,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 12. "OCTL12,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 11. "OCTL11,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 10. "OCTL10,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 9. "OCTL9,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 8. "OCTL8,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 7. "OCTL7,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 6. "OCTL6,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 5. "OCTL5,Port output control (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "OCTL4,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 3. "OCTL3,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 2. "OCTL2,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 1. "OCTL1,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 0. "OCTL0,Port output control (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BOP,GPIO port bit operate register"
|
|
bitfld.long 0x0 31. "CR15,Port Clear bit 15" "0,1"
|
|
bitfld.long 0x0 30. "CR14,Port Clear bit 14" "0,1"
|
|
bitfld.long 0x0 29. "CR13,Port Clear bit 13" "0,1"
|
|
bitfld.long 0x0 28. "CR12,Port Clear bit 12" "0,1"
|
|
bitfld.long 0x0 27. "CR11,Port Clear bit 11" "0,1"
|
|
bitfld.long 0x0 26. "CR10,Port Clear bit 10" "0,1"
|
|
bitfld.long 0x0 25. "CR9,Port Clear bit 9" "0,1"
|
|
bitfld.long 0x0 24. "CR8,Port Clear bit 8" "0,1"
|
|
bitfld.long 0x0 23. "CR7,Port Clear bit 7" "0,1"
|
|
bitfld.long 0x0 22. "CR6,Port Clear bit 6" "0,1"
|
|
bitfld.long 0x0 21. "CR5,Port Clear bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "CR4,Port Clear bit 4" "0,1"
|
|
bitfld.long 0x0 19. "CR3,Port Clear bit 3" "0,1"
|
|
bitfld.long 0x0 18. "CR2,Port Clear bit 2" "0,1"
|
|
bitfld.long 0x0 17. "CR1,Port Clear bit 1" "0,1"
|
|
bitfld.long 0x0 16. "CR0,Port Clear bit 0" "0,1"
|
|
bitfld.long 0x0 15. "BOP15,Port Set bit 15" "0,1"
|
|
bitfld.long 0x0 14. "BOP14,Port Set bit 14" "0,1"
|
|
bitfld.long 0x0 13. "BOP13,Port Set bit 13" "0,1"
|
|
bitfld.long 0x0 12. "BOP12,Port Set bit 12" "0,1"
|
|
bitfld.long 0x0 11. "BOP11,Port Set bit 11" "0,1"
|
|
bitfld.long 0x0 10. "BOP10,Port Set bit 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "BOP9,Port Set bit 9" "0,1"
|
|
bitfld.long 0x0 8. "BOP8,Port Set bit 8" "0,1"
|
|
bitfld.long 0x0 7. "BOP7,Port Set bit 7" "0,1"
|
|
bitfld.long 0x0 6. "BOP6,Port Set bit 6" "0,1"
|
|
bitfld.long 0x0 5. "BOP5,Port Set bit 5" "0,1"
|
|
bitfld.long 0x0 4. "BOP4,Port Set bit 4" "0,1"
|
|
bitfld.long 0x0 3. "BOP3,Port Set bit 3" "0,1"
|
|
bitfld.long 0x0 2. "BOP2,Port Set bit 2" "0,1"
|
|
bitfld.long 0x0 1. "BOP1,Port Set bit 1" "0,1"
|
|
bitfld.long 0x0 0. "BOP0,Port Set bit 0" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LOCK,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LKK,Lock sequence key" "0,1"
|
|
bitfld.long 0x0 15. "LK15,Port Lock bit 15" "0,1"
|
|
bitfld.long 0x0 14. "LK14,Port Lock bit 14" "0,1"
|
|
bitfld.long 0x0 13. "LK13,Port Lock bit 13" "0,1"
|
|
bitfld.long 0x0 12. "LK12,Port Lock bit 12" "0,1"
|
|
bitfld.long 0x0 11. "LK11,Port Lock bit 11" "0,1"
|
|
bitfld.long 0x0 10. "LK10,Port Lock bit 10" "0,1"
|
|
bitfld.long 0x0 9. "LK9,Port Lock bit 9" "0,1"
|
|
bitfld.long 0x0 8. "LK8,Port Lock bit 8" "0,1"
|
|
bitfld.long 0x0 7. "LK7,Port Lock bit 7" "0,1"
|
|
bitfld.long 0x0 6. "LK6,Port Lock bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LK5,Port Lock bit 5" "0,1"
|
|
bitfld.long 0x0 4. "LK4,Port Lock bit 4" "0,1"
|
|
bitfld.long 0x0 3. "LK3,Port Lock bit 3" "0,1"
|
|
bitfld.long 0x0 2. "LK2,Port Lock bit 2" "0,1"
|
|
bitfld.long 0x0 1. "LK1,Port Lock bit 1" "0,1"
|
|
bitfld.long 0x0 0. "LK0,Port Lock bit 0" "0,1"
|
|
line.long 0x4 "AFSEL0,GPIO alternate function selected register 0"
|
|
hexmask.long.byte 0x4 28.--31. 1. "SEL7,Port 7 alternate function selected"
|
|
hexmask.long.byte 0x4 24.--27. 1. "SEL6,Port 6 alternate function selected"
|
|
hexmask.long.byte 0x4 20.--23. 1. "SEL5,Port 5 alternate function selected"
|
|
hexmask.long.byte 0x4 16.--19. 1. "SEL4,Port 4 alternate function selected"
|
|
hexmask.long.byte 0x4 12.--15. 1. "SEL3,Port 3 alternate function selected"
|
|
hexmask.long.byte 0x4 8.--11. 1. "SEL2,Port 2 alternate function selected"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SEL1,Port 1 alternate function selected"
|
|
hexmask.long.byte 0x4 0.--3. 1. "SEL0,Port 0 alternate function selected"
|
|
line.long 0x8 "AFSEL1,GPIO alternate function selected register 1"
|
|
hexmask.long.byte 0x8 28.--31. 1. "SEL15,Port 15 alternate function selected"
|
|
hexmask.long.byte 0x8 24.--27. 1. "SEL14,Port 14 alternate function selected"
|
|
hexmask.long.byte 0x8 20.--23. 1. "SEL13,Port 13 alternate function selected"
|
|
hexmask.long.byte 0x8 16.--19. 1. "SEL12,Port 12 alternate function selected"
|
|
hexmask.long.byte 0x8 12.--15. 1. "SEL11,Port 11 alternate function selected"
|
|
hexmask.long.byte 0x8 8.--11. 1. "SEL10,Port 10 alternate function selected"
|
|
hexmask.long.byte 0x8 4.--7. 1. "SEL9,Port 9 alternate function selected"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SEL8,Port 8 alternate function selected"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "BC,Bit clear register"
|
|
bitfld.long 0x0 15. "CR15,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 14. "CR14,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 13. "CR13,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 12. "CR12,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 11. "CR11,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 10. "CR10,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 9. "CR9,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 8. "CR8,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 7. "CR7,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 6. "CR6,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 5. "CR5,Port cleat bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CR4,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 3. "CR3,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 2. "CR2,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 1. "CR1,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 0. "CR0,Port cleat bit" "0,1"
|
|
line.long 0x4 "TG,Port bit toggle register"
|
|
bitfld.long 0x4 15. "TG15,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 14. "TG14,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 13. "TG13,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 12. "TG12,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 11. "TG11,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 10. "TG10,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 9. "TG9,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 8. "TG8,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 7. "TG7,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 6. "TG6,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 5. "TG5,Port toggle bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TG4,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 3. "TG3,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 2. "TG2,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 1. "TG1,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 0. "TG0,Port toggle bit" "0,1"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "IFL,Input filtering regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FLPRD1,Filter sampling period for GPIO8 to GPIO15:"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FLPRD0,Filter sampling period for GPIO1 to GPIO7:"
|
|
line.long 0x4 "IFTP,Input filtering type regist"
|
|
bitfld.long 0x4 30.--31. "IFTP15,Pin 15 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "IFTP14,Pin 14 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "IFTP13,Pin 13 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "IFTP12,Pin 12 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "IFTP11,Pin 11 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "IFTP10,Pin 10 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "IFTP9,Pin 9 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "IFTP8,Pin 8 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "IFTP7,Pin 7 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "IFTP6,Pin 6 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "IFTP5,Pin 5 input filtering type bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "IFTP4,Pin 4 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "IFTP3,Pin 3 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "IFTP2,Pin 2 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "IFTP1,Pin 1 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "IFTP0,Pin 0 input filtering type bits" "0,1,2,3"
|
|
tree.end
|
|
tree "GPIOF"
|
|
base ad:0x58021400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTL,GPIO port control register"
|
|
bitfld.long 0x0 30.--31. "CTL15,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "CTL14,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "CTL13,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "CTL12,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "CTL11,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "CTL10,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "CTL9,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "CTL8,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "CTL7,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CTL6,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "CTL5,Port x configuration bits (x =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CTL4,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "CTL3,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "CTL2,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "CTL1,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CTL0,Port x configuration bits (x =" "0,1,2,3"
|
|
line.long 0x4 "OMODE,GPIO port output mode register"
|
|
bitfld.long 0x4 15. "OM15,Port 15 output mode bit" "0,1"
|
|
bitfld.long 0x4 14. "OM14,Port 14 output mode bit" "0,1"
|
|
bitfld.long 0x4 13. "OM13,Port 13 output mode bit" "0,1"
|
|
bitfld.long 0x4 12. "OM12,Port 12 output mode bit" "0,1"
|
|
bitfld.long 0x4 11. "OM11,Port 11 output mode bit" "0,1"
|
|
bitfld.long 0x4 10. "OM10,Port 10 output mode bit" "0,1"
|
|
bitfld.long 0x4 9. "OM9,Port 9 output mode bit" "0,1"
|
|
bitfld.long 0x4 8. "OM8,Port 8 output mode bit" "0,1"
|
|
bitfld.long 0x4 7. "OM7,Port 7 output mode bit" "0,1"
|
|
bitfld.long 0x4 6. "OM6,Port 6 output mode bit" "0,1"
|
|
bitfld.long 0x4 5. "OM5,Port 5 output mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "OM4,Port 4 output mode bit" "0,1"
|
|
bitfld.long 0x4 3. "OM3,Port 3 output mode bit" "0,1"
|
|
bitfld.long 0x4 2. "OM2,Port 2 output mode bit" "0,1"
|
|
bitfld.long 0x4 1. "OM1,Port 1 output mode bit" "0,1"
|
|
bitfld.long 0x4 0. "OM0,Port 0 output mode bit" "0,1"
|
|
line.long 0x8 "OSPD,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPD15,Port 15 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPD14,Port 14 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPD13,Port 13 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPD12,Port 12 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPD11,Port 11 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPD10,Port 10 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPD9,Port 9 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPD8,Port 8 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPD7,Port 7 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPD6,Port 6 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "OSPD5,Port 5 output max speed bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "OSPD4,Port 4 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPD3,Port 3 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPD2,Port 2 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPD1,Port 1 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPD0,Port 0 output max speed bits" "0,1,2,3"
|
|
line.long 0xC "PUD,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUD15,Port 15 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUD14,Port 14 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUD13,Port 13 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUD12,Port 12 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUD11,Port 11 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUD10,Port 10 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUD9,Port 9 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUD8,Port 8 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUD7,Port 7 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUD6,Port 6 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUD5,Port 5 pull-up or pull-down bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "PUD4,Port 4 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUD3,Port 3 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUD2,Port 2 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUD1,Port 1 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUD0,Port 0 pull-up or pull-down bits" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "ISTAT,GPIO port input status register"
|
|
bitfld.long 0x0 15. "ISTAT15,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 14. "ISTAT14,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 13. "ISTAT13,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 12. "ISTAT12,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 11. "ISTAT11,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 10. "ISTAT10,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 9. "ISTAT9,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 8. "ISTAT8,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 7. "ISTAT7,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 6. "ISTAT6,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 5. "ISTAT5,Port input status (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ISTAT4,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 3. "ISTAT3,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 2. "ISTAT2,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 1. "ISTAT1,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 0. "ISTAT0,Port input status (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "OCTL,GPIO port output control register"
|
|
bitfld.long 0x0 15. "OCTL15,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 14. "OCTL14,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 13. "OCTL13,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 12. "OCTL12,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 11. "OCTL11,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 10. "OCTL10,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 9. "OCTL9,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 8. "OCTL8,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 7. "OCTL7,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 6. "OCTL6,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 5. "OCTL5,Port output control (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "OCTL4,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 3. "OCTL3,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 2. "OCTL2,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 1. "OCTL1,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 0. "OCTL0,Port output control (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BOP,GPIO port bit operate register"
|
|
bitfld.long 0x0 31. "CR15,Port Clear bit 15" "0,1"
|
|
bitfld.long 0x0 30. "CR14,Port Clear bit 14" "0,1"
|
|
bitfld.long 0x0 29. "CR13,Port Clear bit 13" "0,1"
|
|
bitfld.long 0x0 28. "CR12,Port Clear bit 12" "0,1"
|
|
bitfld.long 0x0 27. "CR11,Port Clear bit 11" "0,1"
|
|
bitfld.long 0x0 26. "CR10,Port Clear bit 10" "0,1"
|
|
bitfld.long 0x0 25. "CR9,Port Clear bit 9" "0,1"
|
|
bitfld.long 0x0 24. "CR8,Port Clear bit 8" "0,1"
|
|
bitfld.long 0x0 23. "CR7,Port Clear bit 7" "0,1"
|
|
bitfld.long 0x0 22. "CR6,Port Clear bit 6" "0,1"
|
|
bitfld.long 0x0 21. "CR5,Port Clear bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "CR4,Port Clear bit 4" "0,1"
|
|
bitfld.long 0x0 19. "CR3,Port Clear bit 3" "0,1"
|
|
bitfld.long 0x0 18. "CR2,Port Clear bit 2" "0,1"
|
|
bitfld.long 0x0 17. "CR1,Port Clear bit 1" "0,1"
|
|
bitfld.long 0x0 16. "CR0,Port Clear bit 0" "0,1"
|
|
bitfld.long 0x0 15. "BOP15,Port Set bit 15" "0,1"
|
|
bitfld.long 0x0 14. "BOP14,Port Set bit 14" "0,1"
|
|
bitfld.long 0x0 13. "BOP13,Port Set bit 13" "0,1"
|
|
bitfld.long 0x0 12. "BOP12,Port Set bit 12" "0,1"
|
|
bitfld.long 0x0 11. "BOP11,Port Set bit 11" "0,1"
|
|
bitfld.long 0x0 10. "BOP10,Port Set bit 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "BOP9,Port Set bit 9" "0,1"
|
|
bitfld.long 0x0 8. "BOP8,Port Set bit 8" "0,1"
|
|
bitfld.long 0x0 7. "BOP7,Port Set bit 7" "0,1"
|
|
bitfld.long 0x0 6. "BOP6,Port Set bit 6" "0,1"
|
|
bitfld.long 0x0 5. "BOP5,Port Set bit 5" "0,1"
|
|
bitfld.long 0x0 4. "BOP4,Port Set bit 4" "0,1"
|
|
bitfld.long 0x0 3. "BOP3,Port Set bit 3" "0,1"
|
|
bitfld.long 0x0 2. "BOP2,Port Set bit 2" "0,1"
|
|
bitfld.long 0x0 1. "BOP1,Port Set bit 1" "0,1"
|
|
bitfld.long 0x0 0. "BOP0,Port Set bit 0" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LOCK,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LKK,Lock sequence key" "0,1"
|
|
bitfld.long 0x0 15. "LK15,Port Lock bit 15" "0,1"
|
|
bitfld.long 0x0 14. "LK14,Port Lock bit 14" "0,1"
|
|
bitfld.long 0x0 13. "LK13,Port Lock bit 13" "0,1"
|
|
bitfld.long 0x0 12. "LK12,Port Lock bit 12" "0,1"
|
|
bitfld.long 0x0 11. "LK11,Port Lock bit 11" "0,1"
|
|
bitfld.long 0x0 10. "LK10,Port Lock bit 10" "0,1"
|
|
bitfld.long 0x0 9. "LK9,Port Lock bit 9" "0,1"
|
|
bitfld.long 0x0 8. "LK8,Port Lock bit 8" "0,1"
|
|
bitfld.long 0x0 7. "LK7,Port Lock bit 7" "0,1"
|
|
bitfld.long 0x0 6. "LK6,Port Lock bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LK5,Port Lock bit 5" "0,1"
|
|
bitfld.long 0x0 4. "LK4,Port Lock bit 4" "0,1"
|
|
bitfld.long 0x0 3. "LK3,Port Lock bit 3" "0,1"
|
|
bitfld.long 0x0 2. "LK2,Port Lock bit 2" "0,1"
|
|
bitfld.long 0x0 1. "LK1,Port Lock bit 1" "0,1"
|
|
bitfld.long 0x0 0. "LK0,Port Lock bit 0" "0,1"
|
|
line.long 0x4 "AFSEL0,GPIO alternate function selected register 0"
|
|
hexmask.long.byte 0x4 28.--31. 1. "SEL7,Port 7 alternate function selected"
|
|
hexmask.long.byte 0x4 24.--27. 1. "SEL6,Port 6 alternate function selected"
|
|
hexmask.long.byte 0x4 20.--23. 1. "SEL5,Port 5 alternate function selected"
|
|
hexmask.long.byte 0x4 16.--19. 1. "SEL4,Port 4 alternate function selected"
|
|
hexmask.long.byte 0x4 12.--15. 1. "SEL3,Port 3 alternate function selected"
|
|
hexmask.long.byte 0x4 8.--11. 1. "SEL2,Port 2 alternate function selected"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SEL1,Port 1 alternate function selected"
|
|
hexmask.long.byte 0x4 0.--3. 1. "SEL0,Port 0 alternate function selected"
|
|
line.long 0x8 "AFSEL1,GPIO alternate function selected register 1"
|
|
hexmask.long.byte 0x8 28.--31. 1. "SEL15,Port 15 alternate function selected"
|
|
hexmask.long.byte 0x8 24.--27. 1. "SEL14,Port 14 alternate function selected"
|
|
hexmask.long.byte 0x8 20.--23. 1. "SEL13,Port 13 alternate function selected"
|
|
hexmask.long.byte 0x8 16.--19. 1. "SEL12,Port 12 alternate function selected"
|
|
hexmask.long.byte 0x8 12.--15. 1. "SEL11,Port 11 alternate function selected"
|
|
hexmask.long.byte 0x8 8.--11. 1. "SEL10,Port 10 alternate function selected"
|
|
hexmask.long.byte 0x8 4.--7. 1. "SEL9,Port 9 alternate function selected"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SEL8,Port 8 alternate function selected"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "BC,Bit clear register"
|
|
bitfld.long 0x0 15. "CR15,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 14. "CR14,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 13. "CR13,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 12. "CR12,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 11. "CR11,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 10. "CR10,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 9. "CR9,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 8. "CR8,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 7. "CR7,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 6. "CR6,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 5. "CR5,Port cleat bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CR4,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 3. "CR3,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 2. "CR2,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 1. "CR1,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 0. "CR0,Port cleat bit" "0,1"
|
|
line.long 0x4 "TG,Port bit toggle register"
|
|
bitfld.long 0x4 15. "TG15,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 14. "TG14,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 13. "TG13,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 12. "TG12,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 11. "TG11,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 10. "TG10,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 9. "TG9,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 8. "TG8,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 7. "TG7,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 6. "TG6,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 5. "TG5,Port toggle bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TG4,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 3. "TG3,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 2. "TG2,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 1. "TG1,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 0. "TG0,Port toggle bit" "0,1"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "IFL,Input filtering regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FLPRD1,Filter sampling period for GPIO8 to GPIO15:"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FLPRD0,Filter sampling period for GPIO1 to GPIO7:"
|
|
line.long 0x4 "IFTP,Input filtering type regist"
|
|
bitfld.long 0x4 30.--31. "IFTP15,Pin 15 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "IFTP14,Pin 14 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "IFTP13,Pin 13 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "IFTP12,Pin 12 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "IFTP11,Pin 11 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "IFTP10,Pin 10 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "IFTP9,Pin 9 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "IFTP8,Pin 8 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "IFTP7,Pin 7 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "IFTP6,Pin 6 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "IFTP5,Pin 5 input filtering type bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "IFTP4,Pin 4 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "IFTP3,Pin 3 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "IFTP2,Pin 2 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "IFTP1,Pin 1 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "IFTP0,Pin 0 input filtering type bits" "0,1,2,3"
|
|
tree.end
|
|
tree "GPIOG"
|
|
base ad:0x58021800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTL,GPIO port control register"
|
|
bitfld.long 0x0 30.--31. "CTL15,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "CTL14,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "CTL13,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "CTL12,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "CTL11,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "CTL10,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "CTL9,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "CTL8,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "CTL7,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CTL6,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "CTL5,Port x configuration bits (x =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CTL4,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "CTL3,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "CTL2,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "CTL1,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CTL0,Port x configuration bits (x =" "0,1,2,3"
|
|
line.long 0x4 "OMODE,GPIO port output mode register"
|
|
bitfld.long 0x4 15. "OM15,Port 15 output mode bit" "0,1"
|
|
bitfld.long 0x4 14. "OM14,Port 14 output mode bit" "0,1"
|
|
bitfld.long 0x4 13. "OM13,Port 13 output mode bit" "0,1"
|
|
bitfld.long 0x4 12. "OM12,Port 12 output mode bit" "0,1"
|
|
bitfld.long 0x4 11. "OM11,Port 11 output mode bit" "0,1"
|
|
bitfld.long 0x4 10. "OM10,Port 10 output mode bit" "0,1"
|
|
bitfld.long 0x4 9. "OM9,Port 9 output mode bit" "0,1"
|
|
bitfld.long 0x4 8. "OM8,Port 8 output mode bit" "0,1"
|
|
bitfld.long 0x4 7. "OM7,Port 7 output mode bit" "0,1"
|
|
bitfld.long 0x4 6. "OM6,Port 6 output mode bit" "0,1"
|
|
bitfld.long 0x4 5. "OM5,Port 5 output mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "OM4,Port 4 output mode bit" "0,1"
|
|
bitfld.long 0x4 3. "OM3,Port 3 output mode bit" "0,1"
|
|
bitfld.long 0x4 2. "OM2,Port 2 output mode bit" "0,1"
|
|
bitfld.long 0x4 1. "OM1,Port 1 output mode bit" "0,1"
|
|
bitfld.long 0x4 0. "OM0,Port 0 output mode bit" "0,1"
|
|
line.long 0x8 "OSPD,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPD15,Port 15 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPD14,Port 14 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPD13,Port 13 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPD12,Port 12 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPD11,Port 11 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPD10,Port 10 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPD9,Port 9 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPD8,Port 8 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPD7,Port 7 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPD6,Port 6 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "OSPD5,Port 5 output max speed bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "OSPD4,Port 4 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPD3,Port 3 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPD2,Port 2 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPD1,Port 1 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPD0,Port 0 output max speed bits" "0,1,2,3"
|
|
line.long 0xC "PUD,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUD15,Port 15 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUD14,Port 14 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUD13,Port 13 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUD12,Port 12 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUD11,Port 11 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUD10,Port 10 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUD9,Port 9 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUD8,Port 8 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUD7,Port 7 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUD6,Port 6 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUD5,Port 5 pull-up or pull-down bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "PUD4,Port 4 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUD3,Port 3 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUD2,Port 2 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUD1,Port 1 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUD0,Port 0 pull-up or pull-down bits" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "ISTAT,GPIO port input status register"
|
|
bitfld.long 0x0 15. "ISTAT15,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 14. "ISTAT14,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 13. "ISTAT13,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 12. "ISTAT12,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 11. "ISTAT11,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 10. "ISTAT10,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 9. "ISTAT9,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 8. "ISTAT8,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 7. "ISTAT7,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 6. "ISTAT6,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 5. "ISTAT5,Port input status (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ISTAT4,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 3. "ISTAT3,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 2. "ISTAT2,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 1. "ISTAT1,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 0. "ISTAT0,Port input status (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "OCTL,GPIO port output control register"
|
|
bitfld.long 0x0 15. "OCTL15,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 14. "OCTL14,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 13. "OCTL13,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 12. "OCTL12,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 11. "OCTL11,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 10. "OCTL10,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 9. "OCTL9,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 8. "OCTL8,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 7. "OCTL7,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 6. "OCTL6,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 5. "OCTL5,Port output control (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "OCTL4,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 3. "OCTL3,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 2. "OCTL2,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 1. "OCTL1,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 0. "OCTL0,Port output control (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BOP,GPIO port bit operate register"
|
|
bitfld.long 0x0 31. "CR15,Port Clear bit 15" "0,1"
|
|
bitfld.long 0x0 30. "CR14,Port Clear bit 14" "0,1"
|
|
bitfld.long 0x0 29. "CR13,Port Clear bit 13" "0,1"
|
|
bitfld.long 0x0 28. "CR12,Port Clear bit 12" "0,1"
|
|
bitfld.long 0x0 27. "CR11,Port Clear bit 11" "0,1"
|
|
bitfld.long 0x0 26. "CR10,Port Clear bit 10" "0,1"
|
|
bitfld.long 0x0 25. "CR9,Port Clear bit 9" "0,1"
|
|
bitfld.long 0x0 24. "CR8,Port Clear bit 8" "0,1"
|
|
bitfld.long 0x0 23. "CR7,Port Clear bit 7" "0,1"
|
|
bitfld.long 0x0 22. "CR6,Port Clear bit 6" "0,1"
|
|
bitfld.long 0x0 21. "CR5,Port Clear bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "CR4,Port Clear bit 4" "0,1"
|
|
bitfld.long 0x0 19. "CR3,Port Clear bit 3" "0,1"
|
|
bitfld.long 0x0 18. "CR2,Port Clear bit 2" "0,1"
|
|
bitfld.long 0x0 17. "CR1,Port Clear bit 1" "0,1"
|
|
bitfld.long 0x0 16. "CR0,Port Clear bit 0" "0,1"
|
|
bitfld.long 0x0 15. "BOP15,Port Set bit 15" "0,1"
|
|
bitfld.long 0x0 14. "BOP14,Port Set bit 14" "0,1"
|
|
bitfld.long 0x0 13. "BOP13,Port Set bit 13" "0,1"
|
|
bitfld.long 0x0 12. "BOP12,Port Set bit 12" "0,1"
|
|
bitfld.long 0x0 11. "BOP11,Port Set bit 11" "0,1"
|
|
bitfld.long 0x0 10. "BOP10,Port Set bit 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "BOP9,Port Set bit 9" "0,1"
|
|
bitfld.long 0x0 8. "BOP8,Port Set bit 8" "0,1"
|
|
bitfld.long 0x0 7. "BOP7,Port Set bit 7" "0,1"
|
|
bitfld.long 0x0 6. "BOP6,Port Set bit 6" "0,1"
|
|
bitfld.long 0x0 5. "BOP5,Port Set bit 5" "0,1"
|
|
bitfld.long 0x0 4. "BOP4,Port Set bit 4" "0,1"
|
|
bitfld.long 0x0 3. "BOP3,Port Set bit 3" "0,1"
|
|
bitfld.long 0x0 2. "BOP2,Port Set bit 2" "0,1"
|
|
bitfld.long 0x0 1. "BOP1,Port Set bit 1" "0,1"
|
|
bitfld.long 0x0 0. "BOP0,Port Set bit 0" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LOCK,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LKK,Lock sequence key" "0,1"
|
|
bitfld.long 0x0 15. "LK15,Port Lock bit 15" "0,1"
|
|
bitfld.long 0x0 14. "LK14,Port Lock bit 14" "0,1"
|
|
bitfld.long 0x0 13. "LK13,Port Lock bit 13" "0,1"
|
|
bitfld.long 0x0 12. "LK12,Port Lock bit 12" "0,1"
|
|
bitfld.long 0x0 11. "LK11,Port Lock bit 11" "0,1"
|
|
bitfld.long 0x0 10. "LK10,Port Lock bit 10" "0,1"
|
|
bitfld.long 0x0 9. "LK9,Port Lock bit 9" "0,1"
|
|
bitfld.long 0x0 8. "LK8,Port Lock bit 8" "0,1"
|
|
bitfld.long 0x0 7. "LK7,Port Lock bit 7" "0,1"
|
|
bitfld.long 0x0 6. "LK6,Port Lock bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LK5,Port Lock bit 5" "0,1"
|
|
bitfld.long 0x0 4. "LK4,Port Lock bit 4" "0,1"
|
|
bitfld.long 0x0 3. "LK3,Port Lock bit 3" "0,1"
|
|
bitfld.long 0x0 2. "LK2,Port Lock bit 2" "0,1"
|
|
bitfld.long 0x0 1. "LK1,Port Lock bit 1" "0,1"
|
|
bitfld.long 0x0 0. "LK0,Port Lock bit 0" "0,1"
|
|
line.long 0x4 "AFSEL0,GPIO alternate function selected register 0"
|
|
hexmask.long.byte 0x4 28.--31. 1. "SEL7,Port 7 alternate function selected"
|
|
hexmask.long.byte 0x4 24.--27. 1. "SEL6,Port 6 alternate function selected"
|
|
hexmask.long.byte 0x4 20.--23. 1. "SEL5,Port 5 alternate function selected"
|
|
hexmask.long.byte 0x4 16.--19. 1. "SEL4,Port 4 alternate function selected"
|
|
hexmask.long.byte 0x4 12.--15. 1. "SEL3,Port 3 alternate function selected"
|
|
hexmask.long.byte 0x4 8.--11. 1. "SEL2,Port 2 alternate function selected"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SEL1,Port 1 alternate function selected"
|
|
hexmask.long.byte 0x4 0.--3. 1. "SEL0,Port 0 alternate function selected"
|
|
line.long 0x8 "AFSEL1,GPIO alternate function selected register 1"
|
|
hexmask.long.byte 0x8 28.--31. 1. "SEL15,Port 15 alternate function selected"
|
|
hexmask.long.byte 0x8 24.--27. 1. "SEL14,Port 14 alternate function selected"
|
|
hexmask.long.byte 0x8 20.--23. 1. "SEL13,Port 13 alternate function selected"
|
|
hexmask.long.byte 0x8 16.--19. 1. "SEL12,Port 12 alternate function selected"
|
|
hexmask.long.byte 0x8 12.--15. 1. "SEL11,Port 11 alternate function selected"
|
|
hexmask.long.byte 0x8 8.--11. 1. "SEL10,Port 10 alternate function selected"
|
|
hexmask.long.byte 0x8 4.--7. 1. "SEL9,Port 9 alternate function selected"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SEL8,Port 8 alternate function selected"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "BC,Bit clear register"
|
|
bitfld.long 0x0 15. "CR15,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 14. "CR14,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 13. "CR13,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 12. "CR12,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 11. "CR11,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 10. "CR10,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 9. "CR9,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 8. "CR8,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 7. "CR7,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 6. "CR6,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 5. "CR5,Port cleat bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CR4,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 3. "CR3,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 2. "CR2,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 1. "CR1,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 0. "CR0,Port cleat bit" "0,1"
|
|
line.long 0x4 "TG,Port bit toggle register"
|
|
bitfld.long 0x4 15. "TG15,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 14. "TG14,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 13. "TG13,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 12. "TG12,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 11. "TG11,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 10. "TG10,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 9. "TG9,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 8. "TG8,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 7. "TG7,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 6. "TG6,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 5. "TG5,Port toggle bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TG4,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 3. "TG3,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 2. "TG2,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 1. "TG1,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 0. "TG0,Port toggle bit" "0,1"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "IFL,Input filtering regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FLPRD1,Filter sampling period for GPIO8 to GPIO15:"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FLPRD0,Filter sampling period for GPIO1 to GPIO7:"
|
|
line.long 0x4 "IFTP,Input filtering type regist"
|
|
bitfld.long 0x4 30.--31. "IFTP15,Pin 15 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "IFTP14,Pin 14 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "IFTP13,Pin 13 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "IFTP12,Pin 12 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "IFTP11,Pin 11 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "IFTP10,Pin 10 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "IFTP9,Pin 9 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "IFTP8,Pin 8 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "IFTP7,Pin 7 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "IFTP6,Pin 6 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "IFTP5,Pin 5 input filtering type bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "IFTP4,Pin 4 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "IFTP3,Pin 3 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "IFTP2,Pin 2 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "IFTP1,Pin 1 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "IFTP0,Pin 0 input filtering type bits" "0,1,2,3"
|
|
tree.end
|
|
tree "GPIOH"
|
|
base ad:0x58021C00
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTL,GPIO port control register"
|
|
bitfld.long 0x0 30.--31. "CTL15,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "CTL14,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "CTL13,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "CTL12,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "CTL11,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "CTL10,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "CTL9,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "CTL8,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "CTL7,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CTL6,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "CTL5,Port x configuration bits (x =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CTL4,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "CTL3,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "CTL2,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "CTL1,Port x configuration bits (x =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CTL0,Port x configuration bits (x =" "0,1,2,3"
|
|
line.long 0x4 "OMODE,GPIO port output mode register"
|
|
bitfld.long 0x4 15. "OM15,Port 15 output mode bit" "0,1"
|
|
bitfld.long 0x4 14. "OM14,Port 14 output mode bit" "0,1"
|
|
bitfld.long 0x4 13. "OM13,Port 13 output mode bit" "0,1"
|
|
bitfld.long 0x4 12. "OM12,Port 12 output mode bit" "0,1"
|
|
bitfld.long 0x4 11. "OM11,Port 11 output mode bit" "0,1"
|
|
bitfld.long 0x4 10. "OM10,Port 10 output mode bit" "0,1"
|
|
bitfld.long 0x4 9. "OM9,Port 9 output mode bit" "0,1"
|
|
bitfld.long 0x4 8. "OM8,Port 8 output mode bit" "0,1"
|
|
bitfld.long 0x4 7. "OM7,Port 7 output mode bit" "0,1"
|
|
bitfld.long 0x4 6. "OM6,Port 6 output mode bit" "0,1"
|
|
bitfld.long 0x4 5. "OM5,Port 5 output mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "OM4,Port 4 output mode bit" "0,1"
|
|
bitfld.long 0x4 3. "OM3,Port 3 output mode bit" "0,1"
|
|
bitfld.long 0x4 2. "OM2,Port 2 output mode bit" "0,1"
|
|
bitfld.long 0x4 1. "OM1,Port 1 output mode bit" "0,1"
|
|
bitfld.long 0x4 0. "OM0,Port 0 output mode bit" "0,1"
|
|
line.long 0x8 "OSPD,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPD15,Port 15 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPD14,Port 14 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPD13,Port 13 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPD12,Port 12 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPD11,Port 11 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPD10,Port 10 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPD9,Port 9 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPD8,Port 8 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPD7,Port 7 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPD6,Port 6 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "OSPD5,Port 5 output max speed bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "OSPD4,Port 4 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPD3,Port 3 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPD2,Port 2 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPD1,Port 1 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPD0,Port 0 output max speed bits" "0,1,2,3"
|
|
line.long 0xC "PUD,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUD15,Port 15 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUD14,Port 14 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUD13,Port 13 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUD12,Port 12 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUD11,Port 11 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUD10,Port 10 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUD9,Port 9 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUD8,Port 8 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUD7,Port 7 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUD6,Port 6 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUD5,Port 5 pull-up or pull-down bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "PUD4,Port 4 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUD3,Port 3 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUD2,Port 2 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUD1,Port 1 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUD0,Port 0 pull-up or pull-down bits" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "ISTAT,GPIO port input status register"
|
|
bitfld.long 0x0 15. "ISTAT15,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 14. "ISTAT14,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 13. "ISTAT13,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 12. "ISTAT12,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 11. "ISTAT11,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 10. "ISTAT10,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 9. "ISTAT9,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 8. "ISTAT8,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 7. "ISTAT7,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 6. "ISTAT6,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 5. "ISTAT5,Port input status (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ISTAT4,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 3. "ISTAT3,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 2. "ISTAT2,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 1. "ISTAT1,Port input status (y =" "0,1"
|
|
bitfld.long 0x0 0. "ISTAT0,Port input status (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "OCTL,GPIO port output control register"
|
|
bitfld.long 0x0 15. "OCTL15,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 14. "OCTL14,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 13. "OCTL13,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 12. "OCTL12,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 11. "OCTL11,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 10. "OCTL10,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 9. "OCTL9,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 8. "OCTL8,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 7. "OCTL7,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 6. "OCTL6,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 5. "OCTL5,Port output control (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "OCTL4,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 3. "OCTL3,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 2. "OCTL2,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 1. "OCTL1,Port output control (y =" "0,1"
|
|
bitfld.long 0x0 0. "OCTL0,Port output control (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BOP,GPIO port bit operate register"
|
|
bitfld.long 0x0 31. "CR15,Port Clear bit 15" "0,1"
|
|
bitfld.long 0x0 30. "CR14,Port Clear bit 14" "0,1"
|
|
bitfld.long 0x0 29. "CR13,Port Clear bit 13" "0,1"
|
|
bitfld.long 0x0 28. "CR12,Port Clear bit 12" "0,1"
|
|
bitfld.long 0x0 27. "CR11,Port Clear bit 11" "0,1"
|
|
bitfld.long 0x0 26. "CR10,Port Clear bit 10" "0,1"
|
|
bitfld.long 0x0 25. "CR9,Port Clear bit 9" "0,1"
|
|
bitfld.long 0x0 24. "CR8,Port Clear bit 8" "0,1"
|
|
bitfld.long 0x0 23. "CR7,Port Clear bit 7" "0,1"
|
|
bitfld.long 0x0 22. "CR6,Port Clear bit 6" "0,1"
|
|
bitfld.long 0x0 21. "CR5,Port Clear bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "CR4,Port Clear bit 4" "0,1"
|
|
bitfld.long 0x0 19. "CR3,Port Clear bit 3" "0,1"
|
|
bitfld.long 0x0 18. "CR2,Port Clear bit 2" "0,1"
|
|
bitfld.long 0x0 17. "CR1,Port Clear bit 1" "0,1"
|
|
bitfld.long 0x0 16. "CR0,Port Clear bit 0" "0,1"
|
|
bitfld.long 0x0 15. "BOP15,Port Set bit 15" "0,1"
|
|
bitfld.long 0x0 14. "BOP14,Port Set bit 14" "0,1"
|
|
bitfld.long 0x0 13. "BOP13,Port Set bit 13" "0,1"
|
|
bitfld.long 0x0 12. "BOP12,Port Set bit 12" "0,1"
|
|
bitfld.long 0x0 11. "BOP11,Port Set bit 11" "0,1"
|
|
bitfld.long 0x0 10. "BOP10,Port Set bit 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "BOP9,Port Set bit 9" "0,1"
|
|
bitfld.long 0x0 8. "BOP8,Port Set bit 8" "0,1"
|
|
bitfld.long 0x0 7. "BOP7,Port Set bit 7" "0,1"
|
|
bitfld.long 0x0 6. "BOP6,Port Set bit 6" "0,1"
|
|
bitfld.long 0x0 5. "BOP5,Port Set bit 5" "0,1"
|
|
bitfld.long 0x0 4. "BOP4,Port Set bit 4" "0,1"
|
|
bitfld.long 0x0 3. "BOP3,Port Set bit 3" "0,1"
|
|
bitfld.long 0x0 2. "BOP2,Port Set bit 2" "0,1"
|
|
bitfld.long 0x0 1. "BOP1,Port Set bit 1" "0,1"
|
|
bitfld.long 0x0 0. "BOP0,Port Set bit 0" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LOCK,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LKK,Lock sequence key" "0,1"
|
|
bitfld.long 0x0 15. "LK15,Port Lock bit 15" "0,1"
|
|
bitfld.long 0x0 14. "LK14,Port Lock bit 14" "0,1"
|
|
bitfld.long 0x0 13. "LK13,Port Lock bit 13" "0,1"
|
|
bitfld.long 0x0 12. "LK12,Port Lock bit 12" "0,1"
|
|
bitfld.long 0x0 11. "LK11,Port Lock bit 11" "0,1"
|
|
bitfld.long 0x0 10. "LK10,Port Lock bit 10" "0,1"
|
|
bitfld.long 0x0 9. "LK9,Port Lock bit 9" "0,1"
|
|
bitfld.long 0x0 8. "LK8,Port Lock bit 8" "0,1"
|
|
bitfld.long 0x0 7. "LK7,Port Lock bit 7" "0,1"
|
|
bitfld.long 0x0 6. "LK6,Port Lock bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LK5,Port Lock bit 5" "0,1"
|
|
bitfld.long 0x0 4. "LK4,Port Lock bit 4" "0,1"
|
|
bitfld.long 0x0 3. "LK3,Port Lock bit 3" "0,1"
|
|
bitfld.long 0x0 2. "LK2,Port Lock bit 2" "0,1"
|
|
bitfld.long 0x0 1. "LK1,Port Lock bit 1" "0,1"
|
|
bitfld.long 0x0 0. "LK0,Port Lock bit 0" "0,1"
|
|
line.long 0x4 "AFSEL0,GPIO alternate function selected register 0"
|
|
hexmask.long.byte 0x4 28.--31. 1. "SEL7,Port 7 alternate function selected"
|
|
hexmask.long.byte 0x4 24.--27. 1. "SEL6,Port 6 alternate function selected"
|
|
hexmask.long.byte 0x4 20.--23. 1. "SEL5,Port 5 alternate function selected"
|
|
hexmask.long.byte 0x4 16.--19. 1. "SEL4,Port 4 alternate function selected"
|
|
hexmask.long.byte 0x4 12.--15. 1. "SEL3,Port 3 alternate function selected"
|
|
hexmask.long.byte 0x4 8.--11. 1. "SEL2,Port 2 alternate function selected"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SEL1,Port 1 alternate function selected"
|
|
hexmask.long.byte 0x4 0.--3. 1. "SEL0,Port 0 alternate function selected"
|
|
line.long 0x8 "AFSEL1,GPIO alternate function selected register 1"
|
|
hexmask.long.byte 0x8 28.--31. 1. "SEL15,Port 15 alternate function selected"
|
|
hexmask.long.byte 0x8 24.--27. 1. "SEL14,Port 14 alternate function selected"
|
|
hexmask.long.byte 0x8 20.--23. 1. "SEL13,Port 13 alternate function selected"
|
|
hexmask.long.byte 0x8 16.--19. 1. "SEL12,Port 12 alternate function selected"
|
|
hexmask.long.byte 0x8 12.--15. 1. "SEL11,Port 11 alternate function selected"
|
|
hexmask.long.byte 0x8 8.--11. 1. "SEL10,Port 10 alternate function selected"
|
|
hexmask.long.byte 0x8 4.--7. 1. "SEL9,Port 9 alternate function selected"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SEL8,Port 8 alternate function selected"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "BC,Bit clear register"
|
|
bitfld.long 0x0 15. "CR15,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 14. "CR14,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 13. "CR13,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 12. "CR12,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 11. "CR11,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 10. "CR10,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 9. "CR9,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 8. "CR8,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 7. "CR7,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 6. "CR6,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 5. "CR5,Port cleat bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CR4,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 3. "CR3,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 2. "CR2,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 1. "CR1,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 0. "CR0,Port cleat bit" "0,1"
|
|
line.long 0x4 "TG,Port bit toggle register"
|
|
bitfld.long 0x4 15. "TG15,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 14. "TG14,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 13. "TG13,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 12. "TG12,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 11. "TG11,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 10. "TG10,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 9. "TG9,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 8. "TG8,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 7. "TG7,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 6. "TG6,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 5. "TG5,Port toggle bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TG4,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 3. "TG3,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 2. "TG2,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 1. "TG1,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 0. "TG0,Port toggle bit" "0,1"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "IFL,Input filtering regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FLPRD1,Filter sampling period for GPIO8 to GPIO15:"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FLPRD0,Filter sampling period for GPIO1 to GPIO7:"
|
|
line.long 0x4 "IFTP,Input filtering type regist"
|
|
bitfld.long 0x4 30.--31. "IFTP15,Pin 15 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "IFTP14,Pin 14 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "IFTP13,Pin 13 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "IFTP12,Pin 12 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "IFTP11,Pin 11 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "IFTP10,Pin 10 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "IFTP9,Pin 9 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "IFTP8,Pin 8 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "IFTP7,Pin 7 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "IFTP6,Pin 6 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "IFTP5,Pin 5 input filtering type bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "IFTP4,Pin 4 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "IFTP3,Pin 3 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "IFTP2,Pin 2 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "IFTP1,Pin 1 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "IFTP0,Pin 0 input filtering type bits" "0,1,2,3"
|
|
tree.end
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
tree "GPIOJ"
|
|
base ad:0x58022400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTL,GPIO port control register"
|
|
bitfld.long 0x0 30.--31. "CTL15,Port x configuration bits (x = 15)" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "CTL14,Port x configuration bits (x = 14)" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "CTL13,Port x configuration bits (x = 13)" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "CTL12,Port x configuration bits (x = 12)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "CTL11,Port x configuration bits (x = 11)" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "CTL10,Port x configuration bits (x = 10)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "CTL9,Port x configuration bits (x = 9)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "CTL8,Port x configuration bits (x = 8)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "CTL7,Port x configuration bits (x = 7)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CTL6,Port x configuration bits (x = 6 )" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "CTL5,Port x configuration bits (x = 5)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CTL4,Port x configuration bits (x = 4 )" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "CTL3,Port x configuration bits (x = 3)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "CTL2,Port x configuration bits (x = 2)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "CTL1,Port x configuration bits (x = 1)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CTL0,Port x configuration bits (x = 0)" "0,1,2,3"
|
|
line.long 0x4 "OMODE,GPIO port output mode register"
|
|
bitfld.long 0x4 15. "OM15,Port 15 output mode bit" "0,1"
|
|
bitfld.long 0x4 14. "OM14,Port 14 output mode bit" "0,1"
|
|
bitfld.long 0x4 13. "OM13,Port 13 output mode bit" "0,1"
|
|
bitfld.long 0x4 12. "OM12,Port 12 output mode bit" "0,1"
|
|
bitfld.long 0x4 11. "OM11,Port 11 output mode bit" "0,1"
|
|
bitfld.long 0x4 10. "OM10,Port 10 output mode bit" "0,1"
|
|
bitfld.long 0x4 9. "OM9,Port 9 output mode bit" "0,1"
|
|
bitfld.long 0x4 8. "OM8,Port 8 output mode bit" "0,1"
|
|
bitfld.long 0x4 7. "OM7,Port 7 output mode bit" "0,1"
|
|
bitfld.long 0x4 6. "OM6,Port 6 output mode bit" "0,1"
|
|
bitfld.long 0x4 5. "OM5,Port 5 output mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "OM4,Port 4 output mode bit" "0,1"
|
|
bitfld.long 0x4 3. "OM3,Port 3 output mode bit" "0,1"
|
|
bitfld.long 0x4 2. "OM2,Port 2 output mode bit" "0,1"
|
|
bitfld.long 0x4 1. "OM1,Port 1 output mode bit" "0,1"
|
|
bitfld.long 0x4 0. "OM0,Port 0 output mode bit" "0,1"
|
|
line.long 0x8 "OSPD,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPD15,Port 15 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPD14,Port 14 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPD13,Port 13 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPD12,Port 12 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPD11,Port 11 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPD10,Port 10 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPD9,Port 9 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPD8,Port 8 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPD7,Port 7 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPD6,Port 6 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "OSPD5,Port 5 output max speed bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "OSPD4,Port 4 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPD3,Port 3 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPD2,Port 2 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPD1,Port 1 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPD0,Port 0 output max speed bits" "0,1,2,3"
|
|
line.long 0xC "PUD,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUD15,Port 15 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUD14,Port 14 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUD13,Port 13 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUD12,Port 12 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUD11,Port 11 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUD10,Port 10 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUD9,Port 9 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUD8,Port 8 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUD7,Port 7 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUD6,Port 6 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUD5,Port 5 pull-up or pull-down bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "PUD4,Port 4 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUD3,Port 3 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUD2,Port 2 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUD1,Port 1 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUD0,Port 0 pull-up or pull-down bits" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "ISTAT,GPIO port input status register"
|
|
bitfld.long 0x0 15. "ISTAT15,Port input status (y = 15)" "0,1"
|
|
bitfld.long 0x0 14. "ISTAT14,Port input status (y = 14)" "0,1"
|
|
bitfld.long 0x0 13. "ISTAT13,Port input status (y = 13)" "0,1"
|
|
bitfld.long 0x0 12. "ISTAT12,Port input status (y = 12)" "0,1"
|
|
bitfld.long 0x0 11. "ISTAT11,Port input status (y = 11)" "0,1"
|
|
bitfld.long 0x0 10. "ISTAT10,Port input status (y = 10)" "0,1"
|
|
bitfld.long 0x0 9. "ISTAT9,Port input status (y = 9)" "0,1"
|
|
bitfld.long 0x0 8. "ISTAT8,Port input status (y = 8)" "0,1"
|
|
bitfld.long 0x0 7. "ISTAT7,Port input status (y = 7)" "0,1"
|
|
bitfld.long 0x0 6. "ISTAT6,Port input status (y = 6)" "0,1"
|
|
bitfld.long 0x0 5. "ISTAT5,Port input status (y = 5)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ISTAT4,Port input status (y = 4)" "0,1"
|
|
bitfld.long 0x0 3. "ISTAT3,Port input status (y = 3)" "0,1"
|
|
bitfld.long 0x0 2. "ISTAT2,Port input status (y = 2)" "0,1"
|
|
bitfld.long 0x0 1. "ISTAT1,Port input status (y = 1)" "0,1"
|
|
bitfld.long 0x0 0. "ISTAT0,Port input status (y = 0)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "OCTL,GPIO port output control register"
|
|
bitfld.long 0x0 15. "OCTL15,Port output control (y = 15)" "0,1"
|
|
bitfld.long 0x0 14. "OCTL14,Port output control (y = 14)" "0,1"
|
|
bitfld.long 0x0 13. "OCTL13,Port output control (y = 13)" "0,1"
|
|
bitfld.long 0x0 12. "OCTL12,Port output control (y = 12)" "0,1"
|
|
bitfld.long 0x0 11. "OCTL11,Port output control (y = 11)" "0,1"
|
|
bitfld.long 0x0 10. "OCTL10,Port output control (y = 10)" "0,1"
|
|
bitfld.long 0x0 9. "OCTL9,Port output control (y = 9)" "0,1"
|
|
bitfld.long 0x0 8. "OCTL8,Port output control (y = 8)" "0,1"
|
|
bitfld.long 0x0 7. "OCTL7,Port output control (y = 7)" "0,1"
|
|
bitfld.long 0x0 6. "OCTL6,Port output control (y = 6)" "0,1"
|
|
bitfld.long 0x0 5. "OCTL5,Port output control (y = 5)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "OCTL4,Port output control (y = 4)" "0,1"
|
|
bitfld.long 0x0 3. "OCTL3,Port output control (y = 3)" "0,1"
|
|
bitfld.long 0x0 2. "OCTL2,Port output control (y = 2)" "0,1"
|
|
bitfld.long 0x0 1. "OCTL1,Port output control (y = 1)" "0,1"
|
|
bitfld.long 0x0 0. "OCTL0,Port output control (y = 0)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BOP,GPIO port bit operate register"
|
|
bitfld.long 0x0 31. "CR15,Port Clear bit 15" "0,1"
|
|
bitfld.long 0x0 30. "CR14,Port Clear bit 14" "0,1"
|
|
bitfld.long 0x0 29. "CR13,Port Clear bit 13" "0,1"
|
|
bitfld.long 0x0 28. "CR12,Port Clear bit 12" "0,1"
|
|
bitfld.long 0x0 27. "CR11,Port Clear bit 11" "0,1"
|
|
bitfld.long 0x0 26. "CR10,Port Clear bit 10" "0,1"
|
|
bitfld.long 0x0 25. "CR9,Port Clear bit 9" "0,1"
|
|
bitfld.long 0x0 24. "CR8,Port Clear bit 8" "0,1"
|
|
bitfld.long 0x0 23. "CR7,Port Clear bit 7" "0,1"
|
|
bitfld.long 0x0 22. "CR6,Port Clear bit 6" "0,1"
|
|
bitfld.long 0x0 21. "CR5,Port Clear bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "CR4,Port Clear bit 4" "0,1"
|
|
bitfld.long 0x0 19. "CR3,Port Clear bit 3" "0,1"
|
|
bitfld.long 0x0 18. "CR2,Port Clear bit 2" "0,1"
|
|
bitfld.long 0x0 17. "CR1,Port Clear bit 1" "0,1"
|
|
bitfld.long 0x0 16. "CR0,Port Clear bit 0" "0,1"
|
|
bitfld.long 0x0 15. "BOP15,Port Set bit 15" "0,1"
|
|
bitfld.long 0x0 14. "BOP14,Port Set bit 14" "0,1"
|
|
bitfld.long 0x0 13. "BOP13,Port Set bit 13" "0,1"
|
|
bitfld.long 0x0 12. "BOP12,Port Set bit 12" "0,1"
|
|
bitfld.long 0x0 11. "BOP11,Port Set bit 11" "0,1"
|
|
bitfld.long 0x0 10. "BOP10,Port Set bit 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "BOP9,Port Set bit 9" "0,1"
|
|
bitfld.long 0x0 8. "BOP8,Port Set bit 8" "0,1"
|
|
bitfld.long 0x0 7. "BOP7,Port Set bit 7" "0,1"
|
|
bitfld.long 0x0 6. "BOP6,Port Set bit 6" "0,1"
|
|
bitfld.long 0x0 5. "BOP5,Port Set bit 5" "0,1"
|
|
bitfld.long 0x0 4. "BOP4,Port Set bit 4" "0,1"
|
|
bitfld.long 0x0 3. "BOP3,Port Set bit 3" "0,1"
|
|
bitfld.long 0x0 2. "BOP2,Port Set bit 2" "0,1"
|
|
bitfld.long 0x0 1. "BOP1,Port Set bit 1" "0,1"
|
|
bitfld.long 0x0 0. "BOP0,Port Set bit 0" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LOCK,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LKK,Lock sequence key" "0,1"
|
|
bitfld.long 0x0 15. "LK15,Port Lock bit 15" "0,1"
|
|
bitfld.long 0x0 14. "LK14,Port Lock bit 14" "0,1"
|
|
bitfld.long 0x0 13. "LK13,Port Lock bit 13" "0,1"
|
|
bitfld.long 0x0 12. "LK12,Port Lock bit 12" "0,1"
|
|
bitfld.long 0x0 11. "LK11,Port Lock bit 11" "0,1"
|
|
bitfld.long 0x0 10. "LK10,Port Lock bit 10" "0,1"
|
|
bitfld.long 0x0 9. "LK9,Port Lock bit 9" "0,1"
|
|
bitfld.long 0x0 8. "LK8,Port Lock bit 8" "0,1"
|
|
bitfld.long 0x0 7. "LK7,Port Lock bit 7" "0,1"
|
|
bitfld.long 0x0 6. "LK6,Port Lock bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LK5,Port Lock bit 5" "0,1"
|
|
bitfld.long 0x0 4. "LK4,Port Lock bit 4" "0,1"
|
|
bitfld.long 0x0 3. "LK3,Port Lock bit 3" "0,1"
|
|
bitfld.long 0x0 2. "LK2,Port Lock bit 2" "0,1"
|
|
bitfld.long 0x0 1. "LK1,Port Lock bit 1" "0,1"
|
|
bitfld.long 0x0 0. "LK0,Port Lock bit 0" "0,1"
|
|
line.long 0x4 "AFSEL0,GPIO alternate function selected register 0"
|
|
hexmask.long.byte 0x4 28.--31. 1. "SEL7,Port 7 alternate function selected"
|
|
hexmask.long.byte 0x4 24.--27. 1. "SEL6,Port 6 alternate function selected"
|
|
hexmask.long.byte 0x4 20.--23. 1. "SEL5,Port 5 alternate function selected"
|
|
hexmask.long.byte 0x4 16.--19. 1. "SEL4,Port 4 alternate function selected"
|
|
hexmask.long.byte 0x4 12.--15. 1. "SEL3,Port 3 alternate function selected"
|
|
hexmask.long.byte 0x4 8.--11. 1. "SEL2,Port 2 alternate function selected"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SEL1,Port 1 alternate function selected"
|
|
hexmask.long.byte 0x4 0.--3. 1. "SEL0,Port 0 alternate function selected"
|
|
line.long 0x8 "AFSEL1,GPIO alternate function selected register 1"
|
|
hexmask.long.byte 0x8 28.--31. 1. "SEL15,Port 15 alternate function selected"
|
|
hexmask.long.byte 0x8 24.--27. 1. "SEL14,Port 14 alternate function selected"
|
|
hexmask.long.byte 0x8 20.--23. 1. "SEL13,Port 13 alternate function selected"
|
|
hexmask.long.byte 0x8 16.--19. 1. "SEL12,Port 12 alternate function selected"
|
|
hexmask.long.byte 0x8 12.--15. 1. "SEL11,Port 11 alternate function selected"
|
|
hexmask.long.byte 0x8 8.--11. 1. "SEL10,Port 10 alternate function selected"
|
|
hexmask.long.byte 0x8 4.--7. 1. "SEL9,Port 9 alternate function selected"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SEL8,Port 8 alternate function selected"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "BC,Bit clear register"
|
|
bitfld.long 0x0 15. "CR15,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 14. "CR14,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 13. "CR13,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 12. "CR12,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 11. "CR11,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 10. "CR10,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 9. "CR9,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 8. "CR8,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 7. "CR7,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 6. "CR6,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 5. "CR5,Port cleat bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CR4,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 3. "CR3,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 2. "CR2,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 1. "CR1,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 0. "CR0,Port cleat bit" "0,1"
|
|
line.long 0x4 "TG,Port bit toggle register"
|
|
bitfld.long 0x4 15. "TG15,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 14. "TG14,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 13. "TG13,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 12. "TG12,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 11. "TG11,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 10. "TG10,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 9. "TG9,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 8. "TG8,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 7. "TG7,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 6. "TG6,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 5. "TG5,Port toggle bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TG4,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 3. "TG3,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 2. "TG2,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 1. "TG1,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 0. "TG0,Port toggle bit" "0,1"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "IFL,Input filtering regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FLPRD1,Filter sampling period for GPIO8 to GPIO15:"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FLPRD0,Filter sampling period for GPIO1 to GPIO7:"
|
|
line.long 0x4 "IFTP,Input filtering type regist"
|
|
bitfld.long 0x4 30.--31. "IFTP15,Pin 15 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "IFTP14,Pin 14 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "IFTP13,Pin 13 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "IFTP12,Pin 12 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "IFTP11,Pin 11 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "IFTP10,Pin 10 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "IFTP9,Pin 9 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "IFTP8,Pin 8 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "IFTP7,Pin 7 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "IFTP6,Pin 6 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "IFTP5,Pin 5 input filtering type bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "IFTP4,Pin 4 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "IFTP3,Pin 3 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "IFTP2,Pin 2 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "IFTP1,Pin 1 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "IFTP0,Pin 0 input filtering type bits" "0,1,2,3"
|
|
tree.end
|
|
tree "GPIOK"
|
|
base ad:0x58022800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTL,GPIO port control register"
|
|
bitfld.long 0x0 30.--31. "CTL15,Port x configuration bits (x = 15)" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "CTL14,Port x configuration bits (x = 14)" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "CTL13,Port x configuration bits (x = 13)" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "CTL12,Port x configuration bits (x = 12)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "CTL11,Port x configuration bits (x = 11)" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "CTL10,Port x configuration bits (x = 10)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "CTL9,Port x configuration bits (x = 9)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "CTL8,Port x configuration bits (x = 8)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "CTL7,Port x configuration bits (x = 7)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CTL6,Port x configuration bits (x = 6 )" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "CTL5,Port x configuration bits (x = 5)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CTL4,Port x configuration bits (x = 4 )" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "CTL3,Port x configuration bits (x = 3)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "CTL2,Port x configuration bits (x = 2)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "CTL1,Port x configuration bits (x = 1)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CTL0,Port x configuration bits (x = 0)" "0,1,2,3"
|
|
line.long 0x4 "OMODE,GPIO port output mode register"
|
|
bitfld.long 0x4 15. "OM15,Port 15 output mode bit" "0,1"
|
|
bitfld.long 0x4 14. "OM14,Port 14 output mode bit" "0,1"
|
|
bitfld.long 0x4 13. "OM13,Port 13 output mode bit" "0,1"
|
|
bitfld.long 0x4 12. "OM12,Port 12 output mode bit" "0,1"
|
|
bitfld.long 0x4 11. "OM11,Port 11 output mode bit" "0,1"
|
|
bitfld.long 0x4 10. "OM10,Port 10 output mode bit" "0,1"
|
|
bitfld.long 0x4 9. "OM9,Port 9 output mode bit" "0,1"
|
|
bitfld.long 0x4 8. "OM8,Port 8 output mode bit" "0,1"
|
|
bitfld.long 0x4 7. "OM7,Port 7 output mode bit" "0,1"
|
|
bitfld.long 0x4 6. "OM6,Port 6 output mode bit" "0,1"
|
|
bitfld.long 0x4 5. "OM5,Port 5 output mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "OM4,Port 4 output mode bit" "0,1"
|
|
bitfld.long 0x4 3. "OM3,Port 3 output mode bit" "0,1"
|
|
bitfld.long 0x4 2. "OM2,Port 2 output mode bit" "0,1"
|
|
bitfld.long 0x4 1. "OM1,Port 1 output mode bit" "0,1"
|
|
bitfld.long 0x4 0. "OM0,Port 0 output mode bit" "0,1"
|
|
line.long 0x8 "OSPD,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPD15,Port 15 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPD14,Port 14 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPD13,Port 13 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPD12,Port 12 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPD11,Port 11 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPD10,Port 10 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPD9,Port 9 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPD8,Port 8 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPD7,Port 7 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPD6,Port 6 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "OSPD5,Port 5 output max speed bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "OSPD4,Port 4 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPD3,Port 3 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPD2,Port 2 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPD1,Port 1 output max speed bits" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPD0,Port 0 output max speed bits" "0,1,2,3"
|
|
line.long 0xC "PUD,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUD15,Port 15 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUD14,Port 14 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUD13,Port 13 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUD12,Port 12 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUD11,Port 11 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUD10,Port 10 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUD9,Port 9 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUD8,Port 8 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUD7,Port 7 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUD6,Port 6 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUD5,Port 5 pull-up or pull-down bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "PUD4,Port 4 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUD3,Port 3 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUD2,Port 2 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUD1,Port 1 pull-up or pull-down bits" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUD0,Port 0 pull-up or pull-down bits" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "ISTAT,GPIO port input status register"
|
|
bitfld.long 0x0 15. "ISTAT15,Port input status (y = 15)" "0,1"
|
|
bitfld.long 0x0 14. "ISTAT14,Port input status (y = 14)" "0,1"
|
|
bitfld.long 0x0 13. "ISTAT13,Port input status (y = 13)" "0,1"
|
|
bitfld.long 0x0 12. "ISTAT12,Port input status (y = 12)" "0,1"
|
|
bitfld.long 0x0 11. "ISTAT11,Port input status (y = 11)" "0,1"
|
|
bitfld.long 0x0 10. "ISTAT10,Port input status (y = 10)" "0,1"
|
|
bitfld.long 0x0 9. "ISTAT9,Port input status (y = 9)" "0,1"
|
|
bitfld.long 0x0 8. "ISTAT8,Port input status (y = 8)" "0,1"
|
|
bitfld.long 0x0 7. "ISTAT7,Port input status (y = 7)" "0,1"
|
|
bitfld.long 0x0 6. "ISTAT6,Port input status (y = 6)" "0,1"
|
|
bitfld.long 0x0 5. "ISTAT5,Port input status (y = 5)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ISTAT4,Port input status (y = 4)" "0,1"
|
|
bitfld.long 0x0 3. "ISTAT3,Port input status (y = 3)" "0,1"
|
|
bitfld.long 0x0 2. "ISTAT2,Port input status (y = 2)" "0,1"
|
|
bitfld.long 0x0 1. "ISTAT1,Port input status (y = 1)" "0,1"
|
|
bitfld.long 0x0 0. "ISTAT0,Port input status (y = 0)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "OCTL,GPIO port output control register"
|
|
bitfld.long 0x0 15. "OCTL15,Port output control (y = 15)" "0,1"
|
|
bitfld.long 0x0 14. "OCTL14,Port output control (y = 14)" "0,1"
|
|
bitfld.long 0x0 13. "OCTL13,Port output control (y = 13)" "0,1"
|
|
bitfld.long 0x0 12. "OCTL12,Port output control (y = 12)" "0,1"
|
|
bitfld.long 0x0 11. "OCTL11,Port output control (y = 11)" "0,1"
|
|
bitfld.long 0x0 10. "OCTL10,Port output control (y = 10)" "0,1"
|
|
bitfld.long 0x0 9. "OCTL9,Port output control (y = 9)" "0,1"
|
|
bitfld.long 0x0 8. "OCTL8,Port output control (y = 8)" "0,1"
|
|
bitfld.long 0x0 7. "OCTL7,Port output control (y = 7)" "0,1"
|
|
bitfld.long 0x0 6. "OCTL6,Port output control (y = 6)" "0,1"
|
|
bitfld.long 0x0 5. "OCTL5,Port output control (y = 5)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "OCTL4,Port output control (y = 4)" "0,1"
|
|
bitfld.long 0x0 3. "OCTL3,Port output control (y = 3)" "0,1"
|
|
bitfld.long 0x0 2. "OCTL2,Port output control (y = 2)" "0,1"
|
|
bitfld.long 0x0 1. "OCTL1,Port output control (y = 1)" "0,1"
|
|
bitfld.long 0x0 0. "OCTL0,Port output control (y = 0)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BOP,GPIO port bit operate register"
|
|
bitfld.long 0x0 31. "CR15,Port Clear bit 15" "0,1"
|
|
bitfld.long 0x0 30. "CR14,Port Clear bit 14" "0,1"
|
|
bitfld.long 0x0 29. "CR13,Port Clear bit 13" "0,1"
|
|
bitfld.long 0x0 28. "CR12,Port Clear bit 12" "0,1"
|
|
bitfld.long 0x0 27. "CR11,Port Clear bit 11" "0,1"
|
|
bitfld.long 0x0 26. "CR10,Port Clear bit 10" "0,1"
|
|
bitfld.long 0x0 25. "CR9,Port Clear bit 9" "0,1"
|
|
bitfld.long 0x0 24. "CR8,Port Clear bit 8" "0,1"
|
|
bitfld.long 0x0 23. "CR7,Port Clear bit 7" "0,1"
|
|
bitfld.long 0x0 22. "CR6,Port Clear bit 6" "0,1"
|
|
bitfld.long 0x0 21. "CR5,Port Clear bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "CR4,Port Clear bit 4" "0,1"
|
|
bitfld.long 0x0 19. "CR3,Port Clear bit 3" "0,1"
|
|
bitfld.long 0x0 18. "CR2,Port Clear bit 2" "0,1"
|
|
bitfld.long 0x0 17. "CR1,Port Clear bit 1" "0,1"
|
|
bitfld.long 0x0 16. "CR0,Port Clear bit 0" "0,1"
|
|
bitfld.long 0x0 15. "BOP15,Port Set bit 15" "0,1"
|
|
bitfld.long 0x0 14. "BOP14,Port Set bit 14" "0,1"
|
|
bitfld.long 0x0 13. "BOP13,Port Set bit 13" "0,1"
|
|
bitfld.long 0x0 12. "BOP12,Port Set bit 12" "0,1"
|
|
bitfld.long 0x0 11. "BOP11,Port Set bit 11" "0,1"
|
|
bitfld.long 0x0 10. "BOP10,Port Set bit 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "BOP9,Port Set bit 9" "0,1"
|
|
bitfld.long 0x0 8. "BOP8,Port Set bit 8" "0,1"
|
|
bitfld.long 0x0 7. "BOP7,Port Set bit 7" "0,1"
|
|
bitfld.long 0x0 6. "BOP6,Port Set bit 6" "0,1"
|
|
bitfld.long 0x0 5. "BOP5,Port Set bit 5" "0,1"
|
|
bitfld.long 0x0 4. "BOP4,Port Set bit 4" "0,1"
|
|
bitfld.long 0x0 3. "BOP3,Port Set bit 3" "0,1"
|
|
bitfld.long 0x0 2. "BOP2,Port Set bit 2" "0,1"
|
|
bitfld.long 0x0 1. "BOP1,Port Set bit 1" "0,1"
|
|
bitfld.long 0x0 0. "BOP0,Port Set bit 0" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LOCK,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LKK,Lock sequence key" "0,1"
|
|
bitfld.long 0x0 15. "LK15,Port Lock bit 15" "0,1"
|
|
bitfld.long 0x0 14. "LK14,Port Lock bit 14" "0,1"
|
|
bitfld.long 0x0 13. "LK13,Port Lock bit 13" "0,1"
|
|
bitfld.long 0x0 12. "LK12,Port Lock bit 12" "0,1"
|
|
bitfld.long 0x0 11. "LK11,Port Lock bit 11" "0,1"
|
|
bitfld.long 0x0 10. "LK10,Port Lock bit 10" "0,1"
|
|
bitfld.long 0x0 9. "LK9,Port Lock bit 9" "0,1"
|
|
bitfld.long 0x0 8. "LK8,Port Lock bit 8" "0,1"
|
|
bitfld.long 0x0 7. "LK7,Port Lock bit 7" "0,1"
|
|
bitfld.long 0x0 6. "LK6,Port Lock bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LK5,Port Lock bit 5" "0,1"
|
|
bitfld.long 0x0 4. "LK4,Port Lock bit 4" "0,1"
|
|
bitfld.long 0x0 3. "LK3,Port Lock bit 3" "0,1"
|
|
bitfld.long 0x0 2. "LK2,Port Lock bit 2" "0,1"
|
|
bitfld.long 0x0 1. "LK1,Port Lock bit 1" "0,1"
|
|
bitfld.long 0x0 0. "LK0,Port Lock bit 0" "0,1"
|
|
line.long 0x4 "AFSEL0,GPIO alternate function selected register 0"
|
|
hexmask.long.byte 0x4 28.--31. 1. "SEL7,Port 7 alternate function selected"
|
|
hexmask.long.byte 0x4 24.--27. 1. "SEL6,Port 6 alternate function selected"
|
|
hexmask.long.byte 0x4 20.--23. 1. "SEL5,Port 5 alternate function selected"
|
|
hexmask.long.byte 0x4 16.--19. 1. "SEL4,Port 4 alternate function selected"
|
|
hexmask.long.byte 0x4 12.--15. 1. "SEL3,Port 3 alternate function selected"
|
|
hexmask.long.byte 0x4 8.--11. 1. "SEL2,Port 2 alternate function selected"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SEL1,Port 1 alternate function selected"
|
|
hexmask.long.byte 0x4 0.--3. 1. "SEL0,Port 0 alternate function selected"
|
|
line.long 0x8 "AFSEL1,GPIO alternate function selected register 1"
|
|
hexmask.long.byte 0x8 28.--31. 1. "SEL15,Port 15 alternate function selected"
|
|
hexmask.long.byte 0x8 24.--27. 1. "SEL14,Port 14 alternate function selected"
|
|
hexmask.long.byte 0x8 20.--23. 1. "SEL13,Port 13 alternate function selected"
|
|
hexmask.long.byte 0x8 16.--19. 1. "SEL12,Port 12 alternate function selected"
|
|
hexmask.long.byte 0x8 12.--15. 1. "SEL11,Port 11 alternate function selected"
|
|
hexmask.long.byte 0x8 8.--11. 1. "SEL10,Port 10 alternate function selected"
|
|
hexmask.long.byte 0x8 4.--7. 1. "SEL9,Port 9 alternate function selected"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SEL8,Port 8 alternate function selected"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "BC,Bit clear register"
|
|
bitfld.long 0x0 15. "CR15,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 14. "CR14,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 13. "CR13,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 12. "CR12,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 11. "CR11,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 10. "CR10,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 9. "CR9,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 8. "CR8,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 7. "CR7,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 6. "CR6,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 5. "CR5,Port cleat bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CR4,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 3. "CR3,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 2. "CR2,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 1. "CR1,Port cleat bit" "0,1"
|
|
bitfld.long 0x0 0. "CR0,Port cleat bit" "0,1"
|
|
line.long 0x4 "TG,Port bit toggle register"
|
|
bitfld.long 0x4 15. "TG15,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 14. "TG14,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 13. "TG13,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 12. "TG12,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 11. "TG11,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 10. "TG10,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 9. "TG9,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 8. "TG8,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 7. "TG7,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 6. "TG6,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 5. "TG5,Port toggle bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TG4,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 3. "TG3,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 2. "TG2,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 1. "TG1,Port toggle bit" "0,1"
|
|
bitfld.long 0x4 0. "TG0,Port toggle bit" "0,1"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "IFL,Input filtering regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FLPRD1,Filter sampling period for GPIO8 to GPIO15:"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FLPRD0,Filter sampling period for GPIO1 to GPIO7:"
|
|
line.long 0x4 "IFTP,Input filtering type regist"
|
|
bitfld.long 0x4 30.--31. "IFTP15,Pin 15 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "IFTP14,Pin 14 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "IFTP13,Pin 13 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "IFTP12,Pin 12 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "IFTP11,Pin 11 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "IFTP10,Pin 10 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "IFTP9,Pin 9 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "IFTP8,Pin 8 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "IFTP7,Pin 7 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "IFTP6,Pin 6 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "IFTP5,Pin 5 input filtering type bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "IFTP4,Pin 4 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "IFTP3,Pin 3 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "IFTP2,Pin 2 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "IFTP1,Pin 1 input filtering type bits" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "IFTP0,Pin 0 input filtering type bits" "0,1,2,3"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
tree "HAU (Hash Acceleration Unit)"
|
|
base ad:0x48021400
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTL,HAU control register"
|
|
bitfld.long 0x0 18. "ALGM,Algorithm selection bit 1" "0,1"
|
|
bitfld.long 0x0 16. "KLM,Key length mode" "0,1"
|
|
bitfld.long 0x0 13. "MDS,Multiple DMA selection" "0,1"
|
|
rbitfld.long 0x0 12. "DINE,DI register is not empty" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "NWIF,Number of words in IN FIFO"
|
|
bitfld.long 0x0 7. "ALGM0,Algorithm selection bit 0" "0,1"
|
|
bitfld.long 0x0 6. "HMS,HAU mode selection" "0,1"
|
|
bitfld.long 0x0 4.--5. "DATAM,Data type mode" "0,1,2,3"
|
|
bitfld.long 0x0 3. "DMAE,DMA enable" "0,1"
|
|
bitfld.long 0x0 2. "START,Start message digest calculation" "0,1"
|
|
line.long 0x4 "DI,HAU data input register"
|
|
hexmask.long 0x4 0.--31. 1. "DI,Message data input"
|
|
line.long 0x8 "CFG,HAU configuration register"
|
|
bitfld.long 0x8 8. "CALEN,Digest calculation enable" "0,1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "VBL,Valid bits length in the last word"
|
|
rgroup.long 0xC++0x13
|
|
line.long 0x0 "DO0,HAU data output register"
|
|
hexmask.long 0x0 0.--31. 1. "DO0,message digest result of hash algorithm"
|
|
line.long 0x4 "DO1,HAU data output register"
|
|
hexmask.long 0x4 0.--31. 1. "DO1,message digest result of hash algorithm"
|
|
line.long 0x8 "DO2,HAU data output register"
|
|
hexmask.long 0x8 0.--31. 1. "DO2,message digest result of hash algorithm"
|
|
line.long 0xC "DO3,HAU data output register"
|
|
hexmask.long 0xC 0.--31. 1. "DO3,message digest result of hash algorithm"
|
|
line.long 0x10 "DO4,HAU data output register"
|
|
hexmask.long 0x10 0.--31. 1. "DO4,message digest result of hash algorithm"
|
|
rgroup.long 0x324++0xB
|
|
line.long 0x0 "DO5,HAU data output register"
|
|
hexmask.long 0x0 0.--31. 1. "DO5,message digest result of hash algorithm"
|
|
line.long 0x4 "DO6,HAU data output register"
|
|
hexmask.long 0x4 0.--31. 1. "DO6,message digest result of hash algorithm"
|
|
line.long 0x8 "DO7,HAU data output register"
|
|
hexmask.long 0x8 0.--31. 1. "DO7,message digest result of hash algorithm"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "INTEN,HAU interrupt enable register"
|
|
bitfld.long 0x0 1. "CCIE,calculation completion interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "DIIE,Data input interrupt enable" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "STAT,HAU status and interrupt flag register"
|
|
bitfld.long 0x0 3. "BUSY,Busy flag bit" "0,1"
|
|
bitfld.long 0x0 2. "DMAS,DMA status flag" "0,1"
|
|
bitfld.long 0x0 1. "CCF,Digest calculation completion flag" "0,1"
|
|
bitfld.long 0x0 0. "DIF,Data input flag" "0,1"
|
|
group.long 0xF8++0xD7
|
|
line.long 0x0 "CTXS0,Context switch register x"
|
|
hexmask.long 0x0 0.--31. 1. "CTX0,The complete internal status"
|
|
line.long 0x4 "CTXS1,Context switch register x"
|
|
hexmask.long 0x4 0.--31. 1. "CTX1,The complete internal status"
|
|
line.long 0x8 "CTXS2,Context switch register x"
|
|
hexmask.long 0x8 0.--31. 1. "CTX2,The complete internal status"
|
|
line.long 0xC "CTXS3,Context switch register x"
|
|
hexmask.long 0xC 0.--31. 1. "CTX3,The complete internal status"
|
|
line.long 0x10 "CTXS4,Context switch register x"
|
|
hexmask.long 0x10 0.--31. 1. "CTX4,The complete internal status"
|
|
line.long 0x14 "CTXS5,Context switch register x"
|
|
hexmask.long 0x14 0.--31. 1. "CTX5,The complete internal status"
|
|
line.long 0x18 "CTXS6,Context switch register x"
|
|
hexmask.long 0x18 0.--31. 1. "CTX6,The complete internal status"
|
|
line.long 0x1C "CTXS7,Context switch register x"
|
|
hexmask.long 0x1C 0.--31. 1. "CTX7,The complete internal status"
|
|
line.long 0x20 "CTXS8,Context switch register x"
|
|
hexmask.long 0x20 0.--31. 1. "CTX8,The complete internal status"
|
|
line.long 0x24 "CTXS9,Context switch register x"
|
|
hexmask.long 0x24 0.--31. 1. "CTX9,The complete internal status"
|
|
line.long 0x28 "CTXS10,Context switch register x"
|
|
hexmask.long 0x28 0.--31. 1. "CTX10,The complete internal status"
|
|
line.long 0x2C "CTXS11,Context switch register x"
|
|
hexmask.long 0x2C 0.--31. 1. "CTX11,The complete internal status"
|
|
line.long 0x30 "CTXS12,Context switch register x"
|
|
hexmask.long 0x30 0.--31. 1. "CTX12,The complete internal status"
|
|
line.long 0x34 "CTXS13,Context switch register x"
|
|
hexmask.long 0x34 0.--31. 1. "CTX13,The complete internal status"
|
|
line.long 0x38 "CTXS14,Context switch register x"
|
|
hexmask.long 0x38 0.--31. 1. "CTX14,The complete internal status"
|
|
line.long 0x3C "CTXS15,Context switch register x"
|
|
hexmask.long 0x3C 0.--31. 1. "CTX15,The complete internal status"
|
|
line.long 0x40 "CTXS16,Context switch register x"
|
|
hexmask.long 0x40 0.--31. 1. "CTX16,The complete internal status"
|
|
line.long 0x44 "CTXS17,Context switch register x"
|
|
hexmask.long 0x44 0.--31. 1. "CTX17,The complete internal status"
|
|
line.long 0x48 "CTXS18,Context switch register x"
|
|
hexmask.long 0x48 0.--31. 1. "CTX18,The complete internal status"
|
|
line.long 0x4C "CTXS19,Context switch register x"
|
|
hexmask.long 0x4C 0.--31. 1. "CTX19,The complete internal status"
|
|
line.long 0x50 "CTXS20,Context switch register x"
|
|
hexmask.long 0x50 0.--31. 1. "CTX20,The complete internal status"
|
|
line.long 0x54 "CTXS21,Context switch register x"
|
|
hexmask.long 0x54 0.--31. 1. "CTX21,The complete internal status"
|
|
line.long 0x58 "CTXS22,Context switch register x"
|
|
hexmask.long 0x58 0.--31. 1. "CTX22,The complete internal status"
|
|
line.long 0x5C "CTXS23,Context switch register x"
|
|
hexmask.long 0x5C 0.--31. 1. "CTX23,The complete internal status"
|
|
line.long 0x60 "CTXS24,Context switch register x"
|
|
hexmask.long 0x60 0.--31. 1. "CTX24,The complete internal status"
|
|
line.long 0x64 "CTXS25,Context switch register x"
|
|
hexmask.long 0x64 0.--31. 1. "CTX25,The complete internal status"
|
|
line.long 0x68 "CTXS26,Context switch register x"
|
|
hexmask.long 0x68 0.--31. 1. "CTX26,The complete internal status"
|
|
line.long 0x6C "CTXS27,Context switch register x"
|
|
hexmask.long 0x6C 0.--31. 1. "CTX27,The complete internal status"
|
|
line.long 0x70 "CTXS28,Context switch register x"
|
|
hexmask.long 0x70 0.--31. 1. "CTX28,The complete internal status"
|
|
line.long 0x74 "CTXS29,Context switch register x"
|
|
hexmask.long 0x74 0.--31. 1. "CTX29,The complete internal status"
|
|
line.long 0x78 "CTXS30,Context switch register x"
|
|
hexmask.long 0x78 0.--31. 1. "CTX30,The complete internal status"
|
|
line.long 0x7C "CTXS31,Context switch register x"
|
|
hexmask.long 0x7C 0.--31. 1. "CTX31,The complete internal status"
|
|
line.long 0x80 "CTXS32,Context switch register x"
|
|
hexmask.long 0x80 0.--31. 1. "CTX32,The complete internal status"
|
|
line.long 0x84 "CTXS33,Context switch register x"
|
|
hexmask.long 0x84 0.--31. 1. "CTX33,The complete internal status"
|
|
line.long 0x88 "CTXS34,Context switch register x"
|
|
hexmask.long 0x88 0.--31. 1. "CTX34,The complete internal status"
|
|
line.long 0x8C "CTXS35,Context switch register x"
|
|
hexmask.long 0x8C 0.--31. 1. "CTX35,The complete internal status"
|
|
line.long 0x90 "CTXS36,Context switch register x"
|
|
hexmask.long 0x90 0.--31. 1. "CTX36,The complete internal status"
|
|
line.long 0x94 "CTXS37,Context switch register x"
|
|
hexmask.long 0x94 0.--31. 1. "CTX37,The complete internal status"
|
|
line.long 0x98 "CTXS38,Context switch register x"
|
|
hexmask.long 0x98 0.--31. 1. "CTX38,The complete internal status"
|
|
line.long 0x9C "CTXS39,Context switch register x"
|
|
hexmask.long 0x9C 0.--31. 1. "CTX39,The complete internal status"
|
|
line.long 0xA0 "CTXS40,Context switch register x"
|
|
hexmask.long 0xA0 0.--31. 1. "CTX40,The complete internal status"
|
|
line.long 0xA4 "CTXS41,Context switch register x"
|
|
hexmask.long 0xA4 0.--31. 1. "CTX41,The complete internal status"
|
|
line.long 0xA8 "CTXS42,Context switch register x"
|
|
hexmask.long 0xA8 0.--31. 1. "CTX42,The complete internal status"
|
|
line.long 0xAC "CTXS43,Context switch register x"
|
|
hexmask.long 0xAC 0.--31. 1. "CTX43,The complete internal status"
|
|
line.long 0xB0 "CTXS44,Context switch register x"
|
|
hexmask.long 0xB0 0.--31. 1. "CTX44,The complete internal status"
|
|
line.long 0xB4 "CTXS45,Context switch register x"
|
|
hexmask.long 0xB4 0.--31. 1. "CTX45,The complete internal status"
|
|
line.long 0xB8 "CTXS46,Context switch register x"
|
|
hexmask.long 0xB8 0.--31. 1. "CTX46,The complete internal status"
|
|
line.long 0xBC "CTXS47,Context switch register x"
|
|
hexmask.long 0xBC 0.--31. 1. "CTX47,The complete internal status"
|
|
line.long 0xC0 "CTXS48,Context switch register x"
|
|
hexmask.long 0xC0 0.--31. 1. "CTX48,The complete internal status"
|
|
line.long 0xC4 "CTXS49,Context switch register x"
|
|
hexmask.long 0xC4 0.--31. 1. "CTX49,The complete internal status"
|
|
line.long 0xC8 "CTXS50,Context switch register x"
|
|
hexmask.long 0xC8 0.--31. 1. "CTX50,The complete internal status"
|
|
line.long 0xCC "CTXS51,Context switch register x"
|
|
hexmask.long 0xCC 0.--31. 1. "CTX51,The complete internal status"
|
|
line.long 0xD0 "CTXS52,Context switch register x"
|
|
hexmask.long 0xD0 0.--31. 1. "CTX52,The complete internal status"
|
|
line.long 0xD4 "CTXS53,Context switch register x"
|
|
hexmask.long 0xD4 0.--31. 1. "CTX53,The complete internal status"
|
|
tree.end
|
|
endif
|
|
tree "HPDF (High Performance Digital Filter)"
|
|
base ad:0x40017000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CH0CTL,Channel 0 control regist"
|
|
bitfld.long 0x0 31. "HPDFEN,Global enable for HPDF interface" "0: HPDF disabled,?"
|
|
bitfld.long 0x0 30. "CKOUTSEL,Serial clock output source selection" "0,1"
|
|
bitfld.long 0x0 29. "CKOUTDM,Serial clock output duty mode" "0,1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Serial clock output divider"
|
|
bitfld.long 0x0 14.--15. "DPM,Data packing mode for HPDF_CHxPDI register" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CMSD,Channel x multiplexer select input data source" "0,1,2,3"
|
|
bitfld.long 0x0 8. "CHPINSEL,Channel inputs pins selection" "0,1"
|
|
bitfld.long 0x0 7. "CHEN,Channel x enable" "0,1"
|
|
bitfld.long 0x0 6. "CKLEN,Clock loss detector enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MMEN,Malfunction monitor enable" "0,1"
|
|
bitfld.long 0x0 2.--3. "SPICKSS,SPI clock source select" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SITYP,Serial interface type" "0,1,2,3"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CH1CTL,Channel 1 control regist"
|
|
bitfld.long 0x0 14.--15. "DPM,Data packing mode for HPDF_CHxPDI register" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CMSD,Channel x multiplexer select input data source" "0,1,2,3"
|
|
bitfld.long 0x0 8. "CHPINSEL,Channel inputs pins selection" "0,1"
|
|
bitfld.long 0x0 7. "CHEN,Channel x enable" "0,1"
|
|
bitfld.long 0x0 6. "CKLEN,Clock loss detector enable" "0,1"
|
|
bitfld.long 0x0 5. "MMEN,Malfunction monitor enable" "0,1"
|
|
bitfld.long 0x0 2.--3. "SPICKSS,SPI clock source select" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SITYP,Serial interface type" "0,1,2,3"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CH2CTL,Channel 2 control regist"
|
|
bitfld.long 0x0 14.--15. "DPM,Data packing mode for HPDF_CHxPDI register" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CMSD,Channel x multiplexer select input data source" "0,1,2,3"
|
|
bitfld.long 0x0 8. "CHPINSEL,Channel inputs pins selection" "0,1"
|
|
bitfld.long 0x0 7. "CHEN,Channel x enable" "0,1"
|
|
bitfld.long 0x0 6. "CKLEN,Clock loss detector enable" "0,1"
|
|
bitfld.long 0x0 5. "MMEN,Malfunction monitor enable" "0,1"
|
|
bitfld.long 0x0 2.--3. "SPICKSS,SPI clock source select" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SITYP,Serial interface type" "0,1,2,3"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "CH3CTL,Channel 3 control regist"
|
|
bitfld.long 0x0 14.--15. "DPM,Data packing mode for HPDF_CHxPDI register" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CMSD,Channel x multiplexer select input data source" "0,1,2,3"
|
|
bitfld.long 0x0 8. "CHPINSEL,Channel inputs pins selection" "0,1"
|
|
bitfld.long 0x0 7. "CHEN,Channel x enable" "0,1"
|
|
bitfld.long 0x0 6. "CKLEN,Clock loss detector enable" "0,1"
|
|
bitfld.long 0x0 5. "MMEN,Malfunction monitor enable" "0,1"
|
|
bitfld.long 0x0 2.--3. "SPICKSS,SPI clock source select" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SITYP,Serial interface type" "0,1,2,3"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "CH4CTL,Channel 4 control regist"
|
|
bitfld.long 0x0 14.--15. "DPM,Data packing mode for HPDF_CHxPDI register" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CMSD,Channel x multiplexer select input data source" "0,1,2,3"
|
|
bitfld.long 0x0 8. "CHPINSEL,Channel inputs pins selection" "0,1"
|
|
bitfld.long 0x0 7. "CHEN,Channel x enable" "0,1"
|
|
bitfld.long 0x0 6. "CKLEN,Clock loss detector enable" "0,1"
|
|
bitfld.long 0x0 5. "MMEN,Malfunction monitor enable" "0,1"
|
|
bitfld.long 0x0 2.--3. "SPICKSS,SPI clock source select" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SITYP,Serial interface type" "0,1,2,3"
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "CH5CTL,Channel 5 control regist"
|
|
bitfld.long 0x0 14.--15. "DPM,Data packing mode for HPDF_CHxPDI register" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CMSD,Channel x multiplexer select input data source" "0,1,2,3"
|
|
bitfld.long 0x0 8. "CHPINSEL,Channel inputs pins selection" "0,1"
|
|
bitfld.long 0x0 7. "CHEN,Channel x enable" "0,1"
|
|
bitfld.long 0x0 6. "CKLEN,Clock loss detector enable" "0,1"
|
|
bitfld.long 0x0 5. "MMEN,Malfunction monitor enable" "0,1"
|
|
bitfld.long 0x0 2.--3. "SPICKSS,SPI clock source select" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SITYP,Serial interface type" "0,1,2,3"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "CH6CTL,Channel 6 control regist"
|
|
bitfld.long 0x0 14.--15. "DPM,Data packing mode for HPDF_CHxPDI register" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CMSD,Channel x multiplexer select input data source" "0,1,2,3"
|
|
bitfld.long 0x0 8. "CHPINSEL,Channel inputs pins selection" "0,1"
|
|
bitfld.long 0x0 7. "CHEN,Channel x enable" "0,1"
|
|
bitfld.long 0x0 6. "CKLEN,Clock loss detector enable" "0,1"
|
|
bitfld.long 0x0 5. "MMEN,Malfunction monitor enable" "0,1"
|
|
bitfld.long 0x0 2.--3. "SPICKSS,SPI clock source select" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SITYP,Serial interface type" "0,1,2,3"
|
|
group.long 0xE0++0x3
|
|
line.long 0x0 "CH7CTL,Channel 7 control regist"
|
|
bitfld.long 0x0 14.--15. "DPM,Data packing mode for HPDF_CHxPDI register" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "CMSD,Channel x multiplexer select input data source" "0,1,2,3"
|
|
bitfld.long 0x0 8. "CHPINSEL,Channel inputs pins selection" "0,1"
|
|
bitfld.long 0x0 7. "CHEN,Channel x enable" "0,1"
|
|
bitfld.long 0x0 6. "CKLEN,Clock loss detector enable" "0,1"
|
|
bitfld.long 0x0 5. "MMEN,Malfunction monitor enable" "0,1"
|
|
bitfld.long 0x0 2.--3. "SPICKSS,SPI clock source select" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SITYP,Serial interface type" "0,1,2,3"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CH0CFG0,Channel 0 configuration register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "CALOFF,24-bit calibration offset"
|
|
hexmask.long.byte 0x0 3.--7. 1. "DTRS,Data right bit-shift"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CH1CFG0,Channel 1 configuration register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "CALOFF,24-bit calibration offset"
|
|
hexmask.long.byte 0x0 3.--7. 1. "DTRS,Data right bit-shift"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "CH2CFG0,Channel 2 configuration register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "CALOFF,24-bit calibration offset"
|
|
hexmask.long.byte 0x0 3.--7. 1. "DTRS,Data right bit-shift"
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "CH3CFG0,Channel 3 configuration register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "CALOFF,24-bit calibration offset"
|
|
hexmask.long.byte 0x0 3.--7. 1. "DTRS,Data right bit-shift"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "CH4CFG0,Channel 4 configuration register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "CALOFF,24-bit calibration offset"
|
|
hexmask.long.byte 0x0 3.--7. 1. "DTRS,Data right bit-shift"
|
|
group.long 0xA4++0x3
|
|
line.long 0x0 "CH5CFG0,Channel 5 configuration register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "CALOFF,24-bit calibration offset"
|
|
hexmask.long.byte 0x0 3.--7. 1. "DTRS,Data right bit-shift"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "CH6CFG0,Channel 6 configuration register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "CALOFF,24-bit calibration offset"
|
|
hexmask.long.byte 0x0 3.--7. 1. "DTRS,Data right bit-shift"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "CH7CFG0,Channel 7 configuration register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "CALOFF,24-bit calibration offset"
|
|
hexmask.long.byte 0x0 3.--7. 1. "DTRS,Data right bit-shift"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CH0CFG1,Channel 0 configuration register"
|
|
bitfld.long 0x0 22.--23. "TMSFO,Threshold monitor Sinc filter order selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TMFOR,Threshold monitor filter oversampling rate (decimation rate)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MMBSD,Malfunction monitor break signal distribution"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MMCT,Malfunction monitor counter threshold"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "CH1CFG1,Channel 1 configuration register"
|
|
bitfld.long 0x0 22.--23. "TMSFO,Threshold monitor Sinc filter order selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TMFOR,Threshold monitor filter oversampling rate (decimation rate)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MMBSD,Malfunction monitor break signal distribution"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MMCT,Malfunction monitor counter threshold"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "CH2CFG1,Channel 2 configuration register"
|
|
bitfld.long 0x0 22.--23. "TMSFO,Threshold monitor Sinc filter order selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TMFOR,Threshold monitor filter oversampling rate (decimation rate)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MMBSD,Malfunction monitor break signal distribution"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MMCT,Malfunction monitor counter threshold"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "CH3CFG1,Channel 3 configuration register"
|
|
bitfld.long 0x0 22.--23. "TMSFO,Threshold monitor Sinc filter order selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TMFOR,Threshold monitor filter oversampling rate (decimation rate)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MMBSD,Malfunction monitor break signal distribution"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MMCT,Malfunction monitor counter threshold"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "CH4CFG1,Channel 4 configuration register"
|
|
bitfld.long 0x0 22.--23. "TMSFO,Threshold monitor Sinc filter order selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TMFOR,Threshold monitor filter oversampling rate (decimation rate)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MMBSD,Malfunction monitor break signal distribution"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MMCT,Malfunction monitor counter threshold"
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "CH5CFG1,Channel 5 configuration register"
|
|
bitfld.long 0x0 22.--23. "TMSFO,Threshold monitor Sinc filter order selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TMFOR,Threshold monitor filter oversampling rate (decimation rate)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MMBSD,Malfunction monitor break signal distribution"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MMCT,Malfunction monitor counter threshold"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "CH6CFG1,Channel 6 configuration register"
|
|
bitfld.long 0x0 22.--23. "TMSFO,Threshold monitor Sinc filter order selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TMFOR,Threshold monitor filter oversampling rate (decimation rate)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MMBSD,Malfunction monitor break signal distribution"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MMCT,Malfunction monitor counter threshold"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "CH7CFG1,Channel 7 configuration register"
|
|
bitfld.long 0x0 22.--23. "TMSFO,Threshold monitor Sinc filter order selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TMFOR,Threshold monitor filter oversampling rate (decimation rate)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MMBSD,Malfunction monitor break signal distribution"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MMCT,Malfunction monitor counter threshold"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CH0TMFDT,Channel 0 threshold monitor filter data regist"
|
|
hexmask.long.word 0x0 0.--15. 1. "TMDATA,Threshold monitor data"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "CH1TMFDT,Channel 1 threshold monitor filter data regist"
|
|
hexmask.long.word 0x0 0.--15. 1. "TMDATA,Threshold monitor data"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "CH2TMFDT,Channel 2 threshold monitor filter data regist"
|
|
hexmask.long.word 0x0 0.--15. 1. "TMDATA,Threshold monitor data"
|
|
rgroup.long 0x6C++0x3
|
|
line.long 0x0 "CH3TMFDT,Channel 3 threshold monitor filter data regist"
|
|
hexmask.long.word 0x0 0.--15. 1. "TMDATA,Threshold monitor data"
|
|
rgroup.long 0x8C++0x3
|
|
line.long 0x0 "CH4TMFDT,Channel 4 threshold monitor filter data regist"
|
|
hexmask.long.word 0x0 0.--15. 1. "TMDATA,Threshold monitor data"
|
|
rgroup.long 0xAC++0x3
|
|
line.long 0x0 "CH5TMFDT,Channel 5 threshold monitor filter data regist"
|
|
hexmask.long.word 0x0 0.--15. 1. "TMDATA,Threshold monitor data"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "CH6TMFDT,Channel 6 threshold monitor filter data regist"
|
|
hexmask.long.word 0x0 0.--15. 1. "TMDATA,Threshold monitor data"
|
|
rgroup.long 0xEC++0x3
|
|
line.long 0x0 "CH7TMFDT,Channel 7 threshold monitor filter data regist"
|
|
hexmask.long.word 0x0 0.--15. 1. "TMDATA,Threshold monitor data"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CH0PDI,Channel 0 parallel data input regist"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATAIN1,Data input for channel x or channel x+1"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATAIN0,Data input for channel x"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "CH1PDI,Channel 1 parallel data input regist"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATAIN1,Data input for channel x or channel x+1"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATAIN0,Data input for channel x"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "CH2PDI,Channel 2 parallel data input regist"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATAIN1,Data input for channel x or channel x+1"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATAIN0,Data input for channel x"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "CH3PDI,Channel 3 parallel data input regist"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATAIN1,Data input for channel x or channel x+1"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATAIN0,Data input for channel x"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "CH4PDI,Channel 4 parallel data input regist"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATAIN1,Data input for channel x or channel x+1"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATAIN0,Data input for channel x"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "CH5PDI,Channel 5 parallel data input regist"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATAIN1,Data input for channel x or channel x+1"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATAIN0,Data input for channel x"
|
|
group.long 0xD0++0x3
|
|
line.long 0x0 "CH6PDI,Channel 6 parallel data input regist"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATAIN1,Data input for channel x or channel x+1"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATAIN0,Data input for channel x"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "CH7PDI,Channel 7 parallel data input regist"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATAIN1,Data input for channel x or channel x+1"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATAIN0,Data input for channel x"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "CH0PS,Channel 0 pulse skip regist"
|
|
hexmask.long.byte 0x0 0.--5. 1. "PLSK,Pulses to skip for input data skipping function"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "CH1PS,Channel 1 pulse skip regist"
|
|
hexmask.long.byte 0x0 0.--5. 1. "PLSK,Pulses to skip for input data skipping function"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "CH2PS,Channel 2 pulse skip regist"
|
|
hexmask.long.byte 0x0 0.--5. 1. "PLSK,Pulses to skip for input data skipping function"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "CH3PS,Channel 3 pulse skip regist"
|
|
hexmask.long.byte 0x0 0.--5. 1. "PLSK,Pulses to skip for input data skipping function"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "CH4PS,Channel 4 pulse skip regist"
|
|
hexmask.long.byte 0x0 0.--5. 1. "PLSK,Pulses to skip for input data skipping function"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "CH5PS,Channel 5 pulse skip regist"
|
|
hexmask.long.byte 0x0 0.--5. 1. "PLSK,Pulses to skip for input data skipping function"
|
|
group.long 0xD4++0x3
|
|
line.long 0x0 "CH6PS,Channel 6 pulse skip regist"
|
|
hexmask.long.byte 0x0 0.--5. 1. "PLSK,Pulses to skip for input data skipping function"
|
|
group.long 0xF4++0x3
|
|
line.long 0x0 "CH7PS,Channel 7 pulse skip regist"
|
|
hexmask.long.byte 0x0 0.--5. 1. "PLSK,Pulses to skip for input data skipping function"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FLT0CTL0,Filter 0 control register"
|
|
bitfld.long 0x0 30. "TMFM,Threshold monitor fast mode" "0,1"
|
|
bitfld.long 0x0 29. "FAST,Fast conversion mode for regular conversions" "0,1"
|
|
bitfld.long 0x0 24.--26. "RCS,Regular conversion channel selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 21. "RCDMAEN,DMA channel enabled to read data for the regular conversion" "0,1"
|
|
bitfld.long 0x0 19. "RCSYN,Regular conversion synchronously with HPDF_FLT0" "0,1"
|
|
bitfld.long 0x0 18. "RCCM,Regular conversions continuous mode" "0,1"
|
|
bitfld.long 0x0 17. "SRCS,Start regular channel conversion by software" "0,1"
|
|
bitfld.long 0x0 13.--14. "ICTEEN,Inserted conversions trigger edge enable" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "ICTSSEL,Inserted conversions trigger signal selection"
|
|
newline
|
|
bitfld.long 0x0 5. "ICDMAEN,DMA channel enabled to read data for the inserted channel group" "0,1"
|
|
bitfld.long 0x0 4. "SCMOD,Scan conversion mode of inserted conversions" "0,1"
|
|
bitfld.long 0x0 3. "ICSYN,Inserted conversion synchronously with the HPDF_FLT0 SICC trigger" "0,1"
|
|
bitfld.long 0x0 1. "SICC,Start inserted group channel conversion" "0,1"
|
|
bitfld.long 0x0 0. "FLTEN,HPDF_FLTy enable" "0,1"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "FLT1CTL0,Filter 1 control register"
|
|
bitfld.long 0x0 30. "TMFM,Threshold monitor fast mode" "0,1"
|
|
bitfld.long 0x0 29. "FAST,Fast conversion mode for regular conversions" "0,1"
|
|
bitfld.long 0x0 24.--26. "RCS,Regular conversion channel selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 21. "RCDMAEN,DMA channel enabled to read data for the regular conversion" "0,1"
|
|
bitfld.long 0x0 19. "RCSYN,Regular conversion synchronously with HPDF_FLT0" "0,1"
|
|
bitfld.long 0x0 18. "RCCM,Regular conversions continuous mode" "0,1"
|
|
bitfld.long 0x0 17. "SRCS,Start regular channel conversion by software" "0,1"
|
|
bitfld.long 0x0 13.--14. "ICTEEN,Inserted conversions trigger edge enable" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "ICTSSEL,Inserted conversions trigger signal selection"
|
|
newline
|
|
bitfld.long 0x0 5. "ICDMAEN,DMA channel enabled to read data for the inserted channel group" "0,1"
|
|
bitfld.long 0x0 4. "SCMOD,Scan conversion mode of inserted conversions" "0,1"
|
|
bitfld.long 0x0 3. "ICSYN,Inserted conversion synchronously with the HPDF_FLT0 SICC trigger" "0,1"
|
|
bitfld.long 0x0 1. "SICC,Start inserted group channel conversion" "0,1"
|
|
bitfld.long 0x0 0. "FLTEN,HPDF_FLTy enable" "0,1"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "FLT2CTL0,Filter 2 control register"
|
|
bitfld.long 0x0 30. "TMFM,Threshold monitor fast mode" "0,1"
|
|
bitfld.long 0x0 29. "FAST,Fast conversion mode for regular conversions" "0,1"
|
|
bitfld.long 0x0 24.--26. "RCS,Regular conversion channel selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 21. "RCDMAEN,DMA channel enabled to read data for the regular conversion" "0,1"
|
|
bitfld.long 0x0 19. "RCSYN,Regular conversion synchronously with HPDF_FLT0" "0,1"
|
|
bitfld.long 0x0 18. "RCCM,Regular conversions continuous mode" "0,1"
|
|
bitfld.long 0x0 17. "SRCS,Start regular channel conversion by software" "0,1"
|
|
bitfld.long 0x0 13.--14. "ICTEEN,Inserted conversions trigger edge enable" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "ICTSSEL,Inserted conversions trigger signal selection"
|
|
newline
|
|
bitfld.long 0x0 5. "ICDMAEN,DMA channel enabled to read data for the inserted channel group" "0,1"
|
|
bitfld.long 0x0 4. "SCMOD,Scan conversion mode of inserted conversions" "0,1"
|
|
bitfld.long 0x0 3. "ICSYN,Inserted conversion synchronously with the HPDF_FLT0 SICC trigger" "0,1"
|
|
bitfld.long 0x0 1. "SICC,Start inserted group channel conversion" "0,1"
|
|
bitfld.long 0x0 0. "FLTEN,HPDF_FLTy enable" "0,1"
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "FLT3CTL0,Filter 3 control register"
|
|
bitfld.long 0x0 30. "TMFM,Threshold monitor fast mode" "0,1"
|
|
bitfld.long 0x0 29. "FAST,Fast conversion mode for regular conversions" "0,1"
|
|
bitfld.long 0x0 24.--26. "RCS,Regular conversion channel selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 21. "RCDMAEN,DMA channel enabled to read data for the regular conversion" "0,1"
|
|
bitfld.long 0x0 19. "RCSYN,Regular conversion synchronously with HPDF_FLT0" "0,1"
|
|
bitfld.long 0x0 18. "RCCM,Regular conversions continuous mode" "0,1"
|
|
bitfld.long 0x0 17. "SRCS,Start regular channel conversion by software" "0,1"
|
|
bitfld.long 0x0 13.--14. "ICTEEN,Inserted conversions trigger edge enable" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "ICTSSEL,Inserted conversions trigger signal selection"
|
|
newline
|
|
bitfld.long 0x0 5. "ICDMAEN,DMA channel enabled to read data for the inserted channel group" "0,1"
|
|
bitfld.long 0x0 4. "SCMOD,Scan conversion mode of inserted conversions" "0,1"
|
|
bitfld.long 0x0 3. "ICSYN,Inserted conversion synchronously with the HPDF_FLT0 SICC trigger" "0,1"
|
|
bitfld.long 0x0 1. "SICC,Start inserted group channel conversion" "0,1"
|
|
bitfld.long 0x0 0. "FLTEN,HPDF_FLTy enable" "0,1"
|
|
group.long 0x104++0x3
|
|
line.long 0x0 "FLT0CTL1,Filter 0 control register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TMCHEN,Threshold monitor channel enable"
|
|
hexmask.long.byte 0x0 8.--15. 1. "EMCS,Extremes monitor channel selection"
|
|
bitfld.long 0x0 6. "CKLIE,Clock loss interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "MMIE,Malfunction monitor interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "TMIE,Threshold monitor interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "RCDOIE,Regular conversion data overflow interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "ICDOIE,Inserted conversion data overflow interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "RCEIE,Regular conversion end interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "ICEIE,Inserted conversion end interrupt enable" "0,1"
|
|
group.long 0x184++0x3
|
|
line.long 0x0 "FLT1CTL1,Filter 1 control register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TMCHEN,Threshold monitor channel enable"
|
|
hexmask.long.byte 0x0 8.--15. 1. "EMCS,Extremes monitor channel selection"
|
|
bitfld.long 0x0 6. "CKLIE,Clock loss interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "MMIE,Malfunction monitor interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "TMIE,Threshold monitor interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "RCDOIE,Regular conversion data overflow interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "ICDOIE,Inserted conversion data overflow interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "RCEIE,Regular conversion end interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "ICEIE,Inserted conversion end interrupt enable" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLT2CTL1,Filter 2 control register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TMCHEN,Threshold monitor channel enable"
|
|
hexmask.long.byte 0x0 8.--15. 1. "EMCS,Extremes monitor channel selection"
|
|
bitfld.long 0x0 6. "CKLIE,Clock loss interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "MMIE,Malfunction monitor interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "TMIE,Threshold monitor interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "RCDOIE,Regular conversion data overflow interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "ICDOIE,Inserted conversion data overflow interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "RCEIE,Regular conversion end interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "ICEIE,Inserted conversion end interrupt enable" "0,1"
|
|
group.long 0x284++0x3
|
|
line.long 0x0 "FLT3CTL1,Filter 2 control register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TMCHEN,Threshold monitor channel enable"
|
|
hexmask.long.byte 0x0 8.--15. 1. "EMCS,Extremes monitor channel selection"
|
|
bitfld.long 0x0 6. "CKLIE,Clock loss interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "MMIE,Malfunction monitor interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "TMIE,Threshold monitor interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "RCDOIE,Regular conversion data overflow interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "ICDOIE,Inserted conversion data overflow interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "RCEIE,Regular conversion end interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "ICEIE,Inserted conversion end interrupt enable" "0,1"
|
|
rgroup.long 0x108++0x3
|
|
line.long 0x0 "FLT0STAT,Filter 0 status regist"
|
|
hexmask.long.byte 0x0 24.--31. 1. "MMF,Malfunction monitor flag"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CKLF,Clock loss flag"
|
|
bitfld.long 0x0 14. "RCPF,Regular conversion in progress flag" "0,1"
|
|
bitfld.long 0x0 13. "ICPF,Inserted conversion in progress flag" "0,1"
|
|
bitfld.long 0x0 4. "TMEOF,Threshold monitor event occurred flag" "0,1"
|
|
bitfld.long 0x0 3. "RCDOF,Regular conversion data overflow flag" "0,1"
|
|
bitfld.long 0x0 2. "ICDOF,Inserted conversion data overflow flag" "0,1"
|
|
bitfld.long 0x0 1. "RCEF,Regular conversion end flag" "0,1"
|
|
bitfld.long 0x0 0. "ICEF,Inserted conversion end flag" "0,1"
|
|
rgroup.long 0x188++0x3
|
|
line.long 0x0 "FLT1STAT,Filter 1 status regist"
|
|
hexmask.long.byte 0x0 24.--31. 1. "MMF,Malfunction monitor flag"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CKLF,Clock loss flag"
|
|
bitfld.long 0x0 14. "RCPF,Regular conversion in progress flag" "0,1"
|
|
bitfld.long 0x0 13. "ICPF,Inserted conversion in progress flag" "0,1"
|
|
bitfld.long 0x0 4. "TMEOF,Threshold monitor event occurred flag" "0,1"
|
|
bitfld.long 0x0 3. "RCDOF,Regular conversion data overflow flag" "0,1"
|
|
bitfld.long 0x0 2. "ICDOF,Inserted conversion data overflow flag" "0,1"
|
|
bitfld.long 0x0 1. "RCEF,Regular conversion end flag" "0,1"
|
|
bitfld.long 0x0 0. "ICEF,Inserted conversion end flag" "0,1"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x0 "FLT2STAT,Filter 2 status regist"
|
|
hexmask.long.byte 0x0 24.--31. 1. "MMF,Malfunction monitor flag"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CKLF,Clock loss flag"
|
|
bitfld.long 0x0 14. "RCPF,Regular conversion in progress flag" "0,1"
|
|
bitfld.long 0x0 13. "ICPF,Inserted conversion in progress flag" "0,1"
|
|
bitfld.long 0x0 4. "TMEOF,Threshold monitor event occurred flag" "0,1"
|
|
bitfld.long 0x0 3. "RCDOF,Regular conversion data overflow flag" "0,1"
|
|
bitfld.long 0x0 2. "ICDOF,Inserted conversion data overflow flag" "0,1"
|
|
bitfld.long 0x0 1. "RCEF,Regular conversion end flag" "0,1"
|
|
bitfld.long 0x0 0. "ICEF,Inserted conversion end flag" "0,1"
|
|
rgroup.long 0x288++0x3
|
|
line.long 0x0 "FLT3STAT,Filter 3 status regist"
|
|
hexmask.long.byte 0x0 24.--31. 1. "MMF,Malfunction monitor flag"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CKLF,Clock loss flag"
|
|
bitfld.long 0x0 14. "RCPF,Regular conversion in progress flag" "0,1"
|
|
bitfld.long 0x0 13. "ICPF,Inserted conversion in progress flag" "0,1"
|
|
bitfld.long 0x0 4. "TMEOF,Threshold monitor event occurred flag" "0,1"
|
|
bitfld.long 0x0 3. "RCDOF,Regular conversion data overflow flag" "0,1"
|
|
bitfld.long 0x0 2. "ICDOF,Inserted conversion data overflow flag" "0,1"
|
|
bitfld.long 0x0 1. "RCEF,Regular conversion end flag" "0,1"
|
|
bitfld.long 0x0 0. "ICEF,Inserted conversion end flag" "0,1"
|
|
group.long 0x10C++0x3
|
|
line.long 0x0 "FLT0INTC,Filter 0 interrupt flag clear regist"
|
|
hexmask.long.byte 0x0 24.--31. 1. "MMFC,Clear the malfunction monitor flag"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CKLFC,Clear the clock loss flag"
|
|
bitfld.long 0x0 3. "RCDOFC,Clear the regular conversion data overflow flag" "0,1"
|
|
bitfld.long 0x0 2. "ICDOFC,Clear the inserted conversion data overflow flag" "0,1"
|
|
group.long 0x18C++0x3
|
|
line.long 0x0 "FLT1INTC,Filter 1 interrupt flag clear regist"
|
|
hexmask.long.byte 0x0 24.--31. 1. "MMFC,Clear the malfunction monitor flag"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CKLFC,Clear the clock loss flag"
|
|
bitfld.long 0x0 3. "RCDOFC,Clear the regular conversion data overflow flag" "0,1"
|
|
bitfld.long 0x0 2. "ICDOFC,Clear the inserted conversion data overflow flag" "0,1"
|
|
group.long 0x20C++0x3
|
|
line.long 0x0 "FLT2INTC,Filter 2 interrupt flag clear regist"
|
|
hexmask.long.byte 0x0 24.--31. 1. "MMFC,Clear the malfunction monitor flag"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CKLFC,Clear the clock loss flag"
|
|
bitfld.long 0x0 3. "RCDOFC,Clear the regular conversion data overflow flag" "0,1"
|
|
bitfld.long 0x0 2. "ICDOFC,Clear the inserted conversion data overflow flag" "0,1"
|
|
group.long 0x28C++0x3
|
|
line.long 0x0 "FLT3INTC,Filter 3 interrupt flag clear regist"
|
|
hexmask.long.byte 0x0 24.--31. 1. "MMFC,Clear the malfunction monitor flag"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CKLFC,Clear the clock loss flag"
|
|
bitfld.long 0x0 3. "RCDOFC,Clear the regular conversion data overflow flag" "0,1"
|
|
bitfld.long 0x0 2. "ICDOFC,Clear the inserted conversion data overflow flag" "0,1"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "FLT0ICGS,Filter 0 inserted channel group selection regist"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ICGSEL,Inserted channel group selection"
|
|
group.long 0x190++0x3
|
|
line.long 0x0 "FLT1ICGS,Filter 1 inserted channel group selection regist"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ICGSEL,Inserted channel group selection"
|
|
group.long 0x210++0x3
|
|
line.long 0x0 "FLT2ICGS,Filter 2 inserted channel group selection regist"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ICGSEL,Inserted channel group selection"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "FLT3ICGS,Filter 3 inserted channel group selection regist"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ICGSEL,Inserted channel group selection"
|
|
group.long 0x114++0x3
|
|
line.long 0x0 "FLT0SFCFG,Filter 0 sinc filter configuration regist"
|
|
bitfld.long 0x0 29.--31. "SFO,Sinc filter order" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 16.--25. 1. "SFOR,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IOR,Integrator oversampling ratio"
|
|
group.long 0x194++0x3
|
|
line.long 0x0 "FLT1SFCFG,Filter 1 sinc filter configuration regist"
|
|
bitfld.long 0x0 29.--31. "SFO,Sinc filter order" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 16.--25. 1. "SFOR,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IOR,Integrator oversampling ratio"
|
|
group.long 0x214++0x3
|
|
line.long 0x0 "FLT2SFCFG,Filter 2 sinc filter configuration regist"
|
|
bitfld.long 0x0 29.--31. "SFO,Sinc filter order" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 16.--25. 1. "SFOR,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IOR,Integrator oversampling ratio"
|
|
group.long 0x294++0x3
|
|
line.long 0x0 "FLT3SFCFG,Filter 3 sinc filter configuration regist"
|
|
bitfld.long 0x0 29.--31. "SFO,Sinc filter order" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 16.--25. 1. "SFOR,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IOR,Integrator oversampling ratio"
|
|
rgroup.long 0x118++0x3
|
|
line.long 0x0 "FLT0IDATA,Filter 0 inserted group conversion data regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "IDATA,Inserted group conversion data"
|
|
bitfld.long 0x0 0.--2. "ICCH,Inserted channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x198++0x3
|
|
line.long 0x0 "FLT1IDATA,Filter 1 inserted group conversion data regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "IDATA,Inserted group conversion data"
|
|
bitfld.long 0x0 0.--2. "ICCH,Inserted channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLT2IDATA,Filter 2 inserted group conversion data regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "IDATA,Inserted group conversion data"
|
|
bitfld.long 0x0 0.--2. "ICCH,Inserted channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x298++0x3
|
|
line.long 0x0 "FLT3IDATA,Filter 3 inserted group conversion data regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "IDATA,Inserted group conversion data"
|
|
bitfld.long 0x0 0.--2. "ICCH,Inserted channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x0 "FLT0RDATA,Filter 0 regular channel conversion data regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RDATA,Regular channel conversion data"
|
|
bitfld.long 0x0 4. "RCHPDT,Regular channel pending data" "0,1"
|
|
bitfld.long 0x0 0.--2. "RCCH,Regular channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x0 "FLT1RDATA,Filter 1 regular channel conversion data regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RDATA,Regular channel conversion data"
|
|
bitfld.long 0x0 4. "RCHPDT,Regular channel pending data" "0,1"
|
|
bitfld.long 0x0 0.--2. "RCCH,Regular channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLT2RDATA,Filter 0 regular channel conversion data regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RDATA,Regular channel conversion data"
|
|
bitfld.long 0x0 4. "RCHPDT,Regular channel pending data" "0,1"
|
|
bitfld.long 0x0 0.--2. "RCCH,Regular channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x29C++0x3
|
|
line.long 0x0 "FLT3RDATA,Filter 3 regular channel conversion data regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RDATA,Regular channel conversion data"
|
|
bitfld.long 0x0 4. "RCHPDT,Regular channel pending data" "0,1"
|
|
bitfld.long 0x0 0.--2. "RCCH,Regular channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "FLT0TMHT,Filter 0 threshold monitor high threshold regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "HTVAL,Threshold monitor high threshold value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "HTBSD,High threshold event break signal distribution"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x0 "FLT1TMHT,Filter 1 threshold monitor high threshold regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "HTVAL,Threshold monitor high threshold value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "HTBSD,High threshold event break signal distribution"
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "FLT2TMHT,Filter 2 threshold monitor high threshold regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "HTVAL,Threshold monitor high threshold value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "HTBSD,High threshold event break signal distribution"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "FLT3TMHT,Filter 3 threshold monitor high threshold regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "HTVAL,Threshold monitor high threshold value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "HTBSD,High threshold event break signal distribution"
|
|
group.long 0x124++0x3
|
|
line.long 0x0 "FLT0TMLT,Filter 0 threshold monitor low threshold regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "LTVAL,Threshold monitor low threshold value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "LTBSD,Low threshold event break signal distribution"
|
|
group.long 0x1A4++0x3
|
|
line.long 0x0 "FLT1TMLT,Filter 1 threshold monitor low threshold regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "LTVAL,Threshold monitor low threshold value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "LTBSD,Low threshold event break signal distribution"
|
|
group.long 0x224++0x3
|
|
line.long 0x0 "FLT2TMLT,Filter 2 threshold monitor low threshold regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "LTVAL,Threshold monitor low threshold value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "LTBSD,Low threshold event break signal distribution"
|
|
group.long 0x2A4++0x3
|
|
line.long 0x0 "FLT3TMLT,Filter 3 threshold monitor low threshold regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "LTVAL,Threshold monitor low threshold value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "LTBSD,Low threshold event break signal distribution"
|
|
rgroup.long 0x128++0x3
|
|
line.long 0x0 "FLT0TMSTAT,Filter 0 threshold monitor status regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "HTF,Threshold monitor high threshold flag"
|
|
hexmask.long.byte 0x0 0.--7. 1. "LTF,Threshold monitor low threshold flag"
|
|
rgroup.long 0x1A8++0x3
|
|
line.long 0x0 "FLT1TMSTAT,Filter 1 threshold monitor status regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "HTF,Threshold monitor high threshold flag"
|
|
hexmask.long.byte 0x0 0.--7. 1. "LTF,Threshold monitor low threshold flag"
|
|
rgroup.long 0x228++0x3
|
|
line.long 0x0 "FLT2TMSTAT,Filter 2 threshold monitor status regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "HTF,Threshold monitor high threshold flag"
|
|
hexmask.long.byte 0x0 0.--7. 1. "LTF,Threshold monitor low threshold flag"
|
|
rgroup.long 0x3A8++0x3
|
|
line.long 0x0 "FLT3TMSTAT,Filter 3 threshold monitor status regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "HTF,Threshold monitor high threshold flag"
|
|
hexmask.long.byte 0x0 0.--7. 1. "LTF,Threshold monitor low threshold flag"
|
|
group.long 0x12C++0x3
|
|
line.long 0x0 "FLT0TMFC,Filter 0 threshold monitor flag clear regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "HTFC,Clear the threshold monitor high threshold flag"
|
|
hexmask.long.byte 0x0 0.--7. 1. "LTFC,Clear the threshold monitor low threshold flag"
|
|
group.long 0x1AC++0x3
|
|
line.long 0x0 "FLT1TMFC,Filter 1 threshold monitor flag clear regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "HTFC,Clear the threshold monitor high threshold flag"
|
|
hexmask.long.byte 0x0 0.--7. 1. "LTFC,Clear the threshold monitor low threshold flag"
|
|
group.long 0x22C++0x3
|
|
line.long 0x0 "FLT2TMFC,Filter 2 threshold monitor flag clear regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "HTFC,Clear the threshold monitor high threshold flag"
|
|
hexmask.long.byte 0x0 0.--7. 1. "LTFC,Clear the threshold monitor low threshold flag"
|
|
group.long 0x2AC++0x3
|
|
line.long 0x0 "FLT3TMFC,Filter 3 threshold monitor flag clear regist"
|
|
hexmask.long.byte 0x0 8.--15. 1. "HTFC,Clear the threshold monitor high threshold flag"
|
|
hexmask.long.byte 0x0 0.--7. 1. "LTFC,Clear the threshold monitor low threshold flag"
|
|
rgroup.long 0x130++0x3
|
|
line.long 0x0 "FLT0EMMAX,Filter 0 extremes monitor maximum regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "MAXVAL,Extremes monitor maximum value"
|
|
bitfld.long 0x0 0.--2. "MAXDC,Extremes monitor maximum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1B0++0x3
|
|
line.long 0x0 "FLT1EMMAX,Filter 1 extremes monitor maximum regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "MAXVAL,Extremes monitor maximum value"
|
|
bitfld.long 0x0 0.--2. "MAXDC,Extremes monitor maximum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x230++0x3
|
|
line.long 0x0 "FLT2EMMAX,Filter 2 extremes monitor maximum regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "MAXVAL,Extremes monitor maximum value"
|
|
bitfld.long 0x0 0.--2. "MAXDC,Extremes monitor maximum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2B0++0x3
|
|
line.long 0x0 "FLT3EMMAX,Filter 3 extremes monitor maximum regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "MAXVAL,Extremes monitor maximum value"
|
|
bitfld.long 0x0 0.--2. "MAXDC,Extremes monitor maximum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x134++0x3
|
|
line.long 0x0 "FLT0EMMIN,Filter 0 extremes monitor minimum regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "MINVAL,Extremes monitor minimum value"
|
|
bitfld.long 0x0 0.--2. "MINDC,Extremes monitor minimum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1B4++0x3
|
|
line.long 0x0 "FLT1EMMIN,Filter 1 extremes monitor minimum regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "MINVAL,Extremes monitor minimum value"
|
|
bitfld.long 0x0 0.--2. "MINDC,Extremes monitor minimum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x234++0x3
|
|
line.long 0x0 "FLT2EMMIN,Filter 2 extremes monitor minimum regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "MINVAL,Extremes monitor minimum value"
|
|
bitfld.long 0x0 0.--2. "MINDC,Extremes monitor minimum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2B4++0x3
|
|
line.long 0x0 "FLT3EMMIN,Filter 3 extremes monitor minimum regist"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "MINVAL,Extremes monitor minimum value"
|
|
bitfld.long 0x0 0.--2. "MINDC,Extremes monitor minimum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x138++0x3
|
|
line.long 0x0 "FLT0CT,Filter 0 conversion timer register"
|
|
hexmask.long 0x0 4.--31. 1. "CTCNT,Extremes monitor minimum value"
|
|
rgroup.long 0x1B8++0x3
|
|
line.long 0x0 "FLT1CT,Filter 1 conversion timer register"
|
|
hexmask.long 0x0 4.--31. 1. "CTCNT,Extremes monitor minimum value"
|
|
rgroup.long 0x238++0x3
|
|
line.long 0x0 "FLT2CT,Filter 2 conversion timer register"
|
|
hexmask.long 0x0 4.--31. 1. "CTCNT,Extremes monitor minimum value"
|
|
rgroup.long 0x2B8++0x3
|
|
line.long 0x0 "FLT3CT,Filter 3 conversion timer register"
|
|
hexmask.long 0x0 4.--31. 1. "CTCNT,Timer counting conversion time"
|
|
tree.end
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
tree "HWSEM (Hardware Semaphore)"
|
|
base ad:0x58026400
|
|
group.long 0x0++0x7F
|
|
line.long 0x0 "WCTL0,Write control register 0"
|
|
bitfld.long 0x0 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PID,Process identification"
|
|
line.long 0x4 "WCTL1,Write control register 1"
|
|
bitfld.long 0x4 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PID,Process identification"
|
|
line.long 0x8 "WCTL2,Write control register 2"
|
|
bitfld.long 0x8 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x8 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PID,Process identification"
|
|
line.long 0xC "WCTL3,Write control register 3"
|
|
bitfld.long 0xC 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0xC 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PID,Process identification"
|
|
line.long 0x10 "WCTL4,Write control register 4"
|
|
bitfld.long 0x10 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x10 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PID,Process identification"
|
|
line.long 0x14 "WCTL5,Write control register 5"
|
|
bitfld.long 0x14 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x14 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PID,Process identification"
|
|
line.long 0x18 "WCTL6,Write control register 6"
|
|
bitfld.long 0x18 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x18 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x18 0.--7. 1. "PID,Process identification"
|
|
line.long 0x1C "WCTL7,Write control register 7"
|
|
bitfld.long 0x1C 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x1C 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PID,Process identification"
|
|
line.long 0x20 "WCTL8,Write control register 8"
|
|
bitfld.long 0x20 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x20 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x20 0.--7. 1. "PID,Process identification"
|
|
line.long 0x24 "WCTL9,Write control register 9"
|
|
bitfld.long 0x24 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x24 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x24 0.--7. 1. "PID,Process identification"
|
|
line.long 0x28 "WCTL10,Write control register 10"
|
|
bitfld.long 0x28 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x28 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x28 0.--7. 1. "PID,Process identification"
|
|
line.long 0x2C "WCTL11,Write control register 11"
|
|
bitfld.long 0x2C 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x2C 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "PID,Process identification"
|
|
line.long 0x30 "WCTL12,Write control register 12"
|
|
bitfld.long 0x30 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x30 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x30 0.--7. 1. "PID,Process identification"
|
|
line.long 0x34 "WCTL13,Write control register 13"
|
|
bitfld.long 0x34 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x34 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x34 0.--7. 1. "PID,Process identification"
|
|
line.long 0x38 "WCTL14,Write control register 14"
|
|
bitfld.long 0x38 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x38 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x38 0.--7. 1. "PID,Process identification"
|
|
line.long 0x3C "WCTL15,Write control register 15"
|
|
bitfld.long 0x3C 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x3C 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "PID,Process identification"
|
|
line.long 0x40 "WCTL16,Write control register 16"
|
|
bitfld.long 0x40 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x40 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x40 0.--7. 1. "PID,Process identification"
|
|
line.long 0x44 "WCTL17,Write control register 17"
|
|
bitfld.long 0x44 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x44 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x44 0.--7. 1. "PID,Process identification"
|
|
line.long 0x48 "WCTL18,Write control register 18"
|
|
bitfld.long 0x48 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x48 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x48 0.--7. 1. "PID,Process identification"
|
|
line.long 0x4C "WCTL19,Write control register 19"
|
|
bitfld.long 0x4C 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x4C 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x4C 0.--7. 1. "PID,Process identification"
|
|
line.long 0x50 "WCTL20,Write control register 20"
|
|
bitfld.long 0x50 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x50 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x50 0.--7. 1. "PID,Process identification"
|
|
line.long 0x54 "WCTL21,Write control register 21"
|
|
bitfld.long 0x54 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x54 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x54 0.--7. 1. "PID,Process identification"
|
|
line.long 0x58 "WCTL22,Write control register 22"
|
|
bitfld.long 0x58 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x58 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x58 0.--7. 1. "PID,Process identification"
|
|
line.long 0x5C "WCTL23,Write control register 23"
|
|
bitfld.long 0x5C 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x5C 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x5C 0.--7. 1. "PID,Process identification"
|
|
line.long 0x60 "WCTL24,Write control register 24"
|
|
bitfld.long 0x60 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x60 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x60 0.--7. 1. "PID,Process identification"
|
|
line.long 0x64 "WCTL25,Write control register 25"
|
|
bitfld.long 0x64 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x64 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x64 0.--7. 1. "PID,Process identification"
|
|
line.long 0x68 "WCTL26,Write control register 26"
|
|
bitfld.long 0x68 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x68 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x68 0.--7. 1. "PID,Process identification"
|
|
line.long 0x6C "WCTL27,Write control register 27"
|
|
bitfld.long 0x6C 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x6C 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x6C 0.--7. 1. "PID,Process identification"
|
|
line.long 0x70 "WCTL28,Write control register 28"
|
|
bitfld.long 0x70 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x70 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x70 0.--7. 1. "PID,Process identification"
|
|
line.long 0x74 "WCTL29,Write control register 29"
|
|
bitfld.long 0x74 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x74 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x74 0.--7. 1. "PID,Process identification"
|
|
line.long 0x78 "WCTL30,Write control register 30"
|
|
bitfld.long 0x78 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x78 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x78 0.--7. 1. "PID,Process identification"
|
|
line.long 0x7C "WCTL31,Write control register 31"
|
|
bitfld.long 0x7C 31. "LK,Lock semaphore by writing" "0,1"
|
|
hexmask.long.byte 0x7C 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x7C 0.--7. 1. "PID,Process identification"
|
|
rgroup.long 0x80++0x7F
|
|
line.long 0x0 "RLK0,Read lock regist 0"
|
|
bitfld.long 0x0 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PID,Process identification"
|
|
line.long 0x4 "RLK1,Read lock regist 1"
|
|
bitfld.long 0x4 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PID,Process identification"
|
|
line.long 0x8 "RLK2,Read lock regist 2"
|
|
bitfld.long 0x8 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x8 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PID,Process identification"
|
|
line.long 0xC "RLK3,Read lock regist 3"
|
|
bitfld.long 0xC 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0xC 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PID,Process identification"
|
|
line.long 0x10 "RLK4,Read lock regist 4"
|
|
bitfld.long 0x10 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x10 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PID,Process identification"
|
|
line.long 0x14 "RLK5,Read lock regist 5"
|
|
bitfld.long 0x14 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x14 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PID,Process identification"
|
|
line.long 0x18 "RLK6,Read lock regist 6"
|
|
bitfld.long 0x18 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x18 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x18 0.--7. 1. "PID,Process identification"
|
|
line.long 0x1C "RLK7,Read lock regist 7"
|
|
bitfld.long 0x1C 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x1C 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PID,Process identification"
|
|
line.long 0x20 "RLK8,Read lock regist 8"
|
|
bitfld.long 0x20 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x20 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x20 0.--7. 1. "PID,Process identification"
|
|
line.long 0x24 "RLK9,Read lock regist 9"
|
|
bitfld.long 0x24 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x24 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x24 0.--7. 1. "PID,Process identification"
|
|
line.long 0x28 "RLK10,Read lock regist 10"
|
|
bitfld.long 0x28 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x28 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x28 0.--7. 1. "PID,Process identification"
|
|
line.long 0x2C "RLK11,Read lock regist 11"
|
|
bitfld.long 0x2C 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x2C 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "PID,Process identification"
|
|
line.long 0x30 "RLK12,Read lock regist 12"
|
|
bitfld.long 0x30 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x30 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x30 0.--7. 1. "PID,Process identification"
|
|
line.long 0x34 "RLK13,Read lock regist 13"
|
|
bitfld.long 0x34 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x34 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x34 0.--7. 1. "PID,Process identification"
|
|
line.long 0x38 "RLK14,Read lock regist 14"
|
|
bitfld.long 0x38 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x38 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x38 0.--7. 1. "PID,Process identification"
|
|
line.long 0x3C "RLK15,Read lock regist 15"
|
|
bitfld.long 0x3C 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x3C 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "PID,Process identification"
|
|
line.long 0x40 "RLK16,Read lock regist 16"
|
|
bitfld.long 0x40 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x40 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x40 0.--7. 1. "PID,Process identification"
|
|
line.long 0x44 "RLK17,Read lock regist 17"
|
|
bitfld.long 0x44 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x44 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x44 0.--7. 1. "PID,Process identification"
|
|
line.long 0x48 "RLK18,Read lock regist 18"
|
|
bitfld.long 0x48 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x48 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x48 0.--7. 1. "PID,Process identification"
|
|
line.long 0x4C "RLK19,Read lock regist 19"
|
|
bitfld.long 0x4C 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x4C 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x4C 0.--7. 1. "PID,Process identification"
|
|
line.long 0x50 "RLK20,Read lock regist 20"
|
|
bitfld.long 0x50 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x50 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x50 0.--7. 1. "PID,Process identification"
|
|
line.long 0x54 "RLK21,Read lock regist 21"
|
|
bitfld.long 0x54 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x54 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x54 0.--7. 1. "PID,Process identification"
|
|
line.long 0x58 "RLK22,Read lock regist 22"
|
|
bitfld.long 0x58 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x58 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x58 0.--7. 1. "PID,Process identification"
|
|
line.long 0x5C "RLK23,Read lock regist 23"
|
|
bitfld.long 0x5C 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x5C 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x5C 0.--7. 1. "PID,Process identification"
|
|
line.long 0x60 "RLK24,Read lock regist 24"
|
|
bitfld.long 0x60 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x60 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x60 0.--7. 1. "PID,Process identification"
|
|
line.long 0x64 "RLK25,Read lock regist 25"
|
|
bitfld.long 0x64 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x64 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x64 0.--7. 1. "PID,Process identification"
|
|
line.long 0x68 "RLK26,Read lock regist 26"
|
|
bitfld.long 0x68 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x68 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x68 0.--7. 1. "PID,Process identification"
|
|
line.long 0x6C "RLK27,Read lock regist 27"
|
|
bitfld.long 0x6C 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x6C 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x6C 0.--7. 1. "PID,Process identification"
|
|
line.long 0x70 "RLK28,Read lock regist 28"
|
|
bitfld.long 0x70 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x70 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x70 0.--7. 1. "PID,Process identification"
|
|
line.long 0x74 "RLK29,Read lock regist 29"
|
|
bitfld.long 0x74 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x74 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x74 0.--7. 1. "PID,Process identification"
|
|
line.long 0x78 "RLK30,Read lock regist 30"
|
|
bitfld.long 0x78 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x78 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x78 0.--7. 1. "PID,Process identification"
|
|
line.long 0x7C "RLK31,Read lock regist 31"
|
|
bitfld.long 0x7C 31. "LK,Lock semaphore by reading" "0,1"
|
|
hexmask.long.byte 0x7C 8.--11. 1. "MID,Bus master identification"
|
|
hexmask.long.byte 0x7C 0.--7. 1. "PID,Process identification"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "INTEN,Interrupt enable register"
|
|
hexmask.long 0x0 0.--31. 1. "SIE,Semaphore interrupt enable bit"
|
|
wgroup.long 0x104++0x3
|
|
line.long 0x0 "INTC,Interrupt flag clear register"
|
|
hexmask.long 0x0 0.--31. 1. "SIFC,Semaphore interrupt flag clear bit"
|
|
rgroup.long 0x108++0x7
|
|
line.long 0x0 "STAT,Status register"
|
|
hexmask.long 0x0 0.--31. 1. "SF,Semaphore status"
|
|
line.long 0x4 "INTF,Interrupt flag register"
|
|
hexmask.long 0x4 0.--31. 1. "SIF,Semaphore interrupt flag status"
|
|
group.long 0x140++0x7
|
|
line.long 0x0 "UNLK,Unlock register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key value"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MID,Bus master identification to clear"
|
|
line.long 0x4 "KEY,Key register"
|
|
hexmask.long.word 0x4 16.--31. 1. "KEY,Key for unlocking all semaphores of a bus master"
|
|
tree.end
|
|
endif
|
|
tree "I2C (Inter-Integrated Circuit Interface)"
|
|
base ad:0x0
|
|
tree "I2C0"
|
|
base ad:0x40005400
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 23. "PECEN,PEC Calculation Switch" "0,1"
|
|
bitfld.long 0x0 22. "SMBALTEN,SMBus Alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDAEN,SMBus device default address enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBHAEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,Whether or not to response to a General Call" "0,1"
|
|
bitfld.long 0x0 18. "WUEN,Wakeup from Deep-sleep mode enable" "0,1"
|
|
bitfld.long 0x0 17. "SS,Whether to stretch SCL low when data is not ready in slave mode" "0,1"
|
|
bitfld.long 0x0 16. "SBCTL,Slave byte control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DENR,DMA enable for reception" "0,1"
|
|
bitfld.long 0x0 14. "DENT,DMA enable for transmission" "0,1"
|
|
bitfld.long 0x0 12. "ANOFF,Analog noise filter disable" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "STPDETIE,Stop detection interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDMIE,Address match interrupt enable in slave mode" "0,1"
|
|
bitfld.long 0x0 2. "RBNEIE,Receive interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "TIE,Receive interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "I2CEN,I2C peripheral enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 26. "PECTRANS,PEC Transfer" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode in master mode" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,Reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BYTENUM,Number of bytes to be transferred"
|
|
bitfld.long 0x4 15. "NACKEN,Generate NACK in slave mode" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Generate a STOP condition on I2C bus" "0,1"
|
|
bitfld.long 0x4 13. "START,Generate a START condition on I2C bus" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header executes read direction only in master receive mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10EN,10-bit addressing mode enable in master mode" "0,1"
|
|
bitfld.long 0x4 10. "TRDIR,Transfer direction in master mode" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADDRESS,Slave address to be sent"
|
|
line.long 0x8 "SADDR0,Slave address register 0"
|
|
bitfld.long 0x8 15. "ADDRESSEN,I2C address enable" "0,1"
|
|
bitfld.long 0x8 10. "ADDFORMAT,Address mode for the I2C slave" "0,1"
|
|
bitfld.long 0x8 8.--9. "ADDRESS_8_9,7-bit address or bits 7:1 of a 10-bit address" "0,1,2,3"
|
|
hexmask.long.byte 0x8 1.--7. 1. "ADDRESS_1_7,Highest two bits of a 10-bit address"
|
|
bitfld.long 0x8 0. "ADDRESS_0,Bit 0 of a 10-bit address" "0,1"
|
|
line.long 0xC "SADDR1,Slave address register 1"
|
|
bitfld.long 0xC 15. "ADDRESS2EN,Second I2C address enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "ADDMSK2,ADDRESS2[7:1] mask" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "ADDRESS2,Second I2C address for the slave"
|
|
line.long 0x10 "TIMING,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PSC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDELY,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADELY,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period"
|
|
line.long 0x14 "TIMEOUT,timeout register"
|
|
bitfld.long 0x14 31. "EXTOEN,Extended clock timeout detection enable" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "BUSTOB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TOEN,Clock timeout detection enable" "0,1"
|
|
bitfld.long 0x14 12. "TOIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "BUSTOA,Bus timeout A"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "STAT,Transfer status register"
|
|
hexmask.long.byte 0x0 17.--23. 1. "READDR,Received match address in slave mode"
|
|
bitfld.long 0x0 16. "TR,Whether the I2C is a transmitter or a receiver in slave mode" "0,1"
|
|
bitfld.long 0x0 15. "I2CBSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 13. "SMBALT,SMBus Alert" "0,1"
|
|
bitfld.long 0x0 12. "TIMEOUT,TIMEOUT flag" "0,1"
|
|
bitfld.long 0x0 11. "PECERR,PEC error" "0,1"
|
|
bitfld.long 0x0 10. "OUERR,Overrun/Underrun error in slave mode" "0,1"
|
|
bitfld.long 0x0 9. "LOSTARB,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BERR,Bus error" "0,1"
|
|
bitfld.long 0x0 7. "TCR,Transfer complete reload" "0,1"
|
|
bitfld.long 0x0 6. "TC,Transfer complete in master mode" "0,1"
|
|
bitfld.long 0x0 5. "STPDET,STOP condition is detected on the bus" "0,1"
|
|
bitfld.long 0x0 4. "NACK,Not Acknowledge flag" "0,1"
|
|
bitfld.long 0x0 3. "ADDSEND,Address received matches in slave mode" "0,1"
|
|
bitfld.long 0x0 2. "RBNE,I2C_RDATA is not empty during receiving" "0,1"
|
|
bitfld.long 0x0 1. "TI,Transmit interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TBE,I2C_TDATA is empty during transmitting" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "STATC,Status clear register"
|
|
bitfld.long 0x0 13. "SMBALTC,SMBus Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMEOUTC,TIMEOUT flag clear" "0,1"
|
|
bitfld.long 0x0 11. "PECERRC,PEC error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OUERRC,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x0 9. "LOSTARBC,Arbitration Lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRC,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STPDETC,STPDET flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKC,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDSENDC,ADDSEND flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PEC,Packet Error Check register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PECV,Packet Error Checking Value"
|
|
line.long 0x4 "RDATA,receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RDATA,Receive data value"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TDATA,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TDATA,Transmit data value"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "CTL2,Control register 2"
|
|
hexmask.long.byte 0x0 9.--15. 1. "ADDM,Defines which bits of ADDRESS"
|
|
tree.end
|
|
tree "I2C1"
|
|
base ad:0x40005800
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 23. "PECEN,PEC Calculation Switch" "0,1"
|
|
bitfld.long 0x0 22. "SMBALTEN,SMBus Alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDAEN,SMBus device default address enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBHAEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,Whether or not to response to a General Call" "0,1"
|
|
bitfld.long 0x0 18. "WUEN,Wakeup from Deep-sleep mode enable" "0,1"
|
|
bitfld.long 0x0 17. "SS,Whether to stretch SCL low when data is not ready in slave mode" "0,1"
|
|
bitfld.long 0x0 16. "SBCTL,Slave byte control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DENR,DMA enable for reception" "0,1"
|
|
bitfld.long 0x0 14. "DENT,DMA enable for transmission" "0,1"
|
|
bitfld.long 0x0 12. "ANOFF,Analog noise filter disable" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "STPDETIE,Stop detection interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDMIE,Address match interrupt enable in slave mode" "0,1"
|
|
bitfld.long 0x0 2. "RBNEIE,Receive interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "TIE,Receive interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "I2CEN,I2C peripheral enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 26. "PECTRANS,PEC Transfer" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode in master mode" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,Reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BYTENUM,Number of bytes to be transferred"
|
|
bitfld.long 0x4 15. "NACKEN,Generate NACK in slave mode" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Generate a STOP condition on I2C bus" "0,1"
|
|
bitfld.long 0x4 13. "START,Generate a START condition on I2C bus" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header executes read direction only in master receive mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10EN,10-bit addressing mode enable in master mode" "0,1"
|
|
bitfld.long 0x4 10. "TRDIR,Transfer direction in master mode" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADDRESS,Slave address to be sent"
|
|
line.long 0x8 "SADDR0,Slave address register 0"
|
|
bitfld.long 0x8 15. "ADDRESSEN,I2C address enable" "0,1"
|
|
bitfld.long 0x8 10. "ADDFORMAT,Address mode for the I2C slave" "0,1"
|
|
bitfld.long 0x8 8.--9. "ADDRESS_8_9,7-bit address or bits 7:1 of a 10-bit address" "0,1,2,3"
|
|
hexmask.long.byte 0x8 1.--7. 1. "ADDRESS_1_7,Highest two bits of a 10-bit address"
|
|
bitfld.long 0x8 0. "ADDRESS_0,Bit 0 of a 10-bit address" "0,1"
|
|
line.long 0xC "SADDR1,Slave address register 1"
|
|
bitfld.long 0xC 15. "ADDRESS2EN,Second I2C address enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "ADDMSK2,ADDRESS2[7:1] mask" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "ADDRESS2,Second I2C address for the slave"
|
|
line.long 0x10 "TIMING,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PSC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDELY,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADELY,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period"
|
|
line.long 0x14 "TIMEOUT,timeout register"
|
|
bitfld.long 0x14 31. "EXTOEN,Extended clock timeout detection enable" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "BUSTOB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TOEN,Clock timeout detection enable" "0,1"
|
|
bitfld.long 0x14 12. "TOIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "BUSTOA,Bus timeout A"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "STAT,Transfer status register"
|
|
hexmask.long.byte 0x0 17.--23. 1. "READDR,Received match address in slave mode"
|
|
bitfld.long 0x0 16. "TR,Whether the I2C is a transmitter or a receiver in slave mode" "0,1"
|
|
bitfld.long 0x0 15. "I2CBSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 13. "SMBALT,SMBus Alert" "0,1"
|
|
bitfld.long 0x0 12. "TIMEOUT,TIMEOUT flag" "0,1"
|
|
bitfld.long 0x0 11. "PECERR,PEC error" "0,1"
|
|
bitfld.long 0x0 10. "OUERR,Overrun/Underrun error in slave mode" "0,1"
|
|
bitfld.long 0x0 9. "LOSTARB,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BERR,Bus error" "0,1"
|
|
bitfld.long 0x0 7. "TCR,Transfer complete reload" "0,1"
|
|
bitfld.long 0x0 6. "TC,Transfer complete in master mode" "0,1"
|
|
bitfld.long 0x0 5. "STPDET,STOP condition is detected on the bus" "0,1"
|
|
bitfld.long 0x0 4. "NACK,Not Acknowledge flag" "0,1"
|
|
bitfld.long 0x0 3. "ADDSEND,Address received matches in slave mode" "0,1"
|
|
bitfld.long 0x0 2. "RBNE,I2C_RDATA is not empty during receiving" "0,1"
|
|
bitfld.long 0x0 1. "TI,Transmit interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TBE,I2C_TDATA is empty during transmitting" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "STATC,Status clear register"
|
|
bitfld.long 0x0 13. "SMBALTC,SMBus Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMEOUTC,TIMEOUT flag clear" "0,1"
|
|
bitfld.long 0x0 11. "PECERRC,PEC error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OUERRC,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x0 9. "LOSTARBC,Arbitration Lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRC,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STPDETC,STPDET flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKC,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDSENDC,ADDSEND flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PEC,Packet Error Check register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PECV,Packet Error Checking Value"
|
|
line.long 0x4 "RDATA,receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RDATA,Receive data value"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TDATA,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TDATA,Transmit data value"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "CTL2,Control register 2"
|
|
hexmask.long.byte 0x0 9.--15. 1. "ADDM,Defines which bits of ADDRESS"
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x4000C000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 23. "PECEN,PEC Calculation Switch" "0,1"
|
|
bitfld.long 0x0 22. "SMBALTEN,SMBus Alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDAEN,SMBus device default address enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBHAEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,Whether or not to response to a General Call" "0,1"
|
|
bitfld.long 0x0 18. "WUEN,Wakeup from Deep-sleep mode enable" "0,1"
|
|
bitfld.long 0x0 17. "SS,Whether to stretch SCL low when data is not ready in slave mode" "0,1"
|
|
bitfld.long 0x0 16. "SBCTL,Slave byte control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DENR,DMA enable for reception" "0,1"
|
|
bitfld.long 0x0 14. "DENT,DMA enable for transmission" "0,1"
|
|
bitfld.long 0x0 12. "ANOFF,Analog noise filter disable" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "STPDETIE,Stop detection interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDMIE,Address match interrupt enable in slave mode" "0,1"
|
|
bitfld.long 0x0 2. "RBNEIE,Receive interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "TIE,Receive interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "I2CEN,I2C peripheral enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 26. "PECTRANS,PEC Transfer" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode in master mode" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,Reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BYTENUM,Number of bytes to be transferred"
|
|
bitfld.long 0x4 15. "NACKEN,Generate NACK in slave mode" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Generate a STOP condition on I2C bus" "0,1"
|
|
bitfld.long 0x4 13. "START,Generate a START condition on I2C bus" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header executes read direction only in master receive mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10EN,10-bit addressing mode enable in master mode" "0,1"
|
|
bitfld.long 0x4 10. "TRDIR,Transfer direction in master mode" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADDRESS,Slave address to be sent"
|
|
line.long 0x8 "SADDR0,Slave address register 0"
|
|
bitfld.long 0x8 15. "ADDRESSEN,I2C address enable" "0,1"
|
|
bitfld.long 0x8 10. "ADDFORMAT,Address mode for the I2C slave" "0,1"
|
|
bitfld.long 0x8 8.--9. "ADDRESS_8_9,7-bit address or bits 7:1 of a 10-bit address" "0,1,2,3"
|
|
hexmask.long.byte 0x8 1.--7. 1. "ADDRESS_1_7,Highest two bits of a 10-bit address"
|
|
bitfld.long 0x8 0. "ADDRESS_0,Bit 0 of a 10-bit address" "0,1"
|
|
line.long 0xC "SADDR1,Slave address register 1"
|
|
bitfld.long 0xC 15. "ADDRESS2EN,Second I2C address enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "ADDMSK2,ADDRESS2[7:1] mask" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "ADDRESS2,Second I2C address for the slave"
|
|
line.long 0x10 "TIMING,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PSC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDELY,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADELY,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period"
|
|
line.long 0x14 "TIMEOUT,timeout register"
|
|
bitfld.long 0x14 31. "EXTOEN,Extended clock timeout detection enable" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "BUSTOB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TOEN,Clock timeout detection enable" "0,1"
|
|
bitfld.long 0x14 12. "TOIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "BUSTOA,Bus timeout A"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "STAT,Transfer status register"
|
|
hexmask.long.byte 0x0 17.--23. 1. "READDR,Received match address in slave mode"
|
|
bitfld.long 0x0 16. "TR,Whether the I2C is a transmitter or a receiver in slave mode" "0,1"
|
|
bitfld.long 0x0 15. "I2CBSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 13. "SMBALT,SMBus Alert" "0,1"
|
|
bitfld.long 0x0 12. "TIMEOUT,TIMEOUT flag" "0,1"
|
|
bitfld.long 0x0 11. "PECERR,PEC error" "0,1"
|
|
bitfld.long 0x0 10. "OUERR,Overrun/Underrun error in slave mode" "0,1"
|
|
bitfld.long 0x0 9. "LOSTARB,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BERR,Bus error" "0,1"
|
|
bitfld.long 0x0 7. "TCR,Transfer complete reload" "0,1"
|
|
bitfld.long 0x0 6. "TC,Transfer complete in master mode" "0,1"
|
|
bitfld.long 0x0 5. "STPDET,STOP condition is detected on the bus" "0,1"
|
|
bitfld.long 0x0 4. "NACK,Not Acknowledge flag" "0,1"
|
|
bitfld.long 0x0 3. "ADDSEND,Address received matches in slave mode" "0,1"
|
|
bitfld.long 0x0 2. "RBNE,I2C_RDATA is not empty during receiving" "0,1"
|
|
bitfld.long 0x0 1. "TI,Transmit interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TBE,I2C_TDATA is empty during transmitting" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "STATC,Status clear register"
|
|
bitfld.long 0x0 13. "SMBALTC,SMBus Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMEOUTC,TIMEOUT flag clear" "0,1"
|
|
bitfld.long 0x0 11. "PECERRC,PEC error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OUERRC,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x0 9. "LOSTARBC,Arbitration Lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRC,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STPDETC,STPDET flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKC,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDSENDC,ADDSEND flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PEC,Packet Error Check register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PECV,Packet Error Checking Value"
|
|
line.long 0x4 "RDATA,receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RDATA,Receive data value"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TDATA,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TDATA,Transmit data value"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "CTL2,Control register 2"
|
|
hexmask.long.byte 0x0 9.--15. 1. "ADDM,Defines which bits of ADDRESS"
|
|
tree.end
|
|
tree "I2C3"
|
|
base ad:0x40005C00
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 23. "PECEN,PEC Calculation Switch" "0,1"
|
|
bitfld.long 0x0 22. "SMBALTEN,SMBus Alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDAEN,SMBus device default address enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBHAEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,Whether or not to response to a General Call" "0,1"
|
|
bitfld.long 0x0 18. "WUEN,Wakeup from Deep-sleep mode enable" "0,1"
|
|
bitfld.long 0x0 17. "SS,Whether to stretch SCL low when data is not ready in slave mode" "0,1"
|
|
bitfld.long 0x0 16. "SBCTL,Slave byte control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DENR,DMA enable for reception" "0,1"
|
|
bitfld.long 0x0 14. "DENT,DMA enable for transmission" "0,1"
|
|
bitfld.long 0x0 12. "ANOFF,Analog noise filter disable" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "STPDETIE,Stop detection interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDMIE,Address match interrupt enable in slave mode" "0,1"
|
|
bitfld.long 0x0 2. "RBNEIE,Receive interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "TIE,Receive interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "I2CEN,I2C peripheral enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 26. "PECTRANS,PEC Transfer" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode in master mode" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,Reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BYTENUM,Number of bytes to be transferred"
|
|
bitfld.long 0x4 15. "NACKEN,Generate NACK in slave mode" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Generate a STOP condition on I2C bus" "0,1"
|
|
bitfld.long 0x4 13. "START,Generate a START condition on I2C bus" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header executes read direction only in master receive mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10EN,10-bit addressing mode enable in master mode" "0,1"
|
|
bitfld.long 0x4 10. "TRDIR,Transfer direction in master mode" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADDRESS,Slave address to be sent"
|
|
line.long 0x8 "SADDR0,Slave address register 0"
|
|
bitfld.long 0x8 15. "ADDRESSEN,I2C address enable" "0,1"
|
|
bitfld.long 0x8 10. "ADDFORMAT,Address mode for the I2C slave" "0,1"
|
|
bitfld.long 0x8 8.--9. "ADDRESS_8_9,7-bit address or bits 7:1 of a 10-bit address" "0,1,2,3"
|
|
hexmask.long.byte 0x8 1.--7. 1. "ADDRESS_1_7,Highest two bits of a 10-bit address"
|
|
bitfld.long 0x8 0. "ADDRESS_0,Bit 0 of a 10-bit address" "0,1"
|
|
line.long 0xC "SADDR1,Slave address register 1"
|
|
bitfld.long 0xC 15. "ADDRESS2EN,Second I2C address enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "ADDMSK2,ADDRESS2[7:1] mask" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "ADDRESS2,Second I2C address for the slave"
|
|
line.long 0x10 "TIMING,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PSC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDELY,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADELY,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period"
|
|
line.long 0x14 "TIMEOUT,timeout register"
|
|
bitfld.long 0x14 31. "EXTOEN,Extended clock timeout detection enable" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "BUSTOB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TOEN,Clock timeout detection enable" "0,1"
|
|
bitfld.long 0x14 12. "TOIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "BUSTOA,Bus timeout A"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "STAT,Transfer status register"
|
|
hexmask.long.byte 0x0 17.--23. 1. "READDR,Received match address in slave mode"
|
|
bitfld.long 0x0 16. "TR,Whether the I2C is a transmitter or a receiver in slave mode" "0,1"
|
|
bitfld.long 0x0 15. "I2CBSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 13. "SMBALT,SMBus Alert" "0,1"
|
|
bitfld.long 0x0 12. "TIMEOUT,TIMEOUT flag" "0,1"
|
|
bitfld.long 0x0 11. "PECERR,PEC error" "0,1"
|
|
bitfld.long 0x0 10. "OUERR,Overrun/Underrun error in slave mode" "0,1"
|
|
bitfld.long 0x0 9. "LOSTARB,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BERR,Bus error" "0,1"
|
|
bitfld.long 0x0 7. "TCR,Transfer complete reload" "0,1"
|
|
bitfld.long 0x0 6. "TC,Transfer complete in master mode" "0,1"
|
|
bitfld.long 0x0 5. "STPDET,STOP condition is detected on the bus" "0,1"
|
|
bitfld.long 0x0 4. "NACK,Not Acknowledge flag" "0,1"
|
|
bitfld.long 0x0 3. "ADDSEND,Address received matches in slave mode" "0,1"
|
|
bitfld.long 0x0 2. "RBNE,I2C_RDATA is not empty during receiving" "0,1"
|
|
bitfld.long 0x0 1. "TI,Transmit interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TBE,I2C_TDATA is empty during transmitting" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "STATC,Status clear register"
|
|
bitfld.long 0x0 13. "SMBALTC,SMBus Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMEOUTC,TIMEOUT flag clear" "0,1"
|
|
bitfld.long 0x0 11. "PECERRC,PEC error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OUERRC,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x0 9. "LOSTARBC,Arbitration Lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRC,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STPDETC,STPDET flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKC,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDSENDC,ADDSEND flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PEC,Packet Error Check register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PECV,Packet Error Checking Value"
|
|
line.long 0x4 "RDATA,receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RDATA,Receive data value"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TDATA,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TDATA,Transmit data value"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "CTL2,Control register 2"
|
|
hexmask.long.byte 0x0 9.--15. 1. "ADDM,Defines which bits of ADDRESS"
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
tree "IPA (Image Processing Accelerator)"
|
|
base ad:0x52001000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 16.--17. "PFCM,Pixel format convert mode" "0,1,2,3"
|
|
bitfld.long 0x0 13. "WCFIE,Enable bit for wrong configuration interrupt" "0,1"
|
|
bitfld.long 0x0 12. "LLFIE,Enable bit for LUT loading finish interrupt" "0,1"
|
|
bitfld.long 0x0 11. "LACIE,Enable bit for LUT access conflict interrupt" "0,1"
|
|
bitfld.long 0x0 10. "TLMIE,Enable bit for transfer line mark interrupt" "0,1"
|
|
bitfld.long 0x0 9. "FTFIE,Enable bit for full transfer finish interrupt" "0,1"
|
|
bitfld.long 0x0 8. "TAEIE,Enable bit for transfer access error interrupt" "0,1"
|
|
bitfld.long 0x0 2. "TST,Transfer stop" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "THU,Transfer hang up" "0,1"
|
|
bitfld.long 0x0 0. "TEN,Transfer enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "INTF,Interrupt flag register"
|
|
bitfld.long 0x0 5. "WCFIF,Wrong configuration interrupt flag" "0,1"
|
|
bitfld.long 0x0 4. "LLFIF,LUT loading finish interrupt flag" "0,1"
|
|
bitfld.long 0x0 3. "LACIF,LUT access conflict interrupt flag" "0,1"
|
|
bitfld.long 0x0 2. "TLMIF,Transfer line mark interrupt flag" "0,1"
|
|
bitfld.long 0x0 1. "FTFIF,Full transfer finish interrupt flag" "0,1"
|
|
bitfld.long 0x0 0. "TAEIF,Transfer access error interrupt flag" "0,1"
|
|
group.long 0x8++0x33
|
|
line.long 0x0 "INTC,Interrupt flag clear register"
|
|
bitfld.long 0x0 5. "WCFIFC,Clear bit for wrong configuration interrupt flag" "0,1"
|
|
bitfld.long 0x0 4. "LLFIFC,Clear bit for LUT loading finish interrupt flag" "0,1"
|
|
bitfld.long 0x0 3. "LACIFC,Clear bit for LUT access conflict interrupt flag" "0,1"
|
|
bitfld.long 0x0 2. "TLMIFC,Clear bit for transfer line mark interrupt flag" "0,1"
|
|
bitfld.long 0x0 1. "TFIFC,Clear bit for full transfer finish interrupt flag" "0,1"
|
|
bitfld.long 0x0 0. "TAEIFC,Clear bit for transfer access error interrupt flag" "0,1"
|
|
line.long 0x4 "FMADDR,Foreground memory base address register"
|
|
hexmask.long 0x4 0.--31. 1. "FMADDR,Foreground memory base address"
|
|
line.long 0x8 "FLOFF,Foreground line offset register"
|
|
hexmask.long.word 0x8 0.--13. 1. "FLOFF,Foreground line offset"
|
|
line.long 0xC "BMADDR,Background memory base address register"
|
|
hexmask.long 0xC 0.--31. 1. "BMADDR,Background memory base address"
|
|
line.long 0x10 "BLOFF,Background line offset register"
|
|
hexmask.long.word 0x10 0.--13. 1. "BLOFF,Background line offset"
|
|
line.long 0x14 "FPCTL,Foreground pixel control register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "FPDAV,Foreground pre- defined alpha value"
|
|
bitfld.long 0x14 23. "FIIMEN,Foreground input interlace mode enable" "0,1"
|
|
bitfld.long 0x14 18.--19. "CSSM,Chroma Sub-Sampling mode" "0,1,2,3"
|
|
bitfld.long 0x14 16.--17. "FAVCA,Foreground alpha value calculation algorithm" "0,1,2,3"
|
|
hexmask.long.byte 0x14 8.--15. 1. "FCNP,Foreground LUT number of pixel"
|
|
bitfld.long 0x14 5. "FLLEN,Foreground LUT loading enable" "0,1"
|
|
bitfld.long 0x14 4. "FLPF,Foreground LUT pixel format" "0,1"
|
|
hexmask.long.byte 0x14 0.--3. 1. "FPF,Foreground pixel format"
|
|
line.long 0x18 "FPV,Foreground pixel value register"
|
|
hexmask.long.byte 0x18 16.--23. 1. "FPDRV,Foreground pre-defined red value"
|
|
hexmask.long.byte 0x18 8.--15. 1. "FPDGV,Foreground pre-defined green value"
|
|
hexmask.long.byte 0x18 0.--7. 1. "FPDBV,Foreground pre-defined blue value"
|
|
line.long 0x1C "BPCTL,Background pixel control register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "BPDAV,Background pre- defined alpha value"
|
|
bitfld.long 0x1C 16.--17. "BAVCA,Background alpha value calculation algorithm" "0,1,2,3"
|
|
hexmask.long.byte 0x1C 8.--15. 1. "BCNP,Background LUT number of pixel"
|
|
bitfld.long 0x1C 5. "BLLEN,Background LUT loading enable" "0,1"
|
|
bitfld.long 0x1C 4. "BLPF,Background LUT pixel format" "0,1"
|
|
hexmask.long.byte 0x1C 0.--3. 1. "BPF,Background pixel format"
|
|
line.long 0x20 "BPV,Background pixel value register"
|
|
hexmask.long.byte 0x20 16.--23. 1. "BPDRV,Background pre-defined red value"
|
|
hexmask.long.byte 0x20 8.--15. 1. "BPDGV,Background pre-defined green value"
|
|
hexmask.long.byte 0x20 0.--7. 1. "BPDBV,Background pre-defined blue value"
|
|
line.long 0x24 "FLMADDR,Foreground LUT memory base address register"
|
|
hexmask.long 0x24 0.--31. 1. "FLMBADDR,Foreground LUT memory base address"
|
|
line.long 0x28 "BLMADDR,Background LUT memory base address register"
|
|
hexmask.long 0x28 0.--31. 1. "BLMADDR,Background LUT memory base address"
|
|
line.long 0x2C "DPCTL,Destination pixel control register"
|
|
bitfld.long 0x2C 18.--19. "VERDEC,Verticle pre decimation filter control" "0,1,2,3"
|
|
bitfld.long 0x2C 16.--17. "HORDEC,Horizontal pre decimation filter control" "0,1,2,3"
|
|
bitfld.long 0x2C 8.--9. "ROT,Indicates the clockwise rotation to be applied at the output" "0,1,2,3"
|
|
bitfld.long 0x2C 0.--2. "DPF,Destination pixel format" "0,1,2,3,4,5,6,7"
|
|
line.long 0x30 "DPV_ARGB8888,Destination pixel value register(When the destination pixel format is"
|
|
hexmask.long.byte 0x30 24.--31. 1. "DPDAV,Destination pre-defined alpha value"
|
|
hexmask.long.byte 0x30 16.--23. 1. "DPDRV,Destination pre-defined red value"
|
|
hexmask.long.byte 0x30 8.--15. 1. "DPDGV,Destination pre-defined green value"
|
|
hexmask.long.byte 0x30 0.--7. 1. "DPDBV,Destination pre-defined blue value"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DPV_RGB888,Destination pixel value register(When the destination pixel format is"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DPDRV,Destination pre-defined red value"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DPDGV,Destination pre-defined green value"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DPDBV,Destination pre-defined blue value"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DPV_RGB565,Destination pixel value register(When the destination pixel format is"
|
|
hexmask.long.byte 0x0 11.--15. 1. "DPDRV,Destination pre-defined red value"
|
|
hexmask.long.byte 0x0 5.--10. 1. "DPDGV,Destination pre-defined green value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DPDBV,Destination pre-defined blue value"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DPV_ARGB1555,Destination pixel value register(When the destination pixel format is"
|
|
bitfld.long 0x0 15. "DPDAV,Destination pre-defined alpha value" "0,1"
|
|
hexmask.long.byte 0x0 10.--14. 1. "DPDRV,Destination pre-defined red value"
|
|
hexmask.long.byte 0x0 5.--9. 1. "DPDGV,Destination pre-defined green value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DPDBV,Destination pre-defined blue value"
|
|
group.long 0x38++0x1F
|
|
line.long 0x0 "DPV_ARGB4444,Destination pixel value register(When the destination pixel format is"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DPDAV,Destination pre-defined alpha value"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DPDRV,Destination pre-defined red value"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DPDGV,Destination pre-defined green value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DPDBV,Destination pre-defined blue value"
|
|
line.long 0x4 "DMADDR,Destination memory base address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMADDR,Destination memory base address"
|
|
line.long 0x8 "DLOFF,Destination line offset register"
|
|
hexmask.long.word 0x8 0.--13. 1. "DLOFF,Destination line offset"
|
|
line.long 0xC "IMS,Image size register"
|
|
hexmask.long.word 0xC 16.--29. 1. "WIDTH,Width of the image to be processed"
|
|
hexmask.long.word 0xC 0.--15. 1. "HEIGHT,Height of the image to be processed"
|
|
line.long 0x10 "LM,Line mark register"
|
|
hexmask.long.word 0x10 0.--15. 1. "LM,line mark"
|
|
line.long 0x14 "ITCTL,Inter-timer control register"
|
|
hexmask.long.byte 0x14 8.--15. 1. "NCCI,Number of clock cycles interval"
|
|
bitfld.long 0x14 0. "ITEN,Inter-timer enable" "0,1"
|
|
line.long 0x18 "BSCTL,Color space conversion coefficient register0"
|
|
hexmask.long.word 0x18 16.--29. 1. "YSCALE,Y scaling factor for the Foreground"
|
|
hexmask.long.word 0x18 0.--13. 1. "XSCALE,X scaling factor for the Foreground"
|
|
line.long 0x1C "DIMS,Scaling destination image size register"
|
|
hexmask.long.word 0x1C 16.--29. 1. "DWIDTH,Width of the image to be processed"
|
|
hexmask.long.word 0x1C 0.--15. 1. "DHEIGHT,Height of the image to be processed"
|
|
group.long 0x5C++0xF
|
|
line.long 0x0 "EF_UV_MADDR,Foreground even frame or UV memory base address register"
|
|
hexmask.long 0x0 0.--31. 1. "EFUVMADDR,Foreground Even Frame/UV memory base address"
|
|
line.long 0x4 "CSCC_CFG0,Color space conversion coefficient register0"
|
|
bitfld.long 0x4 31. "CONVMOD,Color space convert mode" "0,1"
|
|
hexmask.long.word 0x4 18.--28. 1. "C0,Y multiplier coefficient. For YUV"
|
|
hexmask.long.word 0x4 9.--17. 1. "UVOFF,Phase offset implicited for UV/CbCr data"
|
|
hexmask.long.word 0x4 0.--8. 1. "YOFF,Amplitude offset implicited for Y data"
|
|
line.long 0x8 "CCSC_CFG1,Color space conversion coefficient configure register 1"
|
|
hexmask.long.word 0x8 16.--26. 1. "C1,V/Cr Red multiplier coefficient"
|
|
hexmask.long.word 0x8 0.--10. 1. "C4,U/Cb Blue multiplier coefficient. For YUV"
|
|
line.long 0xC "CCSC_CFG2,Color space conversion coefficient register2"
|
|
hexmask.long.word 0xC 16.--26. 1. "C2,V/Cr Green multiplier coefficient"
|
|
hexmask.long.word 0xC 0.--10. 1. "C3,U/Cb Green multiplier coefficient. For YUV"
|
|
tree.end
|
|
endif
|
|
tree "LPDTS (Low Power Digital Temperature Sensor)"
|
|
base ad:0x58006800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CFG,configuration register"
|
|
bitfld.long 0x0 20. "REFSEL,Reference clock selection" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SPT,Sampling time"
|
|
hexmask.long.byte 0x0 8.--11. 1. "ITSEL,Input trigger selection"
|
|
bitfld.long 0x0 4. "TRGS,Trigger selection for frequency measurement" "0,1"
|
|
bitfld.long 0x0 0. "TSEN,Enable temperature sensor" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SDATA,sensor T0 data register 1"
|
|
bitfld.long 0x0 16.--17. "VAL,Engineering value" "0,1,2,3"
|
|
hexmask.long.word 0x0 0.--15. 1. "FREQ,Frequency value"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "RDATA,ramp data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RCVAL,Ramp coefficient"
|
|
line.long 0x4 "IT,Interrupt threshold register"
|
|
hexmask.long.word 0x4 16.--31. 1. "INTHT,Interrupt high threshold"
|
|
hexmask.long.word 0x4 0.--15. 1. "INTLT,Interrupt low threshold"
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x0 "DATA,Temperature data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "COVAL,Value of the counter output"
|
|
line.long 0x4 "STAT,Temperature sensor status register"
|
|
bitfld.long 0x4 15. "TSRF,Temperature sensor ready flag" "0,1"
|
|
bitfld.long 0x4 6. "HTAIF,High threshold asynchronous interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "LTAIF,Low threshold asynchronous interrupt flag" "0,1"
|
|
bitfld.long 0x4 4. "EMAIF,End of measurement asynchronous interrupt flag" "0,1"
|
|
bitfld.long 0x4 2. "HTIF,High threshold interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "LTIF,Low threshold interrupt flag" "0,1"
|
|
bitfld.long 0x4 0. "EMIF,End of measurement interrupt flag" "0,1"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "INTEN,Interrupt enable register"
|
|
bitfld.long 0x0 6. "HTAIE,High threshold asynchronous interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "LTAIE,Low threshold asynchronous interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "EMAIE,End of measurement asynchronous interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,High threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "LTIE,Low threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "EMIE,End of measurement interrupt enable" "0,1"
|
|
line.long 0x4 "INTC,Interrupt clear flag register"
|
|
bitfld.long 0x4 6. "HTAIC,High threshold asynchronous interrupt clear" "0,1"
|
|
bitfld.long 0x4 5. "LTAIC,Low threshold asynchronous interrupt clear" "0,1"
|
|
bitfld.long 0x4 4. "EMAIC,End of Measure asynchronous interrupt clear" "0,1"
|
|
bitfld.long 0x4 2. "HTIC,High threshold interrupt clear" "0,1"
|
|
bitfld.long 0x4 1. "LTIC,Low threshold interrupt clear" "0,1"
|
|
bitfld.long 0x4 0. "EMIC,End of measurement interrupt clear" "0,1"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "OP,Option register"
|
|
hexmask.long 0x0 0.--31. 1. "OP,general purpose option bits"
|
|
tree.end
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
tree "MDIO (Management Data Input/Output)"
|
|
base ad:0x40009400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 1. "PHYB,MDIO PHY bit length" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software reset" "0,1"
|
|
line.long 0x4 "RFRM,Received frame information register"
|
|
bitfld.long 0x4 12.--13. "RTA,Received frame field TA" "0,1,2,3"
|
|
hexmask.long.byte 0x4 7.--11. 1. "RDEV,Received frame field DEVADD"
|
|
hexmask.long.byte 0x4 2.--6. 1. "RPHY,Received frame field PHYADR"
|
|
bitfld.long 0x4 0.--1. "ROP,Received frame field OP" "0,1,2,3"
|
|
rgroup.long 0x8++0xB
|
|
line.long 0x0 "RDATA,Received data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Received frame field DATA"
|
|
line.long 0x4 "RADDR,Received address register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RADDR,Received frame field ADDRESS"
|
|
line.long 0x8 "TDATA,Transfer data register"
|
|
hexmask.long.word 0x8 0.--15. 1. "TDATA,Transfer data"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
hexmask.long.byte 0x0 10.--14. 1. "EDEVADD,Expected DEVADD"
|
|
hexmask.long.byte 0x0 5.--9. 1. "EPHYSEL,Selects expected PHYADR"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PHYSW,Software provided PHYADR"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "STAT,Status register"
|
|
bitfld.long 0x0 13. "RBNE,Read data buffer not empty flag" "0,1"
|
|
bitfld.long 0x0 11. "OVR,Receive overrun flag" "0,1"
|
|
bitfld.long 0x0 10. "UDR,Transmit underrun flag" "0,1"
|
|
bitfld.long 0x0 9. "TO,Timeout flag" "0,1"
|
|
bitfld.long 0x0 8. "TANM,Set at end bit of TA of a write data frame or a write address frame" "0,1"
|
|
bitfld.long 0x0 7. "PHYNM,Set at end bit of PHYADR if PHYADR nonmatches" "0,1"
|
|
bitfld.long 0x0 6. "PHYM,Set at end bit of PHYADR if PHYADR matches" "0,1"
|
|
bitfld.long 0x0 5. "DEVNM,Set at end bit of DEVADD if DEVADD nonmatches" "0,1"
|
|
bitfld.long 0x0 4. "DEVM,Set at end bit of DEVADD if DEVADD matches" "0,1"
|
|
bitfld.long 0x0 3. "RDFRM,Set at end bit of a read data frame if DEVADD and PHYADR both match" "0,1"
|
|
bitfld.long 0x0 2. "RDINCFRM,Set at end bit of a post read increment address frame if DEVADD and" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ADDRFRM,Set at end bit of a write address frame if DEVADD and PHYADR both match" "0,1"
|
|
bitfld.long 0x0 0. "WRFRM,Set at end bit of a write data frame if DEVADD and PHYADR both match" "0,1"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "INTEN,Interrupt enable register"
|
|
bitfld.long 0x0 13. "RBNEIE,interrupt is requested when RBDE bit in MDIO_STAT register becomes active" "0,1"
|
|
bitfld.long 0x0 11. "OVRIE,interrupt is requested when OVR bit in MDIO_STAT register becomes active" "0,1"
|
|
bitfld.long 0x0 10. "UDRIE,interrupt is requested when UDR bit in MDIO_STAT register becomes active" "0,1"
|
|
bitfld.long 0x0 9. "TOIE,interrupt is requested when TO bit in MDIO_STAT register becomes active" "0,1"
|
|
bitfld.long 0x0 8. "TANMIE,interrupt is requested when TANM bit in MDIO_STAT register becomes active" "0,1"
|
|
bitfld.long 0x0 7. "PHYNMIE,interrupt is requested when PHYNM bit in MDIO_STAT register becomes" "0,1"
|
|
bitfld.long 0x0 6. "PHYMIE,interrupt is requested when PHYM bit in MDIO_STAT register becomes active" "0,1"
|
|
bitfld.long 0x0 5. "DEVNMIE,interrupt is requested when DEVNM bit in MDIO_STAT register becomes" "0,1"
|
|
bitfld.long 0x0 4. "DEVMIE,interrupt is requested when DEVM bit in MDIO_STAT register becomes active" "0,1"
|
|
bitfld.long 0x0 3. "RDFRMIE,interrupt is requested when RDFRM bit in MDIO_STAT register becomes" "0,1"
|
|
bitfld.long 0x0 2. "RDINCFRMIE,interrupt is requested when RDINCFRM bit in MDIO_STAT register becomes" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ADDRFRMIE,interrupt is requested when ADDRFRM bit in MDIO_STAT register becomes" "0,1"
|
|
bitfld.long 0x0 0. "WRFRMIE,interrupt is requested when WRFRM bit in MDIO_STAT register becomes" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PIN,pin value register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PHYPIN,Pin value read from hardware PRTADR[4:0] pins"
|
|
line.long 0x4 "TO,Timeout register"
|
|
hexmask.long.word 0x4 1.--16. 1. "TOCNT,MDIO time out"
|
|
bitfld.long 0x4 0. "TOEN,Timeout enable" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "MDMA (Master Direct Memory Access Controller)"
|
|
base ad:0x52000000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "GINTF,Global interrupt flag register"
|
|
bitfld.long 0x0 15. "GIF15,Global interrupt flag of channel 15" "0,1"
|
|
bitfld.long 0x0 14. "GIF14,Global interrupt flag of channel 14" "0,1"
|
|
bitfld.long 0x0 13. "GIF13,Global interrupt flag of channel 13" "0,1"
|
|
bitfld.long 0x0 12. "GIF12,Global interrupt flag of channel 12" "0,1"
|
|
bitfld.long 0x0 11. "GIF11,Global interrupt flag of channel 11" "0,1"
|
|
bitfld.long 0x0 10. "GIF10,Global interrupt flag of channel 10" "0,1"
|
|
bitfld.long 0x0 9. "GIF9,Global interrupt flag of channel 9" "0,1"
|
|
bitfld.long 0x0 8. "GIF8,Global interrupt flag of channel 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "GIF7,Global interrupt flag of channel 7" "0,1"
|
|
bitfld.long 0x0 6. "GIF6,Global interrupt flag of channel 6" "0,1"
|
|
bitfld.long 0x0 5. "GIF5,Global interrupt flag of channel 5" "0,1"
|
|
bitfld.long 0x0 4. "GIF4,Global interrupt flag of channel 4" "0,1"
|
|
bitfld.long 0x0 3. "GIF3,Global interrupt flag of channel 3" "0,1"
|
|
bitfld.long 0x0 2. "GIF2,Global interrupt flag of channel 2" "0,1"
|
|
bitfld.long 0x0 1. "GIF1,Global interrupt flag of channel 1" "0,1"
|
|
bitfld.long 0x0 0. "GIF0,Global interrupt flag of channel 0" "0,1"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "CH0STAT0,Channel 0 status register"
|
|
bitfld.long 0x0 16. "REQAF,Channel x request active flag" "0,1"
|
|
bitfld.long 0x0 4. "TCF,Channel x buffer transfer complete flag" "0,1"
|
|
bitfld.long 0x0 3. "BTCF,Channel x block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 2. "MBTCF,Channel x multi-block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 1. "CHTCF,Channel x channel transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "ERR,Channel x transfer error flag" "0,1"
|
|
wgroup.long 0x44++0x3
|
|
line.long 0x0 "CH0STATC,Channel 0 status clear regist"
|
|
bitfld.long 0x0 4. "TCFC,Channel x buffer transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 3. "BTCFC,Channel x buffer block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 2. "MBTCFC,Channel x buffer multi-block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 1. "CHTCFC,Channel x channel transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 0. "ERRC,Channel x transfer error flag clear" "0,1"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x0 "CH0STAT1,Channel 0 status register"
|
|
bitfld.long 0x0 11. "BZERR,Block size error flag" "0,1"
|
|
bitfld.long 0x0 10. "ASERR,Address and size error flag" "0,1"
|
|
bitfld.long 0x0 9. "MDTERR,Mask data error flag" "0,1"
|
|
bitfld.long 0x0 8. "LDTERR,Link data transfer error flag in the last transfer of the channel" "0,1"
|
|
bitfld.long 0x0 7. "TERRD,Transfer error direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ERRADDR,Transfer error address"
|
|
group.long 0x4C++0x1F
|
|
line.long 0x0 "CH0CTL0,Channel 0 control register"
|
|
bitfld.long 0x0 16. "SWREQ,Software request" "0,1"
|
|
bitfld.long 0x0 14. "WES,Word endianess swapping in double word" "0,1"
|
|
bitfld.long 0x0 13. "HWES,Half word endianess swapping in word" "0,1"
|
|
bitfld.long 0x0 12. "BES,Byte endianess swapping in half word" "0,1"
|
|
bitfld.long 0x0 8. "SMODEN,Secure mode enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TCIE,Buffer transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "BTCIE,Block transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MBTCIE,Multi-block transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "CHTCIE,Channel transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "ERRIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH0CFG,Channel 0 configure regist"
|
|
bitfld.long 0x4 31. "BWMOD,Bufferable write mode" "0,1"
|
|
bitfld.long 0x4 30. "SWREQMOD,Software request mode" "0,1"
|
|
bitfld.long 0x4 28.--29. "TRIGMOD,Trigger mode" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PAMOD,Padding and alignement mode" "0,1,2,3"
|
|
bitfld.long 0x4 25. "PKEN,Pack enable" "0,1"
|
|
hexmask.long.byte 0x4 18.--24. 1. "BTLEN,Buffer transfer length"
|
|
bitfld.long 0x4 15.--17. "DBURST,Transfer burst type of destination" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "SBURST,Transfer burst type of source" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "DIOS,Offset size of destination increment" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "SIOS,Offset size of source increment" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "DWIDTH,Data size of destination" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "SWIDTH,Data size of source" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "DIMOD,Destination increment mode" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SIMOD,Source increment mode" "0,1,2,3"
|
|
line.long 0x8 "CH0BTCFG,Channel 0 block transfer configure regist"
|
|
hexmask.long.word 0x8 20.--31. 1. "BRNUM,Multi-block number"
|
|
bitfld.long 0x8 19. "DADDRUM,Multi-block destination address update mode" "0,1"
|
|
bitfld.long 0x8 18. "SADDRUM,Multi-block source address update mode" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "TBNUM,Transfer byte number in block"
|
|
line.long 0xC "CH0SADDR,Channel 0 source address regist"
|
|
hexmask.long 0xC 0.--31. 1. "SADDR,Source address"
|
|
line.long 0x10 "CH0DADDR,Channel 0 destination address regist"
|
|
hexmask.long 0x10 0.--31. 1. "DADDR,Destination address"
|
|
line.long 0x14 "CH0MBADDRU,Channel 0 multi-block address update regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "DADDRUV,Destination address update value"
|
|
hexmask.long.word 0x14 0.--15. 1. "SADDRUV,Source address update value"
|
|
line.long 0x18 "CH0LADDR,Channel 0 link address regist"
|
|
hexmask.long 0x18 0.--31. 1. "LADDR,Link address"
|
|
line.long 0x1C "CH0CTL1,Channel 0 control register"
|
|
bitfld.long 0x1C 17. "DBSEL,Destination bus select" "0,1"
|
|
bitfld.long 0x1C 16. "SBSEL,Source bus select" "0,1"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "TRIGSEL,Trigger select"
|
|
group.long 0x70++0x7
|
|
line.long 0x0 "CH0MADDR,Channel 0 mask address regist"
|
|
hexmask.long 0x0 0.--31. 1. "MADDR,Mask address"
|
|
line.long 0x4 "CH0MDATA,Channel 0 mask data regist"
|
|
hexmask.long 0x4 0.--31. 1. "MDATA,Mask data"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "CH1STAT0,Channel 1 status register"
|
|
bitfld.long 0x0 16. "REQAF,Channel x request active flag" "0,1"
|
|
bitfld.long 0x0 4. "TCF,Channel x buffer transfer complete flag" "0,1"
|
|
bitfld.long 0x0 3. "BTCF,Channel x block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 2. "MBTCF,Channel x multi-block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 1. "CHTCF,Channel x channel transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "ERR,Channel x transfer error flag" "0,1"
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "CH1STATC,Channel 1 status clear regist"
|
|
bitfld.long 0x0 4. "TCFC,Channel x buffer transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 3. "BTCFC,Channel x buffer block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 2. "MBTCFC,Channel x buffer multi-block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 1. "CHTCFC,Channel x channel transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 0. "ERRC,Channel x transfer error flag clear" "0,1"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "CH1STAT1,Channel 1 status register"
|
|
bitfld.long 0x0 11. "BZERR,Block size error flag" "0,1"
|
|
bitfld.long 0x0 10. "ASERR,Address and size error flag" "0,1"
|
|
bitfld.long 0x0 9. "MDTERR,Mask data error flag" "0,1"
|
|
bitfld.long 0x0 8. "LDTERR,Link data transfer error flag in the last transfer of the channel" "0,1"
|
|
bitfld.long 0x0 7. "TERRD,Transfer error direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ERRADDR,Transfer error address"
|
|
group.long 0x8C++0x1F
|
|
line.long 0x0 "CH1CTL0,Channel 1 control register"
|
|
bitfld.long 0x0 16. "SWREQ,Software request" "0,1"
|
|
bitfld.long 0x0 14. "WES,Word endianess swapping in double word" "0,1"
|
|
bitfld.long 0x0 13. "HWES,Half word endianess swapping in word" "0,1"
|
|
bitfld.long 0x0 12. "BES,Byte endianess swapping in half word" "0,1"
|
|
bitfld.long 0x0 8. "SMODEN,Secure mode enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TCIE,Buffer transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "BTCIE,Block transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MBTCIE,Multi-block transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "CHTCIE,Channel transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "ERRIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH1CFG,Channel 1 configure regist"
|
|
bitfld.long 0x4 31. "BWMOD,Bufferable write mode" "0,1"
|
|
bitfld.long 0x4 30. "SWREQMOD,Software request mode" "0,1"
|
|
bitfld.long 0x4 28.--29. "TRIGMOD,Trigger mode" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PAMOD,Padding and alignement mode" "0,1,2,3"
|
|
bitfld.long 0x4 25. "PKEN,Pack enable" "0,1"
|
|
hexmask.long.byte 0x4 18.--24. 1. "BTLEN,Buffer transfer length"
|
|
bitfld.long 0x4 15.--17. "DBURST,Transfer burst type of destination" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "SBURST,Transfer burst type of source" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "DIOS,Offset size of destination increment" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "SIOS,Offset size of source increment" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "DWIDTH,Data size of destination" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "SWIDTH,Data size of source" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "DIMOD,Destination increment mode" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SIMOD,Source increment mode" "0,1,2,3"
|
|
line.long 0x8 "CH1BTCFG,Channel 1 block transfer configure regist"
|
|
hexmask.long.word 0x8 20.--31. 1. "BRNUM,Multi-block number"
|
|
bitfld.long 0x8 19. "DADDRUM,Multi-block destination address update mode" "0,1"
|
|
bitfld.long 0x8 18. "SADDRUM,Multi-block source address update mode" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "TBNUM,Transfer byte number in block"
|
|
line.long 0xC "CH1SADDR,Channel 1 source address regist"
|
|
hexmask.long 0xC 0.--31. 1. "SADDR,Source address"
|
|
line.long 0x10 "CH1DADDR,Channel 1 destination address regist"
|
|
hexmask.long 0x10 0.--31. 1. "DADDR,Destination address"
|
|
line.long 0x14 "CH1MBADDRU,Channel 1 multi-block address update regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "DADDRUV,Destination address update value"
|
|
hexmask.long.word 0x14 0.--15. 1. "SADDRUV,Source address update value"
|
|
line.long 0x18 "CH1LADDR,Channel 1 link address regist"
|
|
hexmask.long 0x18 0.--31. 1. "LADDR,Link address"
|
|
line.long 0x1C "CH1CTL1,Channel 1 control register"
|
|
bitfld.long 0x1C 17. "DBSEL,Destination bus select" "0,1"
|
|
bitfld.long 0x1C 16. "SBSEL,Source bus select" "0,1"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "TRIGSEL,Trigger select"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "CH1MADDR,Channel 1 mask address regist"
|
|
hexmask.long 0x0 0.--31. 1. "MADDR,Mask address"
|
|
line.long 0x4 "CH1MDATA,Channel 1 mask data regist"
|
|
hexmask.long 0x4 0.--31. 1. "MDATA,Mask data"
|
|
rgroup.long 0xC0++0x3
|
|
line.long 0x0 "CH2STAT0,Channel 2 status register"
|
|
bitfld.long 0x0 16. "REQAF,Channel x request active flag" "0,1"
|
|
bitfld.long 0x0 4. "TCF,Channel x buffer transfer complete flag" "0,1"
|
|
bitfld.long 0x0 3. "BTCF,Channel x block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 2. "MBTCF,Channel x multi-block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 1. "CHTCF,Channel x channel transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "ERR,Channel x transfer error flag" "0,1"
|
|
wgroup.long 0xC4++0x3
|
|
line.long 0x0 "CH2STATC,Channel 2 status clear regist"
|
|
bitfld.long 0x0 4. "TCFC,Channel x buffer transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 3. "BTCFC,Channel x buffer block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 2. "MBTCFC,Channel x buffer multi-block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 1. "CHTCFC,Channel x channel transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 0. "ERRC,Channel x transfer error flag clear" "0,1"
|
|
rgroup.long 0xC8++0x3
|
|
line.long 0x0 "CH2STAT1,Channel 2 status register"
|
|
bitfld.long 0x0 11. "BZERR,Block size error flag" "0,1"
|
|
bitfld.long 0x0 10. "ASERR,Address and size error flag" "0,1"
|
|
bitfld.long 0x0 9. "MDTERR,Mask data error flag" "0,1"
|
|
bitfld.long 0x0 8. "LDTERR,Link data transfer error flag in the last transfer of the channel" "0,1"
|
|
bitfld.long 0x0 7. "TERRD,Transfer error direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ERRADDR,Transfer error address"
|
|
group.long 0xCC++0x1F
|
|
line.long 0x0 "CH2CTL0,Channel 2 control register"
|
|
bitfld.long 0x0 16. "SWREQ,Software request" "0,1"
|
|
bitfld.long 0x0 14. "WES,Word endianess swapping in double word" "0,1"
|
|
bitfld.long 0x0 13. "HWES,Half word endianess swapping in word" "0,1"
|
|
bitfld.long 0x0 12. "BES,Byte endianess swapping in half word" "0,1"
|
|
bitfld.long 0x0 8. "SMODEN,Secure mode enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TCIE,Buffer transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "BTCIE,Block transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MBTCIE,Multi-block transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "CHTCIE,Channel transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "ERRIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH2CFG,Channel 2 configure regist"
|
|
bitfld.long 0x4 31. "BWMOD,Bufferable write mode" "0,1"
|
|
bitfld.long 0x4 30. "SWREQMOD,Software request mode" "0,1"
|
|
bitfld.long 0x4 28.--29. "TRIGMOD,Trigger mode" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PAMOD,Padding and alignement mode" "0,1,2,3"
|
|
bitfld.long 0x4 25. "PKEN,Pack enable" "0,1"
|
|
hexmask.long.byte 0x4 18.--24. 1. "BTLEN,Buffer transfer length"
|
|
bitfld.long 0x4 15.--17. "DBURST,Transfer burst type of destination" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "SBURST,Transfer burst type of source" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "DIOS,Offset size of destination increment" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "SIOS,Offset size of source increment" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "DWIDTH,Data size of destination" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "SWIDTH,Data size of source" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "DIMOD,Destination increment mode" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SIMOD,Source increment mode" "0,1,2,3"
|
|
line.long 0x8 "CH2BTCFG,Channel 2 block transfer configure regist"
|
|
hexmask.long.word 0x8 20.--31. 1. "BRNUM,Multi-block number"
|
|
bitfld.long 0x8 19. "DADDRUM,Multi-block destination address update mode" "0,1"
|
|
bitfld.long 0x8 18. "SADDRUM,Multi-block source address update mode" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "TBNUM,Transfer byte number in block"
|
|
line.long 0xC "CH2SADDR,Channel 2 source address regist"
|
|
hexmask.long 0xC 0.--31. 1. "SADDR,Source address"
|
|
line.long 0x10 "CH2DADDR,Channel 2 destination address regist"
|
|
hexmask.long 0x10 0.--31. 1. "DADDR,Destination address"
|
|
line.long 0x14 "CH2MBADDRU,Channel 2 multi-block address update regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "DADDRUV,Destination address update value"
|
|
hexmask.long.word 0x14 0.--15. 1. "SADDRUV,Source address update value"
|
|
line.long 0x18 "CH2LADDR,Channel 2 link address regist"
|
|
hexmask.long 0x18 0.--31. 1. "LADDR,Link address"
|
|
line.long 0x1C "CH2CTL1,Channel 2 control register"
|
|
bitfld.long 0x1C 17. "DBSEL,Destination bus select" "0,1"
|
|
bitfld.long 0x1C 16. "SBSEL,Source bus select" "0,1"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "TRIGSEL,Trigger select"
|
|
group.long 0xF0++0x7
|
|
line.long 0x0 "CH2MADDR,Channel 2 mask address regist"
|
|
hexmask.long 0x0 0.--31. 1. "MADDR,Mask address"
|
|
line.long 0x4 "CH2MDATA,Channel 2 mask data regist"
|
|
hexmask.long 0x4 0.--31. 1. "MDATA,Mask data"
|
|
rgroup.long 0x100++0x3
|
|
line.long 0x0 "CH3STAT0,Channel 3 status register"
|
|
bitfld.long 0x0 16. "REQAF,Channel x request active flag" "0,1"
|
|
bitfld.long 0x0 4. "TCF,Channel x buffer transfer complete flag" "0,1"
|
|
bitfld.long 0x0 3. "BTCF,Channel x block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 2. "MBTCF,Channel x multi-block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 1. "CHTCF,Channel x channel transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "ERR,Channel x transfer error flag" "0,1"
|
|
wgroup.long 0x104++0x3
|
|
line.long 0x0 "CH3STATC,Channel 3 status clear regist"
|
|
bitfld.long 0x0 4. "TCFC,Channel x buffer transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 3. "BTCFC,Channel x buffer block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 2. "MBTCFC,Channel x buffer multi-block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 1. "CHTCFC,Channel x channel transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 0. "ERRC,Channel x transfer error flag clear" "0,1"
|
|
rgroup.long 0x108++0x3
|
|
line.long 0x0 "CH3STAT1,Channel 3 status register"
|
|
bitfld.long 0x0 11. "BZERR,Block size error flag" "0,1"
|
|
bitfld.long 0x0 10. "ASERR,Address and size error flag" "0,1"
|
|
bitfld.long 0x0 9. "MDTERR,Mask data error flag" "0,1"
|
|
bitfld.long 0x0 8. "LDTERR,Link data transfer error flag in the last transfer of the channel" "0,1"
|
|
bitfld.long 0x0 7. "TERRD,Transfer error direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ERRADDR,Transfer error address"
|
|
group.long 0x10C++0x1F
|
|
line.long 0x0 "CH3CTL0,Channel 3 control register"
|
|
bitfld.long 0x0 16. "SWREQ,Software request" "0,1"
|
|
bitfld.long 0x0 14. "WES,Word endianess swapping in double word" "0,1"
|
|
bitfld.long 0x0 13. "HWES,Half word endianess swapping in word" "0,1"
|
|
bitfld.long 0x0 12. "BES,Byte endianess swapping in half word" "0,1"
|
|
bitfld.long 0x0 8. "SMODEN,Secure mode enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TCIE,Buffer transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "BTCIE,Block transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MBTCIE,Multi-block transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "CHTCIE,Channel transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "ERRIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH3CFG,Channel 3 configure regist"
|
|
bitfld.long 0x4 31. "BWMOD,Bufferable write mode" "0,1"
|
|
bitfld.long 0x4 30. "SWREQMOD,Software request mode" "0,1"
|
|
bitfld.long 0x4 28.--29. "TRIGMOD,Trigger mode" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PAMOD,Padding and alignement mode" "0,1,2,3"
|
|
bitfld.long 0x4 25. "PKEN,Pack enable" "0,1"
|
|
hexmask.long.byte 0x4 18.--24. 1. "BTLEN,Buffer transfer length"
|
|
bitfld.long 0x4 15.--17. "DBURST,Transfer burst type of destination" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "SBURST,Transfer burst type of source" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "DIOS,Offset size of destination increment" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "SIOS,Offset size of source increment" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "DWIDTH,Data size of destination" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "SWIDTH,Data size of source" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "DIMOD,Destination increment mode" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SIMOD,Source increment mode" "0,1,2,3"
|
|
line.long 0x8 "CH3BTCFG,Channel 3 block transfer configure regist"
|
|
hexmask.long.word 0x8 20.--31. 1. "BRNUM,Multi-block number"
|
|
bitfld.long 0x8 19. "DADDRUM,Multi-block destination address update mode" "0,1"
|
|
bitfld.long 0x8 18. "SADDRUM,Multi-block source address update mode" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "TBNUM,Transfer byte number in block"
|
|
line.long 0xC "CH3SADDR,Channel 3 source address regist"
|
|
hexmask.long 0xC 0.--31. 1. "SADDR,Source address"
|
|
line.long 0x10 "CH3DADDR,Channel 3 destination address regist"
|
|
hexmask.long 0x10 0.--31. 1. "DADDR,Destination address"
|
|
line.long 0x14 "CH3MBADDRU,Channel 3 multi-block address update regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "DADDRUV,Destination address update value"
|
|
hexmask.long.word 0x14 0.--15. 1. "SADDRUV,Source address update value"
|
|
line.long 0x18 "CH3LADDR,Channel 3 link address regist"
|
|
hexmask.long 0x18 0.--31. 1. "LADDR,Link address"
|
|
line.long 0x1C "CH3CTL1,Channel 3 control register"
|
|
bitfld.long 0x1C 17. "DBSEL,Destination bus select" "0,1"
|
|
bitfld.long 0x1C 16. "SBSEL,Source bus select" "0,1"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "TRIGSEL,Trigger select"
|
|
group.long 0x130++0x7
|
|
line.long 0x0 "CH3MADDR,Channel 3 mask address regist"
|
|
hexmask.long 0x0 0.--31. 1. "MADDR,Mask address"
|
|
line.long 0x4 "CH3MDATA,Channel 3 mask data regist"
|
|
hexmask.long 0x4 0.--31. 1. "MDATA,Mask data"
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "CH4STAT0,Channel 4 status register"
|
|
bitfld.long 0x0 16. "REQAF,Channel x request active flag" "0,1"
|
|
bitfld.long 0x0 4. "TCF,Channel x buffer transfer complete flag" "0,1"
|
|
bitfld.long 0x0 3. "BTCF,Channel x block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 2. "MBTCF,Channel x multi-block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 1. "CHTCF,Channel x channel transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "ERR,Channel x transfer error flag" "0,1"
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "CH4STATC,Channel 4 status clear regist"
|
|
bitfld.long 0x0 4. "TCFC,Channel x buffer transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 3. "BTCFC,Channel x buffer block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 2. "MBTCFC,Channel x buffer multi-block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 1. "CHTCFC,Channel x channel transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 0. "ERRC,Channel x transfer error flag clear" "0,1"
|
|
rgroup.long 0x148++0x3
|
|
line.long 0x0 "CH4STAT1,Channel 4 status register"
|
|
bitfld.long 0x0 11. "BZERR,Block size error flag" "0,1"
|
|
bitfld.long 0x0 10. "ASERR,Address and size error flag" "0,1"
|
|
bitfld.long 0x0 9. "MDTERR,Mask data error flag" "0,1"
|
|
bitfld.long 0x0 8. "LDTERR,Link data transfer error flag in the last transfer of the channel" "0,1"
|
|
bitfld.long 0x0 7. "TERRD,Transfer error direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ERRADDR,Transfer error address"
|
|
group.long 0x14C++0x1F
|
|
line.long 0x0 "CH4CTL0,Channel 4 control register"
|
|
bitfld.long 0x0 16. "SWREQ,Software request" "0,1"
|
|
bitfld.long 0x0 14. "WES,Word endianess swapping in double word" "0,1"
|
|
bitfld.long 0x0 13. "HWES,Half word endianess swapping in word" "0,1"
|
|
bitfld.long 0x0 12. "BES,Byte endianess swapping in half word" "0,1"
|
|
bitfld.long 0x0 8. "SMODEN,Secure mode enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TCIE,Buffer transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "BTCIE,Block transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MBTCIE,Multi-block transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "CHTCIE,Channel transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "ERRIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH4CFG,Channel 4 configure regist"
|
|
bitfld.long 0x4 31. "BWMOD,Bufferable write mode" "0,1"
|
|
bitfld.long 0x4 30. "SWREQMOD,Software request mode" "0,1"
|
|
bitfld.long 0x4 28.--29. "TRIGMOD,Trigger mode" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PAMOD,Padding and alignement mode" "0,1,2,3"
|
|
bitfld.long 0x4 25. "PKEN,Pack enable" "0,1"
|
|
hexmask.long.byte 0x4 18.--24. 1. "BTLEN,Buffer transfer length"
|
|
bitfld.long 0x4 15.--17. "DBURST,Transfer burst type of destination" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "SBURST,Transfer burst type of source" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "DIOS,Offset size of destination increment" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "SIOS,Offset size of source increment" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "DWIDTH,Data size of destination" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "SWIDTH,Data size of source" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "DIMOD,Destination increment mode" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SIMOD,Source increment mode" "0,1,2,3"
|
|
line.long 0x8 "CH4BTCFG,Channel 4 block transfer configure regist"
|
|
hexmask.long.word 0x8 20.--31. 1. "BRNUM,Multi-block number"
|
|
bitfld.long 0x8 19. "DADDRUM,Multi-block destination address update mode" "0,1"
|
|
bitfld.long 0x8 18. "SADDRUM,Multi-block source address update mode" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "TBNUM,Transfer byte number in block"
|
|
line.long 0xC "CH4SADDR,Channel 4 source address regist"
|
|
hexmask.long 0xC 0.--31. 1. "SADDR,Source address"
|
|
line.long 0x10 "CH4DADDR,Channel 4 destination address regist"
|
|
hexmask.long 0x10 0.--31. 1. "DADDR,Destination address"
|
|
line.long 0x14 "CH4MBADDRU,Channel 4 multi-block address update regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "DADDRUV,Destination address update value"
|
|
hexmask.long.word 0x14 0.--15. 1. "SADDRUV,Source address update value"
|
|
line.long 0x18 "CH4LADDR,Channel 4 link address regist"
|
|
hexmask.long 0x18 0.--31. 1. "LADDR,Link address"
|
|
line.long 0x1C "CH4CTL1,Channel 4 control register"
|
|
bitfld.long 0x1C 17. "DBSEL,Destination bus select" "0,1"
|
|
bitfld.long 0x1C 16. "SBSEL,Source bus select" "0,1"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "TRIGSEL,Trigger select"
|
|
group.long 0x170++0x7
|
|
line.long 0x0 "CH4MADDR,Channel 4 mask address regist"
|
|
hexmask.long 0x0 0.--31. 1. "MADDR,Mask address"
|
|
line.long 0x4 "CH4MDATA,Channel 4 mask data regist"
|
|
hexmask.long 0x4 0.--31. 1. "MDATA,Mask data"
|
|
rgroup.long 0x180++0x3
|
|
line.long 0x0 "CH5STAT0,Channel 5 status register"
|
|
bitfld.long 0x0 16. "REQAF,Channel x request active flag" "0,1"
|
|
bitfld.long 0x0 4. "TCF,Channel x buffer transfer complete flag" "0,1"
|
|
bitfld.long 0x0 3. "BTCF,Channel x block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 2. "MBTCF,Channel x multi-block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 1. "CHTCF,Channel x channel transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "ERR,Channel x transfer error flag" "0,1"
|
|
wgroup.long 0x184++0x3
|
|
line.long 0x0 "CH5STATC,Channel 5 status clear regist"
|
|
bitfld.long 0x0 4. "TCFC,Channel x buffer transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 3. "BTCFC,Channel x buffer block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 2. "MBTCFC,Channel x buffer multi-block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 1. "CHTCFC,Channel x channel transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 0. "ERRC,Channel x transfer error flag clear" "0,1"
|
|
rgroup.long 0x188++0x3
|
|
line.long 0x0 "CH5STAT1,Channel 5 status register"
|
|
bitfld.long 0x0 11. "BZERR,Block size error flag" "0,1"
|
|
bitfld.long 0x0 10. "ASERR,Address and size error flag" "0,1"
|
|
bitfld.long 0x0 9. "MDTERR,Mask data error flag" "0,1"
|
|
bitfld.long 0x0 8. "LDTERR,Link data transfer error flag in the last transfer of the channel" "0,1"
|
|
bitfld.long 0x0 7. "TERRD,Transfer error direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ERRADDR,Transfer error address"
|
|
group.long 0x18C++0x1F
|
|
line.long 0x0 "CH5CTL0,Channel 5 control register"
|
|
bitfld.long 0x0 16. "SWREQ,Software request" "0,1"
|
|
bitfld.long 0x0 14. "WES,Word endianess swapping in double word" "0,1"
|
|
bitfld.long 0x0 13. "HWES,Half word endianess swapping in word" "0,1"
|
|
bitfld.long 0x0 12. "BES,Byte endianess swapping in half word" "0,1"
|
|
bitfld.long 0x0 8. "SMODEN,Secure mode enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TCIE,Buffer transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "BTCIE,Block transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MBTCIE,Multi-block transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "CHTCIE,Channel transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "ERRIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH5CFG,Channel 5 configure regist"
|
|
bitfld.long 0x4 31. "BWMOD,Bufferable write mode" "0,1"
|
|
bitfld.long 0x4 30. "SWREQMOD,Software request mode" "0,1"
|
|
bitfld.long 0x4 28.--29. "TRIGMOD,Trigger mode" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PAMOD,Padding and alignement mode" "0,1,2,3"
|
|
bitfld.long 0x4 25. "PKEN,Pack enable" "0,1"
|
|
hexmask.long.byte 0x4 18.--24. 1. "BTLEN,Buffer transfer length"
|
|
bitfld.long 0x4 15.--17. "DBURST,Transfer burst type of destination" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "SBURST,Transfer burst type of source" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "DIOS,Offset size of destination increment" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "SIOS,Offset size of source increment" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "DWIDTH,Data size of destination" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "SWIDTH,Data size of source" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "DIMOD,Destination increment mode" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SIMOD,Source increment mode" "0,1,2,3"
|
|
line.long 0x8 "CH5BTCFG,Channel 5 block transfer configure regist"
|
|
hexmask.long.word 0x8 20.--31. 1. "BRNUM,Multi-block number"
|
|
bitfld.long 0x8 19. "DADDRUM,Multi-block destination address update mode" "0,1"
|
|
bitfld.long 0x8 18. "SADDRUM,Multi-block source address update mode" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "TBNUM,Transfer byte number in block"
|
|
line.long 0xC "CH5SADDR,Channel 5 source address regist"
|
|
hexmask.long 0xC 0.--31. 1. "SADDR,Source address"
|
|
line.long 0x10 "CH5DADDR,Channel 5 destination address regist"
|
|
hexmask.long 0x10 0.--31. 1. "DADDR,Destination address"
|
|
line.long 0x14 "CH5MBADDRU,Channel 5 multi-block address update regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "DADDRUV,Destination address update value"
|
|
hexmask.long.word 0x14 0.--15. 1. "SADDRUV,Source address update value"
|
|
line.long 0x18 "CH5LADDR,Channel 5 link address regist"
|
|
hexmask.long 0x18 0.--31. 1. "LADDR,Link address"
|
|
line.long 0x1C "CH5CTL1,Channel 5 control register"
|
|
bitfld.long 0x1C 17. "DBSEL,Destination bus select" "0,1"
|
|
bitfld.long 0x1C 16. "SBSEL,Source bus select" "0,1"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "TRIGSEL,Trigger select"
|
|
group.long 0x1B0++0x7
|
|
line.long 0x0 "CH5MADDR,Channel 5 mask address regist"
|
|
hexmask.long 0x0 0.--31. 1. "MADDR,Mask address"
|
|
line.long 0x4 "CH5MDATA,Channel 5 mask data regist"
|
|
hexmask.long 0x4 0.--31. 1. "MDATA,Mask data"
|
|
rgroup.long 0x1C0++0x3
|
|
line.long 0x0 "CH6STAT0,Channel 6 status register"
|
|
bitfld.long 0x0 16. "REQAF,Channel x request active flag" "0,1"
|
|
bitfld.long 0x0 4. "TCF,Channel x buffer transfer complete flag" "0,1"
|
|
bitfld.long 0x0 3. "BTCF,Channel x block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 2. "MBTCF,Channel x multi-block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 1. "CHTCF,Channel x channel transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "ERR,Channel x transfer error flag" "0,1"
|
|
wgroup.long 0x1C4++0x3
|
|
line.long 0x0 "CH6STATC,Channel 6 status clear regist"
|
|
bitfld.long 0x0 4. "TCFC,Channel x buffer transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 3. "BTCFC,Channel x buffer block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 2. "MBTCFC,Channel x buffer multi-block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 1. "CHTCFC,Channel x channel transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 0. "ERRC,Channel x transfer error flag clear" "0,1"
|
|
rgroup.long 0x1C8++0x3
|
|
line.long 0x0 "CH6STAT1,Channel 6 status register"
|
|
bitfld.long 0x0 11. "BZERR,Block size error flag" "0,1"
|
|
bitfld.long 0x0 10. "ASERR,Address and size error flag" "0,1"
|
|
bitfld.long 0x0 9. "MDTERR,Mask data error flag" "0,1"
|
|
bitfld.long 0x0 8. "LDTERR,Link data transfer error flag in the last transfer of the channel" "0,1"
|
|
bitfld.long 0x0 7. "TERRD,Transfer error direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ERRADDR,Transfer error address"
|
|
group.long 0x1CC++0x1F
|
|
line.long 0x0 "CH6CTL0,Channel 6 control register"
|
|
bitfld.long 0x0 16. "SWREQ,Software request" "0,1"
|
|
bitfld.long 0x0 14. "WES,Word endianess swapping in double word" "0,1"
|
|
bitfld.long 0x0 13. "HWES,Half word endianess swapping in word" "0,1"
|
|
bitfld.long 0x0 12. "BES,Byte endianess swapping in half word" "0,1"
|
|
bitfld.long 0x0 8. "SMODEN,Secure mode enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TCIE,Buffer transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "BTCIE,Block transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MBTCIE,Multi-block transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "CHTCIE,Channel transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "ERRIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH6CFG,Channel 6 configure regist"
|
|
bitfld.long 0x4 31. "BWMOD,Bufferable write mode" "0,1"
|
|
bitfld.long 0x4 30. "SWREQMOD,Software request mode" "0,1"
|
|
bitfld.long 0x4 28.--29. "TRIGMOD,Trigger mode" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PAMOD,Padding and alignement mode" "0,1,2,3"
|
|
bitfld.long 0x4 25. "PKEN,Pack enable" "0,1"
|
|
hexmask.long.byte 0x4 18.--24. 1. "BTLEN,Buffer transfer length"
|
|
bitfld.long 0x4 15.--17. "DBURST,Transfer burst type of destination" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "SBURST,Transfer burst type of source" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "DIOS,Offset size of destination increment" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "SIOS,Offset size of source increment" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "DWIDTH,Data size of destination" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "SWIDTH,Data size of source" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "DIMOD,Destination increment mode" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SIMOD,Source increment mode" "0,1,2,3"
|
|
line.long 0x8 "CH6BTCFG,Channel 6 block transfer configure regist"
|
|
hexmask.long.word 0x8 20.--31. 1. "BRNUM,Multi-block number"
|
|
bitfld.long 0x8 19. "DADDRUM,Multi-block destination address update mode" "0,1"
|
|
bitfld.long 0x8 18. "SADDRUM,Multi-block source address update mode" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "TBNUM,Transfer byte number in block"
|
|
line.long 0xC "CH6SADDR,Channel 6 source address regist"
|
|
hexmask.long 0xC 0.--31. 1. "SADDR,Source address"
|
|
line.long 0x10 "CH6DADDR,Channel 6 destination address regist"
|
|
hexmask.long 0x10 0.--31. 1. "DADDR,Destination address"
|
|
line.long 0x14 "CH6MBADDRU,Channel 6 multi-block address update regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "DADDRUV,Destination address update value"
|
|
hexmask.long.word 0x14 0.--15. 1. "SADDRUV,Source address update value"
|
|
line.long 0x18 "CH6LADDR,Channel 6 link address regist"
|
|
hexmask.long 0x18 0.--31. 1. "LADDR,Link address"
|
|
line.long 0x1C "CH6CTL1,Channel 6 control register"
|
|
bitfld.long 0x1C 17. "DBSEL,Destination bus select" "0,1"
|
|
bitfld.long 0x1C 16. "SBSEL,Source bus select" "0,1"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "TRIGSEL,Trigger select"
|
|
group.long 0x1F0++0x7
|
|
line.long 0x0 "CH6MADDR,Channel 6 mask address regist"
|
|
hexmask.long 0x0 0.--31. 1. "MADDR,Mask address"
|
|
line.long 0x4 "CH6MDATA,Channel 6 mask data regist"
|
|
hexmask.long 0x4 0.--31. 1. "MDATA,Mask data"
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x0 "CH7STAT0,Channel 7 status register"
|
|
bitfld.long 0x0 16. "REQAF,Channel x request active flag" "0,1"
|
|
bitfld.long 0x0 4. "TCF,Channel x buffer transfer complete flag" "0,1"
|
|
bitfld.long 0x0 3. "BTCF,Channel x block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 2. "MBTCF,Channel x multi-block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 1. "CHTCF,Channel x channel transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "ERR,Channel x transfer error flag" "0,1"
|
|
wgroup.long 0x204++0x3
|
|
line.long 0x0 "CH7STATC,Channel 7 status clear regist"
|
|
bitfld.long 0x0 4. "TCFC,Channel x buffer transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 3. "BTCFC,Channel x buffer block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 2. "MBTCFC,Channel x buffer multi-block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 1. "CHTCFC,Channel x channel transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 0. "ERRC,Channel x transfer error flag clear" "0,1"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x0 "CH7STAT1,Channel 7 status register"
|
|
bitfld.long 0x0 11. "BZERR,Block size error flag" "0,1"
|
|
bitfld.long 0x0 10. "ASERR,Address and size error flag" "0,1"
|
|
bitfld.long 0x0 9. "MDTERR,Mask data error flag" "0,1"
|
|
bitfld.long 0x0 8. "LDTERR,Link data transfer error flag in the last transfer of the channel" "0,1"
|
|
bitfld.long 0x0 7. "TERRD,Transfer error direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ERRADDR,Transfer error address"
|
|
group.long 0x20C++0x1F
|
|
line.long 0x0 "CH7CTL0,Channel 7 control register"
|
|
bitfld.long 0x0 16. "SWREQ,Software request" "0,1"
|
|
bitfld.long 0x0 14. "WES,Word endianess swapping in double word" "0,1"
|
|
bitfld.long 0x0 13. "HWES,Half word endianess swapping in word" "0,1"
|
|
bitfld.long 0x0 12. "BES,Byte endianess swapping in half word" "0,1"
|
|
bitfld.long 0x0 8. "SMODEN,Secure mode enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TCIE,Buffer transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "BTCIE,Block transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MBTCIE,Multi-block transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "CHTCIE,Channel transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "ERRIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH7CFG,Channel 7 configure regist"
|
|
bitfld.long 0x4 31. "BWMOD,Bufferable write mode" "0,1"
|
|
bitfld.long 0x4 30. "SWREQMOD,Software request mode" "0,1"
|
|
bitfld.long 0x4 28.--29. "TRIGMOD,Trigger mode" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PAMOD,Padding and alignement mode" "0,1,2,3"
|
|
bitfld.long 0x4 25. "PKEN,Pack enable" "0,1"
|
|
hexmask.long.byte 0x4 18.--24. 1. "BTLEN,Buffer transfer length"
|
|
bitfld.long 0x4 15.--17. "DBURST,Transfer burst type of destination" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "SBURST,Transfer burst type of source" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "DIOS,Offset size of destination increment" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "SIOS,Offset size of source increment" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "DWIDTH,Data size of destination" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "SWIDTH,Data size of source" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "DIMOD,Destination increment mode" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SIMOD,Source increment mode" "0,1,2,3"
|
|
line.long 0x8 "CH7BTCFG,Channel 7 block transfer configure regist"
|
|
hexmask.long.word 0x8 20.--31. 1. "BRNUM,Multi-block number"
|
|
bitfld.long 0x8 19. "DADDRUM,Multi-block destination address update mode" "0,1"
|
|
bitfld.long 0x8 18. "SADDRUM,Multi-block source address update mode" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "TBNUM,Transfer byte number in block"
|
|
line.long 0xC "CH7SADDR,Channel 7 source address regist"
|
|
hexmask.long 0xC 0.--31. 1. "SADDR,Source address"
|
|
line.long 0x10 "CH7DADDR,Channel 7 destination address regist"
|
|
hexmask.long 0x10 0.--31. 1. "DADDR,Destination address"
|
|
line.long 0x14 "CH7MBADDRU,Channel 7 multi-block address update regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "DADDRUV,Destination address update value"
|
|
hexmask.long.word 0x14 0.--15. 1. "SADDRUV,Source address update value"
|
|
line.long 0x18 "CH7LADDR,Channel 7 link address regist"
|
|
hexmask.long 0x18 0.--31. 1. "LADDR,Link address"
|
|
line.long 0x1C "CH7CTL1,Channel 7 control register"
|
|
bitfld.long 0x1C 17. "DBSEL,Destination bus select" "0,1"
|
|
bitfld.long 0x1C 16. "SBSEL,Source bus select" "0,1"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "TRIGSEL,Trigger select"
|
|
group.long 0x230++0x7
|
|
line.long 0x0 "CH7MADDR,Channel 7 mask address regist"
|
|
hexmask.long 0x0 0.--31. 1. "MADDR,Mask address"
|
|
line.long 0x4 "CH7MDATA,Channel 7 mask data regist"
|
|
hexmask.long 0x4 0.--31. 1. "MDATA,Mask data"
|
|
rgroup.long 0x240++0x3
|
|
line.long 0x0 "CH8STAT0,Channel 8 status register"
|
|
bitfld.long 0x0 16. "REQAF,Channel x request active flag" "0,1"
|
|
bitfld.long 0x0 4. "TCF,Channel x buffer transfer complete flag" "0,1"
|
|
bitfld.long 0x0 3. "BTCF,Channel x block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 2. "MBTCF,Channel x multi-block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 1. "CHTCF,Channel x channel transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "ERR,Channel x transfer error flag" "0,1"
|
|
wgroup.long 0x244++0x3
|
|
line.long 0x0 "CH8STATC,Channel 8 status clear regist"
|
|
bitfld.long 0x0 4. "TCFC,Channel x buffer transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 3. "BTCFC,Channel x buffer block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 2. "MBTCFC,Channel x buffer multi-block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 1. "CHTCFC,Channel x channel transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 0. "ERRC,Channel x transfer error flag clear" "0,1"
|
|
rgroup.long 0x248++0x3
|
|
line.long 0x0 "CH8STAT1,Channel 8 status register"
|
|
bitfld.long 0x0 11. "BZERR,Block size error flag" "0,1"
|
|
bitfld.long 0x0 10. "ASERR,Address and size error flag" "0,1"
|
|
bitfld.long 0x0 9. "MDTERR,Mask data error flag" "0,1"
|
|
bitfld.long 0x0 8. "LDTERR,Link data transfer error flag in the last transfer of the channel" "0,1"
|
|
bitfld.long 0x0 7. "TERRD,Transfer error direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ERRADDR,Transfer error address"
|
|
group.long 0x24C++0x1F
|
|
line.long 0x0 "CH8CTL0,Channel 8 control register"
|
|
bitfld.long 0x0 16. "SWREQ,Software request" "0,1"
|
|
bitfld.long 0x0 14. "WES,Word endianess swapping in double word" "0,1"
|
|
bitfld.long 0x0 13. "HWES,Half word endianess swapping in word" "0,1"
|
|
bitfld.long 0x0 12. "BES,Byte endianess swapping in half word" "0,1"
|
|
bitfld.long 0x0 8. "SMODEN,Secure mode enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TCIE,Buffer transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "BTCIE,Block transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MBTCIE,Multi-block transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "CHTCIE,Channel transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "ERRIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH8CFG,Channel 8 configure regist"
|
|
bitfld.long 0x4 31. "BWMOD,Bufferable write mode" "0,1"
|
|
bitfld.long 0x4 30. "SWREQMOD,Software request mode" "0,1"
|
|
bitfld.long 0x4 28.--29. "TRIGMOD,Trigger mode" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PAMOD,Padding and alignement mode" "0,1,2,3"
|
|
bitfld.long 0x4 25. "PKEN,Pack enable" "0,1"
|
|
hexmask.long.byte 0x4 18.--24. 1. "BTLEN,Buffer transfer length"
|
|
bitfld.long 0x4 15.--17. "DBURST,Transfer burst type of destination" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "SBURST,Transfer burst type of source" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "DIOS,Offset size of destination increment" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "SIOS,Offset size of source increment" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "DWIDTH,Data size of destination" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "SWIDTH,Data size of source" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "DIMOD,Destination increment mode" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SIMOD,Source increment mode" "0,1,2,3"
|
|
line.long 0x8 "CH8BTCFG,Channel 8 block transfer configure regist"
|
|
hexmask.long.word 0x8 20.--31. 1. "BRNUM,Multi-block number"
|
|
bitfld.long 0x8 19. "DADDRUM,Multi-block destination address update mode" "0,1"
|
|
bitfld.long 0x8 18. "SADDRUM,Multi-block source address update mode" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "TBNUM,Transfer byte number in block"
|
|
line.long 0xC "CH8SADDR,Channel 8 source address regist"
|
|
hexmask.long 0xC 0.--31. 1. "SADDR,Source address"
|
|
line.long 0x10 "CH8DADDR,Channel 8 destination address regist"
|
|
hexmask.long 0x10 0.--31. 1. "DADDR,Destination address"
|
|
line.long 0x14 "CH8MBADDRU,Channel 8 multi-block address update regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "DADDRUV,Destination address update value"
|
|
hexmask.long.word 0x14 0.--15. 1. "SADDRUV,Source address update value"
|
|
line.long 0x18 "CH8LADDR,Channel 8 link address regist"
|
|
hexmask.long 0x18 0.--31. 1. "LADDR,Link address"
|
|
line.long 0x1C "CH8CTL1,Channel 8 control register"
|
|
bitfld.long 0x1C 17. "DBSEL,Destination bus select" "0,1"
|
|
bitfld.long 0x1C 16. "SBSEL,Source bus select" "0,1"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "TRIGSEL,Trigger select"
|
|
group.long 0x270++0x7
|
|
line.long 0x0 "CH8MADDR,Channel 8 mask address regist"
|
|
hexmask.long 0x0 0.--31. 1. "MADDR,Mask address"
|
|
line.long 0x4 "CH8MDATA,Channel 8 mask data regist"
|
|
hexmask.long 0x4 0.--31. 1. "MDATA,Mask data"
|
|
rgroup.long 0x280++0x3
|
|
line.long 0x0 "CH9STAT0,Channel 9 status register"
|
|
bitfld.long 0x0 16. "REQAF,Channel x request active flag" "0,1"
|
|
bitfld.long 0x0 4. "TCF,Channel x buffer transfer complete flag" "0,1"
|
|
bitfld.long 0x0 3. "BTCF,Channel x block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 2. "MBTCF,Channel x multi-block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 1. "CHTCF,Channel x channel transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "ERR,Channel x transfer error flag" "0,1"
|
|
wgroup.long 0x284++0x3
|
|
line.long 0x0 "CH9STATC,Channel 9 status clear regist"
|
|
bitfld.long 0x0 4. "TCFC,Channel x buffer transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 3. "BTCFC,Channel x buffer block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 2. "MBTCFC,Channel x buffer multi-block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 1. "CHTCFC,Channel x channel transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 0. "ERRC,Channel x transfer error flag clear" "0,1"
|
|
rgroup.long 0x288++0x3
|
|
line.long 0x0 "CH9STAT1,Channel 9 status register"
|
|
bitfld.long 0x0 11. "BZERR,Block size error flag" "0,1"
|
|
bitfld.long 0x0 10. "ASERR,Address and size error flag" "0,1"
|
|
bitfld.long 0x0 9. "MDTERR,Mask data error flag" "0,1"
|
|
bitfld.long 0x0 8. "LDTERR,Link data transfer error flag in the last transfer of the channel" "0,1"
|
|
bitfld.long 0x0 7. "TERRD,Transfer error direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ERRADDR,Transfer error address"
|
|
group.long 0x28C++0x1F
|
|
line.long 0x0 "CH9CTL0,Channel 9 control register"
|
|
bitfld.long 0x0 16. "SWREQ,Software request" "0,1"
|
|
bitfld.long 0x0 14. "WES,Word endianess swapping in double word" "0,1"
|
|
bitfld.long 0x0 13. "HWES,Half word endianess swapping in word" "0,1"
|
|
bitfld.long 0x0 12. "BES,Byte endianess swapping in half word" "0,1"
|
|
bitfld.long 0x0 8. "SMODEN,Secure mode enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TCIE,Buffer transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "BTCIE,Block transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MBTCIE,Multi-block transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "CHTCIE,Channel transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "ERRIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH9CFG,Channel 9 configure regist"
|
|
bitfld.long 0x4 31. "BWMOD,Bufferable write mode" "0,1"
|
|
bitfld.long 0x4 30. "SWREQMOD,Software request mode" "0,1"
|
|
bitfld.long 0x4 28.--29. "TRIGMOD,Trigger mode" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PAMOD,Padding and alignement mode" "0,1,2,3"
|
|
bitfld.long 0x4 25. "PKEN,Pack enable" "0,1"
|
|
hexmask.long.byte 0x4 18.--24. 1. "BTLEN,Buffer transfer length"
|
|
bitfld.long 0x4 15.--17. "DBURST,Transfer burst type of destination" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "SBURST,Transfer burst type of source" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "DIOS,Offset size of destination increment" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "SIOS,Offset size of source increment" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "DWIDTH,Data size of destination" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "SWIDTH,Data size of source" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "DIMOD,Destination increment mode" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SIMOD,Source increment mode" "0,1,2,3"
|
|
line.long 0x8 "CH9BTCFG,Channel 9 block transfer configure regist"
|
|
hexmask.long.word 0x8 20.--31. 1. "BRNUM,Multi-block number"
|
|
bitfld.long 0x8 19. "DADDRUM,Multi-block destination address update mode" "0,1"
|
|
bitfld.long 0x8 18. "SADDRUM,Multi-block source address update mode" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "TBNUM,Transfer byte number in block"
|
|
line.long 0xC "CH9SADDR,Channel 9 source address regist"
|
|
hexmask.long 0xC 0.--31. 1. "SADDR,Source address"
|
|
line.long 0x10 "CH9DADDR,Channel 9 destination address regist"
|
|
hexmask.long 0x10 0.--31. 1. "DADDR,Destination address"
|
|
line.long 0x14 "CH9MBADDRU,Channel 9 multi-block address update regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "DADDRUV,Destination address update value"
|
|
hexmask.long.word 0x14 0.--15. 1. "SADDRUV,Source address update value"
|
|
line.long 0x18 "CH9LADDR,Channel 9 link address regist"
|
|
hexmask.long 0x18 0.--31. 1. "LADDR,Link address"
|
|
line.long 0x1C "CH9CTL1,Channel 9 control register"
|
|
bitfld.long 0x1C 17. "DBSEL,Destination bus select" "0,1"
|
|
bitfld.long 0x1C 16. "SBSEL,Source bus select" "0,1"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "TRIGSEL,Trigger select"
|
|
group.long 0x2B0++0x7
|
|
line.long 0x0 "CH9MADDR,Channel 9 mask address regist"
|
|
hexmask.long 0x0 0.--31. 1. "MADDR,Mask address"
|
|
line.long 0x4 "CH9MDATA,Channel 9 mask data regist"
|
|
hexmask.long 0x4 0.--31. 1. "MDATA,Mask data"
|
|
rgroup.long 0x2C0++0x3
|
|
line.long 0x0 "CH10STAT0,Channel 10 status register"
|
|
bitfld.long 0x0 16. "REQAF,Channel x request active flag" "0,1"
|
|
bitfld.long 0x0 4. "TCF,Channel x buffer transfer complete flag" "0,1"
|
|
bitfld.long 0x0 3. "BTCF,Channel x block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 2. "MBTCF,Channel x multi-block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 1. "CHTCF,Channel x channel transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "ERR,Channel x transfer error flag" "0,1"
|
|
wgroup.long 0x2C4++0x3
|
|
line.long 0x0 "CH10STATC,Channel 10 status clear regist"
|
|
bitfld.long 0x0 4. "TCFC,Channel x buffer transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 3. "BTCFC,Channel x buffer block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 2. "MBTCFC,Channel x buffer multi-block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 1. "CHTCFC,Channel x channel transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 0. "ERRC,Channel x transfer error flag clear" "0,1"
|
|
rgroup.long 0x2C8++0x3
|
|
line.long 0x0 "CH10STAT1,Channel 10 status register"
|
|
bitfld.long 0x0 11. "BZERR,Block size error flag" "0,1"
|
|
bitfld.long 0x0 10. "ASERR,Address and size error flag" "0,1"
|
|
bitfld.long 0x0 9. "MDTERR,Mask data error flag" "0,1"
|
|
bitfld.long 0x0 8. "LDTERR,Link data transfer error flag in the last transfer of the channel" "0,1"
|
|
bitfld.long 0x0 7. "TERRD,Transfer error direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ERRADDR,Transfer error address"
|
|
group.long 0x2CC++0x1F
|
|
line.long 0x0 "CH10CTL0,Channel 10 control register"
|
|
bitfld.long 0x0 16. "SWREQ,Software request" "0,1"
|
|
bitfld.long 0x0 14. "WES,Word endianess swapping in double word" "0,1"
|
|
bitfld.long 0x0 13. "HWES,Half word endianess swapping in word" "0,1"
|
|
bitfld.long 0x0 12. "BES,Byte endianess swapping in half word" "0,1"
|
|
bitfld.long 0x0 8. "SMODEN,Secure mode enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TCIE,Buffer transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "BTCIE,Block transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MBTCIE,Multi-block transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "CHTCIE,Channel transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "ERRIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH10CFG,Channel 10 configure regist"
|
|
bitfld.long 0x4 31. "BWMOD,Bufferable write mode" "0,1"
|
|
bitfld.long 0x4 30. "SWREQMOD,Software request mode" "0,1"
|
|
bitfld.long 0x4 28.--29. "TRIGMOD,Trigger mode" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PAMOD,Padding and alignement mode" "0,1,2,3"
|
|
bitfld.long 0x4 25. "PKEN,Pack enable" "0,1"
|
|
hexmask.long.byte 0x4 18.--24. 1. "BTLEN,Buffer transfer length"
|
|
bitfld.long 0x4 15.--17. "DBURST,Transfer burst type of destination" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "SBURST,Transfer burst type of source" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "DIOS,Offset size of destination increment" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "SIOS,Offset size of source increment" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "DWIDTH,Data size of destination" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "SWIDTH,Data size of source" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "DIMOD,Destination increment mode" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SIMOD,Source increment mode" "0,1,2,3"
|
|
line.long 0x8 "CH10BTCFG,Channel 10 block transfer configure regist"
|
|
hexmask.long.word 0x8 20.--31. 1. "BRNUM,Multi-block number"
|
|
bitfld.long 0x8 19. "DADDRUM,Multi-block destination address update mode" "0,1"
|
|
bitfld.long 0x8 18. "SADDRUM,Multi-block source address update mode" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "TBNUM,Transfer byte number in block"
|
|
line.long 0xC "CH10SADDR,Channel 10 source address regist"
|
|
hexmask.long 0xC 0.--31. 1. "SADDR,Source address"
|
|
line.long 0x10 "CH10DADDR,Channel 10 destination address regist"
|
|
hexmask.long 0x10 0.--31. 1. "DADDR,Destination address"
|
|
line.long 0x14 "CH10MBADDRU,Channel 10 multi-block address update regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "DADDRUV,Destination address update value"
|
|
hexmask.long.word 0x14 0.--15. 1. "SADDRUV,Source address update value"
|
|
line.long 0x18 "CH10LADDR,Channel 10 link address regist"
|
|
hexmask.long 0x18 0.--31. 1. "LADDR,Link address"
|
|
line.long 0x1C "CH10CTL1,Channel 10 control register"
|
|
bitfld.long 0x1C 17. "DBSEL,Destination bus select" "0,1"
|
|
bitfld.long 0x1C 16. "SBSEL,Source bus select" "0,1"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "TRIGSEL,Trigger select"
|
|
group.long 0x2F0++0x7
|
|
line.long 0x0 "CH10MADDR,Channel 10 mask address regist"
|
|
hexmask.long 0x0 0.--31. 1. "MADDR,Mask address"
|
|
line.long 0x4 "CH10MDATA,Channel 10 mask data regist"
|
|
hexmask.long 0x4 0.--31. 1. "MDATA,Mask data"
|
|
rgroup.long 0x300++0x3
|
|
line.long 0x0 "CH11STAT0,Channel 11 status register"
|
|
bitfld.long 0x0 16. "REQAF,Channel x request active flag" "0,1"
|
|
bitfld.long 0x0 4. "TCF,Channel x buffer transfer complete flag" "0,1"
|
|
bitfld.long 0x0 3. "BTCF,Channel x block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 2. "MBTCF,Channel x multi-block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 1. "CHTCF,Channel x channel transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "ERR,Channel x transfer error flag" "0,1"
|
|
wgroup.long 0x304++0x3
|
|
line.long 0x0 "CH11STATC,Channel 11 status clear regist"
|
|
bitfld.long 0x0 4. "TCFC,Channel x buffer transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 3. "BTCFC,Channel x buffer block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 2. "MBTCFC,Channel x buffer multi-block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 1. "CHTCFC,Channel x channel transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 0. "ERRC,Channel x transfer error flag clear" "0,1"
|
|
rgroup.long 0x308++0x3
|
|
line.long 0x0 "CH11STAT1,Channel 11 status register"
|
|
bitfld.long 0x0 11. "BZERR,Block size error flag" "0,1"
|
|
bitfld.long 0x0 10. "ASERR,Address and size error flag" "0,1"
|
|
bitfld.long 0x0 9. "MDTERR,Mask data error flag" "0,1"
|
|
bitfld.long 0x0 8. "LDTERR,Link data transfer error flag in the last transfer of the channel" "0,1"
|
|
bitfld.long 0x0 7. "TERRD,Transfer error direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ERRADDR,Transfer error address"
|
|
group.long 0x30C++0x1F
|
|
line.long 0x0 "CH11CTL0,Channel 11 control register"
|
|
bitfld.long 0x0 16. "SWREQ,Software request" "0,1"
|
|
bitfld.long 0x0 14. "WES,Word endianess swapping in double word" "0,1"
|
|
bitfld.long 0x0 13. "HWES,Half word endianess swapping in word" "0,1"
|
|
bitfld.long 0x0 12. "BES,Byte endianess swapping in half word" "0,1"
|
|
bitfld.long 0x0 8. "SMODEN,Secure mode enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TCIE,Buffer transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "BTCIE,Block transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MBTCIE,Multi-block transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "CHTCIE,Channel transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "ERRIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH11CFG,Channel 11 configure regist"
|
|
bitfld.long 0x4 31. "BWMOD,Bufferable write mode" "0,1"
|
|
bitfld.long 0x4 30. "SWREQMOD,Software request mode" "0,1"
|
|
bitfld.long 0x4 28.--29. "TRIGMOD,Trigger mode" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PAMOD,Padding and alignement mode" "0,1,2,3"
|
|
bitfld.long 0x4 25. "PKEN,Pack enable" "0,1"
|
|
hexmask.long.byte 0x4 18.--24. 1. "BTLEN,Buffer transfer length"
|
|
bitfld.long 0x4 15.--17. "DBURST,Transfer burst type of destination" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "SBURST,Transfer burst type of source" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "DIOS,Offset size of destination increment" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "SIOS,Offset size of source increment" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "DWIDTH,Data size of destination" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "SWIDTH,Data size of source" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "DIMOD,Destination increment mode" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SIMOD,Source increment mode" "0,1,2,3"
|
|
line.long 0x8 "CH11BTCFG,Channel 11 block transfer configure regist"
|
|
hexmask.long.word 0x8 20.--31. 1. "BRNUM,Multi-block number"
|
|
bitfld.long 0x8 19. "DADDRUM,Multi-block destination address update mode" "0,1"
|
|
bitfld.long 0x8 18. "SADDRUM,Multi-block source address update mode" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "TBNUM,Transfer byte number in block"
|
|
line.long 0xC "CH11SADDR,Channel 11 source address regist"
|
|
hexmask.long 0xC 0.--31. 1. "SADDR,Source address"
|
|
line.long 0x10 "CH11DADDR,Channel 11 destination address regist"
|
|
hexmask.long 0x10 0.--31. 1. "DADDR,Destination address"
|
|
line.long 0x14 "CH11MBADDRU,Channel 11 multi-block address update regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "DADDRUV,Destination address update value"
|
|
hexmask.long.word 0x14 0.--15. 1. "SADDRUV,Source address update value"
|
|
line.long 0x18 "CH11LADDR,Channel 11 link address regist"
|
|
hexmask.long 0x18 0.--31. 1. "LADDR,Link address"
|
|
line.long 0x1C "CH11CTL1,Channel 11 control register"
|
|
bitfld.long 0x1C 17. "DBSEL,Destination bus select" "0,1"
|
|
bitfld.long 0x1C 16. "SBSEL,Source bus select" "0,1"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "TRIGSEL,Trigger select"
|
|
group.long 0x330++0x7
|
|
line.long 0x0 "CH11MADDR,Channel 11 mask address regist"
|
|
hexmask.long 0x0 0.--31. 1. "MADDR,Mask address"
|
|
line.long 0x4 "CH11MDATA,Channel 11 mask data regist"
|
|
hexmask.long 0x4 0.--31. 1. "MDATA,Mask data"
|
|
rgroup.long 0x340++0x3
|
|
line.long 0x0 "CH12STAT0,Channel 12 status register"
|
|
bitfld.long 0x0 16. "REQAF,Channel x request active flag" "0,1"
|
|
bitfld.long 0x0 4. "TCF,Channel x buffer transfer complete flag" "0,1"
|
|
bitfld.long 0x0 3. "BTCF,Channel x block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 2. "MBTCF,Channel x multi-block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 1. "CHTCF,Channel x channel transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "ERR,Channel x transfer error flag" "0,1"
|
|
wgroup.long 0x344++0x3
|
|
line.long 0x0 "CH12STATC,Channel 12 status clear regist"
|
|
bitfld.long 0x0 4. "TCFC,Channel x buffer transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 3. "BTCFC,Channel x buffer block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 2. "MBTCFC,Channel x buffer multi-block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 1. "CHTCFC,Channel x channel transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 0. "ERRC,Channel x transfer error flag clear" "0,1"
|
|
rgroup.long 0x348++0x3
|
|
line.long 0x0 "CH12STAT1,Channel 12 status register"
|
|
bitfld.long 0x0 11. "BZERR,Block size error flag" "0,1"
|
|
bitfld.long 0x0 10. "ASERR,Address and size error flag" "0,1"
|
|
bitfld.long 0x0 9. "MDTERR,Mask data error flag" "0,1"
|
|
bitfld.long 0x0 8. "LDTERR,Link data transfer error flag in the last transfer of the channel" "0,1"
|
|
bitfld.long 0x0 7. "TERRD,Transfer error direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ERRADDR,Transfer error address"
|
|
group.long 0x34C++0x1F
|
|
line.long 0x0 "CH12CTL0,Channel 12 control register"
|
|
bitfld.long 0x0 16. "SWREQ,Software request" "0,1"
|
|
bitfld.long 0x0 14. "WES,Word endianess swapping in double word" "0,1"
|
|
bitfld.long 0x0 13. "HWES,Half word endianess swapping in word" "0,1"
|
|
bitfld.long 0x0 12. "BES,Byte endianess swapping in half word" "0,1"
|
|
bitfld.long 0x0 8. "SMODEN,Secure mode enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TCIE,Buffer transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "BTCIE,Block transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MBTCIE,Multi-block transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "CHTCIE,Channel transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "ERRIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH12CFG,Channel 12 configure regist"
|
|
bitfld.long 0x4 31. "BWMOD,Bufferable write mode" "0,1"
|
|
bitfld.long 0x4 30. "SWREQMOD,Software request mode" "0,1"
|
|
bitfld.long 0x4 28.--29. "TRIGMOD,Trigger mode" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PAMOD,Padding and alignement mode" "0,1,2,3"
|
|
bitfld.long 0x4 25. "PKEN,Pack enable" "0,1"
|
|
hexmask.long.byte 0x4 18.--24. 1. "BTLEN,Buffer transfer length"
|
|
bitfld.long 0x4 15.--17. "DBURST,Transfer burst type of destination" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "SBURST,Transfer burst type of source" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "DIOS,Offset size of destination increment" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "SIOS,Offset size of source increment" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "DWIDTH,Data size of destination" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "SWIDTH,Data size of source" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "DIMOD,Destination increment mode" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SIMOD,Source increment mode" "0,1,2,3"
|
|
line.long 0x8 "CH12BTCFG,Channel 12 block transfer configure regist"
|
|
hexmask.long.word 0x8 20.--31. 1. "BRNUM,Multi-block number"
|
|
bitfld.long 0x8 19. "DADDRUM,Multi-block destination address update mode" "0,1"
|
|
bitfld.long 0x8 18. "SADDRUM,Multi-block source address update mode" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "TBNUM,Transfer byte number in block"
|
|
line.long 0xC "CH12SADDR,Channel 12 source address regist"
|
|
hexmask.long 0xC 0.--31. 1. "SADDR,Source address"
|
|
line.long 0x10 "CH12DADDR,Channel 12 destination address regist"
|
|
hexmask.long 0x10 0.--31. 1. "DADDR,Destination address"
|
|
line.long 0x14 "CH12MBADDRU,Channel 12 multi-block address update regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "DADDRUV,Destination address update value"
|
|
hexmask.long.word 0x14 0.--15. 1. "SADDRUV,Source address update value"
|
|
line.long 0x18 "CH12LADDR,Channel 12 link address regist"
|
|
hexmask.long 0x18 0.--31. 1. "LADDR,Link address"
|
|
line.long 0x1C "CH12CTL1,Channel 12 control register"
|
|
bitfld.long 0x1C 17. "DBSEL,Destination bus select" "0,1"
|
|
bitfld.long 0x1C 16. "SBSEL,Source bus select" "0,1"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "TRIGSEL,Trigger select"
|
|
group.long 0x370++0x7
|
|
line.long 0x0 "CH12MADDR,Channel 12 mask address regist"
|
|
hexmask.long 0x0 0.--31. 1. "MADDR,Mask address"
|
|
line.long 0x4 "CH12MDATA,Channel 12 mask data regist"
|
|
hexmask.long 0x4 0.--31. 1. "MDATA,Mask data"
|
|
rgroup.long 0x380++0x3
|
|
line.long 0x0 "CH13STAT0,Channel 13 status register"
|
|
bitfld.long 0x0 16. "REQAF,Channel x request active flag" "0,1"
|
|
bitfld.long 0x0 4. "TCF,Channel x buffer transfer complete flag" "0,1"
|
|
bitfld.long 0x0 3. "BTCF,Channel x block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 2. "MBTCF,Channel x multi-block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 1. "CHTCF,Channel x channel transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "ERR,Channel x transfer error flag" "0,1"
|
|
wgroup.long 0x384++0x3
|
|
line.long 0x0 "CH13STATC,Channel 13 status clear regist"
|
|
bitfld.long 0x0 4. "TCFC,Channel x buffer transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 3. "BTCFC,Channel x buffer block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 2. "MBTCFC,Channel x buffer multi-block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 1. "CHTCFC,Channel x channel transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 0. "ERRC,Channel x transfer error flag clear" "0,1"
|
|
rgroup.long 0x388++0x3
|
|
line.long 0x0 "CH13STAT1,Channel 13 status register"
|
|
bitfld.long 0x0 11. "BZERR,Block size error flag" "0,1"
|
|
bitfld.long 0x0 10. "ASERR,Address and size error flag" "0,1"
|
|
bitfld.long 0x0 9. "MDTERR,Mask data error flag" "0,1"
|
|
bitfld.long 0x0 8. "LDTERR,Link data transfer error flag in the last transfer of the channel" "0,1"
|
|
bitfld.long 0x0 7. "TERRD,Transfer error direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ERRADDR,Transfer error address"
|
|
group.long 0x38C++0x1F
|
|
line.long 0x0 "CH13CTL0,Channel 13 control register"
|
|
bitfld.long 0x0 16. "SWREQ,Software request" "0,1"
|
|
bitfld.long 0x0 14. "WES,Word endianess swapping in double word" "0,1"
|
|
bitfld.long 0x0 13. "HWES,Half word endianess swapping in word" "0,1"
|
|
bitfld.long 0x0 12. "BES,Byte endianess swapping in half word" "0,1"
|
|
bitfld.long 0x0 8. "SMODEN,Secure mode enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TCIE,Buffer transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "BTCIE,Block transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MBTCIE,Multi-block transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "CHTCIE,Channel transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "ERRIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH13CFG,Channel 13 configure regist"
|
|
bitfld.long 0x4 31. "BWMOD,Bufferable write mode" "0,1"
|
|
bitfld.long 0x4 30. "SWREQMOD,Software request mode" "0,1"
|
|
bitfld.long 0x4 28.--29. "TRIGMOD,Trigger mode" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PAMOD,Padding and alignement mode" "0,1,2,3"
|
|
bitfld.long 0x4 25. "PKEN,Pack enable" "0,1"
|
|
hexmask.long.byte 0x4 18.--24. 1. "BTLEN,Buffer transfer length"
|
|
bitfld.long 0x4 15.--17. "DBURST,Transfer burst type of destination" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "SBURST,Transfer burst type of source" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "DIOS,Offset size of destination increment" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "SIOS,Offset size of source increment" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "DWIDTH,Data size of destination" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "SWIDTH,Data size of source" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "DIMOD,Destination increment mode" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SIMOD,Source increment mode" "0,1,2,3"
|
|
line.long 0x8 "CH13BTCFG,Channel 13 block transfer configure regist"
|
|
hexmask.long.word 0x8 20.--31. 1. "BRNUM,Multi-block number"
|
|
bitfld.long 0x8 19. "DADDRUM,Multi-block destination address update mode" "0,1"
|
|
bitfld.long 0x8 18. "SADDRUM,Multi-block source address update mode" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "TBNUM,Transfer byte number in block"
|
|
line.long 0xC "CH13SADDR,Channel 13 source address regist"
|
|
hexmask.long 0xC 0.--31. 1. "SADDR,Source address"
|
|
line.long 0x10 "CH13DADDR,Channel 13 destination address regist"
|
|
hexmask.long 0x10 0.--31. 1. "DADDR,Destination address"
|
|
line.long 0x14 "CH13MBADDRU,Channel 13 multi-block address update regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "DADDRUV,Destination address update value"
|
|
hexmask.long.word 0x14 0.--15. 1. "SADDRUV,Source address update value"
|
|
line.long 0x18 "CH13LADDR,Channel 13 link address regist"
|
|
hexmask.long 0x18 0.--31. 1. "LADDR,Link address"
|
|
line.long 0x1C "CH13CTL1,Channel 13 control register"
|
|
bitfld.long 0x1C 17. "DBSEL,Destination bus select" "0,1"
|
|
bitfld.long 0x1C 16. "SBSEL,Source bus select" "0,1"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "TRIGSEL,Trigger select"
|
|
group.long 0x3B0++0x7
|
|
line.long 0x0 "CH13MADDR,Channel 13 mask address regist"
|
|
hexmask.long 0x0 0.--31. 1. "MADDR,Mask address"
|
|
line.long 0x4 "CH13MDATA,Channel 13 mask data regist"
|
|
hexmask.long 0x4 0.--31. 1. "MDATA,Mask data"
|
|
rgroup.long 0x3C0++0x3
|
|
line.long 0x0 "CH14STAT0,Channel 14 status register"
|
|
bitfld.long 0x0 16. "REQAF,Channel x request active flag" "0,1"
|
|
bitfld.long 0x0 4. "TCF,Channel x buffer transfer complete flag" "0,1"
|
|
bitfld.long 0x0 3. "BTCF,Channel x block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 2. "MBTCF,Channel x multi-block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 1. "CHTCF,Channel x channel transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "ERR,Channel x transfer error flag" "0,1"
|
|
wgroup.long 0x3C4++0x3
|
|
line.long 0x0 "CH14STATC,Channel 14 status clear regist"
|
|
bitfld.long 0x0 4. "TCFC,Channel x buffer transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 3. "BTCFC,Channel x buffer block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 2. "MBTCFC,Channel x buffer multi-block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 1. "CHTCFC,Channel x channel transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 0. "ERRC,Channel x transfer error flag clear" "0,1"
|
|
rgroup.long 0x3C8++0x3
|
|
line.long 0x0 "CH14STAT1,Channel 14 status register"
|
|
bitfld.long 0x0 11. "BZERR,Block size error flag" "0,1"
|
|
bitfld.long 0x0 10. "ASERR,Address and size error flag" "0,1"
|
|
bitfld.long 0x0 9. "MDTERR,Mask data error flag" "0,1"
|
|
bitfld.long 0x0 8. "LDTERR,Link data transfer error flag in the last transfer of the channel" "0,1"
|
|
bitfld.long 0x0 7. "TERRD,Transfer error direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ERRADDR,Transfer error address"
|
|
group.long 0x3CC++0x1F
|
|
line.long 0x0 "CH14CTL0,Channel 14 control register"
|
|
bitfld.long 0x0 16. "SWREQ,Software request" "0,1"
|
|
bitfld.long 0x0 14. "WES,Word endianess swapping in double word" "0,1"
|
|
bitfld.long 0x0 13. "HWES,Half word endianess swapping in word" "0,1"
|
|
bitfld.long 0x0 12. "BES,Byte endianess swapping in half word" "0,1"
|
|
bitfld.long 0x0 8. "SMODEN,Secure mode enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TCIE,Buffer transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "BTCIE,Block transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MBTCIE,Multi-block transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "CHTCIE,Channel transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "ERRIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH14CFG,Channel 14 configure regist"
|
|
bitfld.long 0x4 31. "BWMOD,Bufferable write mode" "0,1"
|
|
bitfld.long 0x4 30. "SWREQMOD,Software request mode" "0,1"
|
|
bitfld.long 0x4 28.--29. "TRIGMOD,Trigger mode" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PAMOD,Padding and alignement mode" "0,1,2,3"
|
|
bitfld.long 0x4 25. "PKEN,Pack enable" "0,1"
|
|
hexmask.long.byte 0x4 18.--24. 1. "BTLEN,Buffer transfer length"
|
|
bitfld.long 0x4 15.--17. "DBURST,Transfer burst type of destination" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "SBURST,Transfer burst type of source" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "DIOS,Offset size of destination increment" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "SIOS,Offset size of source increment" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "DWIDTH,Data size of destination" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "SWIDTH,Data size of source" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "DIMOD,Destination increment mode" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SIMOD,Source increment mode" "0,1,2,3"
|
|
line.long 0x8 "CH14BTCFG,Channel 14 block transfer configure regist"
|
|
hexmask.long.word 0x8 20.--31. 1. "BRNUM,Multi-block number"
|
|
bitfld.long 0x8 19. "DADDRUM,Multi-block destination address update mode" "0,1"
|
|
bitfld.long 0x8 18. "SADDRUM,Multi-block source address update mode" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "TBNUM,Transfer byte number in block"
|
|
line.long 0xC "CH14SADDR,Channel 14 source address regist"
|
|
hexmask.long 0xC 0.--31. 1. "SADDR,Source address"
|
|
line.long 0x10 "CH14DADDR,Channel 14 destination address regist"
|
|
hexmask.long 0x10 0.--31. 1. "DADDR,Destination address"
|
|
line.long 0x14 "CH14MBADDRU,Channel 14 multi-block address update regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "DADDRUV,Destination address update value"
|
|
hexmask.long.word 0x14 0.--15. 1. "SADDRUV,Source address update value"
|
|
line.long 0x18 "CH14LADDR,Channel 14 link address regist"
|
|
hexmask.long 0x18 0.--31. 1. "LADDR,Link address"
|
|
line.long 0x1C "CH14CTL1,Channel 14 control register"
|
|
bitfld.long 0x1C 17. "DBSEL,Destination bus select" "0,1"
|
|
bitfld.long 0x1C 16. "SBSEL,Source bus select" "0,1"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "TRIGSEL,Trigger select"
|
|
group.long 0x3F0++0x7
|
|
line.long 0x0 "CH14MADDR,Channel 14 mask address regist"
|
|
hexmask.long 0x0 0.--31. 1. "MADDR,Mask address"
|
|
line.long 0x4 "CH14MDATA,Channel 14 mask data regist"
|
|
hexmask.long 0x4 0.--31. 1. "MDATA,Mask data"
|
|
rgroup.long 0x400++0x3
|
|
line.long 0x0 "CH15STAT0,Channel 15 status register"
|
|
bitfld.long 0x0 16. "REQAF,Channel x request active flag" "0,1"
|
|
bitfld.long 0x0 4. "TCF,Channel x buffer transfer complete flag" "0,1"
|
|
bitfld.long 0x0 3. "BTCF,Channel x block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 2. "MBTCF,Channel x multi-block transfer complete flag" "0,1"
|
|
bitfld.long 0x0 1. "CHTCF,Channel x channel transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "ERR,Channel x transfer error flag" "0,1"
|
|
wgroup.long 0x404++0x3
|
|
line.long 0x0 "CH15STATC,Channel 15 status clear regist"
|
|
bitfld.long 0x0 4. "TCFC,Channel x buffer transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 3. "BTCFC,Channel x buffer block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 2. "MBTCFC,Channel x buffer multi-block transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 1. "CHTCFC,Channel x channel transfer complete flag clear" "0,1"
|
|
bitfld.long 0x0 0. "ERRC,Channel x transfer error flag clear" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "CH15STAT1,Channel 15 status register"
|
|
bitfld.long 0x0 11. "BZERR,Block size error flag" "0,1"
|
|
bitfld.long 0x0 10. "ASERR,Address and size error flag" "0,1"
|
|
bitfld.long 0x0 9. "MDTERR,Mask data error flag" "0,1"
|
|
bitfld.long 0x0 8. "LDTERR,Link data transfer error flag in the last transfer of the channel" "0,1"
|
|
bitfld.long 0x0 7. "TERRD,Transfer error direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ERRADDR,Transfer error address"
|
|
group.long 0x40C++0x1F
|
|
line.long 0x0 "CH15CTL0,Channel 15 control register"
|
|
bitfld.long 0x0 16. "SWREQ,Software request" "0,1"
|
|
bitfld.long 0x0 14. "WES,Word endianess swapping in double word" "0,1"
|
|
bitfld.long 0x0 13. "HWES,Half word endianess swapping in word" "0,1"
|
|
bitfld.long 0x0 12. "BES,Byte endianess swapping in half word" "0,1"
|
|
bitfld.long 0x0 8. "SMODEN,Secure mode enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "PRIO,Priority level" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TCIE,Buffer transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "BTCIE,Block transfer complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MBTCIE,Multi-block transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "CHTCIE,Channel transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "ERRIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
|
|
line.long 0x4 "CH15CFG,Channel 15 configure regist"
|
|
bitfld.long 0x4 31. "BWMOD,Bufferable write mode" "0,1"
|
|
bitfld.long 0x4 30. "SWREQMOD,Software request mode" "0,1"
|
|
bitfld.long 0x4 28.--29. "TRIGMOD,Trigger mode" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "PAMOD,Padding and alignement mode" "0,1,2,3"
|
|
bitfld.long 0x4 25. "PKEN,Pack enable" "0,1"
|
|
hexmask.long.byte 0x4 18.--24. 1. "BTLEN,Buffer transfer length"
|
|
bitfld.long 0x4 15.--17. "DBURST,Transfer burst type of destination" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "SBURST,Transfer burst type of source" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "DIOS,Offset size of destination increment" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "SIOS,Offset size of source increment" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "DWIDTH,Data size of destination" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "SWIDTH,Data size of source" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "DIMOD,Destination increment mode" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SIMOD,Source increment mode" "0,1,2,3"
|
|
line.long 0x8 "CH15BTCFG,Channel 15 block transfer configure regist"
|
|
hexmask.long.word 0x8 20.--31. 1. "BRNUM,Multi-block number"
|
|
bitfld.long 0x8 19. "DADDRUM,Multi-block destination address update mode" "0,1"
|
|
bitfld.long 0x8 18. "SADDRUM,Multi-block source address update mode" "0,1"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. "TBNUM,Transfer byte number in block"
|
|
line.long 0xC "CH15SADDR,Channel 15 source address regist"
|
|
hexmask.long 0xC 0.--31. 1. "SADDR,Source address"
|
|
line.long 0x10 "CH15DADDR,Channel 15 destination address regist"
|
|
hexmask.long 0x10 0.--31. 1. "DADDR,Destination address"
|
|
line.long 0x14 "CH15MBADDRU,Channel 15 multi-block address update regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "DADDRUV,Destination address update value"
|
|
hexmask.long.word 0x14 0.--15. 1. "SADDRUV,Source address update value"
|
|
line.long 0x18 "CH15LADDR,Channel 15 link address regist"
|
|
hexmask.long 0x18 0.--31. 1. "LADDR,Link address"
|
|
line.long 0x1C "CH15CTL1,Channel 15 control register"
|
|
bitfld.long 0x1C 17. "DBSEL,Destination bus select" "0,1"
|
|
bitfld.long 0x1C 16. "SBSEL,Source bus select" "0,1"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "TRIGSEL,Trigger select"
|
|
group.long 0x430++0x7
|
|
line.long 0x0 "CH15MADDR,Channel 15 mask address regist"
|
|
hexmask.long 0x0 0.--31. 1. "MADDR,Mask address"
|
|
line.long 0x4 "CH15MDATA,Channel 15 mask data regist"
|
|
hexmask.long 0x4 0.--31. 1. "MDATA,Mask data"
|
|
tree.end
|
|
tree "NVIC (Nested Vectored Interrupt)"
|
|
base ad:0xE000E100
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ISER0,Interrupt Set-Enable Register"
|
|
hexmask.long 0x0 0.--31. 1. "SETENA,SETENA"
|
|
line.long 0x4 "ISER1,Interrupt Set-Enable Register"
|
|
hexmask.long 0x4 0.--31. 1. "SETENA,SETENA"
|
|
line.long 0x8 "ISER2,Interrupt Set-Enable Register"
|
|
hexmask.long 0x8 0.--31. 1. "SETENA,SETENA"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "ICER0,Interrupt Clear-Enable"
|
|
hexmask.long 0x0 0.--31. 1. "CLRENA,CLRENA"
|
|
line.long 0x4 "ICER1,Interrupt Clear-Enable"
|
|
hexmask.long 0x4 0.--31. 1. "CLRENA,CLRENA"
|
|
line.long 0x8 "ICER2,Interrupt Clear-Enable"
|
|
hexmask.long 0x8 0.--31. 1. "CLRENA,CLRENA"
|
|
group.long 0x100++0xB
|
|
line.long 0x0 "ISPR0,Interrupt Set-Pending Register"
|
|
hexmask.long 0x0 0.--31. 1. "SETPEND,SETPEND"
|
|
line.long 0x4 "ISPR1,Interrupt Set-Pending Register"
|
|
hexmask.long 0x4 0.--31. 1. "SETPEND,SETPEND"
|
|
line.long 0x8 "ISPR2,Interrupt Set-Pending Register"
|
|
hexmask.long 0x8 0.--31. 1. "SETPEND,SETPEND"
|
|
group.long 0x180++0xB
|
|
line.long 0x0 "ICPR0,Interrupt Clear-Pending"
|
|
hexmask.long 0x0 0.--31. 1. "CLRPEND,CLRPEND"
|
|
line.long 0x4 "ICPR1,Interrupt Clear-Pending"
|
|
hexmask.long 0x4 0.--31. 1. "CLRPEND,CLRPEND"
|
|
line.long 0x8 "ICPR2,Interrupt Clear-Pending"
|
|
hexmask.long 0x8 0.--31. 1. "CLRPEND,CLRPEND"
|
|
rgroup.long 0x200++0xB
|
|
line.long 0x0 "IABR0,Interrupt Active Bit Register"
|
|
hexmask.long 0x0 0.--31. 1. "ACTIVE,ACTIVE"
|
|
line.long 0x4 "IABR1,Interrupt Active Bit Register"
|
|
hexmask.long 0x4 0.--31. 1. "ACTIVE,ACTIVE"
|
|
line.long 0x8 "IABR2,Interrupt Active Bit Register"
|
|
hexmask.long 0x8 0.--31. 1. "ACTIVE,ACTIVE"
|
|
group.long 0x300++0x9B
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x0 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x4 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x4 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x8 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x8 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0xC 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0xC 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0xC 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x14 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x14 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x14 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x18 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x18 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x18 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x1C 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x20 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x20 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x20 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x24 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x24 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x24 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x28 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x28 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x28 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x2C 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x2C 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x30 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x30 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x30 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x34 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x34 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x34 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x38 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x38 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x38 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x3C 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x3C 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x40 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x40 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x40 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x44 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x44 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x44 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x48 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x48 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x48 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x4C 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x4C 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x4C 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x50 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x50 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x50 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x54 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x54 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x54 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x58 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x58 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x58 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x5C 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x5C 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x5C 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x60 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x60 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x60 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x64 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x64 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x64 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x68 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x68 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x68 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x6C 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x6C 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x6C 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x70 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x70 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x70 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x74 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x74 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x74 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x78 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x78 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x78 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x7C 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x7C 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x7C 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x80 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x80 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x80 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x84 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x84 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x84 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x88 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x88 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x88 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x8C 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x8C 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x8C 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x90 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x90 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x90 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x94 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x94 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x94 0.--7. 1. "IPR_N0,IPR_N0"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x98 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x98 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x98 0.--7. 1. "IPR_N0,IPR_N0"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "ISER3,Interrupt Set-Enable Register"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "ICER3,Interrupt Clear-Enable"
|
|
group.long 0x10C++0x3
|
|
line.long 0x0 "ISPR3,Interrupt Set-Pending Register"
|
|
group.long 0x1C0++0x3
|
|
line.long 0x0 "ICPR3,Interrupt Clear-Pending"
|
|
group.long 0x20C++0x3
|
|
line.long 0x0 "IABR3,Interrupt Active Bit Register"
|
|
tree.end
|
|
tree "OSPI (Octal-SPI Interface)"
|
|
base ad:0x0
|
|
tree "OSPI0"
|
|
base ad:0x52005000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 28.--29. "FMOD,Functional mode" "0,1,2,3"
|
|
bitfld.long 0x0 23. "SPMOD,Status polling match mode" "0,1"
|
|
bitfld.long 0x0 22. "SPS,Status polling mode stop" "0,1"
|
|
bitfld.long 0x0 19. "SMIE,Status match interrupt enable" "0,1"
|
|
bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 16. "TERRIE,Transfer error interrupt enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "FTL,FIFO threshold level"
|
|
bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x0 0. "OSPIEN,Enable OSPI" "0,1"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "DCFG0,Device configuration register 0"
|
|
bitfld.long 0x0 24.--26. "DTYSEL,Select device type" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 16.--20. 1. "MESZ,Memory size"
|
|
hexmask.long.byte 0x0 8.--13. 1. "CSHC,Chip select high cycle"
|
|
line.long 0x4 "DFCG1,Device configuration register 1"
|
|
bitfld.long 0x4 16.--18. "WPSZ,Wrap size" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PSC,This field defines the scaler factor for generating SCK based on the kernel clock (value+1)"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "STAT,Status register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "FL,FIFO level"
|
|
bitfld.long 0x0 5. "BUSY,Busy" "0,1"
|
|
bitfld.long 0x0 3. "SM,Status match flag" "0,1"
|
|
bitfld.long 0x0 2. "FT,FIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 1. "TC,Transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "TERR,Transfer error flag" "0,1"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "STATC,Status clear register"
|
|
bitfld.long 0x0 3. "SMC,Clear status match flag" "0,1"
|
|
bitfld.long 0x0 1. "TCC,Clear transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "TERRC,Clear transfer error flag" "0,1"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "DTLEN,Data length register"
|
|
hexmask.long 0x0 0.--31. 1. "DTLEN,Data length"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "ADDR,Address register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "DATA,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "STATMK,Status mask register"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,Status mask"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "STATMATCH,Status match register"
|
|
hexmask.long 0x0 0.--31. 1. "MATCH,Status match"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "INTERVAL,Interval register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INTERVAL,Interval cycle"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "TCFG,Transfer configuration register"
|
|
bitfld.long 0x0 27. "DADTR,Data double transfer rate" "0,1"
|
|
bitfld.long 0x0 24.--26. "DATAMOD,Data mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20.--21. "ALTESZ,Alternate bytes size" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0,1"
|
|
bitfld.long 0x0 16.--18. "ALTEMOD,Alternate bytes mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--13. "ADDRSZ,Address size" "0,1,2,3"
|
|
bitfld.long 0x0 11. "ADDRDTR,Address double transfer rate" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "ADDRMOD,Address mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--5. "INSSZ,Instruction size" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "IMOD,Instruction mode" "0,1,2,3,4,5,6,7"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "TIMCFG,Timing configuration register"
|
|
bitfld.long 0x0 30. "SSAMPLE,Sample shift" "0,1"
|
|
bitfld.long 0x0 27. "DEHQC,Delay hold 1/4 cycle" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DUMYC,Number of dummy cycles"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "INS,Instruction register"
|
|
hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "ALTE,Alternate bytes register"
|
|
hexmask.long 0x0 0.--31. 1. "ALTE,Alternate bytes"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "WPTCFG,Wrap transfer configuration register"
|
|
bitfld.long 0x0 27. "DADTR,Data double transfer rate" "0,1"
|
|
bitfld.long 0x0 24.--26. "DATAMOD,Data mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20.--21. "ALTESZ,Alternate bytes size" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0,1"
|
|
bitfld.long 0x0 16.--18. "ALTEMOD,Alternate bytes mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--13. "ADDRSZ,Address size" "0,1,2,3"
|
|
bitfld.long 0x0 11. "ADDRDTR,Address double transfer rate" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "ADDRMOD,Address mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--5. "INSSZ,Instruction size" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "IMOD,Instruction mode" "0,1,2,3,4,5,6,7"
|
|
group.long 0x148++0x3
|
|
line.long 0x0 "WPTIMCFG,Wrap timing configuration register"
|
|
bitfld.long 0x0 30. "SSAMPLE,shift sample" "0,1"
|
|
bitfld.long 0x0 28. "DEHQC,Delay hold 1/4 cycle" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DUMYC,Number of dummy cycles"
|
|
group.long 0x150++0x3
|
|
line.long 0x0 "WPINS,Wrap instruction register"
|
|
hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "WPALTE,Wrap alternate byte register"
|
|
hexmask.long 0x0 0.--31. 1. "ALTE,Alternate bytes"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "WTCFG,Write transfer configuration register"
|
|
bitfld.long 0x0 27. "DADTR,Data double transfer rate" "0,1"
|
|
bitfld.long 0x0 24.--26. "DATAMOD,data mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20.--21. "ALTESZ,Alternate bytes size" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0,1"
|
|
bitfld.long 0x0 16.--18. "ALTEMOD,Alternate bytes mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--13. "ADDRSZ,Address size" "0,1,2,3"
|
|
bitfld.long 0x0 11. "ADDRDTR,Alternate bytes double transfer rate" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "ADDRMOD,address mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--5. "INSSZ,Instruction size" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "IMOD,Instruction mode" "0,1,2,3,4,5,6,7"
|
|
group.long 0x188++0x3
|
|
line.long 0x0 "WTIMCFG,Write timing configuration register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DUMYC,Number of dummy cycles"
|
|
group.long 0x190++0x3
|
|
line.long 0x0 "WINS,Write instruction register"
|
|
hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x0 "WALTE,Write alternate byte register"
|
|
hexmask.long 0x0 0.--31. 1. "ALTE,Alternate bytes"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "HBLCFG,HyperBus lantency configuration register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RWRTIM,Read write recovery time"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ACCTM,Access time"
|
|
bitfld.long 0x0 1. "WZLAT,Write zero latency" "0,1"
|
|
bitfld.long 0x0 0. "LMOD,Latency mode" "0,1"
|
|
tree.end
|
|
tree "OSPI1"
|
|
base ad:0x5200A000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 28.--29. "FMOD,Functional mode" "0,1,2,3"
|
|
bitfld.long 0x0 23. "SPMOD,Status polling match mode" "0,1"
|
|
bitfld.long 0x0 22. "SPS,Status polling mode stop" "0,1"
|
|
bitfld.long 0x0 19. "SMIE,Status match interrupt enable" "0,1"
|
|
bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 16. "TERRIE,Transfer error interrupt enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "FTL,FIFO threshold level"
|
|
bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x0 0. "OSPIEN,Enable OSPI" "0,1"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "DCFG0,Device configuration register 0"
|
|
bitfld.long 0x0 24.--26. "DTYSEL,Select device type" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 16.--20. 1. "MESZ,Memory size"
|
|
hexmask.long.byte 0x0 8.--13. 1. "CSHC,Chip select high cycle"
|
|
line.long 0x4 "DFCG1,Device configuration register 1"
|
|
bitfld.long 0x4 16.--18. "WPSZ,Wrap size" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PSC,This field defines the scaler factor for generating SCK based on the kernel clock (value+1)"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "STAT,Status register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "FL,FIFO level"
|
|
bitfld.long 0x0 5. "BUSY,Busy" "0,1"
|
|
bitfld.long 0x0 3. "SM,Status match flag" "0,1"
|
|
bitfld.long 0x0 2. "FT,FIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 1. "TC,Transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "TERR,Transfer error flag" "0,1"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "STATC,Status clear register"
|
|
bitfld.long 0x0 3. "SMC,Clear status match flag" "0,1"
|
|
bitfld.long 0x0 1. "TCC,Clear transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "TERRC,Clear transfer error flag" "0,1"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "DTLEN,Data length register"
|
|
hexmask.long 0x0 0.--31. 1. "DTLEN,Data length"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "ADDR,Address register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "DATA,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "STATMK,Status mask register"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,Status mask"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "STATMATCH,Status match register"
|
|
hexmask.long 0x0 0.--31. 1. "MATCH,Status match"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "INTERVAL,Interval register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INTERVAL,Interval cycle"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "TCFG,Transfer configuration register"
|
|
bitfld.long 0x0 27. "DADTR,Data double transfer rate" "0,1"
|
|
bitfld.long 0x0 24.--26. "DATAMOD,Data mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20.--21. "ALTESZ,Alternate bytes size" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0,1"
|
|
bitfld.long 0x0 16.--18. "ALTEMOD,Alternate bytes mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--13. "ADDRSZ,Address size" "0,1,2,3"
|
|
bitfld.long 0x0 11. "ADDRDTR,Address double transfer rate" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "ADDRMOD,Address mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--5. "INSSZ,Instruction size" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "IMOD,Instruction mode" "0,1,2,3,4,5,6,7"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "TIMCFG,Timing configuration register"
|
|
bitfld.long 0x0 30. "SSAMPLE,Sample shift" "0,1"
|
|
bitfld.long 0x0 27. "DEHQC,Delay hold 1/4 cycle" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DUMYC,Number of dummy cycles"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "INS,Instruction register"
|
|
hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "ALTE,Alternate bytes register"
|
|
hexmask.long 0x0 0.--31. 1. "ALTE,Alternate bytes"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "WPTCFG,Wrap transfer configuration register"
|
|
bitfld.long 0x0 27. "DADTR,Data double transfer rate" "0,1"
|
|
bitfld.long 0x0 24.--26. "DATAMOD,Data mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20.--21. "ALTESZ,Alternate bytes size" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0,1"
|
|
bitfld.long 0x0 16.--18. "ALTEMOD,Alternate bytes mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--13. "ADDRSZ,Address size" "0,1,2,3"
|
|
bitfld.long 0x0 11. "ADDRDTR,Address double transfer rate" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "ADDRMOD,Address mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--5. "INSSZ,Instruction size" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "IMOD,Instruction mode" "0,1,2,3,4,5,6,7"
|
|
group.long 0x148++0x3
|
|
line.long 0x0 "WPTIMCFG,Wrap timing configuration register"
|
|
bitfld.long 0x0 30. "SSAMPLE,shift sample" "0,1"
|
|
bitfld.long 0x0 28. "DEHQC,Delay hold 1/4 cycle" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DUMYC,Number of dummy cycles"
|
|
group.long 0x150++0x3
|
|
line.long 0x0 "WPINS,Wrap instruction register"
|
|
hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "WPALTE,Wrap alternate byte register"
|
|
hexmask.long 0x0 0.--31. 1. "ALTE,Alternate bytes"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "WTCFG,Write transfer configuration register"
|
|
bitfld.long 0x0 27. "DADTR,Data double transfer rate" "0,1"
|
|
bitfld.long 0x0 24.--26. "DATAMOD,data mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20.--21. "ALTESZ,Alternate bytes size" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0,1"
|
|
bitfld.long 0x0 16.--18. "ALTEMOD,Alternate bytes mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--13. "ADDRSZ,Address size" "0,1,2,3"
|
|
bitfld.long 0x0 11. "ADDRDTR,Alternate bytes double transfer rate" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "ADDRMOD,address mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--5. "INSSZ,Instruction size" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "IMOD,Instruction mode" "0,1,2,3,4,5,6,7"
|
|
group.long 0x188++0x3
|
|
line.long 0x0 "WTIMCFG,Write timing configuration register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DUMYC,Number of dummy cycles"
|
|
group.long 0x190++0x3
|
|
line.long 0x0 "WINS,Write instruction register"
|
|
hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x0 "WALTE,Write alternate byte register"
|
|
hexmask.long 0x0 0.--31. 1. "ALTE,Alternate bytes"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "HBLCFG,HyperBus lantency configuration register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RWRTIM,Read write recovery time"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ACCTM,Access time"
|
|
bitfld.long 0x0 1. "WZLAT,Write zero latency" "0,1"
|
|
bitfld.long 0x0 0. "LMOD,Latency mode" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "OSPIM (OSPI I/O Manager)"
|
|
base ad:0x5200B400
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,2Control register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ACKTM,REQ to ACK time"
|
|
bitfld.long 0x0 0. "MULEN,Multiplexed mode enable" "0,1"
|
|
endif
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "PCFG0,Port configuration regist 0"
|
|
bitfld.long 0x0 25.--26. "SRCPHIO,Source selection for IO[7:4] of port x" "0,1,2,3"
|
|
bitfld.long 0x0 24. "POHEN,Enable for IO[7:4] of port x" "0,1"
|
|
bitfld.long 0x0 17.--18. "SRCPLIO,Source selection for IO[3:0] of port x" "0,1,2,3"
|
|
bitfld.long 0x0 16. "POLEN,Enable for IO[3:0] of port x" "0,1"
|
|
bitfld.long 0x0 9. "SRCPCS,Source selection for CSN of port x" "0,1"
|
|
bitfld.long 0x0 8. "NCSEN,Enable for CSN of port x" "0,1"
|
|
bitfld.long 0x0 1. "SRCPCK,Source selection for SCK of port x" "0,1"
|
|
bitfld.long 0x0 0. "SCKEN,Enable for SCK of port x" "0,1"
|
|
line.long 0x4 "PCFG1,Port configuration regist 1"
|
|
bitfld.long 0x4 25.--26. "SRCPHIO,Source selection for IO[7:4] of port x" "0,1,2,3"
|
|
bitfld.long 0x4 24. "POHEN,Enable for IO[7:4] of port x" "0,1"
|
|
bitfld.long 0x4 17.--18. "SRCPLIO,Source selection for IO[3:0] of port x" "0,1,2,3"
|
|
bitfld.long 0x4 16. "POLEN,Enable for IO[3:0] of port x" "0,1"
|
|
bitfld.long 0x4 9. "SRCPCS,Source selection for CSN of port x" "0,1"
|
|
bitfld.long 0x4 8. "NCSEN,Enable for CSN of port x" "0,1"
|
|
bitfld.long 0x4 1. "SRCPCK,Source selection for SCK of port x" "0,1"
|
|
bitfld.long 0x4 0. "SCKEN,Enable for SCK of port x" "0,1"
|
|
tree.end
|
|
tree "PMU (Power Management Unit)"
|
|
base ad:0x58005800
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 19. "VOVDEN,Peripheral voltage on V0.9V detector enable bit" "0,1"
|
|
bitfld.long 0x0 17.--18. "VAVDVC,VDDA analog voltage detector voltage level configure bits" "0,1,2,3"
|
|
bitfld.long 0x0 16. "VAVDEN,VDDA analog voltage detector voltage enable bit" "0,1"
|
|
bitfld.long 0x0 14.--15. "SLDOVS,Deep-sleep mode voltage scaling selection" "0,1,2,3"
|
|
bitfld.long 0x0 8. "BKPWEN,Backup domain write enable bit" "0,1"
|
|
bitfld.long 0x0 5.--7. "LVDT,Low voltage detector threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4. "LVDEN,Low voltage detector enable bit" "0,1"
|
|
bitfld.long 0x0 3. "STBRST,Standby flag reset bit" "0,1"
|
|
bitfld.long 0x0 2. "WURST,Wakeup flag reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STBMOD,Standby Mode" "0,1"
|
|
line.long 0x4 "CS,Control and status register"
|
|
rbitfld.long 0x4 20. "VOVDF,Peripheral voltage on V0.9V detector flag bit" "0,1"
|
|
rbitfld.long 0x4 16. "VAVDF,VDDA analog voltage detector voltage output on VDDA flag bit" "0,1"
|
|
bitfld.long 0x4 13. "WUPEN5,WKUP Pin5 (PC1) enable" "0,1"
|
|
bitfld.long 0x4 11. "WUPEN3,WKUP pin3 (PC13) enable" "0,1"
|
|
bitfld.long 0x4 9. "WUPEN1,WKUP pin1 (PA2) enable" "0,1"
|
|
bitfld.long 0x4 8. "WUPEN0,WKUP pin0 (PA0) enable" "0,1"
|
|
rbitfld.long 0x4 2. "LVDF,Low voltage detector status flag" "0,1"
|
|
rbitfld.long 0x4 1. "STBF,Standby flag" "0,1"
|
|
rbitfld.long 0x4 0. "WUF,Wakeup Flag" "0,1"
|
|
line.long 0x8 "CTL1,Control register 1"
|
|
rbitfld.long 0x8 23. "TEMPHF,Temperature level monitoring versus high threshold" "0,1"
|
|
rbitfld.long 0x8 22. "TEMPLF,Temperature level monitoring versus low threshold" "0,1"
|
|
rbitfld.long 0x8 21. "VBATHF,VBAT level monitoring versus high threshold" "0,1"
|
|
rbitfld.long 0x8 20. "VBATLF,VBAT level monitoring versus low threshold" "0,1"
|
|
rbitfld.long 0x8 16. "BKPVSRF,Backup voltage stabilizer ready flag" "0,1"
|
|
bitfld.long 0x8 4. "VBTMEN,VBAT and temperature monitoring enable." "0,1"
|
|
bitfld.long 0x8 0. "BKPVSEN,Backup voltage stabilizer enable" "0,1"
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "CTL2,Control register 2"
|
|
rbitfld.long 0x0 26. "USB33RF,USB supply ready flag bit" "0,1"
|
|
bitfld.long 0x0 25. "USBSEN,USB voltage stabilizer enable." "0,1"
|
|
bitfld.long 0x0 24. "VUSB33DEN,VDD33USB voltage level detector enable bit" "0,1"
|
|
rbitfld.long 0x0 16. "DVSRF,Step-down voltage stabilizer ready flag bit" "0,1"
|
|
bitfld.long 0x0 9. "VCEN,VBAT battery charging enable" "0,1"
|
|
bitfld.long 0x0 8. "VCRSEL,VBAT battery charging resistor selection" "0,1"
|
|
bitfld.long 0x0 4.--5. "DVSVC,Step-down voltage stabilizer output voltage level configure bits" "0,1,2,3"
|
|
bitfld.long 0x0 3. "DVSCFG,Step-down voltage stabilizer forced on and in High Power MR mode." "0,1"
|
|
bitfld.long 0x0 2. "DVSEN,Step-down voltage stabilizer enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LDOEN,Low drop-out voltage stabilizer enable bit" "0,1"
|
|
bitfld.long 0x0 0. "BYPASS,Power management unit bypass control bit" "0,1"
|
|
line.long 0x4 "CTL3,Control register 3"
|
|
rbitfld.long 0x4 16. "VOVRF,V0.9V voltage ready bit" "0,1"
|
|
bitfld.long 0x4 12.--14. "LDOVS,LDO output voltage select" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "PAR,Parameter register"
|
|
hexmask.long.byte 0x8 16.--20. 1. "TSW_IRCCNT,When enter Deep-sleep switch to LPIRC4M / IRC64M (confirmed by DSPWUSSEL) clock. Wait the LPIRC4M / IRC64M (confirmed by DSPWUSSEL) counter and then set Deep-sleep mode. The default is 10 clocks."
|
|
hexmask.long.word 0x8 0.--11. 1. "PMU_CNT,Exit Deep-sleep mode wait time count configure bits"
|
|
tree.end
|
|
tree "RAMECCMU (RAM ECC Monitor Unit)"
|
|
base ad:0x0
|
|
tree "RAMECCMU0"
|
|
base ad:0x52009000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "INT,RAMECCMU global interruput register"
|
|
bitfld.long 0x0 3. "GEDERRBWIE,Global ECC double error on byte write interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "GEDERRIE,Global ECC double error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "GESERRIE,Global ECC single error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "GEIE,Global ECC interrupt enable" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "M0CTL,monitor 0 control register"
|
|
bitfld.long 0x0 5. "ECCERRLATEN,ECC error latching enable" "0,1"
|
|
bitfld.long 0x0 4. "ECCDERRBWIE,ECC double error on byte write interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ECCDERRIE,ECC double error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "ECCSERRIE,ECC single error interrupt enable" "0,1"
|
|
line.long 0x4 "M0STAT,monitor 0 status register"
|
|
bitfld.long 0x4 2. "ECCDERRBWDF,ECC double error on byte write detected flag" "0,1"
|
|
bitfld.long 0x4 1. "ECCDERRDF,ECC double error detected flag" "0,1"
|
|
bitfld.long 0x4 0. "ECCSERRDCF,ECC single error detected and corrected flag" "0,1"
|
|
rgroup.long 0x28++0xF
|
|
line.long 0x0 "M0FADDR,monitor 0 failing address register"
|
|
hexmask.long 0x0 0.--31. 1. "ECCFADDR,ECC error failing address"
|
|
line.long 0x4 "M0FDL,monitor 0 failing data low register"
|
|
hexmask.long 0x4 0.--31. 1. "ECCFDL,ECC failing data low bits"
|
|
line.long 0x8 "M0FDH,monitor 0 failing data high register"
|
|
hexmask.long 0x8 0.--31. 1. "ECCFDH,ECC failing data high bitss"
|
|
line.long 0xC "M0FECODE,monitor 0 failing ECC error code register"
|
|
hexmask.long 0xC 0.--31. 1. "ECCFECODE,ECC failing error code"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "M1CTL,monitor 1 control register"
|
|
bitfld.long 0x0 5. "ECCERRLATEN,ECC error latching enable" "0,1"
|
|
bitfld.long 0x0 4. "ECCDERRBWIE,ECC double error on byte write interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ECCDERRIE,ECC double error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "ECCSERRIE,ECC single error interrupt enable" "0,1"
|
|
line.long 0x4 "M1STAT,monitor 1 status register"
|
|
bitfld.long 0x4 2. "ECCDERRBWDF,ECC double error on byte write detected flag" "0,1"
|
|
bitfld.long 0x4 1. "ECCDERRDF,ECC double error detected flag" "0,1"
|
|
bitfld.long 0x4 0. "ECCSERRDCF,ECC single error detected and corrected flag" "0,1"
|
|
rgroup.long 0x48++0xF
|
|
line.long 0x0 "M1FADDR,monitor 1 failing address register"
|
|
hexmask.long 0x0 0.--31. 1. "ECCFADDR,ECC error failing address"
|
|
line.long 0x4 "M1FDL,monitor 1 failing data low register"
|
|
hexmask.long 0x4 0.--31. 1. "ECCFDL,ECC failing data low bits"
|
|
line.long 0x8 "M1FDH,monitor 0 failing data high register"
|
|
hexmask.long 0x8 0.--31. 1. "ECCFDH,ECC failing data high bitss"
|
|
line.long 0xC "M1FECODE,monitor 1 failing ECC error code register"
|
|
hexmask.long 0xC 0.--31. 1. "ECCFECODE,ECC failing error code"
|
|
group.long 0x60++0x7
|
|
line.long 0x0 "M2CTL,monitor 0 control register"
|
|
bitfld.long 0x0 5. "ECCERRLATEN,ECC error latching enable" "0,1"
|
|
bitfld.long 0x0 4. "ECCDERRBWIE,ECC double error on byte write interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ECCDERRIE,ECC double error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "ECCSERRIE,ECC single error interrupt enable" "0,1"
|
|
line.long 0x4 "M2STAT,monitor 0 status register"
|
|
bitfld.long 0x4 2. "ECCDERRBWDF,ECC double error on byte write detected flag" "0,1"
|
|
bitfld.long 0x4 1. "ECCDERRDF,ECC double error detected flag" "0,1"
|
|
bitfld.long 0x4 0. "ECCSERRDCF,ECC single error detected and corrected flag" "0,1"
|
|
rgroup.long 0x68++0xF
|
|
line.long 0x0 "M2FADDR,monitor 0 failing address register"
|
|
hexmask.long 0x0 0.--31. 1. "ECCFADDR,ECC error failing address"
|
|
line.long 0x4 "M2FDL,monitor 0 failing data low register"
|
|
hexmask.long 0x4 0.--31. 1. "ECCFDL,ECC failing data low bits"
|
|
line.long 0x8 "M2FDH,monitor 0 failing data high register"
|
|
hexmask.long 0x8 0.--31. 1. "ECCFDH,ECC failing data high bitss"
|
|
line.long 0xC "M2FECODE,monitor 0 failing ECC error code register"
|
|
hexmask.long 0xC 0.--31. 1. "ECCFECODE,ECC failing error code"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "M3CTL,monitor 0 control register"
|
|
bitfld.long 0x0 5. "ECCERRLATEN,ECC error latching enable" "0,1"
|
|
bitfld.long 0x0 4. "ECCDERRBWIE,ECC double error on byte write interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ECCDERRIE,ECC double error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "ECCSERRIE,ECC single error interrupt enable" "0,1"
|
|
line.long 0x4 "M3STAT,monitor 0 status register"
|
|
bitfld.long 0x4 2. "ECCDERRBWDF,ECC double error on byte write detected flag" "0,1"
|
|
bitfld.long 0x4 1. "ECCDERRDF,ECC double error detected flag" "0,1"
|
|
bitfld.long 0x4 0. "ECCSERRDCF,ECC single error detected and corrected flag" "0,1"
|
|
rgroup.long 0x88++0xF
|
|
line.long 0x0 "M3FADDR,monitor 0 failing address register"
|
|
hexmask.long 0x0 0.--31. 1. "ECCFADDR,ECC error failing address"
|
|
line.long 0x4 "M3FDL,monitor 0 failing data low register"
|
|
hexmask.long 0x4 0.--31. 1. "ECCFDL,ECC failing data low bits"
|
|
line.long 0x8 "M3FDH,monitor 0 failing data high register"
|
|
hexmask.long 0x8 0.--31. 1. "ECCFDH,ECC failing data high bitss"
|
|
line.long 0xC "M3FECODE,monitor 0 failing ECC error code register"
|
|
hexmask.long 0xC 0.--31. 1. "ECCFECODE,ECC failing error code"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "M4CTL,monitor 0 control register"
|
|
bitfld.long 0x0 5. "ECCERRLATEN,ECC error latching enable" "0,1"
|
|
bitfld.long 0x0 4. "ECCDERRBWIE,ECC double error on byte write interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ECCDERRIE,ECC double error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "ECCSERRIE,ECC single error interrupt enable" "0,1"
|
|
line.long 0x4 "M4STAT,monitor 0 status register"
|
|
bitfld.long 0x4 2. "ECCDERRBWDF,ECC double error on byte write detected flag" "0,1"
|
|
bitfld.long 0x4 1. "ECCDERRDF,ECC double error detected flag" "0,1"
|
|
bitfld.long 0x4 0. "ECCSERRDCF,ECC single error detected and corrected flag" "0,1"
|
|
rgroup.long 0xA8++0xF
|
|
line.long 0x0 "M4FADDR,monitor 0 failing address register"
|
|
hexmask.long 0x0 0.--31. 1. "ECCFADDR,ECC error failing address"
|
|
line.long 0x4 "M4FDL,monitor 0 failing data low register"
|
|
hexmask.long 0x4 0.--31. 1. "ECCFDL,ECC failing data low bits"
|
|
line.long 0x8 "M4FDH,monitor 0 failing data high register"
|
|
hexmask.long 0x8 0.--31. 1. "ECCFDH,ECC failing data high bitss"
|
|
line.long 0xC "M4FECODE,monitor 0 failing ECC error code register"
|
|
hexmask.long 0xC 0.--31. 1. "ECCFECODE,ECC failing error code"
|
|
tree.end
|
|
tree "RAMECCMU1"
|
|
base ad:0x48023000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "INT,RAMECCMU global interruput register"
|
|
bitfld.long 0x0 3. "GEDERRBWIE,Global ECC double error on byte write interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "GEDERRIE,Global ECC double error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "GESERRIE,Global ECC single error interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "GEIE,Global ECC interrupt enable" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "M0CTL,monitor 0 control register"
|
|
bitfld.long 0x0 5. "ECCERRLATEN,ECC error latching enable" "0,1"
|
|
bitfld.long 0x0 4. "ECCDERRBWIE,ECC double error on byte write interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ECCDERRIE,ECC double error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "ECCSERRIE,ECC single error interrupt enable" "0,1"
|
|
line.long 0x4 "M0STAT,monitor 0 status register"
|
|
bitfld.long 0x4 2. "ECCDERRBWDF,ECC double error on byte write detected flag" "0,1"
|
|
bitfld.long 0x4 1. "ECCDERRDF,ECC double error detected flag" "0,1"
|
|
bitfld.long 0x4 0. "ECCSERRDCF,ECC single error detected and corrected flag" "0,1"
|
|
rgroup.long 0x28++0xF
|
|
line.long 0x0 "M0FADDR,monitor 0 failing address register"
|
|
hexmask.long 0x0 0.--31. 1. "ECCFADDR,ECC error failing address"
|
|
line.long 0x4 "M0FDL,monitor 0 failing data low register"
|
|
hexmask.long 0x4 0.--31. 1. "ECCFDL,ECC failing data low bits"
|
|
line.long 0x8 "M0FDH,monitor 0 failing data high register"
|
|
hexmask.long 0x8 0.--31. 1. "ECCFDH,ECC failing data high bitss"
|
|
line.long 0xC "M0FECODE,monitor 0 failing ECC error code register"
|
|
hexmask.long 0xC 0.--31. 1. "ECCFECODE,ECC failing error code"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "M1CTL,monitor 1 control register"
|
|
bitfld.long 0x0 5. "ECCERRLATEN,ECC error latching enable" "0,1"
|
|
bitfld.long 0x0 4. "ECCDERRBWIE,ECC double error on byte write interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ECCDERRIE,ECC double error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "ECCSERRIE,ECC single error interrupt enable" "0,1"
|
|
line.long 0x4 "M1STAT,monitor 1 status register"
|
|
bitfld.long 0x4 2. "ECCDERRBWDF,ECC double error on byte write detected flag" "0,1"
|
|
bitfld.long 0x4 1. "ECCDERRDF,ECC double error detected flag" "0,1"
|
|
bitfld.long 0x4 0. "ECCSERRDCF,ECC single error detected and corrected flag" "0,1"
|
|
rgroup.long 0x48++0xF
|
|
line.long 0x0 "M1FADDR,monitor 1 failing address register"
|
|
hexmask.long 0x0 0.--31. 1. "ECCFADDR,ECC error failing address"
|
|
line.long 0x4 "M1FDL,monitor 1 failing data low register"
|
|
hexmask.long 0x4 0.--31. 1. "ECCFDL,ECC failing data low bits"
|
|
line.long 0x8 "M1FDH,monitor 0 failing data high register"
|
|
hexmask.long 0x8 0.--31. 1. "ECCFDH,ECC failing data high bitss"
|
|
line.long 0xC "M1FECODE,monitor 1 failing ECC error code register"
|
|
hexmask.long 0xC 0.--31. 1. "ECCFECODE,ECC failing error code"
|
|
group.long 0x60++0x7
|
|
line.long 0x0 "M2CTL,monitor 0 control register"
|
|
bitfld.long 0x0 5. "ECCERRLATEN,ECC error latching enable" "0,1"
|
|
bitfld.long 0x0 4. "ECCDERRBWIE,ECC double error on byte write interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ECCDERRIE,ECC double error interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "ECCSERRIE,ECC single error interrupt enable" "0,1"
|
|
line.long 0x4 "M2STAT,monitor 0 status register"
|
|
bitfld.long 0x4 2. "ECCDERRBWDF,ECC double error on byte write detected flag" "0,1"
|
|
bitfld.long 0x4 1. "ECCDERRDF,ECC double error detected flag" "0,1"
|
|
bitfld.long 0x4 0. "ECCSERRDCF,ECC single error detected and corrected flag" "0,1"
|
|
rgroup.long 0x68++0xF
|
|
line.long 0x0 "M2FADDR,monitor 0 failing address register"
|
|
hexmask.long 0x0 0.--31. 1. "ECCFADDR,ECC error failing address"
|
|
line.long 0x4 "M2FDL,monitor 0 failing data low register"
|
|
hexmask.long 0x4 0.--31. 1. "ECCFDL,ECC failing data low bits"
|
|
line.long 0x8 "M2FDH,monitor 0 failing data high register"
|
|
hexmask.long 0x8 0.--31. 1. "ECCFDH,ECC failing data high bitss"
|
|
line.long 0xC "M2FECODE,monitor 0 failing ECC error code register"
|
|
hexmask.long 0xC 0.--31. 1. "ECCFECODE,ECC failing error code"
|
|
tree.end
|
|
tree.end
|
|
tree "RCU (Reset and Clock Unit)"
|
|
base ad:0x58024400
|
|
group.long 0x0++0x77
|
|
line.long 0x0 "CTL,Control register"
|
|
rbitfld.long 0x0 31. "IRC64MSTB,IRC64M internal 64MHz RC oscillator stabilization flag" "0,1"
|
|
bitfld.long 0x0 30. "IRC64MEN,Internal 64MHz RC oscillator enable" "0,1"
|
|
rbitfld.long 0x0 29. "PLL2STB,PLL2 clock stabilization flag" "0,1"
|
|
bitfld.long 0x0 28. "PLL2EN,PLL2 enable" "0,1"
|
|
rbitfld.long 0x0 27. "PLL1STB,PLL1 clock stabilization flag" "0,1"
|
|
bitfld.long 0x0 26. "PLL1EN,PLL1 enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 25. "PLL0STB,PLL0 clock stabilization flag" "0,1"
|
|
bitfld.long 0x0 24. "PLL0EN,PLL0 enable" "0,1"
|
|
bitfld.long 0x0 19. "CKMEN,HXTAL clock monitor enable" "0,1"
|
|
bitfld.long 0x0 18. "HXTALBPS,High speed crystal oscillator (HXTAL) clock bypass mode enable" "0,1"
|
|
rbitfld.long 0x0 17. "HXTALSTB,High speed crystal oscillator (HXTAL) clock stabilization flag" "0,1"
|
|
bitfld.long 0x0 16. "HXTALEN,High speed crystal oscillator (HXTAL) enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 7.--15. 1. "IRC64MCALIB,Internal 64MHz RC Oscillator calibration value"
|
|
hexmask.long.byte 0x0 0.--6. 1. "IRC64MADJ,Internal 64MHz RC Oscillator clock trim adjust value"
|
|
line.long 0x4 "PLL0,PLL0 register"
|
|
bitfld.long 0x4 31. "PLLSTBSRC,PLLs stabilization signal sources." "0,1"
|
|
hexmask.long.byte 0x4 24.--30. 1. "PLL0R,The PLL0R output frequency division factor from PLL0 VCO clock"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PLL0P,The PLL0P output frequency division factor from PLL0 VCO clock"
|
|
hexmask.long.word 0x4 6.--14. 1. "PLL0N,The PLL0 VCO clock multiplication factor"
|
|
hexmask.long.byte 0x4 0.--5. 1. "PLL0PSC,The PLL0 VCO source clock prescaler"
|
|
line.long 0x8 "CFG0,Clock configuration register 0"
|
|
bitfld.long 0x8 30.--31. "I2C0SEL,I2C0 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x8 27.--29. "APB3PSC,APB3 prescaler selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24.--26. "APB4PSC,APB4 prescaler selection" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 16.--21. 1. "RTCDIV,RTC clock divider factor"
|
|
bitfld.long 0x8 13.--15. "APB2PSC,APB2 prescaler selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 10.--12. "APB1PSC,APB1 prescaler selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AHBPSC,AHB and AXI prescaler selection"
|
|
rbitfld.long 0x8 2.--3. "SCSS,System clock switch status" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "SCS,System clock switch" "0,1,2,3"
|
|
line.long 0xC "INT,Clock interrupt register"
|
|
bitfld.long 0xC 28. "LCKMIC,LXTAL clock stuck interrupt clear" "0,1"
|
|
rbitfld.long 0xC 27. "LCKMIF,LXTAL clock stuck interrupt flag" "0,1"
|
|
bitfld.long 0xC 26. "LPIRC4MSTBIC,LPIRC4M stabilization interrupt clear" "0,1"
|
|
bitfld.long 0xC 25. "LPIRC4MSTBIE,LPIRC4M stabilization interrupt enable" "0,1"
|
|
rbitfld.long 0xC 24. "LPIRC4MSTBIF,LPIRC4M Clock Stuck Interrupt Flag" "0,1"
|
|
bitfld.long 0xC 23. "CKMIC,HXTAL clock stuck interrupt clear" "0,1"
|
|
newline
|
|
bitfld.long 0xC 22. "PLL2STBIC,PLL2 stabilization interrupt clear" "0,1"
|
|
bitfld.long 0xC 21. "PLL1STBIC,PLL1 stabilization interrupt clear" "0,1"
|
|
bitfld.long 0xC 20. "PLL0STBIC,PLL0 stabilization interrupt clear" "0,1"
|
|
bitfld.long 0xC 19. "HXTALSTBIC,HXTAL stabilization interrupt clear" "0,1"
|
|
bitfld.long 0xC 18. "IRC64MSTBIC,IRC64M stabilization interrupt clear" "0,1"
|
|
bitfld.long 0xC 17. "LXTALSTBIC,LXTAL stabilization interrupt clear" "0,1"
|
|
newline
|
|
bitfld.long 0xC 16. "IRC32KSTBIC,IRC32K stabilization interrupt clear" "0,1"
|
|
bitfld.long 0xC 14. "PLL2STBIE,PLL2 stabilization interrupt enable" "0,1"
|
|
bitfld.long 0xC 13. "PLL1STBIE,PLL1 stabilization interrupt enable" "0,1"
|
|
bitfld.long 0xC 12. "PLL0STBIE,PLL0 stabilization interrupt enable" "0,1"
|
|
bitfld.long 0xC 11. "HXTALSTBIE,HXTAL stabilization interrupt enable" "0,1"
|
|
bitfld.long 0xC 10. "IRC64MSTBIE,IRC64M stabilization interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "LXTALSTBIE,LXTAL stabilization interrupt enable" "0,1"
|
|
bitfld.long 0xC 8. "IRC32KSTBIE,IRC32K stabilization interrupt enable" "0,1"
|
|
rbitfld.long 0xC 7. "CKMIF,HXTAL clock stuck interrupt flag" "0,1"
|
|
rbitfld.long 0xC 6. "PLL2STBIF,PLL2 stabilization interrupt flag" "0,1"
|
|
rbitfld.long 0xC 5. "PLL1STBIF,PLL1 stabilization interrupt flag" "0,1"
|
|
rbitfld.long 0xC 4. "PLL0STBIF,PLL0 stabilization interrupt flag" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 3. "HXTALSTBIF,HXTAL stabilization interrupt flag" "0,1"
|
|
rbitfld.long 0xC 2. "IRC64MSTBIF,IRC64M stabilization interrupt flag" "0,1"
|
|
rbitfld.long 0xC 1. "LXTALSTBIF,LXTAL stabilization interrupt flag" "0,1"
|
|
rbitfld.long 0xC 0. "IRC32KSTBIF,IRC32K stabilization interrupt flag" "0,1"
|
|
line.long 0x10 "AHB1RST,AHB1 reset register"
|
|
bitfld.long 0x10 29. "USBHS1RST,USBHS1 reset" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x10 25. "ENET0RST,Ethernet0 reset" "0,1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x10 23. "DMAMUXRST,DMAMUX reset" "0,1"
|
|
bitfld.long 0x10 22. "DMA1RST,DMA1 reset" "0,1"
|
|
bitfld.long 0x10 21. "DMA0RST,DMA0 reset" "0,1"
|
|
bitfld.long 0x10 14. "USBHS0RST,USBHS0 reset" "0,1"
|
|
newline
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x10 0. "ENET1RST,Ethernet1 reset" "0,1"
|
|
endif
|
|
line.long 0x14 "AHB2RST,AHB2 reset register"
|
|
bitfld.long 0x14 7. "TMURST,TMU reset" "0,1"
|
|
bitfld.long 0x14 6. "TRNGRST,TRNG reset" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x14 4. "HAURST,HAU reset" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x14 3. "CAURST,CAU reset" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x14 2. "SDIO1RST,SDIO1 reset" "0,1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x14 1. "FACRST,FAC reset" "0,1"
|
|
newline
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x14 0. "DCIRST,DCI reset" "0,1"
|
|
endif
|
|
line.long 0x18 "AHB3RST,AHB3 reset register"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x18 9. "RTDEC1RST,RTDEC1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x18 8. "RTDEC0RST,RTDEC0 reset" "0,1"
|
|
endif
|
|
bitfld.long 0x18 6. "OSPI1RST,OSPI1 reset" "0,1"
|
|
bitfld.long 0x18 5. "OSPI0RST,OSPI0 reset" "0,1"
|
|
bitfld.long 0x18 4. "OSPIMRST,OSPIM reset" "0,1"
|
|
bitfld.long 0x18 3. "MDMARST,MDMA reset" "0,1"
|
|
newline
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x18 2. "SDIO0RST,SDIO0 reset" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x18 1. "IPARST,IPA reset" "0,1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x18 0. "EXMCRST,EXMC reset" "0,1"
|
|
line.long 0x1C "AHB4RST,AHB4 reset register"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x1C 15. "HWSEMRST,HWSEM reset" "0,1"
|
|
endif
|
|
bitfld.long 0x1C 14. "CRCRST,CRC reset" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x1C 9. "PKRST,GPIO port K reset" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x1C 8. "PJRST,GPIO port J reset" "0,1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x1C 7. "PHRST,GPIO port H reset" "0,1"
|
|
bitfld.long 0x1C 6. "PGRST,GPIO port G reset" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 5. "PFRST,GPIO port F reset" "0,1"
|
|
bitfld.long 0x1C 4. "PERST,GPIO port E reset" "0,1"
|
|
bitfld.long 0x1C 3. "PDRST,GPIO port D reset" "0,1"
|
|
bitfld.long 0x1C 2. "PCRST,GPIO port C reset" "0,1"
|
|
bitfld.long 0x1C 1. "PBRST,GPIO port B reset" "0,1"
|
|
bitfld.long 0x1C 0. "PARST,GPIO port A reset" "0,1"
|
|
line.long 0x20 "APB1RST,APB1 reset register"
|
|
bitfld.long 0x20 31. "UART7RST,UART7 reset" "0,1"
|
|
bitfld.long 0x20 30. "UART6RST,UART6 reset" "0,1"
|
|
bitfld.long 0x20 29. "DACRST,DAC reset" "0,1"
|
|
bitfld.long 0x20 28. "DACHOLDRST,DAC hold clock reset" "0,1"
|
|
bitfld.long 0x20 27. "CTCRST,CTC reset" "0,1"
|
|
bitfld.long 0x20 24. "I2C3RST,I2C3 reset" "0,1"
|
|
newline
|
|
bitfld.long 0x20 23. "I2C2RST,I2C2 reset" "0,1"
|
|
bitfld.long 0x20 22. "I2C1RST,I2C1 reset" "0,1"
|
|
bitfld.long 0x20 21. "I2C0RST,I2C0 reset" "0,1"
|
|
bitfld.long 0x20 20. "UART4RST,UART4 reset" "0,1"
|
|
bitfld.long 0x20 19. "UART3RST,UART3 reset" "0,1"
|
|
bitfld.long 0x20 18. "USART2RST,USART2 reset" "0,1"
|
|
newline
|
|
bitfld.long 0x20 17. "USART1RST,USART1 reset" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x20 16. "MDIORST,MDIO reset" "0,1"
|
|
endif
|
|
bitfld.long 0x20 15. "SPI2RST,SPI2 reset" "0,1"
|
|
bitfld.long 0x20 14. "SPI1RST,SPI1 reset" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x20 13. "RSPDIFRST,RSPDIF reset" "0,1"
|
|
endif
|
|
bitfld.long 0x20 11. "TIMER51RST,TIMER51 reset" "0,1"
|
|
newline
|
|
bitfld.long 0x20 10. "TIMER50RST,TIMER50 reset" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x20 9. "TIMER31RST,TIMER31 reset" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x20 8. "TIMER30RST,TIMER30 reset" "0,1"
|
|
endif
|
|
bitfld.long 0x20 7. "TIMER23RST,TIMER23 reset" "0,1"
|
|
bitfld.long 0x20 6. "TIMER22RST,TIMER22 reset" "0,1"
|
|
bitfld.long 0x20 5. "TIMER6RST,TIMER6 reset" "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "TIMER5RST,TIMER5 reset" "0,1"
|
|
bitfld.long 0x20 3. "TIMER4RST,TIMER4 reset" "0,1"
|
|
bitfld.long 0x20 2. "TIMER3RST,TIMER3 reset" "0,1"
|
|
bitfld.long 0x20 1. "TIMER2RST,TIMER2 reset" "0,1"
|
|
bitfld.long 0x20 0. "TIMER1RST,TIMER1 reset" "0,1"
|
|
line.long 0x24 "APB2RST,APB2 reset register"
|
|
bitfld.long 0x24 31. "TRIGSELRST,TRIGSEL reset" "0,1"
|
|
bitfld.long 0x24 30. "EDOUTRST,EDOUT reset" "0,1"
|
|
bitfld.long 0x24 29. "TIMER44RST,TIMER44 reset" "0,1"
|
|
bitfld.long 0x24 28. "TIMER43RST,TIMER43 reset" "0,1"
|
|
bitfld.long 0x24 27. "TIMER42RST,TIMER42 reset" "0,1"
|
|
bitfld.long 0x24 26. "TIMER41RST,TIMER41 reset" "0,1"
|
|
newline
|
|
bitfld.long 0x24 25. "TIMER40RST,TIMER40 reset" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x24 24. "SAI2RST,SAI2 reset" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x24 23. "SAI1RST,SAI1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x24 22. "SAI0RST,SAI0 reset" "0,1"
|
|
endif
|
|
bitfld.long 0x24 21. "SPI5RST,SPI5 reset" "0,1"
|
|
bitfld.long 0x24 20. "SPI4RST,SPI4 reset" "0,1"
|
|
newline
|
|
bitfld.long 0x24 19. "HPDFRST,HPDF reset" "0,1"
|
|
bitfld.long 0x24 18. "TIMER16RST,TIMER16 reset" "0,1"
|
|
bitfld.long 0x24 17. "TIMER15RST,TIMER15 reset" "0,1"
|
|
bitfld.long 0x24 16. "TIMER14RST,TIMER14 reset" "0,1"
|
|
bitfld.long 0x24 13. "SPI3RST,SPI3 reset" "0,1"
|
|
bitfld.long 0x24 12. "SPI0RST,SPI0 reset" "0,1"
|
|
newline
|
|
bitfld.long 0x24 10. "ADC2RST,ADC2 reset" "0,1"
|
|
bitfld.long 0x24 9. "ADC1RST,ADC1 reset" "0,1"
|
|
bitfld.long 0x24 8. "ADC0RST,ADC0 reset" "0,1"
|
|
bitfld.long 0x24 5. "USART5RST,USART5 reset" "0,1"
|
|
bitfld.long 0x24 4. "USART0RST,USART0 reset" "0,1"
|
|
bitfld.long 0x24 1. "TIMER7RST,TIMER7 reset" "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "TIMER0RST,TIMER0 reset" "0,1"
|
|
line.long 0x28 "APB3RST,APB3 reset register"
|
|
bitfld.long 0x28 1. "WWDGTRST,WWDGT reset" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x28 0. "TLIRST,TLI reset" "0,1"
|
|
endif
|
|
line.long 0x2C "APB4RST,APB4 reset register"
|
|
bitfld.long 0x2C 4. "PMURST,PMU reset" "0,1"
|
|
bitfld.long 0x2C 3. "LPDTSRST,LPDTS reset" "0,1"
|
|
bitfld.long 0x2C 2. "VREFRST,VREF reset" "0,1"
|
|
bitfld.long 0x2C 1. "CMPRST,CMP reset" "0,1"
|
|
bitfld.long 0x2C 0. "SYSCFGRST,SYSCFG reset" "0,1"
|
|
line.long 0x30 "AHB1EN,AHB1 enable register"
|
|
bitfld.long 0x30 30. "USBHS1ULPIEN,USBHS1 ULPI clock enable" "0,1"
|
|
bitfld.long 0x30 29. "USBHS1EN,USBHS1 clock enable" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x30 28. "ENET0PTPEN,Ethernet0 PTP clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x30 27. "ENET0RXEN,Ethernet0 RX clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x30 26. "ENET0TXEN,Ethernet0 TX clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x30 25. "ENET0EN,Ethernet0 clock enable" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x30 23. "DMAMUXEN,DMAMUX clock enable" "0,1"
|
|
bitfld.long 0x30 22. "DMA1EN,DMA1 clock enable" "0,1"
|
|
bitfld.long 0x30 21. "DMA0EN,DMA0 clock enable" "0,1"
|
|
bitfld.long 0x30 15. "USBHS0ULPIEN,USBHS0 ULPI clock enable" "0,1"
|
|
bitfld.long 0x30 14. "USBHS0EN,USBHS0 clock enable" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x30 3. "ENET1PTPEN,Ethernet1 PTP clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x30 2. "ENET1RXEN,Ethernet1 RX clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x30 1. "ENET1TXEN,Ethernet1 TX clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x30 0. "ENET1EN,Ethernet1 clock enable" "0,1"
|
|
endif
|
|
line.long 0x34 "AHB2EN,AHB2 enable register"
|
|
bitfld.long 0x34 8. "RAMECCMU1EN,RAMECCMU1 clock enable" "0,1"
|
|
bitfld.long 0x34 7. "TMUEN,TMU clock enable" "0,1"
|
|
bitfld.long 0x34 6. "TRNGEN,TRNG clock enable" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x34 4. "HAUEN,HAU clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x34 3. "CAUEN,CAU clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x34 2. "SDIO1EN,SDIO1 clock enable" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x34 1. "FACEN,FAC clock enable" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x34 0. "DCIEN,DCI clock enable" "0,1"
|
|
endif
|
|
line.long 0x38 "AHB3EN,AHB3 enable register"
|
|
bitfld.long 0x38 15. "CPUEN,CPU clock enable" "0,1"
|
|
bitfld.long 0x38 10. "RAMECCMU0EN,RAMECCMU0 clock enable" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x38 9. "RTDEC1EN,RTDEC1 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x38 8. "RTDEC0EN,RTDEC0 clock enable" "0,1"
|
|
endif
|
|
bitfld.long 0x38 6. "OSPI1EN,OSPI1 clock enable" "0,1"
|
|
bitfld.long 0x38 5. "OSPI0EN,OSPI0 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x38 4. "OSPIMEN,OSPIM clock enable" "0,1"
|
|
bitfld.long 0x38 3. "MDMAEN,MDMA clock enable" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x38 2. "SDIO0EN,SDIO0 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x38 1. "IPAEN,IPA clock enable" "0,1"
|
|
endif
|
|
bitfld.long 0x38 0. "EXMCEN,EXMC clock enable" "0,1"
|
|
line.long 0x3C "AHB4EN,AHB4 enable register"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x3C 15. "HWSEMEN,HWSEM clock enable" "0,1"
|
|
endif
|
|
bitfld.long 0x3C 14. "CRCEN,CRC clock enable" "0,1"
|
|
bitfld.long 0x3C 13. "BKPSRAMEN,Backup SRAM clock enable" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x3C 9. "PKEN,GPIO port K clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x3C 8. "PJEN,GPIO port J clock enable" "0,1"
|
|
endif
|
|
bitfld.long 0x3C 7. "PHEN,GPIO port H clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 6. "PGEN,GPIO port G clock enable" "0,1"
|
|
bitfld.long 0x3C 5. "PFEN,GPIO port F clock enable" "0,1"
|
|
bitfld.long 0x3C 4. "PEEN,GPIO port E clock enable" "0,1"
|
|
bitfld.long 0x3C 3. "PDEN,GPIO port D clock enable" "0,1"
|
|
bitfld.long 0x3C 2. "PCEN,GPIO port C clock enable" "0,1"
|
|
bitfld.long 0x3C 1. "PBEN,GPIO port B clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 0. "PAEN,GPIO port A clock enable" "0,1"
|
|
line.long 0x40 "APB1EN,APB1 enable register"
|
|
bitfld.long 0x40 31. "UART7EN,UART7 clock enable" "0,1"
|
|
bitfld.long 0x40 30. "UART6EN,UART6 clock enable" "0,1"
|
|
bitfld.long 0x40 29. "DACEN,DAC clock enable" "0,1"
|
|
bitfld.long 0x40 28. "DACHOLDEN,DAC hold clock enable" "0,1"
|
|
bitfld.long 0x40 27. "CTCEN,CTC clock enable" "0,1"
|
|
bitfld.long 0x40 24. "I2C3EN,I2C3 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x40 23. "I2C2EN,I2C2 clock enable" "0,1"
|
|
bitfld.long 0x40 22. "I2C1EN,I2C1 clock enable" "0,1"
|
|
bitfld.long 0x40 21. "I2C0EN,I2C0 clock enable" "0,1"
|
|
bitfld.long 0x40 20. "UART4EN,UART4 clock enable" "0,1"
|
|
bitfld.long 0x40 19. "UART3EN,UART3 clock enable" "0,1"
|
|
bitfld.long 0x40 18. "USART2EN,USART2 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x40 17. "USART1EN,USART1 clock enable" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x40 16. "MDIOEN,MDIO clock enable" "0,1"
|
|
endif
|
|
bitfld.long 0x40 15. "SPI2EN,SPI2 clock enable" "0,1"
|
|
bitfld.long 0x40 14. "SPI1EN,SPI1 clock enable" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x40 13. "RSPDIFEN,RSPDIF clock enable" "0,1"
|
|
endif
|
|
bitfld.long 0x40 11. "TIMER51EN,TIMER51 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x40 10. "TIMER50EN,TIMER50 clock enable" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x40 9. "TIMER31EN,TIMER31 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x40 8. "TIMER30EN,TIMER30 clock enable" "0,1"
|
|
endif
|
|
bitfld.long 0x40 7. "TIMER23EN,TIMER23 clock enable" "0,1"
|
|
bitfld.long 0x40 6. "TIMER22EN,TIMER22 clock enable" "0,1"
|
|
bitfld.long 0x40 5. "TIMER6EN,TIMER6 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x40 4. "TIMER5EN,TIMER5 clock enable" "0,1"
|
|
bitfld.long 0x40 3. "TIMER4EN,TIMER4 clock enable" "0,1"
|
|
bitfld.long 0x40 2. "TIMER3EN,TIMER3 clock enable" "0,1"
|
|
bitfld.long 0x40 1. "TIMER2EN,TIMER2 clock enable" "0,1"
|
|
bitfld.long 0x40 0. "TIMER1EN,TIMER1 clock enable" "0,1"
|
|
line.long 0x44 "APB2EN,APB2 enable register"
|
|
bitfld.long 0x44 31. "TRIGSELEN,TRIGSEL clock enable" "0,1"
|
|
bitfld.long 0x44 30. "EDOUTEN,EDOUT clock enable" "0,1"
|
|
bitfld.long 0x44 29. "TIMER44EN,TIMER44 clock enable" "0,1"
|
|
bitfld.long 0x44 28. "TIMER43EN,TIMER43 clock enable" "0,1"
|
|
bitfld.long 0x44 27. "TIMER42EN,TIMER42 clock enable" "0,1"
|
|
bitfld.long 0x44 26. "TIMER41EN,TIMER41 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 25. "TIMER40EN,TIMER40 clock enable" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x44 24. "SAI2EN,SAI2 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x44 23. "SAI1EN,SAI1 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x44 22. "SAI0EN,SAI0 clock enable" "0,1"
|
|
endif
|
|
bitfld.long 0x44 21. "SPI5EN,SPI5 clock enable" "0,1"
|
|
bitfld.long 0x44 20. "SPI4EN,SPI4 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 19. "HPDFEN,HPDF clock enable" "0,1"
|
|
bitfld.long 0x44 18. "TIMER16EN,TIMER16 clock enable" "0,1"
|
|
bitfld.long 0x44 17. "TIMER15EN,TIMER15 clock enable" "0,1"
|
|
bitfld.long 0x44 16. "TIMER14EN,TIMER14 clock enable" "0,1"
|
|
bitfld.long 0x44 13. "SPI3EN,SPI3 clock enable" "0,1"
|
|
bitfld.long 0x44 12. "SPI0EN,SPI0 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 10. "ADC2EN,ADC2 clock enable" "0,1"
|
|
bitfld.long 0x44 9. "ADC1EN,ADC1 clock enable" "0,1"
|
|
bitfld.long 0x44 8. "ADC0EN,ADC0 clock enable" "0,1"
|
|
bitfld.long 0x44 5. "USART5EN,USART5 clock enable" "0,1"
|
|
bitfld.long 0x44 4. "USART0EN,USART0 clock enable" "0,1"
|
|
bitfld.long 0x44 1. "TIMER7EN,TIMER7 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 0. "TIMER0EN,TIMER0 clock enable" "0,1"
|
|
line.long 0x48 "APB3EN,APB3 enable register"
|
|
bitfld.long 0x48 1. "WWDGTEN,WWDGT clock enable" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x48 0. "TLIEN,TLI clock enable" "0,1"
|
|
endif
|
|
line.long 0x4C "APB4EN,APB4 enable register"
|
|
bitfld.long 0x4C 4. "PMUEN,PMU clock enable" "0,1"
|
|
bitfld.long 0x4C 3. "LPDTSEN,LPDTS clock enable" "0,1"
|
|
bitfld.long 0x4C 2. "VREFEN,VREF clock enable" "0,1"
|
|
bitfld.long 0x4C 1. "CMPEN,CMP clock enable" "0,1"
|
|
bitfld.long 0x4C 0. "SYSCFGEN,SYSCFG clock enable" "0,1"
|
|
line.long 0x50 "AHB1SPEN,AHB1 sleep mode enable register"
|
|
bitfld.long 0x50 30. "USBHS1ULPISPEN,USBHS1 ULPI clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x50 29. "USBHS1SPEN,USBHS1 clock enable when sleep mode" "0,1"
|
|
newline
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x50 28. "ENET0PTPSPEN,Ethernet0 PTP clock enable when sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x50 27. "ENET0RXSPEN,Ethernet0 RX clock enable when sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x50 26. "ENET0TXSPEN,Ethernet0 TX clock enable when sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x50 25. "ENET0SPEN,Ethernet0 clock enable when sleep mode" "0,1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x50 23. "DMAMUXSPEN,DMAMUX clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x50 22. "DMA1SPEN,DMA1 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x50 21. "DMA0SPEN,DMA0 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x50 17. "SRAM1SPEN,SRAM1 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x50 16. "SRAM0SPEN,SRAM0 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x50 15. "USBHS0ULPISPEN,USBHS0 ULPI clock enable when sleep mode" "0,1"
|
|
newline
|
|
bitfld.long 0x50 14. "USBHS0SPEN,USBHS0 clock enable when sleep mode" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x50 3. "ENET1PTPSPEN,Ethernet1 PTP clock enable when sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x50 2. "ENET1RXSPEN,Ethernet1 RX clock enable when sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x50 1. "ENET1TXSPEN,Ethernet1 TX clock enable when sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x50 0. "ENET1SPEN,Ethernet1 clock enable when sleep mode" "0,1"
|
|
endif
|
|
line.long 0x54 "AHB2SPEN,AHB2 sleep mode enable register"
|
|
bitfld.long 0x54 8. "RAMECCMU1SPEN,RAMECCMU1 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x54 7. "TMUSPEN,TMU clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x54 6. "TRNGSPEN,TRNG clock enable when sleep mode" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x54 4. "HAUSPEN,HAU enable when sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x54 3. "CAUSPEN,CAU clock enable when sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x54 2. "SDIO1SPEN,SDIO1 clock enable when sleep mode" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x54 1. "FACSPEN,FAC clock enable when sleep mode" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x54 0. "DCISPEN,DCI clock enable when sleep mode" "0,1"
|
|
endif
|
|
line.long 0x58 "AHB3SPEN,AHB3 sleep mode enable register"
|
|
bitfld.long 0x58 15. "FMCSPEN,FMC clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x58 14. "AXISRAMSPEN,AXI SRAM clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x58 10. "RAMECCMU0SPEN,RAMECCMU0 clock enable when sleep mode" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x58 9. "RTDEC1SPEN,RTDEC1 clock enable when sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x58 8. "RTDEC0SPEN,RTDEC0 clock enable when sleep mode" "0,1"
|
|
endif
|
|
bitfld.long 0x58 6. "OSPI1SPEN,OSPI1 clock enable when sleep mode" "0,1"
|
|
newline
|
|
bitfld.long 0x58 5. "OSPI0SPEN,OSPI0 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x58 4. "OSPIMSPEN,OSPIM clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x58 3. "MDMASPEN,MDMA clock enable when sleep mode" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x58 2. "SDIO0SPEN,SDIO0 clock enable when sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x58 1. "IPASPEN,IPA clock enable when sleep mode" "0,1"
|
|
endif
|
|
bitfld.long 0x58 0. "EXMCSPEN,EXMC clock enable when sleep mode" "0,1"
|
|
line.long 0x5C "AHB4SPEN,AHB4 sleep mode enable register"
|
|
bitfld.long 0x5C 14. "CRCSPEN,CRC clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x5C 13. "BKPSRAMSPEN,Backup SRAM clock enable when sleep mode" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x5C 9. "PKSPEN,GPIO port K clock enable when sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x5C 8. "PJSPEN,GPIO port J clock enable when sleep mode" "0,1"
|
|
endif
|
|
bitfld.long 0x5C 7. "PHSPEN,GPIO port H clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x5C 6. "PGSPEN,GPIO port G clock enable when sleep mode" "0,1"
|
|
newline
|
|
bitfld.long 0x5C 5. "PFSPEN,GPIO port F clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x5C 4. "PESPEN,GPIO port E clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x5C 3. "PDSPEN,GPIO port D clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x5C 2. "PCSPEN,GPIO port C clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x5C 1. "PBSPEN,GPIO port B clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x5C 0. "PASPEN,GPIO port A clock enable when sleep mode" "0,1"
|
|
line.long 0x60 "APB1SPEN,APB1 sleep mode enable register"
|
|
bitfld.long 0x60 31. "UART7SPEN,UART7 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x60 30. "UART6SPEN,UART6 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x60 29. "DACSPEN,DAC clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x60 28. "DACHOLDSPEN,DAC hold clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x60 27. "CTCSPEN,CTC clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x60 24. "I2C3SPEN,I2C3 clock enable when sleep mode" "0,1"
|
|
newline
|
|
bitfld.long 0x60 23. "I2C2SPEN,I2C2 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x60 22. "I2C1SPEN,I2C1 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x60 21. "I2C0SPEN,I2C0 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x60 20. "UART4SPEN,UART4 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x60 19. "UART3SPEN,UART3 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x60 18. "USART2SPEN,USART2 clock enable when sleep mode" "0,1"
|
|
newline
|
|
bitfld.long 0x60 17. "USART1SPEN,USART1 clock enable when sleep mode" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x60 16. "MDIOSPEN,MDIO clock enable when sleep mode" "0,1"
|
|
endif
|
|
bitfld.long 0x60 15. "SPI2SPEN,SPI2 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x60 14. "SPI1SPEN,SPI1 clock enable when sleep mode" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x60 13. "RSPDIFSPEN,RSPDIF clock enable when sleep mode" "0,1"
|
|
endif
|
|
bitfld.long 0x60 11. "TIMER51SPEN,TIMER51 clock enable when sleep mode" "0,1"
|
|
newline
|
|
bitfld.long 0x60 10. "TIMER50SPEN,TIMER50 clock enable when sleep mode" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x60 9. "TIMER31SPEN,TIMER31 clock enable when sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x60 8. "TIMER30SPEN,TIMER30 clock enable when sleep mode" "0,1"
|
|
endif
|
|
bitfld.long 0x60 7. "TIMER23SPEN,TIMER23 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x60 6. "TIMER22SPEN,TIMER22 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x60 5. "TIMER6SPEN,TIMER6 clock enable when sleep mode" "0,1"
|
|
newline
|
|
bitfld.long 0x60 4. "TIMER5SPEN,TIMER5 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x60 3. "TIMER4SPEN,TIMER4 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x60 2. "TIMER3SPEN,TIMER3 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x60 1. "TIMER2SPEN,TIMER2 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x60 0. "TIMER1SPEN,TIMER1 clock enable when sleep mode" "0,1"
|
|
line.long 0x64 "APB2SPEN,APB2 sleep mode enable register"
|
|
bitfld.long 0x64 31. "TRIGSELSPEN,TRIGSEL clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x64 30. "EDOUTSPEN,EDOUT clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x64 29. "TIMER44SPEN,TIMER44 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x64 28. "TIMER43SPEN,TIMER43 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x64 27. "TIMER42SPEN,TIMER42 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x64 26. "TIMER41SPEN,TIMER41 clock enable when sleep mode" "0,1"
|
|
newline
|
|
bitfld.long 0x64 25. "TIMER40SPEN,TIMER40 clock enable when sleep mode" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x64 24. "SAI2SPEN,SAI2 clock enable when sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x64 23. "SAI1SPEN,SAI1 clock enable when sleep mode" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x64 22. "SAI0SPEN,SAI0 clock enable when sleep mode" "0,1"
|
|
endif
|
|
bitfld.long 0x64 21. "SPI5SPEN,SPI5 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x64 20. "SPI4SPEN,SPI4 clock enable when sleep mode" "0,1"
|
|
newline
|
|
bitfld.long 0x64 19. "HPDFSPEN,HPDF clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x64 18. "TIMER16SPEN,TIMER16 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x64 17. "TIMER15SPEN,TIMER15 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x64 16. "TIMER14SPEN,TIMER14 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x64 13. "SPI3SPEN,SPI3 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x64 12. "SPI0SPEN,SPI0 clock enable when sleep mode" "0,1"
|
|
newline
|
|
bitfld.long 0x64 10. "ADC2SPEN,ADC2 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x64 9. "ADC1SPEN,ADC1 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x64 8. "ADC0SPEN,ADC0 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x64 5. "USART5SPEN,USART5 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x64 4. "USART0SPEN,USART0 clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x64 1. "TIMER7SPEN,TIMER7 clock enable when sleep mode" "0,1"
|
|
newline
|
|
bitfld.long 0x64 0. "TIMER0SPEN,TIMER0 clock enable when sleep mode" "0,1"
|
|
line.long 0x68 "APB3SPEN,APB3 sleep mode enable register"
|
|
bitfld.long 0x68 1. "WWDGTSPEN,WWDGT clock enable when sleep mode" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x68 0. "TLISPEN,TLI clock enable when sleep mode" "0,1"
|
|
endif
|
|
line.long 0x6C "APB4SPEN,APB4 sleep mode enable register"
|
|
bitfld.long 0x6C 4. "PMUSPEN,PMU clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x6C 3. "LPDTSSPEN,LPDTS clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x6C 2. "VREFSPEN,VREF clock enable when sleep mode" "0,1"
|
|
bitfld.long 0x6C 1. "CMPSPEN,CMPclock enable when sleep mode" "0,1"
|
|
bitfld.long 0x6C 0. "SYSCFGSPEN,SYSCFG clock enable when sleep mode" "0,1"
|
|
line.long 0x70 "BDCTL,Backup domain control register"
|
|
bitfld.long 0x70 16. "BKPRST,Backup domain reset" "0,1"
|
|
bitfld.long 0x70 15. "RTCEN,RTC clock enable" "0,1"
|
|
bitfld.long 0x70 8.--9. "RTCSRC,RTC clock entry selection" "0,1,2,3"
|
|
rbitfld.long 0x70 6. "LCKMD,LXTAL clock failure detection" "0,1"
|
|
bitfld.long 0x70 5. "LCKMEN,LXTAL clock monitor enable" "0,1"
|
|
bitfld.long 0x70 3.--4. "LXTALDRI,LXTAL drive capability" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x70 2. "LXTALBPS,LXTAL bypass mode enable" "0,1"
|
|
rbitfld.long 0x70 1. "LXTALSTB,Low speed crystal oscillator stabilization flag" "0,1"
|
|
bitfld.long 0x70 0. "LXTALEN,LXTAL enable" "0,1"
|
|
line.long 0x74 "RSTSCK,Reset source/clock register"
|
|
rbitfld.long 0x74 31. "LPRSTF,Low-power reset flag" "0,1"
|
|
rbitfld.long 0x74 30. "WWDGTRSTF,Window watchdog timer reset flag" "0,1"
|
|
rbitfld.long 0x74 29. "FWDGTRSTF,Free watchdog timer reset flag" "0,1"
|
|
rbitfld.long 0x74 28. "SWRSTF,Software reset flag" "0,1"
|
|
rbitfld.long 0x74 27. "PORRSTF,Power reset flag" "0,1"
|
|
rbitfld.long 0x74 26. "EPRSTF,External PIN reset flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x74 25. "BORRSTF,BOR reset flag" "0,1"
|
|
bitfld.long 0x74 24. "RSTFC,Reset flag clear" "0,1"
|
|
rbitfld.long 0x74 1. "IRC32KSTB,IRC32K stabilization flag" "0,1"
|
|
bitfld.long 0x74 0. "IRC32KEN,IRC32K enable" "0,1"
|
|
group.long 0x80++0x27
|
|
line.long 0x0 "PLLADDCTL,PLL clock additional control register"
|
|
bitfld.long 0x0 31. "PLL2PEN,PLL2P divider output enable" "0,1"
|
|
bitfld.long 0x0 30. "PLL2REN,PLL2R divider output enable" "0,1"
|
|
bitfld.long 0x0 29. "PLL2QEN,PLL2Q divider output enable" "0,1"
|
|
bitfld.long 0x0 28. "PLL1PEN,PLL1P divider output enable" "0,1"
|
|
bitfld.long 0x0 27. "PLL1REN,PLL1R divider output enable" "0,1"
|
|
bitfld.long 0x0 26. "PLL1QEN,PLL1Q divider output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PLL0PEN,PLL0P divider output enable" "0,1"
|
|
bitfld.long 0x0 24. "PLL0REN,PLL0R divider output enable" "0,1"
|
|
bitfld.long 0x0 23. "PLL0QEN,PLL0Q divider output enable" "0,1"
|
|
hexmask.long.byte 0x0 16.--22. 1. "PLL2Q,The PLL2Q output frequency division factor from PLL2 VCO clock"
|
|
hexmask.long.byte 0x0 8.--14. 1. "PLL1Q,The PLL1Q output frequency division factor from PLL1 VCO clock"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PLL0Q,The PLL0Q output frequency division factor from PLL0 VCO clock"
|
|
line.long 0x4 "PLL1,PLL1 register"
|
|
hexmask.long.byte 0x4 24.--30. 1. "PLL1R,The PLL1R output frequency division factor from PLL1 VCO clock"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PLL1P,The PLL1P output frequency division factor from PLL1 VCO clock"
|
|
hexmask.long.word 0x4 6.--14. 1. "PLL1N,The PLL1 VCO clock multiplication factor"
|
|
hexmask.long.byte 0x4 0.--5. 1. "PLL1PSC,The PLL1 VCO source clock prescaler"
|
|
line.long 0x8 "PLL2,PLL2 register"
|
|
hexmask.long.byte 0x8 24.--30. 1. "PLL2R,The PLL2R output frequency division factor from PLL2 VCO clock"
|
|
hexmask.long.byte 0x8 16.--22. 1. "PLL2P,The PLL2 P output frequency division factor from PLL2 VCO clock"
|
|
hexmask.long.word 0x8 6.--14. 1. "PLL2N,The PLL2 VCO clock multiplication factor"
|
|
hexmask.long.byte 0x8 0.--5. 1. "PLL2PSC,The PLL2 VCO source clock prescaler"
|
|
line.long 0xC "CFG1,Clock configuration register 1"
|
|
bitfld.long 0xC 31. "HPDFSEL,HPDF clock source selection" "0,1"
|
|
bitfld.long 0xC 24. "TIMERSEL,TIMER clock selection" "0,1"
|
|
bitfld.long 0xC 22.--23. "USART5SEL,USART5 clock source selection" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "USART2SEL,USART2 clock source selection" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "USART1SEL,USART1 clock source selection" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PLL2RDIV,The divider factor from PLL2R clock" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 14.--15. "PERSEL,CK_PER clock selection" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "CAN2SEL,CAN2 clock source selection" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "CAN1SEL,CAN1 clock selection" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "CAN0SEL,CAN0 clock source selection" "0,1,2,3"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0xC 4.--5. "RSPDIFSEL,RSPDIF clock selection" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0xC 0.--1. "USART0SEL,USART0 clock source selection" "0,1,2,3"
|
|
line.long 0x10 "CFG2,Clock configuration register 2"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x10 28.--30. "SAI2B1SEL,SAI2 Block 1 clock selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x10 24.--26. "SAI2B0SEL,SAI2 Block 0 clock selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x10 20.--22. "SAI1SEL,SAI1 clock selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x10 16.--18. "HPDFASEL,HPDF audio clock source selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x10 16.--18. "SAI0SEL,SA0 and HPDF audio clock selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
bitfld.long 0x10 12.--14. "CKOUT1SEL,CKOUT1 clock source selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--11. 1. "CKOUT1DIV,The CK_OUT1 divider which the CK_OUT1 frequency can be reduced"
|
|
bitfld.long 0x10 4.--6. "CKOUT0SEL,CKOUT0 clock source selection" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x10 0.--3. 1. "CKOUT0DIV,The CK_OUT0 divider which the CK_OUT0 frequency can be reduced"
|
|
line.long 0x14 "CFG3,Clock configuration register 3"
|
|
bitfld.long 0x14 28.--29. "ADC2SEL,ADC2 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x14 26.--27. "ADC01SEL,ADC0 and ADC1 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x14 24. "DSPWUSSEL,Deep-sleep wakeup system clock source selection" "0,1"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x14 12. "SDIO1SEL,SDIO1 clock source selection" "0,1"
|
|
endif
|
|
bitfld.long 0x14 4.--5. "I2C3SEL,I2C3 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. "I2C2SEL,I2C2 clock source selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 0.--1. "I2C1SEL,I2C1 clock source selection" "0,1,2,3"
|
|
line.long 0x18 "PLLALL,PLL all configuration register"
|
|
bitfld.long 0x18 16.--17. "PLLSEL,PLLs clock source selection" "0,1,2,3"
|
|
bitfld.long 0x18 10. "PLL2VCOSEL,PLL2 VCO selection" "0,1"
|
|
bitfld.long 0x18 8.--9. "PLL2RNG,PLL2 input clock range" "0,1,2,3"
|
|
bitfld.long 0x18 6. "PLL1VCOSEL,PLL1 VCO selection" "0,1"
|
|
bitfld.long 0x18 4.--5. "PLL1RNG,PLL1 input clock range" "0,1,2,3"
|
|
bitfld.long 0x18 2. "PLL0VCOSEL,PLL0 VCO selection" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--1. "PLL0RNG,PLL0 input clock range" "0,1,2,3"
|
|
line.long 0x1C "PLL0FRA,PLL0 fraction configuration register"
|
|
bitfld.long 0x1C 15. "PLL0FRAEN,PLL0 fractional latch enable." "0,1"
|
|
hexmask.long.word 0x1C 0.--12. 1. "PLL0FRAN,Fractional part of the multiplication factor for PLL0 VCO"
|
|
line.long 0x20 "PLL1FRA,PLL1 fraction configuration register"
|
|
bitfld.long 0x20 15. "PLL1FRAEN,PLL1 fractional latch enable." "0,1"
|
|
hexmask.long.word 0x20 0.--12. 1. "PLL1FRAN,Fractional part of the multiplication factor for PLL1 VCO"
|
|
line.long 0x24 "PLL2FRA,PLL2 fraction configuration register"
|
|
bitfld.long 0x24 15. "PLL2FRAEN,PLL2 fractional latch enable." "0,1"
|
|
hexmask.long.word 0x24 0.--12. 1. "PLL2FRAN,Fractional part of the multiplication factor for PLL2 VCO"
|
|
group.long 0xC0++0x7
|
|
line.long 0x0 "ADDCTL0,Additional clock control register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "IRC48MCALIB,Internal 48MHz RC oscillator calibration value register"
|
|
rbitfld.long 0x0 17. "IRC48MSTB,Internal 48MHz RC oscillator clock stabilization Flag" "0,1"
|
|
bitfld.long 0x0 16. "IRC48MEN,Internal 48MHz RC oscillator enable" "0,1"
|
|
bitfld.long 0x0 1. "PLL48MSEL,PLL48M clock selection" "0,1"
|
|
bitfld.long 0x0 0. "CK48MSEL,48MHz clock selection" "0,1"
|
|
line.long 0x4 "ADDCTL1,Additional clock control register"
|
|
rbitfld.long 0x4 31. "PLLUSBHS1STB,PLLUSBHS1 clock stabilization flag" "0,1"
|
|
bitfld.long 0x4 30. "PLLUSBHS1EN,PLLUSBHS1 clock enable" "0,1"
|
|
rbitfld.long 0x4 29. "PLLUSBHS0STB,PLLUSBHS0 clock stabilization flag" "0,1"
|
|
bitfld.long 0x4 28. "PLLUSBHS0EN,PLLUSBHS0 clock enable" "0,1"
|
|
bitfld.long 0x4 20. "LPIRC4MDSPEN,LPIRC4M clock enable in deepsleep mode" "0,1"
|
|
bitfld.long 0x4 16.--17. "IRC64MDIV,IRC64M clock divider" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "LPIRC4MCALIB,LPIRC4M calibration value"
|
|
hexmask.long.byte 0x4 2.--7. 1. "LPIRC4MADJ,LPIRC4M frequency clock trim adjust value"
|
|
rbitfld.long 0x4 1. "LPIRC4MSTB,LPIRC4M clock stabilization flag" "0,1"
|
|
bitfld.long 0x4 0. "LPIRC4MEN,LPIRC4M clock enable" "0,1"
|
|
group.long 0xCC++0xF
|
|
line.long 0x0 "ADDINT,Additional clock interrupt register"
|
|
bitfld.long 0x0 22. "IRC48MSTBIC,Internal 48 MHz RC oscillator Stabilization interrupt clear" "0,1"
|
|
bitfld.long 0x0 21. "PLLUSBHS1STBIC,Internal PLL of USBHS1 Stabilization interrupt clear" "0,1"
|
|
bitfld.long 0x0 20. "PLLUSBHS0STBIC,Internal PLL of USBHS0 Stabilization interrupt clear" "0,1"
|
|
bitfld.long 0x0 14. "IRC48MSTBIE,Internal 48 MHz RC oscillator Stabilization interrupt enable" "0,1"
|
|
bitfld.long 0x0 13. "PLLUSBHS1STBIE,Internal PLL of USBHS1 Stabilization interrupt enable" "0,1"
|
|
bitfld.long 0x0 12. "PLLUSBHS0STBIE,Internal PLL of USBHS0 Stabilization interrupt enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 6. "IRC48MSTBIF,IRC48M stabilization interrupt flag" "0,1"
|
|
rbitfld.long 0x0 5. "PLLUSBHS1STBIF,Internal PLL of USBHS1 stabilization interrupt flag" "0,1"
|
|
rbitfld.long 0x0 4. "PLLUSBHS0STBIF,Internal PLL of USBHS0 stabilization interrupt flag" "0,1"
|
|
line.long 0x4 "CFG4,Clock configuration register 4"
|
|
bitfld.long 0x4 8.--9. "EXMCSEL,EXMC clock source selection" "0,1,2,3"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x4 0. "SDIO0SEL,SDIO0 clock source selection" "0,1"
|
|
endif
|
|
line.long 0x8 "USBCLKCTL,USB clock control register"
|
|
bitfld.long 0x8 19.--21. "USBHS1PSC,USBHS1 clock prescaler selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16.--18. "USBHS0PSC,USBHS0 clock prescaler selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 13.--14. "USBHS148MSEL,USBHS1 48M clock source selection" "0,1,2,3"
|
|
bitfld.long 0x8 12. "USBHS1SWEN,USBHS1 clock source selection enable" "0,1"
|
|
bitfld.long 0x8 11. "PLLUSBHS1PRESEL,PLLUSBHS1 clock source preselection" "0,1"
|
|
bitfld.long 0x8 9. "USBHS1SEL,USBHS1 clock source selection" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5.--6. "USBHS048MSEL,USBHS0 48M clock source selection" "0,1,2,3"
|
|
bitfld.long 0x8 4. "USBHS0SWEN,USBHS0 clock source selection enable" "0,1"
|
|
bitfld.long 0x8 3. "PLLUSBHS0PRESEL,PLLUSBHS0 clock source preselection" "0,1"
|
|
bitfld.long 0x8 1. "USBHS0SEL,USBHS0 clock source selection" "0,1"
|
|
line.long 0xC "PLLUSBCFG,PLLUSB configuration register"
|
|
hexmask.long.byte 0xC 24.--30. 1. "PLLUSBHS1MF,The PLLUSBHS1 clock multiplication factor"
|
|
bitfld.long 0xC 20.--22. "USBHS1DV,USBHS1 clock divider factor" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 16.--19. 1. "PLLUSBHS1PREDV,PLLUSBHS1PREDV clock divide factor"
|
|
hexmask.long.byte 0xC 8.--14. 1. "PLLUSBHS0MF,The PLLUSBHS0 clock multiplication factor"
|
|
bitfld.long 0xC 4.--6. "USBHS0DV,USBHS0 clock divider factor" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 0.--3. 1. "PLLUSBHS0PREDV,PLLUSBHS0PREDV clock divide factor"
|
|
group.long 0xE0++0xB
|
|
line.long 0x0 "ADDAPB2RST,APB2 additional reset register"
|
|
bitfld.long 0x0 2. "CAN2RST,CAN2 reset" "0,1"
|
|
bitfld.long 0x0 1. "CAN1RST,CAN1 reset" "0,1"
|
|
bitfld.long 0x0 0. "CAN0RST,CAN0 reset" "0,1"
|
|
line.long 0x4 "ADDAPB2EN,APB2 additional enable register"
|
|
bitfld.long 0x4 2. "CAN2EN,CAN2 clock enable" "0,1"
|
|
bitfld.long 0x4 1. "CAN1EN,CAN1 clock enable" "0,1"
|
|
bitfld.long 0x4 0. "CAN0EN,CAN0 clock enable" "0,1"
|
|
line.long 0x8 "ADDAPB2SPEN,APB2 additional sleep enable register"
|
|
bitfld.long 0x8 2. "CAN2SPEN,CAN2 clock enable in sleep mode" "0,1"
|
|
bitfld.long 0x8 1. "CAN1SPEN,CAN1 clock enable in sleep mode" "0,1"
|
|
bitfld.long 0x8 0. "CAN0SPEN,CAN0 clock enable in sleep mode" "0,1"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "CFG5,Clock configuration register 5"
|
|
bitfld.long 0x0 20.--22. "SPI5SEL,SPI5 / I2S5 clock source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "SPI4SEL,SPI4 clock source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. "SPI3SEL,SPI3 clock source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8.--10. "SPI2SEL,SPI2 / I2S2 clock source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "SPI1SEL,SPI1 / I2S1 clock source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "SPI0SEL,SPI0 / I2S0 clock source selection" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
tree "RSPDIF (Receiver of Sony/Philips Digtial Interface)"
|
|
base ad:0x40004000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 21. "BKSCKEN,Backup symbol clock enable" "0,1"
|
|
bitfld.long 0x0 20. "SCKEN,Symbol clock enable" "0,1"
|
|
bitfld.long 0x0 16.--18. "RXCHSEL,RSPDIF input channel selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 14. "WFRXA,Wait for the four valid transition signal of the selected RSPDIF channel" "0,1"
|
|
bitfld.long 0x0 12.--13. "MAXRT,Maximum number of retries allowed during the RSPDIF synchronization phase" "0: Do not allow retry,?,?,?"
|
|
bitfld.long 0x0 11. "CFCHSEL,The control flow acquires channel state source selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "DMACBEN,Control buffer DMA enable for control flow" "0,1"
|
|
bitfld.long 0x0 9. "PTNCPEN,Preamble type no copy enable bit" "0,1"
|
|
bitfld.long 0x0 8. "CUNCPEN,Channel status and user no copy enable bit" "0,1"
|
|
bitfld.long 0x0 7. "VNCPEN,Validity no copy enable bit" "0,1"
|
|
bitfld.long 0x0 6. "PNCPEN,Parity error no copy enable bit" "0,1"
|
|
bitfld.long 0x0 4.--5. "RXDF,RX data format selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 3. "RXSTEOMEN,RX stereo mode enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAREN,Receiver DMA enable for data flow" "0,1"
|
|
bitfld.long 0x0 0.--1. "RXCFG,RSPDIF configuration" "0,1,2,3"
|
|
line.long 0x4 "INTEN,Interrupt enable register"
|
|
bitfld.long 0x4 6. "RXDCERRIE,RSPDIF data decoding error interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "SYNDOIE,Synchronization done interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "SYNDBIE,Synchronization block detected interrupt enable" "0,1"
|
|
bitfld.long 0x4 3. "RXORERRIE,RX overrun error interrupt enable" "0,1"
|
|
bitfld.long 0x4 2. "PERRIE,Parity error interrupt enable" "0,1"
|
|
bitfld.long 0x4 1. "CBNEIE,RX control buffer is no empty interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RBNEIE,RX buffer is no empty interrupt enable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "STAT,Status register"
|
|
hexmask.long.word 0x0 16.--30. 1. "CKCNT5,The number of consecutive time clock cycles of 5 symbols counted using ck"
|
|
bitfld.long 0x0 8. "TMOUTERR,Time out error" "0,1"
|
|
bitfld.long 0x0 7. "SYNERR,Synchronization error" "0,1"
|
|
bitfld.long 0x0 6. "FRERR,Frame error" "0,1"
|
|
bitfld.long 0x0 5. "SYNDO,Synchronization done" "0,1"
|
|
bitfld.long 0x0 4. "SYNDB,Synchronization block detected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXORERR,RX overrun error" "0,1"
|
|
bitfld.long 0x0 2. "PERR,Parity error" "0,1"
|
|
bitfld.long 0x0 1. "CBNE,The control buffer register is not empty" "0,1"
|
|
bitfld.long 0x0 0. "RBNE,RX data register not empty" "0,1"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "STATC,Status flag clear register"
|
|
bitfld.long 0x0 5. "SYNDOC,clears the synchronization done flag" "0,1"
|
|
bitfld.long 0x0 4. "SYNDBC,clears the synchronization block detected flag" "0,1"
|
|
bitfld.long 0x0 3. "RXORERRC,clears the RX overrun error flag" "0,1"
|
|
bitfld.long 0x0 2. "PERRC,clears the parity error flag" "0,1"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "DATA_F0,RX data register format 0"
|
|
bitfld.long 0x0 28.--29. "PREF,Preamble type" "0,1,2,3"
|
|
bitfld.long 0x0 27. "C,Channel status bit" "0,1"
|
|
bitfld.long 0x0 26. "U,User bit" "0,1"
|
|
bitfld.long 0x0 25. "V,Validity bit" "0,1"
|
|
bitfld.long 0x0 24. "P,Parity error bit" "0,1"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Data value"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "DATA_F1,RX data register format 1"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "DATA,Data value"
|
|
bitfld.long 0x0 4.--5. "PREF,Preamble type" "0,1,2,3"
|
|
bitfld.long 0x0 3. "C,Channel status bit" "0,1"
|
|
bitfld.long 0x0 2. "U,User bit" "0,1"
|
|
bitfld.long 0x0 1. "V,Validity bit" "0,1"
|
|
bitfld.long 0x0 0. "P,Parity error bit" "0,1"
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "DATA_F2,RX data register format 2"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA2,Data value"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA1,Data value"
|
|
line.long 0x4 "CHSTAT,RX Channel status register"
|
|
bitfld.long 0x4 24. "SOB,Start of block" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CHS,Channel A status information"
|
|
hexmask.long.word 0x4 0.--15. 1. "USER,User data information"
|
|
line.long 0x8 "DTH,RX data threshold register"
|
|
hexmask.long.word 0x8 16.--28. 1. "THLO,Low threshold"
|
|
hexmask.long.word 0x8 0.--12. 1. "THHI,High threshold"
|
|
tree.end
|
|
endif
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x58004000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "TIME,time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM mark" "0,1"
|
|
bitfld.long 0x0 20.--21. "HRT,Hour tens in BCD code" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HRU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD code" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD code"
|
|
bitfld.long 0x0 4.--6. "SCT,Second tens in BCD code" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SCU,Second units in BCD code"
|
|
line.long 0x4 "DATE,date register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "YRT,Year tens in BCD code"
|
|
hexmask.long.byte 0x4 16.--19. 1. "YRU,Year units in BCD code"
|
|
bitfld.long 0x4 13.--15. "DOW,Days of the week" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MONT,Month tens in BCD code" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "MONU,Month units in BCD code"
|
|
bitfld.long 0x4 4.--5. "DAYT,Date tens in BCD code" "0,1,2,3"
|
|
hexmask.long.byte 0x4 0.--3. 1. "DAYU,Date units in BCD code"
|
|
line.long 0x8 "CTL,control register"
|
|
bitfld.long 0x8 24. "ITSEN,Internal timestamp event enable" "0,1"
|
|
bitfld.long 0x8 23. "COEN,Calibration output enable" "0,1"
|
|
bitfld.long 0x8 21.--22. "OS,Output selection" "0,1,2,3"
|
|
bitfld.long 0x8 20. "OPOL,Output polarity" "0,1"
|
|
bitfld.long 0x8 19. "COS,Calibration output" "0,1"
|
|
bitfld.long 0x8 18. "DSM,Backup" "0,1"
|
|
bitfld.long 0x8 17. "S1H,Subtract 1 hour (winter time" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "A1H,Add 1 hour (summer time" "0,1"
|
|
bitfld.long 0x8 15. "TSIE,Time-stamp interrupt" "0,1"
|
|
bitfld.long 0x8 14. "WTIE,Auto-wakeup timer interrupt enable" "0,1"
|
|
bitfld.long 0x8 13. "ALRM1IE,Alarm1 interrupt enable" "0,1"
|
|
bitfld.long 0x8 12. "ALRM0IE,Alarm0 interrupt enable" "0,1"
|
|
bitfld.long 0x8 11. "TSEN,timestamp enable" "0,1"
|
|
bitfld.long 0x8 10. "WTEN,Auto-wakeup timer function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "ALRM1EN,Alarm1 enable" "0,1"
|
|
bitfld.long 0x8 8. "ALRM0EN,Alarm0 enable" "0,1"
|
|
bitfld.long 0x8 6. "CS,Hour format" "0,1"
|
|
bitfld.long 0x8 5. "BPSHAD,Bypass the shadow" "0,1"
|
|
bitfld.long 0x8 4. "REFEN,RTC_REFIN reference clock detection" "0,1"
|
|
bitfld.long 0x8 3. "TSEG,Time-stamp event active" "0,1"
|
|
bitfld.long 0x8 0.--2. "WTCS,Auto-wakeup timer clock selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "STAT,initialization and status"
|
|
rbitfld.long 0xC 17. "ITSF,Internal timestamp flag" "0,1"
|
|
rbitfld.long 0xC 16. "SCPF,Smooth calibration pending flag" "0,1"
|
|
bitfld.long 0xC 15. "TP1F,RTC_TAMP1 detection flag" "0,1"
|
|
bitfld.long 0xC 13. "TP0F,RTC_TAMP0 detection flag" "0,1"
|
|
bitfld.long 0xC 12. "TSOVRF,Time-stamp overflow flag" "0,1"
|
|
bitfld.long 0xC 11. "TSF,Time-stamp flag" "0,1"
|
|
bitfld.long 0xC 10. "WTF,Wakeup timer flag" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "ALRM1F,Alarm1 flag" "0,1"
|
|
bitfld.long 0xC 8. "ALRM0F,Alarm0 flag" "0,1"
|
|
bitfld.long 0xC 7. "INITM,Initialization mode" "0,1"
|
|
rbitfld.long 0xC 6. "INITF,Initialization flag" "0,1"
|
|
bitfld.long 0xC 5. "RSYNF,Registers synchronization" "0,1"
|
|
rbitfld.long 0xC 4. "YCM,Initialization status flag" "0,1"
|
|
rbitfld.long 0xC 3. "SOPF,Shift operation pending" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 2. "WTWF,Wakeup timer write enable flag" "0,1"
|
|
rbitfld.long 0xC 1. "ALRM1WF,Alarm1 write flag" "0,1"
|
|
rbitfld.long 0xC 0. "ALRM0WF,Alarm0 write flag" "0,1"
|
|
line.long 0x10 "PSC,prescaler register"
|
|
hexmask.long.byte 0x10 16.--22. 1. "FACTOR_A,Asynchronous prescaler"
|
|
hexmask.long.word 0x10 0.--14. 1. "FACTOR_S,Synchronous prescaler"
|
|
line.long 0x14 "WUT,Wakeup timer register"
|
|
hexmask.long.word 0x14 0.--15. 1. "WTRV,Auto-wakeup timer reloads value"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "ALRM0TD,Alarm 0 time and date register"
|
|
bitfld.long 0x0 31. "MSKD,Alarm date mask" "0,1"
|
|
bitfld.long 0x0 30. "DOWS,Week day selection" "0,1"
|
|
bitfld.long 0x0 28.--29. "DAYT,Date tens in BCD format." "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DAYU,Date units or day in BCD"
|
|
bitfld.long 0x0 23. "MSKH,Alarm hours mask" "0,1"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x0 20.--21. "HRT,Hour tens in BCD format." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HRU,Hour units in BCD format."
|
|
bitfld.long 0x0 15. "MSKM,Alarm minutes mask" "0,1"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD"
|
|
bitfld.long 0x0 7. "MSKS,Alarm seconds mask" "0,1"
|
|
bitfld.long 0x0 4.--6. "SCT,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SCU,Second units in BCD"
|
|
line.long 0x4 "ALRM1TD,Alarm 1 time and date register"
|
|
bitfld.long 0x4 31. "MSKD,Alarm date mask" "0,1"
|
|
bitfld.long 0x4 30. "DOWS,Week day selection" "0,1"
|
|
bitfld.long 0x4 28.--29. "DAYT,Date tens in BCD format." "0,1,2,3"
|
|
hexmask.long.byte 0x4 24.--27. 1. "DAYU,Date units or day in BCD"
|
|
bitfld.long 0x4 23. "MSKH,Alarm hours mask" "0,1"
|
|
bitfld.long 0x4 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x4 20.--21. "HRT,Hour tens in BCD format." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "HRU,Hour units in BCD format."
|
|
bitfld.long 0x4 15. "MSKM,Alarm minutes mask" "0,1"
|
|
bitfld.long 0x4 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 8.--11. 1. "MNU,Minute units in BCD"
|
|
bitfld.long 0x4 7. "MSKS,Alarm seconds mask" "0,1"
|
|
bitfld.long 0x4 4.--6. "SCT,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 0.--3. 1. "SCU,Second units in BCD"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "WPK,write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WPK,Write protection key"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "SS,sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SSC,Sub second value"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "SHIFTCTL,shift control register"
|
|
bitfld.long 0x0 31. "A1S,One second add" "0,1"
|
|
hexmask.long.word 0x0 0.--14. 1. "SFS,Subtract a fraction of a"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "TTS,timestamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM mark" "0,1"
|
|
bitfld.long 0x0 20.--21. "HRT,Hour tens in BCD code" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HRU,Hour units in BCD code"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD code" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD code"
|
|
bitfld.long 0x0 4.--6. "SCT,Second tens in BCD code" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SCU,Second units in BCD code"
|
|
line.long 0x4 "DTS,Date of time stamp register"
|
|
bitfld.long 0x4 13.--15. "DOW,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MONT,Month tens in BCD code" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "MONU,Month units in BCD code"
|
|
bitfld.long 0x4 4.--5. "DAYT,Date tens in BCD code" "0,1,2,3"
|
|
hexmask.long.byte 0x4 0.--3. 1. "DAYU,Date units in BCD code"
|
|
line.long 0x8 "SSTS,time-stamp sub second register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SSC,Sub second value"
|
|
group.long 0x3C++0x93
|
|
line.long 0x0 "HRFC,High resolution frequency compensation register"
|
|
bitfld.long 0x0 15. "FREQI,Increase RTC frequency by 488.5PPM" "0,1"
|
|
bitfld.long 0x0 14. "CWND8,Frequency compensation window 8 second selected" "0,1"
|
|
bitfld.long 0x0 13. "CWND16,Frequency compensation window 16 second selected" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "CMSK,Calibration mask number"
|
|
line.long 0x4 "TAMP,tamper register"
|
|
bitfld.long 0x4 15. "DISPU,RTC_TAMPx pull-up disable" "0,1"
|
|
bitfld.long 0x4 13.--14. "PRCH,Pre-charge duration time of RTC_TAMPx" "0,1,2,3"
|
|
bitfld.long 0x4 11.--12. "FLT,RTC_TAMPx filter count setting" "0,1,2,3"
|
|
bitfld.long 0x4 8.--10. "FREQ,Sampling frequency of tamper event detection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. "TPTS,Make tamper function used for timestamp function" "0,1"
|
|
bitfld.long 0x4 4. "TP1EG,Tamper 1 event trigger edge" "0,1"
|
|
bitfld.long 0x4 3. "TP1EN,Tamper 1 detection enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TPIE,Tamper detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 1. "TP0EG,Tamper 0 event trigger edge" "0,1"
|
|
bitfld.long 0x4 0. "TP0EN,Tamper 0 detection enable" "0,1"
|
|
line.long 0x8 "ALRM0SS,alarm 0 sub second register"
|
|
hexmask.long.byte 0x8 24.--27. 1. "MSKSSC,Mask control bit of SSC"
|
|
hexmask.long.word 0x8 0.--14. 1. "SSC,Alarm sub second value"
|
|
line.long 0xC "ALRM1SS,alarm 1 sub second register"
|
|
hexmask.long.byte 0xC 24.--27. 1. "MSKSSC,Mask control bit of SSC"
|
|
hexmask.long.word 0xC 0.--14. 1. "SSC,Alarm sub second value"
|
|
line.long 0x10 "CFG,Configuration register"
|
|
bitfld.long 0x10 1. "OUT2EN,RTC_OUT pin select" "0,1"
|
|
bitfld.long 0x10 0. "ALRMOUTTYPE,RTC_ALARM Output Type" "0,1"
|
|
line.long 0x14 "BKP0,backup register"
|
|
hexmask.long 0x14 0.--31. 1. "DATA,BKP data"
|
|
line.long 0x18 "BKP1,backup register"
|
|
hexmask.long 0x18 0.--31. 1. "DATA,BKP data"
|
|
line.long 0x1C "BKP2,backup register"
|
|
hexmask.long 0x1C 0.--31. 1. "DATA,BKP data"
|
|
line.long 0x20 "BKP3,backup register"
|
|
hexmask.long 0x20 0.--31. 1. "DATA,BKP data"
|
|
line.long 0x24 "BKP4,backup register"
|
|
hexmask.long 0x24 0.--31. 1. "DATA,BKP data"
|
|
line.long 0x28 "BKP5,backup register"
|
|
hexmask.long 0x28 0.--31. 1. "DATA,BKP data"
|
|
line.long 0x2C "BKP6,backup register"
|
|
hexmask.long 0x2C 0.--31. 1. "DATA,BKP data"
|
|
line.long 0x30 "BKP7,backup register"
|
|
hexmask.long 0x30 0.--31. 1. "DATA,BKP data"
|
|
line.long 0x34 "BKP8,backup register"
|
|
hexmask.long 0x34 0.--31. 1. "DATA,BKP data"
|
|
line.long 0x38 "BKP9,backup register"
|
|
hexmask.long 0x38 0.--31. 1. "DATA,BKP data"
|
|
line.long 0x3C "BKP10,Backup registe 10"
|
|
hexmask.long 0x3C 0.--31. 1. "DATA,Data"
|
|
line.long 0x40 "BKP11,Backup registe 11"
|
|
hexmask.long 0x40 0.--31. 1. "DATA,Data"
|
|
line.long 0x44 "BKP12,Backup registe 12"
|
|
hexmask.long 0x44 0.--31. 1. "DATA,Data"
|
|
line.long 0x48 "BKP13,Backup registe 13"
|
|
hexmask.long 0x48 0.--31. 1. "DATA,Data"
|
|
line.long 0x4C "BKP14,Backup registe 14"
|
|
hexmask.long 0x4C 0.--31. 1. "DATA,Data"
|
|
line.long 0x50 "BKP15,Backup registe 15"
|
|
hexmask.long 0x50 0.--31. 1. "DATA,Data"
|
|
line.long 0x54 "BKP16,Backup registe 16"
|
|
hexmask.long 0x54 0.--31. 1. "DATA,Data"
|
|
line.long 0x58 "BKP17,Backup registe 17"
|
|
hexmask.long 0x58 0.--31. 1. "DATA,Data"
|
|
line.long 0x5C "BKP18,Backup registe 18"
|
|
hexmask.long 0x5C 0.--31. 1. "DATA,Data"
|
|
line.long 0x60 "BKP19,Backup registe 19"
|
|
hexmask.long 0x60 0.--31. 1. "DATA,Data"
|
|
line.long 0x64 "BKP20,Backup registe 20"
|
|
hexmask.long 0x64 0.--31. 1. "DATA,Data"
|
|
line.long 0x68 "BKP21,Backup registe 21"
|
|
hexmask.long 0x68 0.--31. 1. "DATA,Data"
|
|
line.long 0x6C "BKP22,Backup registe 22"
|
|
hexmask.long 0x6C 0.--31. 1. "DATA,Data"
|
|
line.long 0x70 "BKP23,Backup registe 23"
|
|
hexmask.long 0x70 0.--31. 1. "DATA,Data"
|
|
line.long 0x74 "BKP24,Backup registe 24"
|
|
hexmask.long 0x74 0.--31. 1. "DATA,Data"
|
|
line.long 0x78 "BKP25,Backup registe 25"
|
|
hexmask.long 0x78 0.--31. 1. "DATA,Data"
|
|
line.long 0x7C "BKP26,Backup registe 26"
|
|
hexmask.long 0x7C 0.--31. 1. "DATA,Data"
|
|
line.long 0x80 "BKP27,Backup registe 27"
|
|
hexmask.long 0x80 0.--31. 1. "DATA,Data"
|
|
line.long 0x84 "BKP28,Backup registe 28"
|
|
hexmask.long 0x84 0.--31. 1. "DATA,Data"
|
|
line.long 0x88 "BKP29,Backup registe 29"
|
|
hexmask.long 0x88 0.--31. 1. "DATA,Data"
|
|
line.long 0x8C "BKP30,Backup registe 30"
|
|
hexmask.long 0x8C 0.--31. 1. "DATA,Data"
|
|
line.long 0x90 "BKP31,Backup registe 31"
|
|
hexmask.long 0x90 0.--31. 1. "DATA,Data"
|
|
tree.end
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
tree "RTDEC (Real-time Decryption)"
|
|
base ad:0x0
|
|
tree "RTDEC0"
|
|
base ad:0x5200B800
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "ARE0_CFG,Area 0 configuration regist"
|
|
hexmask.long.word 0x0 16.--31. 1. "ARE_FMVER,Area firmware version bits"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ARE_K_CRC,8-bit CRC of area key bits"
|
|
bitfld.long 0x0 4.--5. "MODE,RTDEC mode bits" "0,1,2,3"
|
|
rbitfld.long 0x0 2. "ARE_K_LK,Area key lock bit" "0,1"
|
|
rbitfld.long 0x0 1. "ARE_CFG_LK,Area configure lock bit" "0,1"
|
|
bitfld.long 0x0 0. "ARE_EN,Area real-time decryption enable bit" "0,1"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "ARE1_CFG,Area 1 configuration regist"
|
|
hexmask.long.word 0x0 16.--31. 1. "ARE_FMVER,Area firmware version bits"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ARE_K_CRC,8-bit CRC of area key bits"
|
|
bitfld.long 0x0 4.--5. "MODE,RTDEC mode bits" "0,1,2,3"
|
|
rbitfld.long 0x0 2. "ARE_K_LK,Area key lock bit" "0,1"
|
|
rbitfld.long 0x0 1. "ARE_CFG_LK,Area configure lock bit" "0,1"
|
|
bitfld.long 0x0 0. "ARE_EN,Area real-time decryption enable bit" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "ARE2_CFG,Area 2 configuration regist"
|
|
hexmask.long.word 0x0 16.--31. 1. "ARE_FMVER,Area firmware version bits"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ARE_K_CRC,8-bit CRC of area key bits"
|
|
bitfld.long 0x0 4.--5. "MODE,RTDEC mode bits" "0,1,2,3"
|
|
rbitfld.long 0x0 2. "ARE_K_LK,Area key lock bit" "0,1"
|
|
rbitfld.long 0x0 1. "ARE_CFG_LK,Area configure lock bit" "0,1"
|
|
bitfld.long 0x0 0. "ARE_EN,Area real-time decryption enable bit" "0,1"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "ARE3_CFG,Area 3 configuration regist"
|
|
hexmask.long.word 0x0 16.--31. 1. "ARE_FMVER,Area firmware version bits"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ARE_K_CRC,8-bit CRC of area key bits"
|
|
bitfld.long 0x0 4.--5. "MODE,RTDEC mode bits" "0,1,2,3"
|
|
rbitfld.long 0x0 2. "ARE_K_LK,Area key lock bit" "0,1"
|
|
rbitfld.long 0x0 1. "ARE_CFG_LK,Area configure lock bit" "0,1"
|
|
bitfld.long 0x0 0. "ARE_EN,Area real-time decryption enable bit" "0,1"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "ARE0_SADDR,Area 0 start address regist"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_SADDR,Area x start address bits"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "ARE1_SADDR,Area 1 start address regist"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_SADDR,Area x start address bits"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "ARE2_SADDR,Area 2 start address regist"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_SADDR,Area x start address bits"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "ARE3_SADDR,Area 3 start address regist"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_SADDR,Area x start address bits"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "ARE0_EADDR,Area 0 end address regist"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_EADDR,Area x end address bits"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "ARE1_EADDR,Area 1 end address regist"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_EADDR,Area x end address bits"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "ARE2_EADDR,Area 2 end address regist"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_EADDR,Area x end address bits"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "ARE3_EADDR,Area 3 end address regist"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_EADDR,Area x end address bits"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "ARE0_NONCE0,Area 0 nonce 0 register 0"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_NONCE0,Area 0 nonce address bits"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "ARE1_NONCE0,Area 1 nonce register 0"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_NONCE0,Area 1 nonce 0 address bits"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "ARE2_NONCE0,Area 2 nonce register 0"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_NONCE0,Area 2 nonce 0 address bits"
|
|
group.long 0xBC++0x3
|
|
line.long 0x0 "ARE3_NONCE0,Area 3 nonce register 0"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_NONCE0,Area 3 nonce 0 address bits"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "ARE0_NONCE1,Area 0 nonce register 1"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_NONCE1,Area 0 nonce 1 address bits"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "ARE1_NONCE1,Area 1 nonce register 1"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_NONCE1,Area 1 nonce 1 address bits ARE_RANDNUM[63:32]"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "ARE2_NONCE1,Area 2 nonce register 1"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_NONCE1,Area 2 nonce 1 address bits ARE_RANDNUM[63:32]"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "ARE3_NONCE1,Area 3 nonce register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_NONCE1,Area 3 nonce 1 address bits ARE_RANDNUM[63:32]"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x0 "ARE0_KEY0,Area 0 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY0,Area x key bits ARE_KEY[31:0]"
|
|
wgroup.long 0x64++0x3
|
|
line.long 0x0 "ARE1_KEY0,Area 1 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY0,Area x key bits ARE_KEY[31:0]"
|
|
wgroup.long 0x94++0x3
|
|
line.long 0x0 "ARE2_KEY0,Area 2 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY0,Area x key bits ARE_KEY[31:0]"
|
|
wgroup.long 0xC4++0x3
|
|
line.long 0x0 "ARE3_KEY0,Area 3 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY0,Area x key bits ARE_KEY[31:0]"
|
|
wgroup.long 0x38++0x3
|
|
line.long 0x0 "ARE0_KEY1,Area 0 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY1,Area x key bits ARE_KEY[63:32]"
|
|
wgroup.long 0x68++0x3
|
|
line.long 0x0 "ARE1_KEY1,Area 1 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY1,Area x key bits ARE_KEY[63:32]"
|
|
wgroup.long 0x98++0x3
|
|
line.long 0x0 "ARE2_KEY1,Area 2 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY1,Area x key bits ARE_KEY[63:32]"
|
|
wgroup.long 0xC8++0x3
|
|
line.long 0x0 "ARE3_KEY1,Area 3 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY1,Area x key bits ARE_KEY[63:32]"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "ARE0_KEY2,Area 0 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY2,Area x key bits ARE_KEY[95:64]"
|
|
wgroup.long 0x6C++0x3
|
|
line.long 0x0 "ARE1_KEY2,Area 1 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY2,Area x key bits ARE_KEY[95:64]"
|
|
wgroup.long 0x9C++0x3
|
|
line.long 0x0 "ARE2_KEY2,Area 2 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY2,Area x key bits ARE_KEY[95:64]"
|
|
wgroup.long 0xCC++0x3
|
|
line.long 0x0 "ARE3_KEY2,Area 3 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY2,Area x key bits ARE_KEY[95:64]"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ARE0_KEY3,Area 0 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY3,Area x key bits ARE_KEY[127:96]"
|
|
rgroup.long 0x70++0x3
|
|
line.long 0x0 "ARE1_KEY3,Area 1 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY3,Area x key bits ARE_KEY[127:96]"
|
|
rgroup.long 0xA0++0x3
|
|
line.long 0x0 "ARE2_KEY3,Area 2 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY3,Area x key bits ARE_KEY[127:96]"
|
|
rgroup.long 0xD0++0x3
|
|
line.long 0x0 "ARE3_KEY3,Area 3 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY3,Area x key bits ARE_KEY[127:96]"
|
|
rgroup.long 0x300++0x3
|
|
line.long 0x0 "INTF,Interrupt flag register"
|
|
bitfld.long 0x0 2. "KEF,Key error interrupt flag" "0,1"
|
|
bitfld.long 0x0 1. "ECONEF,Execute-only or execute-never error interrupt flag" "0,1"
|
|
bitfld.long 0x0 0. "SECEF,Security error interrupt flag" "0,1"
|
|
wgroup.long 0x304++0x3
|
|
line.long 0x0 "INTC,Interrupt flag clear register"
|
|
bitfld.long 0x0 2. "KEC,Key error flag clear" "0,1"
|
|
bitfld.long 0x0 1. "ECONEC,Execute-only or execute-never error flag clear" "0,1"
|
|
bitfld.long 0x0 0. "SECEC,Security error interrupt flag" "0,1"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "INTEN,Interrupt enable register"
|
|
bitfld.long 0x0 2. "KEIE,Enable bit for key error interrupt" "0,1"
|
|
bitfld.long 0x0 1. "ECONEIE,Enable bit for execute-only or execute-never error interrupt" "0,1"
|
|
bitfld.long 0x0 0. "SECEIE,Enable bit for security error interrupt" "0,1"
|
|
tree.end
|
|
tree "RTDEC1"
|
|
base ad:0x5200BC00
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "ARE0_CFG,Area 0 configuration regist"
|
|
hexmask.long.word 0x0 16.--31. 1. "ARE_FMVER,Area firmware version bits"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ARE_K_CRC,8-bit CRC of area key bits"
|
|
bitfld.long 0x0 4.--5. "MODE,RTDEC mode bits" "0,1,2,3"
|
|
rbitfld.long 0x0 2. "ARE_K_LK,Area key lock bit" "0,1"
|
|
rbitfld.long 0x0 1. "ARE_CFG_LK,Area configure lock bit" "0,1"
|
|
bitfld.long 0x0 0. "ARE_EN,Area real-time decryption enable bit" "0,1"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "ARE1_CFG,Area 1 configuration regist"
|
|
hexmask.long.word 0x0 16.--31. 1. "ARE_FMVER,Area firmware version bits"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ARE_K_CRC,8-bit CRC of area key bits"
|
|
bitfld.long 0x0 4.--5. "MODE,RTDEC mode bits" "0,1,2,3"
|
|
rbitfld.long 0x0 2. "ARE_K_LK,Area key lock bit" "0,1"
|
|
rbitfld.long 0x0 1. "ARE_CFG_LK,Area configure lock bit" "0,1"
|
|
bitfld.long 0x0 0. "ARE_EN,Area real-time decryption enable bit" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "ARE2_CFG,Area 2 configuration regist"
|
|
hexmask.long.word 0x0 16.--31. 1. "ARE_FMVER,Area firmware version bits"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ARE_K_CRC,8-bit CRC of area key bits"
|
|
bitfld.long 0x0 4.--5. "MODE,RTDEC mode bits" "0,1,2,3"
|
|
rbitfld.long 0x0 2. "ARE_K_LK,Area key lock bit" "0,1"
|
|
rbitfld.long 0x0 1. "ARE_CFG_LK,Area configure lock bit" "0,1"
|
|
bitfld.long 0x0 0. "ARE_EN,Area real-time decryption enable bit" "0,1"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "ARE3_CFG,Area 3 configuration regist"
|
|
hexmask.long.word 0x0 16.--31. 1. "ARE_FMVER,Area firmware version bits"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ARE_K_CRC,8-bit CRC of area key bits"
|
|
bitfld.long 0x0 4.--5. "MODE,RTDEC mode bits" "0,1,2,3"
|
|
rbitfld.long 0x0 2. "ARE_K_LK,Area key lock bit" "0,1"
|
|
rbitfld.long 0x0 1. "ARE_CFG_LK,Area configure lock bit" "0,1"
|
|
bitfld.long 0x0 0. "ARE_EN,Area real-time decryption enable bit" "0,1"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "ARE0_SADDR,Area 0 start address regist"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_SADDR,Area x start address bits"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "ARE1_SADDR,Area 1 start address regist"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_SADDR,Area x start address bits"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "ARE2_SADDR,Area 2 start address regist"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_SADDR,Area x start address bits"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "ARE3_SADDR,Area 3 start address regist"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_SADDR,Area x start address bits"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "ARE0_EADDR,Area 0 end address regist"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_EADDR,Area x end address bits"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "ARE1_EADDR,Area 1 end address regist"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_EADDR,Area x end address bits"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "ARE2_EADDR,Area 2 end address regist"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_EADDR,Area x end address bits"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "ARE3_EADDR,Area 3 end address regist"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_EADDR,Area x end address bits"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "ARE0_NONCE0,Area 0 nonce 0 register 0"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_NONCE0,Area 0 nonce address bits"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "ARE1_NONCE0,Area 1 nonce register 0"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_NONCE0,Area 1 nonce 0 address bits"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "ARE2_NONCE0,Area 2 nonce register 0"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_NONCE0,Area 2 nonce 0 address bits"
|
|
group.long 0xBC++0x3
|
|
line.long 0x0 "ARE3_NONCE0,Area 3 nonce register 0"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_NONCE0,Area 3 nonce 0 address bits"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "ARE0_NONCE1,Area 0 nonce register 1"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_NONCE1,Area 0 nonce 1 address bits"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "ARE1_NONCE1,Area 1 nonce register 1"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_NONCE1,Area 1 nonce 1 address bits ARE_RANDNUM[63:32]"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "ARE2_NONCE1,Area 2 nonce register 1"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_NONCE1,Area 2 nonce 1 address bits ARE_RANDNUM[63:32]"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "ARE3_NONCE1,Area 3 nonce register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_NONCE1,Area 3 nonce 1 address bits ARE_RANDNUM[63:32]"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x0 "ARE0_KEY0,Area 0 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY0,Area x key bits ARE_KEY[31:0]"
|
|
wgroup.long 0x64++0x3
|
|
line.long 0x0 "ARE1_KEY0,Area 1 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY0,Area x key bits ARE_KEY[31:0]"
|
|
wgroup.long 0x94++0x3
|
|
line.long 0x0 "ARE2_KEY0,Area 2 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY0,Area x key bits ARE_KEY[31:0]"
|
|
wgroup.long 0xC4++0x3
|
|
line.long 0x0 "ARE3_KEY0,Area 3 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY0,Area x key bits ARE_KEY[31:0]"
|
|
wgroup.long 0x38++0x3
|
|
line.long 0x0 "ARE0_KEY1,Area 0 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY1,Area x key bits ARE_KEY[63:32]"
|
|
wgroup.long 0x68++0x3
|
|
line.long 0x0 "ARE1_KEY1,Area 1 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY1,Area x key bits ARE_KEY[63:32]"
|
|
wgroup.long 0x98++0x3
|
|
line.long 0x0 "ARE2_KEY1,Area 2 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY1,Area x key bits ARE_KEY[63:32]"
|
|
wgroup.long 0xC8++0x3
|
|
line.long 0x0 "ARE3_KEY1,Area 3 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY1,Area x key bits ARE_KEY[63:32]"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "ARE0_KEY2,Area 0 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY2,Area x key bits ARE_KEY[95:64]"
|
|
wgroup.long 0x6C++0x3
|
|
line.long 0x0 "ARE1_KEY2,Area 1 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY2,Area x key bits ARE_KEY[95:64]"
|
|
wgroup.long 0x9C++0x3
|
|
line.long 0x0 "ARE2_KEY2,Area 2 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY2,Area x key bits ARE_KEY[95:64]"
|
|
wgroup.long 0xCC++0x3
|
|
line.long 0x0 "ARE3_KEY2,Area 3 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY2,Area x key bits ARE_KEY[95:64]"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ARE0_KEY3,Area 0 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY3,Area x key bits ARE_KEY[127:96]"
|
|
rgroup.long 0x70++0x3
|
|
line.long 0x0 "ARE1_KEY3,Area 1 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY3,Area x key bits ARE_KEY[127:96]"
|
|
rgroup.long 0xA0++0x3
|
|
line.long 0x0 "ARE2_KEY3,Area 2 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY3,Area x key bits ARE_KEY[127:96]"
|
|
rgroup.long 0xD0++0x3
|
|
line.long 0x0 "ARE3_KEY3,Area 3 key register"
|
|
hexmask.long 0x0 0.--31. 1. "ARE_KEY3,Area x key bits ARE_KEY[127:96]"
|
|
rgroup.long 0x300++0x3
|
|
line.long 0x0 "INTF,Interrupt flag register"
|
|
bitfld.long 0x0 2. "KEF,Key error interrupt flag" "0,1"
|
|
bitfld.long 0x0 1. "ECONEF,Execute-only or execute-never error interrupt flag" "0,1"
|
|
bitfld.long 0x0 0. "SECEF,Security error interrupt flag" "0,1"
|
|
wgroup.long 0x304++0x3
|
|
line.long 0x0 "INTC,Interrupt flag clear register"
|
|
bitfld.long 0x0 2. "KEC,Key error flag clear" "0,1"
|
|
bitfld.long 0x0 1. "ECONEC,Execute-only or execute-never error flag clear" "0,1"
|
|
bitfld.long 0x0 0. "SECEC,Security error interrupt flag" "0,1"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "INTEN,Interrupt enable register"
|
|
bitfld.long 0x0 2. "KEIE,Enable bit for key error interrupt" "0,1"
|
|
bitfld.long 0x0 1. "ECONEIE,Enable bit for execute-only or execute-never error interrupt" "0,1"
|
|
bitfld.long 0x0 0. "SECEIE,Enable bit for security error interrupt" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "SAI (Serial Audio Interface)"
|
|
base ad:0x0
|
|
tree "SAI0"
|
|
base ad:0x40015800
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "SYNCFG,Synchronize configuration register"
|
|
bitfld.long 0x0 4.--5. "SYNO,Synchronization outputs" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SYNI,Synchronization inputs" "0,1,2,3"
|
|
line.long 0x4 "B0CFG0,Block 0 configuration registe"
|
|
bitfld.long 0x4 27. "MCLKEN,The master clock enable" "0,1"
|
|
bitfld.long 0x4 26. "MOSPR,The master clock oversampling rate" "0,1"
|
|
hexmask.long.byte 0x4 20.--25. 1. "MDIV,Master clock divider ratio"
|
|
bitfld.long 0x4 19. "BYPASS,Clock divider logic bypass" "0,1"
|
|
bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x4 16. "SAIEN,SAI sub-block enable" "0,1"
|
|
bitfld.long 0x4 13. "ODRIV,Output Drive" "0,1"
|
|
bitfld.long 0x4 12. "MONO,Stereo and Mono mode selection" "0,1"
|
|
bitfld.long 0x4 10.--11. "SYNCMOD,Synchronization mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 9. "SAMPEDGE,Sampling clock edge" "0,1"
|
|
bitfld.long 0x4 8. "SHIFTDIR,Shift direction" "0,1"
|
|
bitfld.long 0x4 5.--7. "DATAWD,Data width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 2.--3. "PROT,Protocol selection" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "OPTMOD,Operating mode" "0,1,2,3"
|
|
line.long 0x8 "B0CFG1,Block 0 configuration registe"
|
|
bitfld.long 0x8 14.--15. "CPAMOD,Compander mode" "0,1,2,3"
|
|
bitfld.long 0x8 13. "CPLMOD,Complement mode" "0,1"
|
|
hexmask.long.byte 0x8 7.--12. 1. "MTFCNT,Mute frame count"
|
|
bitfld.long 0x8 6. "MTVAL,Mute value" "0,1"
|
|
bitfld.long 0x8 5. "MT,Mute" "0,1"
|
|
bitfld.long 0x8 4. "SDOM,Serial data output management" "0,1"
|
|
bitfld.long 0x8 3. "FLUSH,FIFO flush" "0,1"
|
|
bitfld.long 0x8 0.--2. "FFTH,FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "B0FCFG,Block 0 frame configuration regist"
|
|
bitfld.long 0xC 18. "FSOST,Frame synchronization offset" "0,1"
|
|
bitfld.long 0xC 17. "FSPL,Frame synchronization active polarity" "0,1"
|
|
bitfld.long 0xC 16. "FSFUNC,Frame synchronization function" "0,1"
|
|
hexmask.long.byte 0xC 8.--14. 1. "FSAWD,Frame synchronization active width"
|
|
hexmask.long.byte 0xC 0.--7. 1. "FWD,Frame width"
|
|
line.long 0x10 "B0SCFG,Block 0 slot configuration regist"
|
|
hexmask.long.word 0x10 16.--31. 1. "SLOTAV,Slot activation vector"
|
|
hexmask.long.byte 0x10 8.--11. 1. "SLOTNUM,Slot number within frame"
|
|
bitfld.long 0x10 6.--7. "SLOTWD,Slot width" "0,1,2,3"
|
|
hexmask.long.byte 0x10 0.--4. 1. "DATAOST,Data offset"
|
|
line.long 0x14 "B0INTEN,Block 0 interrupt enable regist"
|
|
bitfld.long 0x14 6. "FSPDETIE,Frame synchronization postpone detection interrupt enable" "0,1"
|
|
bitfld.long 0x14 5. "FSADETIE,Frame synchronization advanced detection interrupt enable" "0,1"
|
|
bitfld.long 0x14 4. "ACNRDYIE,Audio codec not ready interrupt enable" "0,1"
|
|
bitfld.long 0x14 3. "FFREQIE,FIFO request interrupt enable" "0,1"
|
|
bitfld.long 0x14 2. "ERRCKIE,Error clock interrupt enable" "0,1"
|
|
bitfld.long 0x14 1. "MTDETIE,Mute detection interrupt enable" "0,1"
|
|
bitfld.long 0x14 0. "OUERRIE,FIFO overrun or underrun interrupt enable" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "B0STAT,Block 0 status regist"
|
|
bitfld.long 0x0 16.--18. "FFSTAT,FIFO status" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6. "FSPDET,Frame synchronization postponed detection" "0,1"
|
|
bitfld.long 0x0 5. "FSADET,Frame synchronization advanced detection" "0,1"
|
|
bitfld.long 0x0 4. "ACNRDY,Audio codec not ready" "0,1"
|
|
bitfld.long 0x0 3. "FFREQ,FIFO request" "0,1"
|
|
bitfld.long 0x0 2. "ERRCK,Error clock" "0,1"
|
|
bitfld.long 0x0 1. "MTDET,Mute detection" "0,1"
|
|
bitfld.long 0x0 0. "OUERR,Overrun or underrun" "0,1"
|
|
group.long 0x1C++0x1B
|
|
line.long 0x0 "B0INTC,Block 0 interrupt flag clear regist"
|
|
bitfld.long 0x0 6. "FSPDETC,Frame synchronization postponed detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 5. "FSADETC,Frame synchronization advanced detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 4. "ACNRDYC,Audio codec not ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 2. "ERRCKC,Clock error interrupt clear" "0,1"
|
|
bitfld.long 0x0 1. "MTDETC,Mute detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 0. "OUERRC,Overrun or underrun interrupt clear" "0,1"
|
|
line.long 0x4 "B0DATA,Block 0 data regist"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data"
|
|
line.long 0x8 "B1CFG0,Block 1 configuration registe"
|
|
bitfld.long 0x8 27. "MCLKEN,The master clock enable" "0,1"
|
|
bitfld.long 0x8 26. "MOSPR,The master clock oversampling rate" "0,1"
|
|
hexmask.long.byte 0x8 20.--25. 1. "MDIV,Master clock divider ratio"
|
|
bitfld.long 0x8 19. "BYPASS,Clock divider logic bypass" "0,1"
|
|
bitfld.long 0x8 17. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x8 16. "SAIEN,SAI sub-block enable" "0,1"
|
|
bitfld.long 0x8 13. "ODRIV,Output Drive" "0,1"
|
|
bitfld.long 0x8 12. "MONO,Stereo and Mono mode selection" "0,1"
|
|
bitfld.long 0x8 10.--11. "SYNCMOD,Synchronization mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 9. "SAMPEDGE,Sampling clock edge" "0,1"
|
|
bitfld.long 0x8 8. "SHIFTDIR,Shift direction" "0,1"
|
|
bitfld.long 0x8 5.--7. "DATAWD,Data width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 2.--3. "PROT,Protocol selection" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OPTMOD,Operating mode" "0,1,2,3"
|
|
line.long 0xC "B1CFG1,Block 1 configuration registe"
|
|
bitfld.long 0xC 14.--15. "CPAMOD,Compander mode" "0,1,2,3"
|
|
bitfld.long 0xC 13. "CPLMOD,Complement mode" "0,1"
|
|
hexmask.long.byte 0xC 7.--12. 1. "MTFCNT,Mute frame count"
|
|
bitfld.long 0xC 6. "MTVAL,Mute value" "0,1"
|
|
bitfld.long 0xC 5. "MT,Mute" "0,1"
|
|
bitfld.long 0xC 4. "SDOM,Serial data output management" "0,1"
|
|
bitfld.long 0xC 3. "FLUSH,FIFO flush" "0,1"
|
|
bitfld.long 0xC 0.--2. "FFTH,FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "B1FCFG,Block 1 frame configuration regist"
|
|
bitfld.long 0x10 18. "FSOST,Frame synchronization offset" "0,1"
|
|
bitfld.long 0x10 17. "FSPOLR,Frame synchronization active polarity" "0,1"
|
|
bitfld.long 0x10 16. "FSFUNC,Frame synchronization function" "0,1"
|
|
hexmask.long.byte 0x10 8.--14. 1. "FSAWD,Frame synchronization active width"
|
|
hexmask.long.byte 0x10 0.--7. 1. "FWD,Frame width"
|
|
line.long 0x14 "B1SCFG,Block 1 slot configuration regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "SLOTAV,Slot activation vector"
|
|
hexmask.long.byte 0x14 8.--11. 1. "SLOTNUM,Slot number within frame"
|
|
bitfld.long 0x14 6.--7. "SLOTWD,Slot width" "0,1,2,3"
|
|
hexmask.long.byte 0x14 0.--4. 1. "DATAOST,Data offset"
|
|
line.long 0x18 "B1INTEN,Block 1 interrupt enable regist"
|
|
bitfld.long 0x18 6. "FSPDETIE,Frame synchronization postpone detection interrupt enable" "0,1"
|
|
bitfld.long 0x18 5. "FSADETIE,Frame synchronization advanced detection interrupt enable" "0,1"
|
|
bitfld.long 0x18 4. "ACNRDYIE,Audio codec not ready interrupt enable" "0,1"
|
|
bitfld.long 0x18 3. "FFREQIE,FIFO request interrupt enable" "0,1"
|
|
bitfld.long 0x18 2. "ERRCKIE,Error clock interrupt enable" "0,1"
|
|
bitfld.long 0x18 1. "MTDETIE,Mute detection interrupt enable" "0,1"
|
|
bitfld.long 0x18 0. "OUERRRIE,FIFO overrun or underrun interrupt enable" "0,1"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "B1STAT,Block 1 status regist"
|
|
bitfld.long 0x0 16.--18. "FFSTAT,FIFO status" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6. "FSPDET,Frame synchronization postponed detection" "0,1"
|
|
bitfld.long 0x0 5. "FSADET,Frame synchronization advanced detection" "0,1"
|
|
bitfld.long 0x0 4. "ACNRDY,Audio codec not ready" "0,1"
|
|
bitfld.long 0x0 3. "FFREQ,FIFO request" "0,1"
|
|
bitfld.long 0x0 2. "ERRCK,Error clock" "0,1"
|
|
bitfld.long 0x0 1. "MTDET,Mute detection" "0,1"
|
|
bitfld.long 0x0 0. "OUERR,Overrun or underrun" "0,1"
|
|
group.long 0x3C++0xF
|
|
line.long 0x0 "B1INTC,Block 1 interrupt flag clear regist"
|
|
bitfld.long 0x0 6. "FSPDETC,Frame synchronization postponed detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 5. "FSADETC,Frame synchronization advanced detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 4. "ACNRDYC,Audio codec not ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 2. "ERRCKC,Clock error interrupt clear" "0,1"
|
|
bitfld.long 0x0 1. "MTDETC,Mute detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 0. "OUERRC,Overrun or underrun interrupt clear" "0,1"
|
|
line.long 0x4 "B1DATA,Block 1 data regist"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data"
|
|
line.long 0x8 "PDMCTL,PDM control register"
|
|
bitfld.long 0x8 9. "CLKL1EN,PDM clock line 1 enable" "0,1"
|
|
bitfld.long 0x8 8. "CLKL0EN,PDM clock line 0 enable" "0,1"
|
|
bitfld.long 0x8 4.--5. "MICNUMSEL,Select microphones number" "0,1,2,3"
|
|
bitfld.long 0x8 0. "PDMEN,PDM enable" "0,1"
|
|
line.long 0xC "PDMCFG,PDM configuration register"
|
|
bitfld.long 0xC 20.--22. "DPR2,The 2nd group of right channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16.--18. "DPL2,The 2nd group of left channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 12.--14. "DPR1,The 1st group of right channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 8.--10. "DPL1,The 1st group of left channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 4.--6. "DPR0,The 0 group of right channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 0.--2. "DPL0,The 0 group of left channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "SAI1"
|
|
base ad:0x40015C00
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "SYNCFG,Synchronize configuration register"
|
|
bitfld.long 0x0 4.--5. "SYNO,Synchronization outputs" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SYNI,Synchronization inputs" "0,1,2,3"
|
|
line.long 0x4 "B0CFG0,Block 0 configuration registe"
|
|
bitfld.long 0x4 27. "MCLKEN,The master clock enable" "0,1"
|
|
bitfld.long 0x4 26. "MOSPR,The master clock oversampling rate" "0,1"
|
|
hexmask.long.byte 0x4 20.--25. 1. "MDIV,Master clock divider ratio"
|
|
bitfld.long 0x4 19. "BYPASS,Clock divider logic bypass" "0,1"
|
|
bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x4 16. "SAIEN,SAI sub-block enable" "0,1"
|
|
bitfld.long 0x4 13. "ODRIV,Output Drive" "0,1"
|
|
bitfld.long 0x4 12. "MONO,Stereo and Mono mode selection" "0,1"
|
|
bitfld.long 0x4 10.--11. "SYNCMOD,Synchronization mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 9. "SAMPEDGE,Sampling clock edge" "0,1"
|
|
bitfld.long 0x4 8. "SHIFTDIR,Shift direction" "0,1"
|
|
bitfld.long 0x4 5.--7. "DATAWD,Data width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 2.--3. "PROT,Protocol selection" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "OPTMOD,Operating mode" "0,1,2,3"
|
|
line.long 0x8 "B0CFG1,Block 0 configuration registe"
|
|
bitfld.long 0x8 14.--15. "CPAMOD,Compander mode" "0,1,2,3"
|
|
bitfld.long 0x8 13. "CPLMOD,Complement mode" "0,1"
|
|
hexmask.long.byte 0x8 7.--12. 1. "MTFCNT,Mute frame count"
|
|
bitfld.long 0x8 6. "MTVAL,Mute value" "0,1"
|
|
bitfld.long 0x8 5. "MT,Mute" "0,1"
|
|
bitfld.long 0x8 4. "SDOM,Serial data output management" "0,1"
|
|
bitfld.long 0x8 3. "FLUSH,FIFO flush" "0,1"
|
|
bitfld.long 0x8 0.--2. "FFTH,FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "B0FCFG,Block 0 frame configuration regist"
|
|
bitfld.long 0xC 18. "FSOST,Frame synchronization offset" "0,1"
|
|
bitfld.long 0xC 17. "FSPL,Frame synchronization active polarity" "0,1"
|
|
bitfld.long 0xC 16. "FSFUNC,Frame synchronization function" "0,1"
|
|
hexmask.long.byte 0xC 8.--14. 1. "FSAWD,Frame synchronization active width"
|
|
hexmask.long.byte 0xC 0.--7. 1. "FWD,Frame width"
|
|
line.long 0x10 "B0SCFG,Block 0 slot configuration regist"
|
|
hexmask.long.word 0x10 16.--31. 1. "SLOTAV,Slot activation vector"
|
|
hexmask.long.byte 0x10 8.--11. 1. "SLOTNUM,Slot number within frame"
|
|
bitfld.long 0x10 6.--7. "SLOTWD,Slot width" "0,1,2,3"
|
|
hexmask.long.byte 0x10 0.--4. 1. "DATAOST,Data offset"
|
|
line.long 0x14 "B0INTEN,Block 0 interrupt enable regist"
|
|
bitfld.long 0x14 6. "FSPDETIE,Frame synchronization postpone detection interrupt enable" "0,1"
|
|
bitfld.long 0x14 5. "FSADETIE,Frame synchronization advanced detection interrupt enable" "0,1"
|
|
bitfld.long 0x14 4. "ACNRDYIE,Audio codec not ready interrupt enable" "0,1"
|
|
bitfld.long 0x14 3. "FFREQIE,FIFO request interrupt enable" "0,1"
|
|
bitfld.long 0x14 2. "ERRCKIE,Error clock interrupt enable" "0,1"
|
|
bitfld.long 0x14 1. "MTDETIE,Mute detection interrupt enable" "0,1"
|
|
bitfld.long 0x14 0. "OUERRIE,FIFO overrun or underrun interrupt enable" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "B0STAT,Block 0 status regist"
|
|
bitfld.long 0x0 16.--18. "FFSTAT,FIFO status" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6. "FSPDET,Frame synchronization postponed detection" "0,1"
|
|
bitfld.long 0x0 5. "FSADET,Frame synchronization advanced detection" "0,1"
|
|
bitfld.long 0x0 4. "ACNRDY,Audio codec not ready" "0,1"
|
|
bitfld.long 0x0 3. "FFREQ,FIFO request" "0,1"
|
|
bitfld.long 0x0 2. "ERRCK,Error clock" "0,1"
|
|
bitfld.long 0x0 1. "MTDET,Mute detection" "0,1"
|
|
bitfld.long 0x0 0. "OUERR,Overrun or underrun" "0,1"
|
|
group.long 0x1C++0x1B
|
|
line.long 0x0 "B0INTC,Block 0 interrupt flag clear regist"
|
|
bitfld.long 0x0 6. "FSPDETC,Frame synchronization postponed detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 5. "FSADETC,Frame synchronization advanced detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 4. "ACNRDYC,Audio codec not ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 2. "ERRCKC,Clock error interrupt clear" "0,1"
|
|
bitfld.long 0x0 1. "MTDETC,Mute detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 0. "OUERRC,Overrun or underrun interrupt clear" "0,1"
|
|
line.long 0x4 "B0DATA,Block 0 data regist"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data"
|
|
line.long 0x8 "B1CFG0,Block 1 configuration registe"
|
|
bitfld.long 0x8 27. "MCLKEN,The master clock enable" "0,1"
|
|
bitfld.long 0x8 26. "MOSPR,The master clock oversampling rate" "0,1"
|
|
hexmask.long.byte 0x8 20.--25. 1. "MDIV,Master clock divider ratio"
|
|
bitfld.long 0x8 19. "BYPASS,Clock divider logic bypass" "0,1"
|
|
bitfld.long 0x8 17. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x8 16. "SAIEN,SAI sub-block enable" "0,1"
|
|
bitfld.long 0x8 13. "ODRIV,Output Drive" "0,1"
|
|
bitfld.long 0x8 12. "MONO,Stereo and Mono mode selection" "0,1"
|
|
bitfld.long 0x8 10.--11. "SYNCMOD,Synchronization mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 9. "SAMPEDGE,Sampling clock edge" "0,1"
|
|
bitfld.long 0x8 8. "SHIFTDIR,Shift direction" "0,1"
|
|
bitfld.long 0x8 5.--7. "DATAWD,Data width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 2.--3. "PROT,Protocol selection" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OPTMOD,Operating mode" "0,1,2,3"
|
|
line.long 0xC "B1CFG1,Block 1 configuration registe"
|
|
bitfld.long 0xC 14.--15. "CPAMOD,Compander mode" "0,1,2,3"
|
|
bitfld.long 0xC 13. "CPLMOD,Complement mode" "0,1"
|
|
hexmask.long.byte 0xC 7.--12. 1. "MTFCNT,Mute frame count"
|
|
bitfld.long 0xC 6. "MTVAL,Mute value" "0,1"
|
|
bitfld.long 0xC 5. "MT,Mute" "0,1"
|
|
bitfld.long 0xC 4. "SDOM,Serial data output management" "0,1"
|
|
bitfld.long 0xC 3. "FLUSH,FIFO flush" "0,1"
|
|
bitfld.long 0xC 0.--2. "FFTH,FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "B1FCFG,Block 1 frame configuration regist"
|
|
bitfld.long 0x10 18. "FSOST,Frame synchronization offset" "0,1"
|
|
bitfld.long 0x10 17. "FSPOLR,Frame synchronization active polarity" "0,1"
|
|
bitfld.long 0x10 16. "FSFUNC,Frame synchronization function" "0,1"
|
|
hexmask.long.byte 0x10 8.--14. 1. "FSAWD,Frame synchronization active width"
|
|
hexmask.long.byte 0x10 0.--7. 1. "FWD,Frame width"
|
|
line.long 0x14 "B1SCFG,Block 1 slot configuration regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "SLOTAV,Slot activation vector"
|
|
hexmask.long.byte 0x14 8.--11. 1. "SLOTNUM,Slot number within frame"
|
|
bitfld.long 0x14 6.--7. "SLOTWD,Slot width" "0,1,2,3"
|
|
hexmask.long.byte 0x14 0.--4. 1. "DATAOST,Data offset"
|
|
line.long 0x18 "B1INTEN,Block 1 interrupt enable regist"
|
|
bitfld.long 0x18 6. "FSPDETIE,Frame synchronization postpone detection interrupt enable" "0,1"
|
|
bitfld.long 0x18 5. "FSADETIE,Frame synchronization advanced detection interrupt enable" "0,1"
|
|
bitfld.long 0x18 4. "ACNRDYIE,Audio codec not ready interrupt enable" "0,1"
|
|
bitfld.long 0x18 3. "FFREQIE,FIFO request interrupt enable" "0,1"
|
|
bitfld.long 0x18 2. "ERRCKIE,Error clock interrupt enable" "0,1"
|
|
bitfld.long 0x18 1. "MTDETIE,Mute detection interrupt enable" "0,1"
|
|
bitfld.long 0x18 0. "OUERRRIE,FIFO overrun or underrun interrupt enable" "0,1"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "B1STAT,Block 1 status regist"
|
|
bitfld.long 0x0 16.--18. "FFSTAT,FIFO status" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6. "FSPDET,Frame synchronization postponed detection" "0,1"
|
|
bitfld.long 0x0 5. "FSADET,Frame synchronization advanced detection" "0,1"
|
|
bitfld.long 0x0 4. "ACNRDY,Audio codec not ready" "0,1"
|
|
bitfld.long 0x0 3. "FFREQ,FIFO request" "0,1"
|
|
bitfld.long 0x0 2. "ERRCK,Error clock" "0,1"
|
|
bitfld.long 0x0 1. "MTDET,Mute detection" "0,1"
|
|
bitfld.long 0x0 0. "OUERR,Overrun or underrun" "0,1"
|
|
group.long 0x3C++0xF
|
|
line.long 0x0 "B1INTC,Block 1 interrupt flag clear regist"
|
|
bitfld.long 0x0 6. "FSPDETC,Frame synchronization postponed detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 5. "FSADETC,Frame synchronization advanced detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 4. "ACNRDYC,Audio codec not ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 2. "ERRCKC,Clock error interrupt clear" "0,1"
|
|
bitfld.long 0x0 1. "MTDETC,Mute detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 0. "OUERRC,Overrun or underrun interrupt clear" "0,1"
|
|
line.long 0x4 "B1DATA,Block 1 data regist"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data"
|
|
line.long 0x8 "PDMCTL,PDM control register"
|
|
bitfld.long 0x8 9. "CLKL1EN,PDM clock line 1 enable" "0,1"
|
|
bitfld.long 0x8 8. "CLKL0EN,PDM clock line 0 enable" "0,1"
|
|
bitfld.long 0x8 4.--5. "MICNUMSEL,Select microphones number" "0,1,2,3"
|
|
bitfld.long 0x8 0. "PDMEN,PDM enable" "0,1"
|
|
line.long 0xC "PDMCFG,PDM configuration register"
|
|
bitfld.long 0xC 20.--22. "DPR2,The 2nd group of right channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16.--18. "DPL2,The 2nd group of left channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 12.--14. "DPR1,The 1st group of right channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 8.--10. "DPL1,The 1st group of left channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 4.--6. "DPR0,The 0 group of right channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 0.--2. "DPL0,The 0 group of left channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "SAI2"
|
|
base ad:0x40016000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "SYNCFG,Synchronize configuration register"
|
|
bitfld.long 0x0 4.--5. "SYNO,Synchronization outputs" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SYNI,Synchronization inputs" "0,1,2,3"
|
|
line.long 0x4 "B0CFG0,Block 0 configuration registe"
|
|
bitfld.long 0x4 27. "MCLKEN,The master clock enable" "0,1"
|
|
bitfld.long 0x4 26. "MOSPR,The master clock oversampling rate" "0,1"
|
|
hexmask.long.byte 0x4 20.--25. 1. "MDIV,Master clock divider ratio"
|
|
bitfld.long 0x4 19. "BYPASS,Clock divider logic bypass" "0,1"
|
|
bitfld.long 0x4 17. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x4 16. "SAIEN,SAI sub-block enable" "0,1"
|
|
bitfld.long 0x4 13. "ODRIV,Output Drive" "0,1"
|
|
bitfld.long 0x4 12. "MONO,Stereo and Mono mode selection" "0,1"
|
|
bitfld.long 0x4 10.--11. "SYNCMOD,Synchronization mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 9. "SAMPEDGE,Sampling clock edge" "0,1"
|
|
bitfld.long 0x4 8. "SHIFTDIR,Shift direction" "0,1"
|
|
bitfld.long 0x4 5.--7. "DATAWD,Data width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 2.--3. "PROT,Protocol selection" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "OPTMOD,Operating mode" "0,1,2,3"
|
|
line.long 0x8 "B0CFG1,Block 0 configuration registe"
|
|
bitfld.long 0x8 14.--15. "CPAMOD,Compander mode" "0,1,2,3"
|
|
bitfld.long 0x8 13. "CPLMOD,Complement mode" "0,1"
|
|
hexmask.long.byte 0x8 7.--12. 1. "MTFCNT,Mute frame count"
|
|
bitfld.long 0x8 6. "MTVAL,Mute value" "0,1"
|
|
bitfld.long 0x8 5. "MT,Mute" "0,1"
|
|
bitfld.long 0x8 4. "SDOM,Serial data output management" "0,1"
|
|
bitfld.long 0x8 3. "FLUSH,FIFO flush" "0,1"
|
|
bitfld.long 0x8 0.--2. "FFTH,FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "B0FCFG,Block 0 frame configuration regist"
|
|
bitfld.long 0xC 18. "FSOST,Frame synchronization offset" "0,1"
|
|
bitfld.long 0xC 17. "FSPL,Frame synchronization active polarity" "0,1"
|
|
bitfld.long 0xC 16. "FSFUNC,Frame synchronization function" "0,1"
|
|
hexmask.long.byte 0xC 8.--14. 1. "FSAWD,Frame synchronization active width"
|
|
hexmask.long.byte 0xC 0.--7. 1. "FWD,Frame width"
|
|
line.long 0x10 "B0SCFG,Block 0 slot configuration regist"
|
|
hexmask.long.word 0x10 16.--31. 1. "SLOTAV,Slot activation vector"
|
|
hexmask.long.byte 0x10 8.--11. 1. "SLOTNUM,Slot number within frame"
|
|
bitfld.long 0x10 6.--7. "SLOTWD,Slot width" "0,1,2,3"
|
|
hexmask.long.byte 0x10 0.--4. 1. "DATAOST,Data offset"
|
|
line.long 0x14 "B0INTEN,Block 0 interrupt enable regist"
|
|
bitfld.long 0x14 6. "FSPDETIE,Frame synchronization postpone detection interrupt enable" "0,1"
|
|
bitfld.long 0x14 5. "FSADETIE,Frame synchronization advanced detection interrupt enable" "0,1"
|
|
bitfld.long 0x14 4. "ACNRDYIE,Audio codec not ready interrupt enable" "0,1"
|
|
bitfld.long 0x14 3. "FFREQIE,FIFO request interrupt enable" "0,1"
|
|
bitfld.long 0x14 2. "ERRCKIE,Error clock interrupt enable" "0,1"
|
|
bitfld.long 0x14 1. "MTDETIE,Mute detection interrupt enable" "0,1"
|
|
bitfld.long 0x14 0. "OUERRIE,FIFO overrun or underrun interrupt enable" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "B0STAT,Block 0 status regist"
|
|
bitfld.long 0x0 16.--18. "FFSTAT,FIFO status" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6. "FSPDET,Frame synchronization postponed detection" "0,1"
|
|
bitfld.long 0x0 5. "FSADET,Frame synchronization advanced detection" "0,1"
|
|
bitfld.long 0x0 4. "ACNRDY,Audio codec not ready" "0,1"
|
|
bitfld.long 0x0 3. "FFREQ,FIFO request" "0,1"
|
|
bitfld.long 0x0 2. "ERRCK,Error clock" "0,1"
|
|
bitfld.long 0x0 1. "MTDET,Mute detection" "0,1"
|
|
bitfld.long 0x0 0. "OUERR,Overrun or underrun" "0,1"
|
|
group.long 0x1C++0x1B
|
|
line.long 0x0 "B0INTC,Block 0 interrupt flag clear regist"
|
|
bitfld.long 0x0 6. "FSPDETC,Frame synchronization postponed detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 5. "FSADETC,Frame synchronization advanced detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 4. "ACNRDYC,Audio codec not ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 2. "ERRCKC,Clock error interrupt clear" "0,1"
|
|
bitfld.long 0x0 1. "MTDETC,Mute detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 0. "OUERRC,Overrun or underrun interrupt clear" "0,1"
|
|
line.long 0x4 "B0DATA,Block 0 data regist"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data"
|
|
line.long 0x8 "B1CFG0,Block 1 configuration registe"
|
|
bitfld.long 0x8 27. "MCLKEN,The master clock enable" "0,1"
|
|
bitfld.long 0x8 26. "MOSPR,The master clock oversampling rate" "0,1"
|
|
hexmask.long.byte 0x8 20.--25. 1. "MDIV,Master clock divider ratio"
|
|
bitfld.long 0x8 19. "BYPASS,Clock divider logic bypass" "0,1"
|
|
bitfld.long 0x8 17. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x8 16. "SAIEN,SAI sub-block enable" "0,1"
|
|
bitfld.long 0x8 13. "ODRIV,Output Drive" "0,1"
|
|
bitfld.long 0x8 12. "MONO,Stereo and Mono mode selection" "0,1"
|
|
bitfld.long 0x8 10.--11. "SYNCMOD,Synchronization mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 9. "SAMPEDGE,Sampling clock edge" "0,1"
|
|
bitfld.long 0x8 8. "SHIFTDIR,Shift direction" "0,1"
|
|
bitfld.long 0x8 5.--7. "DATAWD,Data width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 2.--3. "PROT,Protocol selection" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OPTMOD,Operating mode" "0,1,2,3"
|
|
line.long 0xC "B1CFG1,Block 1 configuration registe"
|
|
bitfld.long 0xC 14.--15. "CPAMOD,Compander mode" "0,1,2,3"
|
|
bitfld.long 0xC 13. "CPLMOD,Complement mode" "0,1"
|
|
hexmask.long.byte 0xC 7.--12. 1. "MTFCNT,Mute frame count"
|
|
bitfld.long 0xC 6. "MTVAL,Mute value" "0,1"
|
|
bitfld.long 0xC 5. "MT,Mute" "0,1"
|
|
bitfld.long 0xC 4. "SDOM,Serial data output management" "0,1"
|
|
bitfld.long 0xC 3. "FLUSH,FIFO flush" "0,1"
|
|
bitfld.long 0xC 0.--2. "FFTH,FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "B1FCFG,Block 1 frame configuration regist"
|
|
bitfld.long 0x10 18. "FSOST,Frame synchronization offset" "0,1"
|
|
bitfld.long 0x10 17. "FSPOLR,Frame synchronization active polarity" "0,1"
|
|
bitfld.long 0x10 16. "FSFUNC,Frame synchronization function" "0,1"
|
|
hexmask.long.byte 0x10 8.--14. 1. "FSAWD,Frame synchronization active width"
|
|
hexmask.long.byte 0x10 0.--7. 1. "FWD,Frame width"
|
|
line.long 0x14 "B1SCFG,Block 1 slot configuration regist"
|
|
hexmask.long.word 0x14 16.--31. 1. "SLOTAV,Slot activation vector"
|
|
hexmask.long.byte 0x14 8.--11. 1. "SLOTNUM,Slot number within frame"
|
|
bitfld.long 0x14 6.--7. "SLOTWD,Slot width" "0,1,2,3"
|
|
hexmask.long.byte 0x14 0.--4. 1. "DATAOST,Data offset"
|
|
line.long 0x18 "B1INTEN,Block 1 interrupt enable regist"
|
|
bitfld.long 0x18 6. "FSPDETIE,Frame synchronization postpone detection interrupt enable" "0,1"
|
|
bitfld.long 0x18 5. "FSADETIE,Frame synchronization advanced detection interrupt enable" "0,1"
|
|
bitfld.long 0x18 4. "ACNRDYIE,Audio codec not ready interrupt enable" "0,1"
|
|
bitfld.long 0x18 3. "FFREQIE,FIFO request interrupt enable" "0,1"
|
|
bitfld.long 0x18 2. "ERRCKIE,Error clock interrupt enable" "0,1"
|
|
bitfld.long 0x18 1. "MTDETIE,Mute detection interrupt enable" "0,1"
|
|
bitfld.long 0x18 0. "OUERRRIE,FIFO overrun or underrun interrupt enable" "0,1"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "B1STAT,Block 1 status regist"
|
|
bitfld.long 0x0 16.--18. "FFSTAT,FIFO status" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6. "FSPDET,Frame synchronization postponed detection" "0,1"
|
|
bitfld.long 0x0 5. "FSADET,Frame synchronization advanced detection" "0,1"
|
|
bitfld.long 0x0 4. "ACNRDY,Audio codec not ready" "0,1"
|
|
bitfld.long 0x0 3. "FFREQ,FIFO request" "0,1"
|
|
bitfld.long 0x0 2. "ERRCK,Error clock" "0,1"
|
|
bitfld.long 0x0 1. "MTDET,Mute detection" "0,1"
|
|
bitfld.long 0x0 0. "OUERR,Overrun or underrun" "0,1"
|
|
group.long 0x3C++0xF
|
|
line.long 0x0 "B1INTC,Block 1 interrupt flag clear regist"
|
|
bitfld.long 0x0 6. "FSPDETC,Frame synchronization postponed detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 5. "FSADETC,Frame synchronization advanced detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 4. "ACNRDYC,Audio codec not ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 2. "ERRCKC,Clock error interrupt clear" "0,1"
|
|
bitfld.long 0x0 1. "MTDETC,Mute detection interrupt clear" "0,1"
|
|
bitfld.long 0x0 0. "OUERRC,Overrun or underrun interrupt clear" "0,1"
|
|
line.long 0x4 "B1DATA,Block 1 data regist"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data"
|
|
line.long 0x8 "PDMCTL,PDM control register"
|
|
bitfld.long 0x8 9. "CLKL1EN,PDM clock line 1 enable" "0,1"
|
|
bitfld.long 0x8 8. "CLKL0EN,PDM clock line 0 enable" "0,1"
|
|
bitfld.long 0x8 4.--5. "MICNUMSEL,Select microphones number" "0,1,2,3"
|
|
bitfld.long 0x8 0. "PDMEN,PDM enable" "0,1"
|
|
line.long 0xC "PDMCFG,PDM configuration register"
|
|
bitfld.long 0xC 20.--22. "DPR2,The 2nd group of right channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16.--18. "DPL2,The 2nd group of left channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 12.--14. "DPR1,The 1st group of right channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 8.--10. "DPL1,The 1st group of left channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 4.--6. "DPR0,The 0 group of right channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 0.--2. "DPL0,The 0 group of left channel microphone data flow delay period" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree.end
|
|
tree "SDIO (Secure Digital Input/Output Interface)"
|
|
base ad:0x0
|
|
tree "SDIO0"
|
|
base ad:0x52007000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "PWRCTL,Power control register"
|
|
bitfld.long 0x0 4. "DIRPS,Data and command direction polarity selection bit" "0,1"
|
|
bitfld.long 0x0 3. "VSEN,Voltage switch enable bit" "0,1"
|
|
bitfld.long 0x0 2. "VSSTART,Voltage switch start bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "PWRCTL,SDIO power control bits" "0,1,2,3"
|
|
line.long 0x4 "CLKCTL,Clock control register"
|
|
bitfld.long 0x4 20.--21. "RECLK,Receive clock selection bits" "0,1,2,3"
|
|
bitfld.long 0x4 19. "BUSSP,Bus speed mode selection bit" "0,1"
|
|
bitfld.long 0x4 18. "DRSEL,Data rate selection bit" "0,1"
|
|
bitfld.long 0x4 17. "HWEN,Hardware flow control enable bit" "0,1"
|
|
bitfld.long 0x4 16. "CLKEDGE,Command and data CLK dephasing selection bit" "0,1"
|
|
bitfld.long 0x4 14.--15. "BUSMODE,SDIO card bus mode control bit" "0,1,2,3"
|
|
bitfld.long 0x4 12. "CLKPWRSAV,CLK clock dynamic switch on/off for power saving" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "DIV,Clock division"
|
|
line.long 0x8 "CMDAGMT,Command argument register"
|
|
hexmask.long 0x8 0.--31. 1. "CMDAGMT,SDIO card command argument"
|
|
line.long 0xC "CMDCTL,Command control register"
|
|
bitfld.long 0xC 16. "CMDSR,Suspend or Resume command and signals interrupt period start/end bit" "0,1"
|
|
bitfld.long 0xC 15. "BOOTMODEN,Boot mode procedure enable bit" "0,1"
|
|
bitfld.long 0xC 14. "BOOTMOD,Boot mode selection bit" "0,1"
|
|
bitfld.long 0xC 13. "HOLD,Hold DSM transmission and reception of new data block" "0,1"
|
|
bitfld.long 0xC 12. "CSMEN,Command state machine (CSM) enable bit" "0,1"
|
|
bitfld.long 0xC 11. "WAITDEND,Waits for ends of data transfer" "0,1"
|
|
bitfld.long 0xC 10. "INTWAIT,Interrupt wait instead of timeout" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "CMDRESP,Waits command response type bits" "0,1,2,3"
|
|
bitfld.long 0xC 7. "TRSTOP,Waits for ends of data transfer" "0,1"
|
|
bitfld.long 0xC 6. "TREN,Data transfer enable bit" "0,1"
|
|
hexmask.long.byte 0xC 0.--5. 1. "CMDIDX,Command index"
|
|
rgroup.long 0x10++0x13
|
|
line.long 0x0 "RSPCMDIDX,Command index response register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "RSPCMDIDX,Last response command index"
|
|
line.long 0x4 "RESP0,Response regist 0"
|
|
hexmask.long 0x4 0.--31. 1. "RESP0,Card state"
|
|
line.long 0x8 "RESP1,Response regist 1"
|
|
hexmask.long 0x8 0.--31. 1. "RESP1,Card state"
|
|
line.long 0xC "RESP2,Response regist 2"
|
|
hexmask.long 0xC 0.--31. 1. "RESP2,Card state"
|
|
line.long 0x10 "RESP3,Response regist 3"
|
|
hexmask.long 0x10 0.--31. 1. "RESP3,Card state"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "DATATO,Data timeout register"
|
|
hexmask.long 0x0 0.--31. 1. "DATATO,Data timeout period"
|
|
line.long 0x4 "DATALEN,Data length register"
|
|
hexmask.long 0x4 0.--24. 1. "DATALEN,Data transfer length"
|
|
line.long 0x8 "DATACTL,Data control register"
|
|
bitfld.long 0x8 13. "FIFOREST,FIFO buffer reset flush all data" "0,1"
|
|
bitfld.long 0x8 12. "ACKEN,Boot acknowledgment enable bit" "0,1"
|
|
hexmask.long.byte 0x8 4.--7. 1. "BLKSZ,Data block size"
|
|
bitfld.long 0x8 2.--3. "TRANSMOD,Data transfer mode" "0,1,2,3"
|
|
bitfld.long 0x8 1. "DATADIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x8 0. "DATAEN,Data transfer enable bit" "0,1"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "DATACNT,Data counter register"
|
|
hexmask.long 0x0 0.--24. 1. "DATACNT,Data count value"
|
|
line.long 0x4 "STAT,Status register"
|
|
bitfld.long 0x4 28. "IDMAEND,IDMA transfer end" "0,1"
|
|
bitfld.long 0x4 27. "IDMERR,IDMA transfer error" "0,1"
|
|
bitfld.long 0x4 26. "CLKSTOP,CLK stopped in Voltage switch procedure" "0,1"
|
|
bitfld.long 0x4 25. "VSEND,Voltage switch critical timing section end" "0,1"
|
|
bitfld.long 0x4 24. "ACKTO,Boot acknowledgment timeout" "0,1"
|
|
bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received and check fail" "0,1"
|
|
bitfld.long 0x4 22. "SDIOINT,SD I/O interrupt received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DAT0BSYEND,CMD response busy DAT0 driver low" "0,1"
|
|
bitfld.long 0x4 20. "DAT0BSY,CMD response busy Inverted DAT0 line" "0,1"
|
|
bitfld.long 0x4 19. "RFE,Receive FIFO is empty" "0,1"
|
|
bitfld.long 0x4 18. "TFE,Transmit FIFO is empty" "0,1"
|
|
bitfld.long 0x4 17. "RFF,Receive FIFO is full" "0,1"
|
|
bitfld.long 0x4 16. "TFF,Transmit FIFO is full" "0,1"
|
|
bitfld.long 0x4 15. "RFH,Receive FIFO is half full: at least half the number of words can be read" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "TFH,Transmit FIFO is half empty: at least half the number of words can be" "0,1"
|
|
bitfld.long 0x4 13. "CMDSTA,Data path active state" "0,1"
|
|
bitfld.long 0x4 12. "DATSTA,Command path active state" "0,1"
|
|
bitfld.long 0x4 11. "DATABOR,Data transfer aborted by CMD12" "0,1"
|
|
bitfld.long 0x4 10. "DTBLKEND,Data block sent/received (CRC check passed)" "0,1"
|
|
bitfld.long 0x4 9. "DATHOLD,Data transfer hold" "0,1"
|
|
bitfld.long 0x4 8. "DTEND,Data end (data counter DATACNT is zero)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CMDSEND,Command sent (no response required)" "0,1"
|
|
bitfld.long 0x4 6. "CMDRECV,Command response received (CRC check passed)" "0,1"
|
|
bitfld.long 0x4 5. "RXORE,Received FIFO overrun error occurs" "0,1"
|
|
bitfld.long 0x4 4. "TXURE,Transmit FIFO underrun error occurs" "0,1"
|
|
bitfld.long 0x4 3. "DTTMOUT,Data timeout" "0,1"
|
|
bitfld.long 0x4 2. "CMDTMOUT,Command response timeout" "0,1"
|
|
bitfld.long 0x4 1. "DTCRCERR,Data block sent/received (CRC check failed)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CCRCERR,Command response received (CRC check failed)" "0,1"
|
|
wgroup.long 0x38++0x3
|
|
line.long 0x0 "INTC,Interrupt clear register"
|
|
bitfld.long 0x0 28. "IDMAENDC,IDMAEND flag clear bit" "0,1"
|
|
bitfld.long 0x0 27. "IDMAERRC,IDMERR flag clear bit" "0,1"
|
|
bitfld.long 0x0 26. "CLKSTOPC,CLKSTOP flag clear bit" "0,1"
|
|
bitfld.long 0x0 25. "VSENDC,VSEND flag clear bit" "0,1"
|
|
bitfld.long 0x0 24. "ACKTOC,ACKTO flag clear bit" "0,1"
|
|
bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1"
|
|
bitfld.long 0x0 22. "SDIOINTC,SDIOINT flag clear bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DAT0BSYENDC,DAT0BSYEND flag clear bit" "0,1"
|
|
bitfld.long 0x0 11. "DATABORC,DATABOR flag clear bit" "0,1"
|
|
bitfld.long 0x0 10. "DTBLKENDC,DTBLKEND flag clear bit" "0,1"
|
|
bitfld.long 0x0 9. "DATHOLDC,DATHOLD flag clear bit" "0,1"
|
|
bitfld.long 0x0 8. "DTENDC,DTEND flag clear bit" "0,1"
|
|
bitfld.long 0x0 7. "CMDSENDC,CMDSEND flag clear bit" "0,1"
|
|
bitfld.long 0x0 6. "CMDRECVC,CMDRECV flag clear bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXOREC,RXORE flag clear bit" "0,1"
|
|
bitfld.long 0x0 4. "TXUREC,TXURE flag clear bit" "0,1"
|
|
bitfld.long 0x0 3. "DTTMOUTC,DTTMOUT flag clear bit" "0,1"
|
|
bitfld.long 0x0 2. "CMDTMOUTC,CMDTMOUT flag clear bit" "0,1"
|
|
bitfld.long 0x0 1. "DTCRCERRC,DTCRCERR flag clear bit" "0,1"
|
|
bitfld.long 0x0 0. "CCRCERRC,CCRCERR flag clear bit" "0,1"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "INTEN,Interrupt enable register"
|
|
bitfld.long 0x0 28. "IDMAENDIE,IDMA transfer end interrupt enable" "0,1"
|
|
bitfld.long 0x0 27. "IDMAERRIE,IDMA transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "CLKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "VSENDIE,Voltage switch critical timing section end interrupt enable" "0,1"
|
|
bitfld.long 0x0 24. "ACKTOIE,Boot acknowledgment timeout enable" "0,1"
|
|
bitfld.long 0x0 23. "ACKFAILIE,Boot acknowledgment received and check fail interrupt enable" "0,1"
|
|
bitfld.long 0x0 22. "SDIOINTIE,SD I/O interrupt received interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DAT0BSYENDIE,DAT0 line signal changed from busy to ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 18. "TFEIE,Transmit FIFO empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 17. "RFFIE,Receive FIFO full interrupt enable" "0,1"
|
|
bitfld.long 0x0 15. "RFHIE,Receive FIFO half full interrupt enable" "0,1"
|
|
bitfld.long 0x0 14. "TFHIE,Transmit FIFO half empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 11. "DATABORIE,Data transfer abort interrupt enable" "0,1"
|
|
bitfld.long 0x0 10. "DTBLKENDIE,Data block end interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DATHOLDIE,Data hold interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "DTENDIE,Data end interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "CMDSENDIE,Command sent interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "CMDRECVIE,Command response received interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXOREIE,Received FIFO overrun error interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "TXUREIE,Transmit FIFO underrun error interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "DTTMOUTIE,Data timeout interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CMDTMOUTIE,Command response timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "DTCRCERRIE,Data CRC fail interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CCRCERRIE,Command response CRC fail interrupt enable" "0,1"
|
|
line.long 0x4 "ACKTIMER,FIFO ACK timer register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "ACKTIME,Boot ACK timeout period"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "FIFO,FIFO data register"
|
|
hexmask.long 0x0 0.--31. 1. "FIFODT,Receive FIFO data or transmit FIFO data"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "IDMACTL,FIFO internal DMA control register"
|
|
bitfld.long 0x0 2. "BUFSEL,IDMA double buffer selection bit" "0,1"
|
|
bitfld.long 0x0 1. "BUFMOD,Double buffer selection bit" "0,1"
|
|
bitfld.long 0x0 0. "IDMAEN,FIFO internal DMA enable bit" "0,1"
|
|
line.long 0x4 "IDMASIZE,FIFO internal DMA buffer size register"
|
|
hexmask.long.byte 0x4 5.--12. 1. "IDMASIZE,Number of bytes per buffer"
|
|
line.long 0x8 "IDMAADDR0,IDMA buffer 0 base address register"
|
|
hexmask.long 0x8 0.--31. 1. "IDMAADDR0,The address is a multiple of 4"
|
|
line.long 0xC "IDMAADDR1,IDMA buffer 1 base address register"
|
|
hexmask.long 0xC 0.--31. 1. "IDMAADDR1,The address is a multiple of 4"
|
|
tree.end
|
|
tree "SDIO1"
|
|
base ad:0x48022400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "PWRCTL,Power control register"
|
|
bitfld.long 0x0 4. "DIRPS,Data and command direction polarity selection bit" "0,1"
|
|
bitfld.long 0x0 3. "VSEN,Voltage switch enable bit" "0,1"
|
|
bitfld.long 0x0 2. "VSSTART,Voltage switch start bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "PWRCTL,SDIO power control bits" "0,1,2,3"
|
|
line.long 0x4 "CLKCTL,Clock control register"
|
|
bitfld.long 0x4 20.--21. "RECLK,Receive clock selection bits" "0,1,2,3"
|
|
bitfld.long 0x4 19. "BUSSP,Bus speed mode selection bit" "0,1"
|
|
bitfld.long 0x4 18. "DRSEL,Data rate selection bit" "0,1"
|
|
bitfld.long 0x4 17. "HWEN,Hardware flow control enable bit" "0,1"
|
|
bitfld.long 0x4 16. "CLKEDGE,Command and data CLK dephasing selection bit" "0,1"
|
|
bitfld.long 0x4 14.--15. "BUSMODE,SDIO card bus mode control bit" "0,1,2,3"
|
|
bitfld.long 0x4 12. "CLKPWRSAV,CLK clock dynamic switch on/off for power saving" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "DIV,Clock division"
|
|
line.long 0x8 "CMDAGMT,Command argument register"
|
|
hexmask.long 0x8 0.--31. 1. "CMDAGMT,SDIO card command argument"
|
|
line.long 0xC "CMDCTL,Command control register"
|
|
bitfld.long 0xC 16. "CMDSR,Suspend or Resume command and signals interrupt period start/end bit" "0,1"
|
|
bitfld.long 0xC 15. "BOOTMODEN,Boot mode procedure enable bit" "0,1"
|
|
bitfld.long 0xC 14. "BOOTMOD,Boot mode selection bit" "0,1"
|
|
bitfld.long 0xC 13. "HOLD,Hold DSM transmission and reception of new data block" "0,1"
|
|
bitfld.long 0xC 12. "CSMEN,Command state machine (CSM) enable bit" "0,1"
|
|
bitfld.long 0xC 11. "WAITDEND,Waits for ends of data transfer" "0,1"
|
|
bitfld.long 0xC 10. "INTWAIT,Interrupt wait instead of timeout" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "CMDRESP,Waits command response type bits" "0,1,2,3"
|
|
bitfld.long 0xC 7. "TRSTOP,Waits for ends of data transfer" "0,1"
|
|
bitfld.long 0xC 6. "TREN,Data transfer enable bit" "0,1"
|
|
hexmask.long.byte 0xC 0.--5. 1. "CMDIDX,Command index"
|
|
rgroup.long 0x10++0x13
|
|
line.long 0x0 "RSPCMDIDX,Command index response register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "RSPCMDIDX,Last response command index"
|
|
line.long 0x4 "RESP0,Response regist 0"
|
|
hexmask.long 0x4 0.--31. 1. "RESP0,Card state"
|
|
line.long 0x8 "RESP1,Response regist 1"
|
|
hexmask.long 0x8 0.--31. 1. "RESP1,Card state"
|
|
line.long 0xC "RESP2,Response regist 2"
|
|
hexmask.long 0xC 0.--31. 1. "RESP2,Card state"
|
|
line.long 0x10 "RESP3,Response regist 3"
|
|
hexmask.long 0x10 0.--31. 1. "RESP3,Card state"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "DATATO,Data timeout register"
|
|
hexmask.long 0x0 0.--31. 1. "DATATO,Data timeout period"
|
|
line.long 0x4 "DATALEN,Data length register"
|
|
hexmask.long 0x4 0.--24. 1. "DATALEN,Data transfer length"
|
|
line.long 0x8 "DATACTL,Data control register"
|
|
bitfld.long 0x8 13. "FIFOREST,FIFO buffer reset flush all data" "0,1"
|
|
bitfld.long 0x8 12. "ACKEN,Boot acknowledgment enable bit" "0,1"
|
|
hexmask.long.byte 0x8 4.--7. 1. "BLKSZ,Data block size"
|
|
bitfld.long 0x8 2.--3. "TRANSMOD,Data transfer mode" "0,1,2,3"
|
|
bitfld.long 0x8 1. "DATADIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x8 0. "DATAEN,Data transfer enable bit" "0,1"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "DATACNT,Data counter register"
|
|
hexmask.long 0x0 0.--24. 1. "DATACNT,Data count value"
|
|
line.long 0x4 "STAT,Status register"
|
|
bitfld.long 0x4 28. "IDMAEND,IDMA transfer end" "0,1"
|
|
bitfld.long 0x4 27. "IDMERR,IDMA transfer error" "0,1"
|
|
bitfld.long 0x4 26. "CLKSTOP,CLK stopped in Voltage switch procedure" "0,1"
|
|
bitfld.long 0x4 25. "VSEND,Voltage switch critical timing section end" "0,1"
|
|
bitfld.long 0x4 24. "ACKTO,Boot acknowledgment timeout" "0,1"
|
|
bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received and check fail" "0,1"
|
|
bitfld.long 0x4 22. "SDIOINT,SD I/O interrupt received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DAT0BSYEND,CMD response busy DAT0 driver low" "0,1"
|
|
bitfld.long 0x4 20. "DAT0BSY,CMD response busy Inverted DAT0 line" "0,1"
|
|
bitfld.long 0x4 19. "RFE,Receive FIFO is empty" "0,1"
|
|
bitfld.long 0x4 18. "TFE,Transmit FIFO is empty" "0,1"
|
|
bitfld.long 0x4 17. "RFF,Receive FIFO is full" "0,1"
|
|
bitfld.long 0x4 16. "TFF,Transmit FIFO is full" "0,1"
|
|
bitfld.long 0x4 15. "RFH,Receive FIFO is half full: at least half the number of words can be read" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "TFH,Transmit FIFO is half empty: at least half the number of words can be" "0,1"
|
|
bitfld.long 0x4 13. "CMDSTA,Data path active state" "0,1"
|
|
bitfld.long 0x4 12. "DATSTA,Command path active state" "0,1"
|
|
bitfld.long 0x4 11. "DATABOR,Data transfer aborted by CMD12" "0,1"
|
|
bitfld.long 0x4 10. "DTBLKEND,Data block sent/received (CRC check passed)" "0,1"
|
|
bitfld.long 0x4 9. "DATHOLD,Data transfer hold" "0,1"
|
|
bitfld.long 0x4 8. "DTEND,Data end (data counter DATACNT is zero)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CMDSEND,Command sent (no response required)" "0,1"
|
|
bitfld.long 0x4 6. "CMDRECV,Command response received (CRC check passed)" "0,1"
|
|
bitfld.long 0x4 5. "RXORE,Received FIFO overrun error occurs" "0,1"
|
|
bitfld.long 0x4 4. "TXURE,Transmit FIFO underrun error occurs" "0,1"
|
|
bitfld.long 0x4 3. "DTTMOUT,Data timeout" "0,1"
|
|
bitfld.long 0x4 2. "CMDTMOUT,Command response timeout" "0,1"
|
|
bitfld.long 0x4 1. "DTCRCERR,Data block sent/received (CRC check failed)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CCRCERR,Command response received (CRC check failed)" "0,1"
|
|
wgroup.long 0x38++0x3
|
|
line.long 0x0 "INTC,Interrupt clear register"
|
|
bitfld.long 0x0 28. "IDMAENDC,IDMAEND flag clear bit" "0,1"
|
|
bitfld.long 0x0 27. "IDMAERRC,IDMERR flag clear bit" "0,1"
|
|
bitfld.long 0x0 26. "CLKSTOPC,CLKSTOP flag clear bit" "0,1"
|
|
bitfld.long 0x0 25. "VSENDC,VSEND flag clear bit" "0,1"
|
|
bitfld.long 0x0 24. "ACKTOC,ACKTO flag clear bit" "0,1"
|
|
bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0,1"
|
|
bitfld.long 0x0 22. "SDIOINTC,SDIOINT flag clear bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DAT0BSYENDC,DAT0BSYEND flag clear bit" "0,1"
|
|
bitfld.long 0x0 11. "DATABORC,DATABOR flag clear bit" "0,1"
|
|
bitfld.long 0x0 10. "DTBLKENDC,DTBLKEND flag clear bit" "0,1"
|
|
bitfld.long 0x0 9. "DATHOLDC,DATHOLD flag clear bit" "0,1"
|
|
bitfld.long 0x0 8. "DTENDC,DTEND flag clear bit" "0,1"
|
|
bitfld.long 0x0 7. "CMDSENDC,CMDSEND flag clear bit" "0,1"
|
|
bitfld.long 0x0 6. "CMDRECVC,CMDRECV flag clear bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXOREC,RXORE flag clear bit" "0,1"
|
|
bitfld.long 0x0 4. "TXUREC,TXURE flag clear bit" "0,1"
|
|
bitfld.long 0x0 3. "DTTMOUTC,DTTMOUT flag clear bit" "0,1"
|
|
bitfld.long 0x0 2. "CMDTMOUTC,CMDTMOUT flag clear bit" "0,1"
|
|
bitfld.long 0x0 1. "DTCRCERRC,DTCRCERR flag clear bit" "0,1"
|
|
bitfld.long 0x0 0. "CCRCERRC,CCRCERR flag clear bit" "0,1"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "INTEN,Interrupt enable register"
|
|
bitfld.long 0x0 28. "IDMAENDIE,IDMA transfer end interrupt enable" "0,1"
|
|
bitfld.long 0x0 27. "IDMAERRIE,IDMA transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "CLKSTOPIE,Voltage Switch clock stopped interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "VSENDIE,Voltage switch critical timing section end interrupt enable" "0,1"
|
|
bitfld.long 0x0 24. "ACKTOIE,Boot acknowledgment timeout enable" "0,1"
|
|
bitfld.long 0x0 23. "ACKFAILIE,Boot acknowledgment received and check fail interrupt enable" "0,1"
|
|
bitfld.long 0x0 22. "SDIOINTIE,SD I/O interrupt received interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DAT0BSYENDIE,DAT0 line signal changed from busy to ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 18. "TFEIE,Transmit FIFO empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 17. "RFFIE,Receive FIFO full interrupt enable" "0,1"
|
|
bitfld.long 0x0 15. "RFHIE,Receive FIFO half full interrupt enable" "0,1"
|
|
bitfld.long 0x0 14. "TFHIE,Transmit FIFO half empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 11. "DATABORIE,Data transfer abort interrupt enable" "0,1"
|
|
bitfld.long 0x0 10. "DTBLKENDIE,Data block end interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DATHOLDIE,Data hold interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "DTENDIE,Data end interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "CMDSENDIE,Command sent interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "CMDRECVIE,Command response received interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXOREIE,Received FIFO overrun error interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "TXUREIE,Transmit FIFO underrun error interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "DTTMOUTIE,Data timeout interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CMDTMOUTIE,Command response timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "DTCRCERRIE,Data CRC fail interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "CCRCERRIE,Command response CRC fail interrupt enable" "0,1"
|
|
line.long 0x4 "ACKTIMER,FIFO ACK timer register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "ACKTIME,Boot ACK timeout period"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "FIFO,FIFO data register"
|
|
hexmask.long 0x0 0.--31. 1. "FIFODT,Receive FIFO data or transmit FIFO data"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "IDMACTL,FIFO internal DMA control register"
|
|
bitfld.long 0x0 2. "BUFSEL,IDMA double buffer selection bit" "0,1"
|
|
bitfld.long 0x0 1. "BUFMOD,Double buffer selection bit" "0,1"
|
|
bitfld.long 0x0 0. "IDMAEN,FIFO internal DMA enable bit" "0,1"
|
|
line.long 0x4 "IDMASIZE,FIFO internal DMA buffer size register"
|
|
hexmask.long.byte 0x4 5.--12. 1. "IDMASIZE,Number of bytes per buffer"
|
|
line.long 0x8 "IDMAADDR0,IDMA buffer 0 base address register"
|
|
hexmask.long 0x8 0.--31. 1. "IDMAADDR0,The address is a multiple of 4"
|
|
line.long 0xC "IDMAADDR1,IDMA buffer 1 base address register"
|
|
hexmask.long 0xC 0.--31. 1. "IDMAADDR1,The address is a multiple of 4"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x0
|
|
tree "SPI0"
|
|
base ad:0x40013000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "SPI_CTL0,Control register 0"
|
|
rbitfld.long 0x0 16. "IOAFEN,Related IOs AF configuration enable" "0,1"
|
|
bitfld.long 0x0 15. "TXCRCI,The transmitter CRC initialization configuration" "0,1"
|
|
bitfld.long 0x0 14. "RXCRCI,The receiver CRC initialization configuration" "0,1"
|
|
bitfld.long 0x0 13. "CRCFS,Full scale CRC polynomial configuration" "0,1"
|
|
bitfld.long 0x0 12. "NSSI,The input level of internal NSS signal" "0,1"
|
|
bitfld.long 0x0 10. "MSPDR,Suspend request in SPI master mode" "0,1"
|
|
bitfld.long 0x0 9. "MSTART,Master start transfer" "0,1"
|
|
bitfld.long 0x0 8. "MASP,The master is suspended automatically in receive mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI enable" "0,1"
|
|
line.long 0x4 "SPI_CTL1,Control register 1"
|
|
hexmask.long.word 0x4 16.--31. 1. "TXSER,When previous number of data stored in the TXSIZE has been transferred it will reload the transmission expansion data amount in the TXSER to TXSIZE"
|
|
hexmask.long.word 0x4 0.--15. 1. "TXSIZE,The current number of data to transfer"
|
|
line.long 0x8 "SPI_CFG0,Configuration register 0"
|
|
bitfld.long 0x8 28.--30. "PSC,Master clock prescaler selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "WORDEN,Word access mode enable" "0,1"
|
|
bitfld.long 0x8 23. "BYTEN,Byte access mode enable" "0,1"
|
|
bitfld.long 0x8 22. "CRCEN,CRC calculation enable" "0,1"
|
|
hexmask.long.byte 0x8 16.--20. 1. "CRCSZ,CRC size"
|
|
bitfld.long 0x8 15. "DMATEN,Transmit buffer DMA enable" "0,1"
|
|
bitfld.long 0x8 14. "DMAREN,Receive buffer DMA enable" "0,1"
|
|
bitfld.long 0x8 11.--12. "TXURDT,Detection of underrun error at slave transmitter" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 9.--10. "TXUROP,Operation of slave transmitter when underrun detected" "0,1,2,3"
|
|
hexmask.long.byte 0x8 5.--8. 1. "FIFOLVL,FIFO threshold level"
|
|
hexmask.long.byte 0x8 0.--4. 1. "DZ,Date size"
|
|
line.long 0xC "SPI_CFG1,Configuration register 1"
|
|
bitfld.long 0xC 31. "AFCTL,AF GPIOs control" "0,1"
|
|
bitfld.long 0xC 30. "NSSCTL,NSS pin output control in master mode" "0,1"
|
|
bitfld.long 0xC 29. "NSSDRV,NSS pin output enable in master mode" "0,1"
|
|
bitfld.long 0xC 28. "NSSIOPL,NSS pin input/output polarity selection" "0,1"
|
|
bitfld.long 0xC 26. "NSSIM,NSS input signal manage mode" "0,1"
|
|
bitfld.long 0xC 25. "CKPL,Clock polarity selection" "0,1"
|
|
bitfld.long 0xC 24. "CKPH,Clock phase selection" "0,1"
|
|
bitfld.long 0xC 23. "LF,LSB first mode" "0,1"
|
|
newline
|
|
bitfld.long 0xC 22. "MSTMOD,Master mode enable" "0,1"
|
|
bitfld.long 0xC 21. "TMOD,SPI TI mode enable" "0,1"
|
|
bitfld.long 0xC 18. "BDEN,Bidirectional enable" "0,1"
|
|
bitfld.long 0xC 17. "BDOEN,Bidirectional transmit output enable" "0,1"
|
|
bitfld.long 0xC 16. "RO,Receive only" "0,1"
|
|
bitfld.long 0xC 15. "SWPMIO,MOSI and MISO pin swap" "0,1"
|
|
hexmask.long.byte 0xC 4.--7. 1. "MDFD,Delay between the data frames in SPI master mode"
|
|
hexmask.long.byte 0xC 0.--3. 1. "MSSD,Delay between active edge of NSS and start transfer or receive data in SPI master mode"
|
|
line.long 0x10 "SPI_INT,Interrupt register"
|
|
bitfld.long 0x10 10. "TXSERFIE,TXSER reload interrupt enable" "0,1"
|
|
bitfld.long 0x10 9. "CONFEIE,SPI configuration error interrupt enable" "0,1"
|
|
bitfld.long 0x10 8. "FEIE,TI frame error interrupt enable" "0,1"
|
|
bitfld.long 0x10 7. "CRCERIE,CRC error interrupt enable" "0,1"
|
|
bitfld.long 0x10 6. "RXOREIE,Overrun error interrupt enable" "0,1"
|
|
bitfld.long 0x10 5. "TXUREIE,Underrun error interrupt enable" "0,1"
|
|
bitfld.long 0x10 4. "TXFIE,Transmission filled interrupt enable" "0,1"
|
|
bitfld.long 0x10 3. "ESTCIE,End of transfer or suspend or TxFIFO clear interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "DPIE,DP interrupt enable" "0,1"
|
|
bitfld.long 0x10 1. "TPIE,TP interrupt enable" "0,1"
|
|
bitfld.long 0x10 0. "RPIE,RP interrupt enable" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SPI_STAT,Status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CTXSIZE,These bits show the number of data frames remaining in the TXSIZE bit feild (in the SPI_CTL1 register)"
|
|
bitfld.long 0x0 15. "RWNE,The word of RxFIFO is not empty" "0,1"
|
|
bitfld.long 0x0 13.--14. "RPLVL,RxFIFO packet level" "0,1,2,3"
|
|
bitfld.long 0x0 12. "TC,TxFIFO transmission complete flag" "0,1"
|
|
bitfld.long 0x0 11. "SPD,Suspend flag" "0,1"
|
|
bitfld.long 0x0 10. "TXSERF,The additional SPI data has been reloaded" "0,1"
|
|
bitfld.long 0x0 9. "CONFERR,SPI configuration error" "0,1"
|
|
bitfld.long 0x0 8. "FERR,SPI TI format error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CRCERR,SPI CRC error" "0,1"
|
|
bitfld.long 0x0 6. "RXORERR,Reception overrun error" "0,1"
|
|
bitfld.long 0x0 5. "TXURERR,Transmission underrun error" "0,1"
|
|
bitfld.long 0x0 4. "TXF,TxFIFO transmission has been filled" "0,1"
|
|
bitfld.long 0x0 3. "ET,End of transmission/reception flag" "0,1"
|
|
bitfld.long 0x0 2. "DP,Duplex packet" "0,1"
|
|
bitfld.long 0x0 1. "TP,TxFIFO packet space available flag" "0,1"
|
|
bitfld.long 0x0 0. "RP,RxFIFO packet space available flag" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "SPI_STATC,Interrupt/Status flags clear register"
|
|
bitfld.long 0x0 11. "SPDC,Clear the suspend flag" "0,1"
|
|
bitfld.long 0x0 10. "TXSERFC,Clear the TXSERF flag" "0,1"
|
|
bitfld.long 0x0 9. "CONFERRC,Clear the configuration error flag" "0,1"
|
|
bitfld.long 0x0 8. "FERRC,Clear the SPI TI format error flag" "0,1"
|
|
bitfld.long 0x0 7. "CRCERRC,Clear the CRC error flag" "0,1"
|
|
bitfld.long 0x0 6. "RXORERRC,Clear the reception overrun error flag" "0,1"
|
|
bitfld.long 0x0 5. "TXURERRC,Clear the transmission underrun error flag" "0,1"
|
|
bitfld.long 0x0 4. "TXFC,Clear the TxFIFO transmission filled flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ETC,Clear the end of transmission/reception flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "SPI_TDATA,Data Transfer register"
|
|
hexmask.long 0x0 0.--31. 1. "TDATA,Data transfer register"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "SPI_RDATA,Data Receive register"
|
|
hexmask.long 0x0 0.--31. 1. "RDATA,Data receive register"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "SPI_CRCPOLY,CRC polynomial register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x44++0x7
|
|
line.long 0x0 "SPI_TCRC,TX CRC register"
|
|
hexmask.long 0x0 0.--31. 1. "TCRC,Tx CRC register"
|
|
line.long 0x4 "SPI_RCRC,RX CRC register"
|
|
hexmask.long 0x4 0.--31. 1. "RCRC,Rx CRC register"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "SPI_URDATA,Underrun Data register"
|
|
hexmask.long 0x0 0.--31. 1. "URDATA,Transmission underrun data at slave mode"
|
|
line.long 0x4 "SPI_I2SCTL,I2S control register"
|
|
rbitfld.long 0x4 31. "I2SCH,I2S channel side" "0,1"
|
|
bitfld.long 0x4 25. "MCKOEN,I2S_MCK output enable" "0,1"
|
|
bitfld.long 0x4 24. "OF,Odd factor for the prescaler" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "DIV,Dividing factor for the prescaler"
|
|
bitfld.long 0x4 11. "I2SSEL,I2S mode selection" "0,1"
|
|
bitfld.long 0x4 10. "I2SEN,I2S enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "I2SOPMOD,I2S operation mode" "0,1,2,3"
|
|
bitfld.long 0x4 7. "PCMSMOD,PCM frame synchronization mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3"
|
|
bitfld.long 0x4 3. "CKPL,Idle state clock polarity" "0,1"
|
|
bitfld.long 0x4 1.--2. "DTLEN,Data length" "0,1,2,3"
|
|
bitfld.long 0x4 0. "CHLEN,Channel length" "0,1"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "SPI_RXDLYCK,RX clock delay register"
|
|
bitfld.long 0x0 11. "MRXDEN,When master receive sampling clock delay enable" "0,1"
|
|
hexmask.long.byte 0x0 6.--10. 1. "MRXD,When master receive sampling clock delay units"
|
|
bitfld.long 0x0 5. "SRXDEN,When slave receive sampling clock delay enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SRXD,When slave receive sampling clock delay units"
|
|
tree.end
|
|
tree "SPI1"
|
|
base ad:0x40003800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "SPI_CTL0,Control register 0"
|
|
rbitfld.long 0x0 16. "IOAFEN,Related IOs AF configuration enable" "0,1"
|
|
bitfld.long 0x0 15. "TXCRCI,The transmitter CRC initialization configuration" "0,1"
|
|
bitfld.long 0x0 14. "RXCRCI,The receiver CRC initialization configuration" "0,1"
|
|
bitfld.long 0x0 13. "CRCFS,Full scale CRC polynomial configuration" "0,1"
|
|
bitfld.long 0x0 12. "NSSI,The input level of internal NSS signal" "0,1"
|
|
bitfld.long 0x0 10. "MSPDR,Suspend request in SPI master mode" "0,1"
|
|
bitfld.long 0x0 9. "MSTART,Master start transfer" "0,1"
|
|
bitfld.long 0x0 8. "MASP,The master is suspended automatically in receive mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI enable" "0,1"
|
|
line.long 0x4 "SPI_CTL1,Control register 1"
|
|
hexmask.long.word 0x4 16.--31. 1. "TXSER,When previous number of data stored in the TXSIZE has been transferred it will reload the transmission expansion data amount in the TXSER to TXSIZE"
|
|
hexmask.long.word 0x4 0.--15. 1. "TXSIZE,The current number of data to transfer"
|
|
line.long 0x8 "SPI_CFG0,Configuration register 0"
|
|
bitfld.long 0x8 28.--30. "PSC,Master clock prescaler selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "WORDEN,Word access mode enable" "0,1"
|
|
bitfld.long 0x8 23. "BYTEN,Byte access mode enable" "0,1"
|
|
bitfld.long 0x8 22. "CRCEN,CRC calculation enable" "0,1"
|
|
hexmask.long.byte 0x8 16.--20. 1. "CRCSZ,CRC size"
|
|
bitfld.long 0x8 15. "DMATEN,Transmit buffer DMA enable" "0,1"
|
|
bitfld.long 0x8 14. "DMAREN,Receive buffer DMA enable" "0,1"
|
|
bitfld.long 0x8 11.--12. "TXURDT,Detection of underrun error at slave transmitter" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 9.--10. "TXUROP,Operation of slave transmitter when underrun detected" "0,1,2,3"
|
|
hexmask.long.byte 0x8 5.--8. 1. "FIFOLVL,FIFO threshold level"
|
|
hexmask.long.byte 0x8 0.--4. 1. "DZ,Date size"
|
|
line.long 0xC "SPI_CFG1,Configuration register 1"
|
|
bitfld.long 0xC 31. "AFCTL,AF GPIOs control" "0,1"
|
|
bitfld.long 0xC 30. "NSSCTL,NSS pin output control in master mode" "0,1"
|
|
bitfld.long 0xC 29. "NSSDRV,NSS pin output enable in master mode" "0,1"
|
|
bitfld.long 0xC 28. "NSSIOPL,NSS pin input/output polarity selection" "0,1"
|
|
bitfld.long 0xC 26. "NSSIM,NSS input signal manage mode" "0,1"
|
|
bitfld.long 0xC 25. "CKPL,Clock polarity selection" "0,1"
|
|
bitfld.long 0xC 24. "CKPH,Clock phase selection" "0,1"
|
|
bitfld.long 0xC 23. "LF,LSB first mode" "0,1"
|
|
newline
|
|
bitfld.long 0xC 22. "MSTMOD,Master mode enable" "0,1"
|
|
bitfld.long 0xC 21. "TMOD,SPI TI mode enable" "0,1"
|
|
bitfld.long 0xC 18. "BDEN,Bidirectional enable" "0,1"
|
|
bitfld.long 0xC 17. "BDOEN,Bidirectional transmit output enable" "0,1"
|
|
bitfld.long 0xC 16. "RO,Receive only" "0,1"
|
|
bitfld.long 0xC 15. "SWPMIO,MOSI and MISO pin swap" "0,1"
|
|
hexmask.long.byte 0xC 4.--7. 1. "MDFD,Delay between the data frames in SPI master mode"
|
|
hexmask.long.byte 0xC 0.--3. 1. "MSSD,Delay between active edge of NSS and start transfer or receive data in SPI master mode"
|
|
line.long 0x10 "SPI_INT,Interrupt register"
|
|
bitfld.long 0x10 10. "TXSERFIE,TXSER reload interrupt enable" "0,1"
|
|
bitfld.long 0x10 9. "CONFEIE,SPI configuration error interrupt enable" "0,1"
|
|
bitfld.long 0x10 8. "FEIE,TI frame error interrupt enable" "0,1"
|
|
bitfld.long 0x10 7. "CRCERIE,CRC error interrupt enable" "0,1"
|
|
bitfld.long 0x10 6. "RXOREIE,Overrun error interrupt enable" "0,1"
|
|
bitfld.long 0x10 5. "TXUREIE,Underrun error interrupt enable" "0,1"
|
|
bitfld.long 0x10 4. "TXFIE,Transmission filled interrupt enable" "0,1"
|
|
bitfld.long 0x10 3. "ESTCIE,End of transfer or suspend or TxFIFO clear interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "DPIE,DP interrupt enable" "0,1"
|
|
bitfld.long 0x10 1. "TPIE,TP interrupt enable" "0,1"
|
|
bitfld.long 0x10 0. "RPIE,RP interrupt enable" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SPI_STAT,Status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CTXSIZE,These bits show the number of data frames remaining in the TXSIZE bit feild (in the SPI_CTL1 register)"
|
|
bitfld.long 0x0 15. "RWNE,The word of RxFIFO is not empty" "0,1"
|
|
bitfld.long 0x0 13.--14. "RPLVL,RxFIFO packet level" "0,1,2,3"
|
|
bitfld.long 0x0 12. "TC,TxFIFO transmission complete flag" "0,1"
|
|
bitfld.long 0x0 11. "SPD,Suspend flag" "0,1"
|
|
bitfld.long 0x0 10. "TXSERF,The additional SPI data has been reloaded" "0,1"
|
|
bitfld.long 0x0 9. "CONFERR,SPI configuration error" "0,1"
|
|
bitfld.long 0x0 8. "FERR,SPI TI format error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CRCERR,SPI CRC error" "0,1"
|
|
bitfld.long 0x0 6. "RXORERR,Reception overrun error" "0,1"
|
|
bitfld.long 0x0 5. "TXURERR,Transmission underrun error" "0,1"
|
|
bitfld.long 0x0 4. "TXF,TxFIFO transmission has been filled" "0,1"
|
|
bitfld.long 0x0 3. "ET,End of transmission/reception flag" "0,1"
|
|
bitfld.long 0x0 2. "DP,Duplex packet" "0,1"
|
|
bitfld.long 0x0 1. "TP,TxFIFO packet space available flag" "0,1"
|
|
bitfld.long 0x0 0. "RP,RxFIFO packet space available flag" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "SPI_STATC,Interrupt/Status flags clear register"
|
|
bitfld.long 0x0 11. "SPDC,Clear the suspend flag" "0,1"
|
|
bitfld.long 0x0 10. "TXSERFC,Clear the TXSERF flag" "0,1"
|
|
bitfld.long 0x0 9. "CONFERRC,Clear the configuration error flag" "0,1"
|
|
bitfld.long 0x0 8. "FERRC,Clear the SPI TI format error flag" "0,1"
|
|
bitfld.long 0x0 7. "CRCERRC,Clear the CRC error flag" "0,1"
|
|
bitfld.long 0x0 6. "RXORERRC,Clear the reception overrun error flag" "0,1"
|
|
bitfld.long 0x0 5. "TXURERRC,Clear the transmission underrun error flag" "0,1"
|
|
bitfld.long 0x0 4. "TXFC,Clear the TxFIFO transmission filled flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ETC,Clear the end of transmission/reception flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "SPI_TDATA,Data Transfer register"
|
|
hexmask.long 0x0 0.--31. 1. "TDATA,Data transfer register"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "SPI_RDATA,Data Receive register"
|
|
hexmask.long 0x0 0.--31. 1. "RDATA,Data receive register"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "SPI_CRCPOLY,CRC polynomial register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x44++0x7
|
|
line.long 0x0 "SPI_TCRC,TX CRC register"
|
|
hexmask.long 0x0 0.--31. 1. "TCRC,Tx CRC register"
|
|
line.long 0x4 "SPI_RCRC,RX CRC register"
|
|
hexmask.long 0x4 0.--31. 1. "RCRC,Rx CRC register"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "SPI_URDATA,Underrun Data register"
|
|
hexmask.long 0x0 0.--31. 1. "URDATA,Transmission underrun data at slave mode"
|
|
line.long 0x4 "SPI_I2SCTL,I2S control register"
|
|
rbitfld.long 0x4 31. "I2SCH,I2S channel side" "0,1"
|
|
bitfld.long 0x4 25. "MCKOEN,I2S_MCK output enable" "0,1"
|
|
bitfld.long 0x4 24. "OF,Odd factor for the prescaler" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "DIV,Dividing factor for the prescaler"
|
|
bitfld.long 0x4 11. "I2SSEL,I2S mode selection" "0,1"
|
|
bitfld.long 0x4 10. "I2SEN,I2S enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "I2SOPMOD,I2S operation mode" "0,1,2,3"
|
|
bitfld.long 0x4 7. "PCMSMOD,PCM frame synchronization mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3"
|
|
bitfld.long 0x4 3. "CKPL,Idle state clock polarity" "0,1"
|
|
bitfld.long 0x4 1.--2. "DTLEN,Data length" "0,1,2,3"
|
|
bitfld.long 0x4 0. "CHLEN,Channel length" "0,1"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "SPI_RXDLYCK,RX clock delay register"
|
|
bitfld.long 0x0 11. "MRXDEN,When master receive sampling clock delay enable" "0,1"
|
|
hexmask.long.byte 0x0 6.--10. 1. "MRXD,When master receive sampling clock delay units"
|
|
bitfld.long 0x0 5. "SRXDEN,When slave receive sampling clock delay enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SRXD,When slave receive sampling clock delay units"
|
|
tree.end
|
|
tree "SPI2"
|
|
base ad:0x40003C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "SPI_CTL0,Control register 0"
|
|
rbitfld.long 0x0 16. "IOAFEN,Related IOs AF configuration enable" "0,1"
|
|
bitfld.long 0x0 15. "TXCRCI,The transmitter CRC initialization configuration" "0,1"
|
|
bitfld.long 0x0 14. "RXCRCI,The receiver CRC initialization configuration" "0,1"
|
|
bitfld.long 0x0 13. "CRCFS,Full scale CRC polynomial configuration" "0,1"
|
|
bitfld.long 0x0 12. "NSSI,The input level of internal NSS signal" "0,1"
|
|
bitfld.long 0x0 10. "MSPDR,Suspend request in SPI master mode" "0,1"
|
|
bitfld.long 0x0 9. "MSTART,Master start transfer" "0,1"
|
|
bitfld.long 0x0 8. "MASP,The master is suspended automatically in receive mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI enable" "0,1"
|
|
line.long 0x4 "SPI_CTL1,Control register 1"
|
|
hexmask.long.word 0x4 16.--31. 1. "TXSER,When previous number of data stored in the TXSIZE has been transferred it will reload the transmission expansion data amount in the TXSER to TXSIZE"
|
|
hexmask.long.word 0x4 0.--15. 1. "TXSIZE,The current number of data to transfer"
|
|
line.long 0x8 "SPI_CFG0,Configuration register 0"
|
|
bitfld.long 0x8 28.--30. "PSC,Master clock prescaler selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "WORDEN,Word access mode enable" "0,1"
|
|
bitfld.long 0x8 23. "BYTEN,Byte access mode enable" "0,1"
|
|
bitfld.long 0x8 22. "CRCEN,CRC calculation enable" "0,1"
|
|
hexmask.long.byte 0x8 16.--20. 1. "CRCSZ,CRC size"
|
|
bitfld.long 0x8 15. "DMATEN,Transmit buffer DMA enable" "0,1"
|
|
bitfld.long 0x8 14. "DMAREN,Receive buffer DMA enable" "0,1"
|
|
bitfld.long 0x8 11.--12. "TXURDT,Detection of underrun error at slave transmitter" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 9.--10. "TXUROP,Operation of slave transmitter when underrun detected" "0,1,2,3"
|
|
hexmask.long.byte 0x8 5.--8. 1. "FIFOLVL,FIFO threshold level"
|
|
hexmask.long.byte 0x8 0.--4. 1. "DZ,Date size"
|
|
line.long 0xC "SPI_CFG1,Configuration register 1"
|
|
bitfld.long 0xC 31. "AFCTL,AF GPIOs control" "0,1"
|
|
bitfld.long 0xC 30. "NSSCTL,NSS pin output control in master mode" "0,1"
|
|
bitfld.long 0xC 29. "NSSDRV,NSS pin output enable in master mode" "0,1"
|
|
bitfld.long 0xC 28. "NSSIOPL,NSS pin input/output polarity selection" "0,1"
|
|
bitfld.long 0xC 26. "NSSIM,NSS input signal manage mode" "0,1"
|
|
bitfld.long 0xC 25. "CKPL,Clock polarity selection" "0,1"
|
|
bitfld.long 0xC 24. "CKPH,Clock phase selection" "0,1"
|
|
bitfld.long 0xC 23. "LF,LSB first mode" "0,1"
|
|
newline
|
|
bitfld.long 0xC 22. "MSTMOD,Master mode enable" "0,1"
|
|
bitfld.long 0xC 21. "TMOD,SPI TI mode enable" "0,1"
|
|
bitfld.long 0xC 18. "BDEN,Bidirectional enable" "0,1"
|
|
bitfld.long 0xC 17. "BDOEN,Bidirectional transmit output enable" "0,1"
|
|
bitfld.long 0xC 16. "RO,Receive only" "0,1"
|
|
bitfld.long 0xC 15. "SWPMIO,MOSI and MISO pin swap" "0,1"
|
|
hexmask.long.byte 0xC 4.--7. 1. "MDFD,Delay between the data frames in SPI master mode"
|
|
hexmask.long.byte 0xC 0.--3. 1. "MSSD,Delay between active edge of NSS and start transfer or receive data in SPI master mode"
|
|
line.long 0x10 "SPI_INT,Interrupt register"
|
|
bitfld.long 0x10 10. "TXSERFIE,TXSER reload interrupt enable" "0,1"
|
|
bitfld.long 0x10 9. "CONFEIE,SPI configuration error interrupt enable" "0,1"
|
|
bitfld.long 0x10 8. "FEIE,TI frame error interrupt enable" "0,1"
|
|
bitfld.long 0x10 7. "CRCERIE,CRC error interrupt enable" "0,1"
|
|
bitfld.long 0x10 6. "RXOREIE,Overrun error interrupt enable" "0,1"
|
|
bitfld.long 0x10 5. "TXUREIE,Underrun error interrupt enable" "0,1"
|
|
bitfld.long 0x10 4. "TXFIE,Transmission filled interrupt enable" "0,1"
|
|
bitfld.long 0x10 3. "ESTCIE,End of transfer or suspend or TxFIFO clear interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "DPIE,DP interrupt enable" "0,1"
|
|
bitfld.long 0x10 1. "TPIE,TP interrupt enable" "0,1"
|
|
bitfld.long 0x10 0. "RPIE,RP interrupt enable" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SPI_STAT,Status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CTXSIZE,These bits show the number of data frames remaining in the TXSIZE bit feild (in the SPI_CTL1 register)"
|
|
bitfld.long 0x0 15. "RWNE,The word of RxFIFO is not empty" "0,1"
|
|
bitfld.long 0x0 13.--14. "RPLVL,RxFIFO packet level" "0,1,2,3"
|
|
bitfld.long 0x0 12. "TC,TxFIFO transmission complete flag" "0,1"
|
|
bitfld.long 0x0 11. "SPD,Suspend flag" "0,1"
|
|
bitfld.long 0x0 10. "TXSERF,The additional SPI data has been reloaded" "0,1"
|
|
bitfld.long 0x0 9. "CONFERR,SPI configuration error" "0,1"
|
|
bitfld.long 0x0 8. "FERR,SPI TI format error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CRCERR,SPI CRC error" "0,1"
|
|
bitfld.long 0x0 6. "RXORERR,Reception overrun error" "0,1"
|
|
bitfld.long 0x0 5. "TXURERR,Transmission underrun error" "0,1"
|
|
bitfld.long 0x0 4. "TXF,TxFIFO transmission has been filled" "0,1"
|
|
bitfld.long 0x0 3. "ET,End of transmission/reception flag" "0,1"
|
|
bitfld.long 0x0 2. "DP,Duplex packet" "0,1"
|
|
bitfld.long 0x0 1. "TP,TxFIFO packet space available flag" "0,1"
|
|
bitfld.long 0x0 0. "RP,RxFIFO packet space available flag" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "SPI_STATC,Interrupt/Status flags clear register"
|
|
bitfld.long 0x0 11. "SPDC,Clear the suspend flag" "0,1"
|
|
bitfld.long 0x0 10. "TXSERFC,Clear the TXSERF flag" "0,1"
|
|
bitfld.long 0x0 9. "CONFERRC,Clear the configuration error flag" "0,1"
|
|
bitfld.long 0x0 8. "FERRC,Clear the SPI TI format error flag" "0,1"
|
|
bitfld.long 0x0 7. "CRCERRC,Clear the CRC error flag" "0,1"
|
|
bitfld.long 0x0 6. "RXORERRC,Clear the reception overrun error flag" "0,1"
|
|
bitfld.long 0x0 5. "TXURERRC,Clear the transmission underrun error flag" "0,1"
|
|
bitfld.long 0x0 4. "TXFC,Clear the TxFIFO transmission filled flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ETC,Clear the end of transmission/reception flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "SPI_TDATA,Data Transfer register"
|
|
hexmask.long 0x0 0.--31. 1. "TDATA,Data transfer register"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "SPI_RDATA,Data Receive register"
|
|
hexmask.long 0x0 0.--31. 1. "RDATA,Data receive register"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "SPI_CRCPOLY,CRC polynomial register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x44++0x7
|
|
line.long 0x0 "SPI_TCRC,TX CRC register"
|
|
hexmask.long 0x0 0.--31. 1. "TCRC,Tx CRC register"
|
|
line.long 0x4 "SPI_RCRC,RX CRC register"
|
|
hexmask.long 0x4 0.--31. 1. "RCRC,Rx CRC register"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "SPI_URDATA,Underrun Data register"
|
|
hexmask.long 0x0 0.--31. 1. "URDATA,Transmission underrun data at slave mode"
|
|
line.long 0x4 "SPI_I2SCTL,I2S control register"
|
|
rbitfld.long 0x4 31. "I2SCH,I2S channel side" "0,1"
|
|
bitfld.long 0x4 25. "MCKOEN,I2S_MCK output enable" "0,1"
|
|
bitfld.long 0x4 24. "OF,Odd factor for the prescaler" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "DIV,Dividing factor for the prescaler"
|
|
bitfld.long 0x4 11. "I2SSEL,I2S mode selection" "0,1"
|
|
bitfld.long 0x4 10. "I2SEN,I2S enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "I2SOPMOD,I2S operation mode" "0,1,2,3"
|
|
bitfld.long 0x4 7. "PCMSMOD,PCM frame synchronization mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3"
|
|
bitfld.long 0x4 3. "CKPL,Idle state clock polarity" "0,1"
|
|
bitfld.long 0x4 1.--2. "DTLEN,Data length" "0,1,2,3"
|
|
bitfld.long 0x4 0. "CHLEN,Channel length" "0,1"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "SPI_RXDLYCK,RX clock delay register"
|
|
bitfld.long 0x0 11. "MRXDEN,When master receive sampling clock delay enable" "0,1"
|
|
hexmask.long.byte 0x0 6.--10. 1. "MRXD,When master receive sampling clock delay units"
|
|
bitfld.long 0x0 5. "SRXDEN,When slave receive sampling clock delay enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SRXD,When slave receive sampling clock delay units"
|
|
tree.end
|
|
tree "SPI3"
|
|
base ad:0x40013400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "SPI_CTL0,Control register 0"
|
|
rbitfld.long 0x0 16. "IOAFEN,Related IOs AF configuration enable" "0,1"
|
|
bitfld.long 0x0 15. "TXCRCI,The transmitter CRC initialization configuration" "0,1"
|
|
bitfld.long 0x0 14. "RXCRCI,The receiver CRC initialization configuration" "0,1"
|
|
bitfld.long 0x0 13. "CRCFS,Full scale CRC polynomial configuration" "0,1"
|
|
bitfld.long 0x0 12. "NSSI,The input level of internal NSS signal" "0,1"
|
|
bitfld.long 0x0 10. "MSPDR,Suspend request in SPI master mode" "0,1"
|
|
bitfld.long 0x0 9. "MSTART,Master start transfer" "0,1"
|
|
bitfld.long 0x0 8. "MASP,The master is suspended automatically in receive mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI enable" "0,1"
|
|
line.long 0x4 "SPI_CTL1,Control register 1"
|
|
hexmask.long.word 0x4 16.--31. 1. "TXSER,When previous number of data stored in the TXSIZE has been transferred it will reload the transmission expansion data amount in the TXSER to TXSIZE"
|
|
hexmask.long.word 0x4 0.--15. 1. "TXSIZE,The current number of data to transfer"
|
|
line.long 0x8 "SPI_CFG0,Configuration register 0"
|
|
bitfld.long 0x8 28.--30. "PSC,Master clock prescaler selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "WORDEN,Word access mode enable" "0,1"
|
|
bitfld.long 0x8 23. "BYTEN,Byte access mode enable" "0,1"
|
|
bitfld.long 0x8 22. "CRCEN,CRC calculation enable" "0,1"
|
|
hexmask.long.byte 0x8 16.--20. 1. "CRCSZ,CRC size"
|
|
bitfld.long 0x8 15. "DMATEN,Transmit buffer DMA enable" "0,1"
|
|
bitfld.long 0x8 14. "DMAREN,Receive buffer DMA enable" "0,1"
|
|
bitfld.long 0x8 11.--12. "TXURDT,Detection of underrun error at slave transmitter" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 9.--10. "TXUROP,Operation of slave transmitter when underrun detected" "0,1,2,3"
|
|
hexmask.long.byte 0x8 5.--8. 1. "FIFOLVL,FIFO threshold level"
|
|
hexmask.long.byte 0x8 0.--4. 1. "DZ,Date size"
|
|
line.long 0xC "SPI_CFG1,Configuration register 1"
|
|
bitfld.long 0xC 31. "AFCTL,AF GPIOs control" "0,1"
|
|
bitfld.long 0xC 30. "NSSCTL,NSS pin output control in master mode" "0,1"
|
|
bitfld.long 0xC 29. "NSSDRV,NSS pin output enable in master mode" "0,1"
|
|
bitfld.long 0xC 28. "NSSIOPL,NSS pin input/output polarity selection" "0,1"
|
|
bitfld.long 0xC 26. "NSSIM,NSS input signal manage mode" "0,1"
|
|
bitfld.long 0xC 25. "CKPL,Clock polarity selection" "0,1"
|
|
bitfld.long 0xC 24. "CKPH,Clock phase selection" "0,1"
|
|
bitfld.long 0xC 23. "LF,LSB first mode" "0,1"
|
|
newline
|
|
bitfld.long 0xC 22. "MSTMOD,Master mode enable" "0,1"
|
|
bitfld.long 0xC 21. "TMOD,SPI TI mode enable" "0,1"
|
|
bitfld.long 0xC 18. "BDEN,Bidirectional enable" "0,1"
|
|
bitfld.long 0xC 17. "BDOEN,Bidirectional transmit output enable" "0,1"
|
|
bitfld.long 0xC 16. "RO,Receive only" "0,1"
|
|
bitfld.long 0xC 15. "SWPMIO,MOSI and MISO pin swap" "0,1"
|
|
hexmask.long.byte 0xC 4.--7. 1. "MDFD,Delay between the data frames in SPI master mode"
|
|
hexmask.long.byte 0xC 0.--3. 1. "MSSD,Delay between active edge of NSS and start transfer or receive data in SPI master mode"
|
|
line.long 0x10 "SPI_INT,Interrupt register"
|
|
bitfld.long 0x10 10. "TXSERFIE,TXSER reload interrupt enable" "0,1"
|
|
bitfld.long 0x10 9. "CONFEIE,SPI configuration error interrupt enable" "0,1"
|
|
bitfld.long 0x10 8. "FEIE,TI frame error interrupt enable" "0,1"
|
|
bitfld.long 0x10 7. "CRCERIE,CRC error interrupt enable" "0,1"
|
|
bitfld.long 0x10 6. "RXOREIE,Overrun error interrupt enable" "0,1"
|
|
bitfld.long 0x10 5. "TXUREIE,Underrun error interrupt enable" "0,1"
|
|
bitfld.long 0x10 4. "TXFIE,Transmission filled interrupt enable" "0,1"
|
|
bitfld.long 0x10 3. "ESTCIE,End of transfer or suspend or TxFIFO clear interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "DPIE,DP interrupt enable" "0,1"
|
|
bitfld.long 0x10 1. "TPIE,TP interrupt enable" "0,1"
|
|
bitfld.long 0x10 0. "RPIE,RP interrupt enable" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SPI_STAT,Status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CTXSIZE,These bits show the number of data frames remaining in the TXSIZE bit feild (in the SPI_CTL1 register)"
|
|
bitfld.long 0x0 15. "RWNE,The word of RxFIFO is not empty" "0,1"
|
|
bitfld.long 0x0 13.--14. "RPLVL,RxFIFO packet level" "0,1,2,3"
|
|
bitfld.long 0x0 12. "TC,TxFIFO transmission complete flag" "0,1"
|
|
bitfld.long 0x0 11. "SPD,Suspend flag" "0,1"
|
|
bitfld.long 0x0 10. "TXSERF,The additional SPI data has been reloaded" "0,1"
|
|
bitfld.long 0x0 9. "CONFERR,SPI configuration error" "0,1"
|
|
bitfld.long 0x0 8. "FERR,SPI TI format error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CRCERR,SPI CRC error" "0,1"
|
|
bitfld.long 0x0 6. "RXORERR,Reception overrun error" "0,1"
|
|
bitfld.long 0x0 5. "TXURERR,Transmission underrun error" "0,1"
|
|
bitfld.long 0x0 4. "TXF,TxFIFO transmission has been filled" "0,1"
|
|
bitfld.long 0x0 3. "ET,End of transmission/reception flag" "0,1"
|
|
bitfld.long 0x0 2. "DP,Duplex packet" "0,1"
|
|
bitfld.long 0x0 1. "TP,TxFIFO packet space available flag" "0,1"
|
|
bitfld.long 0x0 0. "RP,RxFIFO packet space available flag" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "SPI_STATC,Interrupt/Status flags clear register"
|
|
bitfld.long 0x0 11. "SPDC,Clear the suspend flag" "0,1"
|
|
bitfld.long 0x0 10. "TXSERFC,Clear the TXSERF flag" "0,1"
|
|
bitfld.long 0x0 9. "CONFERRC,Clear the configuration error flag" "0,1"
|
|
bitfld.long 0x0 8. "FERRC,Clear the SPI TI format error flag" "0,1"
|
|
bitfld.long 0x0 7. "CRCERRC,Clear the CRC error flag" "0,1"
|
|
bitfld.long 0x0 6. "RXORERRC,Clear the reception overrun error flag" "0,1"
|
|
bitfld.long 0x0 5. "TXURERRC,Clear the transmission underrun error flag" "0,1"
|
|
bitfld.long 0x0 4. "TXFC,Clear the TxFIFO transmission filled flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ETC,Clear the end of transmission/reception flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "SPI_TDATA,Data Transfer register"
|
|
hexmask.long 0x0 0.--31. 1. "TDATA,Data transfer register"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "SPI_RDATA,Data Receive register"
|
|
hexmask.long 0x0 0.--31. 1. "RDATA,Data receive register"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "SPI_CRCPOLY,CRC polynomial register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x44++0x7
|
|
line.long 0x0 "SPI_TCRC,TX CRC register"
|
|
hexmask.long 0x0 0.--31. 1. "TCRC,Tx CRC register"
|
|
line.long 0x4 "SPI_RCRC,RX CRC register"
|
|
hexmask.long 0x4 0.--31. 1. "RCRC,Rx CRC register"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "SPI_URDATA,Underrun Data register"
|
|
hexmask.long 0x0 0.--31. 1. "URDATA,Transmission underrun data at slave mode"
|
|
line.long 0x4 "SPI_I2SCTL,I2S control register"
|
|
rbitfld.long 0x4 31. "I2SCH,I2S channel side" "0,1"
|
|
bitfld.long 0x4 25. "MCKOEN,I2S_MCK output enable" "0,1"
|
|
bitfld.long 0x4 24. "OF,Odd factor for the prescaler" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "DIV,Dividing factor for the prescaler"
|
|
bitfld.long 0x4 11. "I2SSEL,I2S mode selection" "0,1"
|
|
bitfld.long 0x4 10. "I2SEN,I2S enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "I2SOPMOD,I2S operation mode" "0,1,2,3"
|
|
bitfld.long 0x4 7. "PCMSMOD,PCM frame synchronization mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3"
|
|
bitfld.long 0x4 3. "CKPL,Idle state clock polarity" "0,1"
|
|
bitfld.long 0x4 1.--2. "DTLEN,Data length" "0,1,2,3"
|
|
bitfld.long 0x4 0. "CHLEN,Channel length" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "SPI_QCTL,Quad_SPI mode control register"
|
|
bitfld.long 0x0 2. "IO23_DRV,Drive IO2 and IO3 enable" "0,1"
|
|
bitfld.long 0x0 1. "QRD,Quad-SPI mode read select" "0,1"
|
|
bitfld.long 0x0 0. "QMOD,Quad-SPI mode enable" "0,1"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "SPI_RXDLYCK,RX clock delay register"
|
|
bitfld.long 0x0 11. "MRXDEN,When master receive sampling clock delay enable" "0,1"
|
|
hexmask.long.byte 0x0 6.--10. 1. "MRXD,When master receive sampling clock delay units"
|
|
bitfld.long 0x0 5. "SRXDEN,When slave receive sampling clock delay enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SRXD,When slave receive sampling clock delay units"
|
|
tree.end
|
|
tree "SPI4"
|
|
base ad:0x40015000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "SPI_CTL0,Control register 0"
|
|
rbitfld.long 0x0 16. "IOAFEN,Related IOs AF configuration enable" "0,1"
|
|
bitfld.long 0x0 15. "TXCRCI,The transmitter CRC initialization configuration" "0,1"
|
|
bitfld.long 0x0 14. "RXCRCI,The receiver CRC initialization configuration" "0,1"
|
|
bitfld.long 0x0 13. "CRCFS,Full scale CRC polynomial configuration" "0,1"
|
|
bitfld.long 0x0 12. "NSSI,The input level of internal NSS signal" "0,1"
|
|
bitfld.long 0x0 10. "MSPDR,Suspend request in SPI master mode" "0,1"
|
|
bitfld.long 0x0 9. "MSTART,Master start transfer" "0,1"
|
|
bitfld.long 0x0 8. "MASP,The master is suspended automatically in receive mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI enable" "0,1"
|
|
line.long 0x4 "SPI_CTL1,Control register 1"
|
|
hexmask.long.word 0x4 16.--31. 1. "TXSER,When previous number of data stored in the TXSIZE has been transferred it will reload the transmission expansion data amount in the TXSER to TXSIZE"
|
|
hexmask.long.word 0x4 0.--15. 1. "TXSIZE,The current number of data to transfer"
|
|
line.long 0x8 "SPI_CFG0,Configuration register 0"
|
|
bitfld.long 0x8 28.--30. "PSC,Master clock prescaler selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "WORDEN,Word access mode enable" "0,1"
|
|
bitfld.long 0x8 23. "BYTEN,Byte access mode enable" "0,1"
|
|
bitfld.long 0x8 22. "CRCEN,CRC calculation enable" "0,1"
|
|
hexmask.long.byte 0x8 16.--20. 1. "CRCSZ,CRC size"
|
|
bitfld.long 0x8 15. "DMATEN,Transmit buffer DMA enable" "0,1"
|
|
bitfld.long 0x8 14. "DMAREN,Receive buffer DMA enable" "0,1"
|
|
bitfld.long 0x8 11.--12. "TXURDT,Detection of underrun error at slave transmitter" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 9.--10. "TXUROP,Operation of slave transmitter when underrun detected" "0,1,2,3"
|
|
hexmask.long.byte 0x8 5.--8. 1. "FIFOLVL,FIFO threshold level"
|
|
hexmask.long.byte 0x8 0.--4. 1. "DZ,Date size"
|
|
line.long 0xC "SPI_CFG1,Configuration register 1"
|
|
bitfld.long 0xC 31. "AFCTL,AF GPIOs control" "0,1"
|
|
bitfld.long 0xC 30. "NSSCTL,NSS pin output control in master mode" "0,1"
|
|
bitfld.long 0xC 29. "NSSDRV,NSS pin output enable in master mode" "0,1"
|
|
bitfld.long 0xC 28. "NSSIOPL,NSS pin input/output polarity selection" "0,1"
|
|
bitfld.long 0xC 26. "NSSIM,NSS input signal manage mode" "0,1"
|
|
bitfld.long 0xC 25. "CKPL,Clock polarity selection" "0,1"
|
|
bitfld.long 0xC 24. "CKPH,Clock phase selection" "0,1"
|
|
bitfld.long 0xC 23. "LF,LSB first mode" "0,1"
|
|
newline
|
|
bitfld.long 0xC 22. "MSTMOD,Master mode enable" "0,1"
|
|
bitfld.long 0xC 21. "TMOD,SPI TI mode enable" "0,1"
|
|
bitfld.long 0xC 18. "BDEN,Bidirectional enable" "0,1"
|
|
bitfld.long 0xC 17. "BDOEN,Bidirectional transmit output enable" "0,1"
|
|
bitfld.long 0xC 16. "RO,Receive only" "0,1"
|
|
bitfld.long 0xC 15. "SWPMIO,MOSI and MISO pin swap" "0,1"
|
|
hexmask.long.byte 0xC 4.--7. 1. "MDFD,Delay between the data frames in SPI master mode"
|
|
hexmask.long.byte 0xC 0.--3. 1. "MSSD,Delay between active edge of NSS and start transfer or receive data in SPI master mode"
|
|
line.long 0x10 "SPI_INT,Interrupt register"
|
|
bitfld.long 0x10 10. "TXSERFIE,TXSER reload interrupt enable" "0,1"
|
|
bitfld.long 0x10 9. "CONFEIE,SPI configuration error interrupt enable" "0,1"
|
|
bitfld.long 0x10 8. "FEIE,TI frame error interrupt enable" "0,1"
|
|
bitfld.long 0x10 7. "CRCERIE,CRC error interrupt enable" "0,1"
|
|
bitfld.long 0x10 6. "RXOREIE,Overrun error interrupt enable" "0,1"
|
|
bitfld.long 0x10 5. "TXUREIE,Underrun error interrupt enable" "0,1"
|
|
bitfld.long 0x10 4. "TXFIE,Transmission filled interrupt enable" "0,1"
|
|
bitfld.long 0x10 3. "ESTCIE,End of transfer or suspend or TxFIFO clear interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "DPIE,DP interrupt enable" "0,1"
|
|
bitfld.long 0x10 1. "TPIE,TP interrupt enable" "0,1"
|
|
bitfld.long 0x10 0. "RPIE,RP interrupt enable" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SPI_STAT,Status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CTXSIZE,These bits show the number of data frames remaining in the TXSIZE bit feild (in the SPI_CTL1 register)"
|
|
bitfld.long 0x0 15. "RWNE,The word of RxFIFO is not empty" "0,1"
|
|
bitfld.long 0x0 13.--14. "RPLVL,RxFIFO packet level" "0,1,2,3"
|
|
bitfld.long 0x0 12. "TC,TxFIFO transmission complete flag" "0,1"
|
|
bitfld.long 0x0 11. "SPD,Suspend flag" "0,1"
|
|
bitfld.long 0x0 10. "TXSERF,The additional SPI data has been reloaded" "0,1"
|
|
bitfld.long 0x0 9. "CONFERR,SPI configuration error" "0,1"
|
|
bitfld.long 0x0 8. "FERR,SPI TI format error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CRCERR,SPI CRC error" "0,1"
|
|
bitfld.long 0x0 6. "RXORERR,Reception overrun error" "0,1"
|
|
bitfld.long 0x0 5. "TXURERR,Transmission underrun error" "0,1"
|
|
bitfld.long 0x0 4. "TXF,TxFIFO transmission has been filled" "0,1"
|
|
bitfld.long 0x0 3. "ET,End of transmission/reception flag" "0,1"
|
|
bitfld.long 0x0 2. "DP,Duplex packet" "0,1"
|
|
bitfld.long 0x0 1. "TP,TxFIFO packet space available flag" "0,1"
|
|
bitfld.long 0x0 0. "RP,RxFIFO packet space available flag" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "SPI_STATC,Interrupt/Status flags clear register"
|
|
bitfld.long 0x0 11. "SPDC,Clear the suspend flag" "0,1"
|
|
bitfld.long 0x0 10. "TXSERFC,Clear the TXSERF flag" "0,1"
|
|
bitfld.long 0x0 9. "CONFERRC,Clear the configuration error flag" "0,1"
|
|
bitfld.long 0x0 8. "FERRC,Clear the SPI TI format error flag" "0,1"
|
|
bitfld.long 0x0 7. "CRCERRC,Clear the CRC error flag" "0,1"
|
|
bitfld.long 0x0 6. "RXORERRC,Clear the reception overrun error flag" "0,1"
|
|
bitfld.long 0x0 5. "TXURERRC,Clear the transmission underrun error flag" "0,1"
|
|
bitfld.long 0x0 4. "TXFC,Clear the TxFIFO transmission filled flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ETC,Clear the end of transmission/reception flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "SPI_TDATA,Data Transfer register"
|
|
hexmask.long 0x0 0.--31. 1. "TDATA,Data transfer register"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "SPI_RDATA,Data Receive register"
|
|
hexmask.long 0x0 0.--31. 1. "RDATA,Data receive register"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "SPI_CRCPOLY,CRC polynomial register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x44++0x7
|
|
line.long 0x0 "SPI_TCRC,TX CRC register"
|
|
hexmask.long 0x0 0.--31. 1. "TCRC,Tx CRC register"
|
|
line.long 0x4 "SPI_RCRC,RX CRC register"
|
|
hexmask.long 0x4 0.--31. 1. "RCRC,Rx CRC register"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "SPI_URDATA,Underrun Data register"
|
|
hexmask.long 0x0 0.--31. 1. "URDATA,Transmission underrun data at slave mode"
|
|
line.long 0x4 "SPI_I2SCTL,I2S control register"
|
|
rbitfld.long 0x4 31. "I2SCH,I2S channel side" "0,1"
|
|
bitfld.long 0x4 25. "MCKOEN,I2S_MCK output enable" "0,1"
|
|
bitfld.long 0x4 24. "OF,Odd factor for the prescaler" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "DIV,Dividing factor for the prescaler"
|
|
bitfld.long 0x4 11. "I2SSEL,I2S mode selection" "0,1"
|
|
bitfld.long 0x4 10. "I2SEN,I2S enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "I2SOPMOD,I2S operation mode" "0,1,2,3"
|
|
bitfld.long 0x4 7. "PCMSMOD,PCM frame synchronization mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3"
|
|
bitfld.long 0x4 3. "CKPL,Idle state clock polarity" "0,1"
|
|
bitfld.long 0x4 1.--2. "DTLEN,Data length" "0,1,2,3"
|
|
bitfld.long 0x4 0. "CHLEN,Channel length" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "SPI_QCTL,Quad_SPI mode control register"
|
|
bitfld.long 0x0 2. "IO23_DRV,Drive IO2 and IO3 enable" "0,1"
|
|
bitfld.long 0x0 1. "QRD,Quad-SPI mode read select" "0,1"
|
|
bitfld.long 0x0 0. "QMOD,Quad-SPI mode enable" "0,1"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "SPI_RXDLYCK,RX clock delay register"
|
|
bitfld.long 0x0 11. "MRXDEN,When master receive sampling clock delay enable" "0,1"
|
|
hexmask.long.byte 0x0 6.--10. 1. "MRXD,When master receive sampling clock delay units"
|
|
bitfld.long 0x0 5. "SRXDEN,When slave receive sampling clock delay enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SRXD,When slave receive sampling clock delay units"
|
|
tree.end
|
|
tree "SPI5"
|
|
base ad:0x40013800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "SPI_CTL0,Control register 0"
|
|
rbitfld.long 0x0 16. "IOAFEN,Related IOs AF configuration enable" "0,1"
|
|
bitfld.long 0x0 15. "TXCRCI,The transmitter CRC initialization configuration" "0,1"
|
|
bitfld.long 0x0 14. "RXCRCI,The receiver CRC initialization configuration" "0,1"
|
|
bitfld.long 0x0 13. "CRCFS,Full scale CRC polynomial configuration" "0,1"
|
|
bitfld.long 0x0 12. "NSSI,The input level of internal NSS signal" "0,1"
|
|
bitfld.long 0x0 10. "MSPDR,Suspend request in SPI master mode" "0,1"
|
|
bitfld.long 0x0 9. "MSTART,Master start transfer" "0,1"
|
|
bitfld.long 0x0 8. "MASP,The master is suspended automatically in receive mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI enable" "0,1"
|
|
line.long 0x4 "SPI_CTL1,Control register 1"
|
|
hexmask.long.word 0x4 16.--31. 1. "TXSER,When previous number of data stored in the TXSIZE has been transferred it will reload the transmission expansion data amount in the TXSER to TXSIZE"
|
|
hexmask.long.word 0x4 0.--15. 1. "TXSIZE,The current number of data to transfer"
|
|
line.long 0x8 "SPI_CFG0,Configuration register 0"
|
|
bitfld.long 0x8 28.--30. "PSC,Master clock prescaler selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "WORDEN,Word access mode enable" "0,1"
|
|
bitfld.long 0x8 23. "BYTEN,Byte access mode enable" "0,1"
|
|
bitfld.long 0x8 22. "CRCEN,CRC calculation enable" "0,1"
|
|
hexmask.long.byte 0x8 16.--20. 1. "CRCSZ,CRC size"
|
|
bitfld.long 0x8 15. "DMATEN,Transmit buffer DMA enable" "0,1"
|
|
bitfld.long 0x8 14. "DMAREN,Receive buffer DMA enable" "0,1"
|
|
bitfld.long 0x8 11.--12. "TXURDT,Detection of underrun error at slave transmitter" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 9.--10. "TXUROP,Operation of slave transmitter when underrun detected" "0,1,2,3"
|
|
hexmask.long.byte 0x8 5.--8. 1. "FIFOLVL,FIFO threshold level"
|
|
hexmask.long.byte 0x8 0.--4. 1. "DZ,Date size"
|
|
line.long 0xC "SPI_CFG1,Configuration register 1"
|
|
bitfld.long 0xC 31. "AFCTL,AF GPIOs control" "0,1"
|
|
bitfld.long 0xC 30. "NSSCTL,NSS pin output control in master mode" "0,1"
|
|
bitfld.long 0xC 29. "NSSDRV,NSS pin output enable in master mode" "0,1"
|
|
bitfld.long 0xC 28. "NSSIOPL,NSS pin input/output polarity selection" "0,1"
|
|
bitfld.long 0xC 26. "NSSIM,NSS input signal manage mode" "0,1"
|
|
bitfld.long 0xC 25. "CKPL,Clock polarity selection" "0,1"
|
|
bitfld.long 0xC 24. "CKPH,Clock phase selection" "0,1"
|
|
bitfld.long 0xC 23. "LF,LSB first mode" "0,1"
|
|
newline
|
|
bitfld.long 0xC 22. "MSTMOD,Master mode enable" "0,1"
|
|
bitfld.long 0xC 21. "TMOD,SPI TI mode enable" "0,1"
|
|
bitfld.long 0xC 18. "BDEN,Bidirectional enable" "0,1"
|
|
bitfld.long 0xC 17. "BDOEN,Bidirectional transmit output enable" "0,1"
|
|
bitfld.long 0xC 16. "RO,Receive only" "0,1"
|
|
bitfld.long 0xC 15. "SWPMIO,MOSI and MISO pin swap" "0,1"
|
|
hexmask.long.byte 0xC 4.--7. 1. "MDFD,Delay between the data frames in SPI master mode"
|
|
hexmask.long.byte 0xC 0.--3. 1. "MSSD,Delay between active edge of NSS and start transfer or receive data in SPI master mode"
|
|
line.long 0x10 "SPI_INT,Interrupt register"
|
|
bitfld.long 0x10 10. "TXSERFIE,TXSER reload interrupt enable" "0,1"
|
|
bitfld.long 0x10 9. "CONFEIE,SPI configuration error interrupt enable" "0,1"
|
|
bitfld.long 0x10 8. "FEIE,TI frame error interrupt enable" "0,1"
|
|
bitfld.long 0x10 7. "CRCERIE,CRC error interrupt enable" "0,1"
|
|
bitfld.long 0x10 6. "RXOREIE,Overrun error interrupt enable" "0,1"
|
|
bitfld.long 0x10 5. "TXUREIE,Underrun error interrupt enable" "0,1"
|
|
bitfld.long 0x10 4. "TXFIE,Transmission filled interrupt enable" "0,1"
|
|
bitfld.long 0x10 3. "ESTCIE,End of transfer or suspend or TxFIFO clear interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "DPIE,DP interrupt enable" "0,1"
|
|
bitfld.long 0x10 1. "TPIE,TP interrupt enable" "0,1"
|
|
bitfld.long 0x10 0. "RPIE,RP interrupt enable" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SPI_STAT,Status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CTXSIZE,These bits show the number of data frames remaining in the TXSIZE bit feild (in the SPI_CTL1 register)"
|
|
bitfld.long 0x0 15. "RWNE,The word of RxFIFO is not empty" "0,1"
|
|
bitfld.long 0x0 13.--14. "RPLVL,RxFIFO packet level" "0,1,2,3"
|
|
bitfld.long 0x0 12. "TC,TxFIFO transmission complete flag" "0,1"
|
|
bitfld.long 0x0 11. "SPD,Suspend flag" "0,1"
|
|
bitfld.long 0x0 10. "TXSERF,The additional SPI data has been reloaded" "0,1"
|
|
bitfld.long 0x0 9. "CONFERR,SPI configuration error" "0,1"
|
|
bitfld.long 0x0 8. "FERR,SPI TI format error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CRCERR,SPI CRC error" "0,1"
|
|
bitfld.long 0x0 6. "RXORERR,Reception overrun error" "0,1"
|
|
bitfld.long 0x0 5. "TXURERR,Transmission underrun error" "0,1"
|
|
bitfld.long 0x0 4. "TXF,TxFIFO transmission has been filled" "0,1"
|
|
bitfld.long 0x0 3. "ET,End of transmission/reception flag" "0,1"
|
|
bitfld.long 0x0 2. "DP,Duplex packet" "0,1"
|
|
bitfld.long 0x0 1. "TP,TxFIFO packet space available flag" "0,1"
|
|
bitfld.long 0x0 0. "RP,RxFIFO packet space available flag" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "SPI_STATC,Interrupt/Status flags clear register"
|
|
bitfld.long 0x0 11. "SPDC,Clear the suspend flag" "0,1"
|
|
bitfld.long 0x0 10. "TXSERFC,Clear the TXSERF flag" "0,1"
|
|
bitfld.long 0x0 9. "CONFERRC,Clear the configuration error flag" "0,1"
|
|
bitfld.long 0x0 8. "FERRC,Clear the SPI TI format error flag" "0,1"
|
|
bitfld.long 0x0 7. "CRCERRC,Clear the CRC error flag" "0,1"
|
|
bitfld.long 0x0 6. "RXORERRC,Clear the reception overrun error flag" "0,1"
|
|
bitfld.long 0x0 5. "TXURERRC,Clear the transmission underrun error flag" "0,1"
|
|
bitfld.long 0x0 4. "TXFC,Clear the TxFIFO transmission filled flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ETC,Clear the end of transmission/reception flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "SPI_TDATA,Data Transfer register"
|
|
hexmask.long 0x0 0.--31. 1. "TDATA,Data transfer register"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "SPI_RDATA,Data Receive register"
|
|
hexmask.long 0x0 0.--31. 1. "RDATA,Data receive register"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "SPI_CRCPOLY,CRC polynomial register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x44++0x7
|
|
line.long 0x0 "SPI_TCRC,TX CRC register"
|
|
hexmask.long 0x0 0.--31. 1. "TCRC,Tx CRC register"
|
|
line.long 0x4 "SPI_RCRC,RX CRC register"
|
|
hexmask.long 0x4 0.--31. 1. "RCRC,Rx CRC register"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "SPI_URDATA,Underrun Data register"
|
|
hexmask.long 0x0 0.--31. 1. "URDATA,Transmission underrun data at slave mode"
|
|
line.long 0x4 "SPI_I2SCTL,I2S control register"
|
|
rbitfld.long 0x4 31. "I2SCH,I2S channel side" "0,1"
|
|
bitfld.long 0x4 25. "MCKOEN,I2S_MCK output enable" "0,1"
|
|
bitfld.long 0x4 24. "OF,Odd factor for the prescaler" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "DIV,Dividing factor for the prescaler"
|
|
bitfld.long 0x4 11. "I2SSEL,I2S mode selection" "0,1"
|
|
bitfld.long 0x4 10. "I2SEN,I2S enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "I2SOPMOD,I2S operation mode" "0,1,2,3"
|
|
bitfld.long 0x4 7. "PCMSMOD,PCM frame synchronization mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3"
|
|
bitfld.long 0x4 3. "CKPL,Idle state clock polarity" "0,1"
|
|
bitfld.long 0x4 1.--2. "DTLEN,Data length" "0,1,2,3"
|
|
bitfld.long 0x4 0. "CHLEN,Channel length" "0,1"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "SPI_RXDLYCK,RX clock delay register"
|
|
bitfld.long 0x0 11. "MRXDEN,When master receive sampling clock delay enable" "0,1"
|
|
hexmask.long.byte 0x0 6.--10. 1. "MRXD,When master receive sampling clock delay units"
|
|
bitfld.long 0x0 5. "SRXDEN,When slave receive sampling clock delay enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SRXD,When slave receive sampling clock delay units"
|
|
tree.end
|
|
tree.end
|
|
tree "SYSCFG (System Configuration Controller)"
|
|
base ad:0x58000400
|
|
group.long 0x4++0x17
|
|
line.long 0x0 "PMCFG,Peripheral mode configuration register"
|
|
bitfld.long 0x0 27. "PC3SWON,PC3 switch open" "0,1"
|
|
bitfld.long 0x0 26. "PC2SWON,PC2 switch open" "0,1"
|
|
bitfld.long 0x0 25. "PA1SWON,PA1 switch open" "0,1"
|
|
bitfld.long 0x0 24. "PA0SWON,PA0 switch open" "0,1"
|
|
newline
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x0 23. "ENET0_PHY_SEL,Ethernet0 PHY interface selection" "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
bitfld.long 0x0 22. "ENET1_PHY_SEL,Ethernet1 PHY interface selection" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 7. "PB9FMPEN,PB9 pin Fm+ mode enable" "0,1"
|
|
bitfld.long 0x0 6. "PB8FMPEN,PB8 pin Fm+ mode enable" "0,1"
|
|
bitfld.long 0x0 5. "PB7FMPEN,PB7 pin Fm+ mode enable" "0,1"
|
|
bitfld.long 0x0 4. "PB6FMPEN,PB6 pin Fm+ mode enable" "0,1"
|
|
bitfld.long 0x0 3. "I2C3FMPEN,I2C3 Fm+" "0,1"
|
|
bitfld.long 0x0 2. "I2C2FMPEN,I2C2 Fm+" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C1FMPEN,I2C1 Fm+" "0,1"
|
|
bitfld.long 0x0 0. "I2C0FMPEN,I2C0 Fm+" "0,1"
|
|
line.long 0x4 "EXTISS0,EXTI sources selection register 0"
|
|
hexmask.long.byte 0x4 12.--15. 1. "EXTI3_SS,EXTI 3 sources selection"
|
|
hexmask.long.byte 0x4 8.--11. 1. "EXTI2_SS,EXTI 2 sources selection"
|
|
hexmask.long.byte 0x4 4.--7. 1. "EXTI1_SS,EXTI 1 sources selection"
|
|
hexmask.long.byte 0x4 0.--3. 1. "EXTI0_SS,EXTI 0 sources selection"
|
|
line.long 0x8 "EXTISS1,EXTI sources selection register 1"
|
|
hexmask.long.byte 0x8 12.--15. 1. "EXTI7_SS,EXTI 7 sources selection"
|
|
hexmask.long.byte 0x8 8.--11. 1. "EXTI6_SS,EXTI 6 sources selection"
|
|
hexmask.long.byte 0x8 4.--7. 1. "EXTI5_SS,EXTI 5 sources selection"
|
|
hexmask.long.byte 0x8 0.--3. 1. "EXTI4_SS,EXTI 4 sources selection"
|
|
line.long 0xC "EXTISS2,EXTI sources selection register 2"
|
|
hexmask.long.byte 0xC 12.--15. 1. "EXTI11_SS,EXTI 11 sources selection"
|
|
hexmask.long.byte 0xC 8.--11. 1. "EXTI10_SS,EXTI 10 sources selection"
|
|
hexmask.long.byte 0xC 4.--7. 1. "EXTI9_SS,EXTI 9 sources selection"
|
|
hexmask.long.byte 0xC 0.--3. 1. "EXTI8_SS,EXTI 8 sources selection"
|
|
line.long 0x10 "EXTISS3,EXTI sources selection register 3"
|
|
hexmask.long.byte 0x10 12.--15. 1. "EXTI15_SS,EXTI 15 sources selection"
|
|
hexmask.long.byte 0x10 8.--11. 1. "EXTI14_SS,EXTI 14 sources selection"
|
|
hexmask.long.byte 0x10 4.--7. 1. "EXTI13_SS,EXTI 13 sources selection"
|
|
hexmask.long.byte 0x10 0.--3. 1. "EXTI12_SS,EXTI 12 sources selection"
|
|
line.long 0x14 "LKCTL,Lockup control register"
|
|
bitfld.long 0x14 15. "AXIRAM_LOCK,Region 0 AXI-SRAM ECC double error lock bit" "0,1"
|
|
bitfld.long 0x14 14. "ITCM_LOCK,Region 0 ITCM-RAM ECC double error lock bit" "0,1"
|
|
bitfld.long 0x14 13. "DTCM_LOCK,Region 0 DTCM ECC double error lock bit" "0,1"
|
|
bitfld.long 0x14 12. "SRAM0_LOCK,Region 1 SRAM0 ECC double error lockup bit" "0,1"
|
|
bitfld.long 0x14 11. "SRAM1_LOCK,Region 1 SRAM1 ECC double error lockup bit" "0,1"
|
|
bitfld.long 0x14 7. "BKPRAM_LOCK,Region 2 backup SRAM ECC double error lockup bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "CPU_LOCK,CPU lockup bit" "0,1"
|
|
bitfld.long 0x14 2. "LVD_LOCK,Low voltage detector lockup bit" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CPSCTL,I/O compensation control register"
|
|
rbitfld.long 0x0 23. "IOLV,I/O in low voltage state" "0,1"
|
|
bitfld.long 0x0 16. "IOSPDOP,I/O speed optimization High-speed at low-voltage" "0,1"
|
|
rbitfld.long 0x0 8. "CPS_RDY,Compensation cell ready flag" "0,1"
|
|
bitfld.long 0x0 0. "CPS_EN,I/O compensation cell enable" "0,1"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "CPSCCCFG,I/O compensation cell code configuration register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PCPSCC,PMOS compensation cell code"
|
|
hexmask.long.byte 0x0 0.--3. 1. "NCPSCC,NMOS compensation cell code"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "TIMERCISEL0,Timer input selection register 0"
|
|
hexmask.long.byte 0x0 28.--31. 1. "TIMER0_CI3_SEL,Selects TIMER0_CI3 input selection"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TIMER0_CI2_SEL,Selects TIMER0_CI2 input selection"
|
|
hexmask.long.byte 0x0 20.--23. 1. "TIMER0_CI1_SEL,Selects TIMER0_CI1 input selection"
|
|
hexmask.long.byte 0x0 16.--19. 1. "TIMER0_CI0_SEL,Selects TIMER0_CI0 input selection"
|
|
hexmask.long.byte 0x0 12.--15. 1. "TIMER7_CI3_SEL,Selects TIMER7_CI3 input selection"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TIMER7_CI2_SEL,Selects TIMER7_CI2 input selection"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "TIMER7_CI1_SEL,Selects TIMER7_CI1 input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TIMER7_CI0_SEL,Selects TIMER7_CI0 input selection"
|
|
line.long 0x4 "TIMERCISEL1,Timer input selection register 1"
|
|
hexmask.long.byte 0x4 28.--31. 1. "TIMER1_CI3_SEL,TIMER1_CI3 input selection"
|
|
hexmask.long.byte 0x4 24.--27. 1. "TIMER1_CI2_SEL,TIMER1_CI2 input selection"
|
|
hexmask.long.byte 0x4 20.--23. 1. "TIMER1_CI1_SEL,TIMER1_CI1 input selection"
|
|
hexmask.long.byte 0x4 16.--19. 1. "TIMER1_CI0_SEL,TIMER1_CI0 input selection"
|
|
hexmask.long.byte 0x4 12.--15. 1. "TIMER2_CI3_SEL,TIMER2_CI3 input selection"
|
|
hexmask.long.byte 0x4 8.--11. 1. "TIMER2_CI2_SEL,TIMER2_CI2 input selection"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "TIMER2_CI1_SEL,TIMER2_CI1 input selection"
|
|
hexmask.long.byte 0x4 0.--3. 1. "TIMER2_CI0_SEL,TIMER2_CI0 input selection"
|
|
line.long 0x8 "TIMERCISEL2,Timer input selection register 2"
|
|
hexmask.long.byte 0x8 28.--31. 1. "TIMER3_CI3_SEL,TIMER3_CI3 input selection"
|
|
hexmask.long.byte 0x8 24.--27. 1. "TIMER3_CI2_SEL,TIMER3_CI2 input selection"
|
|
hexmask.long.byte 0x8 20.--23. 1. "TIMER3_CI1_SEL,TIMER3_CI1 input selection"
|
|
hexmask.long.byte 0x8 16.--19. 1. "TIMER3_CI0_SEL,TIMER3_CI0 input selection"
|
|
hexmask.long.byte 0x8 12.--15. 1. "TIMER4_CI3_SEL,TIMER4_CI3 input selection"
|
|
hexmask.long.byte 0x8 8.--11. 1. "TIMER4_CI2_SEL,TIMER4_CI2 input selection"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "TIMER4_CI1_SEL,TIMER4_CI1 input selection"
|
|
hexmask.long.byte 0x8 0.--3. 1. "TIMER4_CI0_SEL,TIMER4_CI0 input selection"
|
|
line.long 0xC "TIMERCISEL3,Timer input selection register 3"
|
|
hexmask.long.byte 0xC 28.--31. 1. "TIMER22_CI3_SEL,TIMER22_CI3 input selection"
|
|
hexmask.long.byte 0xC 24.--27. 1. "TIMER22_CI2_SEL,TIMER22_CI2 input selection"
|
|
hexmask.long.byte 0xC 20.--23. 1. "TIMER22_CI1_SEL,TIMER22_CI1 input selection"
|
|
hexmask.long.byte 0xC 16.--19. 1. "TIMER22_CI0_SEL,TIMER22_CI0 input selection"
|
|
hexmask.long.byte 0xC 12.--15. 1. "TIMER23_CI3_SEL,TIMER23_CI3 input selection"
|
|
hexmask.long.byte 0xC 8.--11. 1. "TIMER23_CI2_SEL,TIMER23_CI2 input selection"
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "TIMER23_CI1_SEL,TIMER23_CI1 input selection"
|
|
hexmask.long.byte 0xC 0.--3. 1. "TIMER23_CI0_SEL,TIMER23_CI0 input selection"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "TIMERCISEL4,Timer input selection register 4"
|
|
hexmask.long.byte 0x0 28.--31. 1. "TIMER30_CI3_SEL,TIMER30_CI3 input selection"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TIMER30_CI2_SEL,TIMER30_CI2 input selection"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "TIMER30_CI1_SEL,TIMER30_CI1 input selection"
|
|
hexmask.long.byte 0x0 16.--19. 1. "TIMER30_CI0_SEL,TIMER30_CI0 input selection"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "TIMER31_CI3_SEL,TIMER31_CI3 input selection"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TIMER31_CI2_SEL,TIMER31_CI2 input selection"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "TIMER31_CI1_SEL,TIMER31_CI1 input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TIMER31_CI0_SEL,TIMER31_CI0 input selection"
|
|
endif
|
|
group.long 0x48++0x7
|
|
line.long 0x0 "TIMERCISEL5,Timer input selection register 5"
|
|
hexmask.long.byte 0x0 28.--31. 1. "TIMER42_CI1_SEL,Selects TIMER42_CI1 input"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TIMER42_CI0_SEL,Selects TIMER42_CI0 input"
|
|
hexmask.long.byte 0x0 20.--23. 1. "TIMER41_CI1_SEL,Selects TIMER41_CI1 input"
|
|
hexmask.long.byte 0x0 16.--19. 1. "TIMER41_CI0_SEL,Selects TIMER41_CI0 input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "TIMER40_CI1_SEL,Selects TIMER40_CI1 input"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TIMER40_CI0_SEL,Selects TIMER40_CI0 input"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "TIMER14_CI1_SEL,Selects TIMER14_CI1 input"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TIMER14_CI0_SEL,Selects TIMER14_CI0 input"
|
|
line.long 0x4 "TIMERCISEL6,Timer input selection register 6"
|
|
hexmask.long.byte 0x4 20.--23. 1. "TIMER44_CI1_SEL,Selects TIMER44_CI1 input"
|
|
hexmask.long.byte 0x4 16.--19. 1. "TIMER44_CI0_SEL,Selects TIMER44_CI0 input"
|
|
hexmask.long.byte 0x4 12.--15. 1. "TIMER43_CI1_SEL,Selects TIMER43_CI1 input"
|
|
hexmask.long.byte 0x4 8.--11. 1. "TIMER43_CI0_SEL,Selects TIMER43_CI0 input"
|
|
hexmask.long.byte 0x4 4.--7. 1. "TIMER16_CI0_SEL,Selects TIMER16_CI0 input"
|
|
hexmask.long.byte 0x4 0.--3. 1. "TIMER15_CI0_SEL,Selects TIMER15_CI0 input"
|
|
rgroup.long 0x54++0x7
|
|
line.long 0x0 "CPUICAC,CPU ICACHE error status registe"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CPU_ICDET,The ICACHE error detection information"
|
|
hexmask.long.tbyte 0x0 6.--27. 1. "CPU_ICERR,The ICACHE error bank information"
|
|
line.long 0x4 "CPUDCAC,CPU DCACHE error status register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "CPU_DCDET,The DCACHE error detection information"
|
|
hexmask.long.tbyte 0x4 6.--27. 1. "CPU_DCERR,The DCACHE error bank information"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "FPUINTEN,FPU interrupt enable register"
|
|
bitfld.long 0x0 5. "IXIE,Inexact interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 4. "IDIE,Input denormal interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 3. "OVFIE,Overflow interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 2. "UFIE,Underflow interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 1. "DZIE,Divide by 0 interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 0. "IOPIZ,Invalid operation interrupt enable bit" "0,1"
|
|
group.long 0x64++0x7
|
|
line.long 0x0 "SRAMCFG0,SYSCFG SRAM configuration register 0"
|
|
bitfld.long 0x0 0.--1. "SECURE_SRAM_SIZE,These bits indicate the size of secure sram" "0,1,2,3"
|
|
line.long 0x4 "SRAMCFG1,SYSCFG SRAM configuration register 1"
|
|
bitfld.long 0x4 0. "TCM_WAITSTATE,TCM wait state configuration" "0,1"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "TIMER0CFG0,TIMER0 configuration register 0"
|
|
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
|
|
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG2,Quadrature decoder mode 2 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG1,Quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG0,Quadrature decoder mode 0 configuration"
|
|
group.long 0x10C++0x3
|
|
line.long 0x0 "TIMER1CFG0,TIMER1 configuration register 0"
|
|
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
|
|
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG2,Quadrature decoder mode 2 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG1,Quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG0,Quadrature decoder mode 0 configuration"
|
|
group.long 0x118++0x3
|
|
line.long 0x0 "TIMER2CFG0,TIMER2 configuration register 0"
|
|
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
|
|
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG2,Quadrature decoder mode 2 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG1,Quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG0,Quadrature decoder mode 0 configuration"
|
|
group.long 0x124++0x3
|
|
line.long 0x0 "TIMER3CFG0,TIMER3 configuration register 0"
|
|
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
|
|
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG2,Quadrature decoder mode 2 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG1,Quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG0,Quadrature decoder mode 0 configuration"
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "TIMER4CFG0,TIMER4 configuration register 0"
|
|
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
|
|
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG2,Quadrature decoder mode 2 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG1,Quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG0,Quadrature decoder mode 0 configuration"
|
|
group.long 0x13C++0x3
|
|
line.long 0x0 "TIMER7CFG0,TIMER7 configuration register 0"
|
|
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
|
|
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG2,Quadrature decoder mode 2 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG1,Quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG0,Quadrature decoder mode 0 configuration"
|
|
group.long 0x148++0x3
|
|
line.long 0x0 "TIMER14CFG0,TIMER14 configuration register 0"
|
|
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
|
|
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
|
|
group.long 0x154++0x3
|
|
line.long 0x0 "TIMER22CFG0,TIMER22 configuration register 0"
|
|
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
|
|
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG2,Quadrature decoder mode 2 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG1,Quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG0,Quadrature decoder mode 0 configuration"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "TIMER23CFG0,TIMER23 configuration register 0"
|
|
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
|
|
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG2,Quadrature decoder mode 2 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG1,Quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG0,Quadrature decoder mode 0 configuration"
|
|
group.long 0x16C++0x3
|
|
line.long 0x0 "TIMER30CFG0,TIMER30 configuration register 0"
|
|
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
|
|
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG2,Quadrature decoder mode 2 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG1,Quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG0,Quadrature decoder mode 0 configuration"
|
|
group.long 0x178++0x3
|
|
line.long 0x0 "TIMER31CFG0,TIMER31 configuration register 0"
|
|
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
|
|
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG2,Quadrature decoder mode 2 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG1,Quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG0,Quadrature decoder mode 0 configuration"
|
|
group.long 0x184++0x3
|
|
line.long 0x0 "TIMER40CFG0,TIMER40 configuration register 0"
|
|
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
|
|
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
|
|
group.long 0x190++0x3
|
|
line.long 0x0 "TIMER41CFG0,TIMER41 configuration register 0"
|
|
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
|
|
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
|
|
group.long 0x19C++0x3
|
|
line.long 0x0 "TIMER42CFG0,TIMER42 configuration register 0"
|
|
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
|
|
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
|
|
group.long 0x1A8++0x3
|
|
line.long 0x0 "TIMER43CFG0,TIMER43 configuration register 0"
|
|
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
|
|
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
|
|
group.long 0x1B4++0x3
|
|
line.long 0x0 "TIMER44CFG0,TIMER44 configuration register 0"
|
|
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
|
|
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
|
|
group.long 0x104++0x3
|
|
line.long 0x0 "TIMER0CFG1,TIMER0 configuration register 1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG9,Non-quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG8,Non-quadrature decoder mode 0 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG7,Restart or event mode configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "TIMER1CFG1,TIMER1 configuration register 1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG9,Non-quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG8,Non-quadrature decoder mode 0 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG7,Restart or event mode configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
|
|
group.long 0x11C++0x3
|
|
line.long 0x0 "TIMER2CFG1,TIMER2 configuration register 1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG9,Non-quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG8,Non-quadrature decoder mode 0 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG7,Restart or event mode configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "TIMER3CFG1,TIMER3 configuration register 1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG9,Non-quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG8,Non-quadrature decoder mode 0 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG7,Restart or event mode configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
|
|
group.long 0x134++0x3
|
|
line.long 0x0 "TIMER4CFG1,TIMER4 configuration register 1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG9,Non-quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG8,Non-quadrature decoder mode 0 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG7,Restart or event mode configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "TIMER7CFG1,TIMER7 configuration register 1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG9,Non-quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG8,Non-quadrature decoder mode 0 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG7,Restart or event mode configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
|
|
group.long 0x14C++0x3
|
|
line.long 0x0 "TIMER14CFG1,TIMER14 configuration register 1"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG7,Restart or event mode configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
|
|
group.long 0x158++0x3
|
|
line.long 0x0 "TIMER22CFG1,TIMER22 configuration register 1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG9,Non-quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG8,Non-quadrature decoder mode 0 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG7,Restart or event mode configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
|
|
group.long 0x164++0x3
|
|
line.long 0x0 "TIMER23CFG1,TIMER23 configuration register 1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG9,Non-quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG8,Non-quadrature decoder mode 0 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG7,Restart or event mode configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
|
|
group.long 0x170++0x3
|
|
line.long 0x0 "TIMER30CFG1,TIMER30 configuration register 1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG9,Non-quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG8,Non-quadrature decoder mode 0 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG7,Restart or event mode configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
|
|
group.long 0x17C++0x3
|
|
line.long 0x0 "TIMER31CFG1,TIMER31 configuration register 1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG9,Non-quadrature decoder mode 1 configuration"
|
|
hexmask.long.byte 0x0 10.--14. 1. "TSCFG8,Non-quadrature decoder mode 0 configuration"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG7,Restart or event mode configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
|
|
group.long 0x188++0x3
|
|
line.long 0x0 "TIMER40CFG1,TIMER40 configuration register 1"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG7,Restart or event mode configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
|
|
group.long 0x194++0x3
|
|
line.long 0x0 "TIMER41CFG1,TIMER41 configuration register 1"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG7,Restart or event mode configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x0 "TIMER42CFG1,TIMER42 configuration register 1"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG7,Restart or event mode configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
|
|
group.long 0x1AC++0x3
|
|
line.long 0x0 "TIMER43CFG1,TIMER43 configuration register 1"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG7,Restart or event mode configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
|
|
group.long 0x1B8++0x3
|
|
line.long 0x0 "TIMER44CFG1,TIMER44 configuration register 1"
|
|
hexmask.long.byte 0x0 5.--9. 1. "TSCFG7,Restart or event mode configuration"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "TIMER0CFG2,TIMER0 configuration register 2"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
|
|
group.long 0x114++0x3
|
|
line.long 0x0 "TIMER1CFG2,TIMER1 configuration register 2"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "TIMER2CFG2,TIMER2 configuration register 2"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
|
|
group.long 0x12C++0x3
|
|
line.long 0x0 "TIMER3CFG2,TIMER3 configuration register 2"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
|
|
group.long 0x138++0x3
|
|
line.long 0x0 "TIMER4CFG2,TIMER4 configuration register 2"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
|
|
group.long 0x144++0x3
|
|
line.long 0x0 "TIMER7CFG2,TIMER7 configuration register 2"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
|
|
group.long 0x150++0x3
|
|
line.long 0x0 "TIMER14CFG2,TIMER14 configuration register 2"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
|
|
group.long 0x15C++0x3
|
|
line.long 0x0 "TIMER22CFG2,TIMER22 configuration register 2"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
|
|
group.long 0x168++0x3
|
|
line.long 0x0 "TIMER23CFG2,TIMER23 configuration register 2"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
|
|
group.long 0x174++0x3
|
|
line.long 0x0 "TIMER30CFG2,TIMER30 configuration register 2"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "TIMER31CFG2,TIMER31 configuration register 2"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
|
|
group.long 0x18C++0x3
|
|
line.long 0x0 "TIMER40CFG2,TIMER40 configuration register 2"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
|
|
group.long 0x198++0x3
|
|
line.long 0x0 "TIMER41CFG2,TIMER41 configuration register 2"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
|
|
group.long 0x1A4++0x3
|
|
line.long 0x0 "TIMER42CFG2,TIMER42 configuration register 2"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
|
|
group.long 0x1B0++0x3
|
|
line.long 0x0 "TIMER43CFG2,TIMER43 configuration register 2"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
|
|
group.long 0x1BC++0x3
|
|
line.long 0x0 "TIMER44CFG2,TIMER44 configuration register 2"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
|
|
rgroup.long 0x300++0x3
|
|
line.long 0x0 "USERCFG0,User configuration register 0"
|
|
bitfld.long 0x0 4.--6. "BOOT_MODE,Boot mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--1. "BORLEV,BOR Brownout reset threshold level" "0,1,2,3"
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rgroup.long 0x304++0x3
|
|
line.long 0x0 "USERCFG1,User configuration register 1"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ANA_VERSION,The analog version signal"
|
|
endif
|
|
tree.end
|
|
tree "TIMER (Timer)"
|
|
base ad:0x0
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
tree "TIMER30"
|
|
base ad:0x4000E800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
line.long 0x8 "SMCFG,Slave mode configuration register"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "SMC1,Part of SMC is used to enable external clock mode 1" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETFC,External trigger filter control"
|
|
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
|
|
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0xC 31. "CH3COMADDIE,Channel 3 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 30. "CH2COMADDIE,Channel 2 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 17. "DECDISIE,Quadrature decoder signal disconnection interrupt enable" "0,1"
|
|
bitfld.long 0xC 16. "DECJIE,Quadrature decoder signal jump (the two signals jump at the same time)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CH3DEN,Channel 3 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 11. "CH2DEN,Channel 2 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CH3IE,Channel 3 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CH2IE,Channel 2 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "INTF,Interrupt flag register"
|
|
bitfld.long 0x10 31. "CH3COMADDIF,Channel 3 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 30. "CH2COMADDIF,Channel 2 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "DECDISIF,Quadrature decoder signal disconnection interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "DECJIF,Quadrature decoder signal jump (the two signals jump at the same time)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CH3OF,Channel 3 over capture flag" "0,1"
|
|
bitfld.long 0x10 11. "CH2OF,Channel 2 over capture flag" "0,1"
|
|
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
|
|
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CH3IF,Channel 3 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CH2IF,Channel 2 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 31. "CH3COMADDG,Channel 3 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 30. "CH2COMADDG,Channel 2 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
|
|
bitfld.long 0x0 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output mode)"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input mode)"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL1_Output,Channel control register 1 (output mode)"
|
|
bitfld.long 0x4 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x4 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
bitfld.long 0x4 29. "CH3COMADDSEN,Channel 3 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 28. "CH2COMADDSEN,Channel 2 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 24. "CH3COMCTL_3,BIT 3 of channel 3 compare output control" "0,1"
|
|
bitfld.long 0x4 23. "CH2COMCTL_3,BIT 3 of channel 2 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
bitfld.long 0x4 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CHCTL1_Input,Channel control register 1 (input mode)"
|
|
bitfld.long 0x0 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x0 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH3CAPFLT,Channel 3 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH2CAPFLT,Channel 2 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x4 15. "CH3NP,Multi mode channel 3 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 13. "CH3P,Channel 3 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 12. "CH3EN,Channel 3 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 11. "CH2NP,Multi mode channel 2 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 9. "CH2P,Channel 2 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 8. "CH2EN,Channel 2 capture/compare function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CH1NP,Multi mode channel 1 output polarity" "0,1"
|
|
bitfld.long 0x4 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 3. "CH0NP,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x4 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
rbitfld.long 0x8 31. "UPIFBU,UPIF bit backup" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,current counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0x10 "CAR,Counter auto reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CARL,Counter auto reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
|
|
line.long 0x4 "CH1CV,Channel 1 capture/compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CH1VAL,Capture or compare value of channel1"
|
|
line.long 0x8 "CH2CV,Channel 2 capture/compare value register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CH2VAL,Capture or compare value of channel 2"
|
|
line.long 0xC "CH3CV,Channel 3 capture/compare value register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CH3VAL,Capture or compare value of channel 3"
|
|
group.long 0x64++0x13
|
|
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
|
|
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
|
|
line.long 0x8 "CH2COMV_ADD,Channel 2 additional compare value register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CH2COMVAL_ADD,Additional compare value of channel 2"
|
|
line.long 0xC "CH3COMV_ADD,Channel 3 additional compare value register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CH3COMVAL_ADD,Additional compare value of channel 3"
|
|
line.long 0x10 "CTL2,Control register 2"
|
|
bitfld.long 0x10 31. "CH3CPWMEN,Channel 3 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 30. "CH2CPWMEN,Channel 2 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
|
|
bitfld.long 0x10 18. "DECJDEN,Quadrature decoder signal jump detection enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14.--15. "CH3OMPSEL,Channel 3 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "CH2OMPSEL,Channel 2 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "WDGPER,Watchdog counter register"
|
|
hexmask.long 0x0 0.--31. 1. "WDGPER,Watchdog timeout count"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
tree.end
|
|
tree "TIMER31"
|
|
base ad:0x4000EC00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
line.long 0x8 "SMCFG,Slave mode configuration register"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "SMC1,Part of SMC is used to enable external clock mode 1" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETFC,External trigger filter control"
|
|
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
|
|
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0xC 31. "CH3COMADDIE,Channel 3 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 30. "CH2COMADDIE,Channel 2 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 17. "DECDISIE,Quadrature decoder signal disconnection interrupt enable" "0,1"
|
|
bitfld.long 0xC 16. "DECJIE,Quadrature decoder signal jump (the two signals jump at the same time)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CH3DEN,Channel 3 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 11. "CH2DEN,Channel 2 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CH3IE,Channel 3 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CH2IE,Channel 2 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "INTF,Interrupt flag register"
|
|
bitfld.long 0x10 31. "CH3COMADDIF,Channel 3 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 30. "CH2COMADDIF,Channel 2 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "DECDISIF,Quadrature decoder signal disconnection interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "DECJIF,Quadrature decoder signal jump (the two signals jump at the same time)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CH3OF,Channel 3 over capture flag" "0,1"
|
|
bitfld.long 0x10 11. "CH2OF,Channel 2 over capture flag" "0,1"
|
|
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
|
|
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CH3IF,Channel 3 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CH2IF,Channel 2 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 31. "CH3COMADDG,Channel 3 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 30. "CH2COMADDG,Channel 2 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
|
|
bitfld.long 0x0 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output mode)"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input mode)"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL1_Output,Channel control register 1 (output mode)"
|
|
bitfld.long 0x4 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x4 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
bitfld.long 0x4 29. "CH3COMADDSEN,Channel 3 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 28. "CH2COMADDSEN,Channel 2 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 24. "CH3COMCTL_3,BIT 3 of channel 3 compare output control" "0,1"
|
|
bitfld.long 0x4 23. "CH2COMCTL_3,BIT 3 of channel 2 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
bitfld.long 0x4 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CHCTL1_Input,Channel control register 1 (input mode)"
|
|
bitfld.long 0x0 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x0 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH3CAPFLT,Channel 3 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH2CAPFLT,Channel 2 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x4 15. "CH3NP,Multi mode channel 3 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 13. "CH3P,Channel 3 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 12. "CH3EN,Channel 3 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 11. "CH2NP,Multi mode channel 2 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 9. "CH2P,Channel 2 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 8. "CH2EN,Channel 2 capture/compare function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CH1NP,Multi mode channel 1 output polarity" "0,1"
|
|
bitfld.long 0x4 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 3. "CH0NP,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x4 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
rbitfld.long 0x8 31. "UPIFBU,UPIF bit backup" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,current counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0x10 "CAR,Counter auto reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CARL,Counter auto reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
|
|
line.long 0x4 "CH1CV,Channel 1 capture/compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CH1VAL,Capture or compare value of channel1"
|
|
line.long 0x8 "CH2CV,Channel 2 capture/compare value register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CH2VAL,Capture or compare value of channel 2"
|
|
line.long 0xC "CH3CV,Channel 3 capture/compare value register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CH3VAL,Capture or compare value of channel 3"
|
|
group.long 0x64++0x13
|
|
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
|
|
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
|
|
line.long 0x8 "CH2COMV_ADD,Channel 2 additional compare value register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CH2COMVAL_ADD,Additional compare value of channel 2"
|
|
line.long 0xC "CH3COMV_ADD,Channel 3 additional compare value register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CH3COMVAL_ADD,Additional compare value of channel 3"
|
|
line.long 0x10 "CTL2,Control register 2"
|
|
bitfld.long 0x10 31. "CH3CPWMEN,Channel 3 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 30. "CH2CPWMEN,Channel 2 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
|
|
bitfld.long 0x10 18. "DECJDEN,Quadrature decoder signal jump detection enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14.--15. "CH3OMPSEL,Channel 3 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "CH2OMPSEL,Channel 2 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "WDGPER,Watchdog counter register"
|
|
hexmask.long 0x0 0.--31. 1. "WDGPER,Watchdog timeout count"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "TIMER0"
|
|
base ad:0x40010000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 30.--31. "CCUC,Commutation control shadow register update control" "0,1,2,3"
|
|
bitfld.long 0x4 20.--22. "MMC1,Master mode control 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 15. "ISO3N,Idle state of multi mode channel 3 complementary output" "0,1"
|
|
bitfld.long 0x4 14. "ISO3,Idle state of channel 3 output" "0,1"
|
|
bitfld.long 0x4 13. "ISO2N,Idle state of multi mode channel 2 complementary output" "0,1"
|
|
bitfld.long 0x4 12. "ISO2,Idle state of channel 2 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ISO1N,Idle state of multi mode channel 1 complementary output" "0,1"
|
|
bitfld.long 0x4 10. "ISO1,Idle state of channel 1 output" "0,1"
|
|
bitfld.long 0x4 9. "ISO0N,Idle state of multi mode channel 0 complementary output" "0,1"
|
|
bitfld.long 0x4 8. "ISO0,Idle state of channel 0 output" "0,1"
|
|
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
line.long 0x8 "SMCFG,Slave mode configuration register"
|
|
bitfld.long 0x8 31. "TRGS_3,Bit 3 of trigger selection" "0,1"
|
|
bitfld.long 0x8 16. "SMC_3,Bit 3 of slave mode control" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "SMC1,Part of SMC is used to enable external clock mode 1" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETFC,External trigger filter control"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TRGS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0.--2. "SMC,Slave mode control" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0xC 31. "CH3COMADDIE,Channel 3 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 30. "CH2COMADDIE,Channel 2 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 27. "MCH3DEN,Multi mode channel 3 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 26. "MCH2DEN,Multi mode channel 2 capture/compare DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "MCH1DEN,Multi mode channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 24. "MCH0DEN,Multi mode channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 23. "MCH3IE,Multi mode channel 3 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 22. "MCH2IE,Multi mode channel 2 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 21. "MCH1IE,Multi mode channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 20. "MCH0IE,Multi mode channel 0 capture/compare interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
|
|
bitfld.long 0xC 18. "DECJDEN,Quadrature decoder signal jump (the two signals jump at the same time) detection enable" "0,1"
|
|
bitfld.long 0xC 17. "DECDISIE,Quadrature decoder signal disconnection interrupt enable" "0,1"
|
|
bitfld.long 0xC 16. "DECJIE,Quadrature decoder signal jump (the two signals jump at the same time) interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "CMTDEN,Commutation DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "CH3DEN,Channel 3 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 11. "CH2DEN,Channel 2 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BRKIE,Break interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "CMTIE,Commutation interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CH3IE,Channel 3 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CH2IE,Channel 2 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "INTF,Interrupt flag register"
|
|
bitfld.long 0x10 31. "CH3COMADDIF,Channel 3 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 30. "CH2COMADDIF,Channel 2 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 27. "MCH3OF,Multi mode channel 3 over capture flag" "0,1"
|
|
bitfld.long 0x10 26. "MCH2OF,Multi mode channel 2 over capture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "MCH1OF,Multi mode channel 1 over capture flag" "0,1"
|
|
bitfld.long 0x10 24. "MCH0OF,Multi mode channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 23. "MCH3IF,Multi mode channel 3 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 22. "MCH2IF,Multi mode channel 2 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 21. "MCH1IF,Multi mode channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 20. "MCH0IF,Multi mode channel 0 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "DECDISIF,Quadrature decoder signal disconnection interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "DECJIF,Quadrature decoder signal jump (the two signals jump at the same time) interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SYSBIF,SYSBIF" "0,1"
|
|
bitfld.long 0x10 12. "CH3OF,Channel 3 over capture flag" "0,1"
|
|
bitfld.long 0x10 11. "CH2OF,Channel 2 over capture flag" "0,1"
|
|
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 8. "BRK1IF,Break1 interrupt flag" "0,1"
|
|
bitfld.long 0x10 7. "BRK0IF,Break0 interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 5. "CMTIF,Channel commutation interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CH3IF,Channel 3 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CH2IF,Channel 2 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 31. "CH3COMADDG,Channel 3 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 30. "CH2COMADDG,Channel 2 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 23. "MCH3G,Multi mode channel 3 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 22. "MCH2G,Multi mode channel 2 capture or compare event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MCH1G,Multi mode channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 20. "MCH0G,Multi mode channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 8. "BRK1G,Break1 event generation" "0,1"
|
|
bitfld.long 0x0 7. "BRK0G,Break0 event generation" "0,1"
|
|
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
|
|
bitfld.long 0x0 5. "CMTG,Channel commutation event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL1_Output,Channel control register 1 (output"
|
|
bitfld.long 0x4 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x4 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
bitfld.long 0x4 29. "CH3COMADDSEN,Channel 3 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 28. "CH2COMADDSEN,Channel 2 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 24. "CH3COMCTL_3,BIT 3 of channel 3 compare output control" "0,1"
|
|
bitfld.long 0x4 23. "CH2COMCTL_3,BIT 3 of channel 2 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
bitfld.long 0x4 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
|
|
group.long 0x1C++0x2F
|
|
line.long 0x0 "CHCTL1_Input,Channel control register 1 (input"
|
|
bitfld.long 0x0 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x0 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH3CAPFLT,Channel 3 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH2CAPFLT,Channel 2 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x4 15. "MCH3P,Multi mode channel 3 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 14. "MCH3EN,Multi mode channel 3 capture/compare enable" "0,1"
|
|
bitfld.long 0x4 13. "CH3P,Channel 3 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 12. "CH3EN,Channel 3 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 11. "MCH2P,Multi mode channel 2 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 10. "MCH2EN,Multi mode channel 2 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CH2P,Channel 2 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 8. "CH2EN,Channel 2 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 7. "MCH1P,Multi mode channel 1 output polarity" "0,1"
|
|
bitfld.long 0x4 6. "MCH1EN,Multi mode channel 1 output enable" "0,1"
|
|
bitfld.long 0x4 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MCH0P,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x4 2. "MCH0EN,Multi mode channel 0 capture/compare enable" "0,1"
|
|
bitfld.long 0x4 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
bitfld.long 0x8 31. "UPIFBU,UPIF bit backup" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,current counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0x10 "CAR,Counter auto reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CARL,Counter auto reload value"
|
|
line.long 0x14 "CREP0,Counter repetition register"
|
|
hexmask.long.byte 0x14 0.--7. 1. "CREP0,Counter repetition value"
|
|
line.long 0x18 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
|
|
line.long 0x1C "CH1CV,Channel 1 capture/compare value register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CH1VAL,Capture or compare value of channel1"
|
|
line.long 0x20 "CH2CV,Channel 2 capture/compare value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "CH2VAL,Capture or compare value of channel 2"
|
|
line.long 0x24 "CH3CV,Channel 3 capture/compare value register"
|
|
hexmask.long.word 0x24 0.--15. 1. "CH3VAL,Capture or compare value of channel 3"
|
|
line.long 0x28 "CCHP,channel complementary protection register"
|
|
bitfld.long 0x28 29. "BRK1LK,BREAK1 input locked" "0,1"
|
|
bitfld.long 0x28 28. "BRK0LK,BREAK0 input locked" "0,1"
|
|
bitfld.long 0x28 27. "BRK1REL,BREAK1 input released" "0,1"
|
|
bitfld.long 0x28 26. "BRK0REL,BREAK0 input released" "0,1"
|
|
bitfld.long 0x28 25. "BRK1P,BREAK1 input signal polarity" "0,1"
|
|
bitfld.long 0x28 24. "BRK1EN,BREAK1 input signal enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x28 20.--23. 1. "BRK1F,BREAK1 input signal filter"
|
|
hexmask.long.byte 0x28 16.--19. 1. "BRK0F,BREAK0 input signal filter"
|
|
bitfld.long 0x28 15. "POEN,Primary output enable" "0,1"
|
|
bitfld.long 0x28 14. "OAEN,Output automatic enable" "0,1"
|
|
bitfld.long 0x28 13. "BRK0P,BREAK0 input signal polarity" "0,1"
|
|
bitfld.long 0x28 12. "BRK0EN,BREAK0 input signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x28 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x28 10. "IOS,Idle mode off-state configure" "0,1"
|
|
bitfld.long 0x28 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0x2C "MCHCTL0_Output,Multi mode channel control register 0 (output"
|
|
bitfld.long 0x2C 31. "MCH1MS_2,Multi mode channel 1 I/O mode selection" "0,1"
|
|
bitfld.long 0x2C 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
bitfld.long 0x2C 15. "MCH1COMCEN,Multi mode channel 1 output compare clear enable" "0,1"
|
|
bitfld.long 0x2C 12.--14. "MCH1COMCTL,Multi mode channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 11. "MCH1COMSEN,Multi mode channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x2C 8.--9. "MCH1MS,Multi mode channel 1 I/O mode selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2C 7. "MCH0COMCEN,Multi mode channel 0 output compare clear enable" "0,1"
|
|
bitfld.long 0x2C 4.--6. "MCH0COMCTL,Multi mode channel 0 output compare control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 3. "MCH0COMSEN,Multi mode channel 0 output compare shadow enable" "0,1"
|
|
bitfld.long 0x2C 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x48++0x7
|
|
line.long 0x0 "MCHCTL0_Input,Multi mode channel control register 0 (input"
|
|
bitfld.long 0x0 31. "MCH1MS_2,Multi mode channel 1 I/O mode selection" "0,1"
|
|
bitfld.long 0x0 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MCH1CAPFLT,Multi mode channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "MCH1CAPPSC,Multi mode channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MCH1MS,Multi mode channel 1 I/O mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MCH0CAPFLT,Multi mode channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MCH0CAPPSC,Multi mode channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
line.long 0x4 "MCHCTL1_Output,Multi mode channel control register 1 (output"
|
|
bitfld.long 0x4 31. "MCH3MS_2,2th bit of MCH3MS" "0,1"
|
|
bitfld.long 0x4 30. "MCH2MS_2,2th bit of MCH2MS" "0,1"
|
|
bitfld.long 0x4 15. "MCH3COMCEN,Multi mode channel 3 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "MCH3COMCTL,Multi mode channel 3 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "MCH3COMSEN,Multi mode channel 3 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "MCH3MS,Multi mode channel 3 I/O mode selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 7. "MCH2COMCEN,Multi mode channel 2 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "MCH2COMCTL,Multi mode channel 2 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "MCH2COMSEN,Multi mode channel 2 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "MCH2MS,Multi mode channel 2 I/O mode selection" "0,1,2,3"
|
|
group.long 0x4C++0x2B
|
|
line.long 0x0 "MCHCTL1_Input,Multi mode channel control register 1(input"
|
|
bitfld.long 0x0 31. "MCH3MS_2,2th bit of MCH3MS" "0,1"
|
|
bitfld.long 0x0 30. "MCH2MS_2,2th bit of MCH2MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MCH3CAPFLT,Multi mode channel 3 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "MCH3CAPPSC,Multi mode channel 3 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MCH3MS,Multi mode channel 3 I/O mode selection." "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MCH2CAPFLT,Multi mode channel 2 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MCH2CAPPSC,Multi mode channel 2 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MCH2MS,Multi mode channel 2 I/O mode selection" "0,1,2,3"
|
|
line.long 0x4 "MCHFCTL2,Multi mode channel control register 2"
|
|
bitfld.long 0x4 6.--7. "MCH3FP,Multi mode channel 3 capture/compare free polarity" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "MCH2FP,Multi mode channel 2 capture/compare free polarity" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "MCH1FP,Multi mode channel 1 capture/compare free polarity" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "MCH0FP,Multi mode channel 0 capture/compare free polarity" "0,1,2,3"
|
|
line.long 0x8 "MCH0CV,Multi mode channel 0 capture/compare value register"
|
|
hexmask.long.word 0x8 0.--15. 1. "MCH0VAL,Capture/compare value of multi mode channel 0"
|
|
line.long 0xC "MCH1CV,Multi mode channel 1 capture/compare value register"
|
|
hexmask.long.word 0xC 0.--15. 1. "MCH1VAL,Capture/compare value of multi mode channel 1"
|
|
line.long 0x10 "MCH2CV,Multi mode channel 2 capture/compare value register"
|
|
hexmask.long.word 0x10 0.--15. 1. "MCH2VAL,Capture/compare value of multi mode channel 2"
|
|
line.long 0x14 "MCH3CV,Capture/compare value of multi mode channel 3"
|
|
hexmask.long.word 0x14 0.--15. 1. "MCH3VAL,Capture/compare value of channel 3"
|
|
line.long 0x18 "CH0COMV_ADD,Channel 0 additional compare value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
|
|
line.long 0x1C "CH1COMV_ADD,Channel 1 additional compare value register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
|
|
line.long 0x20 "CH2COMV_ADD,Channel 2 additional compare value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "CH2COMVAL_ADD,Additional compare value of channel 2"
|
|
line.long 0x24 "CH3COMV_ADD,Channel 3 additional compare value register"
|
|
hexmask.long.word 0x24 0.--15. 1. "CH3COMVAL_ADD,Additional compare value of channel 3"
|
|
line.long 0x28 "CTL2,Control register 2"
|
|
bitfld.long 0x28 31. "CH3CPWMEN,Channel 3 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x28 30. "CH2CPWMEN,Channel 2 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x28 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x28 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x28 26.--27. "MCH3MSEL,Multi mode channel 3 mode select" "0,1,2,3"
|
|
bitfld.long 0x28 24.--25. "MCH2MSEL,Multi mode channel 2 mode select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x28 22.--23. "MCH1MSEL,Multi mode channel 1 mode select" "0,1,2,3"
|
|
bitfld.long 0x28 20.--21. "MCH0MSEL,Multi mode channel 0 mode select" "0,1,2,3"
|
|
bitfld.long 0x28 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
|
|
bitfld.long 0x28 18. "DECJDEN,Quadrature decoder signal jump (the two signals jump at the same time) detection enable" "0,1"
|
|
bitfld.long 0x28 14.--15. "CH3OMPSEL,Channel 3 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x28 12.--13. "CH2OMPSEL,Channel 2 output match pulse select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x28 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x28 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x28 7. "BRKENCH3,Break control enable for channel 3" "0,1"
|
|
bitfld.long 0x28 6. "BRKENCH2,Break control enable for channel 2" "0,1"
|
|
bitfld.long 0x28 5. "BRKENCH1,Break control enable for channel 1" "0,1"
|
|
bitfld.long 0x28 4. "BRKENCH0,Break control enable for channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 3. "DTIENCH3,Dead time inserted enable for channel 3" "0,1"
|
|
bitfld.long 0x28 2. "DTIENCH2,Dead time inserted enable for channel 2" "0,1"
|
|
bitfld.long 0x28 1. "DTIENCH1,Dead time inserted enable for channel 1" "0,1"
|
|
bitfld.long 0x28 0. "DTIENCH0,Dead time inserted enable for channel 0" "0,1"
|
|
group.long 0x7C++0x1F
|
|
line.long 0x0 "FCCHP0,Free complementary channel protection register 0"
|
|
bitfld.long 0x0 31. "FCCHP0EN,Free complementary channel protection register 0 enable" "0,1"
|
|
bitfld.long 0x0 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x0 10. "IOS,Idle mode off-state configure" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0x4 "FCCHP1,Free complementary channel protection register 1"
|
|
bitfld.long 0x4 31. "FCCHP1EN,Free complementary channel protection register 1 enable" "0,1"
|
|
bitfld.long 0x4 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x4 10. "IOS,Idle mode off-state configure" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0x8 "FCCHP2,Free complementary channel protection register 2"
|
|
bitfld.long 0x8 31. "FCCHP2EN,Free complementary channel protection register 2 enable" "0,1"
|
|
bitfld.long 0x8 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x8 10. "IOS,Idle mode off-state configure" "0,1"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0xC "FCCHP3,Free complementary channel protection register 3"
|
|
bitfld.long 0xC 31. "FCCHP3EN,Free complementary channel protection register 3 enable" "0,1"
|
|
bitfld.long 0xC 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0xC 10. "IOS,Idle mode off-state configure" "0,1"
|
|
hexmask.long.byte 0xC 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0x10 "AFCTL0,alternate function control register 0"
|
|
bitfld.long 0x10 26. "BRK0CMP1P,BRK CMP1 input polarity" "0,1"
|
|
bitfld.long 0x10 25. "BRK0CMP0P,BRK CMP0 input polarity" "0,1"
|
|
bitfld.long 0x10 18. "BRK0IN2P,BREAK0 BRKIN2 alternate function input polarity" "0,1"
|
|
bitfld.long 0x10 17. "BRK0IN1P,BREAK0 BRKIN1 alternate function input polarity" "0,1"
|
|
bitfld.long 0x10 16. "BRK0IN0P,BREAK0 BRKIN0 alternate function input polarity" "0,1"
|
|
bitfld.long 0x10 10. "BRK0CMP1EN,BRK CMP1 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "BRK0CMP0EN,BRK CMP0 enable" "0,1"
|
|
bitfld.long 0x10 8. "BRK0HPDFEN,BRK HPDF input enable" "0,1"
|
|
bitfld.long 0x10 2. "BRK0IN2EN,BREAK0 BRKIN2 alternate function input enable" "0,1"
|
|
bitfld.long 0x10 1. "BRK0IN1EN,BREAK0 BRKIN1 alternate function input enable" "0,1"
|
|
bitfld.long 0x10 0. "BRK0IN0EN,BREAK0 BRKIN0 alternate function input enable" "0,1"
|
|
line.long 0x14 "AFCTL1,alternate function control register 0"
|
|
bitfld.long 0x14 26. "BRK1CMP1P,BRK1 CMP1 input polarity" "0,1"
|
|
bitfld.long 0x14 25. "BRK1CMP0P,BRK1 CMP0 input polarity" "0,1"
|
|
bitfld.long 0x14 18. "BRK1IN2P,BREAK1 BRKIN2 alternate function input polarity" "0,1"
|
|
bitfld.long 0x14 17. "BRK1IN1P,BREAK1 BRKIN1 alternate function input polarity" "0,1"
|
|
bitfld.long 0x14 16. "BRK1IN0P,BRK1 BRKIN0 alternate function input polarity" "0,1"
|
|
bitfld.long 0x14 10. "BRK1CMP1EN,BRK1 CMP1 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "BRK1CMP0EN,BRK1 CMP0 enable" "0,1"
|
|
bitfld.long 0x14 8. "BRK1HPDFEN,BRK1 HPDF input enable" "0,1"
|
|
bitfld.long 0x14 2. "BRK1IN2EN,BREAK1 BRKIN1 alternate function input enable" "0,1"
|
|
bitfld.long 0x14 1. "BRK1IN1EN,BREAK1 BRKIN1 alternate function input enable" "0,1"
|
|
bitfld.long 0x14 0. "BRK1IN0EN,BRK1 BRK1IN alternate function input enable" "0,1"
|
|
line.long 0x18 "WDGPER,Watchdog counter register"
|
|
hexmask.long 0x18 0.--31. 1. "WDGPER,Watchdog timeout count"
|
|
line.long 0x1C "CREP1,Counter repetition register 1"
|
|
hexmask.long 0x1C 0.--31. 1. "CREP1,Counter repetition value 1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 3. "CCUSEL,Commutation control shadow register update select" "0,1"
|
|
bitfld.long 0x0 2. "CREPSEL,The counter repetition register select" "0,1"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
bitfld.long 0x0 0. "OUTSEL,The output value selection" "0,1"
|
|
tree.end
|
|
tree "TIMER1"
|
|
base ad:0x40000000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
line.long 0x8 "SMCFG,Slave mode configuration register"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "SMC1,Part of SMC is used to enable external clock mode 1" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETFC,External trigger filter control"
|
|
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
|
|
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0xC 31. "CH3COMADDIE,Channel 3 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 30. "CH2COMADDIE,Channel 2 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 17. "DECDISIE,Quadrature decoder signal disconnection interrupt enable" "0,1"
|
|
bitfld.long 0xC 16. "DECJIE,Quadrature decoder signal jump (the two signals jump at the same time) interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CH3DEN,Channel 3 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 11. "CH2DEN,Channel 2 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CH3IE,Channel 3 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CH2IE,Channel 2 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "INTF,Interrupt flag register"
|
|
bitfld.long 0x10 31. "CH3COMADDIF,Channel 3 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 30. "CH2COMADDIF,Channel 2 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "DECDISIF,Quadrature decoder signal disconnection interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "DECJIF,Quadrature decoder signal jump (the two signals jump at the same time) interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CH3OF,Channel 3 over capture flag" "0,1"
|
|
bitfld.long 0x10 11. "CH2OF,Channel 2 over capture flag" "0,1"
|
|
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
|
|
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CH3IF,Channel 3 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CH2IF,Channel 2 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 31. "CH3COMADDG,Channel 3 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 30. "CH2COMADDG,Channel 2 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
|
|
bitfld.long 0x0 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL1_Output,Channel control register 1 (output"
|
|
bitfld.long 0x4 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x4 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
bitfld.long 0x4 29. "CH3COMADDSEN,Channel 3 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 28. "CH2COMADDSEN,Channel 2 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 24. "CH3COMCTL_3,BIT 3 of channel 3 compare output control" "0,1"
|
|
bitfld.long 0x4 23. "CH2COMCTL_3,BIT 3 of channel 2 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
bitfld.long 0x4 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CHCTL1_Input,Channel control register 1 (input"
|
|
bitfld.long 0x0 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x0 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH3CAPFLT,Channel 3 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH2CAPFLT,Channel 2 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x4 15. "CH3NP,Multi mode channel 3 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 13. "CH3P,Channel 3 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 12. "CH3EN,Channel 3 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 11. "CH2NP,Multi mode channel 2 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 9. "CH2P,Channel 2 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 8. "CH2EN,Channel 2 capture/compare function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CH1NP,Multi mode channel 1 output polarity" "0,1"
|
|
bitfld.long 0x4 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 3. "CH0NP,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x4 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long 0x8 0.--31. 1. "CNT,current counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0x10 "CAR,Counter auto reload register"
|
|
hexmask.long 0x10 0.--31. 1. "CARL,Counter auto reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long 0x0 0.--31. 1. "CH0VAL,Capture or compare value of channel0"
|
|
line.long 0x4 "CH1CV,Channel 1 capture/compare value register"
|
|
hexmask.long 0x4 0.--31. 1. "CH1VAL,Capture or compare value of channel1"
|
|
line.long 0x8 "CH2CV,Channel 2 capture/compare value register"
|
|
hexmask.long 0x8 0.--31. 1. "CH2VAL,Capture or compare value of channel 2"
|
|
line.long 0xC "CH3CV,Channel 3 capture/compare value register"
|
|
hexmask.long 0xC 0.--31. 1. "CH3VAL,Capture or compare value of channel 3"
|
|
group.long 0x64++0x13
|
|
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
|
|
hexmask.long 0x0 0.--31. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
|
|
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
|
|
hexmask.long 0x4 0.--31. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
|
|
line.long 0x8 "CH2COMV_ADD,Channel 2 additional compare value register"
|
|
hexmask.long 0x8 0.--31. 1. "CH2COMVAL_ADD,Additional compare value of channel 2"
|
|
line.long 0xC "CH3COMV_ADD,Channel 3 additional compare value register"
|
|
hexmask.long 0xC 0.--31. 1. "CH3COMVAL_ADD,Additional compare value of channel 3"
|
|
line.long 0x10 "CTL2,Control register 2"
|
|
bitfld.long 0x10 31. "CH3CPWMEN,Channel 3 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 30. "CH2CPWMEN,Channel 2 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
|
|
bitfld.long 0x10 18. "DECJDEN,Quadrature decoder signal jump detection enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14.--15. "CH3OMPSEL,Channel 3 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "CH2OMPSEL,Channel 2 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "WDGPER,Watchdog counter register"
|
|
hexmask.long 0x0 0.--31. 1. "WDGPER,Watchdog timeout count"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
tree.end
|
|
tree "TIMER2"
|
|
base ad:0x40000400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
line.long 0x8 "SMCFG,Slave mode configuration register"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "SMC1,Part of SMC is used to enable external clock mode 1" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETFC,External trigger filter control"
|
|
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
|
|
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0xC 31. "CH3COMADDIE,Channel 3 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 30. "CH2COMADDIE,Channel 2 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 17. "DECDISIE,Quadrature decoder signal disconnection interrupt enable" "0,1"
|
|
bitfld.long 0xC 16. "DECJIE,Quadrature decoder signal jump (the two signals jump at the same time) interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CH3DEN,Channel 3 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 11. "CH2DEN,Channel 2 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CH3IE,Channel 3 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CH2IE,Channel 2 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "INTF,Interrupt flag register"
|
|
bitfld.long 0x10 31. "CH3COMADDIF,Channel 3 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 30. "CH2COMADDIF,Channel 2 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "DECDISIF,Quadrature decoder signal disconnection interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "DECJIF,Quadrature decoder signal jump (the two signals jump at the same time) interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CH3OF,Channel 3 over capture flag" "0,1"
|
|
bitfld.long 0x10 11. "CH2OF,Channel 2 over capture flag" "0,1"
|
|
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
|
|
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CH3IF,Channel 3 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CH2IF,Channel 2 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 31. "CH3COMADDG,Channel 3 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 30. "CH2COMADDG,Channel 2 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
|
|
bitfld.long 0x0 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL1_Output,Channel control register 1 (output"
|
|
bitfld.long 0x4 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x4 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
bitfld.long 0x4 29. "CH3COMADDSEN,Channel 3 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 28. "CH2COMADDSEN,Channel 2 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 24. "CH3COMCTL_3,BIT 3 of channel 3 compare output control" "0,1"
|
|
bitfld.long 0x4 23. "CH2COMCTL_3,BIT 3 of channel 2 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
bitfld.long 0x4 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CHCTL1_Input,Channel control register 1 (input"
|
|
bitfld.long 0x0 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x0 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH3CAPFLT,Channel 3 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH2CAPFLT,Channel 2 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x4 15. "CH3NP,Multi mode channel 3 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 13. "CH3P,Channel 3 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 12. "CH3EN,Channel 3 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 11. "CH2NP,Multi mode channel 2 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 9. "CH2P,Channel 2 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 8. "CH2EN,Channel 2 capture/compare function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CH1NP,Multi mode channel 1 output polarity" "0,1"
|
|
bitfld.long 0x4 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 3. "CH0NP,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x4 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
rbitfld.long 0x8 31. "UPIFBU,UPIF bit backup" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,current counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0x10 "CAR,Counter auto reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CARL,Counter auto reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
|
|
line.long 0x4 "CH1CV,Channel 1 capture/compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CH1VAL,Capture or compare value of channel1"
|
|
line.long 0x8 "CH2CV,Channel 2 capture/compare value register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CH2VAL,Capture or compare value of channel 2"
|
|
line.long 0xC "CH3CV,Channel 3 capture/compare value register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CH3VAL,Capture or compare value of channel 3"
|
|
group.long 0x64++0x13
|
|
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
|
|
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
|
|
line.long 0x8 "CH2COMV_ADD,Channel 2 additional compare value register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CH2COMVAL_ADD,Additional compare value of channel 2"
|
|
line.long 0xC "CH3COMV_ADD,Channel 3 additional compare value register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CH3COMVAL_ADD,Additional compare value of channel 3"
|
|
line.long 0x10 "CTL2,Control register 2"
|
|
bitfld.long 0x10 31. "CH3CPWMEN,Channel 3 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 30. "CH2CPWMEN,Channel 2 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
|
|
bitfld.long 0x10 18. "DECJDEN,Quadrature decoder signal jump detection enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14.--15. "CH3OMPSEL,Channel 3 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "CH2OMPSEL,Channel 2 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "WDGPER,Watchdog counter register"
|
|
hexmask.long 0x0 0.--31. 1. "WDGPER,Watchdog timeout count"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
tree.end
|
|
tree "TIMER3"
|
|
base ad:0x40000800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
line.long 0x8 "SMCFG,Slave mode configuration register"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "SMC1,Part of SMC is used to enable external clock mode 1" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETFC,External trigger filter control"
|
|
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
|
|
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0xC 31. "CH3COMADDIE,Channel 3 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 30. "CH2COMADDIE,Channel 2 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 17. "DECDISIE,Quadrature decoder signal disconnection interrupt enable" "0,1"
|
|
bitfld.long 0xC 16. "DECJIE,Quadrature decoder signal jump (the two signals jump at the same time) interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CH3DEN,Channel 3 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 11. "CH2DEN,Channel 2 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CH3IE,Channel 3 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CH2IE,Channel 2 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "INTF,Interrupt flag register"
|
|
bitfld.long 0x10 31. "CH3COMADDIF,Channel 3 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 30. "CH2COMADDIF,Channel 2 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "DECDISIF,Quadrature decoder signal disconnection interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "DECJIF,Quadrature decoder signal jump (the two signals jump at the same time) interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CH3OF,Channel 3 over capture flag" "0,1"
|
|
bitfld.long 0x10 11. "CH2OF,Channel 2 over capture flag" "0,1"
|
|
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
|
|
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CH3IF,Channel 3 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CH2IF,Channel 2 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 31. "CH3COMADDG,Channel 3 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 30. "CH2COMADDG,Channel 2 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
|
|
bitfld.long 0x0 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL1_Output,Channel control register 1 (output"
|
|
bitfld.long 0x4 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x4 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
bitfld.long 0x4 29. "CH3COMADDSEN,Channel 3 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 28. "CH2COMADDSEN,Channel 2 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 24. "CH3COMCTL_3,BIT 3 of channel 3 compare output control" "0,1"
|
|
bitfld.long 0x4 23. "CH2COMCTL_3,BIT 3 of channel 2 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
bitfld.long 0x4 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CHCTL1_Input,Channel control register 1 (input"
|
|
bitfld.long 0x0 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x0 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH3CAPFLT,Channel 3 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH2CAPFLT,Channel 2 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x4 15. "CH3NP,Multi mode channel 3 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 13. "CH3P,Channel 3 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 12. "CH3EN,Channel 3 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 11. "CH2NP,Multi mode channel 2 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 9. "CH2P,Channel 2 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 8. "CH2EN,Channel 2 capture/compare function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CH1NP,Multi mode channel 1 output polarity" "0,1"
|
|
bitfld.long 0x4 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 3. "CH0NP,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x4 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
rbitfld.long 0x8 31. "UPIFBU,UPIF bit backup" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,current counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0x10 "CAR,Counter auto reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CARL,Counter auto reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
|
|
line.long 0x4 "CH1CV,Channel 1 capture/compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CH1VAL,Capture or compare value of channel1"
|
|
line.long 0x8 "CH2CV,Channel 2 capture/compare value register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CH2VAL,Capture or compare value of channel 2"
|
|
line.long 0xC "CH3CV,Channel 3 capture/compare value register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CH3VAL,Capture or compare value of channel 3"
|
|
group.long 0x64++0x13
|
|
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
|
|
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
|
|
line.long 0x8 "CH2COMV_ADD,Channel 2 additional compare value register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CH2COMVAL_ADD,Additional compare value of channel 2"
|
|
line.long 0xC "CH3COMV_ADD,Channel 3 additional compare value register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CH3COMVAL_ADD,Additional compare value of channel 3"
|
|
line.long 0x10 "CTL2,Control register 2"
|
|
bitfld.long 0x10 31. "CH3CPWMEN,Channel 3 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 30. "CH2CPWMEN,Channel 2 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
|
|
bitfld.long 0x10 18. "DECJDEN,Quadrature decoder signal jump detection enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14.--15. "CH3OMPSEL,Channel 3 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "CH2OMPSEL,Channel 2 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "WDGPER,Watchdog counter register"
|
|
hexmask.long 0x0 0.--31. 1. "WDGPER,Watchdog timeout count"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
tree.end
|
|
tree "TIMER4"
|
|
base ad:0x40000C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
line.long 0x8 "SMCFG,Slave mode configuration register"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "SMC1,Part of SMC is used to enable external clock mode 1" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETFC,External trigger filter control"
|
|
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
|
|
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0xC 31. "CH3COMADDIE,Channel 3 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 30. "CH2COMADDIE,Channel 2 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 17. "DECDISIE,Quadrature decoder signal disconnection interrupt enable" "0,1"
|
|
bitfld.long 0xC 16. "DECJIE,Quadrature decoder signal jump (the two signals jump at the same time) interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CH3DEN,Channel 3 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 11. "CH2DEN,Channel 2 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CH3IE,Channel 3 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CH2IE,Channel 2 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "INTF,Interrupt flag register"
|
|
bitfld.long 0x10 31. "CH3COMADDIF,Channel 3 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 30. "CH2COMADDIF,Channel 2 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "DECDISIF,Quadrature decoder signal disconnection interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "DECJIF,Quadrature decoder signal jump (the two signals jump at the same time) interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CH3OF,Channel 3 over capture flag" "0,1"
|
|
bitfld.long 0x10 11. "CH2OF,Channel 2 over capture flag" "0,1"
|
|
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
|
|
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CH3IF,Channel 3 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CH2IF,Channel 2 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 31. "CH3COMADDG,Channel 3 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 30. "CH2COMADDG,Channel 2 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
|
|
bitfld.long 0x0 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL1_Output,Channel control register 1 (output"
|
|
bitfld.long 0x4 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x4 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
bitfld.long 0x4 29. "CH3COMADDSEN,Channel 3 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 28. "CH2COMADDSEN,Channel 2 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 24. "CH3COMCTL_3,BIT 3 of channel 3 compare output control" "0,1"
|
|
bitfld.long 0x4 23. "CH2COMCTL_3,BIT 3 of channel 2 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
bitfld.long 0x4 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CHCTL1_Input,Channel control register 1 (input"
|
|
bitfld.long 0x0 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x0 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH3CAPFLT,Channel 3 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH2CAPFLT,Channel 2 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x4 15. "CH3NP,Multi mode channel 3 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 13. "CH3P,Channel 3 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 12. "CH3EN,Channel 3 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 11. "CH2NP,Multi mode channel 2 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 9. "CH2P,Channel 2 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 8. "CH2EN,Channel 2 capture/compare function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CH1NP,Multi mode channel 1 output polarity" "0,1"
|
|
bitfld.long 0x4 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 3. "CH0NP,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x4 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long 0x8 0.--31. 1. "CNT,current counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0x10 "CAR,Counter auto reload register"
|
|
hexmask.long 0x10 0.--31. 1. "CARL,Counter auto reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long 0x0 0.--31. 1. "CH0VAL,Capture or compare value of channel0"
|
|
line.long 0x4 "CH1CV,Channel 1 capture/compare value register"
|
|
hexmask.long 0x4 0.--31. 1. "CH1VAL,Capture or compare value of channel1"
|
|
line.long 0x8 "CH2CV,Channel 2 capture/compare value register"
|
|
hexmask.long 0x8 0.--31. 1. "CH2VAL,Capture or compare value of channel 2"
|
|
line.long 0xC "CH3CV,Channel 3 capture/compare value register"
|
|
hexmask.long 0xC 0.--31. 1. "CH3VAL,Capture or compare value of channel 3"
|
|
group.long 0x64++0x13
|
|
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
|
|
hexmask.long 0x0 0.--31. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
|
|
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
|
|
hexmask.long 0x4 0.--31. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
|
|
line.long 0x8 "CH2COMV_ADD,Channel 2 additional compare value register"
|
|
hexmask.long 0x8 0.--31. 1. "CH2COMVAL_ADD,Additional compare value of channel 2"
|
|
line.long 0xC "CH3COMV_ADD,Channel 3 additional compare value register"
|
|
hexmask.long 0xC 0.--31. 1. "CH3COMVAL_ADD,Additional compare value of channel 3"
|
|
line.long 0x10 "CTL2,Control register 2"
|
|
bitfld.long 0x10 31. "CH3CPWMEN,Channel 3 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 30. "CH2CPWMEN,Channel 2 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
|
|
bitfld.long 0x10 18. "DECJDEN,Quadrature decoder signal jump detection enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14.--15. "CH3OMPSEL,Channel 3 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "CH2OMPSEL,Channel 2 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "WDGPER,Watchdog counter register"
|
|
hexmask.long 0x0 0.--31. 1. "WDGPER,Watchdog timeout count"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
tree.end
|
|
tree "TIMER5"
|
|
base ad:0x40001000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTL0,control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "SPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "UPS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,control register 1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DMAINTEN,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "INTF,status register"
|
|
bitfld.long 0x4 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,event generation register"
|
|
bitfld.long 0x0 0. "UPG,Update generation" "0,1"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
hexmask.long 0x0 0.--31. 1. "CNT,Low counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "CARL,Counter auto-reload low register"
|
|
hexmask.long 0x8 0.--31. 1. "CARL,Low Auto-reload value"
|
|
tree.end
|
|
tree "TIMER6"
|
|
base ad:0x40001400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTL0,control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "SPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "UPS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,control register 1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DMAINTEN,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "INTF,status register"
|
|
bitfld.long 0x4 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,event generation register"
|
|
bitfld.long 0x0 0. "UPG,Update generation" "0,1"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
hexmask.long 0x0 0.--31. 1. "CNT,Low counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "CARL,Counter auto-reload low register"
|
|
hexmask.long 0x8 0.--31. 1. "CARL,Low Auto-reload value"
|
|
tree.end
|
|
tree "TIMER7"
|
|
base ad:0x40010400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 30.--31. "CCUC,Commutation control shadow register update control" "0,1,2,3"
|
|
bitfld.long 0x4 20.--22. "MMC1,Master mode control 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 15. "ISO3N,Idle state of multi mode channel 3 complementary output" "0,1"
|
|
bitfld.long 0x4 14. "ISO3,Idle state of channel 3 output" "0,1"
|
|
bitfld.long 0x4 13. "ISO2N,Idle state of multi mode channel 2 complementary output" "0,1"
|
|
bitfld.long 0x4 12. "ISO2,Idle state of channel 2 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ISO1N,Idle state of multi mode channel 1 complementary output" "0,1"
|
|
bitfld.long 0x4 10. "ISO1,Idle state of channel 1 output" "0,1"
|
|
bitfld.long 0x4 9. "ISO0N,Idle state of multi mode channel 0 complementary output" "0,1"
|
|
bitfld.long 0x4 8. "ISO0,Idle state of channel 0 output" "0,1"
|
|
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
line.long 0x8 "SMCFG,Slave mode configuration register"
|
|
bitfld.long 0x8 31. "TRGS_3,Bit 3 of trigger selection" "0,1"
|
|
bitfld.long 0x8 16. "SMC_3,Bit 3 of slave mode control" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "SMC1,Part of SMC is used to enable external clock mode 1" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETFC,External trigger filter control"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TRGS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0.--2. "SMC,Slave mode control" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0xC 31. "CH3COMADDIE,Channel 3 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 30. "CH2COMADDIE,Channel 2 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 27. "MCH3DEN,Multi mode channel 3 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 26. "MCH2DEN,Multi mode channel 2 capture/compare DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "MCH1DEN,Multi mode channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 24. "MCH0DEN,Multi mode channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 23. "MCH3IE,Multi mode channel 3 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 22. "MCH2IE,Multi mode channel 2 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 21. "MCH1IE,Multi mode channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 20. "MCH0IE,Multi mode channel 0 capture/compare interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
|
|
bitfld.long 0xC 18. "DECJDEN,Quadrature decoder signal jump (the two signals jump at the same time) detection enable" "0,1"
|
|
bitfld.long 0xC 17. "DECDISIE,Quadrature decoder signal disconnection interrupt enable" "0,1"
|
|
bitfld.long 0xC 16. "DECJIE,Quadrature decoder signal jump (the two signals jump at the same time) interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "CMTDEN,Commutation DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "CH3DEN,Channel 3 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 11. "CH2DEN,Channel 2 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BRKIE,Break interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "CMTIE,Commutation interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CH3IE,Channel 3 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CH2IE,Channel 2 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "INTF,Interrupt flag register"
|
|
bitfld.long 0x10 31. "CH3COMADDIF,Channel 3 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 30. "CH2COMADDIF,Channel 2 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 27. "MCH3OF,Multi mode channel 3 over capture flag" "0,1"
|
|
bitfld.long 0x10 26. "MCH2OF,Multi mode channel 2 over capture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "MCH1OF,Multi mode channel 1 over capture flag" "0,1"
|
|
bitfld.long 0x10 24. "MCH0OF,Multi mode channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 23. "MCH3IF,Multi mode channel 3 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 22. "MCH2IF,Multi mode channel 2 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 21. "MCH1IF,Multi mode channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 20. "MCH0IF,Multi mode channel 0 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "DECDISIF,Quadrature decoder signal disconnection interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "DECJIF,Quadrature decoder signal jump (the two signals jump at the same time) interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SYSBIF,SYSBIF" "0,1"
|
|
bitfld.long 0x10 12. "CH3OF,Channel 3 over capture flag" "0,1"
|
|
bitfld.long 0x10 11. "CH2OF,Channel 2 over capture flag" "0,1"
|
|
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 8. "BRK1IF,Break1 interrupt flag" "0,1"
|
|
bitfld.long 0x10 7. "BRK0IF,Break0 interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 5. "CMTIF,Channel commutation interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CH3IF,Channel 3 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CH2IF,Channel 2 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 31. "CH3COMADDG,Channel 3 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 30. "CH2COMADDG,Channel 2 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 23. "MCH3G,Multi mode channel 3 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 22. "MCH2G,Multi mode channel 2 capture or compare event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MCH1G,Multi mode channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 20. "MCH0G,Multi mode channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 8. "BRK1G,Break1 event generation" "0,1"
|
|
bitfld.long 0x0 7. "BRK0G,Break0 event generation" "0,1"
|
|
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
|
|
bitfld.long 0x0 5. "CMTG,Channel commutation event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL1_Output,Channel control register 1 (output"
|
|
bitfld.long 0x4 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x4 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
bitfld.long 0x4 29. "CH3COMADDSEN,Channel 3 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 28. "CH2COMADDSEN,Channel 2 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 24. "CH3COMCTL_3,BIT 3 of channel 3 compare output control" "0,1"
|
|
bitfld.long 0x4 23. "CH2COMCTL_3,BIT 3 of channel 2 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
bitfld.long 0x4 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
|
|
group.long 0x1C++0x2F
|
|
line.long 0x0 "CHCTL1_Input,Channel control register 1 (input"
|
|
bitfld.long 0x0 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x0 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH3CAPFLT,Channel 3 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH2CAPFLT,Channel 2 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x4 15. "MCH3P,Multi mode channel 3 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 14. "MCH3EN,Multi mode channel 3 capture/compare enable" "0,1"
|
|
bitfld.long 0x4 13. "CH3P,Channel 3 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 12. "CH3EN,Channel 3 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 11. "MCH2P,Multi mode channel 2 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 10. "MCH2EN,Multi mode channel 2 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CH2P,Channel 2 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 8. "CH2EN,Channel 2 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 7. "MCH1P,Multi mode channel 1 output polarity" "0,1"
|
|
bitfld.long 0x4 6. "MCH1EN,Multi mode channel 1 output enable" "0,1"
|
|
bitfld.long 0x4 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MCH0P,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x4 2. "MCH0EN,Multi mode channel 0 capture/compare enable" "0,1"
|
|
bitfld.long 0x4 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
bitfld.long 0x8 31. "UPIFBU,UPIF bit backup" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,current counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0x10 "CAR,Counter auto reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CARL,Counter auto reload value"
|
|
line.long 0x14 "CREP0,Counter repetition register"
|
|
hexmask.long.byte 0x14 0.--7. 1. "CREP0,Counter repetition value"
|
|
line.long 0x18 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
|
|
line.long 0x1C "CH1CV,Channel 1 capture/compare value register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CH1VAL,Capture or compare value of channel1"
|
|
line.long 0x20 "CH2CV,Channel 2 capture/compare value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "CH2VAL,Capture or compare value of channel 2"
|
|
line.long 0x24 "CH3CV,Channel 3 capture/compare value register"
|
|
hexmask.long.word 0x24 0.--15. 1. "CH3VAL,Capture or compare value of channel 3"
|
|
line.long 0x28 "CCHP,channel complementary protection register"
|
|
bitfld.long 0x28 29. "BRK1LK,BREAK1 input locked" "0,1"
|
|
bitfld.long 0x28 28. "BRK0LK,BREAK0 input locked" "0,1"
|
|
bitfld.long 0x28 27. "BRK1REL,BREAK1 input released" "0,1"
|
|
bitfld.long 0x28 26. "BRK0REL,BREAK0 input released" "0,1"
|
|
bitfld.long 0x28 25. "BRK1P,BREAK1 input signal polarity" "0,1"
|
|
bitfld.long 0x28 24. "BRK1EN,BREAK1 input signal enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x28 20.--23. 1. "BRK1F,BREAK1 input signal filter"
|
|
hexmask.long.byte 0x28 16.--19. 1. "BRK0F,BREAK0 input signal filter"
|
|
bitfld.long 0x28 15. "POEN,Primary output enable" "0,1"
|
|
bitfld.long 0x28 14. "OAEN,Output automatic enable" "0,1"
|
|
bitfld.long 0x28 13. "BRK0P,BREAK0 input signal polarity" "0,1"
|
|
bitfld.long 0x28 12. "BRK0EN,BREAK0 input signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x28 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x28 10. "IOS,Idle mode off-state configure" "0,1"
|
|
bitfld.long 0x28 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0x2C "MCHCTL0_Output,Multi mode channel control register 0 (output"
|
|
bitfld.long 0x2C 31. "MCH1MS_2,Multi mode channel 1 I/O mode selection" "0,1"
|
|
bitfld.long 0x2C 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
bitfld.long 0x2C 15. "MCH1COMCEN,Multi mode channel 1 output compare clear enable" "0,1"
|
|
bitfld.long 0x2C 12.--14. "MCH1COMCTL,Multi mode channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 11. "MCH1COMSEN,Multi mode channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x2C 8.--9. "MCH1MS,Multi mode channel 1 I/O mode selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2C 7. "MCH0COMCEN,Multi mode channel 0 output compare clear enable" "0,1"
|
|
bitfld.long 0x2C 4.--6. "MCH0COMCTL,Multi mode channel 0 output compare control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 3. "MCH0COMSEN,Multi mode channel 0 output compare shadow enable" "0,1"
|
|
bitfld.long 0x2C 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x48++0x7
|
|
line.long 0x0 "MCHCTL0_Input,Multi mode channel control register 0 (input"
|
|
bitfld.long 0x0 31. "MCH1MS_2,Multi mode channel 1 I/O mode selection" "0,1"
|
|
bitfld.long 0x0 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MCH1CAPFLT,Multi mode channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "MCH1CAPPSC,Multi mode channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MCH1MS,Multi mode channel 1 I/O mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MCH0CAPFLT,Multi mode channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MCH0CAPPSC,Multi mode channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
line.long 0x4 "MCHCTL1_Output,Multi mode channel control register 1 (output"
|
|
bitfld.long 0x4 31. "MCH3MS_2,2th bit of MCH3MS" "0,1"
|
|
bitfld.long 0x4 30. "MCH2MS_2,2th bit of MCH2MS" "0,1"
|
|
bitfld.long 0x4 15. "MCH3COMCEN,Multi mode channel 3 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "MCH3COMCTL,Multi mode channel 3 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "MCH3COMSEN,Multi mode channel 3 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "MCH3MS,Multi mode channel 3 I/O mode selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 7. "MCH2COMCEN,Multi mode channel 2 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "MCH2COMCTL,Multi mode channel 2 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "MCH2COMSEN,Multi mode channel 2 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "MCH2MS,Multi mode channel 2 I/O mode selection" "0,1,2,3"
|
|
group.long 0x4C++0x2B
|
|
line.long 0x0 "MCHCTL1_Input,Multi mode channel control register 1(input"
|
|
bitfld.long 0x0 31. "MCH3MS_2,2th bit of MCH3MS" "0,1"
|
|
bitfld.long 0x0 30. "MCH2MS_2,2th bit of MCH2MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MCH3CAPFLT,Multi mode channel 3 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "MCH3CAPPSC,Multi mode channel 3 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MCH3MS,Multi mode channel 3 I/O mode selection." "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MCH2CAPFLT,Multi mode channel 2 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MCH2CAPPSC,Multi mode channel 2 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MCH2MS,Multi mode channel 2 I/O mode selection" "0,1,2,3"
|
|
line.long 0x4 "MCHFCTL2,Multi mode channel control register 2"
|
|
bitfld.long 0x4 6.--7. "MCH3FP,Multi mode channel 3 capture/compare free polarity" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "MCH2FP,Multi mode channel 2 capture/compare free polarity" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "MCH1FP,Multi mode channel 1 capture/compare free polarity" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "MCH0FP,Multi mode channel 0 capture/compare free polarity" "0,1,2,3"
|
|
line.long 0x8 "MCH0CV,Multi mode channel 0 capture/compare value register"
|
|
hexmask.long.word 0x8 0.--15. 1. "MCH0VAL,Capture/compare value of multi mode channel 0"
|
|
line.long 0xC "MCH1CV,Multi mode channel 1 capture/compare value register"
|
|
hexmask.long.word 0xC 0.--15. 1. "MCH1VAL,Capture/compare value of multi mode channel 1"
|
|
line.long 0x10 "MCH2CV,Multi mode channel 2 capture/compare value register"
|
|
hexmask.long.word 0x10 0.--15. 1. "MCH2VAL,Capture/compare value of multi mode channel 2"
|
|
line.long 0x14 "MCH3CV,Capture/compare value of multi mode channel 3"
|
|
hexmask.long.word 0x14 0.--15. 1. "MCH3VAL,Capture/compare value of channel 3"
|
|
line.long 0x18 "CH0COMV_ADD,Channel 0 additional compare value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
|
|
line.long 0x1C "CH1COMV_ADD,Channel 1 additional compare value register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
|
|
line.long 0x20 "CH2COMV_ADD,Channel 2 additional compare value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "CH2COMVAL_ADD,Additional compare value of channel 2"
|
|
line.long 0x24 "CH3COMV_ADD,Channel 3 additional compare value register"
|
|
hexmask.long.word 0x24 0.--15. 1. "CH3COMVAL_ADD,Additional compare value of channel 3"
|
|
line.long 0x28 "CTL2,Control register 2"
|
|
bitfld.long 0x28 31. "CH3CPWMEN,Channel 3 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x28 30. "CH2CPWMEN,Channel 2 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x28 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x28 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x28 26.--27. "MCH3MSEL,Multi mode channel 3 mode select" "0,1,2,3"
|
|
bitfld.long 0x28 24.--25. "MCH2MSEL,Multi mode channel 2 mode select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x28 22.--23. "MCH1MSEL,Multi mode channel 1 mode select" "0,1,2,3"
|
|
bitfld.long 0x28 20.--21. "MCH0MSEL,Multi mode channel 0 mode select" "0,1,2,3"
|
|
bitfld.long 0x28 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
|
|
bitfld.long 0x28 18. "DECJDEN,Quadrature decoder signal jump (the two signals jump at the same time) detection enable" "0,1"
|
|
bitfld.long 0x28 14.--15. "CH3OMPSEL,Channel 3 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x28 12.--13. "CH2OMPSEL,Channel 2 output match pulse select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x28 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x28 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x28 7. "BRKENCH3,Break control enable for channel 3" "0,1"
|
|
bitfld.long 0x28 6. "BRKENCH2,Break control enable for channel 2" "0,1"
|
|
bitfld.long 0x28 5. "BRKENCH1,Break control enable for channel 1" "0,1"
|
|
bitfld.long 0x28 4. "BRKENCH0,Break control enable for channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 3. "DTIENCH3,Dead time inserted enable for channel 3" "0,1"
|
|
bitfld.long 0x28 2. "DTIENCH2,Dead time inserted enable for channel 2" "0,1"
|
|
bitfld.long 0x28 1. "DTIENCH1,Dead time inserted enable for channel 1" "0,1"
|
|
bitfld.long 0x28 0. "DTIENCH0,Dead time inserted enable for channel 0" "0,1"
|
|
group.long 0x7C++0x1F
|
|
line.long 0x0 "FCCHP0,Free complementary channel protection register 0"
|
|
bitfld.long 0x0 31. "FCCHP0EN,Free complementary channel protection register 0 enable" "0,1"
|
|
bitfld.long 0x0 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x0 10. "IOS,Idle mode off-state configure" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0x4 "FCCHP1,Free complementary channel protection register 1"
|
|
bitfld.long 0x4 31. "FCCHP1EN,Free complementary channel protection register 1 enable" "0,1"
|
|
bitfld.long 0x4 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x4 10. "IOS,Idle mode off-state configure" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0x8 "FCCHP2,Free complementary channel protection register 2"
|
|
bitfld.long 0x8 31. "FCCHP2EN,Free complementary channel protection register 2 enable" "0,1"
|
|
bitfld.long 0x8 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x8 10. "IOS,Idle mode off-state configure" "0,1"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0xC "FCCHP3,Free complementary channel protection register 3"
|
|
bitfld.long 0xC 31. "FCCHP3EN,Free complementary channel protection register 3 enable" "0,1"
|
|
bitfld.long 0xC 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0xC 10. "IOS,Idle mode off-state configure" "0,1"
|
|
hexmask.long.byte 0xC 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0x10 "AFCTL0,alternate function control register 0"
|
|
bitfld.long 0x10 26. "BRK0CMP1P,BRK CMP1 input polarity" "0,1"
|
|
bitfld.long 0x10 25. "BRK0CMP0P,BRK CMP0 input polarity" "0,1"
|
|
bitfld.long 0x10 18. "BRK0IN2P,BREAK0 BRKIN2 alternate function input polarity" "0,1"
|
|
bitfld.long 0x10 17. "BRK0IN1P,BREAK0 BRKIN1 alternate function input polarity" "0,1"
|
|
bitfld.long 0x10 16. "BRK0IN0P,BREAK0 BRKIN0 alternate function input polarity" "0,1"
|
|
bitfld.long 0x10 10. "BRK0CMP1EN,BRK CMP1 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "BRK0CMP0EN,BRK CMP0 enable" "0,1"
|
|
bitfld.long 0x10 8. "BRK0HPDFEN,BRK HPDF input enable" "0,1"
|
|
bitfld.long 0x10 2. "BRK0IN2EN,BREAK0 BRKIN2 alternate function input enable" "0,1"
|
|
bitfld.long 0x10 1. "BRK0IN1EN,BREAK0 BRKIN1 alternate function input enable" "0,1"
|
|
bitfld.long 0x10 0. "BRK0IN0EN,BREAK0 BRKIN0 alternate function input enable" "0,1"
|
|
line.long 0x14 "AFCTL1,alternate function control register 0"
|
|
bitfld.long 0x14 26. "BRK1CMP1P,BRK1 CMP1 input polarity" "0,1"
|
|
bitfld.long 0x14 25. "BRK1CMP0P,BRK1 CMP0 input polarity" "0,1"
|
|
bitfld.long 0x14 18. "BRK1IN2P,BREAK1 BRKIN2 alternate function input polarity" "0,1"
|
|
bitfld.long 0x14 17. "BRK1IN1P,BREAK1 BRKIN1 alternate function input polarity" "0,1"
|
|
bitfld.long 0x14 16. "BRK1IN0P,BRK1 BRKIN0 alternate function input polarity" "0,1"
|
|
bitfld.long 0x14 10. "BRK1CMP1EN,BRK1 CMP1 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "BRK1CMP0EN,BRK1 CMP0 enable" "0,1"
|
|
bitfld.long 0x14 8. "BRK1HPDFEN,BRK1 HPDF input enable" "0,1"
|
|
bitfld.long 0x14 2. "BRK1IN2EN,BREAK1 BRKIN1 alternate function input enable" "0,1"
|
|
bitfld.long 0x14 1. "BRK1IN1EN,BREAK1 BRKIN1 alternate function input enable" "0,1"
|
|
bitfld.long 0x14 0. "BRK1IN0EN,BRK1 BRK1IN alternate function input enable" "0,1"
|
|
line.long 0x18 "WDGPER,Watchdog counter register"
|
|
hexmask.long 0x18 0.--31. 1. "WDGPER,Watchdog timeout count"
|
|
line.long 0x1C "CREP1,Counter repetition register 1"
|
|
hexmask.long 0x1C 0.--31. 1. "CREP1,Counter repetition value 1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 3. "CCUSEL,Commutation control shadow register update select" "0,1"
|
|
bitfld.long 0x0 2. "CREPSEL,The counter repetition register select" "0,1"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
bitfld.long 0x0 0. "OUTSEL,The output value selection" "0,1"
|
|
tree.end
|
|
tree "TIMER14"
|
|
base ad:0x40014000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 30.--31. "CCUC,Commutation control shadow register update control" "0,1,2,3"
|
|
bitfld.long 0x4 10. "ISO1,Idle state of channel 1 output" "0,1"
|
|
bitfld.long 0x4 9. "ISO0N,Idle state of multi mode channel 0 complementary output" "0,1"
|
|
bitfld.long 0x4 8. "ISO0,Idle state of channel 0 output" "0,1"
|
|
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
line.long 0x8 "SMCFG,Slave mode configuration register"
|
|
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
|
|
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 24. "MCH0DEN,Multi mode channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 20. "MCH0IE,Multi mode channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "CMTDEN,Commutation DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BRKIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "CMTIE,Commutation interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "INTF,Interrupt flag register"
|
|
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 24. "MCH0OF,Multi mode channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 20. "MCH0IF,Multi mode channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SYSBIF,SYSBIF" "0,1"
|
|
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 7. "BRK0IF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 5. "CMTIF,Channel commutation interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 20. "MCH0G,Multi mode channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 7. "BRK0G,Break event generation" "0,1"
|
|
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
|
|
bitfld.long 0x0 5. "CMTG,Channel commutation event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 0 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x0 7. "MCH1P,Multi mode channel 1 output polarity" "0,1"
|
|
bitfld.long 0x0 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x0 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
|
|
bitfld.long 0x0 3. "MCH0P,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x0 2. "MCH0EN,Multi mode channel 0 capture/compare enable" "0,1"
|
|
bitfld.long 0x0 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
bitfld.long 0x4 31. "UPIFBU,UPIF bit backup" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,current counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0xC "CAR,Counter auto reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CARL,Counter auto reload value"
|
|
line.long 0x10 "CREP0,Counter repetition register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "CREP0,Counter repetition value"
|
|
line.long 0x14 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
|
|
line.long 0x18 "CH1CV,Channel 1 capture/compare value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "CH1VAL,Capture or compare value of channel1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "CCHP,channel complementary protection register"
|
|
bitfld.long 0x0 28. "BRK0LK,BREAK0 input locked" "0,1"
|
|
bitfld.long 0x0 26. "BRK0REL,BREAK0 input released" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BRK0F,BREAK0 input signal filter"
|
|
bitfld.long 0x0 15. "POEN,Primary output enable" "0,1"
|
|
bitfld.long 0x0 14. "OAEN,Output automatic enable" "0,1"
|
|
bitfld.long 0x0 13. "BRK0P,BREAK0 input signal polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "BRK0EN,BREAK0 input signal enable" "0,1"
|
|
bitfld.long 0x0 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x0 10. "IOS,Idle mode off-state configure" "0,1"
|
|
bitfld.long 0x0 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0x4 "MCHCTL0_Output,Multi mode channel control register 0 (output"
|
|
bitfld.long 0x4 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
bitfld.long 0x4 16. "MCH0COMCTL_3,Multi mode channel 0 compare output control" "0,1"
|
|
bitfld.long 0x4 8.--9. "MCH1MS,Multi mode channel 1 I/O mode selection" "0,1,2,3"
|
|
bitfld.long 0x4 4.--6. "MCH0COMCTL,Multi mode channel 0 output compare control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "MCH0COMSEN,Multi mode channel 0 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "MCHCTL0_Input,Multi mode channel control register 0 (input"
|
|
bitfld.long 0x0 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MCH0CAPFLT,Multi mode channel 0 input capture filter control"
|
|
bitfld.long 0x0 2.--3. "MCH0CAPPSC,Multi mode channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x50++0x7
|
|
line.long 0x0 "MCHFCTL2,Multi mode channel control register 2"
|
|
bitfld.long 0x0 0.--1. "MCH0FP,Multi mode channel 0 capture/compare free polarity" "0,1,2,3"
|
|
line.long 0x4 "MCH0CV,Multi mode channel 0 capture/compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "MCH0VAL,Capture/compare value of multi mode channel 0"
|
|
group.long 0x64++0x7
|
|
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
|
|
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "CTL2,Control register 2"
|
|
bitfld.long 0x0 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x0 20.--21. "MCH0MSEL,Multi mode channel 0 mode select" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "AFCTL0,alternate function control register 0"
|
|
bitfld.long 0x0 26. "BRK0CMP1P,BRK CMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 25. "BRK0CMP0P,BRK CMP0 input polarity" "0,1"
|
|
bitfld.long 0x0 16. "BRK0IN0P,BREAK0 BRKIN0 alternate function input polarity" "0,1"
|
|
bitfld.long 0x0 10. "BRK0CMP1EN,BRK CMP1 enable" "0,1"
|
|
bitfld.long 0x0 9. "BRK0CMP0EN,BRK CMP0 enable" "0,1"
|
|
bitfld.long 0x0 8. "BRK0HPDFEN,BRK HPDF input enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BRK0IN0EN,BREAK0 BRKIN0 alternate function input enable" "0,1"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "CREP1,Counter repetition register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CREP1,Counter repetition value 1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 3. "CCUSEL,Commutation control shadow register update select" "0,1"
|
|
bitfld.long 0x0 2. "CREPSEL,The counter repetition register select" "0,1"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
bitfld.long 0x0 0. "OUTSEL,The output value selection" "0,1"
|
|
tree.end
|
|
tree "TIMER15"
|
|
base ad:0x40014400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 30.--31. "CCUC,Commutation control shadow register update control" "0,1,2,3"
|
|
bitfld.long 0x4 9. "ISO0N,Idle state of multi mode channel 0 complementary output" "0,1"
|
|
bitfld.long 0x4 8. "ISO0,Idle state of channel 0 output" "0,1"
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0x0 24. "MCH0DEN,Multi mode channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0x0 20. "MCH0IE,Multi mode channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0x0 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 7. "BRKIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "CMTIE,Commutation interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "INTF,Interrupt flag register"
|
|
bitfld.long 0x4 24. "MCH0OF,Multi mode channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x4 20. "MCH0IF,Multi mode channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x4 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x4 7. "BRK0IF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "CMTIF,Channel commutation interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 20. "MCH0G,Multi mode channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 7. "BRK0G,Break event generation" "0,1"
|
|
bitfld.long 0x0 5. "CMTG,Channel commutation event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 3 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output"
|
|
bitfld.long 0x0 30. "CH0MS_2,Channel 0 I/O mode selection" "0,1"
|
|
bitfld.long 0x0 16. "CH2COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input"
|
|
bitfld.long 0x0 30. "CH0MS_2,Channel 0 I/O mode selection" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x0 3. "MCH0P,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x0 2. "MCH0EN,Multi mode channel 0 capture/compare enable" "0,1"
|
|
bitfld.long 0x0 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x0 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
bitfld.long 0x4 31. "UPIFBU,UPIF bit backup" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,current counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0xC "CAR,Counter auto reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CARL,Counter auto reload value"
|
|
line.long 0x10 "CREP0,Counter repetition register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "CREP0,Counter repetition value"
|
|
line.long 0x14 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "CCHP,channel complementary protection register"
|
|
bitfld.long 0x0 28. "BRK0LK,BREAK0 input locked" "0,1"
|
|
bitfld.long 0x0 26. "BRK0REL,BREAK0 input released" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BRK0F,BREAK0 input signal filter"
|
|
bitfld.long 0x0 15. "POEN,Primary output enable" "0,1"
|
|
bitfld.long 0x0 14. "OAEN,Output automatic enable" "0,1"
|
|
bitfld.long 0x0 13. "BRK0P,BREAK0 input signal polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "BRK0EN,BREAK0 input signal enable" "0,1"
|
|
bitfld.long 0x0 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x0 10. "IOS,Idle mode off-state configure" "0,1"
|
|
bitfld.long 0x0 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0x4 "MCHCTL0_Output,Multi mode channel control register 0 (output"
|
|
bitfld.long 0x4 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
bitfld.long 0x4 16. "MCH0COMCTL_3,Multi mode channel 0 compare output control." "0,1"
|
|
bitfld.long 0x4 7. "MCH0COMCEN,Multi mode channel 0 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "MCH0COMCTL,Multi mode channel 0 output compare control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "MCH0COMSEN,Multi mode channel 0 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "MCHCTL0_Input,Multi mode channel control register 0 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MCH0CAPFLT,Multi mode channel 0 input capture filter control"
|
|
bitfld.long 0x0 2.--3. "MCH0CAPPSC,Multi mode channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x50++0x7
|
|
line.long 0x0 "MCHFCTL2,Multi mode channel control register 2"
|
|
bitfld.long 0x0 0.--1. "MCH0FP,Multi mode channel 0 capture/compare free polarity" "0,1,2,3"
|
|
line.long 0x4 "MCH0CV,Multi mode channel 0 capture/compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "MCH0VAL,Capture/compare value of multi mode channel 0"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "CTL2,Control register 2"
|
|
bitfld.long 0x0 20.--21. "MCH0MSEL,Multi mode channel 0 mode select" "0,1,2,3"
|
|
bitfld.long 0x0 4. "BRKENCH0,Break control enable for channel 0" "0,1"
|
|
bitfld.long 0x0 0. "DTIENCH0,Dead time inserted enable for channel 0" "0,1"
|
|
group.long 0x7C++0x3
|
|
line.long 0x0 "FCCHP0,Free complementary channel protection register 0"
|
|
bitfld.long 0x0 31. "FCCHP0EN,Free complementary channel protection register 0 enable" "0,1"
|
|
bitfld.long 0x0 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x0 10. "IOS,Idle mode off-state configure" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configure"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "AFCTL0,alternate function control register 0"
|
|
bitfld.long 0x0 26. "BRK0CMP1P,BRK CMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 25. "BRK0CMP0P,BRK CMP0 input polarity" "0,1"
|
|
bitfld.long 0x0 16. "BRK0IN0P,BREAK0 BRKIN0 alternate function input polarity" "0,1"
|
|
bitfld.long 0x0 10. "BRK0CMP1EN,BRK CMP1 enable" "0,1"
|
|
bitfld.long 0x0 9. "BRK0CMP0EN,BRK CMP0 enable" "0,1"
|
|
bitfld.long 0x0 8. "BRK0HPDFEN,BRK HPDF input enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BRK0IN0EN,BREAK0 BRKIN0 alternate function input enable" "0,1"
|
|
group.long 0x94++0x7
|
|
line.long 0x0 "WDGPER,Watchdog counter register"
|
|
hexmask.long 0x0 0.--31. 1. "WDGPER,Watchdog timeout count"
|
|
line.long 0x4 "CREP1,Counter repetition register 1"
|
|
hexmask.long 0x4 0.--31. 1. "CREP1,Counter repetition value 1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 3. "CCUSEL,Commutation control shadow register update select" "0,1"
|
|
bitfld.long 0x0 2. "CREPSEL,The counter repetition register select" "0,1"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
bitfld.long 0x0 0. "OUTSEL,The output value selection" "0,1"
|
|
tree.end
|
|
tree "TIMER16"
|
|
base ad:0x40014800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 30.--31. "CCUC,Commutation control shadow register update control" "0,1,2,3"
|
|
bitfld.long 0x4 9. "ISO0N,Idle state of multi mode channel 0 complementary output" "0,1"
|
|
bitfld.long 0x4 8. "ISO0,Idle state of channel 0 output" "0,1"
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0x0 24. "MCH0DEN,Multi mode channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0x0 20. "MCH0IE,Multi mode channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0x0 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 7. "BRKIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "CMTIE,Commutation interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "INTF,Interrupt flag register"
|
|
bitfld.long 0x4 24. "MCH0OF,Multi mode channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x4 20. "MCH0IF,Multi mode channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x4 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x4 7. "BRK0IF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "CMTIF,Channel commutation interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 20. "MCH0G,Multi mode channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 7. "BRK0G,Break event generation" "0,1"
|
|
bitfld.long 0x0 5. "CMTG,Channel commutation event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 3 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output"
|
|
bitfld.long 0x0 30. "CH0MS_2,Channel 0 I/O mode selection" "0,1"
|
|
bitfld.long 0x0 16. "CH2COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input"
|
|
bitfld.long 0x0 30. "CH0MS_2,Channel 0 I/O mode selection" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x0 3. "MCH0P,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x0 2. "MCH0EN,Multi mode channel 0 capture/compare enable" "0,1"
|
|
bitfld.long 0x0 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x0 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
bitfld.long 0x4 31. "UPIFBU,UPIF bit backup" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,current counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0xC "CAR,Counter auto reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CARL,Counter auto reload value"
|
|
line.long 0x10 "CREP0,Counter repetition register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "CREP0,Counter repetition value"
|
|
line.long 0x14 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "CCHP,channel complementary protection register"
|
|
bitfld.long 0x0 28. "BRK0LK,BREAK0 input locked" "0,1"
|
|
bitfld.long 0x0 26. "BRK0REL,BREAK0 input released" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BRK0F,BREAK0 input signal filter"
|
|
bitfld.long 0x0 15. "POEN,Primary output enable" "0,1"
|
|
bitfld.long 0x0 14. "OAEN,Output automatic enable" "0,1"
|
|
bitfld.long 0x0 13. "BRK0P,BREAK0 input signal polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "BRK0EN,BREAK0 input signal enable" "0,1"
|
|
bitfld.long 0x0 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x0 10. "IOS,Idle mode off-state configure" "0,1"
|
|
bitfld.long 0x0 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0x4 "MCHCTL0_Output,Multi mode channel control register 0 (output"
|
|
bitfld.long 0x4 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
bitfld.long 0x4 16. "MCH0COMCTL_3,Multi mode channel 0 compare output control." "0,1"
|
|
bitfld.long 0x4 7. "MCH0COMCEN,Multi mode channel 0 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "MCH0COMCTL,Multi mode channel 0 output compare control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "MCH0COMSEN,Multi mode channel 0 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "MCHCTL0_Input,Multi mode channel control register 0 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MCH0CAPFLT,Multi mode channel 0 input capture filter control"
|
|
bitfld.long 0x0 2.--3. "MCH0CAPPSC,Multi mode channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x50++0x7
|
|
line.long 0x0 "MCHFCTL2,Multi mode channel control register 2"
|
|
bitfld.long 0x0 0.--1. "MCH0FP,Multi mode channel 0 capture/compare free polarity" "0,1,2,3"
|
|
line.long 0x4 "MCH0CV,Multi mode channel 0 capture/compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "MCH0VAL,Capture/compare value of multi mode channel 0"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "CTL2,Control register 2"
|
|
bitfld.long 0x0 20.--21. "MCH0MSEL,Multi mode channel 0 mode select" "0,1,2,3"
|
|
bitfld.long 0x0 4. "BRKENCH0,Break control enable for channel 0" "0,1"
|
|
bitfld.long 0x0 0. "DTIENCH0,Dead time inserted enable for channel 0" "0,1"
|
|
group.long 0x7C++0x3
|
|
line.long 0x0 "FCCHP0,Free complementary channel protection register 0"
|
|
bitfld.long 0x0 31. "FCCHP0EN,Free complementary channel protection register 0 enable" "0,1"
|
|
bitfld.long 0x0 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x0 10. "IOS,Idle mode off-state configure" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configure"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "AFCTL0,alternate function control register 0"
|
|
bitfld.long 0x0 26. "BRK0CMP1P,BRK CMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 25. "BRK0CMP0P,BRK CMP0 input polarity" "0,1"
|
|
bitfld.long 0x0 16. "BRK0IN0P,BREAK0 BRKIN0 alternate function input polarity" "0,1"
|
|
bitfld.long 0x0 10. "BRK0CMP1EN,BRK CMP1 enable" "0,1"
|
|
bitfld.long 0x0 9. "BRK0CMP0EN,BRK CMP0 enable" "0,1"
|
|
bitfld.long 0x0 8. "BRK0HPDFEN,BRK HPDF input enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BRK0IN0EN,BREAK0 BRKIN0 alternate function input enable" "0,1"
|
|
group.long 0x94++0x7
|
|
line.long 0x0 "WDGPER,Watchdog counter register"
|
|
hexmask.long 0x0 0.--31. 1. "WDGPER,Watchdog timeout count"
|
|
line.long 0x4 "CREP1,Counter repetition register 1"
|
|
hexmask.long 0x4 0.--31. 1. "CREP1,Counter repetition value 1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 3. "CCUSEL,Commutation control shadow register update select" "0,1"
|
|
bitfld.long 0x0 2. "CREPSEL,The counter repetition register select" "0,1"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
bitfld.long 0x0 0. "OUTSEL,The output value selection" "0,1"
|
|
tree.end
|
|
tree "TIMER22"
|
|
base ad:0x4000E000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
line.long 0x8 "SMCFG,Slave mode configuration register"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "SMC1,Part of SMC is used to enable external clock mode 1" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETFC,External trigger filter control"
|
|
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
|
|
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0xC 31. "CH3COMADDIE,Channel 3 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 30. "CH2COMADDIE,Channel 2 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 17. "DECDISIE,Quadrature decoder signal disconnection interrupt enable" "0,1"
|
|
bitfld.long 0xC 16. "DECJIE,Quadrature decoder signal jump (the two signals jump at the same time) interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CH3DEN,Channel 3 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 11. "CH2DEN,Channel 2 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CH3IE,Channel 3 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CH2IE,Channel 2 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "INTF,Interrupt flag register"
|
|
bitfld.long 0x10 31. "CH3COMADDIF,Channel 3 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 30. "CH2COMADDIF,Channel 2 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "DECDISIF,Quadrature decoder signal disconnection interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "DECJIF,Quadrature decoder signal jump (the two signals jump at the same time) interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CH3OF,Channel 3 over capture flag" "0,1"
|
|
bitfld.long 0x10 11. "CH2OF,Channel 2 over capture flag" "0,1"
|
|
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
|
|
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CH3IF,Channel 3 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CH2IF,Channel 2 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 31. "CH3COMADDG,Channel 3 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 30. "CH2COMADDG,Channel 2 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
|
|
bitfld.long 0x0 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL1_Output,Channel control register 1 (output"
|
|
bitfld.long 0x4 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x4 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
bitfld.long 0x4 29. "CH3COMADDSEN,Channel 3 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 28. "CH2COMADDSEN,Channel 2 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 24. "CH3COMCTL_3,BIT 3 of channel 3 compare output control" "0,1"
|
|
bitfld.long 0x4 23. "CH2COMCTL_3,BIT 3 of channel 2 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
bitfld.long 0x4 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CHCTL1_Input,Channel control register 1 (input"
|
|
bitfld.long 0x0 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x0 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH3CAPFLT,Channel 3 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH2CAPFLT,Channel 2 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x4 15. "CH3NP,Multi mode channel 3 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 13. "CH3P,Channel 3 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 12. "CH3EN,Channel 3 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 11. "CH2NP,Multi mode channel 2 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 9. "CH2P,Channel 2 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 8. "CH2EN,Channel 2 capture/compare function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CH1NP,Multi mode channel 1 output polarity" "0,1"
|
|
bitfld.long 0x4 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 3. "CH0NP,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x4 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long 0x8 0.--31. 1. "CNT,current counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0x10 "CAR,Counter auto reload register"
|
|
hexmask.long 0x10 0.--31. 1. "CARL,Counter auto reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long 0x0 0.--31. 1. "CH0VAL,Capture or compare value of channel0"
|
|
line.long 0x4 "CH1CV,Channel 1 capture/compare value register"
|
|
hexmask.long 0x4 0.--31. 1. "CH1VAL,Capture or compare value of channel1"
|
|
line.long 0x8 "CH2CV,Channel 2 capture/compare value register"
|
|
hexmask.long 0x8 0.--31. 1. "CH2VAL,Capture or compare value of channel 2"
|
|
line.long 0xC "CH3CV,Channel 3 capture/compare value register"
|
|
hexmask.long 0xC 0.--31. 1. "CH3VAL,Capture or compare value of channel 3"
|
|
group.long 0x64++0x13
|
|
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
|
|
hexmask.long 0x0 0.--31. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
|
|
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
|
|
hexmask.long 0x4 0.--31. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
|
|
line.long 0x8 "CH2COMV_ADD,Channel 2 additional compare value register"
|
|
hexmask.long 0x8 0.--31. 1. "CH2COMVAL_ADD,Additional compare value of channel 2"
|
|
line.long 0xC "CH3COMV_ADD,Channel 3 additional compare value register"
|
|
hexmask.long 0xC 0.--31. 1. "CH3COMVAL_ADD,Additional compare value of channel 3"
|
|
line.long 0x10 "CTL2,Control register 2"
|
|
bitfld.long 0x10 31. "CH3CPWMEN,Channel 3 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 30. "CH2CPWMEN,Channel 2 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
|
|
bitfld.long 0x10 18. "DECJDEN,Quadrature decoder signal jump detection enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14.--15. "CH3OMPSEL,Channel 3 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "CH2OMPSEL,Channel 2 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "WDGPER,Watchdog counter register"
|
|
hexmask.long 0x0 0.--31. 1. "WDGPER,Watchdog timeout count"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
tree.end
|
|
tree "TIMER23"
|
|
base ad:0x4000E400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
line.long 0x8 "SMCFG,Slave mode configuration register"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "SMC1,Part of SMC is used to enable external clock mode 1" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETFC,External trigger filter control"
|
|
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
|
|
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0xC 31. "CH3COMADDIE,Channel 3 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 30. "CH2COMADDIE,Channel 2 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 17. "DECDISIE,Quadrature decoder signal disconnection interrupt enable" "0,1"
|
|
bitfld.long 0xC 16. "DECJIE,Quadrature decoder signal jump (the two signals jump at the same time) interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CH3DEN,Channel 3 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 11. "CH2DEN,Channel 2 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CH3IE,Channel 3 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CH2IE,Channel 2 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "INTF,Interrupt flag register"
|
|
bitfld.long 0x10 31. "CH3COMADDIF,Channel 3 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 30. "CH2COMADDIF,Channel 2 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "DECDISIF,Quadrature decoder signal disconnection interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "DECJIF,Quadrature decoder signal jump (the two signals jump at the same time) interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CH3OF,Channel 3 over capture flag" "0,1"
|
|
bitfld.long 0x10 11. "CH2OF,Channel 2 over capture flag" "0,1"
|
|
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
|
|
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CH3IF,Channel 3 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CH2IF,Channel 2 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 31. "CH3COMADDG,Channel 3 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 30. "CH2COMADDG,Channel 2 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
|
|
bitfld.long 0x0 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL1_Output,Channel control register 1 (output"
|
|
bitfld.long 0x4 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x4 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
bitfld.long 0x4 29. "CH3COMADDSEN,Channel 3 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 28. "CH2COMADDSEN,Channel 2 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 24. "CH3COMCTL_3,BIT 3 of channel 3 compare output control" "0,1"
|
|
bitfld.long 0x4 23. "CH2COMCTL_3,BIT 3 of channel 2 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
bitfld.long 0x4 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CHCTL1_Input,Channel control register 1 (input"
|
|
bitfld.long 0x0 31. "CH3MS_2,2th bit of CH3MS" "0,1"
|
|
bitfld.long 0x0 30. "CH2MS_2,2th bit of CH2MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH3CAPFLT,Channel 3 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH2CAPFLT,Channel 2 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
|
|
line.long 0x4 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x4 15. "CH3NP,Multi mode channel 3 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 13. "CH3P,Channel 3 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 12. "CH3EN,Channel 3 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 11. "CH2NP,Multi mode channel 2 capture/compare polarity" "0,1"
|
|
bitfld.long 0x4 9. "CH2P,Channel 2 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 8. "CH2EN,Channel 2 capture/compare function enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CH1NP,Multi mode channel 1 output polarity" "0,1"
|
|
bitfld.long 0x4 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
|
|
bitfld.long 0x4 3. "CH0NP,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x4 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x4 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long 0x8 0.--31. 1. "CNT,current counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0x10 "CAR,Counter auto reload register"
|
|
hexmask.long 0x10 0.--31. 1. "CARL,Counter auto reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long 0x0 0.--31. 1. "CH0VAL,Capture or compare value of channel0"
|
|
line.long 0x4 "CH1CV,Channel 1 capture/compare value register"
|
|
hexmask.long 0x4 0.--31. 1. "CH1VAL,Capture or compare value of channel1"
|
|
line.long 0x8 "CH2CV,Channel 2 capture/compare value register"
|
|
hexmask.long 0x8 0.--31. 1. "CH2VAL,Capture or compare value of channel 2"
|
|
line.long 0xC "CH3CV,Channel 3 capture/compare value register"
|
|
hexmask.long 0xC 0.--31. 1. "CH3VAL,Capture or compare value of channel 3"
|
|
group.long 0x64++0x13
|
|
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
|
|
hexmask.long 0x0 0.--31. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
|
|
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
|
|
hexmask.long 0x4 0.--31. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
|
|
line.long 0x8 "CH2COMV_ADD,Channel 2 additional compare value register"
|
|
hexmask.long 0x8 0.--31. 1. "CH2COMVAL_ADD,Additional compare value of channel 2"
|
|
line.long 0xC "CH3COMV_ADD,Channel 3 additional compare value register"
|
|
hexmask.long 0xC 0.--31. 1. "CH3COMVAL_ADD,Additional compare value of channel 3"
|
|
line.long 0x10 "CTL2,Control register 2"
|
|
bitfld.long 0x10 31. "CH3CPWMEN,Channel 3 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 30. "CH2CPWMEN,Channel 2 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x10 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
|
|
bitfld.long 0x10 18. "DECJDEN,Quadrature decoder signal jump detection enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14.--15. "CH3OMPSEL,Channel 3 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "CH2OMPSEL,Channel 2 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "WDGPER,Watchdog counter register"
|
|
hexmask.long 0x0 0.--31. 1. "WDGPER,Watchdog timeout count"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
tree.end
|
|
tree "TIMER40"
|
|
base ad:0x4001D000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 30.--31. "CCUC,Commutation control shadow register update control" "0,1,2,3"
|
|
bitfld.long 0x4 10. "ISO1,Idle state of channel 1 output" "0,1"
|
|
bitfld.long 0x4 9. "ISO0N,Idle state of multi mode channel 0 complementary output" "0,1"
|
|
bitfld.long 0x4 8. "ISO0,Idle state of channel 0 output" "0,1"
|
|
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
line.long 0x8 "SMCFG,Slave mode configuration register"
|
|
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
|
|
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 24. "MCH0DEN,Multi mode channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 20. "MCH0IE,Multi mode channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "CMTDEN,Commutation DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BRKIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "CMTIE,Commutation interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "INTF,Interrupt flag register"
|
|
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 24. "MCH0OF,Multi mode channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 20. "MCH0IF,Multi mode channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SYSBIF,SYSBIF" "0,1"
|
|
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 7. "BRK0IF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 5. "CMTIF,Channel commutation interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 20. "MCH0G,Multi mode channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 7. "BRK0G,Break event generation" "0,1"
|
|
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
|
|
bitfld.long 0x0 5. "CMTG,Channel commutation event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 0 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x0 7. "MCH1P,Multi mode channel 1 output polarity" "0,1"
|
|
bitfld.long 0x0 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x0 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
|
|
bitfld.long 0x0 3. "MCH0P,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x0 2. "MCH0EN,Multi mode channel 0 capture/compare enable" "0,1"
|
|
bitfld.long 0x0 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
bitfld.long 0x4 31. "UPIFBU,UPIF bit backup" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,current counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0xC "CAR,Counter auto reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CARL,Counter auto reload value"
|
|
line.long 0x10 "CREP0,Counter repetition register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "CREP0,Counter repetition value"
|
|
line.long 0x14 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
|
|
line.long 0x18 "CH1CV,Channel 1 capture/compare value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "CH1VAL,Capture or compare value of channel1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "CCHP,channel complementary protection register"
|
|
bitfld.long 0x0 28. "BRK0LK,BREAK0 input locked" "0,1"
|
|
bitfld.long 0x0 26. "BRK0REL,BREAK0 input released" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BRK0F,BREAK0 input signal filter"
|
|
bitfld.long 0x0 15. "POEN,Primary output enable" "0,1"
|
|
bitfld.long 0x0 14. "OAEN,Output automatic enable" "0,1"
|
|
bitfld.long 0x0 13. "BRK0P,BREAK0 input signal polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "BRK0EN,BREAK0 input signal enable" "0,1"
|
|
bitfld.long 0x0 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x0 10. "IOS,Idle mode off-state configure" "0,1"
|
|
bitfld.long 0x0 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0x4 "MCHCTL0_Output,Multi mode channel control register 0 (output"
|
|
bitfld.long 0x4 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
bitfld.long 0x4 16. "MCH0COMCTL_3,Multi mode channel 0 compare output control" "0,1"
|
|
bitfld.long 0x4 8.--9. "MCH1MS,Multi mode channel 1 I/O mode selection" "0,1,2,3"
|
|
bitfld.long 0x4 4.--6. "MCH0COMCTL,Multi mode channel 0 output compare control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "MCH0COMSEN,Multi mode channel 0 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "MCHCTL0_Input,Multi mode channel control register 0 (input"
|
|
bitfld.long 0x0 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MCH0CAPFLT,Multi mode channel 0 input capture filter control"
|
|
bitfld.long 0x0 2.--3. "MCH0CAPPSC,Multi mode channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x50++0x7
|
|
line.long 0x0 "MCHFCTL2,Multi mode channel control register 2"
|
|
bitfld.long 0x0 0.--1. "MCH0FP,Multi mode channel 0 capture/compare free polarity" "0,1,2,3"
|
|
line.long 0x4 "MCH0CV,Multi mode channel 0 capture/compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "MCH0VAL,Capture/compare value of multi mode channel 0"
|
|
group.long 0x64++0x7
|
|
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
|
|
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "CTL2,Control register 2"
|
|
bitfld.long 0x0 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x0 20.--21. "MCH0MSEL,Multi mode channel 0 mode select" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "AFCTL0,alternate function control register 0"
|
|
bitfld.long 0x0 26. "BRK0CMP1P,BRK CMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 25. "BRK0CMP0P,BRK CMP0 input polarity" "0,1"
|
|
bitfld.long 0x0 16. "BRK0IN0P,BREAK0 BRKIN0 alternate function input polarity" "0,1"
|
|
bitfld.long 0x0 10. "BRK0CMP1EN,BRK CMP1 enable" "0,1"
|
|
bitfld.long 0x0 9. "BRK0CMP0EN,BRK CMP0 enable" "0,1"
|
|
bitfld.long 0x0 8. "BRK0HPDFEN,BRK HPDF input enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BRK0IN0EN,BREAK0 BRKIN0 alternate function input enable" "0,1"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "CREP1,Counter repetition register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CREP1,Counter repetition value 1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 3. "CCUSEL,Commutation control shadow register update select" "0,1"
|
|
bitfld.long 0x0 2. "CREPSEL,The counter repetition register select" "0,1"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
bitfld.long 0x0 0. "OUTSEL,The output value selection" "0,1"
|
|
tree.end
|
|
tree "TIMER41"
|
|
base ad:0x4001D400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 30.--31. "CCUC,Commutation control shadow register update control" "0,1,2,3"
|
|
bitfld.long 0x4 10. "ISO1,Idle state of channel 1 output" "0,1"
|
|
bitfld.long 0x4 9. "ISO0N,Idle state of multi mode channel 0 complementary output" "0,1"
|
|
bitfld.long 0x4 8. "ISO0,Idle state of channel 0 output" "0,1"
|
|
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
line.long 0x8 "SMCFG,Slave mode configuration register"
|
|
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
|
|
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 24. "MCH0DEN,Multi mode channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 20. "MCH0IE,Multi mode channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "CMTDEN,Commutation DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BRKIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "CMTIE,Commutation interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "INTF,Interrupt flag register"
|
|
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 24. "MCH0OF,Multi mode channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 20. "MCH0IF,Multi mode channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SYSBIF,SYSBIF" "0,1"
|
|
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 7. "BRK0IF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 5. "CMTIF,Channel commutation interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 20. "MCH0G,Multi mode channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 7. "BRK0G,Break event generation" "0,1"
|
|
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
|
|
bitfld.long 0x0 5. "CMTG,Channel commutation event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 0 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x0 7. "MCH1P,Multi mode channel 1 output polarity" "0,1"
|
|
bitfld.long 0x0 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x0 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
|
|
bitfld.long 0x0 3. "MCH0P,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x0 2. "MCH0EN,Multi mode channel 0 capture/compare enable" "0,1"
|
|
bitfld.long 0x0 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
bitfld.long 0x4 31. "UPIFBU,UPIF bit backup" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,current counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0xC "CAR,Counter auto reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CARL,Counter auto reload value"
|
|
line.long 0x10 "CREP0,Counter repetition register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "CREP0,Counter repetition value"
|
|
line.long 0x14 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
|
|
line.long 0x18 "CH1CV,Channel 1 capture/compare value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "CH1VAL,Capture or compare value of channel1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "CCHP,channel complementary protection register"
|
|
bitfld.long 0x0 28. "BRK0LK,BREAK0 input locked" "0,1"
|
|
bitfld.long 0x0 26. "BRK0REL,BREAK0 input released" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BRK0F,BREAK0 input signal filter"
|
|
bitfld.long 0x0 15. "POEN,Primary output enable" "0,1"
|
|
bitfld.long 0x0 14. "OAEN,Output automatic enable" "0,1"
|
|
bitfld.long 0x0 13. "BRK0P,BREAK0 input signal polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "BRK0EN,BREAK0 input signal enable" "0,1"
|
|
bitfld.long 0x0 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x0 10. "IOS,Idle mode off-state configure" "0,1"
|
|
bitfld.long 0x0 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0x4 "MCHCTL0_Output,Multi mode channel control register 0 (output"
|
|
bitfld.long 0x4 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
bitfld.long 0x4 16. "MCH0COMCTL_3,Multi mode channel 0 compare output control" "0,1"
|
|
bitfld.long 0x4 8.--9. "MCH1MS,Multi mode channel 1 I/O mode selection" "0,1,2,3"
|
|
bitfld.long 0x4 4.--6. "MCH0COMCTL,Multi mode channel 0 output compare control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "MCH0COMSEN,Multi mode channel 0 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "MCHCTL0_Input,Multi mode channel control register 0 (input"
|
|
bitfld.long 0x0 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MCH0CAPFLT,Multi mode channel 0 input capture filter control"
|
|
bitfld.long 0x0 2.--3. "MCH0CAPPSC,Multi mode channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x50++0x7
|
|
line.long 0x0 "MCHFCTL2,Multi mode channel control register 2"
|
|
bitfld.long 0x0 0.--1. "MCH0FP,Multi mode channel 0 capture/compare free polarity" "0,1,2,3"
|
|
line.long 0x4 "MCH0CV,Multi mode channel 0 capture/compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "MCH0VAL,Capture/compare value of multi mode channel 0"
|
|
group.long 0x64++0x7
|
|
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
|
|
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "CTL2,Control register 2"
|
|
bitfld.long 0x0 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x0 20.--21. "MCH0MSEL,Multi mode channel 0 mode select" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "AFCTL0,alternate function control register 0"
|
|
bitfld.long 0x0 26. "BRK0CMP1P,BRK CMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 25. "BRK0CMP0P,BRK CMP0 input polarity" "0,1"
|
|
bitfld.long 0x0 16. "BRK0IN0P,BREAK0 BRKIN0 alternate function input polarity" "0,1"
|
|
bitfld.long 0x0 10. "BRK0CMP1EN,BRK CMP1 enable" "0,1"
|
|
bitfld.long 0x0 9. "BRK0CMP0EN,BRK CMP0 enable" "0,1"
|
|
bitfld.long 0x0 8. "BRK0HPDFEN,BRK HPDF input enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BRK0IN0EN,BREAK0 BRKIN0 alternate function input enable" "0,1"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "CREP1,Counter repetition register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CREP1,Counter repetition value 1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 3. "CCUSEL,Commutation control shadow register update select" "0,1"
|
|
bitfld.long 0x0 2. "CREPSEL,The counter repetition register select" "0,1"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
bitfld.long 0x0 0. "OUTSEL,The output value selection" "0,1"
|
|
tree.end
|
|
tree "TIMER42"
|
|
base ad:0x4001D800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 30.--31. "CCUC,Commutation control shadow register update control" "0,1,2,3"
|
|
bitfld.long 0x4 10. "ISO1,Idle state of channel 1 output" "0,1"
|
|
bitfld.long 0x4 9. "ISO0N,Idle state of multi mode channel 0 complementary output" "0,1"
|
|
bitfld.long 0x4 8. "ISO0,Idle state of channel 0 output" "0,1"
|
|
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
line.long 0x8 "SMCFG,Slave mode configuration register"
|
|
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
|
|
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 24. "MCH0DEN,Multi mode channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 20. "MCH0IE,Multi mode channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "CMTDEN,Commutation DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BRKIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "CMTIE,Commutation interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "INTF,Interrupt flag register"
|
|
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 24. "MCH0OF,Multi mode channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 20. "MCH0IF,Multi mode channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SYSBIF,SYSBIF" "0,1"
|
|
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 7. "BRK0IF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 5. "CMTIF,Channel commutation interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 20. "MCH0G,Multi mode channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 7. "BRK0G,Break event generation" "0,1"
|
|
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
|
|
bitfld.long 0x0 5. "CMTG,Channel commutation event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 0 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x0 7. "MCH1P,Multi mode channel 1 output polarity" "0,1"
|
|
bitfld.long 0x0 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x0 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
|
|
bitfld.long 0x0 3. "MCH0P,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x0 2. "MCH0EN,Multi mode channel 0 capture/compare enable" "0,1"
|
|
bitfld.long 0x0 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
bitfld.long 0x4 31. "UPIFBU,UPIF bit backup" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,current counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0xC "CAR,Counter auto reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CARL,Counter auto reload value"
|
|
line.long 0x10 "CREP0,Counter repetition register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "CREP0,Counter repetition value"
|
|
line.long 0x14 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
|
|
line.long 0x18 "CH1CV,Channel 1 capture/compare value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "CH1VAL,Capture or compare value of channel1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "CCHP,channel complementary protection register"
|
|
bitfld.long 0x0 28. "BRK0LK,BREAK0 input locked" "0,1"
|
|
bitfld.long 0x0 26. "BRK0REL,BREAK0 input released" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BRK0F,BREAK0 input signal filter"
|
|
bitfld.long 0x0 15. "POEN,Primary output enable" "0,1"
|
|
bitfld.long 0x0 14. "OAEN,Output automatic enable" "0,1"
|
|
bitfld.long 0x0 13. "BRK0P,BREAK0 input signal polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "BRK0EN,BREAK0 input signal enable" "0,1"
|
|
bitfld.long 0x0 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x0 10. "IOS,Idle mode off-state configure" "0,1"
|
|
bitfld.long 0x0 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0x4 "MCHCTL0_Output,Multi mode channel control register 0 (output"
|
|
bitfld.long 0x4 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
bitfld.long 0x4 16. "MCH0COMCTL_3,Multi mode channel 0 compare output control" "0,1"
|
|
bitfld.long 0x4 8.--9. "MCH1MS,Multi mode channel 1 I/O mode selection" "0,1,2,3"
|
|
bitfld.long 0x4 4.--6. "MCH0COMCTL,Multi mode channel 0 output compare control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "MCH0COMSEN,Multi mode channel 0 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "MCHCTL0_Input,Multi mode channel control register 0 (input"
|
|
bitfld.long 0x0 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MCH0CAPFLT,Multi mode channel 0 input capture filter control"
|
|
bitfld.long 0x0 2.--3. "MCH0CAPPSC,Multi mode channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x50++0x7
|
|
line.long 0x0 "MCHFCTL2,Multi mode channel control register 2"
|
|
bitfld.long 0x0 0.--1. "MCH0FP,Multi mode channel 0 capture/compare free polarity" "0,1,2,3"
|
|
line.long 0x4 "MCH0CV,Multi mode channel 0 capture/compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "MCH0VAL,Capture/compare value of multi mode channel 0"
|
|
group.long 0x64++0x7
|
|
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
|
|
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "CTL2,Control register 2"
|
|
bitfld.long 0x0 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x0 20.--21. "MCH0MSEL,Multi mode channel 0 mode select" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "AFCTL0,alternate function control register 0"
|
|
bitfld.long 0x0 26. "BRK0CMP1P,BRK CMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 25. "BRK0CMP0P,BRK CMP0 input polarity" "0,1"
|
|
bitfld.long 0x0 16. "BRK0IN0P,BREAK0 BRKIN0 alternate function input polarity" "0,1"
|
|
bitfld.long 0x0 10. "BRK0CMP1EN,BRK CMP1 enable" "0,1"
|
|
bitfld.long 0x0 9. "BRK0CMP0EN,BRK CMP0 enable" "0,1"
|
|
bitfld.long 0x0 8. "BRK0HPDFEN,BRK HPDF input enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BRK0IN0EN,BREAK0 BRKIN0 alternate function input enable" "0,1"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "CREP1,Counter repetition register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CREP1,Counter repetition value 1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 3. "CCUSEL,Commutation control shadow register update select" "0,1"
|
|
bitfld.long 0x0 2. "CREPSEL,The counter repetition register select" "0,1"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
bitfld.long 0x0 0. "OUTSEL,The output value selection" "0,1"
|
|
tree.end
|
|
tree "TIMER43"
|
|
base ad:0x4001DC00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 30.--31. "CCUC,Commutation control shadow register update control" "0,1,2,3"
|
|
bitfld.long 0x4 10. "ISO1,Idle state of channel 1 output" "0,1"
|
|
bitfld.long 0x4 9. "ISO0N,Idle state of multi mode channel 0 complementary output" "0,1"
|
|
bitfld.long 0x4 8. "ISO0,Idle state of channel 0 output" "0,1"
|
|
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
line.long 0x8 "SMCFG,Slave mode configuration register"
|
|
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
|
|
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 24. "MCH0DEN,Multi mode channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 20. "MCH0IE,Multi mode channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "CMTDEN,Commutation DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BRKIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "CMTIE,Commutation interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "INTF,Interrupt flag register"
|
|
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 24. "MCH0OF,Multi mode channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 20. "MCH0IF,Multi mode channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SYSBIF,SYSBIF" "0,1"
|
|
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 7. "BRK0IF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 5. "CMTIF,Channel commutation interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 20. "MCH0G,Multi mode channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 7. "BRK0G,Break event generation" "0,1"
|
|
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
|
|
bitfld.long 0x0 5. "CMTG,Channel commutation event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 0 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x0 7. "MCH1P,Multi mode channel 1 output polarity" "0,1"
|
|
bitfld.long 0x0 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x0 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
|
|
bitfld.long 0x0 3. "MCH0P,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x0 2. "MCH0EN,Multi mode channel 0 capture/compare enable" "0,1"
|
|
bitfld.long 0x0 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
bitfld.long 0x4 31. "UPIFBU,UPIF bit backup" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,current counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0xC "CAR,Counter auto reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CARL,Counter auto reload value"
|
|
line.long 0x10 "CREP0,Counter repetition register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "CREP0,Counter repetition value"
|
|
line.long 0x14 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
|
|
line.long 0x18 "CH1CV,Channel 1 capture/compare value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "CH1VAL,Capture or compare value of channel1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "CCHP,channel complementary protection register"
|
|
bitfld.long 0x0 28. "BRK0LK,BREAK0 input locked" "0,1"
|
|
bitfld.long 0x0 26. "BRK0REL,BREAK0 input released" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BRK0F,BREAK0 input signal filter"
|
|
bitfld.long 0x0 15. "POEN,Primary output enable" "0,1"
|
|
bitfld.long 0x0 14. "OAEN,Output automatic enable" "0,1"
|
|
bitfld.long 0x0 13. "BRK0P,BREAK0 input signal polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "BRK0EN,BREAK0 input signal enable" "0,1"
|
|
bitfld.long 0x0 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x0 10. "IOS,Idle mode off-state configure" "0,1"
|
|
bitfld.long 0x0 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0x4 "MCHCTL0_Output,Multi mode channel control register 0 (output"
|
|
bitfld.long 0x4 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
bitfld.long 0x4 16. "MCH0COMCTL_3,Multi mode channel 0 compare output control" "0,1"
|
|
bitfld.long 0x4 8.--9. "MCH1MS,Multi mode channel 1 I/O mode selection" "0,1,2,3"
|
|
bitfld.long 0x4 4.--6. "MCH0COMCTL,Multi mode channel 0 output compare control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "MCH0COMSEN,Multi mode channel 0 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "MCHCTL0_Input,Multi mode channel control register 0 (input"
|
|
bitfld.long 0x0 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MCH0CAPFLT,Multi mode channel 0 input capture filter control"
|
|
bitfld.long 0x0 2.--3. "MCH0CAPPSC,Multi mode channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x50++0x7
|
|
line.long 0x0 "MCHFCTL2,Multi mode channel control register 2"
|
|
bitfld.long 0x0 0.--1. "MCH0FP,Multi mode channel 0 capture/compare free polarity" "0,1,2,3"
|
|
line.long 0x4 "MCH0CV,Multi mode channel 0 capture/compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "MCH0VAL,Capture/compare value of multi mode channel 0"
|
|
group.long 0x64++0x7
|
|
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
|
|
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "CTL2,Control register 2"
|
|
bitfld.long 0x0 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x0 20.--21. "MCH0MSEL,Multi mode channel 0 mode select" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "AFCTL0,alternate function control register 0"
|
|
bitfld.long 0x0 26. "BRK0CMP1P,BRK CMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 25. "BRK0CMP0P,BRK CMP0 input polarity" "0,1"
|
|
bitfld.long 0x0 16. "BRK0IN0P,BREAK0 BRKIN0 alternate function input polarity" "0,1"
|
|
bitfld.long 0x0 10. "BRK0CMP1EN,BRK CMP1 enable" "0,1"
|
|
bitfld.long 0x0 9. "BRK0CMP0EN,BRK CMP0 enable" "0,1"
|
|
bitfld.long 0x0 8. "BRK0HPDFEN,BRK HPDF input enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BRK0IN0EN,BREAK0 BRKIN0 alternate function input enable" "0,1"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "CREP1,Counter repetition register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CREP1,Counter repetition value 1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 3. "CCUSEL,Commutation control shadow register update select" "0,1"
|
|
bitfld.long 0x0 2. "CREPSEL,The counter repetition register select" "0,1"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
bitfld.long 0x0 0. "OUTSEL,The output value selection" "0,1"
|
|
tree.end
|
|
tree "TIMER44"
|
|
base ad:0x4001F000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "UPS,Update source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
bitfld.long 0x4 30.--31. "CCUC,Commutation control shadow register update control" "0,1,2,3"
|
|
bitfld.long 0x4 10. "ISO1,Idle state of channel 1 output" "0,1"
|
|
bitfld.long 0x4 9. "ISO0N,Idle state of multi mode channel 0 complementary output" "0,1"
|
|
bitfld.long 0x4 8. "ISO0,Idle state of channel 0 output" "0,1"
|
|
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
|
|
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
|
|
line.long 0x8 "SMCFG,Slave mode configuration register"
|
|
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
|
|
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
|
|
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 24. "MCH0DEN,Multi mode channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 20. "MCH0IE,Multi mode channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "CMTDEN,Commutation DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BRKIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "CMTIE,Commutation interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "INTF,Interrupt flag register"
|
|
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 24. "MCH0OF,Multi mode channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 20. "MCH0IF,Multi mode channel 0 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SYSBIF,SYSBIF" "0,1"
|
|
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
|
|
bitfld.long 0x10 7. "BRK0IF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 5. "CMTIF,Channel commutation interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,Software event generation register"
|
|
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
|
|
bitfld.long 0x0 20. "MCH0G,Multi mode channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 7. "BRK0G,Break event generation" "0,1"
|
|
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
|
|
bitfld.long 0x0 5. "CMTG,Channel commutation event generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
|
|
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
|
|
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 0 compare output control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input"
|
|
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
|
|
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
|
|
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "CHCTL2,Channel control register 2"
|
|
bitfld.long 0x0 7. "MCH1P,Multi mode channel 1 output polarity" "0,1"
|
|
bitfld.long 0x0 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
|
|
bitfld.long 0x0 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
|
|
bitfld.long 0x0 3. "MCH0P,Multi mode channel 0 output polarity" "0,1"
|
|
bitfld.long 0x0 2. "MCH0EN,Multi mode channel 0 capture/compare enable" "0,1"
|
|
bitfld.long 0x0 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
bitfld.long 0x4 31. "UPIFBU,UPIF bit backup" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,current counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value of the counter clock"
|
|
line.long 0xC "CAR,Counter auto reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CARL,Counter auto reload value"
|
|
line.long 0x10 "CREP0,Counter repetition register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "CREP0,Counter repetition value"
|
|
line.long 0x14 "CH0CV,Channel 0 capture/compare value register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
|
|
line.long 0x18 "CH1CV,Channel 1 capture/compare value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "CH1VAL,Capture or compare value of channel1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "CCHP,channel complementary protection register"
|
|
bitfld.long 0x0 28. "BRK0LK,BREAK0 input locked" "0,1"
|
|
bitfld.long 0x0 26. "BRK0REL,BREAK0 input released" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BRK0F,BREAK0 input signal filter"
|
|
bitfld.long 0x0 15. "POEN,Primary output enable" "0,1"
|
|
bitfld.long 0x0 14. "OAEN,Output automatic enable" "0,1"
|
|
bitfld.long 0x0 13. "BRK0P,BREAK0 input signal polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "BRK0EN,BREAK0 input signal enable" "0,1"
|
|
bitfld.long 0x0 11. "ROS,Run mode off-state configure" "0,1"
|
|
bitfld.long 0x0 10. "IOS,Idle mode off-state configure" "0,1"
|
|
bitfld.long 0x0 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configure"
|
|
line.long 0x4 "MCHCTL0_Output,Multi mode channel control register 0 (output"
|
|
bitfld.long 0x4 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
bitfld.long 0x4 16. "MCH0COMCTL_3,Multi mode channel 0 compare output control" "0,1"
|
|
bitfld.long 0x4 8.--9. "MCH1MS,Multi mode channel 1 I/O mode selection" "0,1,2,3"
|
|
bitfld.long 0x4 4.--6. "MCH0COMCTL,Multi mode channel 0 output compare control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "MCH0COMSEN,Multi mode channel 0 output compare shadow enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "MCHCTL0_Input,Multi mode channel control register 0 (input"
|
|
bitfld.long 0x0 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MCH0CAPFLT,Multi mode channel 0 input capture filter control"
|
|
bitfld.long 0x0 2.--3. "MCH0CAPPSC,Multi mode channel 0 input capture prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
|
|
group.long 0x50++0x7
|
|
line.long 0x0 "MCHFCTL2,Multi mode channel control register 2"
|
|
bitfld.long 0x0 0.--1. "MCH0FP,Multi mode channel 0 capture/compare free polarity" "0,1,2,3"
|
|
line.long 0x4 "MCH0CV,Multi mode channel 0 capture/compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "MCH0VAL,Capture/compare value of multi mode channel 0"
|
|
group.long 0x64++0x7
|
|
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
|
|
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "CTL2,Control register 2"
|
|
bitfld.long 0x0 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x0 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
|
|
bitfld.long 0x0 20.--21. "MCH0MSEL,Multi mode channel 0 mode select" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "AFCTL0,alternate function control register 0"
|
|
bitfld.long 0x0 26. "BRK0CMP1P,BRK CMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 25. "BRK0CMP0P,BRK CMP0 input polarity" "0,1"
|
|
bitfld.long 0x0 16. "BRK0IN0P,BREAK0 BRKIN0 alternate function input polarity" "0,1"
|
|
bitfld.long 0x0 10. "BRK0CMP1EN,BRK CMP1 enable" "0,1"
|
|
bitfld.long 0x0 9. "BRK0CMP0EN,BRK CMP0 enable" "0,1"
|
|
bitfld.long 0x0 8. "BRK0HPDFEN,BRK HPDF input enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BRK0IN0EN,BREAK0 BRKIN0 alternate function input enable" "0,1"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "CREP1,Counter repetition register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CREP1,Counter repetition value 1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "DMACFG,DMA configuration register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
|
|
line.long 0x4 "DMATB,DMA transfer buffer register"
|
|
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "CFG,Configuration register"
|
|
bitfld.long 0x0 3. "CCUSEL,Commutation control shadow register update select" "0,1"
|
|
bitfld.long 0x0 2. "CREPSEL,The counter repetition register select" "0,1"
|
|
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection" "0,1"
|
|
bitfld.long 0x0 0. "OUTSEL,The output value selection" "0,1"
|
|
tree.end
|
|
tree "TIMER50"
|
|
base ad:0x4000F000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTL0,control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "SPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "UPS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,control register 1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DMAINTEN,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "INTF,status register"
|
|
bitfld.long 0x4 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,event generation register"
|
|
bitfld.long 0x0 0. "UPG,Update generation" "0,1"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNTL,counter"
|
|
hexmask.long 0x0 0.--31. 1. "CNTL,Low counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "CARL,Counter auto-reload low register"
|
|
hexmask.long 0x8 0.--31. 1. "CARLL,Low Auto-reload value"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "CNTH,Counter high register"
|
|
bitfld.long 0x0 31. "CNTH_31,CNTH_31" "0,1"
|
|
hexmask.long 0x0 0.--29. 1. "CNTH32_63,CNTH32_63"
|
|
line.long 0x4 "CARH,Counter high register"
|
|
hexmask.long 0x4 0.--31. 1. "CARLH32_63,CARLH32_63"
|
|
tree.end
|
|
tree "TIMER51"
|
|
base ad:0x4000F400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTL0,control register 0"
|
|
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
|
|
bitfld.long 0x0 7. "ARSE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "SPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "UPS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CTL1,control register 1"
|
|
bitfld.long 0x4 4.--6. "MMC0,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DMAINTEN,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UPDEN,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 0. "UPIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "INTF,status register"
|
|
bitfld.long 0x4 0. "UPIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "SWEVG,event generation register"
|
|
bitfld.long 0x0 0. "UPG,Update generation" "0,1"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNTL,counter"
|
|
hexmask.long 0x0 0.--31. 1. "CNTL,Low counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "CARL,Counter auto-reload low register"
|
|
hexmask.long 0x8 0.--31. 1. "CARLL,Low Auto-reload value"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "CNTH,Counter high register"
|
|
bitfld.long 0x0 31. "CNTH_31,CNTH_31" "0,1"
|
|
hexmask.long 0x0 0.--29. 1. "CNTH32_63,CNTH32_63"
|
|
line.long 0x4 "CARH,Counter high register"
|
|
hexmask.long 0x4 0.--31. 1. "CARLH32_63,CARLH32_63"
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
tree "TLI (TFT-LCD Interface)"
|
|
base ad:0x50001000
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "SPSZ,Synchronous pulse size register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HPSZ,size of horizontal synchronous pluse"
|
|
hexmask.long.word 0x0 0.--11. 1. "VPSZ,size of vertical synchronous pluse"
|
|
line.long 0x4 "BPSZ,Back-porch size register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HBPSZ,Size of the horizontal back porch plus synchronous pulse"
|
|
hexmask.long.word 0x4 0.--11. 1. "VBPSZ,Size of the vertical back porch plus synchronous pulse"
|
|
line.long 0x8 "ASZ,Active size register"
|
|
hexmask.long.word 0x8 16.--27. 1. "HASZ,Size of the horizontal active area width plus back porch and synchronous"
|
|
hexmask.long.word 0x8 0.--11. 1. "VASZ,Size of the vertical active area width plus back porch and synchronous"
|
|
line.long 0xC "TSZ,Total size register"
|
|
hexmask.long.word 0xC 16.--27. 1. "HTSZ,Horizontal total size of the display"
|
|
hexmask.long.word 0xC 0.--11. 1. "VTSZ,Vertical total size of the display"
|
|
line.long 0x10 "CTL,Control register"
|
|
bitfld.long 0x10 31. "HPPS,Horizontal Pulse Polarity Selection" "0,1"
|
|
bitfld.long 0x10 30. "VPPS,Vertical Pulse Polarity Selection" "0,1"
|
|
bitfld.long 0x10 29. "DEPS,Data Enable Polarity Selection" "0,1"
|
|
bitfld.long 0x10 28. "CLKPS,Pixel Clock Polarity Selection" "0,1"
|
|
bitfld.long 0x10 16. "DFEN,Dither Function Enable" "0,1"
|
|
bitfld.long 0x10 12.--14. "RDB,Red channel Dither Bits Number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 8.--10. "GDB,Green channel Dither Bits Number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 4.--6. "BDB,Blue channel Dither Bits Number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0. "TLIEN,TLI enable bit" "0,1"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "RL,Reload layer register"
|
|
bitfld.long 0x0 1. "FBR,Frame Blank Reload" "0,1"
|
|
bitfld.long 0x0 0. "RQR,Request Reload" "0,1"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "BGC,Background color register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BVR,Background value red"
|
|
hexmask.long.byte 0x0 8.--15. 1. "BVG,Background value green"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BVB,Background value blue"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "INTEN,Interrupt enable register"
|
|
bitfld.long 0x0 3. "LCRIE,Layer Configuration Reloaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "TEIE,Transaction Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "FEIE,FIFO Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "LMIE,Line Mark Interrupt Enable" "0,1"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "INTF,Interrupt flag register"
|
|
bitfld.long 0x0 3. "LCRF,Layer Configuration Reloaded Flag" "0,1"
|
|
bitfld.long 0x0 2. "TEF,Transaction Error Flag" "0,1"
|
|
bitfld.long 0x0 1. "FEF,FIFO Error Flag" "0,1"
|
|
bitfld.long 0x0 0. "LMF,Line Mark Flag" "0,1"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "INTC,Interrupt flag clear register"
|
|
bitfld.long 0x0 3. "LCRC,Layer Configuration Reloaded Flag Clear" "0,1"
|
|
bitfld.long 0x0 2. "TEC,Transaction Error Flag Clear" "0,1"
|
|
bitfld.long 0x0 1. "FEC,FIFO Error Flag Clear" "0,1"
|
|
bitfld.long 0x0 0. "LMC,Line Mark Flag Clear" "0,1"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "LM,Line mark register"
|
|
hexmask.long.word 0x0 0.--10. 1. "LM,Line Mark value"
|
|
rgroup.long 0x44++0x7
|
|
line.long 0x0 "CPPOS,Current pixel position register"
|
|
hexmask.long.word 0x0 16.--31. 1. "HPOS,Horizontal position"
|
|
hexmask.long.word 0x0 0.--15. 1. "VPOS,Vertical position"
|
|
line.long 0x4 "STAT,Status register"
|
|
bitfld.long 0x4 3. "HS,Current HS staus of the TLI" "0,1"
|
|
bitfld.long 0x4 2. "VS,Current VS staus of the TLI" "0,1"
|
|
bitfld.long 0x4 1. "HDE,Current HDE status" "0,1"
|
|
bitfld.long 0x4 0. "VDE,Current VDE status" "0,1"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "L0CTL,Layer 0 control register"
|
|
bitfld.long 0x0 4. "LUTEN,LUT enable" "0,1"
|
|
bitfld.long 0x0 1. "CKEYEN,Color keying enable" "0,1"
|
|
bitfld.long 0x0 0. "LEN,Layer enable" "0,1"
|
|
group.long 0x104++0x3
|
|
line.long 0x0 "L1CTL,Layer 1 control register"
|
|
bitfld.long 0x0 4. "LUTEN,LUT enable" "0,1"
|
|
bitfld.long 0x0 1. "CKEYEN,Color keying enable" "0,1"
|
|
bitfld.long 0x0 0. "LEN,Layer enable" "0,1"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "L0HPOS,Layer 0 horizontal position parameters register"
|
|
hexmask.long.word 0x0 16.--27. 1. "WRP,Window right position"
|
|
hexmask.long.word 0x0 0.--11. 1. "WLP,Window left position"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "L1HPOS,Layer 1 horizontal position parameters register"
|
|
hexmask.long.word 0x0 16.--27. 1. "WRP,Window right position"
|
|
hexmask.long.word 0x0 0.--11. 1. "WLP,Window left position"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "L0VPOS,Layer 0 vertical position parameters register"
|
|
hexmask.long.word 0x0 16.--27. 1. "WBP,Window bottom position"
|
|
hexmask.long.word 0x0 0.--11. 1. "WTP,Window top position"
|
|
group.long 0x10C++0x3
|
|
line.long 0x0 "L1VPOS,Layer 1 vertical position parameters register"
|
|
hexmask.long.word 0x0 16.--27. 1. "WBP,Window bottom position"
|
|
hexmask.long.word 0x0 0.--11. 1. "WTP,Window top position"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "L0CKEY,Layer 0 color key register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CKEYR,Color Key Red"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CKEYG,Color Key Green"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CKEYB,Color Key Blue"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "L1CKEY,Layer 1 color key register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CKEYR,Color Key Red"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CKEYG,Color Key Green"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CKEYB,Color Key Blue"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "L0PPF,Layer 0 packeted pixel format register"
|
|
bitfld.long 0x0 0.--2. "PPF,Packeted Pixel Format" "0,1,2,3,4,5,6,7"
|
|
group.long 0x114++0x3
|
|
line.long 0x0 "L1PPF,Layer 1 packeted pixel format register"
|
|
bitfld.long 0x0 0.--2. "PPF,Packeted Pixel Format" "0,1,2,3,4,5,6,7"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "L0SA,Layer 0 specified alpha register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SA,Specified alpha"
|
|
group.long 0x118++0x3
|
|
line.long 0x0 "L1SA,Layer 1 specified alpha register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SA,Specified alpha"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "L0DC,Layer 0 default color register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DCA,The default color ALPHA"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DCR,The default color red"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DCG,The default color green"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DCB,The default color blue"
|
|
group.long 0x11C++0x3
|
|
line.long 0x0 "L1DC,Layer 1 default color register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DCA,The default color ALPHA"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DCR,The default color red"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DCG,The default color green"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DCB,The default color blue"
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "L0BLEND,Layer 0 blending register"
|
|
bitfld.long 0x0 8.--10. "ACF1,Alpha Calculation Factor 1 of Blending Method" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "ACF2,Alpha Calculation Factor 2 of Blending Method" "0,1,2,3,4,5,6,7"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "L1BLEND,Layer 1 blending register"
|
|
bitfld.long 0x0 8.--10. "ACF1,Alpha Calculation Factor 1 of Blending Method" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "ACF2,Alpha Calculation Factor 2 of Blending Method" "0,1,2,3,4,5,6,7"
|
|
group.long 0xAC++0x3
|
|
line.long 0x0 "L0FBADDR,Layer 0 frame base address register"
|
|
hexmask.long 0x0 0.--31. 1. "FBADD,Frame Buffer base Address"
|
|
group.long 0x12C++0x3
|
|
line.long 0x0 "L1FBADDR,Layer 1 frame base address register"
|
|
hexmask.long 0x0 0.--31. 1. "FBADD,Frame Buffer base Address"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "L0FLLEN,Layer 0 frame line length register"
|
|
hexmask.long.word 0x0 16.--29. 1. "STDOFF,Frame Buffer Stride Offset"
|
|
hexmask.long.word 0x0 0.--13. 1. "FLL,Frame Line Length"
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "L1FLLEN,Layer 1 frame line length register"
|
|
hexmask.long.word 0x0 16.--29. 1. "STDOFF,Frame Buffer Stride Offset"
|
|
hexmask.long.word 0x0 0.--13. 1. "FLL,Frame Line Length"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "L0FTLN,Layer 0 frame total line number register"
|
|
hexmask.long.word 0x0 0.--10. 1. "FTLN,Frame Total Line Number"
|
|
group.long 0x134++0x3
|
|
line.long 0x0 "L1FTLN,Layer 1 frame total line number register"
|
|
hexmask.long.word 0x0 0.--10. 1. "FTLN,Frame Total Line Number"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "L0LUT,Layer 0 look up table register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TADD,Look Up Table Write Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TR,Red Channel of a LUT entry"
|
|
hexmask.long.byte 0x0 8.--15. 1. "TG,Green channel of a LUT entry"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TB,Blue channel of a LUT entry"
|
|
group.long 0x144++0x3
|
|
line.long 0x0 "L1LUT,Layer 1 look up table register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TADD,Look Up Table Write Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TR,Red channel of a LUT entry"
|
|
hexmask.long.byte 0x0 8.--15. 1. "TG,Green channel of a LUT entry"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TB,Blue channel of a LUT entry"
|
|
tree.end
|
|
endif
|
|
tree "TMU (Trigonometric Math Unit)"
|
|
base ad:0x48024400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CS,Control and status register"
|
|
rbitfld.long 0x0 31. "ENDF,End of TMU operation flag" "0,1"
|
|
bitfld.long 0x0 22. "IWIDTH,Width of input data" "0,1"
|
|
bitfld.long 0x0 21. "OWIDTH,Width of output data" "0,1"
|
|
bitfld.long 0x0 20. "INUM,The number of times that the IDATA needs to be written" "0,1"
|
|
bitfld.long 0x0 19. "ONUM,The number of times that the ODATA needs to be read" "0,1"
|
|
bitfld.long 0x0 18. "WDEN,Enable DMA request to write IDATA" "0,1"
|
|
bitfld.long 0x0 17. "RDEN,Enable DMA request to read ODATA" "0,1"
|
|
bitfld.long 0x0 16. "RIE,Enable interrupt request to read ODATA" "0,1"
|
|
bitfld.long 0x0 8.--10. "FACTOR,Scaling factor" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 4.--7. 1. "ITRTNUM,Number of iterations"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MODE,Mode of CORDIC operation"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "IDATA,Input data register"
|
|
hexmask.long 0x0 0.--31. 1. "IDATA,The input data"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "ODATA,Output Data register"
|
|
hexmask.long 0x0 0.--31. 1. "ODATA,The output data"
|
|
tree.end
|
|
tree "TRIGSEL (Trigger Selection Controller)"
|
|
base ad:0x40018400
|
|
sif (cpuis("GD32H75E*"))
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "EXTOUT_0,Trigger selection for EXTOUT register 0"
|
|
bitfld.long 0x0 31. "LK,TRIGSEL register lock." "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INSEL1,Trigger input source selection for output1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x4 "EXTOUT_1,Trigger selection for EXTOUT register 1"
|
|
bitfld.long 0x4 31. "LK,TRIGSEL register lock." "0,1"
|
|
hexmask.long.byte 0x4 8.--15. 1. "INSEL1,Trigger input source selection for output1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x8 "EXTOUT_2,Trigger selection for EXTOUT register 2"
|
|
bitfld.long 0x8 31. "LK,TRIGSEL register lock." "0,1"
|
|
hexmask.long.byte 0x8 8.--15. 1. "INSEL1,Trigger input source selection for output1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0xC "EXTOUT_3,Trigger selection for EXTOUT register 3"
|
|
bitfld.long 0xC 31. "LK,TRIGSEL register lock." "0,1"
|
|
hexmask.long.byte 0xC 8.--15. 1. "INSEL1,Trigger input source selection for output1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "DAC0OUT0,Trigger selection for DAC0_OUT0 register"
|
|
bitfld.long 0x0 31. "LK,TRIGSEL register lock." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x4 "DAC0OUT1,Trigger selection for DAC0_OUT1 register"
|
|
bitfld.long 0x4 31. "LK,TRIGSEL register lock." "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "EXTOUT0,Trigger selection for EXTOUT0 register"
|
|
rbitfld.long 0x0 31. "LK,TRIGSEL register lock" "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INSEL1,Trigger input source selection for output1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x4 "EXTOUT1,Trigger selection for EXTOUT1 register"
|
|
bitfld.long 0x4 31. "LK,TRIGSEL register lock" "0,1"
|
|
hexmask.long.byte 0x4 8.--15. 1. "INSEL1,Trigger input source selection for output1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x8 "EXTOUT2,Trigger selection for EXTOUT2 register"
|
|
rbitfld.long 0x8 31. "LK,TRIGSEL register lock" "0,1"
|
|
hexmask.long.byte 0x8 8.--15. 1. "INSEL1,Trigger input source selection for output1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0xC "EXTOUT3,Trigger selection for EXTOUT3 register"
|
|
bitfld.long 0xC 31. "LK,TRIGSEL register lock" "0,1"
|
|
hexmask.long.byte 0xC 8.--15. 1. "INSEL1,Trigger input source selection for output1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "DACOUT0,Trigger selection for DAC_OUT0 register"
|
|
rbitfld.long 0x0 31. "LK,TRIGSEL register lock" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x4 "DACOUT1,Trigger selection for DAC_OUT1 register"
|
|
rbitfld.long 0x4 31. "LK,TRIGSEL register lock" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
group.long 0x7C++0x7
|
|
line.long 0x0 "TIMER30ETI,Trigger selection for TIMER30_ETI register"
|
|
rbitfld.long 0x0 31. "LK,TRIGSEL register lock" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x4 "TIMER31ETI,Trigger selection for TIMER31_ETI register"
|
|
rbitfld.long 0x4 31. "LK,TRIGSEL register lock" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "TIMER30ITI14,Trigger selection for TIMER30_ITI14 register"
|
|
rbitfld.long 0x0 31. "LK,TRIGSEL register lock" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x4 "TIMER31ITI14,Trigger selection for TIMER31_ITI14 register"
|
|
rbitfld.long 0x4 31. "LK,TRIGSEL register lock" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
endif
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "ADC0,Trigger selection for ADC0 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x0 31. "LK,TRIGSEL register lock." "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INSEL1,Trigger input source selection for output1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x0 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x0 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x4 "ADC1,Trigger selection for ADC1 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x4 31. "LK,TRIGSEL register lock." "0,1"
|
|
hexmask.long.byte 0x4 8.--15. 1. "INSEL1,Trigger input source selection for output1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x4 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x4 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x8 "ADC2,Trigger selection for ADC2 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x8 31. "LK,TRIGSEL register lock." "0,1"
|
|
hexmask.long.byte 0x8 8.--15. 1. "INSEL1,Trigger input source selection for output1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x8 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x8 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
group.long 0x24++0x57
|
|
line.long 0x0 "TIMER0BRKIN,Trigger selection for TIMER0_BRKIN register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x0 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x0 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x0 16.--23. 1. "INSEL2,Trigger input source selection for output2"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INSEL1,Trigger input source selection for output1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x4 "TIMER7BRKIN,Trigger selection for TIMER7_BRKIN register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x4 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x4 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x4 16.--23. 1. "INSEL2,Trigger input source selection for output2"
|
|
hexmask.long.byte 0x4 8.--15. 1. "INSEL1,Trigger input source selection for output1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x8 "TIMER14BRKIN,Trigger selection for TIMER14_BRKIN register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x8 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x8 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x8 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0xC "TIMER15BRKIN,Trigger selection for TIMER15_BRKIN register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0xC 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0xC 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0xC 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x10 "TIMER16BRKIN,Trigger selection for TIMER16_BRKIN register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x10 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x10 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x10 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x14 "TIMER40BRKIN,Trigger selection for TIMER40_BRKIN register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x14 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x14 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x14 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x18 "TIMER41BRKIN,Trigger selection for TIMER41_BRKIN register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x18 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x18 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x18 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x1C "TIMER42BRKIN,Trigger selection for TIMER42_BRKIN register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x1C 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x1C 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x1C 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x20 "TIMER43BRKIN,Trigger selection for TIMER43_BRKIN register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x20 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x20 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x20 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x24 "TIMER44BRKIN,Trigger selection for TIMER44_BRKIN register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x24 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x24 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x24 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x28 "CAN0,Trigger selection for CAN0 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x28 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x28 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x28 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x2C "CAN1,Trigger selection for CAN1 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x2C 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x2C 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x2C 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x30 "CAN2,Trigger selection for CAN2 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x30 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x30 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x30 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x34 "LPDTS,Trigger selection for LPDTS register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x34 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x34 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x34 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x38 "TIMER0ETI,Trigger selection for TIMER0_ETI register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x38 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x38 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x38 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x3C "TIMER1ETI,Trigger selection for TIMER1_ETI register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x3C 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x3C 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x3C 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x40 "TIMER2ETI,Trigger selection for TIMER2_ETI register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x40 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x40 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x40 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x44 "TIMER3ETI,Trigger selection for TIMER3_ETI register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x44 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x44 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x44 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x48 "TIMER4ETI,Trigger selection for TIMER4_ETI register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x48 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x48 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x48 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x4C "TIMER7ETI,Trigger selection for TIMER7_ETI register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x4C 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x4C 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x4C 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x50 "TIMER22ETI,Trigger selection for TIMER22_ETI register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x50 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x50 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x50 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x54 "TIMER23ETI,Trigger selection for TIMER23_ETI register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x54 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x54 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x54 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
group.long 0x84++0x2B
|
|
line.long 0x0 "EDOUT,Trigger selection for EDOUT register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x0 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x0 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x0 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x4 "HPDF,Trigger selection for HPDF register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x4 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x4 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x4 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x8 "TIMER0ITI14,Trigger selection for TIMER0_ITI14 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x8 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x8 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x8 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0xC "TIMER1ITI14,Trigger selection for TIMER1_ITI14 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0xC 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0xC 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0xC 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x10 "TIMER2ITI14,Trigger selection for TIMER2_ITI14 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x10 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x10 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x10 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x14 "TIMER3ITI14,Trigger selection for TIMER3_ITI14 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x14 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x14 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x14 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x18 "TIMER4ITI14,Trigger selection for TIMER4_ITI14 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x18 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x18 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x18 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x1C "TIMER7ITI14,Trigger selection for TIMER7_ITI14 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x1C 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x1C 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x1C 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x20 "TIMER14ITI14,Trigger selection for TIMER14_ITI14 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x20 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x20 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x20 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x24 "TIMER22ITI14,Trigger selection for TIMER22_ITI14 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x24 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x24 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x24 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x28 "TIMER23ITI14,Trigger selection for TIMER23_ITI14 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x28 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x28 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x28 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
group.long 0xB8++0x13
|
|
line.long 0x0 "TIMER40ITI14,Trigger selection for TIMER40_ITI14 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x0 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x0 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x0 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x4 "TIMER41ITI14,Trigger selection for TIMER41_ITI14 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x4 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x4 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x4 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x8 "TIMER42ITI14,Trigger selection for TIMER42_ITI14 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x8 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x8 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x8 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0xC "TIMER43ITI14,Trigger selection for TIMER43_ITI14 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0xC 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0xC 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0xC 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
line.long 0x10 "TIMER44ITI14,Trigger selection for TIMER44_ITI14 register"
|
|
sif (cpuis("GD32H75E*"))
|
|
bitfld.long 0x10 31. "LK,TRIGSEL register lock." "0,1"
|
|
endif
|
|
sif (cpuis("GD32H73*")||cpuis("GD32H757*")||cpuis("GD32H759*"))
|
|
rbitfld.long 0x10 31. "LK,TRIGSEL register lock" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x10 0.--7. 1. "INSEL0,Trigger input source selection for output0"
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0x48021800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTL,Control register"
|
|
rbitfld.long 0x0 31. "CTL_LK,TRNG_CTL register lock bit" "0,1"
|
|
bitfld.long 0x0 30. "CONDRST,reset conditioning logic" "0,1"
|
|
bitfld.long 0x0 24.--25. "NR,analog trng power mode" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CLKDIV,TRNG clock divider"
|
|
bitfld.long 0x0 15. "INMOD,select random seed number input to conditioning module" "0,1"
|
|
bitfld.long 0x0 14. "OUTMOD,select random data width output of conditioning module" "0,1"
|
|
bitfld.long 0x0 12.--13. "ALGO,None NIST compliant" "0,1,2,3"
|
|
bitfld.long 0x0 10. "COND_EN,enable conditioning component" "0,1"
|
|
bitfld.long 0x0 9. "PP_EN,enable post_processing" "0,1"
|
|
bitfld.long 0x0 8. "INIT,init hash algo when conditioning enabled" "0,1"
|
|
bitfld.long 0x0 7. "RT_EN,replace test enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CED,clock error detection" "0,1"
|
|
bitfld.long 0x0 4. "MOD_SEL,LFSR or NIST mode selection" "0,1"
|
|
bitfld.long 0x0 3. "IE,Interrupt enabled bit" "0,1"
|
|
bitfld.long 0x0 2. "TRNGEN,TRNG enabled bit" "0,1"
|
|
line.long 0x4 "STAT,Status register"
|
|
bitfld.long 0x4 6. "SEIF,Seed error interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "CEIF,Clock error interrupt flag" "0,1"
|
|
bitfld.long 0x4 3. "ERR_STA,NIST mode error flag this bit could be reset by CONDRST" "0,1"
|
|
rbitfld.long 0x4 2. "SECS,Seed error current status" "0,1"
|
|
rbitfld.long 0x4 1. "CECS,Clock error current status" "0,1"
|
|
rbitfld.long 0x4 0. "DRDY,Random data ready status bit" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "DATA,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "TRNDATA,32-bit random data"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "HTCFG,Health tests configure register"
|
|
hexmask.long.word 0x0 16.--25. 1. "APT_TH,Adaptive proportion test threshold"
|
|
hexmask.long.byte 0x0 0.--6. 1. "RCT_TH,Repetition count test threshold"
|
|
tree.end
|
|
tree "UART (Universal Synchronous/Asynchronous Receiver/Transmitter)"
|
|
base ad:0x0
|
|
tree "UART3"
|
|
base ad:0x40004C00
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 31. "AMIE1,ADDR1 match interrupt enable" "0,1"
|
|
bitfld.long 0x0 28. "WL1,Word length 1" "0,1"
|
|
bitfld.long 0x0 27. "EBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTIE,Receiver timeout interrupt enable" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEA,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DED,Driver Enable de-assertion time"
|
|
bitfld.long 0x0 15. "OVSMOD,Oversample mode" "0,1"
|
|
bitfld.long 0x0 14. "AMIE0,ADDR0 match interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MEN,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "WL0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WM,Wakeup method in mute mode" "0,1"
|
|
bitfld.long 0x0 10. "PCEN,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PM,Parity mode" "0,1"
|
|
bitfld.long 0x0 8. "PERRIE,Parity error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TBEIE_TFNFIE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RBNEIE_RFNEIE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE line detected interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TEN,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "REN,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Deep-sleep mode" "0,1"
|
|
bitfld.long 0x0 0. "UEN,USART enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADDR0,Address 0 of the USART terminal"
|
|
bitfld.long 0x4 23. "RTEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBF,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "DINV,Data bit level inversion" "0,1"
|
|
bitfld.long 0x4 17. "TINV,TX pin level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RINV,RX pin level inversion" "0,1"
|
|
bitfld.long 0x4 15. "STRP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LMEN,LIN mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STB,STOP bits length" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CKEN,CK pin enable" "0,1"
|
|
bitfld.long 0x4 10. "CPL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPH,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "CLEN,CK length" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBLEN,LIN break frame length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM0,Address detection mode 0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "AMEN0,Match Address Mode Enable 0" "0,1"
|
|
line.long 0x8 "CTL2,Control register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. "ADDR1,Address 1 of the USART terminal"
|
|
bitfld.long 0x8 23. "ADDM1,Address detection mode 1" "0,1"
|
|
bitfld.long 0x8 22. "WUIE,Wakeup from Deep-sleep mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUM,Wakeup mode from Deep-sleep mode" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCRTNUM,Smartcard auto-retry number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16. "AMEN1,Match Address Mode Enable 1" "0,1"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity mode" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,Disable DMA on reception error" "0,1"
|
|
bitfld.long 0x8 12. "OVRD,Overrun disable" "0,1"
|
|
bitfld.long 0x8 11. "OSB,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSEN,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSEN,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DENT,DMA enable for transmission" "0,1"
|
|
bitfld.long 0x8 6. "DENR,DMA enable for reception" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NKEN,NACK enable in Smartcard mode" "0,1"
|
|
bitfld.long 0x8 3. "HDEN,Half-duplex enable" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0,1"
|
|
bitfld.long 0x8 0. "ERRIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BAUD,Baud rate generator register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_INT,Integer of baud-rate divider"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_DIV,Fraction of baud-rate divider"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "CMD,Command register"
|
|
bitfld.long 0x0 4. "TXFCMD,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFCMD,Receive data flush command" "0,1"
|
|
bitfld.long 0x0 2. "MMCMD,Mute mode command" "0,1"
|
|
bitfld.long 0x0 1. "SBKCMD,Send break command" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "STAT,Status register"
|
|
bitfld.long 0x0 22. "REA,Receive enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 21. "TEA,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from Deep-sleep mode flag" "0,1"
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from mute mode" "0,1"
|
|
bitfld.long 0x0 18. "SBF,Send break flag" "0,1"
|
|
bitfld.long 0x0 17. "AMF0,ADDR0 match flag" "0,1"
|
|
bitfld.long 0x0 16. "BSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 13. "AMF1,ADDR1 match flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EBF,End of block flag" "0,1"
|
|
bitfld.long 0x0 11. "RTF,Receiver timeout flag" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS level" "0,1"
|
|
bitfld.long 0x0 9. "CTSF,CTS change flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detected flag" "0,1"
|
|
bitfld.long 0x0 7. "TBE_TFNF,When FIFO is disabled:" "0,1"
|
|
bitfld.long 0x0 6. "TC,Transmission completed" "0,1"
|
|
bitfld.long 0x0 5. "RBNE_RFNE,Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEF,IDLE line detected flag" "0,1"
|
|
bitfld.long 0x0 3. "ORERR,Overrun error" "0,1"
|
|
bitfld.long 0x0 2. "NERR,Noise error flag" "0,1"
|
|
bitfld.long 0x0 1. "FERR,Frame error flag" "0,1"
|
|
bitfld.long 0x0 0. "PERR,Parity error flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "INTC,Interrupt status clear register"
|
|
bitfld.long 0x0 20. "WUC,Wakeup from Deep-sleep mode clear" "0,1"
|
|
bitfld.long 0x0 17. "AMC0,ADDR0 match clear" "0,1"
|
|
bitfld.long 0x0 16. "AMC1,ADDR1 match clear" "0,1"
|
|
bitfld.long 0x0 12. "EBC,End of block clear" "0,1"
|
|
bitfld.long 0x0 11. "RTC,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSC,CTS change clear" "0,1"
|
|
bitfld.long 0x0 8. "LBDC,LIN break detected clear" "0,1"
|
|
bitfld.long 0x0 6. "TCC,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEC,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "OREC,Overrun error clear" "0,1"
|
|
bitfld.long 0x0 2. "NEC,Noise detected clear" "0,1"
|
|
bitfld.long 0x0 1. "FEC,Frame error flag clear" "0,1"
|
|
bitfld.long 0x0 0. "PEC,Parity error clear" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDATA,Receive data register"
|
|
hexmask.long.word 0x0 0.--9. 1. "RDATA,Receive Data value"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TDATA,Transmit data register"
|
|
hexmask.long.word 0x0 0.--9. 1. "TDATA,Transmit Data value"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "CHC,USART coherence control register"
|
|
bitfld.long 0x0 8. "EPERR,Early parity error flag" "0,1"
|
|
bitfld.long 0x0 0. "HCM,Hardware flow control coherence mode" "0,1"
|
|
group.long 0xD0++0x3
|
|
line.long 0x0 "FCS,USART FIFO control and status register"
|
|
bitfld.long 0x0 31. "TFEIE,Transmit FIFO empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 29. "TFTIE,Transmit FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 27. "RFTIE,Receive FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "TFEC,Transmit FIFO empty flag clear" "0,1"
|
|
rbitfld.long 0x0 25. "TFTIF,Transmit FIFO threshold interrupt flag" "0,1"
|
|
rbitfld.long 0x0 24. "TFEIF,Transmit FIFO empty interrupt flag" "0,1"
|
|
rbitfld.long 0x0 22. "RFTIF,Receive FIFO threshold interrupt flag" "0,1"
|
|
bitfld.long 0x0 19.--21. "TFTCFG,Transmit FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "RFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15. "RFFIF,Receive FIFO full interrupt flag" "0,1"
|
|
rbitfld.long 0x0 12.--14. "RFCNT,Receive FIFO counter number" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x0 11. "RFF,Receive FIFO full flag" "0,1"
|
|
bitfld.long 0x0 10. "RFE,Receive FIFO empty flag" "0,1"
|
|
bitfld.long 0x0 9. "RFFIE,Receive FIFO full interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "FEN,FIFO enable" "0,1"
|
|
rbitfld.long 0x0 7. "TFF,Transmit FIFO full flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 6. "TFE,Transmit FIFO empty flag" "0,1"
|
|
bitfld.long 0x0 5. "TFT,Transmit FIFO threshold flag" "0,1"
|
|
rbitfld.long 0x0 4. "RFT,Receive FIFO threshold flag" "0,1"
|
|
rbitfld.long 0x0 1.--2. "RFCNT_3_4,Bits 3_4 of receive FIFO counter number" "0,1,2,3"
|
|
bitfld.long 0x0 0. "ELNACK,Early NACK when smartcard mode is selected" "0,1"
|
|
tree.end
|
|
tree "UART4"
|
|
base ad:0x40005000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 31. "AMIE1,ADDR1 match interrupt enable" "0,1"
|
|
bitfld.long 0x0 28. "WL1,Word length 1" "0,1"
|
|
bitfld.long 0x0 27. "EBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTIE,Receiver timeout interrupt enable" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEA,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DED,Driver Enable de-assertion time"
|
|
bitfld.long 0x0 15. "OVSMOD,Oversample mode" "0,1"
|
|
bitfld.long 0x0 14. "AMIE0,ADDR0 match interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MEN,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "WL0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WM,Wakeup method in mute mode" "0,1"
|
|
bitfld.long 0x0 10. "PCEN,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PM,Parity mode" "0,1"
|
|
bitfld.long 0x0 8. "PERRIE,Parity error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TBEIE_TFNFIE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RBNEIE_RFNEIE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE line detected interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TEN,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "REN,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Deep-sleep mode" "0,1"
|
|
bitfld.long 0x0 0. "UEN,USART enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADDR0,Address 0 of the USART terminal"
|
|
bitfld.long 0x4 23. "RTEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBF,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "DINV,Data bit level inversion" "0,1"
|
|
bitfld.long 0x4 17. "TINV,TX pin level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RINV,RX pin level inversion" "0,1"
|
|
bitfld.long 0x4 15. "STRP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LMEN,LIN mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STB,STOP bits length" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CKEN,CK pin enable" "0,1"
|
|
bitfld.long 0x4 10. "CPL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPH,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "CLEN,CK length" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBLEN,LIN break frame length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM0,Address detection mode 0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "AMEN0,Match Address Mode Enable 0" "0,1"
|
|
line.long 0x8 "CTL2,Control register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. "ADDR1,Address 1 of the USART terminal"
|
|
bitfld.long 0x8 23. "ADDM1,Address detection mode 1" "0,1"
|
|
bitfld.long 0x8 22. "WUIE,Wakeup from Deep-sleep mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUM,Wakeup mode from Deep-sleep mode" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCRTNUM,Smartcard auto-retry number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16. "AMEN1,Match Address Mode Enable 1" "0,1"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity mode" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,Disable DMA on reception error" "0,1"
|
|
bitfld.long 0x8 12. "OVRD,Overrun disable" "0,1"
|
|
bitfld.long 0x8 11. "OSB,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSEN,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSEN,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DENT,DMA enable for transmission" "0,1"
|
|
bitfld.long 0x8 6. "DENR,DMA enable for reception" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NKEN,NACK enable in Smartcard mode" "0,1"
|
|
bitfld.long 0x8 3. "HDEN,Half-duplex enable" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0,1"
|
|
bitfld.long 0x8 0. "ERRIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BAUD,Baud rate generator register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_INT,Integer of baud-rate divider"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_DIV,Fraction of baud-rate divider"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "CMD,Command register"
|
|
bitfld.long 0x0 4. "TXFCMD,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFCMD,Receive data flush command" "0,1"
|
|
bitfld.long 0x0 2. "MMCMD,Mute mode command" "0,1"
|
|
bitfld.long 0x0 1. "SBKCMD,Send break command" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "STAT,Status register"
|
|
bitfld.long 0x0 22. "REA,Receive enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 21. "TEA,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from Deep-sleep mode flag" "0,1"
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from mute mode" "0,1"
|
|
bitfld.long 0x0 18. "SBF,Send break flag" "0,1"
|
|
bitfld.long 0x0 17. "AMF0,ADDR0 match flag" "0,1"
|
|
bitfld.long 0x0 16. "BSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 13. "AMF1,ADDR1 match flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EBF,End of block flag" "0,1"
|
|
bitfld.long 0x0 11. "RTF,Receiver timeout flag" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS level" "0,1"
|
|
bitfld.long 0x0 9. "CTSF,CTS change flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detected flag" "0,1"
|
|
bitfld.long 0x0 7. "TBE_TFNF,When FIFO is disabled:" "0,1"
|
|
bitfld.long 0x0 6. "TC,Transmission completed" "0,1"
|
|
bitfld.long 0x0 5. "RBNE_RFNE,Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEF,IDLE line detected flag" "0,1"
|
|
bitfld.long 0x0 3. "ORERR,Overrun error" "0,1"
|
|
bitfld.long 0x0 2. "NERR,Noise error flag" "0,1"
|
|
bitfld.long 0x0 1. "FERR,Frame error flag" "0,1"
|
|
bitfld.long 0x0 0. "PERR,Parity error flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "INTC,Interrupt status clear register"
|
|
bitfld.long 0x0 20. "WUC,Wakeup from Deep-sleep mode clear" "0,1"
|
|
bitfld.long 0x0 17. "AMC0,ADDR0 match clear" "0,1"
|
|
bitfld.long 0x0 16. "AMC1,ADDR1 match clear" "0,1"
|
|
bitfld.long 0x0 12. "EBC,End of block clear" "0,1"
|
|
bitfld.long 0x0 11. "RTC,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSC,CTS change clear" "0,1"
|
|
bitfld.long 0x0 8. "LBDC,LIN break detected clear" "0,1"
|
|
bitfld.long 0x0 6. "TCC,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEC,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "OREC,Overrun error clear" "0,1"
|
|
bitfld.long 0x0 2. "NEC,Noise detected clear" "0,1"
|
|
bitfld.long 0x0 1. "FEC,Frame error flag clear" "0,1"
|
|
bitfld.long 0x0 0. "PEC,Parity error clear" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDATA,Receive data register"
|
|
hexmask.long.word 0x0 0.--9. 1. "RDATA,Receive Data value"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TDATA,Transmit data register"
|
|
hexmask.long.word 0x0 0.--9. 1. "TDATA,Transmit Data value"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "CHC,USART coherence control register"
|
|
bitfld.long 0x0 8. "EPERR,Early parity error flag" "0,1"
|
|
bitfld.long 0x0 0. "HCM,Hardware flow control coherence mode" "0,1"
|
|
group.long 0xD0++0x3
|
|
line.long 0x0 "FCS,USART FIFO control and status register"
|
|
bitfld.long 0x0 31. "TFEIE,Transmit FIFO empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 29. "TFTIE,Transmit FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 27. "RFTIE,Receive FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "TFEC,Transmit FIFO empty flag clear" "0,1"
|
|
rbitfld.long 0x0 25. "TFTIF,Transmit FIFO threshold interrupt flag" "0,1"
|
|
rbitfld.long 0x0 24. "TFEIF,Transmit FIFO empty interrupt flag" "0,1"
|
|
rbitfld.long 0x0 22. "RFTIF,Receive FIFO threshold interrupt flag" "0,1"
|
|
bitfld.long 0x0 19.--21. "TFTCFG,Transmit FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "RFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15. "RFFIF,Receive FIFO full interrupt flag" "0,1"
|
|
rbitfld.long 0x0 12.--14. "RFCNT,Receive FIFO counter number" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x0 11. "RFF,Receive FIFO full flag" "0,1"
|
|
bitfld.long 0x0 10. "RFE,Receive FIFO empty flag" "0,1"
|
|
bitfld.long 0x0 9. "RFFIE,Receive FIFO full interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "FEN,FIFO enable" "0,1"
|
|
rbitfld.long 0x0 7. "TFF,Transmit FIFO full flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 6. "TFE,Transmit FIFO empty flag" "0,1"
|
|
bitfld.long 0x0 5. "TFT,Transmit FIFO threshold flag" "0,1"
|
|
rbitfld.long 0x0 4. "RFT,Receive FIFO threshold flag" "0,1"
|
|
rbitfld.long 0x0 1.--2. "RFCNT_3_4,Bits 3_4 of receive FIFO counter number" "0,1,2,3"
|
|
bitfld.long 0x0 0. "ELNACK,Early NACK when smartcard mode is selected" "0,1"
|
|
tree.end
|
|
tree "UART6"
|
|
base ad:0x40007800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 31. "AMIE1,ADDR1 match interrupt enable" "0,1"
|
|
bitfld.long 0x0 28. "WL1,Word length 1" "0,1"
|
|
bitfld.long 0x0 27. "EBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTIE,Receiver timeout interrupt enable" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEA,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DED,Driver Enable de-assertion time"
|
|
bitfld.long 0x0 15. "OVSMOD,Oversample mode" "0,1"
|
|
bitfld.long 0x0 14. "AMIE0,ADDR0 match interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MEN,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "WL0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WM,Wakeup method in mute mode" "0,1"
|
|
bitfld.long 0x0 10. "PCEN,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PM,Parity mode" "0,1"
|
|
bitfld.long 0x0 8. "PERRIE,Parity error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TBEIE_TFNFIE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RBNEIE_RFNEIE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE line detected interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TEN,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "REN,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Deep-sleep mode" "0,1"
|
|
bitfld.long 0x0 0. "UEN,USART enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADDR0,Address 0 of the USART terminal"
|
|
bitfld.long 0x4 23. "RTEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBF,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "DINV,Data bit level inversion" "0,1"
|
|
bitfld.long 0x4 17. "TINV,TX pin level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RINV,RX pin level inversion" "0,1"
|
|
bitfld.long 0x4 15. "STRP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LMEN,LIN mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STB,STOP bits length" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CKEN,CK pin enable" "0,1"
|
|
bitfld.long 0x4 10. "CPL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPH,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "CLEN,CK length" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBLEN,LIN break frame length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM0,Address detection mode 0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "AMEN0,Match Address Mode Enable 0" "0,1"
|
|
line.long 0x8 "CTL2,Control register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. "ADDR1,Address 1 of the USART terminal"
|
|
bitfld.long 0x8 23. "ADDM1,Address detection mode 1" "0,1"
|
|
bitfld.long 0x8 22. "WUIE,Wakeup from Deep-sleep mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUM,Wakeup mode from Deep-sleep mode" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCRTNUM,Smartcard auto-retry number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16. "AMEN1,Match Address Mode Enable 1" "0,1"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity mode" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,Disable DMA on reception error" "0,1"
|
|
bitfld.long 0x8 12. "OVRD,Overrun disable" "0,1"
|
|
bitfld.long 0x8 11. "OSB,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSEN,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSEN,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DENT,DMA enable for transmission" "0,1"
|
|
bitfld.long 0x8 6. "DENR,DMA enable for reception" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NKEN,NACK enable in Smartcard mode" "0,1"
|
|
bitfld.long 0x8 3. "HDEN,Half-duplex enable" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0,1"
|
|
bitfld.long 0x8 0. "ERRIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BAUD,Baud rate generator register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_INT,Integer of baud-rate divider"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_DIV,Fraction of baud-rate divider"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "CMD,Command register"
|
|
bitfld.long 0x0 4. "TXFCMD,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFCMD,Receive data flush command" "0,1"
|
|
bitfld.long 0x0 2. "MMCMD,Mute mode command" "0,1"
|
|
bitfld.long 0x0 1. "SBKCMD,Send break command" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "STAT,Status register"
|
|
bitfld.long 0x0 22. "REA,Receive enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 21. "TEA,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from Deep-sleep mode flag" "0,1"
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from mute mode" "0,1"
|
|
bitfld.long 0x0 18. "SBF,Send break flag" "0,1"
|
|
bitfld.long 0x0 17. "AMF0,ADDR0 match flag" "0,1"
|
|
bitfld.long 0x0 16. "BSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 13. "AMF1,ADDR1 match flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EBF,End of block flag" "0,1"
|
|
bitfld.long 0x0 11. "RTF,Receiver timeout flag" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS level" "0,1"
|
|
bitfld.long 0x0 9. "CTSF,CTS change flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detected flag" "0,1"
|
|
bitfld.long 0x0 7. "TBE_TFNF,When FIFO is disabled:" "0,1"
|
|
bitfld.long 0x0 6. "TC,Transmission completed" "0,1"
|
|
bitfld.long 0x0 5. "RBNE_RFNE,Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEF,IDLE line detected flag" "0,1"
|
|
bitfld.long 0x0 3. "ORERR,Overrun error" "0,1"
|
|
bitfld.long 0x0 2. "NERR,Noise error flag" "0,1"
|
|
bitfld.long 0x0 1. "FERR,Frame error flag" "0,1"
|
|
bitfld.long 0x0 0. "PERR,Parity error flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "INTC,Interrupt status clear register"
|
|
bitfld.long 0x0 20. "WUC,Wakeup from Deep-sleep mode clear" "0,1"
|
|
bitfld.long 0x0 17. "AMC0,ADDR0 match clear" "0,1"
|
|
bitfld.long 0x0 16. "AMC1,ADDR1 match clear" "0,1"
|
|
bitfld.long 0x0 12. "EBC,End of block clear" "0,1"
|
|
bitfld.long 0x0 11. "RTC,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSC,CTS change clear" "0,1"
|
|
bitfld.long 0x0 8. "LBDC,LIN break detected clear" "0,1"
|
|
bitfld.long 0x0 6. "TCC,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEC,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "OREC,Overrun error clear" "0,1"
|
|
bitfld.long 0x0 2. "NEC,Noise detected clear" "0,1"
|
|
bitfld.long 0x0 1. "FEC,Frame error flag clear" "0,1"
|
|
bitfld.long 0x0 0. "PEC,Parity error clear" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDATA,Receive data register"
|
|
hexmask.long.word 0x0 0.--9. 1. "RDATA,Receive Data value"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TDATA,Transmit data register"
|
|
hexmask.long.word 0x0 0.--9. 1. "TDATA,Transmit Data value"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "CHC,USART coherence control register"
|
|
bitfld.long 0x0 8. "EPERR,Early parity error flag" "0,1"
|
|
bitfld.long 0x0 0. "HCM,Hardware flow control coherence mode" "0,1"
|
|
group.long 0xD0++0x3
|
|
line.long 0x0 "FCS,USART FIFO control and status register"
|
|
bitfld.long 0x0 31. "TFEIE,Transmit FIFO empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 29. "TFTIE,Transmit FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 27. "RFTIE,Receive FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "TFEC,Transmit FIFO empty flag clear" "0,1"
|
|
rbitfld.long 0x0 25. "TFTIF,Transmit FIFO threshold interrupt flag" "0,1"
|
|
rbitfld.long 0x0 24. "TFEIF,Transmit FIFO empty interrupt flag" "0,1"
|
|
rbitfld.long 0x0 22. "RFTIF,Receive FIFO threshold interrupt flag" "0,1"
|
|
bitfld.long 0x0 19.--21. "TFTCFG,Transmit FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "RFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15. "RFFIF,Receive FIFO full interrupt flag" "0,1"
|
|
rbitfld.long 0x0 12.--14. "RFCNT,Receive FIFO counter number" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x0 11. "RFF,Receive FIFO full flag" "0,1"
|
|
bitfld.long 0x0 10. "RFE,Receive FIFO empty flag" "0,1"
|
|
bitfld.long 0x0 9. "RFFIE,Receive FIFO full interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "FEN,FIFO enable" "0,1"
|
|
rbitfld.long 0x0 7. "TFF,Transmit FIFO full flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 6. "TFE,Transmit FIFO empty flag" "0,1"
|
|
bitfld.long 0x0 5. "TFT,Transmit FIFO threshold flag" "0,1"
|
|
rbitfld.long 0x0 4. "RFT,Receive FIFO threshold flag" "0,1"
|
|
rbitfld.long 0x0 1.--2. "RFCNT_3_4,Bits 3_4 of receive FIFO counter number" "0,1,2,3"
|
|
bitfld.long 0x0 0. "ELNACK,Early NACK when smartcard mode is selected" "0,1"
|
|
tree.end
|
|
tree "UART7"
|
|
base ad:0x40007C00
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 31. "AMIE1,ADDR1 match interrupt enable" "0,1"
|
|
bitfld.long 0x0 28. "WL1,Word length 1" "0,1"
|
|
bitfld.long 0x0 27. "EBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTIE,Receiver timeout interrupt enable" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEA,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DED,Driver Enable de-assertion time"
|
|
bitfld.long 0x0 15. "OVSMOD,Oversample mode" "0,1"
|
|
bitfld.long 0x0 14. "AMIE0,ADDR0 match interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MEN,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "WL0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WM,Wakeup method in mute mode" "0,1"
|
|
bitfld.long 0x0 10. "PCEN,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PM,Parity mode" "0,1"
|
|
bitfld.long 0x0 8. "PERRIE,Parity error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TBEIE_TFNFIE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RBNEIE_RFNEIE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE line detected interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TEN,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "REN,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Deep-sleep mode" "0,1"
|
|
bitfld.long 0x0 0. "UEN,USART enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADDR0,Address 0 of the USART terminal"
|
|
bitfld.long 0x4 23. "RTEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBF,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "DINV,Data bit level inversion" "0,1"
|
|
bitfld.long 0x4 17. "TINV,TX pin level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RINV,RX pin level inversion" "0,1"
|
|
bitfld.long 0x4 15. "STRP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LMEN,LIN mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STB,STOP bits length" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CKEN,CK pin enable" "0,1"
|
|
bitfld.long 0x4 10. "CPL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPH,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "CLEN,CK length" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBLEN,LIN break frame length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM0,Address detection mode 0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "AMEN0,Match Address Mode Enable 0" "0,1"
|
|
line.long 0x8 "CTL2,Control register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. "ADDR1,Address 1 of the USART terminal"
|
|
bitfld.long 0x8 23. "ADDM1,Address detection mode 1" "0,1"
|
|
bitfld.long 0x8 22. "WUIE,Wakeup from Deep-sleep mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUM,Wakeup mode from Deep-sleep mode" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCRTNUM,Smartcard auto-retry number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16. "AMEN1,Match Address Mode Enable 1" "0,1"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity mode" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,Disable DMA on reception error" "0,1"
|
|
bitfld.long 0x8 12. "OVRD,Overrun disable" "0,1"
|
|
bitfld.long 0x8 11. "OSB,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSEN,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSEN,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DENT,DMA enable for transmission" "0,1"
|
|
bitfld.long 0x8 6. "DENR,DMA enable for reception" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NKEN,NACK enable in Smartcard mode" "0,1"
|
|
bitfld.long 0x8 3. "HDEN,Half-duplex enable" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0,1"
|
|
bitfld.long 0x8 0. "ERRIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BAUD,Baud rate generator register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_INT,Integer of baud-rate divider"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_DIV,Fraction of baud-rate divider"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "CMD,Command register"
|
|
bitfld.long 0x0 4. "TXFCMD,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFCMD,Receive data flush command" "0,1"
|
|
bitfld.long 0x0 2. "MMCMD,Mute mode command" "0,1"
|
|
bitfld.long 0x0 1. "SBKCMD,Send break command" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "STAT,Status register"
|
|
bitfld.long 0x0 22. "REA,Receive enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 21. "TEA,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from Deep-sleep mode flag" "0,1"
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from mute mode" "0,1"
|
|
bitfld.long 0x0 18. "SBF,Send break flag" "0,1"
|
|
bitfld.long 0x0 17. "AMF0,ADDR0 match flag" "0,1"
|
|
bitfld.long 0x0 16. "BSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 13. "AMF1,ADDR1 match flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EBF,End of block flag" "0,1"
|
|
bitfld.long 0x0 11. "RTF,Receiver timeout flag" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS level" "0,1"
|
|
bitfld.long 0x0 9. "CTSF,CTS change flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detected flag" "0,1"
|
|
bitfld.long 0x0 7. "TBE_TFNF,When FIFO is disabled:" "0,1"
|
|
bitfld.long 0x0 6. "TC,Transmission completed" "0,1"
|
|
bitfld.long 0x0 5. "RBNE_RFNE,Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEF,IDLE line detected flag" "0,1"
|
|
bitfld.long 0x0 3. "ORERR,Overrun error" "0,1"
|
|
bitfld.long 0x0 2. "NERR,Noise error flag" "0,1"
|
|
bitfld.long 0x0 1. "FERR,Frame error flag" "0,1"
|
|
bitfld.long 0x0 0. "PERR,Parity error flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "INTC,Interrupt status clear register"
|
|
bitfld.long 0x0 20. "WUC,Wakeup from Deep-sleep mode clear" "0,1"
|
|
bitfld.long 0x0 17. "AMC0,ADDR0 match clear" "0,1"
|
|
bitfld.long 0x0 16. "AMC1,ADDR1 match clear" "0,1"
|
|
bitfld.long 0x0 12. "EBC,End of block clear" "0,1"
|
|
bitfld.long 0x0 11. "RTC,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSC,CTS change clear" "0,1"
|
|
bitfld.long 0x0 8. "LBDC,LIN break detected clear" "0,1"
|
|
bitfld.long 0x0 6. "TCC,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEC,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "OREC,Overrun error clear" "0,1"
|
|
bitfld.long 0x0 2. "NEC,Noise detected clear" "0,1"
|
|
bitfld.long 0x0 1. "FEC,Frame error flag clear" "0,1"
|
|
bitfld.long 0x0 0. "PEC,Parity error clear" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDATA,Receive data register"
|
|
hexmask.long.word 0x0 0.--9. 1. "RDATA,Receive Data value"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TDATA,Transmit data register"
|
|
hexmask.long.word 0x0 0.--9. 1. "TDATA,Transmit Data value"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "CHC,USART coherence control register"
|
|
bitfld.long 0x0 8. "EPERR,Early parity error flag" "0,1"
|
|
bitfld.long 0x0 0. "HCM,Hardware flow control coherence mode" "0,1"
|
|
group.long 0xD0++0x3
|
|
line.long 0x0 "FCS,USART FIFO control and status register"
|
|
bitfld.long 0x0 31. "TFEIE,Transmit FIFO empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 29. "TFTIE,Transmit FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 27. "RFTIE,Receive FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "TFEC,Transmit FIFO empty flag clear" "0,1"
|
|
rbitfld.long 0x0 25. "TFTIF,Transmit FIFO threshold interrupt flag" "0,1"
|
|
rbitfld.long 0x0 24. "TFEIF,Transmit FIFO empty interrupt flag" "0,1"
|
|
rbitfld.long 0x0 22. "RFTIF,Receive FIFO threshold interrupt flag" "0,1"
|
|
bitfld.long 0x0 19.--21. "TFTCFG,Transmit FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "RFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15. "RFFIF,Receive FIFO full interrupt flag" "0,1"
|
|
rbitfld.long 0x0 12.--14. "RFCNT,Receive FIFO counter number" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x0 11. "RFF,Receive FIFO full flag" "0,1"
|
|
bitfld.long 0x0 10. "RFE,Receive FIFO empty flag" "0,1"
|
|
bitfld.long 0x0 9. "RFFIE,Receive FIFO full interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "FEN,FIFO enable" "0,1"
|
|
rbitfld.long 0x0 7. "TFF,Transmit FIFO full flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 6. "TFE,Transmit FIFO empty flag" "0,1"
|
|
bitfld.long 0x0 5. "TFT,Transmit FIFO threshold flag" "0,1"
|
|
rbitfld.long 0x0 4. "RFT,Receive FIFO threshold flag" "0,1"
|
|
rbitfld.long 0x0 1.--2. "RFCNT_3_4,Bits 3_4 of receive FIFO counter number" "0,1,2,3"
|
|
bitfld.long 0x0 0. "ELNACK,Early NACK when smartcard mode is selected" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"
|
|
base ad:0x0
|
|
tree "USART0"
|
|
base ad:0x40011000
|
|
group.long 0x0++0x17
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|
line.long 0x0 "CTL0,Control register 0"
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|
bitfld.long 0x0 31. "AMIE1,ADDR1 match interrupt enable" "0,1"
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|
bitfld.long 0x0 28. "WL1,Word length 1" "0,1"
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|
bitfld.long 0x0 27. "EBIE,End of Block interrupt enable" "0,1"
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|
bitfld.long 0x0 26. "RTIE,Receiver timeout interrupt enable" "0,1"
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|
hexmask.long.byte 0x0 21.--25. 1. "DEA,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DED,Driver Enable de-assertion time"
|
|
bitfld.long 0x0 15. "OVSMOD,Oversample mode" "0,1"
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|
bitfld.long 0x0 14. "AMIE0,ADDR0 match interrupt enable" "0,1"
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|
newline
|
|
bitfld.long 0x0 13. "MEN,Mute mode enable" "0,1"
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|
bitfld.long 0x0 12. "WL0,Word length" "0,1"
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|
bitfld.long 0x0 11. "WM,Wakeup method in mute mode" "0,1"
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|
bitfld.long 0x0 10. "PCEN,Parity control enable" "0,1"
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|
bitfld.long 0x0 9. "PM,Parity mode" "0,1"
|
|
bitfld.long 0x0 8. "PERRIE,Parity error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TBEIE_TFNFIE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
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|
newline
|
|
bitfld.long 0x0 5. "RBNEIE_RFNEIE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE line detected interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TEN,Transmitter enable" "0,1"
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|
bitfld.long 0x0 2. "REN,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Deep-sleep mode" "0,1"
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|
bitfld.long 0x0 0. "UEN,USART enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADDR0,Address 0 of the USART terminal"
|
|
bitfld.long 0x4 23. "RTEN,Receiver timeout enable" "0,1"
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|
bitfld.long 0x4 19. "MSBF,Most significant bit first" "0,1"
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|
bitfld.long 0x4 18. "DINV,Data bit level inversion" "0,1"
|
|
bitfld.long 0x4 17. "TINV,TX pin level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RINV,RX pin level inversion" "0,1"
|
|
bitfld.long 0x4 15. "STRP,Swap TX/RX pins" "0,1"
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|
bitfld.long 0x4 14. "LMEN,LIN mode enable" "0,1"
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|
newline
|
|
bitfld.long 0x4 12.--13. "STB,STOP bits length" "0,1,2,3"
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|
bitfld.long 0x4 11. "CKEN,CK pin enable" "0,1"
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|
bitfld.long 0x4 10. "CPL,Clock polarity" "0,1"
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|
bitfld.long 0x4 9. "CPH,Clock phase" "0,1"
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|
bitfld.long 0x4 8. "CLEN,CK length" "0,1"
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|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
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|
bitfld.long 0x4 5. "LBLEN,LIN break frame length" "0,1"
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|
bitfld.long 0x4 4. "ADDM0,Address detection mode 0" "0,1"
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|
newline
|
|
bitfld.long 0x4 0. "AMEN0,Match Address Mode Enable 0" "0,1"
|
|
line.long 0x8 "CTL2,Control register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. "ADDR1,Address 1 of the USART terminal"
|
|
bitfld.long 0x8 23. "ADDM1,Address detection mode 1" "0,1"
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|
bitfld.long 0x8 22. "WUIE,Wakeup from Deep-sleep mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUM,Wakeup mode from Deep-sleep mode" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCRTNUM,Smartcard auto-retry number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16. "AMEN1,Match Address Mode Enable 1" "0,1"
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|
bitfld.long 0x8 15. "DEP,Driver enable polarity mode" "0,1"
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|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
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|
newline
|
|
bitfld.long 0x8 13. "DDRE,Disable DMA on reception error" "0,1"
|
|
bitfld.long 0x8 12. "OVRD,Overrun disable" "0,1"
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|
bitfld.long 0x8 11. "OSB,One sample bit method" "0,1"
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|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSEN,CTS enable" "0,1"
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|
bitfld.long 0x8 8. "RTSEN,RTS enable" "0,1"
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|
bitfld.long 0x8 7. "DENT,DMA enable for transmission" "0,1"
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|
bitfld.long 0x8 6. "DENR,DMA enable for reception" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NKEN,NACK enable in Smartcard mode" "0,1"
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bitfld.long 0x8 3. "HDEN,Half-duplex enable" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0,1"
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|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0,1"
|
|
bitfld.long 0x8 0. "ERRIE,Error interrupt enable" "0,1"
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|
line.long 0xC "BAUD,Baud rate generator register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_INT,Integer of baud-rate divider"
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hexmask.long.byte 0xC 0.--3. 1. "BRR_DIV,Fraction of baud-rate divider"
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|
line.long 0x10 "GP,Prescaler and guard time configuration register"
|
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hexmask.long.byte 0x10 8.--15. 1. "GUAT,Guard time value in smartcard mode"
|
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value for dividing the system clock"
|
|
line.long 0x14 "RT,Receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BL,Block Length"
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|
hexmask.long.tbyte 0x14 0.--23. 1. "RT,Receiver timeout threshold"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "CMD,Command register"
|
|
bitfld.long 0x0 4. "TXFCMD,Transmit data flush request" "0,1"
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|
bitfld.long 0x0 3. "RXFCMD,Receive data flush command" "0,1"
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|
bitfld.long 0x0 2. "MMCMD,Mute mode command" "0,1"
|
|
bitfld.long 0x0 1. "SBKCMD,Send break command" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "STAT,Status register"
|
|
bitfld.long 0x0 22. "REA,Receive enable acknowledge flag" "0,1"
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|
bitfld.long 0x0 21. "TEA,Transmit enable acknowledge flag" "0,1"
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|
bitfld.long 0x0 20. "WUF,Wakeup from Deep-sleep mode flag" "0,1"
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|
bitfld.long 0x0 19. "RWU,Receiver wakeup from mute mode" "0,1"
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|
bitfld.long 0x0 18. "SBF,Send break flag" "0,1"
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|
bitfld.long 0x0 17. "AMF0,ADDR0 match flag" "0,1"
|
|
bitfld.long 0x0 16. "BSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 13. "AMF1,ADDR1 match flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EBF,End of block flag" "0,1"
|
|
bitfld.long 0x0 11. "RTF,Receiver timeout flag" "0,1"
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|
bitfld.long 0x0 10. "CTS,CTS level" "0,1"
|
|
bitfld.long 0x0 9. "CTSF,CTS change flag" "0,1"
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|
bitfld.long 0x0 8. "LBDF,LIN break detected flag" "0,1"
|
|
bitfld.long 0x0 7. "TBE_TFNF,When FIFO is disabled:" "0,1"
|
|
bitfld.long 0x0 6. "TC,Transmission completed" "0,1"
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|
bitfld.long 0x0 5. "RBNE_RFNE,Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEF,IDLE line detected flag" "0,1"
|
|
bitfld.long 0x0 3. "ORERR,Overrun error" "0,1"
|
|
bitfld.long 0x0 2. "NERR,Noise error flag" "0,1"
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|
bitfld.long 0x0 1. "FERR,Frame error flag" "0,1"
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|
bitfld.long 0x0 0. "PERR,Parity error flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "INTC,Interrupt status clear register"
|
|
bitfld.long 0x0 20. "WUC,Wakeup from Deep-sleep mode clear" "0,1"
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|
bitfld.long 0x0 17. "AMC0,ADDR0 match clear" "0,1"
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bitfld.long 0x0 16. "AMC1,ADDR1 match clear" "0,1"
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bitfld.long 0x0 12. "EBC,End of block clear" "0,1"
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bitfld.long 0x0 11. "RTC,Receiver timeout clear" "0,1"
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|
bitfld.long 0x0 9. "CTSC,CTS change clear" "0,1"
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|
bitfld.long 0x0 8. "LBDC,LIN break detected clear" "0,1"
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|
bitfld.long 0x0 6. "TCC,Transmission complete clear" "0,1"
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newline
|
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bitfld.long 0x0 4. "IDLEC,Idle line detected clear" "0,1"
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|
bitfld.long 0x0 3. "OREC,Overrun error clear" "0,1"
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|
bitfld.long 0x0 2. "NEC,Noise detected clear" "0,1"
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bitfld.long 0x0 1. "FEC,Frame error flag clear" "0,1"
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|
bitfld.long 0x0 0. "PEC,Parity error clear" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "RDATA,Receive data register"
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hexmask.long.word 0x0 0.--9. 1. "RDATA,Receive Data value"
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group.long 0x28++0x3
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line.long 0x0 "TDATA,Transmit data register"
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hexmask.long.word 0x0 0.--9. 1. "TDATA,Transmit Data value"
|
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group.long 0xC0++0x3
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line.long 0x0 "CHC,USART coherence control register"
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bitfld.long 0x0 8. "EPERR,Early parity error flag" "0,1"
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bitfld.long 0x0 0. "HCM,Hardware flow control coherence mode" "0,1"
|
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group.long 0xD0++0x3
|
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line.long 0x0 "FCS,USART FIFO control and status register"
|
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bitfld.long 0x0 31. "TFEIE,Transmit FIFO empty interrupt enable" "0,1"
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bitfld.long 0x0 29. "TFTIE,Transmit FIFO threshold interrupt enable" "0,1"
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bitfld.long 0x0 27. "RFTIE,Receive FIFO threshold interrupt enable" "0,1"
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bitfld.long 0x0 26. "TFEC,Transmit FIFO empty flag clear" "0,1"
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rbitfld.long 0x0 25. "TFTIF,Transmit FIFO threshold interrupt flag" "0,1"
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rbitfld.long 0x0 24. "TFEIF,Transmit FIFO empty interrupt flag" "0,1"
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rbitfld.long 0x0 22. "RFTIF,Receive FIFO threshold interrupt flag" "0,1"
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bitfld.long 0x0 19.--21. "TFTCFG,Transmit FIFO threshold configuration" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x0 16.--18. "RFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 15. "RFFIF,Receive FIFO full interrupt flag" "0,1"
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rbitfld.long 0x0 12.--14. "RFCNT,Receive FIFO counter number" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 11. "RFF,Receive FIFO full flag" "0,1"
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bitfld.long 0x0 10. "RFE,Receive FIFO empty flag" "0,1"
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bitfld.long 0x0 9. "RFFIE,Receive FIFO full interrupt enable" "0,1"
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bitfld.long 0x0 8. "FEN,FIFO enable" "0,1"
|
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rbitfld.long 0x0 7. "TFF,Transmit FIFO full flag" "0,1"
|
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newline
|
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rbitfld.long 0x0 6. "TFE,Transmit FIFO empty flag" "0,1"
|
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bitfld.long 0x0 5. "TFT,Transmit FIFO threshold flag" "0,1"
|
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rbitfld.long 0x0 4. "RFT,Receive FIFO threshold flag" "0,1"
|
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rbitfld.long 0x0 1.--2. "RFCNT_3_4,Bit 3_4 of receive FIFO counter number" "0,1,2,3"
|
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bitfld.long 0x0 0. "ELNACK,Early NACK when smartcard mode is selected" "0,1"
|
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tree.end
|
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tree "USART1"
|
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base ad:0x40004400
|
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group.long 0x0++0x17
|
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line.long 0x0 "CTL0,Control register 0"
|
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bitfld.long 0x0 31. "AMIE1,ADDR1 match interrupt enable" "0,1"
|
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bitfld.long 0x0 28. "WL1,Word length 1" "0,1"
|
|
bitfld.long 0x0 27. "EBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTIE,Receiver timeout interrupt enable" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEA,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DED,Driver Enable de-assertion time"
|
|
bitfld.long 0x0 15. "OVSMOD,Oversample mode" "0,1"
|
|
bitfld.long 0x0 14. "AMIE0,ADDR0 match interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MEN,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "WL0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WM,Wakeup method in mute mode" "0,1"
|
|
bitfld.long 0x0 10. "PCEN,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PM,Parity mode" "0,1"
|
|
bitfld.long 0x0 8. "PERRIE,Parity error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TBEIE_TFNFIE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RBNEIE_RFNEIE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE line detected interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TEN,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "REN,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Deep-sleep mode" "0,1"
|
|
bitfld.long 0x0 0. "UEN,USART enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADDR0,Address 0 of the USART terminal"
|
|
bitfld.long 0x4 23. "RTEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBF,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "DINV,Data bit level inversion" "0,1"
|
|
bitfld.long 0x4 17. "TINV,TX pin level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RINV,RX pin level inversion" "0,1"
|
|
bitfld.long 0x4 15. "STRP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LMEN,LIN mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STB,STOP bits length" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CKEN,CK pin enable" "0,1"
|
|
bitfld.long 0x4 10. "CPL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPH,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "CLEN,CK length" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBLEN,LIN break frame length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM0,Address detection mode 0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "AMEN0,Match Address Mode Enable 0" "0,1"
|
|
line.long 0x8 "CTL2,Control register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. "ADDR1,Address 1 of the USART terminal"
|
|
bitfld.long 0x8 23. "ADDM1,Address detection mode 1" "0,1"
|
|
bitfld.long 0x8 22. "WUIE,Wakeup from Deep-sleep mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUM,Wakeup mode from Deep-sleep mode" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCRTNUM,Smartcard auto-retry number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16. "AMEN1,Match Address Mode Enable 1" "0,1"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity mode" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,Disable DMA on reception error" "0,1"
|
|
bitfld.long 0x8 12. "OVRD,Overrun disable" "0,1"
|
|
bitfld.long 0x8 11. "OSB,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSEN,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSEN,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DENT,DMA enable for transmission" "0,1"
|
|
bitfld.long 0x8 6. "DENR,DMA enable for reception" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NKEN,NACK enable in Smartcard mode" "0,1"
|
|
bitfld.long 0x8 3. "HDEN,Half-duplex enable" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0,1"
|
|
bitfld.long 0x8 0. "ERRIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BAUD,Baud rate generator register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_INT,Integer of baud-rate divider"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_DIV,Fraction of baud-rate divider"
|
|
line.long 0x10 "GP,Prescaler and guard time configuration register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GUAT,Guard time value in smartcard mode"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value for dividing the system clock"
|
|
line.long 0x14 "RT,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BL,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RT,Receiver timeout threshold"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "CMD,Command register"
|
|
bitfld.long 0x0 4. "TXFCMD,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFCMD,Receive data flush command" "0,1"
|
|
bitfld.long 0x0 2. "MMCMD,Mute mode command" "0,1"
|
|
bitfld.long 0x0 1. "SBKCMD,Send break command" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "STAT,Status register"
|
|
bitfld.long 0x0 22. "REA,Receive enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 21. "TEA,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from Deep-sleep mode flag" "0,1"
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from mute mode" "0,1"
|
|
bitfld.long 0x0 18. "SBF,Send break flag" "0,1"
|
|
bitfld.long 0x0 17. "AMF0,ADDR0 match flag" "0,1"
|
|
bitfld.long 0x0 16. "BSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 13. "AMF1,ADDR1 match flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EBF,End of block flag" "0,1"
|
|
bitfld.long 0x0 11. "RTF,Receiver timeout flag" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS level" "0,1"
|
|
bitfld.long 0x0 9. "CTSF,CTS change flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detected flag" "0,1"
|
|
bitfld.long 0x0 7. "TBE_TFNF,When FIFO is disabled:" "0,1"
|
|
bitfld.long 0x0 6. "TC,Transmission completed" "0,1"
|
|
bitfld.long 0x0 5. "RBNE_RFNE,Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEF,IDLE line detected flag" "0,1"
|
|
bitfld.long 0x0 3. "ORERR,Overrun error" "0,1"
|
|
bitfld.long 0x0 2. "NERR,Noise error flag" "0,1"
|
|
bitfld.long 0x0 1. "FERR,Frame error flag" "0,1"
|
|
bitfld.long 0x0 0. "PERR,Parity error flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "INTC,Interrupt status clear register"
|
|
bitfld.long 0x0 20. "WUC,Wakeup from Deep-sleep mode clear" "0,1"
|
|
bitfld.long 0x0 17. "AMC0,ADDR0 match clear" "0,1"
|
|
bitfld.long 0x0 16. "AMC1,ADDR1 match clear" "0,1"
|
|
bitfld.long 0x0 12. "EBC,End of block clear" "0,1"
|
|
bitfld.long 0x0 11. "RTC,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSC,CTS change clear" "0,1"
|
|
bitfld.long 0x0 8. "LBDC,LIN break detected clear" "0,1"
|
|
bitfld.long 0x0 6. "TCC,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEC,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "OREC,Overrun error clear" "0,1"
|
|
bitfld.long 0x0 2. "NEC,Noise detected clear" "0,1"
|
|
bitfld.long 0x0 1. "FEC,Frame error flag clear" "0,1"
|
|
bitfld.long 0x0 0. "PEC,Parity error clear" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDATA,Receive data register"
|
|
hexmask.long.word 0x0 0.--9. 1. "RDATA,Receive Data value"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TDATA,Transmit data register"
|
|
hexmask.long.word 0x0 0.--9. 1. "TDATA,Transmit Data value"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "CHC,USART coherence control register"
|
|
bitfld.long 0x0 8. "EPERR,Early parity error flag" "0,1"
|
|
bitfld.long 0x0 0. "HCM,Hardware flow control coherence mode" "0,1"
|
|
group.long 0xD0++0x3
|
|
line.long 0x0 "FCS,USART FIFO control and status register"
|
|
bitfld.long 0x0 31. "TFEIE,Transmit FIFO empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 29. "TFTIE,Transmit FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 27. "RFTIE,Receive FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "TFEC,Transmit FIFO empty flag clear" "0,1"
|
|
rbitfld.long 0x0 25. "TFTIF,Transmit FIFO threshold interrupt flag" "0,1"
|
|
rbitfld.long 0x0 24. "TFEIF,Transmit FIFO empty interrupt flag" "0,1"
|
|
rbitfld.long 0x0 22. "RFTIF,Receive FIFO threshold interrupt flag" "0,1"
|
|
bitfld.long 0x0 19.--21. "TFTCFG,Transmit FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "RFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15. "RFFIF,Receive FIFO full interrupt flag" "0,1"
|
|
rbitfld.long 0x0 12.--14. "RFCNT,Receive FIFO counter number" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x0 11. "RFF,Receive FIFO full flag" "0,1"
|
|
bitfld.long 0x0 10. "RFE,Receive FIFO empty flag" "0,1"
|
|
bitfld.long 0x0 9. "RFFIE,Receive FIFO full interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "FEN,FIFO enable" "0,1"
|
|
rbitfld.long 0x0 7. "TFF,Transmit FIFO full flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 6. "TFE,Transmit FIFO empty flag" "0,1"
|
|
bitfld.long 0x0 5. "TFT,Transmit FIFO threshold flag" "0,1"
|
|
rbitfld.long 0x0 4. "RFT,Receive FIFO threshold flag" "0,1"
|
|
rbitfld.long 0x0 1.--2. "RFCNT_3_4,Bit 3_4 of receive FIFO counter number" "0,1,2,3"
|
|
bitfld.long 0x0 0. "ELNACK,Early NACK when smartcard mode is selected" "0,1"
|
|
tree.end
|
|
tree "USART2"
|
|
base ad:0x40004800
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 31. "AMIE1,ADDR1 match interrupt enable" "0,1"
|
|
bitfld.long 0x0 28. "WL1,Word length 1" "0,1"
|
|
bitfld.long 0x0 27. "EBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTIE,Receiver timeout interrupt enable" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEA,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DED,Driver Enable de-assertion time"
|
|
bitfld.long 0x0 15. "OVSMOD,Oversample mode" "0,1"
|
|
bitfld.long 0x0 14. "AMIE0,ADDR0 match interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MEN,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "WL0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WM,Wakeup method in mute mode" "0,1"
|
|
bitfld.long 0x0 10. "PCEN,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PM,Parity mode" "0,1"
|
|
bitfld.long 0x0 8. "PERRIE,Parity error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TBEIE_TFNFIE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RBNEIE_RFNEIE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE line detected interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TEN,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "REN,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Deep-sleep mode" "0,1"
|
|
bitfld.long 0x0 0. "UEN,USART enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADDR0,Address 0 of the USART terminal"
|
|
bitfld.long 0x4 23. "RTEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBF,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "DINV,Data bit level inversion" "0,1"
|
|
bitfld.long 0x4 17. "TINV,TX pin level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RINV,RX pin level inversion" "0,1"
|
|
bitfld.long 0x4 15. "STRP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LMEN,LIN mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STB,STOP bits length" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CKEN,CK pin enable" "0,1"
|
|
bitfld.long 0x4 10. "CPL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPH,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "CLEN,CK length" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBLEN,LIN break frame length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM0,Address detection mode 0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "AMEN0,Match Address Mode Enable 0" "0,1"
|
|
line.long 0x8 "CTL2,Control register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. "ADDR1,Address 1 of the USART terminal"
|
|
bitfld.long 0x8 23. "ADDM1,Address detection mode 1" "0,1"
|
|
bitfld.long 0x8 22. "WUIE,Wakeup from Deep-sleep mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUM,Wakeup mode from Deep-sleep mode" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCRTNUM,Smartcard auto-retry number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16. "AMEN1,Match Address Mode Enable 1" "0,1"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity mode" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,Disable DMA on reception error" "0,1"
|
|
bitfld.long 0x8 12. "OVRD,Overrun disable" "0,1"
|
|
bitfld.long 0x8 11. "OSB,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSEN,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSEN,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DENT,DMA enable for transmission" "0,1"
|
|
bitfld.long 0x8 6. "DENR,DMA enable for reception" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NKEN,NACK enable in Smartcard mode" "0,1"
|
|
bitfld.long 0x8 3. "HDEN,Half-duplex enable" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0,1"
|
|
bitfld.long 0x8 0. "ERRIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BAUD,Baud rate generator register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_INT,Integer of baud-rate divider"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_DIV,Fraction of baud-rate divider"
|
|
line.long 0x10 "GP,Prescaler and guard time configuration register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GUAT,Guard time value in smartcard mode"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value for dividing the system clock"
|
|
line.long 0x14 "RT,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BL,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RT,Receiver timeout threshold"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "CMD,Command register"
|
|
bitfld.long 0x0 4. "TXFCMD,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFCMD,Receive data flush command" "0,1"
|
|
bitfld.long 0x0 2. "MMCMD,Mute mode command" "0,1"
|
|
bitfld.long 0x0 1. "SBKCMD,Send break command" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "STAT,Status register"
|
|
bitfld.long 0x0 22. "REA,Receive enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 21. "TEA,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from Deep-sleep mode flag" "0,1"
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from mute mode" "0,1"
|
|
bitfld.long 0x0 18. "SBF,Send break flag" "0,1"
|
|
bitfld.long 0x0 17. "AMF0,ADDR0 match flag" "0,1"
|
|
bitfld.long 0x0 16. "BSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 13. "AMF1,ADDR1 match flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EBF,End of block flag" "0,1"
|
|
bitfld.long 0x0 11. "RTF,Receiver timeout flag" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS level" "0,1"
|
|
bitfld.long 0x0 9. "CTSF,CTS change flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detected flag" "0,1"
|
|
bitfld.long 0x0 7. "TBE_TFNF,When FIFO is disabled:" "0,1"
|
|
bitfld.long 0x0 6. "TC,Transmission completed" "0,1"
|
|
bitfld.long 0x0 5. "RBNE_RFNE,Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEF,IDLE line detected flag" "0,1"
|
|
bitfld.long 0x0 3. "ORERR,Overrun error" "0,1"
|
|
bitfld.long 0x0 2. "NERR,Noise error flag" "0,1"
|
|
bitfld.long 0x0 1. "FERR,Frame error flag" "0,1"
|
|
bitfld.long 0x0 0. "PERR,Parity error flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "INTC,Interrupt status clear register"
|
|
bitfld.long 0x0 20. "WUC,Wakeup from Deep-sleep mode clear" "0,1"
|
|
bitfld.long 0x0 17. "AMC0,ADDR0 match clear" "0,1"
|
|
bitfld.long 0x0 16. "AMC1,ADDR1 match clear" "0,1"
|
|
bitfld.long 0x0 12. "EBC,End of block clear" "0,1"
|
|
bitfld.long 0x0 11. "RTC,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSC,CTS change clear" "0,1"
|
|
bitfld.long 0x0 8. "LBDC,LIN break detected clear" "0,1"
|
|
bitfld.long 0x0 6. "TCC,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEC,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "OREC,Overrun error clear" "0,1"
|
|
bitfld.long 0x0 2. "NEC,Noise detected clear" "0,1"
|
|
bitfld.long 0x0 1. "FEC,Frame error flag clear" "0,1"
|
|
bitfld.long 0x0 0. "PEC,Parity error clear" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDATA,Receive data register"
|
|
hexmask.long.word 0x0 0.--9. 1. "RDATA,Receive Data value"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TDATA,Transmit data register"
|
|
hexmask.long.word 0x0 0.--9. 1. "TDATA,Transmit Data value"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "CHC,USART coherence control register"
|
|
bitfld.long 0x0 8. "EPERR,Early parity error flag" "0,1"
|
|
bitfld.long 0x0 0. "HCM,Hardware flow control coherence mode" "0,1"
|
|
group.long 0xD0++0x3
|
|
line.long 0x0 "FCS,USART FIFO control and status register"
|
|
bitfld.long 0x0 31. "TFEIE,Transmit FIFO empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 29. "TFTIE,Transmit FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 27. "RFTIE,Receive FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "TFEC,Transmit FIFO empty flag clear" "0,1"
|
|
rbitfld.long 0x0 25. "TFTIF,Transmit FIFO threshold interrupt flag" "0,1"
|
|
rbitfld.long 0x0 24. "TFEIF,Transmit FIFO empty interrupt flag" "0,1"
|
|
rbitfld.long 0x0 22. "RFTIF,Receive FIFO threshold interrupt flag" "0,1"
|
|
bitfld.long 0x0 19.--21. "TFTCFG,Transmit FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "RFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15. "RFFIF,Receive FIFO full interrupt flag" "0,1"
|
|
rbitfld.long 0x0 12.--14. "RFCNT,Receive FIFO counter number" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x0 11. "RFF,Receive FIFO full flag" "0,1"
|
|
bitfld.long 0x0 10. "RFE,Receive FIFO empty flag" "0,1"
|
|
bitfld.long 0x0 9. "RFFIE,Receive FIFO full interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "FEN,FIFO enable" "0,1"
|
|
rbitfld.long 0x0 7. "TFF,Transmit FIFO full flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 6. "TFE,Transmit FIFO empty flag" "0,1"
|
|
bitfld.long 0x0 5. "TFT,Transmit FIFO threshold flag" "0,1"
|
|
rbitfld.long 0x0 4. "RFT,Receive FIFO threshold flag" "0,1"
|
|
rbitfld.long 0x0 1.--2. "RFCNT_3_4,Bit 3_4 of receive FIFO counter number" "0,1,2,3"
|
|
bitfld.long 0x0 0. "ELNACK,Early NACK when smartcard mode is selected" "0,1"
|
|
tree.end
|
|
tree "USART5"
|
|
base ad:0x40011400
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTL0,Control register 0"
|
|
bitfld.long 0x0 31. "AMIE1,ADDR1 match interrupt enable" "0,1"
|
|
bitfld.long 0x0 28. "WL1,Word length 1" "0,1"
|
|
bitfld.long 0x0 27. "EBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTIE,Receiver timeout interrupt enable" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEA,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DED,Driver Enable de-assertion time"
|
|
bitfld.long 0x0 15. "OVSMOD,Oversample mode" "0,1"
|
|
bitfld.long 0x0 14. "AMIE0,ADDR0 match interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MEN,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "WL0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WM,Wakeup method in mute mode" "0,1"
|
|
bitfld.long 0x0 10. "PCEN,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PM,Parity mode" "0,1"
|
|
bitfld.long 0x0 8. "PERRIE,Parity error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TBEIE_TFNFIE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RBNEIE_RFNEIE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE line detected interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TEN,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "REN,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Deep-sleep mode" "0,1"
|
|
bitfld.long 0x0 0. "UEN,USART enable" "0,1"
|
|
line.long 0x4 "CTL1,Control register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADDR0,Address 0 of the USART terminal"
|
|
bitfld.long 0x4 23. "RTEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBF,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "DINV,Data bit level inversion" "0,1"
|
|
bitfld.long 0x4 17. "TINV,TX pin level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RINV,RX pin level inversion" "0,1"
|
|
bitfld.long 0x4 15. "STRP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LMEN,LIN mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STB,STOP bits length" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CKEN,CK pin enable" "0,1"
|
|
bitfld.long 0x4 10. "CPL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPH,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "CLEN,CK length" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBLEN,LIN break frame length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM0,Address detection mode 0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "AMEN0,Match Address Mode Enable 0" "0,1"
|
|
line.long 0x8 "CTL2,Control register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. "ADDR1,Address 1 of the USART terminal"
|
|
bitfld.long 0x8 23. "ADDM1,Address detection mode 1" "0,1"
|
|
bitfld.long 0x8 22. "WUIE,Wakeup from Deep-sleep mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUM,Wakeup mode from Deep-sleep mode" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCRTNUM,Smartcard auto-retry number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16. "AMEN1,Match Address Mode Enable 1" "0,1"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity mode" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,Disable DMA on reception error" "0,1"
|
|
bitfld.long 0x8 12. "OVRD,Overrun disable" "0,1"
|
|
bitfld.long 0x8 11. "OSB,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSEN,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSEN,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DENT,DMA enable for transmission" "0,1"
|
|
bitfld.long 0x8 6. "DENR,DMA enable for reception" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NKEN,NACK enable in Smartcard mode" "0,1"
|
|
bitfld.long 0x8 3. "HDEN,Half-duplex enable" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0,1"
|
|
bitfld.long 0x8 0. "ERRIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BAUD,Baud rate generator register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_INT,Integer of baud-rate divider"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_DIV,Fraction of baud-rate divider"
|
|
line.long 0x10 "GP,Prescaler and guard time configuration register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GUAT,Guard time value in smartcard mode"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value for dividing the system clock"
|
|
line.long 0x14 "RT,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BL,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RT,Receiver timeout threshold"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "CMD,Command register"
|
|
bitfld.long 0x0 4. "TXFCMD,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFCMD,Receive data flush command" "0,1"
|
|
bitfld.long 0x0 2. "MMCMD,Mute mode command" "0,1"
|
|
bitfld.long 0x0 1. "SBKCMD,Send break command" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "STAT,Status register"
|
|
bitfld.long 0x0 22. "REA,Receive enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 21. "TEA,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from Deep-sleep mode flag" "0,1"
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from mute mode" "0,1"
|
|
bitfld.long 0x0 18. "SBF,Send break flag" "0,1"
|
|
bitfld.long 0x0 17. "AMF0,ADDR0 match flag" "0,1"
|
|
bitfld.long 0x0 16. "BSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 13. "AMF1,ADDR1 match flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EBF,End of block flag" "0,1"
|
|
bitfld.long 0x0 11. "RTF,Receiver timeout flag" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS level" "0,1"
|
|
bitfld.long 0x0 9. "CTSF,CTS change flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detected flag" "0,1"
|
|
bitfld.long 0x0 7. "TBE_TFNF,When FIFO is disabled:" "0,1"
|
|
bitfld.long 0x0 6. "TC,Transmission completed" "0,1"
|
|
bitfld.long 0x0 5. "RBNE_RFNE,Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEF,IDLE line detected flag" "0,1"
|
|
bitfld.long 0x0 3. "ORERR,Overrun error" "0,1"
|
|
bitfld.long 0x0 2. "NERR,Noise error flag" "0,1"
|
|
bitfld.long 0x0 1. "FERR,Frame error flag" "0,1"
|
|
bitfld.long 0x0 0. "PERR,Parity error flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "INTC,Interrupt status clear register"
|
|
bitfld.long 0x0 20. "WUC,Wakeup from Deep-sleep mode clear" "0,1"
|
|
bitfld.long 0x0 17. "AMC0,ADDR0 match clear" "0,1"
|
|
bitfld.long 0x0 16. "AMC1,ADDR1 match clear" "0,1"
|
|
bitfld.long 0x0 12. "EBC,End of block clear" "0,1"
|
|
bitfld.long 0x0 11. "RTC,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSC,CTS change clear" "0,1"
|
|
bitfld.long 0x0 8. "LBDC,LIN break detected clear" "0,1"
|
|
bitfld.long 0x0 6. "TCC,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEC,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "OREC,Overrun error clear" "0,1"
|
|
bitfld.long 0x0 2. "NEC,Noise detected clear" "0,1"
|
|
bitfld.long 0x0 1. "FEC,Frame error flag clear" "0,1"
|
|
bitfld.long 0x0 0. "PEC,Parity error clear" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDATA,Receive data register"
|
|
hexmask.long.word 0x0 0.--9. 1. "RDATA,Receive Data value"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TDATA,Transmit data register"
|
|
hexmask.long.word 0x0 0.--9. 1. "TDATA,Transmit Data value"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "CHC,USART coherence control register"
|
|
bitfld.long 0x0 8. "EPERR,Early parity error flag" "0,1"
|
|
bitfld.long 0x0 0. "HCM,Hardware flow control coherence mode" "0,1"
|
|
group.long 0xD0++0x3
|
|
line.long 0x0 "FCS,USART FIFO control and status register"
|
|
bitfld.long 0x0 31. "TFEIE,Transmit FIFO empty interrupt enable" "0,1"
|
|
bitfld.long 0x0 29. "TFTIE,Transmit FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 27. "RFTIE,Receive FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "TFEC,Transmit FIFO empty flag clear" "0,1"
|
|
rbitfld.long 0x0 25. "TFTIF,Transmit FIFO threshold interrupt flag" "0,1"
|
|
rbitfld.long 0x0 24. "TFEIF,Transmit FIFO empty interrupt flag" "0,1"
|
|
rbitfld.long 0x0 22. "RFTIF,Receive FIFO threshold interrupt flag" "0,1"
|
|
bitfld.long 0x0 19.--21. "TFTCFG,Transmit FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "RFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15. "RFFIF,Receive FIFO full interrupt flag" "0,1"
|
|
rbitfld.long 0x0 12.--14. "RFCNT,Receive FIFO counter number" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x0 11. "RFF,Receive FIFO full flag" "0,1"
|
|
bitfld.long 0x0 10. "RFE,Receive FIFO empty flag" "0,1"
|
|
bitfld.long 0x0 9. "RFFIE,Receive FIFO full interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "FEN,FIFO enable" "0,1"
|
|
rbitfld.long 0x0 7. "TFF,Transmit FIFO full flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 6. "TFE,Transmit FIFO empty flag" "0,1"
|
|
bitfld.long 0x0 5. "TFT,Transmit FIFO threshold flag" "0,1"
|
|
rbitfld.long 0x0 4. "RFT,Receive FIFO threshold flag" "0,1"
|
|
rbitfld.long 0x0 1.--2. "RFCNT_3_4,Bit 3_4 of receive FIFO counter number" "0,1,2,3"
|
|
bitfld.long 0x0 0. "ELNACK,Early NACK when smartcard mode is selected" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "USBHS (Universal Serial Bus High-Speed Interface)"
|
|
base ad:0x0
|
|
tree "USBHS0"
|
|
tree "USBHS0_DEVICE"
|
|
base ad:0x40040800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DCFG,device configuration register"
|
|
bitfld.long 0x0 11.--12. "EOPFT,end of periodic frame time" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--10. 1. "DAR,Device address"
|
|
bitfld.long 0x0 2. "NZLSOH,Non-zero-length status OUT" "0,1"
|
|
bitfld.long 0x0 0.--1. "DS,Device speed" "0,1,2,3"
|
|
line.long 0x4 "DCTL,device control register"
|
|
bitfld.long 0x4 18. "L1RJCT,Deep sleep reject" "0,1"
|
|
bitfld.long 0x4 11. "POIF,Power-on initialization flag" "0,1"
|
|
bitfld.long 0x4 10. "CGONAK,Clear global OUT NAK" "0,1"
|
|
bitfld.long 0x4 9. "SGONAK,Set global OUT NAK" "0,1"
|
|
bitfld.long 0x4 8. "CGINAK,Clear global IN NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "SGINAK,Set global IN NAK" "0,1"
|
|
bitfld.long 0x4 4.--6. "DTEST,Device Test control" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x4 3. "GONS,Global OUT NAK status" "0,1"
|
|
rbitfld.long 0x4 2. "GINS,Global IN NAK status" "0,1"
|
|
bitfld.long 0x4 1. "SD,Soft disconnect" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RWKUP,Remote wakeup" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "DSTAT,device status register"
|
|
hexmask.long.word 0x0 8.--21. 1. "FNRSOF,Frame number of the received"
|
|
bitfld.long 0x0 1.--2. "ES,Enumerated speed" "0,1,2,3"
|
|
bitfld.long 0x0 0. "SPST,Suspend status" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "DIEPINTEN,device IN endpoint common interrupt"
|
|
bitfld.long 0x0 13. "NAKEN,NAK handshake sent by USBHS interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 6. "IEPNEEN,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUDEN,Endpoint Tx FIFO underrun interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 3. "CITOEN,Control IN timeout condition interrupt enable (Non-isochronous" "0,1"
|
|
bitfld.long 0x0 1. "EPDISEN,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TFEN,Transfer finished interrupt" "0,1"
|
|
line.long 0x4 "DOEPINTEN,device OUT endpoint common interrupt"
|
|
bitfld.long 0x4 14. "NYETEN,Send NYET handshake interrupt enable bit" "0,1"
|
|
bitfld.long 0x4 6. "BTBSTPEN,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x4 4. "EPRXFOVREN,Endpoint Rx FIFO overrun interrupt enable" "0,1"
|
|
bitfld.long 0x4 3. "STPFEN,SETUP phase finished interrupt enable" "0,1"
|
|
bitfld.long 0x4 1. "EPDISEN,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TFEN,Transfer finished interrupt" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "DAEPINT,device all endpoints interrupt"
|
|
hexmask.long.byte 0x0 16.--21. 1. "OEPITB,Device all OUT endpoint interrupt bits"
|
|
hexmask.long.byte 0x0 0.--5. 1. "IEPITB,Device all IN endpoint interrupt bits"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "DAEPINTEN,Device all endpoints interrupt enable register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "OEPIE,OUT endpoint interrupt enable bits"
|
|
hexmask.long.byte 0x0 0.--5. 1. "IEPIE,IN EP interrupt interrupt enable bits"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "DVBUSDT,device VBUS discharge time"
|
|
hexmask.long.word 0x0 0.--15. 1. "DVBUSDT,Device VBUS discharge time"
|
|
line.long 0x4 "DVBUSPT,device VBUS pulsing time"
|
|
hexmask.long.word 0x4 0.--11. 1. "DVBUSPT,Device VBUS pulsing time"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "DIEPFEINTEN,device IN endpoint FIFO empty"
|
|
hexmask.long.byte 0x0 0.--5. 1. "IEPTXFEIE,IN EP Tx FIFO empty interrupt enable"
|
|
rgroup.long 0x38++0x7
|
|
line.long 0x0 "DEP1INT,Device endpoint 1 interrupt register"
|
|
bitfld.long 0x0 17. "OEP1INT,OUT Endpoint 1 interrupt" "0,1"
|
|
bitfld.long 0x0 1. "IEP1INT,IN Endpoint 1 interrupt" "0,1"
|
|
line.long 0x4 "DEP1INTEN,Device endpoint 1 interrupt register"
|
|
bitfld.long 0x4 17. "OEP1INTEN,OUT Endpoint 1 interrupt enable" "0,1"
|
|
bitfld.long 0x4 1. "IEP1INTEN,IN Endpoint 1 interrupt enable" "0,1"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "DIEP1INTEN,Device IN endpoint 1 interrupt enable register"
|
|
bitfld.long 0x0 13. "NAKEN,Interrupt enable bit of NAK handshake sent by USBHS" "0,1"
|
|
bitfld.long 0x0 6. "IEPNEEN,IN endpoint NAK effective interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUDEN,Endpoint Tx FIFO underrun interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 3. "CITOEN,Control In Timeout interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 1. "EPDISEN,Endpoint disabled interrupt enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TFEN,Transfer finished interrupt enable bit" "0,1"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "DOEP1INTEN,Device OUT endpoint 1 interrupt enable register"
|
|
bitfld.long 0x0 13. "NYETEN,Send NYET handshake interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTPEN,Back-to-back SETUP packets interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVREN,Endpoint Rx FIFO over run interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 3. "STPFEN,SETUP phase finished interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 1. "EPDISEN,Endpoint disabled interrupt enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TFEN,Transfer finished interrupt enable bit" "0,1"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "DIEP0CTL,device IN endpoint 0 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
rbitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
rbitfld.long 0x0 15. "EPACT,endpoint active" "0,1"
|
|
bitfld.long 0x0 0.--1. "MPL,Maximum packet length" "0,1,2,3"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "DIEP1CTL,device in endpoint-1 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "DIEP2CTL,device endpoint-2 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "DIEP3CTL,device endpoint-3 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "DIEP4CTL,device endpoint-4 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x0 "DIEP5CTL,device endpoint-5 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x1C0++0x3
|
|
line.long 0x0 "DIEP6CTL,device endpoint-6 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x1E0++0x3
|
|
line.long 0x0 "DIEP7CTL,device endpoint-7 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x300++0x3
|
|
line.long 0x0 "DOEP0CTL,device endpoint-0 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
rbitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SNOOP,Snoop mode" "0,1"
|
|
rbitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
rbitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
rbitfld.long 0x0 0.--1. "MPL,Maximum packet length" "0,1,2,3"
|
|
group.long 0x320++0x3
|
|
line.long 0x0 "DOEP1CTL,device endpoint-1 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNOOP,Snoop mode" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x340++0x3
|
|
line.long 0x0 "DOEP2CTL,device endpoint-2 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNOOP,Snoop mode" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x360++0x3
|
|
line.long 0x0 "DOEP3CTL,device endpoint-3 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNOOP,Snoop mode" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x380++0x3
|
|
line.long 0x0 "DOEP4CTL,device endpoint-4 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNOOP,Snoop mode" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x3A0++0x3
|
|
line.long 0x0 "DOEP5CTL,device endpoint-5 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNOOP,Snoop mode" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x3C0++0x3
|
|
line.long 0x0 "DOEP6CTL,device endpoint-6 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNOOP,Snoop mode" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x3E0++0x3
|
|
line.long 0x0 "DOEP7CTL,device endpoint-7 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNOOP,Snoop mode" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "DIEP0INTF,device endpoint-0 interrupt"
|
|
bitfld.long 0x0 13. "NAK,NAK handshake sent by USBHS" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x0 6. "IEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
|
|
bitfld.long 0x0 3. "CITO,Control in timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint finished" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "DIEP1INTF,device endpoint-1 interrupt"
|
|
bitfld.long 0x0 13. "NAK,NAK handshake sent by USBHS" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x0 6. "IEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
|
|
bitfld.long 0x0 3. "CITO,Control in timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint finished" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x148++0x3
|
|
line.long 0x0 "DIEP2INTF,device endpoint-2 interrupt"
|
|
bitfld.long 0x0 13. "NAK,NAK handshake sent by USBHS" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x0 6. "IEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
|
|
bitfld.long 0x0 3. "CITO,Control in timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint finished" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x168++0x3
|
|
line.long 0x0 "DIEP3INTF,device endpoint-3 interrupt"
|
|
bitfld.long 0x0 13. "NAK,NAK handshake sent by USBHS" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x0 6. "IEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
|
|
bitfld.long 0x0 3. "CITO,Control in timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint finished" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x188++0x3
|
|
line.long 0x0 "DIEP4INTF,device endpoint-4 interrupt"
|
|
bitfld.long 0x0 13. "NAK,NAK handshake sent by USBHS" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x0 6. "IEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
|
|
bitfld.long 0x0 3. "CITO,Control in timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint finished" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x1A8++0x3
|
|
line.long 0x0 "DIEP5INTF,device endpoint-5 interrupt"
|
|
bitfld.long 0x0 13. "NAK,NAK handshake sent by USBHS" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x0 6. "IEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
|
|
bitfld.long 0x0 3. "CITO,Control in timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint finished" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x1C8++0x3
|
|
line.long 0x0 "DIEP6INTF,device endpoint-6 interrupt"
|
|
bitfld.long 0x0 13. "NAK,NAK handshake sent by USBHS" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x0 6. "IEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
|
|
bitfld.long 0x0 3. "CITO,Control in timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint finished" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x1E8++0x3
|
|
line.long 0x0 "DIEP7INTF,device endpoint-7 interrupt"
|
|
bitfld.long 0x0 13. "NAK,NAK handshake sent by USBHS" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x0 6. "IEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
|
|
bitfld.long 0x0 3. "CITO,Control in timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint finished" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "DOEP0INTF,device out endpoint-0 interrupt flag"
|
|
bitfld.long 0x0 14. "NYET,NYET handshake is sent" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
|
|
bitfld.long 0x0 3. "STPF,Setup phase finished" "0,1"
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x328++0x3
|
|
line.long 0x0 "DOEP1INTF,device out endpoint-1 interrupt flag"
|
|
bitfld.long 0x0 14. "NYET,NYET handshake is sent" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
|
|
bitfld.long 0x0 3. "STPF,Setup phase finished" "0,1"
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x348++0x3
|
|
line.long 0x0 "DOEP2INTF,device out endpoint-2 interrupt flag"
|
|
bitfld.long 0x0 14. "NYET,NYET handshake is sent" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
|
|
bitfld.long 0x0 3. "STPF,Setup phase finished" "0,1"
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x368++0x3
|
|
line.long 0x0 "DOEP3INTF,device out endpoint-3 interrupt flag"
|
|
bitfld.long 0x0 14. "NYET,NYET handshake is sent" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
|
|
bitfld.long 0x0 3. "STPF,Setup phase finished" "0,1"
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x388++0x3
|
|
line.long 0x0 "DOEP4INTF,device out endpoint-4 interrupt flag"
|
|
bitfld.long 0x0 14. "NYET,NYET handshake is sent" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
|
|
bitfld.long 0x0 3. "STPF,Setup phase finished" "0,1"
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x3A8++0x3
|
|
line.long 0x0 "DOEP5INTF,device out endpoint-5 interrupt flag"
|
|
bitfld.long 0x0 14. "NYET,NYET handshake is sent" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
|
|
bitfld.long 0x0 3. "STPF,Setup phase finished" "0,1"
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x3C8++0x3
|
|
line.long 0x0 "DOEP6INTF,device out endpoint-6 interrupt flag"
|
|
bitfld.long 0x0 14. "NYET,NYET handshake is sent" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
|
|
bitfld.long 0x0 3. "STPF,Setup phase finished" "0,1"
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x3E8++0x3
|
|
line.long 0x0 "DOEP7INTF,device out endpoint-7 interrupt flag"
|
|
bitfld.long 0x0 14. "NYET,NYET handshake is sent" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
|
|
bitfld.long 0x0 3. "STPF,Setup phase finished" "0,1"
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "DIEP0LEN,device IN endpoint-0 transfer length"
|
|
bitfld.long 0x0 19.--20. "PCNT,Packet count" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TLEN,Transfer length"
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "DOEP0LEN,device OUT endpoint-0 transfer length"
|
|
bitfld.long 0x0 29.--30. "STPCNT,SETUP packet count" "0,1,2,3"
|
|
bitfld.long 0x0 19. "PCNT,Packet count" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TLEN,Transfer length"
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "DIEP1LEN,device IN endpoint-1 transfer length"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x150++0x3
|
|
line.long 0x0 "DIEP2LEN,device IN endpoint-2 transfer length"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x170++0x3
|
|
line.long 0x0 "DIEP3LEN,device IN endpoint-3 transfer length"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x190++0x3
|
|
line.long 0x0 "DIEP4LEN,device IN endpoint-4 transfer length"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x1B0++0x3
|
|
line.long 0x0 "DIEP5LEN,device IN endpoint-5 transfer length"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x1D0++0x3
|
|
line.long 0x0 "DIEP6LEN,device IN endpoint-6 transfer length"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x1F0++0x3
|
|
line.long 0x0 "DIEP7LEN,device IN endpoint-7 transfer length"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x330++0x3
|
|
line.long 0x0 "DOEP1LEN,device OUT endpoint-1 transfer length"
|
|
bitfld.long 0x0 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x350++0x3
|
|
line.long 0x0 "DOEP2LEN,device OUT endpoint-2 transfer length"
|
|
bitfld.long 0x0 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x370++0x3
|
|
line.long 0x0 "DOEP3LEN,device OUT endpoint-3 transfer length"
|
|
bitfld.long 0x0 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x390++0x3
|
|
line.long 0x0 "DOEP4LEN,device OUT endpoint-4 transfer length"
|
|
bitfld.long 0x0 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x3B0++0x3
|
|
line.long 0x0 "DOEP5LEN,device OUT endpoint-5 transfer length"
|
|
bitfld.long 0x0 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x3D0++0x3
|
|
line.long 0x0 "DOEP6LEN,device OUT endpoint-6 transfer length"
|
|
bitfld.long 0x0 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x3F0++0x3
|
|
line.long 0x0 "DOEP7LEN,device OUT endpoint-7 transfer length"
|
|
bitfld.long 0x0 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x114++0x3
|
|
line.long 0x0 "DIEP0DMAADDR,Device IN endpoint 0 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x134++0x3
|
|
line.long 0x0 "DIEP1DMAADDR,Device IN endpoint 1 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x154++0x3
|
|
line.long 0x0 "DIEP2DMAADDR,Device IN endpoint 2 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x174++0x3
|
|
line.long 0x0 "DIEP3DMAADDR,Device IN endpoint 3 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x194++0x3
|
|
line.long 0x0 "DIEP4DMAADDR,Device IN endpoint 4 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x1B4++0x3
|
|
line.long 0x0 "DIEP5DMAADDR,Device IN endpoint 5 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x1D4++0x3
|
|
line.long 0x0 "DIEP6DMAADDR,Device IN endpoint 6 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x1F4++0x3
|
|
line.long 0x0 "DIEP7DMAADDR,Device IN endpoint 7 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x314++0x3
|
|
line.long 0x0 "DOEP0DMAADDR,Device OUT endpoint 0 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x334++0x3
|
|
line.long 0x0 "DOEP1DMAADDR,Device OUT endpoint 1 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x354++0x3
|
|
line.long 0x0 "DOEP2DMAADDR,Device OUT endpoint 2 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x374++0x3
|
|
line.long 0x0 "DOEP3DMAADDR,Device OUT endpoint 3 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x394++0x3
|
|
line.long 0x0 "DOEP4DMAADDR,Device OUT endpoint 4 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x3B4++0x3
|
|
line.long 0x0 "DOEP5DMAADDR,Device OUT endpoint 5 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x3D4++0x3
|
|
line.long 0x0 "DOEP6DMAADDR,Device OUT endpoint 6 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x3F4++0x3
|
|
line.long 0x0 "DOEP7DMAADDR,Device OUT endpoint 7 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
rgroup.long 0x118++0x3
|
|
line.long 0x0 "DIEP0TFSTAT,device IN endpoint 0 transmit FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space"
|
|
rgroup.long 0x138++0x3
|
|
line.long 0x0 "DIEP1TFSTAT,device IN endpoint 1 transmit FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space"
|
|
rgroup.long 0x158++0x3
|
|
line.long 0x0 "DIEP2TFSTAT,device IN endpoint 2 transmit FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space"
|
|
rgroup.long 0x178++0x3
|
|
line.long 0x0 "DIEP3TFSTAT,device IN endpoint 3 transmit FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space"
|
|
rgroup.long 0x198++0x3
|
|
line.long 0x0 "DIEP4TFSTAT,device IN endpoint 4 transmit FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space"
|
|
rgroup.long 0x1B8++0x3
|
|
line.long 0x0 "DIEP5TFSTAT,device IN endpoint 5 transmit FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space"
|
|
rgroup.long 0x1D8++0x3
|
|
line.long 0x0 "DIEP6TFSTAT,device IN endpoint 6 transmit FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space"
|
|
rgroup.long 0x1F8++0x3
|
|
line.long 0x0 "DIEP7TFSTAT,device IN endpoint 7 transmit FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space"
|
|
tree.end
|
|
tree "USBHS0_GLOBAL"
|
|
base ad:0x40040000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "GOTGCS,Global OTG control and status register"
|
|
bitfld.long 0x0 20. "OV,Select OTG version" "0,1"
|
|
rbitfld.long 0x0 19. "BSV,B-session valid" "0,1"
|
|
rbitfld.long 0x0 18. "ASV,A-session valid" "0,1"
|
|
rbitfld.long 0x0 17. "DI,Debounce interval" "0,1"
|
|
rbitfld.long 0x0 16. "IDPS,ID pin status" "0,1"
|
|
bitfld.long 0x0 12. "EHE,Embedded host enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1"
|
|
bitfld.long 0x0 10. "HHNPEN,Host HNP enable" "0,1"
|
|
bitfld.long 0x0 9. "HNPREQ,HNP request" "0,1"
|
|
rbitfld.long 0x0 8. "HNPS,HNP success" "0,1"
|
|
bitfld.long 0x0 7. "BVOV,Override value of B-peripheral session valid" "0,1"
|
|
bitfld.long 0x0 6. "BVOE,Override enable of B-peripheral session valid" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "AVOV,Override value of A-peripheral session valid" "0,1"
|
|
bitfld.long 0x0 4. "AVOE,Override enable of A-peripheral session valid" "0,1"
|
|
bitfld.long 0x0 3. "VOV,Override value of VBUS valid" "0,1"
|
|
bitfld.long 0x0 2. "VOE,Override enable of VBUS valid" "0,1"
|
|
bitfld.long 0x0 1. "SRPREQ,SRP request" "0,1"
|
|
rbitfld.long 0x0 0. "SRPS,SRP success" "0,1"
|
|
line.long 0x4 "GOTGINTF,Global OTG interrupt flag register"
|
|
bitfld.long 0x4 20. "IDCHG,There is a change in the value of ID input" "0,1"
|
|
bitfld.long 0x4 19. "DF,Debounce finish" "0,1"
|
|
bitfld.long 0x4 18. "ADTO,A-device timeout" "0,1"
|
|
bitfld.long 0x4 17. "HNPDET,Host negotiation request detected" "0,1"
|
|
bitfld.long 0x4 9. "HNPEND,HNP end" "0,1"
|
|
bitfld.long 0x4 8. "SRPEND,Session request success status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SESEND,Session end" "0,1"
|
|
line.long 0x8 "GAHBCS,Global AHB control and status register"
|
|
bitfld.long 0x8 8. "PTXFTH,Periodic Tx FIFO threshold" "0,1"
|
|
bitfld.long 0x8 7. "TXFTH,Tx FIFO threshold" "0,1"
|
|
bitfld.long 0x8 5. "DMAEN,DMA function Enable" "0,1"
|
|
hexmask.long.byte 0x8 1.--4. 1. "BURST,The AHB burst type used by DMA"
|
|
bitfld.long 0x8 0. "GINTEN,Global interrupt enable" "0,1"
|
|
line.long 0xC "GUSBCS,Global USB control and status register"
|
|
bitfld.long 0xC 30. "FDM,Force device mode" "0,1"
|
|
bitfld.long 0xC 29. "FHM,Force host mode" "0,1"
|
|
bitfld.long 0xC 21. "ULPIEOI,ULPI external over-current indicator" "0,1"
|
|
bitfld.long 0xC 20. "ULPIEVD,ULPI external VBUS driver" "0,1"
|
|
hexmask.long.byte 0xC 10.--13. 1. "UTT,USB turnaround time"
|
|
bitfld.long 0xC 9. "HNPCEN,HNP capability enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "SRPCEN,SRP capability enable" "0,1"
|
|
bitfld.long 0xC 6. "EMBPHY_FS,Embedded FS PHY selected" "0,1"
|
|
bitfld.long 0xC 5. "EMBPHY_HS,Embedded HS PHY selected" "0,1"
|
|
bitfld.long 0xC 4. "HS_EFT_FE,HS current software enable" "0,1"
|
|
bitfld.long 0xC 0.--2. "TOC,Timeout calibration" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "GRSTCTL,Global reset control register (USBHS_GRSTCTL)"
|
|
rbitfld.long 0x10 31. "DMAIDL,DMA Idle state" "0,1"
|
|
rbitfld.long 0x10 30. "DMABSY,DMA Busy" "0,1"
|
|
hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number"
|
|
bitfld.long 0x10 5. "TXFF,TxFIFO flush" "0,1"
|
|
bitfld.long 0x10 4. "RXFF,RxFIFO flush" "0,1"
|
|
bitfld.long 0x10 2. "HFCRST,Host frame counter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "HCSRST,HCLK soft reset" "0,1"
|
|
bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1"
|
|
line.long 0x14 "GINTF,Global interrupt flag register (USBFS_GINTF)"
|
|
bitfld.long 0x14 31. "WKUPIF,Wakeup interrupt flag" "0,1"
|
|
bitfld.long 0x14 30. "SESIF,Session interrupt flag" "0,1"
|
|
bitfld.long 0x14 29. "DISCIF,Disconnect interrupt flag" "0,1"
|
|
bitfld.long 0x14 28. "IDPSC,ID pin status change" "0,1"
|
|
bitfld.long 0x14 27. "LPMIF,LPM interrupt flag" "0,1"
|
|
rbitfld.long 0x14 26. "PTXFEIF,Periodic TxFIFO empty interrupt flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 25. "HCIF,Host channels interrupt flag" "0,1"
|
|
rbitfld.long 0x14 24. "HPIF,Host port interrupt flag" "0,1"
|
|
bitfld.long 0x14 21. "PXNCIF_ISOONCIF,periodic transfer not complete interrupt flag(Host" "0,1"
|
|
bitfld.long 0x14 20. "ISOINCIF,Isochronous IN transfer Not Complete Interrupt Flag" "0,1"
|
|
rbitfld.long 0x14 19. "OEPIF,OUT endpoint interrupt flag" "0,1"
|
|
rbitfld.long 0x14 18. "IEPIF,IN endpoint interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x14 15. "EOPFIF,End of periodic frame" "0,1"
|
|
bitfld.long 0x14 14. "ISOOPDIF,Isochronous OUT packet dropped" "0,1"
|
|
bitfld.long 0x14 13. "ENUMF,Enumeration finished" "0,1"
|
|
bitfld.long 0x14 12. "RST,USB reset" "0,1"
|
|
bitfld.long 0x14 11. "SP,USB suspend" "0,1"
|
|
bitfld.long 0x14 10. "ESP,Early suspend" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 7. "GONAK,Global OUT NAK effective" "0,1"
|
|
rbitfld.long 0x14 6. "GNPINAK,Global Non-Periodic IN NAK effective" "0,1"
|
|
rbitfld.long 0x14 5. "NPTXFEIF,Non-periodic TxFIFO empty interrupt flag" "0,1"
|
|
rbitfld.long 0x14 4. "RXFNEIF,RxFIFO non-empty interrupt flag" "0,1"
|
|
bitfld.long 0x14 3. "SOF,Start of frame" "0,1"
|
|
rbitfld.long 0x14 2. "OTGIF,OTG interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "MFIF,Mode fault interrupt flag" "0,1"
|
|
rbitfld.long 0x14 0. "COPM,Current operation mode" "0,1"
|
|
line.long 0x18 "GINTEN,Global interrupt enable register"
|
|
bitfld.long 0x18 31. "WKUPIE,Wakeup interrupt enable" "0,1"
|
|
bitfld.long 0x18 30. "SESIE,Session interrupt enable" "0,1"
|
|
bitfld.long 0x18 29. "DISCIE,Disconnect interrupt enable" "0,1"
|
|
bitfld.long 0x18 28. "IDPSCIE,ID pin status change interrupt enable" "0,1"
|
|
bitfld.long 0x18 27. "LPMIE,LPM interrupt enable" "0,1"
|
|
bitfld.long 0x18 26. "PTXFEIE,Periodic TxFIFO empty interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 25. "HCIE,Host channels interrupt enable" "0,1"
|
|
rbitfld.long 0x18 24. "HPIE,Host port interrupt enable" "0,1"
|
|
bitfld.long 0x18 21. "PXNCIE_ISOONCIE,periodic transfer not compelete Interrupt enable(Host" "0,1"
|
|
bitfld.long 0x18 20. "ISOINCIE,isochronous IN transfer not complete" "0,1"
|
|
bitfld.long 0x18 19. "OEPIE,OUT endpoints interrupt enable" "0,1"
|
|
bitfld.long 0x18 18. "IEPIE,IN endpoints interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 15. "EOPFIE,End of periodic frame interrupt enable" "0,1"
|
|
bitfld.long 0x18 14. "ISOOPDIE,Isochronous OUT packet dropped interrupt enable" "0,1"
|
|
bitfld.long 0x18 13. "ENUMFIE,Enumeration finish interrupt enable" "0,1"
|
|
bitfld.long 0x18 12. "RSTIE,USB reset interrupt enable" "0,1"
|
|
bitfld.long 0x18 11. "SPIE,USB suspend interrupt enable" "0,1"
|
|
bitfld.long 0x18 10. "ESPIE,Early suspend interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "GONAKIE,Global OUT NAK effective" "0,1"
|
|
bitfld.long 0x18 6. "GNPINAKIE,Global non-periodic IN NAK effective interrupt enable" "0,1"
|
|
bitfld.long 0x18 5. "NPTXFEIE,Non-periodic TxFIFO empty" "0,1"
|
|
bitfld.long 0x18 4. "RXFNEIE,Receive FIFO non-empty" "0,1"
|
|
bitfld.long 0x18 3. "SOFIE,Start of frame interrupt enable" "0,1"
|
|
bitfld.long 0x18 2. "OTGIE,OTG interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "MFIE,Mode fault interrupt" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "GRSTATR_Device,Global Receive status read(Device"
|
|
hexmask.long.byte 0x0 17.--20. 1. "RPCKST,Recieve packet status"
|
|
bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 4.--14. 1. "BCOUNT,Byte count"
|
|
hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number"
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x0 "GRSTATR_Host,Global Receive status read(Host"
|
|
hexmask.long.byte 0x0 17.--20. 1. "RPCKST,Reivece packet status"
|
|
bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 4.--14. 1. "BCOUNT,Byte count"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CNUM,Channel number"
|
|
line.long 0x4 "GRSTATP_Device,Global Receive status pop(Device"
|
|
hexmask.long.byte 0x4 17.--20. 1. "RPCKST,Recieve packet status"
|
|
bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x4 4.--14. 1. "BCOUNT,Byte count"
|
|
hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "GRSTATP_Host,Global Receive status pop(Host"
|
|
hexmask.long.byte 0x0 17.--20. 1. "RPCKST,Reivece packet status"
|
|
bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 4.--14. 1. "BCOUNT,Byte count"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CNUM,Channel number"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "GRFLEN,Global Receive FIFO size register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXFD,Rx FIFO depth"
|
|
line.long 0x4 "HNPTFLEN,Host non-periodic transmit FIFO length register"
|
|
hexmask.long.word 0x4 16.--31. 1. "HNPTXFD,host non-periodic TxFIFO depth"
|
|
hexmask.long.word 0x4 0.--15. 1. "HNPTXRSAR,host non-periodic transmit Tx RAM start"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "DIEP0TFLEN,Device IN endpoint 0 transmit FIFO length"
|
|
hexmask.long.word 0x0 16.--31. 1. "IEP0TXFD,in endpoint 0 Tx FIFO depth"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEP0TXRSAR,in endpoint 0 Tx RAM start address"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "HNPTFQSTAT,Host non-periodic transmit FIFO/queue"
|
|
hexmask.long.byte 0x0 24.--30. 1. "NPTXRQTOP,Top of the non-periodic transmit request"
|
|
hexmask.long.byte 0x0 16.--23. 1. "NPTXRQS,Non-periodic transmit request queue"
|
|
hexmask.long.word 0x0 0.--15. 1. "NPTXFS,Non-periodic TxFIFO space"
|
|
group.long 0x38++0x7
|
|
line.long 0x0 "GCCFG,Global core configuration register (USBFS_GCCFG)"
|
|
bitfld.long 0x0 21. "VDEN,Enable of VBUS sensing comparator to detect VBUS valid" "0,1"
|
|
bitfld.long 0x0 20. "SOFOEN,SOF output enable" "0,1"
|
|
bitfld.long 0x0 16. "PWRON,Power on" "0,1"
|
|
bitfld.long 0x0 15. "SDMEN,Secondary detection mode enable" "0,1"
|
|
bitfld.long 0x0 14. "PDMEN,Primary detection mode enable" "0,1"
|
|
bitfld.long 0x0 13. "DCDMEN,Data connect detection mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "BCDEN,Battery charging detection enable" "0,1"
|
|
bitfld.long 0x0 3. "PS2F,PS2 detection status" "0,1"
|
|
bitfld.long 0x0 2. "SDF,Secondary detection status" "0,1"
|
|
bitfld.long 0x0 1. "PDF,Primary detection status" "0,1"
|
|
bitfld.long 0x0 0. "DCDF,Data connect detection status" "0,1"
|
|
line.long 0x4 "CID,core ID register"
|
|
hexmask.long 0x4 0.--31. 1. "CID,Core ID"
|
|
group.long 0x54++0x7
|
|
line.long 0x0 "GLPMCFG,Global core LPM configuration register"
|
|
bitfld.long 0x0 28. "BESLEN,LPM Errata selection enable" "0,1"
|
|
bitfld.long 0x0 25.--27. "LPMRCS,LPM retry count status" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24. "LPMSND,Send LPM transaction" "0,1"
|
|
bitfld.long 0x0 21.--23. "LPMRC,LPM retry count" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 17.--20. 1. "LPMCHI,Channel number index when send LPM transaction"
|
|
bitfld.long 0x0 16. "RSOK,Resume can be sent after sleep state" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LPMSLPS,Sleep status" "0,1"
|
|
bitfld.long 0x0 13.--14. "LPMRSP,Response of LPM" "0,1,2,3"
|
|
bitfld.long 0x0 12. "DSEN,Deep sleep enable" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "BESLTH,BESL threshold"
|
|
bitfld.long 0x0 7. "SSEN,Shallow sleep enable" "0,1"
|
|
bitfld.long 0x0 6. "REW,RemoteWake value" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service latency"
|
|
bitfld.long 0x0 1. "ACKLPM,ACK in LPM transaction enable" "0,1"
|
|
bitfld.long 0x0 0. "LPMEN,LPM enable" "0,1"
|
|
line.long 0x4 "PWRD,Power down register (USBHS_PWRD)"
|
|
bitfld.long 0x4 23. "ADPF,ADP event interrupt flag" "0,1"
|
|
bitfld.long 0x4 0. "ADPMEN,ADP module enable" "0,1"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "ADPCTL,ADP control andstatus register"
|
|
bitfld.long 0x0 27.--28. "RWR,Read and write request" "0,1,2,3"
|
|
bitfld.long 0x0 26. "ADPTFM,The mask of ADP timeout interrupt flag" "0,1"
|
|
bitfld.long 0x0 25. "ADPSNFM,The mask of ADP sense interrupt flag" "0,1"
|
|
bitfld.long 0x0 24. "ADPPRFM,The mask of ADP probe interrupt flag" "0,1"
|
|
bitfld.long 0x0 23. "ADPTF,ADP timeout interrupt flag" "0,1"
|
|
bitfld.long 0x0 22. "ADPSNF,ADP sense interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "ADPPRF,ADP probe interrupt flag" "0,1"
|
|
bitfld.long 0x0 20. "ADPEN,ADP enable" "0,1"
|
|
rbitfld.long 0x0 19. "ADPRST,ADP reset" "0,1"
|
|
bitfld.long 0x0 18. "SNEN,ADP sense enable" "0,1"
|
|
bitfld.long 0x0 17. "PREN,ADP probe enable" "0,1"
|
|
hexmask.long.word 0x0 6.--16. 1. "CHGT,The latest time that VBUS ramps from VADPSINK to VADPPRB"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "PERPR,Period of probe" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "RESOPR,The resolution of CHGT value" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "DSCHGPR,Time of probe discharge" "0,1,2,3"
|
|
group.long 0x100++0x17
|
|
line.long 0x0 "HPTFLEN,Host periodic transmit FIFO length register (HPTFLEN)"
|
|
hexmask.long.word 0x0 16.--31. 1. "HPTXFD,Host periodic TxFIFO depth"
|
|
hexmask.long.word 0x0 0.--15. 1. "HPTXFSAR,Host periodic TxFIFO start"
|
|
line.long 0x4 "DIEP1TFLEN,device IN endpoint transmit FIFO size"
|
|
hexmask.long.word 0x4 16.--31. 1. "IEPTXFD,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x4 0.--15. 1. "IEPTXRSAR,IN endpoint FIFO transmit RAM start"
|
|
line.long 0x8 "DIEP2TFLEN,device IN endpoint transmit FIFO size"
|
|
hexmask.long.word 0x8 16.--31. 1. "IEPTXFD,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x8 0.--15. 1. "IEPTXRSAR,IN endpoint FIFO transmit RAM start"
|
|
line.long 0xC "DIEP3TFLEN,device IN endpoint transmit FIFO size"
|
|
hexmask.long.word 0xC 16.--31. 1. "IEPTXFD,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0xC 0.--15. 1. "IEPTXRSAR,IN endpoint FIFO4 transmit RAM start"
|
|
line.long 0x10 "DIEP4TFLEN,device IN endpoint transmit FIFO size"
|
|
hexmask.long.word 0x10 16.--31. 1. "IEPTXFD,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x10 0.--15. 1. "IEPTXRSAR,IN endpoint FIFO4 transmit RAM start"
|
|
line.long 0x14 "DIEP5TFLEN,device IN endpoint transmit FIFO size"
|
|
hexmask.long.word 0x14 16.--31. 1. "IEPTXFD,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x14 0.--15. 1. "IEPTXRSAR,IN endpoint FIFO4 transmit RAM start"
|
|
tree.end
|
|
tree "USBHS0_HOST"
|
|
base ad:0x40040400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "HCTL,host configuration register"
|
|
bitfld.long 0x0 2. "SPDFSLS,Speed limited to FS and LS" "0,1"
|
|
line.long 0x4 "HFT,Host frame interval"
|
|
hexmask.long.word 0x4 0.--15. 1. "FRI,Frame interval"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "HFINFR,OTG_FS host frame number/frame time"
|
|
hexmask.long.word 0x0 16.--31. 1. "FRT,Frame remaining time"
|
|
hexmask.long.word 0x0 0.--15. 1. "FRNUM,Frame number"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "HPTFQSTAT,Host periodic transmit FIFO/queue"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PTXREQT,Top of the periodic transmit request"
|
|
hexmask.long.byte 0x0 16.--23. 1. "PTXREQS,Periodic transmit request queue space"
|
|
hexmask.long.word 0x0 0.--15. 1. "PTXFS,Periodic transmit data FIFO space"
|
|
line.long 0x4 "HACHINT,Host all channels interrupt"
|
|
hexmask.long.word 0x4 0.--11. 1. "HACHINT,Host all channel interrupts"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "HACHINTEN,host all channels interrupt mask"
|
|
hexmask.long.word 0x0 0.--11. 1. "CINTEN,Channel interrupt enable"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "HPCS,Host port control and status register (USBFS_HPCS)"
|
|
rbitfld.long 0x0 17.--18. "PS,Port speed" "0,1,2,3"
|
|
hexmask.long.byte 0x0 13.--16. 1. "PTEST,Port Test control"
|
|
bitfld.long 0x0 12. "PP,Port power" "0,1"
|
|
rbitfld.long 0x0 10.--11. "PLST,Port line status" "0,1,2,3"
|
|
bitfld.long 0x0 8. "PRST,Port reset" "0,1"
|
|
bitfld.long 0x0 7. "PSP,Port suspend" "0,1"
|
|
bitfld.long 0x0 6. "PREM,Port resume" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PEDC,Port enable/disable change" "0,1"
|
|
bitfld.long 0x0 2. "PE,Port enable" "0,1"
|
|
bitfld.long 0x0 1. "PCD,Port connect detected" "0,1"
|
|
rbitfld.long 0x0 0. "PCST,Port connect status" "0,1"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "HCH0CTL,host channel-0 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "HCH1CTL,host channel-1 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "HCH2CTL,host channel-2 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "HCH3CTL,host channel-3 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "HCH4CTL,host channel-4 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x0 "HCH5CTL,host channel-5 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x1C0++0x3
|
|
line.long 0x0 "HCH6CTL,host channel-6 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x1E0++0x3
|
|
line.long 0x0 "HCH7CTL,host channel-7 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "HCH8CTL,host channel-8 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "HCH9CTL,host channel-9 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "HCH10CTL,host channel-10 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x260++0x3
|
|
line.long 0x0 "HCH11CTL,host channel-11 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "HCH12CTL,host channel-12 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "HCH13CTL,host channel-13 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x2C0++0x3
|
|
line.long 0x0 "HCH14CTL,host channel-14 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x2E0++0x3
|
|
line.long 0x0 "HCH15CTL,host channel-15 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x104++0x3
|
|
line.long 0x0 "HCH0STCTL,host channel-0 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x124++0x3
|
|
line.long 0x0 "HCH1STCTL,host channel-1 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x144++0x3
|
|
line.long 0x0 "HCH2STCTL,host channel-2 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x164++0x3
|
|
line.long 0x0 "HCH3STCTL,host channel-3 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x184++0x3
|
|
line.long 0x0 "HCH4STCTL,host channel-4 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x1A4++0x3
|
|
line.long 0x0 "HCH5STCTL,host channel-5 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x1C4++0x3
|
|
line.long 0x0 "HCH6STCTL,host channel-6 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x1E4++0x3
|
|
line.long 0x0 "HCH7STCTL,host channel-7 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "HCH8STCTL,host channel-8 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x224++0x3
|
|
line.long 0x0 "HCH9STCTL,host channel-9 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x244++0x3
|
|
line.long 0x0 "HCH10STCTL,host channel-10 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x264++0x3
|
|
line.long 0x0 "HCH11STCTL,host channel-11 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x284++0x3
|
|
line.long 0x0 "HCH12STCTL,host channel-12 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x2A4++0x3
|
|
line.long 0x0 "HCH13STCTL,host channel-13 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x2C4++0x3
|
|
line.long 0x0 "HCH14STCTL,host channel-14 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "HCH15STCTL,host channel-15 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "HCH0INTF,host channel-0 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "HCH1INTF,host channel-1 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x148++0x3
|
|
line.long 0x0 "HCH2INTF,host channel-2 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x168++0x3
|
|
line.long 0x0 "HCH3INTF,host channel-3 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x188++0x3
|
|
line.long 0x0 "HCH4INTF,host channel-4 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x1A8++0x3
|
|
line.long 0x0 "HCH5INTF,host channel-5 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x1C8++0x3
|
|
line.long 0x0 "HCH6INTF,host channel-6 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x1E8++0x3
|
|
line.long 0x0 "HCH7INTF,host channel-7 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x208++0x3
|
|
line.long 0x0 "HCH8INTF,host channel-8 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x228++0x3
|
|
line.long 0x0 "HCH9INTF,host channel-9 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x248++0x3
|
|
line.long 0x0 "HCH10INTF,host channel-10 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x268++0x3
|
|
line.long 0x0 "HCH11INTF,host channel-11 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x288++0x3
|
|
line.long 0x0 "HCH12INTF,host channel-12 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x2A8++0x3
|
|
line.long 0x0 "HCH13INTF,host channel-13 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x2C8++0x3
|
|
line.long 0x0 "HCH14INTF,host channel-14 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x2E8++0x3
|
|
line.long 0x0 "HCH15INTF,host channel-15 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x10C++0x3
|
|
line.long 0x0 "HCH0INTEN,host channel-0 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x12C++0x3
|
|
line.long 0x0 "HCH1INTEN,host channel-1 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x14C++0x3
|
|
line.long 0x0 "HCH2INTEN,host channel-2 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x16C++0x3
|
|
line.long 0x0 "HCH3INTEN,host channel-3 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x18C++0x3
|
|
line.long 0x0 "HCH4INTEN,host channel-4 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x1AC++0x3
|
|
line.long 0x0 "HCH5INTEN,host channel-5 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x1CC++0x3
|
|
line.long 0x0 "HCH6INTEN,host channel-6 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x1EC++0x3
|
|
line.long 0x0 "HCH7INTEN,host channel-7 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x20C++0x3
|
|
line.long 0x0 "HCH8INTEN,host channel-8 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x22C++0x3
|
|
line.long 0x0 "HCH9INTEN,host channel-9 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x24C++0x3
|
|
line.long 0x0 "HCH10INTEN,host channel-10 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x26C++0x3
|
|
line.long 0x0 "HCH11INTEN,host channel-11 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x28C++0x3
|
|
line.long 0x0 "HCH12INTEN,host channel-12 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x2AC++0x3
|
|
line.long 0x0 "HCH13INTEN,host channel-13 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x2CC++0x3
|
|
line.long 0x0 "HCH14INTEN,host channel-14 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x2EC++0x3
|
|
line.long 0x0 "HCH15INTEN,host channel-15 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "HCH0LEN,host channel-0 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "HCH1LEN,host channel-1 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x150++0x3
|
|
line.long 0x0 "HCH2LEN,host channel-2 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x170++0x3
|
|
line.long 0x0 "HCH3LEN,host channel-3 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x190++0x3
|
|
line.long 0x0 "HCH4LEN,host channel-4 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x1B0++0x3
|
|
line.long 0x0 "HCH5LEN,host channel-5 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x1D0++0x3
|
|
line.long 0x0 "HCH6LEN,host channel-6 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x1F0++0x3
|
|
line.long 0x0 "HCH7LEN,host channel-7 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x210++0x3
|
|
line.long 0x0 "HCH8LEN,host channel-8 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x230++0x3
|
|
line.long 0x0 "HCH9LEN,host channel-9 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x250++0x3
|
|
line.long 0x0 "HCH10LEN,host channel-10 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x270++0x3
|
|
line.long 0x0 "HCH11LEN,host channel-11 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "HCH12LEN,host channel-12 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x2B0++0x3
|
|
line.long 0x0 "HCH13LEN,host channel-13 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x2D0++0x3
|
|
line.long 0x0 "HCH14LEN,host channel-14 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x2F0++0x3
|
|
line.long 0x0 "HCH15LEN,host channel-15 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x114++0x3
|
|
line.long 0x0 "HCH0DMAADDR,Host channel 0 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x134++0x3
|
|
line.long 0x0 "HCH1DMAADDR,Host channel 1 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x154++0x3
|
|
line.long 0x0 "HCH2DMAADDR,Host channel 2 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x174++0x3
|
|
line.long 0x0 "HCH3DMAADDR,Host channel 3 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x194++0x3
|
|
line.long 0x0 "HCH4DMAADDR,Host channel 4 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x1B4++0x3
|
|
line.long 0x0 "HCH5DMAADDR,Host channel 5 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x1D4++0x3
|
|
line.long 0x0 "HCH6DMAADDR,Host channel 6 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x1F4++0x3
|
|
line.long 0x0 "HCH7DMAADDR,Host channel 7 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x214++0x3
|
|
line.long 0x0 "HCH8DMAADDR,Host channel 8 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x234++0x3
|
|
line.long 0x0 "HCH9DMAADDR,Host channel 9 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x254++0x3
|
|
line.long 0x0 "HCH10DMAADDR,Host channel 10 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x274++0x3
|
|
line.long 0x0 "HCH11DMAADDR,Host channel 11 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x294++0x3
|
|
line.long 0x0 "HCH12DMAADDR,Host channel 12 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x2B4++0x3
|
|
line.long 0x0 "HCH13DMAADDR,Host channel 13 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x2D4++0x3
|
|
line.long 0x0 "HCH14DMAADDR,Host channel 14 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x2F4++0x3
|
|
line.long 0x0 "HCH15DMAADDR,Host channel 15 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
tree.end
|
|
tree "USBHS0_PWRCLK"
|
|
base ad:0x40040E00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PWRCLKCTL,power and clock gating control"
|
|
rbitfld.long 0x0 7. "DSLEEP,PHY is in deep sleep status" "0,1"
|
|
rbitfld.long 0x0 6. "SSLEEP,PHY is in shallow sleep status" "0,1"
|
|
rbitfld.long 0x0 5. "SCGEN,internal clock gating enable" "0,1"
|
|
rbitfld.long 0x0 4. "SUSP,PHY is in suspend status" "0,1"
|
|
bitfld.long 0x0 1. "SHCLK,Stop HCLK" "0,1"
|
|
bitfld.long 0x0 0. "SUCLK,Stop the USB clock" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "USBHS1"
|
|
tree "USBHS1_DEVICE"
|
|
base ad:0x40080800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DCFG,device configuration register"
|
|
bitfld.long 0x0 11.--12. "EOPFT,end of periodic frame time" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--10. 1. "DAR,Device address"
|
|
bitfld.long 0x0 2. "NZLSOH,Non-zero-length status OUT" "0,1"
|
|
bitfld.long 0x0 0.--1. "DS,Device speed" "0,1,2,3"
|
|
line.long 0x4 "DCTL,device control register"
|
|
bitfld.long 0x4 18. "L1RJCT,Deep sleep reject" "0,1"
|
|
bitfld.long 0x4 11. "POIF,Power-on initialization flag" "0,1"
|
|
bitfld.long 0x4 10. "CGONAK,Clear global OUT NAK" "0,1"
|
|
bitfld.long 0x4 9. "SGONAK,Set global OUT NAK" "0,1"
|
|
bitfld.long 0x4 8. "CGINAK,Clear global IN NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "SGINAK,Set global IN NAK" "0,1"
|
|
bitfld.long 0x4 4.--6. "DTEST,Device Test control" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x4 3. "GONS,Global OUT NAK status" "0,1"
|
|
rbitfld.long 0x4 2. "GINS,Global IN NAK status" "0,1"
|
|
bitfld.long 0x4 1. "SD,Soft disconnect" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RWKUP,Remote wakeup" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "DSTAT,device status register"
|
|
hexmask.long.word 0x0 8.--21. 1. "FNRSOF,Frame number of the received"
|
|
bitfld.long 0x0 1.--2. "ES,Enumerated speed" "0,1,2,3"
|
|
bitfld.long 0x0 0. "SPST,Suspend status" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "DIEPINTEN,device IN endpoint common interrupt"
|
|
bitfld.long 0x0 13. "NAKEN,NAK handshake sent by USBHS interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 6. "IEPNEEN,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUDEN,Endpoint Tx FIFO underrun interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 3. "CITOEN,Control IN timeout condition interrupt enable (Non-isochronous" "0,1"
|
|
bitfld.long 0x0 1. "EPDISEN,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TFEN,Transfer finished interrupt" "0,1"
|
|
line.long 0x4 "DOEPINTEN,device OUT endpoint common interrupt"
|
|
bitfld.long 0x4 14. "NYETEN,Send NYET handshake interrupt enable bit" "0,1"
|
|
bitfld.long 0x4 6. "BTBSTPEN,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x4 4. "EPRXFOVREN,Endpoint Rx FIFO overrun interrupt enable" "0,1"
|
|
bitfld.long 0x4 3. "STPFEN,SETUP phase finished interrupt enable" "0,1"
|
|
bitfld.long 0x4 1. "EPDISEN,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TFEN,Transfer finished interrupt" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "DAEPINT,device all endpoints interrupt"
|
|
hexmask.long.byte 0x0 16.--21. 1. "OEPITB,Device all OUT endpoint interrupt bits"
|
|
hexmask.long.byte 0x0 0.--5. 1. "IEPITB,Device all IN endpoint interrupt bits"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "DAEPINTEN,Device all endpoints interrupt enable register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "OEPIE,OUT endpoint interrupt enable bits"
|
|
hexmask.long.byte 0x0 0.--5. 1. "IEPIE,IN EP interrupt interrupt enable bits"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "DVBUSDT,device VBUS discharge time"
|
|
hexmask.long.word 0x0 0.--15. 1. "DVBUSDT,Device VBUS discharge time"
|
|
line.long 0x4 "DVBUSPT,device VBUS pulsing time"
|
|
hexmask.long.word 0x4 0.--11. 1. "DVBUSPT,Device VBUS pulsing time"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "DIEPFEINTEN,device IN endpoint FIFO empty"
|
|
hexmask.long.byte 0x0 0.--5. 1. "IEPTXFEIE,IN EP Tx FIFO empty interrupt enable"
|
|
rgroup.long 0x38++0x7
|
|
line.long 0x0 "DEP1INT,Device endpoint 1 interrupt register"
|
|
bitfld.long 0x0 17. "OEP1INT,OUT Endpoint 1 interrupt" "0,1"
|
|
bitfld.long 0x0 1. "IEP1INT,IN Endpoint 1 interrupt" "0,1"
|
|
line.long 0x4 "DEP1INTEN,Device endpoint 1 interrupt register"
|
|
bitfld.long 0x4 17. "OEP1INTEN,OUT Endpoint 1 interrupt enable" "0,1"
|
|
bitfld.long 0x4 1. "IEP1INTEN,IN Endpoint 1 interrupt enable" "0,1"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "DIEP1INTEN,Device IN endpoint 1 interrupt enable register"
|
|
bitfld.long 0x0 13. "NAKEN,Interrupt enable bit of NAK handshake sent by USBHS" "0,1"
|
|
bitfld.long 0x0 6. "IEPNEEN,IN endpoint NAK effective interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUDEN,Endpoint Tx FIFO underrun interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 3. "CITOEN,Control In Timeout interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 1. "EPDISEN,Endpoint disabled interrupt enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TFEN,Transfer finished interrupt enable bit" "0,1"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "DOEP1INTEN,Device OUT endpoint 1 interrupt enable register"
|
|
bitfld.long 0x0 13. "NYETEN,Send NYET handshake interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTPEN,Back-to-back SETUP packets interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVREN,Endpoint Rx FIFO over run interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 3. "STPFEN,SETUP phase finished interrupt enable bit" "0,1"
|
|
bitfld.long 0x0 1. "EPDISEN,Endpoint disabled interrupt enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TFEN,Transfer finished interrupt enable bit" "0,1"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "DIEP0CTL,device IN endpoint 0 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
rbitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
rbitfld.long 0x0 15. "EPACT,endpoint active" "0,1"
|
|
bitfld.long 0x0 0.--1. "MPL,Maximum packet length" "0,1,2,3"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "DIEP1CTL,device in endpoint-1 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "DIEP2CTL,device endpoint-2 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "DIEP3CTL,device endpoint-3 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "DIEP4CTL,device endpoint-4 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x0 "DIEP5CTL,device endpoint-5 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x1C0++0x3
|
|
line.long 0x0 "DIEP6CTL,device endpoint-6 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x1E0++0x3
|
|
line.long 0x0 "DIEP7CTL,device endpoint-7 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x300++0x3
|
|
line.long 0x0 "DOEP0CTL,device endpoint-0 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
rbitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SNOOP,Snoop mode" "0,1"
|
|
rbitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
rbitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
rbitfld.long 0x0 0.--1. "MPL,Maximum packet length" "0,1,2,3"
|
|
group.long 0x320++0x3
|
|
line.long 0x0 "DOEP1CTL,device endpoint-1 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNOOP,Snoop mode" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x340++0x3
|
|
line.long 0x0 "DOEP2CTL,device endpoint-2 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNOOP,Snoop mode" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x360++0x3
|
|
line.long 0x0 "DOEP3CTL,device endpoint-3 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNOOP,Snoop mode" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x380++0x3
|
|
line.long 0x0 "DOEP4CTL,device endpoint-4 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNOOP,Snoop mode" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x3A0++0x3
|
|
line.long 0x0 "DOEP5CTL,device endpoint-5 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNOOP,Snoop mode" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x3C0++0x3
|
|
line.long 0x0 "DOEP6CTL,device endpoint-6 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNOOP,Snoop mode" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x3E0++0x3
|
|
line.long 0x0 "DOEP7CTL,device endpoint-7 control"
|
|
bitfld.long 0x0 31. "EPEN,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPD,Endpoint disable" "0,1"
|
|
bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNOOP,Snoop mode" "0,1"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKS,NAK status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
|
|
bitfld.long 0x0 15. "EPACT,Endpoint active" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,maximum packet length"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "DIEP0INTF,device endpoint-0 interrupt"
|
|
bitfld.long 0x0 13. "NAK,NAK handshake sent by USBHS" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x0 6. "IEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
|
|
bitfld.long 0x0 3. "CITO,Control in timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint finished" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "DIEP1INTF,device endpoint-1 interrupt"
|
|
bitfld.long 0x0 13. "NAK,NAK handshake sent by USBHS" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x0 6. "IEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
|
|
bitfld.long 0x0 3. "CITO,Control in timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint finished" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x148++0x3
|
|
line.long 0x0 "DIEP2INTF,device endpoint-2 interrupt"
|
|
bitfld.long 0x0 13. "NAK,NAK handshake sent by USBHS" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x0 6. "IEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
|
|
bitfld.long 0x0 3. "CITO,Control in timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint finished" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x168++0x3
|
|
line.long 0x0 "DIEP3INTF,device endpoint-3 interrupt"
|
|
bitfld.long 0x0 13. "NAK,NAK handshake sent by USBHS" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x0 6. "IEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
|
|
bitfld.long 0x0 3. "CITO,Control in timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint finished" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x188++0x3
|
|
line.long 0x0 "DIEP4INTF,device endpoint-4 interrupt"
|
|
bitfld.long 0x0 13. "NAK,NAK handshake sent by USBHS" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x0 6. "IEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
|
|
bitfld.long 0x0 3. "CITO,Control in timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint finished" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x1A8++0x3
|
|
line.long 0x0 "DIEP5INTF,device endpoint-5 interrupt"
|
|
bitfld.long 0x0 13. "NAK,NAK handshake sent by USBHS" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x0 6. "IEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
|
|
bitfld.long 0x0 3. "CITO,Control in timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint finished" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x1C8++0x3
|
|
line.long 0x0 "DIEP6INTF,device endpoint-6 interrupt"
|
|
bitfld.long 0x0 13. "NAK,NAK handshake sent by USBHS" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x0 6. "IEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
|
|
bitfld.long 0x0 3. "CITO,Control in timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint finished" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x1E8++0x3
|
|
line.long 0x0 "DIEP7INTF,device endpoint-7 interrupt"
|
|
bitfld.long 0x0 13. "NAK,NAK handshake sent by USBHS" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x0 6. "IEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
|
|
bitfld.long 0x0 3. "CITO,Control in timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint finished" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "DOEP0INTF,device out endpoint-0 interrupt flag"
|
|
bitfld.long 0x0 14. "NYET,NYET handshake is sent" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
|
|
bitfld.long 0x0 3. "STPF,Setup phase finished" "0,1"
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x328++0x3
|
|
line.long 0x0 "DOEP1INTF,device out endpoint-1 interrupt flag"
|
|
bitfld.long 0x0 14. "NYET,NYET handshake is sent" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
|
|
bitfld.long 0x0 3. "STPF,Setup phase finished" "0,1"
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x348++0x3
|
|
line.long 0x0 "DOEP2INTF,device out endpoint-2 interrupt flag"
|
|
bitfld.long 0x0 14. "NYET,NYET handshake is sent" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
|
|
bitfld.long 0x0 3. "STPF,Setup phase finished" "0,1"
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x368++0x3
|
|
line.long 0x0 "DOEP3INTF,device out endpoint-3 interrupt flag"
|
|
bitfld.long 0x0 14. "NYET,NYET handshake is sent" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
|
|
bitfld.long 0x0 3. "STPF,Setup phase finished" "0,1"
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x388++0x3
|
|
line.long 0x0 "DOEP4INTF,device out endpoint-4 interrupt flag"
|
|
bitfld.long 0x0 14. "NYET,NYET handshake is sent" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
|
|
bitfld.long 0x0 3. "STPF,Setup phase finished" "0,1"
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x3A8++0x3
|
|
line.long 0x0 "DOEP5INTF,device out endpoint-5 interrupt flag"
|
|
bitfld.long 0x0 14. "NYET,NYET handshake is sent" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
|
|
bitfld.long 0x0 3. "STPF,Setup phase finished" "0,1"
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x3C8++0x3
|
|
line.long 0x0 "DOEP6INTF,device out endpoint-6 interrupt flag"
|
|
bitfld.long 0x0 14. "NYET,NYET handshake is sent" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
|
|
bitfld.long 0x0 3. "STPF,Setup phase finished" "0,1"
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x3E8++0x3
|
|
line.long 0x0 "DOEP7INTF,device out endpoint-7 interrupt flag"
|
|
bitfld.long 0x0 14. "NYET,NYET handshake is sent" "0,1"
|
|
bitfld.long 0x0 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
|
|
bitfld.long 0x0 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
|
|
bitfld.long 0x0 3. "STPF,Setup phase finished" "0,1"
|
|
bitfld.long 0x0 1. "EPDIS,Endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "DIEP0LEN,device IN endpoint-0 transfer length"
|
|
bitfld.long 0x0 19.--20. "PCNT,Packet count" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TLEN,Transfer length"
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "DOEP0LEN,device OUT endpoint-0 transfer length"
|
|
bitfld.long 0x0 29.--30. "STPCNT,SETUP packet count" "0,1,2,3"
|
|
bitfld.long 0x0 19. "PCNT,Packet count" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TLEN,Transfer length"
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "DIEP1LEN,device IN endpoint-1 transfer length"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x150++0x3
|
|
line.long 0x0 "DIEP2LEN,device IN endpoint-2 transfer length"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x170++0x3
|
|
line.long 0x0 "DIEP3LEN,device IN endpoint-3 transfer length"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x190++0x3
|
|
line.long 0x0 "DIEP4LEN,device IN endpoint-4 transfer length"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x1B0++0x3
|
|
line.long 0x0 "DIEP5LEN,device IN endpoint-5 transfer length"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x1D0++0x3
|
|
line.long 0x0 "DIEP6LEN,device IN endpoint-6 transfer length"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x1F0++0x3
|
|
line.long 0x0 "DIEP7LEN,device IN endpoint-7 transfer length"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x330++0x3
|
|
line.long 0x0 "DOEP1LEN,device OUT endpoint-1 transfer length"
|
|
bitfld.long 0x0 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x350++0x3
|
|
line.long 0x0 "DOEP2LEN,device OUT endpoint-2 transfer length"
|
|
bitfld.long 0x0 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x370++0x3
|
|
line.long 0x0 "DOEP3LEN,device OUT endpoint-3 transfer length"
|
|
bitfld.long 0x0 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x390++0x3
|
|
line.long 0x0 "DOEP4LEN,device OUT endpoint-4 transfer length"
|
|
bitfld.long 0x0 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x3B0++0x3
|
|
line.long 0x0 "DOEP5LEN,device OUT endpoint-5 transfer length"
|
|
bitfld.long 0x0 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x3D0++0x3
|
|
line.long 0x0 "DOEP6LEN,device OUT endpoint-6 transfer length"
|
|
bitfld.long 0x0 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x3F0++0x3
|
|
line.long 0x0 "DOEP7LEN,device OUT endpoint-7 transfer length"
|
|
bitfld.long 0x0 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x114++0x3
|
|
line.long 0x0 "DIEP0DMAADDR,Device IN endpoint 0 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x134++0x3
|
|
line.long 0x0 "DIEP1DMAADDR,Device IN endpoint 1 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x154++0x3
|
|
line.long 0x0 "DIEP2DMAADDR,Device IN endpoint 2 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x174++0x3
|
|
line.long 0x0 "DIEP3DMAADDR,Device IN endpoint 3 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x194++0x3
|
|
line.long 0x0 "DIEP4DMAADDR,Device IN endpoint 4 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x1B4++0x3
|
|
line.long 0x0 "DIEP5DMAADDR,Device IN endpoint 5 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x1D4++0x3
|
|
line.long 0x0 "DIEP6DMAADDR,Device IN endpoint 6 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x1F4++0x3
|
|
line.long 0x0 "DIEP7DMAADDR,Device IN endpoint 7 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x314++0x3
|
|
line.long 0x0 "DOEP0DMAADDR,Device OUT endpoint 0 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x334++0x3
|
|
line.long 0x0 "DOEP1DMAADDR,Device OUT endpoint 1 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x354++0x3
|
|
line.long 0x0 "DOEP2DMAADDR,Device OUT endpoint 2 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x374++0x3
|
|
line.long 0x0 "DOEP3DMAADDR,Device OUT endpoint 3 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x394++0x3
|
|
line.long 0x0 "DOEP4DMAADDR,Device OUT endpoint 4 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x3B4++0x3
|
|
line.long 0x0 "DOEP5DMAADDR,Device OUT endpoint 5 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x3D4++0x3
|
|
line.long 0x0 "DOEP6DMAADDR,Device OUT endpoint 6 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x3F4++0x3
|
|
line.long 0x0 "DOEP7DMAADDR,Device OUT endpoint 7 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
rgroup.long 0x118++0x3
|
|
line.long 0x0 "DIEP0TFSTAT,device IN endpoint 0 transmit FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space"
|
|
rgroup.long 0x138++0x3
|
|
line.long 0x0 "DIEP1TFSTAT,device IN endpoint 1 transmit FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space"
|
|
rgroup.long 0x158++0x3
|
|
line.long 0x0 "DIEP2TFSTAT,device IN endpoint 2 transmit FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space"
|
|
rgroup.long 0x178++0x3
|
|
line.long 0x0 "DIEP3TFSTAT,device IN endpoint 3 transmit FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space"
|
|
rgroup.long 0x198++0x3
|
|
line.long 0x0 "DIEP4TFSTAT,device IN endpoint 4 transmit FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space"
|
|
rgroup.long 0x1B8++0x3
|
|
line.long 0x0 "DIEP5TFSTAT,device IN endpoint 5 transmit FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space"
|
|
rgroup.long 0x1D8++0x3
|
|
line.long 0x0 "DIEP6TFSTAT,device IN endpoint 6 transmit FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space"
|
|
rgroup.long 0x1F8++0x3
|
|
line.long 0x0 "DIEP7TFSTAT,device IN endpoint 7 transmit FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space"
|
|
tree.end
|
|
tree "USBHS1_GLOBAL"
|
|
base ad:0x40080000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "GOTGCS,Global OTG control and status register"
|
|
bitfld.long 0x0 20. "OV,Select OTG version" "0,1"
|
|
rbitfld.long 0x0 19. "BSV,B-session valid" "0,1"
|
|
rbitfld.long 0x0 18. "ASV,A-session valid" "0,1"
|
|
rbitfld.long 0x0 17. "DI,Debounce interval" "0,1"
|
|
rbitfld.long 0x0 16. "IDPS,ID pin status" "0,1"
|
|
bitfld.long 0x0 12. "EHE,Embedded host enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1"
|
|
bitfld.long 0x0 10. "HHNPEN,Host HNP enable" "0,1"
|
|
bitfld.long 0x0 9. "HNPREQ,HNP request" "0,1"
|
|
rbitfld.long 0x0 8. "HNPS,HNP success" "0,1"
|
|
bitfld.long 0x0 7. "BVOV,Override value of B-peripheral session valid" "0,1"
|
|
bitfld.long 0x0 6. "BVOE,Override enable of B-peripheral session valid" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "AVOV,Override value of A-peripheral session valid" "0,1"
|
|
bitfld.long 0x0 4. "AVOE,Override enable of A-peripheral session valid" "0,1"
|
|
bitfld.long 0x0 3. "VOV,Override value of VBUS valid" "0,1"
|
|
bitfld.long 0x0 2. "VOE,Override enable of VBUS valid" "0,1"
|
|
bitfld.long 0x0 1. "SRPREQ,SRP request" "0,1"
|
|
rbitfld.long 0x0 0. "SRPS,SRP success" "0,1"
|
|
line.long 0x4 "GOTGINTF,Global OTG interrupt flag register"
|
|
bitfld.long 0x4 20. "IDCHG,There is a change in the value of ID input" "0,1"
|
|
bitfld.long 0x4 19. "DF,Debounce finish" "0,1"
|
|
bitfld.long 0x4 18. "ADTO,A-device timeout" "0,1"
|
|
bitfld.long 0x4 17. "HNPDET,Host negotiation request detected" "0,1"
|
|
bitfld.long 0x4 9. "HNPEND,HNP end" "0,1"
|
|
bitfld.long 0x4 8. "SRPEND,Session request success status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SESEND,Session end" "0,1"
|
|
line.long 0x8 "GAHBCS,Global AHB control and status register"
|
|
bitfld.long 0x8 8. "PTXFTH,Periodic Tx FIFO threshold" "0,1"
|
|
bitfld.long 0x8 7. "TXFTH,Tx FIFO threshold" "0,1"
|
|
bitfld.long 0x8 5. "DMAEN,DMA function Enable" "0,1"
|
|
hexmask.long.byte 0x8 1.--4. 1. "BURST,The AHB burst type used by DMA"
|
|
bitfld.long 0x8 0. "GINTEN,Global interrupt enable" "0,1"
|
|
line.long 0xC "GUSBCS,Global USB control and status register"
|
|
bitfld.long 0xC 30. "FDM,Force device mode" "0,1"
|
|
bitfld.long 0xC 29. "FHM,Force host mode" "0,1"
|
|
bitfld.long 0xC 21. "ULPIEOI,ULPI external over-current indicator" "0,1"
|
|
bitfld.long 0xC 20. "ULPIEVD,ULPI external VBUS driver" "0,1"
|
|
hexmask.long.byte 0xC 10.--13. 1. "UTT,USB turnaround time"
|
|
bitfld.long 0xC 9. "HNPCEN,HNP capability enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "SRPCEN,SRP capability enable" "0,1"
|
|
bitfld.long 0xC 6. "EMBPHY_FS,Embedded FS PHY selected" "0,1"
|
|
bitfld.long 0xC 5. "EMBPHY_HS,Embedded HS PHY selected" "0,1"
|
|
bitfld.long 0xC 4. "HS_EFT_FE,HS current software enable" "0,1"
|
|
bitfld.long 0xC 0.--2. "TOC,Timeout calibration" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "GRSTCTL,Global reset control register (USBHS_GRSTCTL)"
|
|
rbitfld.long 0x10 31. "DMAIDL,DMA Idle state" "0,1"
|
|
rbitfld.long 0x10 30. "DMABSY,DMA Busy" "0,1"
|
|
hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number"
|
|
bitfld.long 0x10 5. "TXFF,TxFIFO flush" "0,1"
|
|
bitfld.long 0x10 4. "RXFF,RxFIFO flush" "0,1"
|
|
bitfld.long 0x10 2. "HFCRST,Host frame counter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "HCSRST,HCLK soft reset" "0,1"
|
|
bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1"
|
|
line.long 0x14 "GINTF,Global interrupt flag register (USBFS_GINTF)"
|
|
bitfld.long 0x14 31. "WKUPIF,Wakeup interrupt flag" "0,1"
|
|
bitfld.long 0x14 30. "SESIF,Session interrupt flag" "0,1"
|
|
bitfld.long 0x14 29. "DISCIF,Disconnect interrupt flag" "0,1"
|
|
bitfld.long 0x14 28. "IDPSC,ID pin status change" "0,1"
|
|
bitfld.long 0x14 27. "LPMIF,LPM interrupt flag" "0,1"
|
|
rbitfld.long 0x14 26. "PTXFEIF,Periodic TxFIFO empty interrupt flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 25. "HCIF,Host channels interrupt flag" "0,1"
|
|
rbitfld.long 0x14 24. "HPIF,Host port interrupt flag" "0,1"
|
|
bitfld.long 0x14 21. "PXNCIF_ISOONCIF,periodic transfer not complete interrupt flag(Host" "0,1"
|
|
bitfld.long 0x14 20. "ISOINCIF,Isochronous IN transfer Not Complete Interrupt Flag" "0,1"
|
|
rbitfld.long 0x14 19. "OEPIF,OUT endpoint interrupt flag" "0,1"
|
|
rbitfld.long 0x14 18. "IEPIF,IN endpoint interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x14 15. "EOPFIF,End of periodic frame" "0,1"
|
|
bitfld.long 0x14 14. "ISOOPDIF,Isochronous OUT packet dropped" "0,1"
|
|
bitfld.long 0x14 13. "ENUMF,Enumeration finished" "0,1"
|
|
bitfld.long 0x14 12. "RST,USB reset" "0,1"
|
|
bitfld.long 0x14 11. "SP,USB suspend" "0,1"
|
|
bitfld.long 0x14 10. "ESP,Early suspend" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 7. "GONAK,Global OUT NAK effective" "0,1"
|
|
rbitfld.long 0x14 6. "GNPINAK,Global Non-Periodic IN NAK effective" "0,1"
|
|
rbitfld.long 0x14 5. "NPTXFEIF,Non-periodic TxFIFO empty interrupt flag" "0,1"
|
|
rbitfld.long 0x14 4. "RXFNEIF,RxFIFO non-empty interrupt flag" "0,1"
|
|
bitfld.long 0x14 3. "SOF,Start of frame" "0,1"
|
|
rbitfld.long 0x14 2. "OTGIF,OTG interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "MFIF,Mode fault interrupt flag" "0,1"
|
|
rbitfld.long 0x14 0. "COPM,Current operation mode" "0,1"
|
|
line.long 0x18 "GINTEN,Global interrupt enable register"
|
|
bitfld.long 0x18 31. "WKUPIE,Wakeup interrupt enable" "0,1"
|
|
bitfld.long 0x18 30. "SESIE,Session interrupt enable" "0,1"
|
|
bitfld.long 0x18 29. "DISCIE,Disconnect interrupt enable" "0,1"
|
|
bitfld.long 0x18 28. "IDPSCIE,ID pin status change interrupt enable" "0,1"
|
|
bitfld.long 0x18 27. "LPMIE,LPM interrupt enable" "0,1"
|
|
bitfld.long 0x18 26. "PTXFEIE,Periodic TxFIFO empty interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 25. "HCIE,Host channels interrupt enable" "0,1"
|
|
rbitfld.long 0x18 24. "HPIE,Host port interrupt enable" "0,1"
|
|
bitfld.long 0x18 21. "PXNCIE_ISOONCIE,periodic transfer not compelete Interrupt enable(Host" "0,1"
|
|
bitfld.long 0x18 20. "ISOINCIE,isochronous IN transfer not complete" "0,1"
|
|
bitfld.long 0x18 19. "OEPIE,OUT endpoints interrupt enable" "0,1"
|
|
bitfld.long 0x18 18. "IEPIE,IN endpoints interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 15. "EOPFIE,End of periodic frame interrupt enable" "0,1"
|
|
bitfld.long 0x18 14. "ISOOPDIE,Isochronous OUT packet dropped interrupt enable" "0,1"
|
|
bitfld.long 0x18 13. "ENUMFIE,Enumeration finish interrupt enable" "0,1"
|
|
bitfld.long 0x18 12. "RSTIE,USB reset interrupt enable" "0,1"
|
|
bitfld.long 0x18 11. "SPIE,USB suspend interrupt enable" "0,1"
|
|
bitfld.long 0x18 10. "ESPIE,Early suspend interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "GONAKIE,Global OUT NAK effective" "0,1"
|
|
bitfld.long 0x18 6. "GNPINAKIE,Global non-periodic IN NAK effective interrupt enable" "0,1"
|
|
bitfld.long 0x18 5. "NPTXFEIE,Non-periodic TxFIFO empty" "0,1"
|
|
bitfld.long 0x18 4. "RXFNEIE,Receive FIFO non-empty" "0,1"
|
|
bitfld.long 0x18 3. "SOFIE,Start of frame interrupt enable" "0,1"
|
|
bitfld.long 0x18 2. "OTGIE,OTG interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "MFIE,Mode fault interrupt" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "GRSTATR_Device,Global Receive status read(Device"
|
|
hexmask.long.byte 0x0 17.--20. 1. "RPCKST,Recieve packet status"
|
|
bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 4.--14. 1. "BCOUNT,Byte count"
|
|
hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number"
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x0 "GRSTATR_Host,Global Receive status read(Host"
|
|
hexmask.long.byte 0x0 17.--20. 1. "RPCKST,Reivece packet status"
|
|
bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 4.--14. 1. "BCOUNT,Byte count"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CNUM,Channel number"
|
|
line.long 0x4 "GRSTATP_Device,Global Receive status pop(Device"
|
|
hexmask.long.byte 0x4 17.--20. 1. "RPCKST,Recieve packet status"
|
|
bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x4 4.--14. 1. "BCOUNT,Byte count"
|
|
hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "GRSTATP_Host,Global Receive status pop(Host"
|
|
hexmask.long.byte 0x0 17.--20. 1. "RPCKST,Reivece packet status"
|
|
bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 4.--14. 1. "BCOUNT,Byte count"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CNUM,Channel number"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "GRFLEN,Global Receive FIFO size register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXFD,Rx FIFO depth"
|
|
line.long 0x4 "HNPTFLEN,Host non-periodic transmit FIFO length register"
|
|
hexmask.long.word 0x4 16.--31. 1. "HNPTXFD,host non-periodic TxFIFO depth"
|
|
hexmask.long.word 0x4 0.--15. 1. "HNPTXRSAR,host non-periodic transmit Tx RAM start"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "DIEP0TFLEN,Device IN endpoint 0 transmit FIFO length"
|
|
hexmask.long.word 0x0 16.--31. 1. "IEP0TXFD,in endpoint 0 Tx FIFO depth"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEP0TXRSAR,in endpoint 0 Tx RAM start address"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "HNPTFQSTAT,Host non-periodic transmit FIFO/queue"
|
|
hexmask.long.byte 0x0 24.--30. 1. "NPTXRQTOP,Top of the non-periodic transmit request"
|
|
hexmask.long.byte 0x0 16.--23. 1. "NPTXRQS,Non-periodic transmit request queue"
|
|
hexmask.long.word 0x0 0.--15. 1. "NPTXFS,Non-periodic TxFIFO space"
|
|
group.long 0x38++0x7
|
|
line.long 0x0 "GCCFG,Global core configuration register (USBFS_GCCFG)"
|
|
bitfld.long 0x0 21. "VDEN,Enable of VBUS sensing comparator to detect VBUS valid" "0,1"
|
|
bitfld.long 0x0 20. "SOFOEN,SOF output enable" "0,1"
|
|
bitfld.long 0x0 16. "PWRON,Power on" "0,1"
|
|
bitfld.long 0x0 15. "SDMEN,Secondary detection mode enable" "0,1"
|
|
bitfld.long 0x0 14. "PDMEN,Primary detection mode enable" "0,1"
|
|
bitfld.long 0x0 13. "DCDMEN,Data connect detection mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "BCDEN,Battery charging detection enable" "0,1"
|
|
bitfld.long 0x0 3. "PS2F,PS2 detection status" "0,1"
|
|
bitfld.long 0x0 2. "SDF,Secondary detection status" "0,1"
|
|
bitfld.long 0x0 1. "PDF,Primary detection status" "0,1"
|
|
bitfld.long 0x0 0. "DCDF,Data connect detection status" "0,1"
|
|
line.long 0x4 "CID,core ID register"
|
|
hexmask.long 0x4 0.--31. 1. "CID,Core ID"
|
|
group.long 0x54++0x7
|
|
line.long 0x0 "GLPMCFG,Global core LPM configuration register"
|
|
bitfld.long 0x0 28. "BESLEN,LPM Errata selection enable" "0,1"
|
|
bitfld.long 0x0 25.--27. "LPMRCS,LPM retry count status" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24. "LPMSND,Send LPM transaction" "0,1"
|
|
bitfld.long 0x0 21.--23. "LPMRC,LPM retry count" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 17.--20. 1. "LPMCHI,Channel number index when send LPM transaction"
|
|
bitfld.long 0x0 16. "RSOK,Resume can be sent after sleep state" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LPMSLPS,Sleep status" "0,1"
|
|
bitfld.long 0x0 13.--14. "LPMRSP,Response of LPM" "0,1,2,3"
|
|
bitfld.long 0x0 12. "DSEN,Deep sleep enable" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "BESLTH,BESL threshold"
|
|
bitfld.long 0x0 7. "SSEN,Shallow sleep enable" "0,1"
|
|
bitfld.long 0x0 6. "REW,RemoteWake value" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service latency"
|
|
bitfld.long 0x0 1. "ACKLPM,ACK in LPM transaction enable" "0,1"
|
|
bitfld.long 0x0 0. "LPMEN,LPM enable" "0,1"
|
|
line.long 0x4 "PWRD,Power down register (USBHS_PWRD)"
|
|
bitfld.long 0x4 23. "ADPF,ADP event interrupt flag" "0,1"
|
|
bitfld.long 0x4 0. "ADPMEN,ADP module enable" "0,1"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "ADPCTL,ADP control andstatus register"
|
|
bitfld.long 0x0 27.--28. "RWR,Read and write request" "0,1,2,3"
|
|
bitfld.long 0x0 26. "ADPTFM,The mask of ADP timeout interrupt flag" "0,1"
|
|
bitfld.long 0x0 25. "ADPSNFM,The mask of ADP sense interrupt flag" "0,1"
|
|
bitfld.long 0x0 24. "ADPPRFM,The mask of ADP probe interrupt flag" "0,1"
|
|
bitfld.long 0x0 23. "ADPTF,ADP timeout interrupt flag" "0,1"
|
|
bitfld.long 0x0 22. "ADPSNF,ADP sense interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "ADPPRF,ADP probe interrupt flag" "0,1"
|
|
bitfld.long 0x0 20. "ADPEN,ADP enable" "0,1"
|
|
rbitfld.long 0x0 19. "ADPRST,ADP reset" "0,1"
|
|
bitfld.long 0x0 18. "SNEN,ADP sense enable" "0,1"
|
|
bitfld.long 0x0 17. "PREN,ADP probe enable" "0,1"
|
|
hexmask.long.word 0x0 6.--16. 1. "CHGT,The latest time that VBUS ramps from VADPSINK to VADPPRB"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "PERPR,Period of probe" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "RESOPR,The resolution of CHGT value" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "DSCHGPR,Time of probe discharge" "0,1,2,3"
|
|
group.long 0x100++0x17
|
|
line.long 0x0 "HPTFLEN,Host periodic transmit FIFO length register (HPTFLEN)"
|
|
hexmask.long.word 0x0 16.--31. 1. "HPTXFD,Host periodic TxFIFO depth"
|
|
hexmask.long.word 0x0 0.--15. 1. "HPTXFSAR,Host periodic TxFIFO start"
|
|
line.long 0x4 "DIEP1TFLEN,device IN endpoint transmit FIFO size"
|
|
hexmask.long.word 0x4 16.--31. 1. "IEPTXFD,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x4 0.--15. 1. "IEPTXRSAR,IN endpoint FIFO transmit RAM start"
|
|
line.long 0x8 "DIEP2TFLEN,device IN endpoint transmit FIFO size"
|
|
hexmask.long.word 0x8 16.--31. 1. "IEPTXFD,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x8 0.--15. 1. "IEPTXRSAR,IN endpoint FIFO transmit RAM start"
|
|
line.long 0xC "DIEP3TFLEN,device IN endpoint transmit FIFO size"
|
|
hexmask.long.word 0xC 16.--31. 1. "IEPTXFD,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0xC 0.--15. 1. "IEPTXRSAR,IN endpoint FIFO4 transmit RAM start"
|
|
line.long 0x10 "DIEP4TFLEN,device IN endpoint transmit FIFO size"
|
|
hexmask.long.word 0x10 16.--31. 1. "IEPTXFD,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x10 0.--15. 1. "IEPTXRSAR,IN endpoint FIFO4 transmit RAM start"
|
|
line.long 0x14 "DIEP5TFLEN,device IN endpoint transmit FIFO size"
|
|
hexmask.long.word 0x14 16.--31. 1. "IEPTXFD,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x14 0.--15. 1. "IEPTXRSAR,IN endpoint FIFO4 transmit RAM start"
|
|
tree.end
|
|
tree "USBHS1_HOST"
|
|
base ad:0x40080400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "HCTL,host configuration register"
|
|
bitfld.long 0x0 2. "SPDFSLS,Speed limited to FS and LS" "0,1"
|
|
line.long 0x4 "HFT,Host frame interval"
|
|
hexmask.long.word 0x4 0.--15. 1. "FRI,Frame interval"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "HFINFR,OTG_FS host frame number/frame time"
|
|
hexmask.long.word 0x0 16.--31. 1. "FRT,Frame remaining time"
|
|
hexmask.long.word 0x0 0.--15. 1. "FRNUM,Frame number"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "HPTFQSTAT,Host periodic transmit FIFO/queue"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PTXREQT,Top of the periodic transmit request"
|
|
hexmask.long.byte 0x0 16.--23. 1. "PTXREQS,Periodic transmit request queue space"
|
|
hexmask.long.word 0x0 0.--15. 1. "PTXFS,Periodic transmit data FIFO space"
|
|
line.long 0x4 "HACHINT,Host all channels interrupt"
|
|
hexmask.long.word 0x4 0.--11. 1. "HACHINT,Host all channel interrupts"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "HACHINTEN,host all channels interrupt mask"
|
|
hexmask.long.word 0x0 0.--11. 1. "CINTEN,Channel interrupt enable"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "HPCS,Host port control and status register (USBFS_HPCS)"
|
|
rbitfld.long 0x0 17.--18. "PS,Port speed" "0,1,2,3"
|
|
hexmask.long.byte 0x0 13.--16. 1. "PTEST,Port Test control"
|
|
bitfld.long 0x0 12. "PP,Port power" "0,1"
|
|
rbitfld.long 0x0 10.--11. "PLST,Port line status" "0,1,2,3"
|
|
bitfld.long 0x0 8. "PRST,Port reset" "0,1"
|
|
bitfld.long 0x0 7. "PSP,Port suspend" "0,1"
|
|
bitfld.long 0x0 6. "PREM,Port resume" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PEDC,Port enable/disable change" "0,1"
|
|
bitfld.long 0x0 2. "PE,Port enable" "0,1"
|
|
bitfld.long 0x0 1. "PCD,Port connect detected" "0,1"
|
|
rbitfld.long 0x0 0. "PCST,Port connect status" "0,1"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "HCH0CTL,host channel-0 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "HCH1CTL,host channel-1 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "HCH2CTL,host channel-2 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "HCH3CTL,host channel-3 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "HCH4CTL,host channel-4 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x0 "HCH5CTL,host channel-5 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x1C0++0x3
|
|
line.long 0x0 "HCH6CTL,host channel-6 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x1E0++0x3
|
|
line.long 0x0 "HCH7CTL,host channel-7 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "HCH8CTL,host channel-8 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "HCH9CTL,host channel-9 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "HCH10CTL,host channel-10 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x260++0x3
|
|
line.long 0x0 "HCH11CTL,host channel-11 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "HCH12CTL,host channel-12 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "HCH13CTL,host channel-13 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x2C0++0x3
|
|
line.long 0x0 "HCH14CTL,host channel-14 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x2E0++0x3
|
|
line.long 0x0 "HCH15CTL,host channel-15 characteristics"
|
|
bitfld.long 0x0 31. "CEN,Channel enable" "0,1"
|
|
bitfld.long 0x0 30. "CDIS,Channel disable" "0,1"
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAR,Device address"
|
|
bitfld.long 0x0 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.long 0x0 17. "LSD,Low-speed device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1"
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPL,Maximum packet size"
|
|
group.long 0x104++0x3
|
|
line.long 0x0 "HCH0STCTL,host channel-0 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x124++0x3
|
|
line.long 0x0 "HCH1STCTL,host channel-1 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x144++0x3
|
|
line.long 0x0 "HCH2STCTL,host channel-2 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x164++0x3
|
|
line.long 0x0 "HCH3STCTL,host channel-3 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x184++0x3
|
|
line.long 0x0 "HCH4STCTL,host channel-4 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x1A4++0x3
|
|
line.long 0x0 "HCH5STCTL,host channel-5 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x1C4++0x3
|
|
line.long 0x0 "HCH6STCTL,host channel-6 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x1E4++0x3
|
|
line.long 0x0 "HCH7STCTL,host channel-7 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "HCH8STCTL,host channel-8 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x224++0x3
|
|
line.long 0x0 "HCH9STCTL,host channel-9 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x244++0x3
|
|
line.long 0x0 "HCH10STCTL,host channel-10 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x264++0x3
|
|
line.long 0x0 "HCH11STCTL,host channel-11 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x284++0x3
|
|
line.long 0x0 "HCH12STCTL,host channel-12 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x2A4++0x3
|
|
line.long 0x0 "HCH13STCTL,host channel-13 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x2C4++0x3
|
|
line.long 0x0 "HCH14STCTL,host channel-14 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "HCH15STCTL,host channel-15 split transaction control register"
|
|
bitfld.long 0x0 31. "SPLEN,Enable high speed split transaction" "0,1"
|
|
bitfld.long 0x0 16. "CSPLT,Complete split enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "ISOPCE,Isochronous OUT payload continuation encoding" "0,1,2,3"
|
|
hexmask.long.byte 0x0 7.--13. 1. "HADDR,HUB address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PADDR,Port address"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "HCH0INTF,host channel-0 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "HCH1INTF,host channel-1 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x148++0x3
|
|
line.long 0x0 "HCH2INTF,host channel-2 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x168++0x3
|
|
line.long 0x0 "HCH3INTF,host channel-3 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x188++0x3
|
|
line.long 0x0 "HCH4INTF,host channel-4 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x1A8++0x3
|
|
line.long 0x0 "HCH5INTF,host channel-5 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x1C8++0x3
|
|
line.long 0x0 "HCH6INTF,host channel-6 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x1E8++0x3
|
|
line.long 0x0 "HCH7INTF,host channel-7 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x208++0x3
|
|
line.long 0x0 "HCH8INTF,host channel-8 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x228++0x3
|
|
line.long 0x0 "HCH9INTF,host channel-9 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x248++0x3
|
|
line.long 0x0 "HCH10INTF,host channel-10 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x268++0x3
|
|
line.long 0x0 "HCH11INTF,host channel-11 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x288++0x3
|
|
line.long 0x0 "HCH12INTF,host channel-12 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x2A8++0x3
|
|
line.long 0x0 "HCH13INTF,host channel-13 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x2C8++0x3
|
|
line.long 0x0 "HCH14INTF,host channel-14 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x2E8++0x3
|
|
line.long 0x0 "HCH15INTF,host channel-15 interrupt register"
|
|
bitfld.long 0x0 10. "DTER,Data toggle error" "0,1"
|
|
bitfld.long 0x0 9. "REQOVR,Request queue overrun" "0,1"
|
|
bitfld.long 0x0 8. "BBER,Babble error" "0,1"
|
|
bitfld.long 0x0 7. "USBER,USB bus error" "0,1"
|
|
bitfld.long 0x0 6. "NYET,NYET" "0,1"
|
|
bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1"
|
|
bitfld.long 0x0 4. "NAK,NAK response received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALL,STALL response received" "0,1"
|
|
bitfld.long 0x0 2. "DMAER,DMA Error" "0,1"
|
|
bitfld.long 0x0 1. "CH,Channel halted" "0,1"
|
|
bitfld.long 0x0 0. "TF,Transfer finished" "0,1"
|
|
group.long 0x10C++0x3
|
|
line.long 0x0 "HCH0INTEN,host channel-0 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x12C++0x3
|
|
line.long 0x0 "HCH1INTEN,host channel-1 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x14C++0x3
|
|
line.long 0x0 "HCH2INTEN,host channel-2 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x16C++0x3
|
|
line.long 0x0 "HCH3INTEN,host channel-3 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x18C++0x3
|
|
line.long 0x0 "HCH4INTEN,host channel-4 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x1AC++0x3
|
|
line.long 0x0 "HCH5INTEN,host channel-5 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x1CC++0x3
|
|
line.long 0x0 "HCH6INTEN,host channel-6 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x1EC++0x3
|
|
line.long 0x0 "HCH7INTEN,host channel-7 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x20C++0x3
|
|
line.long 0x0 "HCH8INTEN,host channel-8 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x22C++0x3
|
|
line.long 0x0 "HCH9INTEN,host channel-9 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x24C++0x3
|
|
line.long 0x0 "HCH10INTEN,host channel-10 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x26C++0x3
|
|
line.long 0x0 "HCH11INTEN,host channel-11 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x28C++0x3
|
|
line.long 0x0 "HCH12INTEN,host channel-12 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x2AC++0x3
|
|
line.long 0x0 "HCH13INTEN,host channel-13 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x2CC++0x3
|
|
line.long 0x0 "HCH14INTEN,host channel-14 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x2EC++0x3
|
|
line.long 0x0 "HCH15INTEN,host channel-15 interrupt enable register"
|
|
bitfld.long 0x0 10. "DTERIE,Data toggle error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "BBERIE,Babble error interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "USBERIE,USB bus error interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "NYETIE,NYET interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "ACKIE,ACK interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NAKIE,NAK interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STALLIE,STALL interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAERIE,DMA Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CHIE,Channel halted interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "TFIE,Transfer completed interrupt enable" "0,1"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "HCH0LEN,host channel-0 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "HCH1LEN,host channel-1 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x150++0x3
|
|
line.long 0x0 "HCH2LEN,host channel-2 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x170++0x3
|
|
line.long 0x0 "HCH3LEN,host channel-3 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x190++0x3
|
|
line.long 0x0 "HCH4LEN,host channel-4 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x1B0++0x3
|
|
line.long 0x0 "HCH5LEN,host channel-5 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x1D0++0x3
|
|
line.long 0x0 "HCH6LEN,host channel-6 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x1F0++0x3
|
|
line.long 0x0 "HCH7LEN,host channel-7 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x210++0x3
|
|
line.long 0x0 "HCH8LEN,host channel-8 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x230++0x3
|
|
line.long 0x0 "HCH9LEN,host channel-9 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x250++0x3
|
|
line.long 0x0 "HCH10LEN,host channel-10 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x270++0x3
|
|
line.long 0x0 "HCH11LEN,host channel-11 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "HCH12LEN,host channel-12 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x2B0++0x3
|
|
line.long 0x0 "HCH13LEN,host channel-13 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x2D0++0x3
|
|
line.long 0x0 "HCH14LEN,host channel-14 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x2F0++0x3
|
|
line.long 0x0 "HCH15LEN,host channel-15 transfer length"
|
|
bitfld.long 0x0 31. "PING,PING token request" "0,1"
|
|
bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3"
|
|
hexmask.long.word 0x0 19.--28. 1. "PCNT,Packet count"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,Transfer length"
|
|
group.long 0x114++0x3
|
|
line.long 0x0 "HCH0DMAADDR,Host channel 0 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x134++0x3
|
|
line.long 0x0 "HCH1DMAADDR,Host channel 1 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x154++0x3
|
|
line.long 0x0 "HCH2DMAADDR,Host channel 2 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x174++0x3
|
|
line.long 0x0 "HCH3DMAADDR,Host channel 3 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x194++0x3
|
|
line.long 0x0 "HCH4DMAADDR,Host channel 4 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x1B4++0x3
|
|
line.long 0x0 "HCH5DMAADDR,Host channel 5 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x1D4++0x3
|
|
line.long 0x0 "HCH6DMAADDR,Host channel 6 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x1F4++0x3
|
|
line.long 0x0 "HCH7DMAADDR,Host channel 7 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x214++0x3
|
|
line.long 0x0 "HCH8DMAADDR,Host channel 8 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x234++0x3
|
|
line.long 0x0 "HCH9DMAADDR,Host channel 9 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x254++0x3
|
|
line.long 0x0 "HCH10DMAADDR,Host channel 10 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x274++0x3
|
|
line.long 0x0 "HCH11DMAADDR,Host channel 11 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x294++0x3
|
|
line.long 0x0 "HCH12DMAADDR,Host channel 12 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x2B4++0x3
|
|
line.long 0x0 "HCH13DMAADDR,Host channel 13 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x2D4++0x3
|
|
line.long 0x0 "HCH14DMAADDR,Host channel 14 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x2F4++0x3
|
|
line.long 0x0 "HCH15DMAADDR,Host channel 15 DMA address register"
|
|
hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address"
|
|
tree.end
|
|
tree "USBHS1_PWRCLK"
|
|
base ad:0x40080E00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PWRCLKCTL,power and clock gating control"
|
|
rbitfld.long 0x0 7. "DSLEEP,PHY is in deep sleep status" "0,1"
|
|
rbitfld.long 0x0 6. "SSLEEP,PHY is in shallow sleep status" "0,1"
|
|
rbitfld.long 0x0 5. "SCGEN,internal clock gating enable" "0,1"
|
|
rbitfld.long 0x0 4. "SUSP,PHY is in suspend status" "0,1"
|
|
bitfld.long 0x0 1. "SHCLK,Stop HCLK" "0,1"
|
|
bitfld.long 0x0 0. "SUCLK,Stop the USB clock" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "VREF"
|
|
base ad:0x58003C00
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CS,Control and status register"
|
|
rbitfld.long 0x0 4.--5. "VREFS,Voltage reference select" "0,1,2,3"
|
|
rbitfld.long 0x0 3. "VREFRDY,VREF ready" "0,1"
|
|
bitfld.long 0x0 1. "HIPM,High impedance mode" "0,1"
|
|
bitfld.long 0x0 0. "VREFEN,VREF enable" "0,1"
|
|
line.long 0x4 "CALIB,Calibration register"
|
|
hexmask.long.byte 0x4 0.--5. 1. "VREFCAL,VREF calibration"
|
|
tree.end
|
|
tree "WWDGT (Window Watchdog Timer)"
|
|
base ad:0x50003000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 7. "WDGTEN,Activation bit" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CNT,7-bit counter"
|
|
line.long 0x4 "CFG,Configuration register"
|
|
bitfld.long 0x4 9. "EWIE,Early wakeup interrupt" "0,1"
|
|
bitfld.long 0x4 7.--8. "PSC,Prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x4 0.--6. 1. "WIN,7-bit window value"
|
|
line.long 0x8 "STAT,Status register"
|
|
bitfld.long 0x8 0. "EWIF,Early wakeup interrupt" "0,1"
|
|
tree.end
|
|
newline
|
|
AUTOINDENT.OFF
|