746 lines
36 KiB
Plaintext
746 lines
36 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: IMX8XDXL Specific Menu
|
|
; @Props: Released
|
|
; @Author: KWI, JON
|
|
; @Changelog: 2020-07-15 KWI
|
|
; 2021-04-02 KWI
|
|
; 2022-01-22 JON
|
|
; @Manufacturer: NXP - NXP Semiconductors
|
|
; @Core: Cortex-A35, Cortex-M4F
|
|
; @Chip: IMX8DXL, IMX8DXL-CM4, IMX8DXL-SCU
|
|
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: menimx8dxl.men 19879 2025-08-27 15:27:14Z jhuang $
|
|
|
|
add
|
|
menu
|
|
(
|
|
IF SOFTWARE.BUILD.BASE()>=69655.
|
|
(
|
|
popup "&CPU"
|
|
(
|
|
separator
|
|
IF CPU.FEATURE(MMU)&&CPU.FEATURE(MPUTRANSLATION)
|
|
(
|
|
popup "[:mmu]MMU/MPU"
|
|
(
|
|
menuitem "[:mmureg]MMU Control" "MMU.view"
|
|
separator
|
|
menuitem "[:mmu]MMU/MPU Table Dump" "MMU.DUMP.PageTable"
|
|
menuitem "[:mmu]MMU/MPU Table List" "MMU.List.PageTable"
|
|
IF CPU.FEATURE(ITLBDUMP)||CPU.FEATURE(DTLBDUMP)||CPU.FEATURE(TLB0DUMP)||CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
separator
|
|
)
|
|
IF CPU.FEATURE(ITLBDUMP)
|
|
(
|
|
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
|
|
)
|
|
IF CPU.FEATURE(DTLBDUMP)
|
|
(
|
|
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
|
|
)
|
|
IF CPU.FEATURE(TLB0DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
|
|
)
|
|
IF CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
|
|
)
|
|
)
|
|
)
|
|
ELSE
|
|
(
|
|
IF CPU.FEATURE(MMU)
|
|
(
|
|
popup "[:mmu]MMU"
|
|
(
|
|
menuitem "[:mmureg]MMU Control" "MMU.view"
|
|
separator
|
|
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
|
|
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
|
|
IF CPU.FEATURE(ITLBDUMP)||CPU.FEATURE(DTLBDUMP)||CPU.FEATURE(TLB0DUMP)||CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
separator
|
|
)
|
|
IF CPU.FEATURE(ITLBDUMP)
|
|
(
|
|
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
|
|
)
|
|
IF CPU.FEATURE(DTLBDUMP)
|
|
(
|
|
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
|
|
)
|
|
IF CPU.FEATURE(TLB0DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
|
|
)
|
|
IF CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
|
|
)
|
|
)
|
|
)
|
|
IF CPU.FEATURE(MPUTRANSLATION)
|
|
(
|
|
popup "[:mmu]MPU"
|
|
(
|
|
menuitem "[:mmu]MPU Table Dump" "MMU.DUMP.PageTable"
|
|
menuitem "[:mmu]MPU Table List" "MMU.List.PageTable"
|
|
)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU")
|
|
(
|
|
popup "[:mmu]SMMU"
|
|
(
|
|
menuitem "[:chip]SMMU1 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU1 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU2")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU2 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU2 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU3")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU3 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU3 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU4")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU4 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU4 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU5")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU5 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU5 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU6")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU6 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU6 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
)
|
|
)
|
|
IF CPU.FEATURE(L1ICACHEDUMP)||CPU.FEATURE(L1DCACHEDUMP)||CPU.FEATURE(L2CACHEDUMP)
|
|
(
|
|
popup "[:cache]Cache"
|
|
(
|
|
IF CPU.FEATURE(L1ICACHEDUMP)
|
|
(
|
|
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
|
|
menuitem "[:cache]ICACHE List" "CACHE.List IC"
|
|
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
|
|
)
|
|
IF CPU.FEATURE(L1DCACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
|
|
menuitem "[:cache]DCACHE List" "CACHE.List DC"
|
|
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
|
|
)
|
|
IF CPU.FEATURE(L2CACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
|
|
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
|
|
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Trace"
|
|
(
|
|
separator
|
|
IF COMPonent.AVAILable("ITM")
|
|
(
|
|
popup "ITM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]ITM settings..." "ITM.state"
|
|
separator
|
|
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("STM")
|
|
(
|
|
popup "STM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]STM settings..." "STM.state"
|
|
separator
|
|
menuitem "[:alist]STMTrace List" "STMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("HTM")
|
|
(
|
|
popup "HTM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]HTM settings..." "HTM.state"
|
|
separator
|
|
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("TPIU")
|
|
(
|
|
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
|
|
)
|
|
IF COMPonent.AVAILable("ETR")
|
|
(
|
|
menuitem "[:oconfig]ETR settings..."
|
|
(
|
|
PRIVATE &pdd
|
|
&pdd=OS.PDD()
|
|
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
|
|
)
|
|
)
|
|
)
|
|
popup "&Misc"
|
|
(
|
|
popup "Tools"
|
|
(
|
|
IF CPUIS64BIT()||CPU.FEATURE("SPR")
|
|
(
|
|
menuitem "ARM System Register Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
|
|
)
|
|
)
|
|
IF CPU.FEATURE("C15")
|
|
(
|
|
menuitem "ARM Coprocessor Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Perf"
|
|
(
|
|
IF CPU.FEATURE(BMC)
|
|
(
|
|
before "Reset"
|
|
menuitem "[:bmc]Benchmark Counters" "BMC.state"
|
|
before "Reset"
|
|
separator
|
|
)
|
|
)
|
|
)
|
|
popup "Peripherals"
|
|
(
|
|
if (CORENAME()=="CORTEXA35")
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-A35)"
|
|
(
|
|
menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,ID Registers"""
|
|
menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,System Control and Configuration"""
|
|
menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,Memory Management Unit"""
|
|
menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,Virtualization Extensions"""
|
|
menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,Cache Control and Configuration"""
|
|
menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,System Performance Monitor"""
|
|
menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,System Timer Registers"""
|
|
menuitem "[:chip]Generic Interrupt Controller System Registers[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,Generic Interrupt Controller System Registers"""
|
|
separator
|
|
menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,Debug Registers"""
|
|
separator
|
|
menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,Breakpoint Registers"""
|
|
menuitem "[:chip]Watchpoint Control Registers[AArch64]" "per , ""Core Registers (Cortex-A35),AArch64,Watchpoint Control Registers"""
|
|
separator
|
|
menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,ID Registers"""
|
|
menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,System Control and Configuration"""
|
|
menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,Memory Management Unit"""
|
|
menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,Virtualization Extensions"""
|
|
menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,Cache Control and Configuration"""
|
|
menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,System Performance Monitor"""
|
|
menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,System Timer Registers"""
|
|
menuitem "[:chip]Generic Interrupt Controller System Registers[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,Generic Interrupt Controller System Registers"""
|
|
separator
|
|
menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,Debug Registers"""
|
|
separator
|
|
menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,Breakpoint Registers"""
|
|
menuitem "[:chip]Watchpoint Control Registers[AArch32]" "per , ""Core Registers (Cortex-A35),AArch32,Watchpoint Control Registers"""
|
|
separator
|
|
menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A35),Interrupt Controller (GIC-500)"""
|
|
)
|
|
)
|
|
else if (CORENAME()=="CORTEXM4F")
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-M4F)"
|
|
(
|
|
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
|
|
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
|
|
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
|
|
menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
|
|
popup "[:chip]Debug"
|
|
(
|
|
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
|
|
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
|
|
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
|
|
)
|
|
)
|
|
)
|
|
separator
|
|
menuitem "ADMA__ADC0" "per , ""ADC"""
|
|
if cpuis("IMX8D?L-CM4")
|
|
(
|
|
menuitem "LMEM" "per , ""AHB_LMEM64_REV2 (LMEM64),LMEM"""
|
|
)
|
|
menuitem "CONNECTIVITY__APBH" "per , ""APBHDMA (APBH)"""
|
|
menuitem "ADMA__ASRC0" "per , ""ASRC"""
|
|
popup "BBS_SIM (ASMC)"
|
|
(
|
|
menuitem "CM4__ASMC" "per , ""BBS_SIM (ASMC),CM4__ASMC"""
|
|
menuitem "SCU__ASMC" "per , ""BBS_SIM (ASMC),SCU__ASMC"""
|
|
)
|
|
menuitem "CONNECTIVITY__BCH" "per , ""BCH32 (BCH)"""
|
|
menuitem "CM4__LPCG_LPI2C" "per , ""CM4_LPCG_LPI2C,CM4__LPCG_LPI2C"""
|
|
menuitem "CM4__LPCG_LPIT" "per , ""CM4_LPCG_LPIT,CM4__LPCG_LPIT"""
|
|
menuitem "CM4__LPCG_LPUART" "per , ""CM4_LPCG_LPUART,CM4__LPCG_LPUART"""
|
|
menuitem "CM4__LPCG_MMCAU_HCLK" "per , ""CM4_LPCG_MMCAU_HCLK,CM4__LPCG_MMCAU_HCLK"""
|
|
menuitem "CM4__LPCG_TCMC_HCLK" "per , ""CM4_LPCG_TCMC_HCLK,CM4__LPCG_TCMC_HCLK"""
|
|
menuitem "CM4__LPCG_TPM" "per , ""CM4_LPCG_TPM,CM4__LPCG_TPM"""
|
|
menuitem "CONNECTIVITY__LPCG_ENET_QOS" "per , ""CONNECTIVITY_LPCG_ENET_QOS"""
|
|
menuitem "CONNECTIVITY__LPCG_ENET0" "per , ""CONNECTIVITY_LPCG_ENET0"""
|
|
menuitem "CONNECTIVITY__LPCG_RAWNAND" "per , ""CONNECTIVITY_LPCG_RAWNAND"""
|
|
menuitem "CONNECTIVITY__LPCG_USBO2" "per , ""CONNECTIVITY_LPCG_USBO2"""
|
|
popup "CONNECTIVITY_LPCG_USBPHY_"
|
|
(
|
|
menuitem "CONNECTIVITY__LPCG_USBPHY_1" "per , ""CONNECTIVITY_LPCG_USBPHY_,CONNECTIVITY__LPCG_USBPHY_1"""
|
|
menuitem "CONNECTIVITY__LPCG_USBPHY_2" "per , ""CONNECTIVITY_LPCG_USBPHY_,CONNECTIVITY__LPCG_USBPHY_2"""
|
|
)
|
|
popup "CONNECTIVITY_LPCG_USDHC"
|
|
(
|
|
menuitem "CONNECTIVITY__LPCG_USDHC0" "per , ""CONNECTIVITY_LPCG_USDHC,CONNECTIVITY__LPCG_USDHC0"""
|
|
menuitem "CONNECTIVITY__LPCG_USDHC1" "per , ""CONNECTIVITY_LPCG_USDHC,CONNECTIVITY__LPCG_USDHC1"""
|
|
menuitem "CONNECTIVITY__LPCG_USDHC2" "per , ""CONNECTIVITY_LPCG_USDHC,CONNECTIVITY__LPCG_USDHC2"""
|
|
)
|
|
popup "D_IP_FLEXCAN3_SYN (CAN)"
|
|
(
|
|
menuitem "ADMA__CAN0" "per , ""D_IP_FLEXCAN3_SYN (CAN),ADMA__CAN0"""
|
|
menuitem "ADMA__CAN1" "per , ""D_IP_FLEXCAN3_SYN (CAN),ADMA__CAN1"""
|
|
menuitem "ADMA__CAN2" "per , ""D_IP_FLEXCAN3_SYN (CAN),ADMA__CAN2"""
|
|
)
|
|
popup "D_IP_FLEXTIMER32_SYN (FTM)"
|
|
(
|
|
menuitem "ADMA__FTM0" "per , ""D_IP_FLEXTIMER32_SYN (FTM),ADMA__FTM0"""
|
|
menuitem "ADMA__FTM1" "per , ""D_IP_FLEXTIMER32_SYN (FTM),ADMA__FTM1"""
|
|
)
|
|
menuitem "IRQSTEER" "per , ""D_IP_IRQ_STEER_SYN (IRQSTEER)"""
|
|
popup "D_IP_LPIT_SYN (LPIT)"
|
|
(
|
|
menuitem "CM4__LPIT" "per , ""D_IP_LPIT_SYN (LPIT),CM4__LPIT"""
|
|
menuitem "SCU__LPIT" "per , ""D_IP_LPIT_SYN (LPIT),SCU__LPIT"""
|
|
)
|
|
popup "D_IP_USB_DCD_SYN (USBDCD)"
|
|
(
|
|
menuitem "CONNECTIVITY__USBDCD1" "per , ""D_IP_USB_DCD_SYN (USBDCD),CONNECTIVITY__USBDCD1"""
|
|
menuitem "CONNECTIVITY__USBDCD2" "per , ""D_IP_USB_DCD_SYN (USBDCD),CONNECTIVITY__USBDCD2"""
|
|
)
|
|
menuitem "SCU__LPC" "per , ""D_SSL_SCU_LPC_SYN (SCU_LPC)"""
|
|
menuitem "DRC__DDRC" "per , ""DDRC (DDR Controller)"""
|
|
menuitem "DRC__DDR_PHY" "per , ""DWC_DDRPHY_TOP"""
|
|
menuitem "CONNECTIVITY__ENET_QOS" "per , ""DWC_ETHER_QOS (DWC_ether_qos)"""
|
|
menuitem "CONNECTIVITY__ENET0" "per , ""ENET_MACAXI_1G (ENET)"""
|
|
popup "FLEXSPI (FlexSPI)"
|
|
(
|
|
menuitem "LSIO__FLEXSPI0" "per , ""FLEXSPI (FlexSPI),LSIO__FLEXSPI0"""
|
|
menuitem "LSIO__FLEXSPI1" "per , ""FLEXSPI (FlexSPI),LSIO__FLEXSPI1"""
|
|
)
|
|
popup "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
|
|
(
|
|
menuitem "HSIO__GPIO" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),HSIO__GPIO"""
|
|
menuitem "LSIO__GPIO0" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),LSIO__GPIO0"""
|
|
menuitem "LSIO__GPIO1" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),LSIO__GPIO1"""
|
|
menuitem "LSIO__GPIO2" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),LSIO__GPIO2"""
|
|
menuitem "LSIO__GPIO3" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),LSIO__GPIO3"""
|
|
menuitem "LSIO__GPIO4" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),LSIO__GPIO4"""
|
|
menuitem "LSIO__GPIO5" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),LSIO__GPIO5"""
|
|
menuitem "LSIO__GPIO6" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),LSIO__GPIO6"""
|
|
menuitem "LSIO__GPIO7" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),LSIO__GPIO7"""
|
|
)
|
|
menuitem "CONNECTIVITY__GPMI" "per , ""GPMI2 (GPMI)"""
|
|
popup "GPT (General Purpose Timer)"
|
|
(
|
|
menuitem "ADMA__GPT0" "per , ""GPT (General Purpose Timer),ADMA__GPT0"""
|
|
menuitem "ADMA__GPT1" "per , ""GPT (General Purpose Timer),ADMA__GPT1"""
|
|
menuitem "ADMA__GPT2" "per , ""GPT (General Purpose Timer),ADMA__GPT2"""
|
|
menuitem "ADMA__GPT3" "per , ""GPT (General Purpose Timer),ADMA__GPT3"""
|
|
menuitem "LSIO__GPT0" "per , ""GPT (General Purpose Timer),LSIO__GPT0"""
|
|
menuitem "LSIO__GPT1" "per , ""GPT (General Purpose Timer),LSIO__GPT1"""
|
|
menuitem "LSIO__GPT2" "per , ""GPT (General Purpose Timer),LSIO__GPT2"""
|
|
menuitem "LSIO__GPT3" "per , ""GPT (General Purpose Timer),LSIO__GPT3"""
|
|
menuitem "LSIO__GPT4" "per , ""GPT (General Purpose Timer),LSIO__GPT4"""
|
|
)
|
|
menuitem "HSIO__HSIO_MISC_REGS" "per , ""HSIO_MISC_REGS (HSIO CRR module for MISC)"""
|
|
menuitem "HSIO__HSIO_PCIEX1_REGS" "per , ""HSIO_PCIEX1_REGS (HSIO CRR module for PCIe)"""
|
|
menuitem "HSIO__CSR" "per , ""HSIO_PHYX1_REGS (HSIO CRR module for PHY)"""
|
|
popup "INT_MUX (INTMUX)"
|
|
(
|
|
menuitem "CM4__INTMUX" "per , ""INT_MUX (INTMUX),CM4__INTMUX"""
|
|
menuitem "SCU__INTMUX" "per , ""INT_MUX (INTMUX),SCU__INTMUX"""
|
|
)
|
|
menuitem "IOMUXD" "per , ""IOMUXD"""
|
|
menuitem "ADMA__LCDIF" "per , ""LCDIF (LCD Interface)"""
|
|
menuitem "HSIO__LPCG_GPIO_IPG_CLK_S" "per , ""LPCG_GPIO_CLK"""
|
|
menuitem "ADMA__LPCG_ACM_REGS_IPG_CLK" "per , ""LPCG_LPCG_ACM_REGS"""
|
|
menuitem "ADMA__LPCG_ANAMIX_IPG_CLK_ADC0" "per , ""LPCG_LPCG_ADC0"""
|
|
menuitem "DRC__LPCG_DDR_CTL_PCLK" "per , ""LPCG_LPCG_APB"""
|
|
menuitem "ADMA__LPCG_ASRC0_IPG_CLK" "per , ""LPCG_LPCG_ASRC0"""
|
|
popup "LPCG_LPCG_AUD_PLL_DIV_CLK"
|
|
(
|
|
menuitem "ADMA__LPCG_ACM_AUD_PLL_DIV_CLK0" "per , ""LPCG_LPCG_AUD_PLL_DIV_CLK,ADMA__LPCG_ACM_AUD_PLL_DIV_CLK0"""
|
|
menuitem "ADMA__LPCG_ACM_AUD_PLL_DIV_CLK1" "per , ""LPCG_LPCG_AUD_PLL_DIV_CLK,ADMA__LPCG_ACM_AUD_PLL_DIV_CLK1"""
|
|
)
|
|
popup "LPCG_LPCG_AUD_REC_CLK"
|
|
(
|
|
menuitem "ADMA__LPCG_ACM_AUD_REC_CLK0" "per , ""LPCG_LPCG_AUD_REC_CLK,ADMA__LPCG_ACM_AUD_REC_CLK0"""
|
|
menuitem "ADMA__LPCG_ACM_AUD_REC_CLK1" "per , ""LPCG_LPCG_AUD_REC_CLK,ADMA__LPCG_ACM_AUD_REC_CLK1"""
|
|
)
|
|
popup "LPCG_LPCG_CAN"
|
|
(
|
|
menuitem "ADMA__LPCG_CAN0_IPG_CLK" "per , ""LPCG_LPCG_CAN,ADMA__LPCG_CAN0_IPG_CLK"""
|
|
menuitem "ADMA__LPCG_CAN1_IPG_CLK" "per , ""LPCG_LPCG_CAN,ADMA__LPCG_CAN1_IPG_CLK"""
|
|
menuitem "ADMA__LPCG_CAN2_IPG_CLK" "per , ""LPCG_LPCG_CAN,ADMA__LPCG_CAN2_IPG_CLK"""
|
|
)
|
|
menuitem "DRC__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK" "per , ""LPCG_LPCG_DDRC"""
|
|
popup "LPCG_LPCG_EDMA"
|
|
(
|
|
menuitem "ADMA__LPCG_EDMA0_HCLK" "per , ""LPCG_LPCG_EDMA,ADMA__LPCG_EDMA0_HCLK"""
|
|
menuitem "ADMA__LPCG_EDMA2_HCLK" "per , ""LPCG_LPCG_EDMA,ADMA__LPCG_EDMA2_HCLK"""
|
|
menuitem "ADMA__LPCG_EDMA3_HCLK" "per , ""LPCG_LPCG_EDMA,ADMA__LPCG_EDMA3_HCLK"""
|
|
)
|
|
popup "LPCG_LPCG_FTM"
|
|
(
|
|
menuitem "ADMA__LPCG_FTM0_IPG_CLK" "per , ""LPCG_LPCG_FTM,ADMA__LPCG_FTM0_IPG_CLK"""
|
|
menuitem "ADMA__LPCG_FTM1_IPG_CLK" "per , ""LPCG_LPCG_FTM,ADMA__LPCG_FTM1_IPG_CLK"""
|
|
)
|
|
popup "LPCG_LPCG_GPT"
|
|
(
|
|
menuitem "ADMA__LPCG_GPT0_IPG_CLK_24M" "per , ""LPCG_LPCG_GPT,ADMA__LPCG_GPT0_IPG_CLK_24M"""
|
|
menuitem "ADMA__LPCG_GPT1_IPG_CLK_24M" "per , ""LPCG_LPCG_GPT,ADMA__LPCG_GPT1_IPG_CLK_24M"""
|
|
menuitem "ADMA__LPCG_GPT2_IPG_CLK_24M" "per , ""LPCG_LPCG_GPT,ADMA__LPCG_GPT2_IPG_CLK_24M"""
|
|
menuitem "ADMA__LPCG_GPT3_IPG_CLK_24M" "per , ""LPCG_LPCG_GPT,ADMA__LPCG_GPT3_IPG_CLK_24M"""
|
|
)
|
|
popup "LPCG_LPCG_I2C"
|
|
(
|
|
menuitem "ADMA__LPCG_I2C0_IPG_CLK" "per , ""LPCG_LPCG_I2C,ADMA__LPCG_I2C0_IPG_CLK"""
|
|
menuitem "ADMA__LPCG_I2C1_IPG_CLK" "per , ""LPCG_LPCG_I2C,ADMA__LPCG_I2C1_IPG_CLK"""
|
|
menuitem "ADMA__LPCG_I2C2_IPG_CLK" "per , ""LPCG_LPCG_I2C,ADMA__LPCG_I2C2_IPG_CLK"""
|
|
menuitem "ADMA__LPCG_I2C3_IPG_CLK" "per , ""LPCG_LPCG_I2C,ADMA__LPCG_I2C3_IPG_CLK"""
|
|
)
|
|
menuitem "ADMA__LPCG_GIC_CLK" "per , ""LPCG_LPCG_IRQ"""
|
|
menuitem "ADMA__LPCG_LCDIF_APB_CLK" "per , ""LPCG_LPCG_LCDIF"""
|
|
popup "LPCG_LPCG_MCLKOUT"
|
|
(
|
|
menuitem "ADMA__LPCG_MCLKOUT0" "per , ""LPCG_LPCG_MCLKOUT,ADMA__LPCG_MCLKOUT0"""
|
|
menuitem "ADMA__LPCG_MCLKOUT1" "per , ""LPCG_LPCG_MCLKOUT,ADMA__LPCG_MCLKOUT1"""
|
|
)
|
|
menuitem "ADMA__LPCG_MQS_HMCLK" "per , ""LPCG_LPCG_MQS_REGS"""
|
|
menuitem "DRC__LPCG_DDR_PHY_PUB_CTL_CLK" "per , ""LPCG_LPCG_PUB"""
|
|
menuitem "ADMA__LPCG_PWM_IPG_CLK" "per , ""LPCG_LPCG_PWM"""
|
|
popup "LPCG_LPCG_SAI"
|
|
(
|
|
menuitem "ADMA__LPCG_SAI0_IPG_CLK" "per , ""LPCG_LPCG_SAI,ADMA__LPCG_SAI0_IPG_CLK"""
|
|
menuitem "ADMA__LPCG_SAI1_IPG_CLK" "per , ""LPCG_LPCG_SAI,ADMA__LPCG_SAI1_IPG_CLK"""
|
|
menuitem "ADMA__LPCG_SAI2_IPG_CLK" "per , ""LPCG_LPCG_SAI,ADMA__LPCG_SAI2_IPG_CLK"""
|
|
menuitem "ADMA__LPCG_SAI3_IPG_CLK" "per , ""LPCG_LPCG_SAI,ADMA__LPCG_SAI3_IPG_CLK"""
|
|
)
|
|
menuitem "DRC__LPCG_DDR_CTL_SBR_CLK" "per , ""LPCG_LPCG_SBR"""
|
|
menuitem "ADMA__LPCG_SPDIF0_GCLKW_T0" "per , ""LPCG_LPCG_SPDIF0"""
|
|
popup "LPCG_LPCG_SPI"
|
|
(
|
|
menuitem "ADMA__LPCG_SPI0_IPG_CLK" "per , ""LPCG_LPCG_SPI,ADMA__LPCG_SPI0_IPG_CLK"""
|
|
menuitem "ADMA__LPCG_SPI1_IPG_CLK" "per , ""LPCG_LPCG_SPI,ADMA__LPCG_SPI1_IPG_CLK"""
|
|
menuitem "ADMA__LPCG_SPI2_IPG_CLK" "per , ""LPCG_LPCG_SPI,ADMA__LPCG_SPI2_IPG_CLK"""
|
|
menuitem "ADMA__LPCG_SPI3_IPG_CLK" "per , ""LPCG_LPCG_SPI,ADMA__LPCG_SPI3_IPG_CLK"""
|
|
)
|
|
menuitem "DRC__LPCG_SSI_PORT0_CLK" "per , ""LPCG_LPCG_SSI"""
|
|
popup "LPCG_LPCG_UART"
|
|
(
|
|
menuitem "ADMA__LPCG_UART0_IPG_CLK" "per , ""LPCG_LPCG_UART,ADMA__LPCG_UART0_IPG_CLK"""
|
|
menuitem "ADMA__LPCG_UART1_IPG_CLK" "per , ""LPCG_LPCG_UART,ADMA__LPCG_UART1_IPG_CLK"""
|
|
menuitem "ADMA__LPCG_UART2_IPG_CLK" "per , ""LPCG_LPCG_UART,ADMA__LPCG_UART2_IPG_CLK"""
|
|
menuitem "ADMA__LPCG_UART3_IPG_CLK" "per , ""LPCG_LPCG_UART,ADMA__LPCG_UART3_IPG_CLK"""
|
|
)
|
|
menuitem "SCU__LPCG_LPI2C" "per , ""LPCG_LPI2C"""
|
|
menuitem "SCU__LPCG_LPIT" "per , ""LPCG_LPIT"""
|
|
menuitem "SCU__LPCG_LPUART" "per , ""LPCG_LPUART"""
|
|
menuitem "HSIO__LPCG_HSIO_MISC_REGS_IPG_CLK" "per , ""LPCG_MISC_CRR5"""
|
|
menuitem "SCU__LPCG_MMCAU_HCLK" "per , ""LPCG_MMCAU_HCLK"""
|
|
menuitem "HSIO__LPCG_PCIE_CLK_RST_A_MSTR_AXI_CLK" "per , ""LPCG_PCIEX1"""
|
|
menuitem "HSIO__LPCG_HSIO_PCIEX1_REGS_IPG_CLK" "per , ""LPCG_PCIEX1_CRR3"""
|
|
menuitem "HSIO__LPCG_PCS_PHY_X1_APB_PCLK_0" "per , ""LPCG_PHYX1"""
|
|
menuitem "HSIO__LPCG_HSIO_PHYX1_REGS_IPG_CLK" "per , ""LPCG_PHYX1_CRR1"""
|
|
menuitem "HSIO__LPCG_SSI_PCLK" "per , ""LPCG_SSI"""
|
|
menuitem "SCU__LPCG_TCMC_HCLK" "per , ""LPCG_TCMC_HCLK"""
|
|
menuitem "SCU__LPCG_TPM" "per , ""LPCG_TPM"""
|
|
popup "LPI2C"
|
|
(
|
|
menuitem "ADMA__LPI2C0" "per , ""LPI2C,ADMA__LPI2C0"""
|
|
menuitem "ADMA__LPI2C1" "per , ""LPI2C,ADMA__LPI2C1"""
|
|
menuitem "ADMA__LPI2C2" "per , ""LPI2C,ADMA__LPI2C2"""
|
|
menuitem "ADMA__LPI2C3" "per , ""LPI2C,ADMA__LPI2C3"""
|
|
menuitem "CM4__LPI2C" "per , ""LPI2C,CM4__LPI2C"""
|
|
menuitem "SCU__LPI2C" "per , ""LPI2C,SCU__LPI2C"""
|
|
)
|
|
popup "LPSPI"
|
|
(
|
|
menuitem "ADMA__LPSPI0" "per , ""LPSPI,ADMA__LPSPI0"""
|
|
menuitem "ADMA__LPSPI1" "per , ""LPSPI,ADMA__LPSPI1"""
|
|
menuitem "ADMA__LPSPI2" "per , ""LPSPI,ADMA__LPSPI2"""
|
|
menuitem "ADMA__LPSPI3" "per , ""LPSPI,ADMA__LPSPI3"""
|
|
)
|
|
popup "LPTPM (TPM)"
|
|
(
|
|
menuitem "CM4__TPM" "per , ""LPTPM (TPM),CM4__TPM"""
|
|
menuitem "SCU__TPM" "per , ""LPTPM (TPM),SCU__TPM"""
|
|
)
|
|
popup "LPUART"
|
|
(
|
|
menuitem "ADMA__LPUART0" "per , ""LPUART,ADMA__LPUART0"""
|
|
menuitem "ADMA__LPUART1" "per , ""LPUART,ADMA__LPUART1"""
|
|
menuitem "ADMA__LPUART2" "per , ""LPUART,ADMA__LPUART2"""
|
|
menuitem "ADMA__LPUART3" "per , ""LPUART,ADMA__LPUART3"""
|
|
menuitem "CM4__LPUART" "per , ""LPUART,CM4__LPUART"""
|
|
menuitem "SCU__LPUART" "per , ""LPUART,SCU__LPUART"""
|
|
)
|
|
popup "LSIO_LPCG_GPIO"
|
|
(
|
|
menuitem "LSIO__LPCG_GPIO0" "per , ""LSIO_LPCG_GPIO,LSIO__LPCG_GPIO0"""
|
|
menuitem "LSIO__LPCG_GPIO1" "per , ""LSIO_LPCG_GPIO,LSIO__LPCG_GPIO1"""
|
|
menuitem "LSIO__LPCG_GPIO2" "per , ""LSIO_LPCG_GPIO,LSIO__LPCG_GPIO2"""
|
|
menuitem "LSIO__LPCG_GPIO3" "per , ""LSIO_LPCG_GPIO,LSIO__LPCG_GPIO3"""
|
|
menuitem "LSIO__LPCG_GPIO4" "per , ""LSIO_LPCG_GPIO,LSIO__LPCG_GPIO4"""
|
|
menuitem "LSIO__LPCG_GPIO5" "per , ""LSIO_LPCG_GPIO,LSIO__LPCG_GPIO5"""
|
|
menuitem "LSIO__LPCG_GPIO6" "per , ""LSIO_LPCG_GPIO,LSIO__LPCG_GPIO6"""
|
|
menuitem "LSIO__LPCG_GPIO7" "per , ""LSIO_LPCG_GPIO,LSIO__LPCG_GPIO7"""
|
|
)
|
|
popup "LSIO_LPCG_GPT"
|
|
(
|
|
menuitem "LSIO__LPCG_GPT0" "per , ""LSIO_LPCG_GPT,LSIO__LPCG_GPT0"""
|
|
menuitem "LSIO__LPCG_GPT1" "per , ""LSIO_LPCG_GPT,LSIO__LPCG_GPT1"""
|
|
menuitem "LSIO__LPCG_GPT2" "per , ""LSIO_LPCG_GPT,LSIO__LPCG_GPT2"""
|
|
menuitem "LSIO__LPCG_GPT3" "per , ""LSIO_LPCG_GPT,LSIO__LPCG_GPT3"""
|
|
menuitem "LSIO__LPCG_GPT4" "per , ""LSIO_LPCG_GPT,LSIO__LPCG_GPT4"""
|
|
)
|
|
menuitem "LSIO__LPCG_KPP" "per , ""LSIO_LPCG_KPP"""
|
|
menuitem "LSIO__LPCG_MU10_DSP" "per , ""LSIO_LPCG_MU10_DSP"""
|
|
menuitem "LSIO__LPCG_MU10_MCU" "per , ""LSIO_LPCG_MU10_MCU"""
|
|
menuitem "LSIO__LPCG_MU11_DSP" "per , ""LSIO_LPCG_MU11_DSP"""
|
|
menuitem "LSIO__LPCG_MU11_MCU" "per , ""LSIO_LPCG_MU11_MCU"""
|
|
menuitem "LSIO__LPCG_MU12_DSP" "per , ""LSIO_LPCG_MU12_DSP"""
|
|
menuitem "LSIO__LPCG_MU12_MCU" "per , ""LSIO_LPCG_MU12_MCU"""
|
|
menuitem "LSIO__LPCG_MU13_DSP" "per , ""LSIO_LPCG_MU13_DSP"""
|
|
menuitem "LSIO__LPCG_MU13_MCU" "per , ""LSIO_LPCG_MU13_MCU"""
|
|
menuitem "LSIO__LPCG_MU5_DSP" "per , ""LSIO_LPCG_MU5_DSP"""
|
|
menuitem "LSIO__LPCG_MU5_MCU" "per , ""LSIO_LPCG_MU5_MCU"""
|
|
menuitem "LSIO__LPCG_MU6_DSP" "per , ""LSIO_LPCG_MU6_DSP"""
|
|
menuitem "LSIO__LPCG_MU6_MCU" "per , ""LSIO_LPCG_MU6_MCU"""
|
|
menuitem "LSIO__LPCG_MU7_DSP" "per , ""LSIO_LPCG_MU7_DSP"""
|
|
menuitem "LSIO__LPCG_MU7_MCU" "per , ""LSIO_LPCG_MU7_MCU"""
|
|
menuitem "LSIO__LPCG_MU8_DSP" "per , ""LSIO_LPCG_MU8_DSP"""
|
|
menuitem "LSIO__LPCG_MU8_MCU" "per , ""LSIO_LPCG_MU8_MCU"""
|
|
menuitem "LSIO__LPCG_MU9_DSP" "per , ""LSIO_LPCG_MU9_DSP"""
|
|
menuitem "LSIO__LPCG_MU9_MCU" "per , ""LSIO_LPCG_MU9_MCU"""
|
|
menuitem "LSIO__LPCG_OCRAM" "per , ""LSIO_LPCG_OCRAM"""
|
|
popup "LSIO_LPCG_PWM"
|
|
(
|
|
menuitem "LSIO__LPCG_PWM0" "per , ""LSIO_LPCG_PWM,LSIO__LPCG_PWM0"""
|
|
menuitem "LSIO__LPCG_PWM1" "per , ""LSIO_LPCG_PWM,LSIO__LPCG_PWM1"""
|
|
menuitem "LSIO__LPCG_PWM2" "per , ""LSIO_LPCG_PWM,LSIO__LPCG_PWM2"""
|
|
menuitem "LSIO__LPCG_PWM3" "per , ""LSIO_LPCG_PWM,LSIO__LPCG_PWM3"""
|
|
menuitem "LSIO__LPCG_PWM4" "per , ""LSIO_LPCG_PWM,LSIO__LPCG_PWM4"""
|
|
menuitem "LSIO__LPCG_PWM5" "per , ""LSIO_LPCG_PWM,LSIO__LPCG_PWM5"""
|
|
menuitem "LSIO__LPCG_PWM6" "per , ""LSIO_LPCG_PWM,LSIO__LPCG_PWM6"""
|
|
menuitem "LSIO__LPCG_PWM7" "per , ""LSIO_LPCG_PWM,LSIO__LPCG_PWM7"""
|
|
)
|
|
popup "LSIO_LPCG_QSPI"
|
|
(
|
|
menuitem "LSIO__LPCG_QSPI0" "per , ""LSIO_LPCG_QSPI,LSIO__LPCG_QSPI0"""
|
|
menuitem "LSIO__LPCG_QSPI1" "per , ""LSIO_LPCG_QSPI,LSIO__LPCG_QSPI1"""
|
|
)
|
|
popup "MUA (Messaging Unit Processor A-side)"
|
|
(
|
|
menuitem "CM4__MU0_A0" "per , ""MUA (Messaging Unit Processor A-side),CM4__MU0_A0"""
|
|
menuitem "CM4__MU0_A1" "per , ""MUA (Messaging Unit Processor A-side),CM4__MU0_A1"""
|
|
menuitem "CM4__MU0_A2" "per , ""MUA (Messaging Unit Processor A-side),CM4__MU0_A2"""
|
|
menuitem "CM4__MU0_A3" "per , ""MUA (Messaging Unit Processor A-side),CM4__MU0_A3"""
|
|
menuitem "CM4__MU1_A" "per , ""MUA (Messaging Unit Processor A-side),CM4__MU1_A"""
|
|
menuitem "LSIO__MU0_A" "per , ""MUA (Messaging Unit Processor A-side),LSIO__MU0_A"""
|
|
menuitem "LSIO__MU1_A" "per , ""MUA (Messaging Unit Processor A-side),LSIO__MU1_A"""
|
|
menuitem "LSIO__MU2_A" "per , ""MUA (Messaging Unit Processor A-side),LSIO__MU2_A"""
|
|
menuitem "LSIO__MU3_A" "per , ""MUA (Messaging Unit Processor A-side),LSIO__MU3_A"""
|
|
menuitem "LSIO__MU4_A" "per , ""MUA (Messaging Unit Processor A-side),LSIO__MU4_A"""
|
|
menuitem "LSIO__MU5_A" "per , ""MUA (Messaging Unit Processor A-side),LSIO__MU5_A"""
|
|
menuitem "LSIO__MU6_A" "per , ""MUA (Messaging Unit Processor A-side),LSIO__MU6_A"""
|
|
menuitem "LSIO__MU7_A" "per , ""MUA (Messaging Unit Processor A-side),LSIO__MU7_A"""
|
|
menuitem "LSIO__MU8_A" "per , ""MUA (Messaging Unit Processor A-side),LSIO__MU8_A"""
|
|
menuitem "LSIO__MU9_A" "per , ""MUA (Messaging Unit Processor A-side),LSIO__MU9_A"""
|
|
menuitem "LSIO__MU10_A" "per , ""MUA (Messaging Unit Processor A-side),LSIO__MU10_A"""
|
|
menuitem "LSIO__MU11_A" "per , ""MUA (Messaging Unit Processor A-side),LSIO__MU11_A"""
|
|
menuitem "LSIO__MU12_A" "per , ""MUA (Messaging Unit Processor A-side),LSIO__MU12_A"""
|
|
menuitem "LSIO__MU13_A" "per , ""MUA (Messaging Unit Processor A-side),LSIO__MU13_A"""
|
|
menuitem "SCU__MU0_A0" "per , ""MUA (Messaging Unit Processor A-side),SCU__MU0_A0"""
|
|
menuitem "SCU__MU0_A1" "per , ""MUA (Messaging Unit Processor A-side),SCU__MU0_A1"""
|
|
menuitem "SCU__MU0_A2" "per , ""MUA (Messaging Unit Processor A-side),SCU__MU0_A2"""
|
|
menuitem "SCU__MU0_A3" "per , ""MUA (Messaging Unit Processor A-side),SCU__MU0_A3"""
|
|
menuitem "SCU__MU1_A" "per , ""MUA (Messaging Unit Processor A-side),SCU__MU1_A"""
|
|
)
|
|
popup "MUB (Messaging Unit Processor B-side)"
|
|
(
|
|
menuitem "CM4__MU0_B0" "per , ""MUB (Messaging Unit Processor B-side),CM4__MU0_B0"""
|
|
menuitem "CM4__MU0_B1" "per , ""MUB (Messaging Unit Processor B-side),CM4__MU0_B1"""
|
|
menuitem "CM4__MU0_B2" "per , ""MUB (Messaging Unit Processor B-side),CM4__MU0_B2"""
|
|
menuitem "CM4__MU0_B3" "per , ""MUB (Messaging Unit Processor B-side),CM4__MU0_B3"""
|
|
menuitem "LSIO__MU5_B" "per , ""MUB (Messaging Unit Processor B-side),LSIO__MU5_B"""
|
|
menuitem "LSIO__MU6_B" "per , ""MUB (Messaging Unit Processor B-side),LSIO__MU6_B"""
|
|
menuitem "LSIO__MU7_B" "per , ""MUB (Messaging Unit Processor B-side),LSIO__MU7_B"""
|
|
menuitem "LSIO__MU8_B" "per , ""MUB (Messaging Unit Processor B-side),LSIO__MU8_B"""
|
|
menuitem "LSIO__MU9_B" "per , ""MUB (Messaging Unit Processor B-side),LSIO__MU9_B"""
|
|
menuitem "LSIO__MU10_B" "per , ""MUB (Messaging Unit Processor B-side),LSIO__MU10_B"""
|
|
menuitem "LSIO__MU11_B" "per , ""MUB (Messaging Unit Processor B-side),LSIO__MU11_B"""
|
|
menuitem "LSIO__MU12_B" "per , ""MUB (Messaging Unit Processor B-side),LSIO__MU12_B"""
|
|
menuitem "LSIO__MU13_B" "per , ""MUB (Messaging Unit Processor B-side),LSIO__MU13_B"""
|
|
menuitem "SCU__MU0_B0" "per , ""MUB (Messaging Unit Processor B-side),SCU__MU0_B0"""
|
|
menuitem "SCU__MU0_B1" "per , ""MUB (Messaging Unit Processor B-side),SCU__MU0_B1"""
|
|
menuitem "SCU__MU0_B2" "per , ""MUB (Messaging Unit Processor B-side),SCU__MU0_B2"""
|
|
menuitem "SCU__MU0_B3" "per , ""MUB (Messaging Unit Processor B-side),SCU__MU0_B3"""
|
|
)
|
|
menuitem "HSIO__PCIE_PHY" "per , ""PHY_PMAPCS_TOP (PCIE_PHY)"""
|
|
popup "PWM (Pulse-Width Modulator)"
|
|
(
|
|
menuitem "ADMA__PWM" "per , ""PWM (Pulse-Width Modulator),ADMA__PWM"""
|
|
menuitem "LSIO__PWM0" "per , ""PWM (Pulse-Width Modulator),LSIO__PWM0"""
|
|
menuitem "LSIO__PWM1" "per , ""PWM (Pulse-Width Modulator),LSIO__PWM1"""
|
|
menuitem "LSIO__PWM2" "per , ""PWM (Pulse-Width Modulator),LSIO__PWM2"""
|
|
menuitem "LSIO__PWM3" "per , ""PWM (Pulse-Width Modulator),LSIO__PWM3"""
|
|
menuitem "LSIO__PWM4" "per , ""PWM (Pulse-Width Modulator),LSIO__PWM4"""
|
|
menuitem "LSIO__PWM5" "per , ""PWM (Pulse-Width Modulator),LSIO__PWM5"""
|
|
menuitem "LSIO__PWM6" "per , ""PWM (Pulse-Width Modulator),LSIO__PWM6"""
|
|
menuitem "LSIO__PWM7" "per , ""PWM (Pulse-Width Modulator),LSIO__PWM7"""
|
|
)
|
|
popup "RGPIO2P (GPIO)"
|
|
(
|
|
menuitem "CM4__RGPIO" "per , ""RGPIO2P (GPIO),CM4__RGPIO"""
|
|
menuitem "SCU__RGPIO" "per , ""RGPIO2P (GPIO),SCU__RGPIO"""
|
|
)
|
|
popup "SAI (I2S)"
|
|
(
|
|
menuitem "ADMA__SAI0" "per , ""SAI (I2S),ADMA__SAI0"""
|
|
menuitem "ADMA__SAI1" "per , ""SAI (I2S),ADMA__SAI1"""
|
|
menuitem "ADMA__SAI2" "per , ""SAI (I2S),ADMA__SAI2"""
|
|
menuitem "ADMA__SAI3" "per , ""SAI (I2S),ADMA__SAI3"""
|
|
)
|
|
popup "SEMA42_IPS (SEMA42)"
|
|
(
|
|
menuitem "CM4__SEMA42" "per , ""SEMA42_IPS (SEMA42),CM4__SEMA42"""
|
|
menuitem "SCU__SEMA42" "per , ""SEMA42_IPS (SEMA42),SCU__SEMA42"""
|
|
)
|
|
menuitem "ADMA__SPDIF0" "per , ""SPDIF (Sony/Philips Digital Interface)"""
|
|
popup "SPP_DMA3 (DMA MP)"
|
|
(
|
|
menuitem "ADMA__EDMA0" "per , ""SPP_DMA3 (DMA MP),ADMA__EDMA0"""
|
|
menuitem "ADMA__EDMA2" "per , ""SPP_DMA3 (DMA MP),ADMA__EDMA2"""
|
|
menuitem "ADMA__EDMA3" "per , ""SPP_DMA3 (DMA MP),ADMA__EDMA3"""
|
|
)
|
|
popup "SPP_DMA3_TCD (DMA TCD)"
|
|
(
|
|
menuitem "ADMA__EDMA0_TCD" "per , ""SPP_DMA3_TCD (DMA TCD),ADMA__EDMA0_TCD"""
|
|
menuitem "ADMA__EDMA2_TCD" "per , ""SPP_DMA3_TCD (DMA TCD),ADMA__EDMA2_TCD"""
|
|
menuitem "ADMA__EDMA3_TCD" "per , ""SPP_DMA3_TCD (DMA TCD),ADMA__EDMA3_TCD"""
|
|
)
|
|
menuitem "ADMA__ACM" "per , ""SS_ADMA__ACM (ACM control IPS slave)"""
|
|
popup "TSTMR (Timestamp Timer)"
|
|
(
|
|
menuitem "CM4__TSTMR" "per , ""TSTMR (Timestamp Timer),CM4__TSTMR"""
|
|
menuitem "SCU__TSTMR" "per , ""TSTMR (Timestamp Timer),SCU__TSTMR"""
|
|
)
|
|
menuitem "CONNECTIVITY__USB" "per , ""USB (Universal Serial Bus)"""
|
|
menuitem "CONNECTIVITY__USBNC" "per , ""USBNC (Universal Serial Bus)"""
|
|
popup "USBPHY (USBPHY Register Reference Index)"
|
|
(
|
|
menuitem "CONNECTIVITY__USBPHY1" "per , ""USBPHY (USBPHY Register Reference Index),CONNECTIVITY__USBPHY1"""
|
|
menuitem "CONNECTIVITY__USBPHY2" "per , ""USBPHY (USBPHY Register Reference Index),CONNECTIVITY__USBPHY2"""
|
|
)
|
|
popup "USDHC (Ultra Secured Digital Host Controller)"
|
|
(
|
|
menuitem "CONNECTIVITY__USDHC0" "per , ""USDHC (Ultra Secured Digital Host Controller),CONNECTIVITY__USDHC0"""
|
|
menuitem "CONNECTIVITY__USDHC1" "per , ""USDHC (Ultra Secured Digital Host Controller),CONNECTIVITY__USDHC1"""
|
|
menuitem "CONNECTIVITY__USDHC2" "per , ""USDHC (Ultra Secured Digital Host Controller),CONNECTIVITY__USDHC2"""
|
|
)
|
|
popup "WDOG (Watchdog Timer Unit)"
|
|
(
|
|
menuitem "CM4__WDOG" "per , ""WDOG (Watchdog Timer Unit),CM4__WDOG"""
|
|
menuitem "SCU__WDOG" "per , ""WDOG (Watchdog Timer Unit),SCU__WDOG"""
|
|
)
|
|
)
|
|
)
|