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Work/Src/Gen4_R-Car_Trace32/2_Trunk/pergd32g553.per
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; --------------------------------------------------------------------------------
; @Title: GD32G553 On-Chip Peripherals
; @Props: Released
; @Author: KRZ
; @Changelog: 2025-07-04 KRZ
; @Manufacturer: GigaDevice - GigaDevice Semiconductor Inc.
; @Doc: Generated (TRACE32, build: 180698.), based on:
; GD32A503.svd (GD32G5x3_DFP.1.1.0)
; @Core: Cortex-M33F
; @Chip: GD32G553*
; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: pergd32g553.per 19702 2025-07-04 14:44:03Z kwisniewski $
AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M33F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 29. " EXTEXCLALL ,Allows external exclusive operations to be used in a configuration with no MPU" "No,Yes"
bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
textline " "
bitfld.long 0x00 9. " DISOOFP ,Disables floating-point" "No,Yes"
bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle" "No,Yes"
group.long 0x0C++0x0F
line.long 0x00 "CPPWR,Coprocessor Power Control Register"
bitfld.long 0x00 21. " SUS10 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 20. " SU10 ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 15. " SUS7 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 14. " SU7 ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 13. " SUS6 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 12. " SU6 ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline " "
bitfld.long 0x00 11. " SUS5 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 10. " SU5 ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 9. " SUS4 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 8. " SU4 ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 7. " SUS3 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 6. " SU3 ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline " "
bitfld.long 0x00 5. " SUS2 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 4. " SU2 ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 3. " SUS1 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 2. " SU1 ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 1. " SUS0 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 0. " SU0 ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted"
line.long 0x04 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x04 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
bitfld.long 0x04 2. " CLKSOURCE ,SysTick clock source" "External,Core"
bitfld.long 0x04 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
textline " "
bitfld.long 0x04 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
line.long 0x08 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x0C "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT ,Current counter value"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPUID Base Register"
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main Extension"
newline
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xD21=Cortex-M33"
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control and State Register"
setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET , On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET , On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
textline " "
bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
textline " "
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
textline " "
bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration and Control Register"
bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
textline " "
bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
line.long 0x14 "SHPR1,System Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of system handler 7, SecureFault"
hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6, UsageFault"
hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5, BusFault"
textline " "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4, MemManage"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
bitfld.long 0x20 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
bitfld.long 0x20 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
textline " "
bitfld.long 0x20 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
textline " "
bitfld.long 0x20 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
textline " "
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
bitfld.long 0x20 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
bitfld.long 0x20 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
textline " "
bitfld.long 0x20 8. " MONITORACT ,Monitor exception status" "Not active,Active"
bitfld.long 0x20 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
bitfld.long 0x20 5. " NMIACT ,NMI exception status" "Not active,Active"
textline " "
bitfld.long 0x20 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
bitfld.long 0x20 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
bitfld.long 0x20 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
textline " "
bitfld.long 0x20 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
bitfld.long 0x20 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. " MSTKERR ,Stacking Access Violations" "Not occurred,Occurred"
textline " "
bitfld.byte 0x00 3. " MUNSTKERR ,Unstacking Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. " STKERR ,Derived bus fault (exception entry)" "Not occurred,Occurred"
textline " "
bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault (exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
textline " "
bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "UFSR,Usage Fault Status Register"
eventfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
eventfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
eventfld.word 0x00 4. " STKOF ,Stack overflow error" "No error,Error"
textline " "
eventfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
eventfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
eventfld.word 0x00 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
textline " "
eventfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x03
line.long 0x00 "HFSR,HardFault Status Register"
bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD48)
group.long 0xD8C++0x03
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 11. " CP11 ,Enables Non-secure access to coprocessor CP11" "Disabled,Enabled"
bitfld.long 0x00 10. " CP10 ,Enables Non-secure access to coprocessor CP10" "Disabled,Enabled"
bitfld.long 0x00 7. " CP7 ,Enables Non-secure access to coprocessor CP7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " CP6 ,Enables Non-secure access to coprocessor CP6" "Disabled,Enabled"
bitfld.long 0x00 5. " CP5 ,Enables Non-secure access to coprocessor CP5" "Disabled,Enabled"
bitfld.long 0x00 4. " CP4 ,Enables Non-secure access to coprocessor CP4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " CP3 ,Enables Non-secure access to coprocessor CP3" "Disabled,Enabled"
bitfld.long 0x00 2. " CP2 ,Enables Non-secure access to coprocessor CP2" "Disabled,Enabled"
bitfld.long 0x00 1. " CP1 ,Enables Non-secure access to coprocessor CP1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " CP0 ,Enables Non-secure access to coprocessor CP0" "Disabled,Enabled"
else
hgroup.long 0xD8C++0x03
hide.long 0x00 "NSACR,Non-Secure Access Control Register (not accessible)"
endif
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Triggered Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be pended"
tree "Memory System"
width 10.
rgroup.long 0xD78++0x03
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
textline " "
bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
textline " "
bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
textline " "
bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C)&0xE0000000)==0x80000000)
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
textline " "
bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
endif
rgroup.long 0xD80++0x03
line.long 0x00 "CCSIDR,Cache Size ID Register"
bitfld.long 0x00 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
bitfld.long 0x00 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
bitfld.long 0x00 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
textline " "
bitfld.long 0x00 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
textline " "
bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
group.long 0xD84++0x03
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
wgroup.long 0xF50++0x03
line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
wgroup.long 0xF58++0x23
line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
tree.end
tree "Feature Registers"
width 10.
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1 ,T32 instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
bitfld.long 0x04 4.--7. " SECURITY ,Security support" "Not implemented,Implemented,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " MPROFDBG ,M-profile debug. Indicates the supported M-profile debug architecture" "Not supported,ARMv8-M Debug architecture,?..."
rgroup.long 0xD4C++0x03
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. " TCM ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..."
textline " "
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,,PMSAv8,?..."
rgroup.long 0xD54++0x03
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD5C++0x03
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 8.--11. " BPMAINT ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..."
bitfld.long 0x00 4.--7. " CMAINTSW ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..."
bitfld.long 0x00 0.--3. " CMAINTVA ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..."
rgroup.long 0xD60++0x03
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
rgroup.long 0xD64++0x03
line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x00 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x00 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline " "
bitfld.long 0x00 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Basic,Extended,?..."
rgroup.long 0xD68++0x03
line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x00 28.--31. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x00 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x00 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,SMULL/SMLAL,,SMULL/SMLAL/DSP,?..."
textline " "
bitfld.long 0x00 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MUL,MUL/MLA/MLS,?..."
bitfld.long 0x00 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x00 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline " "
bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,,Load-acquire/Store-release/Exclusive,?..."
rgroup.long 0xD6C++0x03
line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x00 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x00 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline " "
bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x00 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Extended,?..."
textline " "
bitfld.long 0x00 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..."
rgroup.long 0xD70++0x03
line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x00 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,CPS/MRS/MSR,?..."
bitfld.long 0x00 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" ",,,Supported,?..."
bitfld.long 0x00 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,,,DMB/DSB/ISB,?..."
textline " "
bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x00 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,,,Load/store,?..."
bitfld.long 0x00 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,?..."
tree.end
tree "CoreSight Identification Registers"
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 11.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "DPIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DPIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DPIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DPIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "DCIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "DCIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "DCIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
endif
tree.end
newline
group.long 0xDC0++0x07
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 24.--27. " ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 16.--19. " ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 8.--11. " ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 0.--3. " ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 24.--27. " ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 16.--19. " ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 8.--11. " ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 0.--3. " ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Security Attribution Unit (SAU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
group.long 0xDD0++0x03
line.long 0x00 "SAU_CTRL,SAU Control Register"
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
rgroup.long 0xDD4++0x03
line.long 0x00 "SAU_TYPE,SAU Type Register"
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xDD8++0x03
line.long 0x00 "SAU_RNR,SAU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
tree.close "SAU regions"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x0
group.long 0xDDC++0x03 "Region 0"
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x1
group.long 0xDDC++0x03 "Region 1"
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x2
group.long 0xDDC++0x03 "Region 2"
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x3
group.long 0xDDC++0x03 "Region 3"
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x4
group.long 0xDDC++0x03 "Region 4"
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x5
group.long 0xDDC++0x03 "Region 5"
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x6
group.long 0xDDC++0x03 "Region 6"
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x7
group.long 0xDDC++0x03 "Region 7"
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
else
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
tree.end
group.long 0xDE4++0x03
line.long 0x00 "SFSR,Secure Fault Status Register"
bitfld.long 0x00 7. " LSERR ,Lazy state error flag" "Not occurred,Occurred"
bitfld.long 0x00 6. " SFARVALID ,Secure fault address valid" "Not valid,Valid"
bitfld.long 0x00 5. " LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred"
bitfld.long 0x00 3. " AUVIOL ,Attribution unit violation flag" "Not occurred,Occurred"
bitfld.long 0x00 2. " INVER ,Invalid exception return flag" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 1. " INVIS ,Invalid integrity signature flag" "Not occurred,Occurred"
bitfld.long 0x00 0. " INVEP ,Invalid entry point" "Not occurred,Occurred"
group.long 0xDE8++0x03
line.long 0x00 "SFAR,Secure Fault Address Register"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
group.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,0-511"
width 24.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x104++0x03
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x104++0x03
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x108++0x03
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x108++0x03
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x10C++0x03
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x10C++0x03
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x110++0x03
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x110++0x03
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x114++0x03
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x114++0x03
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x118++0x03
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x118++0x03
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x11C++0x03
line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA254 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA253 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA252 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA251 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA250 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA248 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA247 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA246 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA245 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA244 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA242 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA241 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA240 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x11C++0x03
hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x120++0x03
line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA286 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA285 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA284 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA283 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA282 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA280 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA279 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA278 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA277 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA276 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA274 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA273 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA272 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA271 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA270 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA268 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA267 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA266 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA265 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA264 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA262 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA261 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA260 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA259 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA258 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA256 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x120++0x03
hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x124++0x03
line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA318 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA317 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA316 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA315 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA314 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA312 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA311 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA310 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA309 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA308 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA306 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA305 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA304 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA303 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA302 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA300 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA299 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA298 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA297 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA296 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA294 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA293 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA292 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA291 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA290 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA288 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x124++0x03
hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x128++0x03
line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA350 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA349 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA348 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA347 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA346 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA344 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA343 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA342 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA341 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA340 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA338 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA337 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA336 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA335 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA334 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA332 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA331 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA330 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA329 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA328 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA326 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA325 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA324 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA323 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA322 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA320 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x128++0x03
hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x12C++0x03
line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA382 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA381 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA380 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA379 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA378 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA376 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA375 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA374 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA373 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA372 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA370 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA369 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA368 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA367 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA366 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA364 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA363 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA362 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA361 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA360 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA358 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA357 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA356 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA355 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA354 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA352 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x12C++0x03
hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x130++0x03
line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA414 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA413 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA412 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA411 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA410 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA408 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA407 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA406 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA405 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA404 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA402 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA401 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA400 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA399 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA398 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA396 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA395 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA394 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA393 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA392 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA390 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA389 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA388 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA387 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA386 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA384 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x130++0x03
hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x134++0x03
line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA446 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA445 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA444 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA443 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA442 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA440 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA439 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA438 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA437 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA436 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA434 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA433 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA432 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA431 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA430 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA428 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA427 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA426 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA425 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA424 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA422 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA421 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA420 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA419 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA418 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA416 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x134++0x03
hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x138++0x03
line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA478 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA477 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA476 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA475 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA474 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA472 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA471 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA470 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA469 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA468 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA466 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA465 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA464 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA463 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA462 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA460 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA459 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA458 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA457 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA456 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA454 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA453 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA452 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA451 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA450 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA448 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x138++0x03
hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x13C++0x03
line.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA511 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA510 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA509 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA508 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA507 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA506 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA505 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA504 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA503 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA502 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA501 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA500 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA499 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA498 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA497 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA496 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA495 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA494 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA493 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA492 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA491 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA490 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA489 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA488 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA487 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA486 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA485 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA484 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA483 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA482 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA481 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA480 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x13C++0x03
hide.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
width 24.
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x204++0x03
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x204++0x03
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x208++0x03
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x208++0x03
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x20C++0x03
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x20C++0x03
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x210++0x03
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x210++0x03
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x214++0x03
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x214++0x03
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x218++0x03
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x218++0x03
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x21C++0x03
line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN254 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN253 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN252 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN251 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN250 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN248 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN247 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN246 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN245 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN244 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN242 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN241 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN240 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x21C++0x03
hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x220++0x03
line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN286 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN285 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN284 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN283 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN282 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN280 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN279 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN278 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN277 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN276 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN274 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN273 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN272 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN271 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN270 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN268 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN267 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN266 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN265 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN264 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN262 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN261 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN260 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN259 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN258 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN256 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x220++0x03
hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x224++0x03
line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN318 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN317 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN316 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN315 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN314 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN312 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN311 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN310 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN309 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN308 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN306 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN305 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN304 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN303 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN302 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN300 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN299 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN298 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN297 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN296 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN294 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN293 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN292 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN291 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN290 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN288 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x224++0x03
hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x228++0x03
line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN350 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN349 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN348 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN347 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN346 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN344 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN343 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN342 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN341 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN340 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN338 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN337 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN336 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN335 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN334 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN332 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN331 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN330 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN329 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN328 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN326 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN325 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN324 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN323 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN322 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN320 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x228++0x03
hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x22C++0x03
line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN382 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN381 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN380 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN379 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN378 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN376 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN375 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN374 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN373 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN372 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN370 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN369 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN368 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN367 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN366 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN364 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN363 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN362 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN361 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN360 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN358 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN357 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN356 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN355 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN354 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN352 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x22C++0x03
hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x230++0x03
line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN414 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN413 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN412 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN411 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN410 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN408 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN407 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN406 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN405 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN404 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN402 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN401 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN400 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN399 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN398 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN396 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN395 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN394 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN393 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN392 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN390 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN389 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN388 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN387 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN386 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN384 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x230++0x03
hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x234++0x03
line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN446 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN445 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN444 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN443 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN442 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN440 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN439 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN438 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN437 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN436 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN434 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN433 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN432 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN431 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN430 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN428 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN427 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN426 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN425 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN424 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN422 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN421 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN420 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN419 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN418 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN416 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x234++0x03
hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x238++0x03
line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN478 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN477 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN476 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN475 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN474 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN472 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN471 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN470 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN469 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN468 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN466 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN465 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN464 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN463 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN462 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN460 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN459 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN458 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN457 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN456 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN454 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN453 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN452 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN451 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN450 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN448 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x238++0x03
hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x23C++0x03
line.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN511 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN510 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN509 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN508 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN507 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN506 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN505 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN504 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN503 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN502 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN501 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN500 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN499 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN498 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN497 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN496 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN495 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN494 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN493 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN492 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN491 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN490 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN489 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN488 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN487 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN486 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN485 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN484 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN483 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN482 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN481 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN480 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x23C++0x03
hide.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
width 11.
tree "Interrupt Active Bit Registers"
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE0,Active Bit Register 0"
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
rgroup.long 0x304++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x304++0x03
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
rgroup.long 0x308++0x03
line.long 0x00 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x308++0x03
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
rgroup.long 0x30C++0x03
line.long 0x00 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x30C++0x03
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
rgroup.long 0x310++0x03
line.long 0x00 "ACTIVE4,Active Bit Register 4"
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x310++0x03
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
rgroup.long 0x314++0x03
line.long 0x00 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x314++0x03
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
rgroup.long 0x318++0x03
line.long 0x00 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x318++0x03
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
rgroup.long 0x31C++0x03
line.long 0x00 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x00 31. " ACTIVE255 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE254 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE253 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE252 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE251 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE250 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE249 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE248 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE247 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE246 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE245 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE244 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE243 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE242 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE241 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE240 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x31C++0x03
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
rgroup.long 0x320++0x03
line.long 0x00 "ACTIVE8,Active Bit Register 8"
bitfld.long 0x00 31. " ACTIVE287 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE286 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE285 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE284 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE283 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE282 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE281 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE280 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE279 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE278 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE277 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE276 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE275 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE274 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE273 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE272 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE271 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE270 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE269 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE268 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE267 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE266 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE265 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE264 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE263 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE262 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE261 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE260 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE259 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE258 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE257 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE256 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x320++0x03
hide.long 0x00 "ACTIVE8,Active Bit Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
rgroup.long 0x324++0x03
line.long 0x00 "ACTIVE9,Active Bit Register 9"
bitfld.long 0x00 31. " ACTIVE319 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE318 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE317 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE316 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE315 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE314 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE313 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE312 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE311 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE310 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE309 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE308 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE307 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE306 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE305 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE304 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE303 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE302 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE301 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE300 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE299 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE298 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE297 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE296 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE295 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE294 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE293 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE292 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE291 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE290 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE289 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE288 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x324++0x03
hide.long 0x00 "ACTIVE9,Active Bit Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
rgroup.long 0x328++0x03
line.long 0x00 "ACTIVE10,Active Bit Register 10"
bitfld.long 0x00 31. " ACTIVE351 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE350 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE349 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE348 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE347 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE346 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE345 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE344 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE343 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE342 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE341 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE340 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE339 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE338 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE337 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE336 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE335 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE334 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE333 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE332 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE331 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE330 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE329 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE328 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE327 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE326 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE325 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE324 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE323 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE322 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE321 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE320 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x328++0x03
hide.long 0x00 "ACTIVE10,Active Bit Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
rgroup.long 0x32C++0x03
line.long 0x00 "ACTIVE11,Active Bit Register 11"
bitfld.long 0x00 31. " ACTIVE383 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE382 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE381 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE380 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE379 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE378 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE377 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE376 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE375 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE374 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE373 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE372 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE371 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE370 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE369 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE368 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE367 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE366 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE365 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE364 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE363 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE362 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE361 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE360 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE359 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE358 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE357 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE356 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE355 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE354 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE353 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE352 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x32C++0x03
hide.long 0x00 "ACTIVE11,Active Bit Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
rgroup.long 0x330++0x03
line.long 0x00 "ACTIVE12,Active Bit Register 12"
bitfld.long 0x00 31. " ACTIVE415 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE414 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE413 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE412 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE411 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE410 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE409 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE408 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE407 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE406 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE405 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE404 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE403 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE402 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE401 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE400 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE399 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE398 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE397 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE396 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE395 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE394 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE393 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE392 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE391 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE390 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE389 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE388 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE387 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE386 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE385 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE384 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x330++0x03
hide.long 0x00 "ACTIVE12,Active Bit Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
rgroup.long 0x334++0x03
line.long 0x00 "ACTIVE13,Active Bit Register 13"
bitfld.long 0x00 31. " ACTIVE447 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE446 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE445 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE444 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE443 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE442 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE441 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE440 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE439 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE438 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE437 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE436 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE435 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE434 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE433 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE432 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE431 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE430 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE429 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE428 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE427 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE426 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE425 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE424 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE423 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE422 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE421 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE420 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE419 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE418 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE417 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE416 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x334++0x03
hide.long 0x00 "ACTIVE13,Active Bit Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
rgroup.long 0x338++0x03
line.long 0x00 "ACTIVE14,Active Bit Register 14"
bitfld.long 0x00 31. " ACTIVE479 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE478 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE477 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE476 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE475 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE474 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE473 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE472 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE471 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE470 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE469 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE468 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE467 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE466 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE465 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE464 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE463 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE462 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE461 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE460 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE459 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE458 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE457 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE456 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE455 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE454 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE453 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE452 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE451 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE450 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE449 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE448 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x338++0x03
hide.long 0x00 "ACTIVE14,Active Bit Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
rgroup.long 0x33C++0x03
line.long 0x00 "ACTIVE15,Active Bit Register 15"
bitfld.long 0x00 31. " ACTIVE511 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE510 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE509 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE508 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE507 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE506 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE505 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE504 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE503 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE502 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE501 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE500 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE499 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE498 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE497 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE496 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE495 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE494 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE493 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE492 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE491 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE490 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE489 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE488 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE487 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE486 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE485 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE484 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE483 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE482 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE481 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE480 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x33C++0x03
hide.long 0x00 "ACTIVE15,Active Bit Register 15"
endif
tree.end
width 13.
tree "Interrupt Target Non-Secure Registers"
group.long 0x380++0x03
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x384++0x03
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
else
hgroup.long 0x384++0x03
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x388++0x03
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
else
hgroup.long 0x388++0x03
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x38C++0x03
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
else
hgroup.long 0x38C++0x03
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x390++0x03
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
else
hgroup.long 0x390++0x03
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x394++0x03
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
else
hgroup.long 0x394++0x03
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x398++0x03
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
else
hgroup.long 0x398++0x03
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x39C++0x03
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
bitfld.long 0x00 31. " ITNS255 ,Interrupt Targets Non-secure 255" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS254 ,Interrupt Targets Non-secure 254" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS253 ,Interrupt Targets Non-secure 253" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS252 ,Interrupt Targets Non-secure 252" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS251 ,Interrupt Targets Non-secure 251" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS250 ,Interrupt Targets Non-secure 250" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS249 ,Interrupt Targets Non-secure 249" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS248 ,Interrupt Targets Non-secure 248" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS247 ,Interrupt Targets Non-secure 247" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS246 ,Interrupt Targets Non-secure 246" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS245 ,Interrupt Targets Non-secure 245" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS244 ,Interrupt Targets Non-secure 244" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS243 ,Interrupt Targets Non-secure 243" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS242 ,Interrupt Targets Non-secure 242" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS241 ,Interrupt Targets Non-secure 241" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS240 ,Interrupt Targets Non-secure 240" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
else
hgroup.long 0x39C++0x03
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x3A0++0x03
line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
bitfld.long 0x00 31. " ITNS287 ,Interrupt Targets Non-secure 287" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS286 ,Interrupt Targets Non-secure 286" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS285 ,Interrupt Targets Non-secure 285" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS284 ,Interrupt Targets Non-secure 284" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS283 ,Interrupt Targets Non-secure 283" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS282 ,Interrupt Targets Non-secure 282" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS281 ,Interrupt Targets Non-secure 281" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS280 ,Interrupt Targets Non-secure 280" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS279 ,Interrupt Targets Non-secure 279" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS278 ,Interrupt Targets Non-secure 278" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS277 ,Interrupt Targets Non-secure 277" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS276 ,Interrupt Targets Non-secure 276" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS275 ,Interrupt Targets Non-secure 275" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS274 ,Interrupt Targets Non-secure 274" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS273 ,Interrupt Targets Non-secure 273" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS272 ,Interrupt Targets Non-secure 272" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS271 ,Interrupt Targets Non-secure 271" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS270 ,Interrupt Targets Non-secure 270" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS269 ,Interrupt Targets Non-secure 269" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS268 ,Interrupt Targets Non-secure 268" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS267 ,Interrupt Targets Non-secure 267" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS266 ,Interrupt Targets Non-secure 266" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS265 ,Interrupt Targets Non-secure 265" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS264 ,Interrupt Targets Non-secure 264" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS263 ,Interrupt Targets Non-secure 263" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS262 ,Interrupt Targets Non-secure 262" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS261 ,Interrupt Targets Non-secure 261" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS260 ,Interrupt Targets Non-secure 260" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS259 ,Interrupt Targets Non-secure 259" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS258 ,Interrupt Targets Non-secure 258" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS257 ,Interrupt Targets Non-secure 257" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS256 ,Interrupt Targets Non-secure 256" "Secure,Non-secure"
else
hgroup.long 0x3A0++0x03
hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x3A4++0x03
line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
bitfld.long 0x00 31. " ITNS319 ,Interrupt Targets Non-secure 319" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS318 ,Interrupt Targets Non-secure 318" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS317 ,Interrupt Targets Non-secure 317" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS316 ,Interrupt Targets Non-secure 316" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS315 ,Interrupt Targets Non-secure 315" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS314 ,Interrupt Targets Non-secure 314" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS313 ,Interrupt Targets Non-secure 313" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS312 ,Interrupt Targets Non-secure 312" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS311 ,Interrupt Targets Non-secure 311" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS310 ,Interrupt Targets Non-secure 310" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS309 ,Interrupt Targets Non-secure 309" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS308 ,Interrupt Targets Non-secure 308" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS307 ,Interrupt Targets Non-secure 307" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS306 ,Interrupt Targets Non-secure 306" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS305 ,Interrupt Targets Non-secure 305" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS304 ,Interrupt Targets Non-secure 304" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS303 ,Interrupt Targets Non-secure 303" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS302 ,Interrupt Targets Non-secure 302" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS301 ,Interrupt Targets Non-secure 301" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS300 ,Interrupt Targets Non-secure 300" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS299 ,Interrupt Targets Non-secure 299" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS298 ,Interrupt Targets Non-secure 298" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS297 ,Interrupt Targets Non-secure 297" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS296 ,Interrupt Targets Non-secure 296" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS295 ,Interrupt Targets Non-secure 295" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS294 ,Interrupt Targets Non-secure 294" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS293 ,Interrupt Targets Non-secure 293" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS292 ,Interrupt Targets Non-secure 292" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS291 ,Interrupt Targets Non-secure 291" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS290 ,Interrupt Targets Non-secure 290" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS289 ,Interrupt Targets Non-secure 289" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS288 ,Interrupt Targets Non-secure 288" "Secure,Non-secure"
else
hgroup.long 0x3A4++0x03
hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x3A8++0x03
line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
bitfld.long 0x00 31. " ITNS351 ,Interrupt Targets Non-secure 351" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS350 ,Interrupt Targets Non-secure 350" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS349 ,Interrupt Targets Non-secure 349" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS348 ,Interrupt Targets Non-secure 348" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS347 ,Interrupt Targets Non-secure 347" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS346 ,Interrupt Targets Non-secure 346" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS345 ,Interrupt Targets Non-secure 345" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS344 ,Interrupt Targets Non-secure 344" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS343 ,Interrupt Targets Non-secure 343" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS342 ,Interrupt Targets Non-secure 342" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS341 ,Interrupt Targets Non-secure 341" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS340 ,Interrupt Targets Non-secure 340" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS339 ,Interrupt Targets Non-secure 339" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS338 ,Interrupt Targets Non-secure 338" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS337 ,Interrupt Targets Non-secure 337" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS336 ,Interrupt Targets Non-secure 336" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS335 ,Interrupt Targets Non-secure 335" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS334 ,Interrupt Targets Non-secure 334" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS333 ,Interrupt Targets Non-secure 333" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS332 ,Interrupt Targets Non-secure 332" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS331 ,Interrupt Targets Non-secure 331" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS330 ,Interrupt Targets Non-secure 330" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS329 ,Interrupt Targets Non-secure 329" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS328 ,Interrupt Targets Non-secure 328" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS327 ,Interrupt Targets Non-secure 327" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS326 ,Interrupt Targets Non-secure 326" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS325 ,Interrupt Targets Non-secure 325" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS324 ,Interrupt Targets Non-secure 324" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS323 ,Interrupt Targets Non-secure 323" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS322 ,Interrupt Targets Non-secure 322" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS321 ,Interrupt Targets Non-secure 321" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS320 ,Interrupt Targets Non-secure 320" "Secure,Non-secure"
else
hgroup.long 0x3A8++0x03
hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x3AC++0x03
line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
bitfld.long 0x00 31. " ITNS383 ,Interrupt Targets Non-secure 383" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS382 ,Interrupt Targets Non-secure 382" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS381 ,Interrupt Targets Non-secure 381" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS380 ,Interrupt Targets Non-secure 380" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS379 ,Interrupt Targets Non-secure 379" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS378 ,Interrupt Targets Non-secure 378" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS377 ,Interrupt Targets Non-secure 377" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS376 ,Interrupt Targets Non-secure 376" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS375 ,Interrupt Targets Non-secure 375" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS374 ,Interrupt Targets Non-secure 374" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS373 ,Interrupt Targets Non-secure 373" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS372 ,Interrupt Targets Non-secure 372" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS371 ,Interrupt Targets Non-secure 371" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS370 ,Interrupt Targets Non-secure 370" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS369 ,Interrupt Targets Non-secure 369" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS368 ,Interrupt Targets Non-secure 368" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS367 ,Interrupt Targets Non-secure 367" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS366 ,Interrupt Targets Non-secure 366" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS365 ,Interrupt Targets Non-secure 365" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS364 ,Interrupt Targets Non-secure 364" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS363 ,Interrupt Targets Non-secure 363" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS362 ,Interrupt Targets Non-secure 362" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS361 ,Interrupt Targets Non-secure 361" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS360 ,Interrupt Targets Non-secure 360" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS359 ,Interrupt Targets Non-secure 359" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS358 ,Interrupt Targets Non-secure 358" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS357 ,Interrupt Targets Non-secure 357" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS356 ,Interrupt Targets Non-secure 356" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS355 ,Interrupt Targets Non-secure 355" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS354 ,Interrupt Targets Non-secure 354" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS353 ,Interrupt Targets Non-secure 353" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS352 ,Interrupt Targets Non-secure 352" "Secure,Non-secure"
else
hgroup.long 0x3AC++0x03
hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x3B0++0x03
line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
bitfld.long 0x00 31. " ITNS415 ,Interrupt Targets Non-secure 415" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS414 ,Interrupt Targets Non-secure 414" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS413 ,Interrupt Targets Non-secure 413" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS412 ,Interrupt Targets Non-secure 412" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS411 ,Interrupt Targets Non-secure 411" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS410 ,Interrupt Targets Non-secure 410" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS409 ,Interrupt Targets Non-secure 409" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS408 ,Interrupt Targets Non-secure 408" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS407 ,Interrupt Targets Non-secure 407" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS406 ,Interrupt Targets Non-secure 406" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS405 ,Interrupt Targets Non-secure 405" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS404 ,Interrupt Targets Non-secure 404" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS403 ,Interrupt Targets Non-secure 403" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS402 ,Interrupt Targets Non-secure 402" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS401 ,Interrupt Targets Non-secure 401" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS400 ,Interrupt Targets Non-secure 400" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS399 ,Interrupt Targets Non-secure 399" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS398 ,Interrupt Targets Non-secure 398" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS397 ,Interrupt Targets Non-secure 397" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS396 ,Interrupt Targets Non-secure 396" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS395 ,Interrupt Targets Non-secure 395" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS394 ,Interrupt Targets Non-secure 394" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS393 ,Interrupt Targets Non-secure 393" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS392 ,Interrupt Targets Non-secure 392" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS391 ,Interrupt Targets Non-secure 391" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS390 ,Interrupt Targets Non-secure 390" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS389 ,Interrupt Targets Non-secure 389" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS388 ,Interrupt Targets Non-secure 388" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS387 ,Interrupt Targets Non-secure 387" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS386 ,Interrupt Targets Non-secure 386" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS385 ,Interrupt Targets Non-secure 385" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS384 ,Interrupt Targets Non-secure 384" "Secure,Non-secure"
else
hgroup.long 0x3B0++0x03
hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x3B4++0x03
line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
bitfld.long 0x00 31. " ITNS447 ,Interrupt Targets Non-secure 447" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS446 ,Interrupt Targets Non-secure 446" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS445 ,Interrupt Targets Non-secure 445" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS444 ,Interrupt Targets Non-secure 444" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS443 ,Interrupt Targets Non-secure 443" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS442 ,Interrupt Targets Non-secure 442" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS441 ,Interrupt Targets Non-secure 441" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS440 ,Interrupt Targets Non-secure 440" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS439 ,Interrupt Targets Non-secure 439" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS438 ,Interrupt Targets Non-secure 438" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS437 ,Interrupt Targets Non-secure 437" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS436 ,Interrupt Targets Non-secure 436" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS435 ,Interrupt Targets Non-secure 435" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS434 ,Interrupt Targets Non-secure 434" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS433 ,Interrupt Targets Non-secure 433" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS432 ,Interrupt Targets Non-secure 432" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS431 ,Interrupt Targets Non-secure 431" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS430 ,Interrupt Targets Non-secure 430" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS429 ,Interrupt Targets Non-secure 429" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS428 ,Interrupt Targets Non-secure 428" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS427 ,Interrupt Targets Non-secure 427" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS426 ,Interrupt Targets Non-secure 426" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS425 ,Interrupt Targets Non-secure 425" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS424 ,Interrupt Targets Non-secure 424" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS423 ,Interrupt Targets Non-secure 423" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS422 ,Interrupt Targets Non-secure 422" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS421 ,Interrupt Targets Non-secure 421" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS420 ,Interrupt Targets Non-secure 420" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS419 ,Interrupt Targets Non-secure 419" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS418 ,Interrupt Targets Non-secure 418" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS417 ,Interrupt Targets Non-secure 417" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS416 ,Interrupt Targets Non-secure 416" "Secure,Non-secure"
else
hgroup.long 0x3B4++0x03
hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x3B8++0x03
line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
bitfld.long 0x00 31. " ITNS479 ,Interrupt Targets Non-secure 479" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS478 ,Interrupt Targets Non-secure 478" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS477 ,Interrupt Targets Non-secure 477" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS476 ,Interrupt Targets Non-secure 476" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS475 ,Interrupt Targets Non-secure 475" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS474 ,Interrupt Targets Non-secure 474" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS473 ,Interrupt Targets Non-secure 473" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS472 ,Interrupt Targets Non-secure 472" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS471 ,Interrupt Targets Non-secure 471" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS470 ,Interrupt Targets Non-secure 470" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS469 ,Interrupt Targets Non-secure 469" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS468 ,Interrupt Targets Non-secure 468" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS467 ,Interrupt Targets Non-secure 467" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS466 ,Interrupt Targets Non-secure 466" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS465 ,Interrupt Targets Non-secure 465" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS464 ,Interrupt Targets Non-secure 464" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS463 ,Interrupt Targets Non-secure 463" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS462 ,Interrupt Targets Non-secure 462" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS461 ,Interrupt Targets Non-secure 461" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS460 ,Interrupt Targets Non-secure 460" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS459 ,Interrupt Targets Non-secure 459" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS458 ,Interrupt Targets Non-secure 458" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS457 ,Interrupt Targets Non-secure 457" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS456 ,Interrupt Targets Non-secure 456" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS455 ,Interrupt Targets Non-secure 455" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS454 ,Interrupt Targets Non-secure 454" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS453 ,Interrupt Targets Non-secure 453" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS452 ,Interrupt Targets Non-secure 452" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS451 ,Interrupt Targets Non-secure 451" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS450 ,Interrupt Targets Non-secure 450" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS449 ,Interrupt Targets Non-secure 449" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS448 ,Interrupt Targets Non-secure 448" "Secure,Non-secure"
else
hgroup.long 0x3B8++0x03
hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x0F)
group.long 0x3BC++0x03
line.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
bitfld.long 0x00 31. " ITNS511 ,Interrupt Targets Non-secure 511" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS510 ,Interrupt Targets Non-secure 510" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS509 ,Interrupt Targets Non-secure 509" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS508 ,Interrupt Targets Non-secure 508" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS507 ,Interrupt Targets Non-secure 507" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS506 ,Interrupt Targets Non-secure 506" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS505 ,Interrupt Targets Non-secure 505" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS504 ,Interrupt Targets Non-secure 504" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS503 ,Interrupt Targets Non-secure 503" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS502 ,Interrupt Targets Non-secure 502" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS501 ,Interrupt Targets Non-secure 501" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS500 ,Interrupt Targets Non-secure 500" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS499 ,Interrupt Targets Non-secure 499" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS498 ,Interrupt Targets Non-secure 498" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS497 ,Interrupt Targets Non-secure 497" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS496 ,Interrupt Targets Non-secure 496" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS495 ,Interrupt Targets Non-secure 495" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS494 ,Interrupt Targets Non-secure 494" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS493 ,Interrupt Targets Non-secure 493" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS492 ,Interrupt Targets Non-secure 492" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS491 ,Interrupt Targets Non-secure 491" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS490 ,Interrupt Targets Non-secure 490" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS489 ,Interrupt Targets Non-secure 489" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS488 ,Interrupt Targets Non-secure 488" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS487 ,Interrupt Targets Non-secure 487" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS486 ,Interrupt Targets Non-secure 486" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS485 ,Interrupt Targets Non-secure 485" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS484 ,Interrupt Targets Non-secure 484" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS483 ,Interrupt Targets Non-secure 483" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS482 ,Interrupt Targets Non-secure 482" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS481 ,Interrupt Targets Non-secure 481" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS480 ,Interrupt Targets Non-secure 480" "Secure,Non-secure"
else
hgroup.long 0x3BC++0x03
hide.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
endif
tree.end
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x420++0x1F
line.long 0x0 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
line.long 0x4 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
line.long 0x8 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
line.long 0xC "IPR11,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
line.long 0x10 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
line.long 0x14 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
line.long 0x18 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
line.long 0x1C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
else
hgroup.long 0x420++0x1F
hide.long 0x0 "IPR8,Interrupt Priority Register"
hide.long 0x4 "IPR9,Interrupt Priority Register"
hide.long 0x8 "IPR10,Interrupt Priority Register"
hide.long 0xC "IPR11,Interrupt Priority Register"
hide.long 0x10 "IPR12,Interrupt Priority Register"
hide.long 0x14 "IPR13,Interrupt Priority Register"
hide.long 0x18 "IPR14,Interrupt Priority Register"
hide.long 0x1C "IPR15,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x440++0x1F
line.long 0x0 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
line.long 0x4 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
line.long 0x8 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
line.long 0xC "IPR19,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
line.long 0x10 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
line.long 0x14 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
line.long 0x18 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
line.long 0x1C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
else
hgroup.long 0x440++0x1F
hide.long 0x0 "IPR16,Interrupt Priority Register"
hide.long 0x4 "IPR17,Interrupt Priority Register"
hide.long 0x8 "IPR18,Interrupt Priority Register"
hide.long 0xC "IPR19,Interrupt Priority Register"
hide.long 0x10 "IPR20,Interrupt Priority Register"
hide.long 0x14 "IPR21,Interrupt Priority Register"
hide.long 0x18 "IPR22,Interrupt Priority Register"
hide.long 0x1C "IPR23,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x460++0x1F
line.long 0x0 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
line.long 0x4 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
line.long 0x8 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
line.long 0xC "IPR27,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
line.long 0x10 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
line.long 0x14 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
line.long 0x18 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
line.long 0x1C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
else
hgroup.long 0x460++0x1F
hide.long 0x0 "IPR24,Interrupt Priority Register"
hide.long 0x4 "IPR25,Interrupt Priority Register"
hide.long 0x8 "IPR26,Interrupt Priority Register"
hide.long 0xC "IPR27,Interrupt Priority Register"
hide.long 0x10 "IPR28,Interrupt Priority Register"
hide.long 0x14 "IPR29,Interrupt Priority Register"
hide.long 0x18 "IPR30,Interrupt Priority Register"
hide.long 0x1C "IPR31,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x480++0x1F
line.long 0x0 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
line.long 0x4 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
line.long 0x8 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
line.long 0xC "IPR35,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
line.long 0x10 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
line.long 0x14 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
line.long 0x18 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
line.long 0x1C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
else
hgroup.long 0x480++0x1F
hide.long 0x0 "IPR32,Interrupt Priority Register"
hide.long 0x4 "IPR33,Interrupt Priority Register"
hide.long 0x8 "IPR34,Interrupt Priority Register"
hide.long 0xC "IPR35,Interrupt Priority Register"
hide.long 0x10 "IPR36,Interrupt Priority Register"
hide.long 0x14 "IPR37,Interrupt Priority Register"
hide.long 0x18 "IPR38,Interrupt Priority Register"
hide.long 0x1C "IPR39,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x4A0++0x1F
line.long 0x0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
line.long 0x4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
line.long 0x8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
line.long 0xC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
line.long 0x10 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
line.long 0x14 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
line.long 0x18 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
line.long 0x1C "IPR47,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
else
hgroup.long 0x4A0++0x1F
hide.long 0x0 "IPR40,Interrupt Priority Register"
hide.long 0x4 "IPR41,Interrupt Priority Register"
hide.long 0x8 "IPR42,Interrupt Priority Register"
hide.long 0xC "IPR43,Interrupt Priority Register"
hide.long 0x10 "IPR44,Interrupt Priority Register"
hide.long 0x14 "IPR45,Interrupt Priority Register"
hide.long 0x18 "IPR46,Interrupt Priority Register"
hide.long 0x1C "IPR47,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x4C0++0x1F
line.long 0x0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
line.long 0x4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
line.long 0x8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
line.long 0xC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
line.long 0x10 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
line.long 0x14 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
line.long 0x18 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
line.long 0x1C "IPR55,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
else
hgroup.long 0x4C0++0x1F
hide.long 0x0 "IPR48,Interrupt Priority Register"
hide.long 0x4 "IPR49,Interrupt Priority Register"
hide.long 0x8 "IPR50,Interrupt Priority Register"
hide.long 0xC "IPR51,Interrupt Priority Register"
hide.long 0x10 "IPR52,Interrupt Priority Register"
hide.long 0x14 "IPR53,Interrupt Priority Register"
hide.long 0x18 "IPR54,Interrupt Priority Register"
hide.long 0x1C "IPR55,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x4E0++0x1F
line.long 0x0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
line.long 0x4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
line.long 0x8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
line.long 0xC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
line.long 0x10 "IPR60,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_243 ,Interrupt 243 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_242 ,Interrupt 242 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_241 ,Interrupt 241 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_240 ,Interrupt 240 Priority"
line.long 0x14 "IPR61,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_247 ,Interrupt 247 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_246 ,Interrupt 246 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_245 ,Interrupt 245 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_244 ,Interrupt 244 Priority"
line.long 0x18 "IPR62,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_251 ,Interrupt 251 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_250 ,Interrupt 250 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_249 ,Interrupt 249 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_248 ,Interrupt 248 Priority"
line.long 0x1C "IPR63,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_255 ,Interrupt 255 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_254 ,Interrupt 254 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_253 ,Interrupt 253 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_252 ,Interrupt 252 Priority"
else
hgroup.long 0x4E0++0x1F
hide.long 0x0 "IPR56,Interrupt Priority Register"
hide.long 0x4 "IPR57,Interrupt Priority Register"
hide.long 0x8 "IPR58,Interrupt Priority Register"
hide.long 0xC "IPR59,Interrupt Priority Register"
hide.long 0x10 "IPR60,Interrupt Priority Register"
hide.long 0x14 "IPR61,Interrupt Priority Register"
hide.long 0x18 "IPR62,Interrupt Priority Register"
hide.long 0x1C "IPR63,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x500++0x1F
line.long 0x0 "IPR64,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_259 ,Interrupt 259 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_258 ,Interrupt 258 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_257 ,Interrupt 257 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_256 ,Interrupt 256 Priority"
line.long 0x4 "IPR65,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_263 ,Interrupt 263 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_262 ,Interrupt 262 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_261 ,Interrupt 261 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_260 ,Interrupt 260 Priority"
line.long 0x8 "IPR66,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_267 ,Interrupt 267 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_266 ,Interrupt 266 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_265 ,Interrupt 265 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_264 ,Interrupt 264 Priority"
line.long 0xC "IPR67,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_271 ,Interrupt 271 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_270 ,Interrupt 270 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_269 ,Interrupt 269 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_268 ,Interrupt 268 Priority"
line.long 0x10 "IPR68,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_275 ,Interrupt 275 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_274 ,Interrupt 274 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_273 ,Interrupt 273 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_272 ,Interrupt 272 Priority"
line.long 0x14 "IPR69,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_279 ,Interrupt 279 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_278 ,Interrupt 278 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_277 ,Interrupt 277 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_276 ,Interrupt 276 Priority"
line.long 0x18 "IPR70,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_283 ,Interrupt 283 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_282 ,Interrupt 282 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_281 ,Interrupt 281 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_280 ,Interrupt 280 Priority"
line.long 0x1C "IPR71,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_287 ,Interrupt 287 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_286 ,Interrupt 286 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_285 ,Interrupt 285 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_284 ,Interrupt 284 Priority"
else
hgroup.long 0x500++0x1F
hide.long 0x0 "IPR64,Interrupt Priority Register"
hide.long 0x4 "IPR65,Interrupt Priority Register"
hide.long 0x8 "IPR66,Interrupt Priority Register"
hide.long 0xC "IPR67,Interrupt Priority Register"
hide.long 0x10 "IPR68,Interrupt Priority Register"
hide.long 0x14 "IPR69,Interrupt Priority Register"
hide.long 0x18 "IPR70,Interrupt Priority Register"
hide.long 0x1C "IPR71,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x520++0x1F
line.long 0x0 "IPR72,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_291 ,Interrupt 291 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_290 ,Interrupt 290 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_289 ,Interrupt 289 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_288 ,Interrupt 288 Priority"
line.long 0x4 "IPR73,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_295 ,Interrupt 295 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_294 ,Interrupt 294 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_293 ,Interrupt 293 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_292 ,Interrupt 292 Priority"
line.long 0x8 "IPR74,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_299 ,Interrupt 299 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_298 ,Interrupt 298 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_297 ,Interrupt 297 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_296 ,Interrupt 296 Priority"
line.long 0xC "IPR75,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_303 ,Interrupt 303 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_302 ,Interrupt 302 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_301 ,Interrupt 301 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_300 ,Interrupt 300 Priority"
line.long 0x10 "IPR76,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_307 ,Interrupt 307 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_306 ,Interrupt 306 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_305 ,Interrupt 305 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_304 ,Interrupt 304 Priority"
line.long 0x14 "IPR77,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_311 ,Interrupt 311 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_310 ,Interrupt 310 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_309 ,Interrupt 309 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_308 ,Interrupt 308 Priority"
line.long 0x18 "IPR78,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_315 ,Interrupt 315 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_314 ,Interrupt 314 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_313 ,Interrupt 313 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_312 ,Interrupt 312 Priority"
line.long 0x1C "IPR79,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_319 ,Interrupt 319 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_318 ,Interrupt 318 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_317 ,Interrupt 317 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_316 ,Interrupt 316 Priority"
else
hgroup.long 0x520++0x1F
hide.long 0x0 "IPR72,Interrupt Priority Register"
hide.long 0x4 "IPR73,Interrupt Priority Register"
hide.long 0x8 "IPR74,Interrupt Priority Register"
hide.long 0xC "IPR75,Interrupt Priority Register"
hide.long 0x10 "IPR76,Interrupt Priority Register"
hide.long 0x14 "IPR77,Interrupt Priority Register"
hide.long 0x18 "IPR78,Interrupt Priority Register"
hide.long 0x1C "IPR79,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x540++0x1F
line.long 0x0 "IPR80,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_323 ,Interrupt 323 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_322 ,Interrupt 322 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_321 ,Interrupt 321 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_320 ,Interrupt 320 Priority"
line.long 0x4 "IPR81,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_327 ,Interrupt 327 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_326 ,Interrupt 326 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_325 ,Interrupt 325 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_324 ,Interrupt 324 Priority"
line.long 0x8 "IPR82,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_331 ,Interrupt 331 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_330 ,Interrupt 330 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_329 ,Interrupt 329 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_328 ,Interrupt 328 Priority"
line.long 0xC "IPR83,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_335 ,Interrupt 335 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_334 ,Interrupt 334 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_333 ,Interrupt 333 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_332 ,Interrupt 332 Priority"
line.long 0x10 "IPR84,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_339 ,Interrupt 339 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_338 ,Interrupt 338 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_337 ,Interrupt 337 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_336 ,Interrupt 336 Priority"
line.long 0x14 "IPR85,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_343 ,Interrupt 343 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_342 ,Interrupt 342 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_341 ,Interrupt 341 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_340 ,Interrupt 340 Priority"
line.long 0x18 "IPR86,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_347 ,Interrupt 347 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_346 ,Interrupt 346 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_345 ,Interrupt 345 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_344 ,Interrupt 344 Priority"
line.long 0x1C "IPR87,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_351 ,Interrupt 351 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_350 ,Interrupt 350 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_349 ,Interrupt 349 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_348 ,Interrupt 348 Priority"
else
hgroup.long 0x540++0x1F
hide.long 0x0 "IPR80,Interrupt Priority Register"
hide.long 0x4 "IPR81,Interrupt Priority Register"
hide.long 0x8 "IPR82,Interrupt Priority Register"
hide.long 0xC "IPR83,Interrupt Priority Register"
hide.long 0x10 "IPR84,Interrupt Priority Register"
hide.long 0x14 "IPR85,Interrupt Priority Register"
hide.long 0x18 "IPR86,Interrupt Priority Register"
hide.long 0x1C "IPR87,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x560++0x1F
line.long 0x0 "IPR88,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_355 ,Interrupt 355 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_354 ,Interrupt 354 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_353 ,Interrupt 353 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_352 ,Interrupt 352 Priority"
line.long 0x4 "IPR89,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_359 ,Interrupt 359 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_358 ,Interrupt 358 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_357 ,Interrupt 357 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_356 ,Interrupt 356 Priority"
line.long 0x8 "IPR90,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_363 ,Interrupt 363 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_362 ,Interrupt 362 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_361 ,Interrupt 361 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_360 ,Interrupt 360 Priority"
line.long 0xC "IPR91,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_367 ,Interrupt 367 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_366 ,Interrupt 366 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_365 ,Interrupt 365 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_364 ,Interrupt 364 Priority"
line.long 0x10 "IPR92,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_371 ,Interrupt 371 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_370 ,Interrupt 370 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_369 ,Interrupt 369 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_368 ,Interrupt 368 Priority"
line.long 0x14 "IPR93,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_375 ,Interrupt 375 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_374 ,Interrupt 374 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_373 ,Interrupt 373 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_372 ,Interrupt 372 Priority"
line.long 0x18 "IPR94,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_379 ,Interrupt 379 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_378 ,Interrupt 378 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_377 ,Interrupt 377 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_376 ,Interrupt 376 Priority"
line.long 0x1C "IPR95,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_383 ,Interrupt 383 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_382 ,Interrupt 382 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_381 ,Interrupt 381 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_380 ,Interrupt 380 Priority"
else
hgroup.long 0x560++0x1F
hide.long 0x0 "IPR88,Interrupt Priority Register"
hide.long 0x4 "IPR89,Interrupt Priority Register"
hide.long 0x8 "IPR90,Interrupt Priority Register"
hide.long 0xC "IPR91,Interrupt Priority Register"
hide.long 0x10 "IPR92,Interrupt Priority Register"
hide.long 0x14 "IPR93,Interrupt Priority Register"
hide.long 0x18 "IPR94,Interrupt Priority Register"
hide.long 0x1C "IPR95,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x580++0x1F
line.long 0x0 "IPR96,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_387 ,Interrupt 387 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_386 ,Interrupt 386 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_385 ,Interrupt 385 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_384 ,Interrupt 384 Priority"
line.long 0x4 "IPR97,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_391 ,Interrupt 391 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_390 ,Interrupt 390 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_389 ,Interrupt 389 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_388 ,Interrupt 388 Priority"
line.long 0x8 "IPR98,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_395 ,Interrupt 395 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_394 ,Interrupt 394 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_393 ,Interrupt 393 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_392 ,Interrupt 392 Priority"
line.long 0xC "IPR99,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_399 ,Interrupt 399 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_398 ,Interrupt 398 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_397 ,Interrupt 397 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_396 ,Interrupt 396 Priority"
line.long 0x10 "IPR100,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_403 ,Interrupt 403 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_402 ,Interrupt 402 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_401 ,Interrupt 401 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_400 ,Interrupt 400 Priority"
line.long 0x14 "IPR101,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_407 ,Interrupt 407 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_406 ,Interrupt 406 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_405 ,Interrupt 405 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_404 ,Interrupt 404 Priority"
line.long 0x18 "IPR102,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_411 ,Interrupt 411 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_410 ,Interrupt 410 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_409 ,Interrupt 409 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_408 ,Interrupt 408 Priority"
line.long 0x1C "IPR103,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_415 ,Interrupt 415 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_414 ,Interrupt 414 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_413 ,Interrupt 413 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_412 ,Interrupt 412 Priority"
else
hgroup.long 0x580++0x1F
hide.long 0x0 "IPR96,Interrupt Priority Register"
hide.long 0x4 "IPR97,Interrupt Priority Register"
hide.long 0x8 "IPR98,Interrupt Priority Register"
hide.long 0xC "IPR99,Interrupt Priority Register"
hide.long 0x10 "IPR100,Interrupt Priority Register"
hide.long 0x14 "IPR101,Interrupt Priority Register"
hide.long 0x18 "IPR102,Interrupt Priority Register"
hide.long 0x1C "IPR103,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x5A0++0x1F
line.long 0x0 "IPR104,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_419 ,Interrupt 419 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_418 ,Interrupt 418 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_417 ,Interrupt 417 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_416 ,Interrupt 416 Priority"
line.long 0x4 "IPR105,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_423 ,Interrupt 423 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_422 ,Interrupt 422 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_421 ,Interrupt 421 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_420 ,Interrupt 420 Priority"
line.long 0x8 "IPR106,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_427 ,Interrupt 427 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_426 ,Interrupt 426 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_425 ,Interrupt 425 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_424 ,Interrupt 424 Priority"
line.long 0xC "IPR107,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_431 ,Interrupt 431 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_430 ,Interrupt 430 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_429 ,Interrupt 429 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_428 ,Interrupt 428 Priority"
line.long 0x10 "IPR108,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_435 ,Interrupt 435 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_434 ,Interrupt 434 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_433 ,Interrupt 433 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_432 ,Interrupt 432 Priority"
line.long 0x14 "IPR109,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_439 ,Interrupt 439 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_438 ,Interrupt 438 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_437 ,Interrupt 437 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_436 ,Interrupt 436 Priority"
line.long 0x18 "IPR110,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_443 ,Interrupt 443 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_442 ,Interrupt 442 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_441 ,Interrupt 441 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_440 ,Interrupt 440 Priority"
line.long 0x1C "IPR111,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_447 ,Interrupt 447 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_446 ,Interrupt 446 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_445 ,Interrupt 445 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_444 ,Interrupt 444 Priority"
else
hgroup.long 0x5A0++0x1F
hide.long 0x0 "IPR104,Interrupt Priority Register"
hide.long 0x4 "IPR105,Interrupt Priority Register"
hide.long 0x8 "IPR106,Interrupt Priority Register"
hide.long 0xC "IPR107,Interrupt Priority Register"
hide.long 0x10 "IPR108,Interrupt Priority Register"
hide.long 0x14 "IPR109,Interrupt Priority Register"
hide.long 0x18 "IPR110,Interrupt Priority Register"
hide.long 0x1C "IPR111,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x5C0++0x1F
line.long 0x0 "IPR112,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_451 ,Interrupt 451 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_450 ,Interrupt 450 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_449 ,Interrupt 449 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_448 ,Interrupt 448 Priority"
line.long 0x4 "IPR113,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_455 ,Interrupt 455 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_454 ,Interrupt 454 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_453 ,Interrupt 453 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_452 ,Interrupt 452 Priority"
line.long 0x8 "IPR114,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_459 ,Interrupt 459 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_458 ,Interrupt 458 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_457 ,Interrupt 457 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_456 ,Interrupt 456 Priority"
line.long 0xC "IPR115,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_463 ,Interrupt 463 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_462 ,Interrupt 462 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_461 ,Interrupt 461 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_460 ,Interrupt 460 Priority"
line.long 0x10 "IPR116,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_467 ,Interrupt 467 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_466 ,Interrupt 466 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_465 ,Interrupt 465 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_464 ,Interrupt 464 Priority"
line.long 0x14 "IPR117,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_471 ,Interrupt 471 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_470 ,Interrupt 470 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_469 ,Interrupt 469 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_468 ,Interrupt 468 Priority"
line.long 0x18 "IPR118,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_475 ,Interrupt 475 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_474 ,Interrupt 474 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_473 ,Interrupt 473 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_472 ,Interrupt 472 Priority"
line.long 0x1C "IPR119,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_479 ,Interrupt 479 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_478 ,Interrupt 478 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_477 ,Interrupt 477 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_476 ,Interrupt 476 Priority"
else
hgroup.long 0x5C0++0x1F
hide.long 0x0 "IPR112,Interrupt Priority Register"
hide.long 0x4 "IPR113,Interrupt Priority Register"
hide.long 0x8 "IPR114,Interrupt Priority Register"
hide.long 0xC "IPR115,Interrupt Priority Register"
hide.long 0x10 "IPR116,Interrupt Priority Register"
hide.long 0x14 "IPR117,Interrupt Priority Register"
hide.long 0x18 "IPR118,Interrupt Priority Register"
hide.long 0x1C "IPR119,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif (CORENAME()=="CORTEXM33F")
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 29. " LSPENS ,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "Writeable,Write ignored"
newline
bitfld.long 0x00 28. " CLRONRET ,Clear floating point caller saved registers on exception return" "Disabled,Enabled"
bitfld.long 0x00 27. " CLRONRETS ,Clear on return Secure only" "Both states,Secure only"
bitfld.long 0x00 26. " TS ,Treat as Secure" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " UFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the UsageFault exception to pending" "Not able,Able"
bitfld.long 0x00 9. " SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High"
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
newline
bitfld.long 0x00 7. " SFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able"
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
newline
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 2. " S ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure"
newline
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
newline
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x0B
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
newline
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
newline
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Fully denormalized,?..."
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 13.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
newline
group.long 0xE04++0x07
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
rgroup.long 0xFB8++0x03
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
newline
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 12.
group.long 0x00++0x03
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,?..."
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
textline " "
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x04))&0x20000000)==0x20000000)
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
hexmask.long 0x00 5.--28. 0x20 " REMAP ,Remap address"
else
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
tree "CoreSight Identification Registers"
width 12.
rgroup.long 0xFCC++0x03
line.long 0x00 "FP_DEVTYPE,FPB CoreSight Device Type Register"
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "FP_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "FP_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "FP_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "FP_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "FP_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "FP_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "FP_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 16.
group.long 0x00++0x03
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,?..."
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
textline " "
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline " "
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline " "
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x1000000)==0x0000000)
group.long 0x04++0x03
line.long 0x00 "DWT_CYCCNT,Cycle Count register"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x0000000)
group.long 0x08++0x17
line.long 0x00 "DWT_CPICNT,CPI Count register"
hexmask.long.byte 0x00 0.--7. 1. " CPICNT ,Base instruction overhead counter"
line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x04 0.--7. 1. " EXCCNT ,The exception overhead counter"
line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT ,Sleep Counter"
line.long 0x10 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x10 0.--7. 1. " LSUCNT ,Load-store overhead counter"
line.long 0x14 "DWT_FOLDCNT,Folded-instruction Count register"
hexmask.long.byte 0x14 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
endif
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline " "
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
endif
group.long (0x20+0x08)++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
endif
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
endif
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
endif
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
tree "CoreSight Identification Registers"
width 13.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFCC++0x03
line.long 0x00 "DWT_DEVTYPE,Device Type Identifier register"
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
rgroup.long 0xFE0++0x0F
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "DWT_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "DWT_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "DWT_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "ADC (Analog-to-Digital Converter)"
base ad:0x0
tree "ADC0"
base ad:0x50000000
group.long 0x0++0x53
line.long 0x0 "STAT,Status register"
bitfld.long 0x0 31. "WDE2,Analog watchdog 2 event flag" "0,1"
bitfld.long 0x0 30. "WDE1,Analog watchdog 1 event flag" "0,1"
bitfld.long 0x0 5. "ROVF,Routine data register overflow" "0,1"
bitfld.long 0x0 4. "STRC,Start flag of routine sequence" "0,1"
bitfld.long 0x0 3. "STIC,Start flag of inserted sequence" "0,1"
bitfld.long 0x0 2. "EOIC,End of inserted sequence conversion flag" "0,1"
bitfld.long 0x0 1. "EOC,End of sequence conversion flag" "0,1"
bitfld.long 0x0 0. "WDE0,Analog watchdog 0 event flag" "0,1"
line.long 0x4 "CTL0,Control register 0"
bitfld.long 0x4 31. "WDE2IE,Interrupt enable for WDE2" "0,1"
bitfld.long 0x4 30. "WDE1IE,Interrupt enable for WDE1" "0,1"
bitfld.long 0x4 26. "ROVFIE,Interrupt enable for ROVF" "0,1"
bitfld.long 0x4 24.--25. "DRES,ADC data resolution" "0,1,2,3"
bitfld.long 0x4 23. "RWD0EN,Routine channel analog watchdog 0 enable" "0,1"
bitfld.long 0x4 22. "IWD0EN,Inserted channel analog watchdog 0 enable" "0,1"
bitfld.long 0x4 13.--15. "DISNUM,Number of conversions in discontinuous mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 12. "DISIC,Discontinuous mode on inserted channels" "0,1"
newline
bitfld.long 0x4 11. "DISRC,Discontinuous mode on routine channels" "0,1"
bitfld.long 0x4 10. "ICA,Inserted sequence convert automatically" "0,1"
bitfld.long 0x4 9. "WD0SC,When in scan mode analog watchdog 0 is effective on a single channel" "0,1"
bitfld.long 0x4 8. "SM,Scan mode" "0,1"
bitfld.long 0x4 7. "EOICIE,Interrupt enable for EOIC" "0,1"
bitfld.long 0x4 6. "WDE0IE,Interrupt enable for WDE0" "0,1"
bitfld.long 0x4 5. "EOCIE,Interrupt enable for EOC" "0,1"
hexmask.long.byte 0x4 0.--4. 1. "WD0CHSEL,Analog watchdog 0 channel select"
line.long 0x8 "CTL1,Control register 1"
bitfld.long 0x8 30. "SWRCST,Software start on routine channel" "0,1"
bitfld.long 0x8 28.--29. "ETMRC,External trigger mode for routine channel" "0,1,2,3"
bitfld.long 0x8 27. "CALMOD,ADC calibration mode" "0,1"
bitfld.long 0x8 25. "VBATEN,This bit can be set or cleared by software in ADC0 and ADC2" "0,1"
bitfld.long 0x8 24. "INREFEN,This bit can be set or cleared by software in ADC0" "0,1"
bitfld.long 0x8 23. "TSVEN1,This bit can be set or cleared by software in ADC0" "0,1"
bitfld.long 0x8 22. "SWICST,Software start on inserted channel" "0,1"
bitfld.long 0x8 20.--21. "ETMIC,External trigger mode for inserted channel" "0,1,2,3"
newline
bitfld.long 0x8 18. "MVMC,Mean value mode Configuration" "0,1"
bitfld.long 0x8 17. "WAIEN,Weighted averaging in inserted sequence mean value mode enable" "0,1"
bitfld.long 0x8 16. "GAINEN,Gain mode enable" "0,1"
bitfld.long 0x8 12. "HPDFCFG,HPDF mode configuration" "0,1"
bitfld.long 0x8 11. "DAL,Data alignment" "0,1"
bitfld.long 0x8 10. "EOCM,End of conversion mode" "0,1"
bitfld.long 0x8 9. "DDM,DMA disable mode" "0,1"
bitfld.long 0x8 8. "DMA,DMA request enable" "0,1"
newline
bitfld.long 0x8 4.--6. "CALNUM,Calibration Times" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 3. "RSTCLB,Reset calibration" "0,1"
bitfld.long 0x8 2. "CLB,ADC calibration" "0,1"
bitfld.long 0x8 1. "CTN,Continuous mode" "0,1"
bitfld.long 0x8 0. "ADCON,ADC ON" "0,1"
line.long 0xC "IOFF0,Inserted channel data offset registe 0"
hexmask.long.tbyte 0xC 0.--23. 1. "IOFF,Data offset for inserted channel x"
line.long 0x10 "IOFF1,Inserted channel data offset registe 1"
hexmask.long.tbyte 0x10 0.--23. 1. "IOFF,Data offset for inserted channel x"
line.long 0x14 "IOFF2,Inserted channel data offset registe 2"
hexmask.long.tbyte 0x14 0.--23. 1. "IOFF,Data offset for inserted channel x"
line.long 0x18 "IOFF3,Inserted channel data offset registe 3"
hexmask.long.tbyte 0x18 0.--23. 1. "IOFF,Data offset for inserted channel x"
line.long 0x1C "WDHT0,Watchdog high threshold register 0"
hexmask.long.tbyte 0x1C 0.--21. 1. "WDHT0,High threshold for analog watchdog 0"
line.long 0x20 "WDLT0,Watchdog low threshold register 0"
hexmask.long.tbyte 0x20 0.--21. 1. "WDLT0,Low threshold for analog watchdog 0"
line.long 0x24 "RSQ0,Routine sequence register 0"
hexmask.long.byte 0x24 20.--23. 1. "RL,Routine sequence length"
hexmask.long.word 0x24 5.--14. 1. "RSMP15,Routine channel sample time"
hexmask.long.byte 0x24 0.--4. 1. "RSQ15,refer to RSQ0[4:0] description"
line.long 0x28 "RSQ1,Routine sequence register 1"
hexmask.long.word 0x28 21.--30. 1. "RSMP14,Routine channel sample time"
hexmask.long.byte 0x28 16.--20. 1. "RSQ14,refer to RSQ0[4:0] description"
hexmask.long.word 0x28 5.--14. 1. "RSMP13,Routine channel sample time"
hexmask.long.byte 0x28 0.--4. 1. "RSQ13,refer to RSQ0[4:0] description"
line.long 0x2C "RSQ2,Routine sequence register 2"
hexmask.long.word 0x2C 21.--30. 1. "RSMP12,Routine channel sample time"
hexmask.long.byte 0x2C 16.--20. 1. "RSQ12,refer to RSQ0[4:0] description"
hexmask.long.word 0x2C 5.--14. 1. "RSMP11,Routine channel sample time"
hexmask.long.byte 0x2C 0.--4. 1. "RSQ11,refer to RSQ0[4:0] description"
line.long 0x30 "RSQ3,Routine sequence register 3"
hexmask.long.word 0x30 21.--30. 1. "RSMP10,Routine channel sample time"
hexmask.long.byte 0x30 16.--20. 1. "RSQ10,refer to RSQ0[4:0] description"
hexmask.long.word 0x30 5.--14. 1. "RSMP9,Routine channel sample time"
hexmask.long.byte 0x30 0.--4. 1. "RSQ9,refer to RSQ0[4:0] description"
line.long 0x34 "RSQ4,Routine sequence register 4"
hexmask.long.word 0x34 21.--30. 1. "RSMP8,Routine channel sample time"
hexmask.long.byte 0x34 16.--20. 1. "RSQ8,refer to RSQ0[4:0] description"
hexmask.long.word 0x34 5.--14. 1. "RSMP7,Routine channel sample time"
hexmask.long.byte 0x34 0.--4. 1. "RSQ7,refer to RSQ0[4:0] description"
line.long 0x38 "RSQ5,Routine sequence register 5"
hexmask.long.word 0x38 21.--30. 1. "RSMP6,Routine channel sample time"
hexmask.long.byte 0x38 16.--20. 1. "RSQ6,refer to RSQ0[4:0] description"
hexmask.long.word 0x38 5.--14. 1. "RSMP5,Routine channel sample time"
hexmask.long.byte 0x38 0.--4. 1. "RSQ5,refer to RSQ0[4:0] description"
line.long 0x3C "RSQ6,Routine sequence register 6"
hexmask.long.word 0x3C 21.--30. 1. "RSMP4,Routine channel sample time"
hexmask.long.byte 0x3C 16.--20. 1. "RSQ4,refer to RSQ0[4:0] description"
hexmask.long.word 0x3C 5.--14. 1. "RSMP3,Routine channel sample time"
hexmask.long.byte 0x3C 0.--4. 1. "RSQ3,refer to RSQ0[4:0] description"
line.long 0x40 "RSQ7,Routine sequence register 7"
hexmask.long.word 0x40 21.--30. 1. "RSMP2,Routine channel sample time"
hexmask.long.byte 0x40 16.--20. 1. "RSQ2,refer to RSQ0[4:0] description"
hexmask.long.word 0x40 5.--14. 1. "RSMP1,Routine channel sample time"
hexmask.long.byte 0x40 0.--4. 1. "RSQ1,refer to RSQ0[4:0] description"
line.long 0x44 "RSQ8,Routine sequence register 8"
hexmask.long.word 0x44 5.--14. 1. "RSMP0,Routine channel sample time"
hexmask.long.byte 0x44 0.--4. 1. "RSQ0,The channel number (0"
line.long 0x48 "ISQ0,Inserted sequence register 0"
bitfld.long 0x48 20.--21. "IL,Inserted sequence length" "0,1,2,3"
hexmask.long.word 0x48 5.--14. 1. "ISMP3,Inserted channel sample time"
hexmask.long.byte 0x48 0.--4. 1. "ISQ3,refer to ISQ0[4:0] description"
line.long 0x4C "ISQ1,Inserted sequence register 1"
hexmask.long.word 0x4C 21.--30. 1. "ISMP2,Inserted channel sample time"
hexmask.long.byte 0x4C 16.--20. 1. "ISQ2,refer to ISQ0[4:0] description"
hexmask.long.word 0x4C 5.--14. 1. "ISMP1,Inserted channel sample time"
hexmask.long.byte 0x4C 0.--4. 1. "ISQ1,refer to ISQ0[4:0] description"
line.long 0x50 "ISQ2,Inserted sequence register 2"
hexmask.long.word 0x50 5.--14. 1. "ISMP0,Inserted channel sample time"
hexmask.long.byte 0x50 0.--4. 1. "ISQ0,The channel number (0"
rgroup.long 0x54++0x13
line.long 0x0 "IDATA0,Inserted data registe 0"
hexmask.long 0x0 0.--31. 1. "IDATAn,Inserted number n conversion data"
line.long 0x4 "IDATA1,Inserted data registe 1"
hexmask.long 0x4 0.--31. 1. "IDATAn,Inserted number n conversion data"
line.long 0x8 "IDATA2,Inserted data registe 2"
hexmask.long 0x8 0.--31. 1. "IDATAn,Inserted number n conversion data"
line.long 0xC "IDATA3,Inserted data registe 3"
hexmask.long 0xC 0.--31. 1. "IDATAn,Inserted number n conversion data"
line.long 0x10 "RDATA,Routine data register"
hexmask.long 0x10 0.--31. 1. "RDATA,Routine channel data"
group.long 0x80++0x3
line.long 0x0 "OVSAMPCTL,Oversample control register"
hexmask.long.word 0x0 16.--25. 1. "OVSR,Oversampling ratio"
bitfld.long 0x0 9. "TOVS,Triggered oversampling" "0,1"
hexmask.long.byte 0x0 5.--8. 1. "OVSS,Oversampling shift"
bitfld.long 0x0 0. "OVSEN,Oversampling Enable" "0,1"
group.long 0xA0++0x1B
line.long 0x0 "WD1SR,Watchdog 1 Channel Selection Register"
hexmask.long.tbyte 0x0 0.--21. 1. "AWD1CS,Analog watchdog 1 channel selection"
line.long 0x4 "WD2SR,Watchdog 2 Channel Selection Register"
hexmask.long.tbyte 0x4 0.--21. 1. "AWD2CS,Analog watchdog 2 channel selection"
line.long 0x8 "WDHT1,Watchdog high threshold register1"
hexmask.long.tbyte 0x8 0.--21. 1. "WDHT1,High threshold for analog watchdog 1"
line.long 0xC "WDLT1,Watchdog low threshold register1"
hexmask.long.tbyte 0xC 0.--21. 1. "WDLT1,Low threshold for analog watchdog 1"
line.long 0x10 "WDHT2,Watchdog high threshold register2"
hexmask.long.tbyte 0x10 0.--21. 1. "WDHT2,High threshold for analog watchdog 2"
line.long 0x14 "WDLT2,Watchdog low threshold register2"
hexmask.long.tbyte 0x14 0.--21. 1. "WDLT2,Low threshold for analog watchdog 2"
line.long 0x18 "DIFCTL,Differential mode control register"
hexmask.long.tbyte 0x18 0.--21. 1. "DIFCTL,Differential mode for channel 21"
group.long 0xC0++0x3
line.long 0x0 "GAINCFG,Gain configure register"
hexmask.long.word 0x0 0.--13. 1. "GAIN,Gain factor"
rgroup.long 0x300++0x3
line.long 0x0 "SSTAT,Summary status register"
bitfld.long 0x0 7. "ADC0_ROVF,This bit is the mirror image of the ROVF bit of ADC0" "0,1"
bitfld.long 0x0 6. "ADC0_STRC,This bit is the mirror image of the STRC bit of ADC0" "0,1"
bitfld.long 0x0 5. "ADC0_STIC,This bit is the mirror image of the STIC bit of ADC0" "0,1"
bitfld.long 0x0 4. "ADC0_EOIC,This bit is the mirror image of the EOIC bit of ADC0" "0,1"
bitfld.long 0x0 3. "ADC0_EOC,This bit is the mirror image of the EOC bit of ADC0" "0,1"
bitfld.long 0x0 2. "ADC0_WDE2,This bit is the mirror image of the WDE2 bit of ADC0" "0,1"
bitfld.long 0x0 1. "ADC0_WDE1,This bit is the mirror image of the WDE1 bit of ADC0" "0,1"
bitfld.long 0x0 0. "ADC0_WDE0,This bit is the mirror image of the WDE0 bit of ADC0" "0,1"
group.long 0x304++0x3
line.long 0x0 "SYNCCTL,Sync control register"
hexmask.long.byte 0x0 20.--23. 1. "ADCCK,ADC clock prescaler"
hexmask.long.byte 0x0 16.--19. 1. "ADCSCK,ADC sync clock mode"
bitfld.long 0x0 14.--15. "SYNCDMA,ADC sync DMA mode selection" "0,1,2,3"
bitfld.long 0x0 13. "SYNCDDM,ADC sync DMA disable mode" "0,1"
hexmask.long.byte 0x0 8.--11. 1. "SYNCDLY,ADC sync delay"
hexmask.long.byte 0x0 0.--4. 1. "SYNCM,ADC sync mode"
rgroup.long 0x308++0x3
line.long 0x0 "SYNCDATA,Sync routine data register"
hexmask.long.word 0x0 16.--31. 1. "SYNCDATA1,Routine data 1 in ADC sync mode"
hexmask.long.word 0x0 0.--15. 1. "SYNCDATA0,Routine data 0 in ADC sync mode"
tree.end
tree "ADC1"
base ad:0x50000400
group.long 0x0++0x53
line.long 0x0 "STAT,Status register"
bitfld.long 0x0 31. "WDE2,Analog watchdog 2 event flag" "0,1"
bitfld.long 0x0 30. "WDE1,Analog watchdog 1 event flag" "0,1"
bitfld.long 0x0 5. "ROVF,Routine data register overflow" "0,1"
bitfld.long 0x0 4. "STRC,Start flag of routine sequence" "0,1"
bitfld.long 0x0 3. "STIC,Start flag of inserted sequence" "0,1"
bitfld.long 0x0 2. "EOIC,End of inserted sequence conversion flag" "0,1"
bitfld.long 0x0 1. "EOC,End of sequence conversion flag" "0,1"
bitfld.long 0x0 0. "WDE0,Analog watchdog 0 event flag" "0,1"
line.long 0x4 "CTL0,Control register 0"
bitfld.long 0x4 31. "WDE2IE,Interrupt enable for WDE2" "0,1"
bitfld.long 0x4 30. "WDE1IE,Interrupt enable for WDE1" "0,1"
bitfld.long 0x4 26. "ROVFIE,Interrupt enable for ROVF" "0,1"
bitfld.long 0x4 24.--25. "DRES,ADC data resolution" "0,1,2,3"
bitfld.long 0x4 23. "RWD0EN,Routine channel analog watchdog 0 enable" "0,1"
bitfld.long 0x4 22. "IWD0EN,Inserted channel analog watchdog 0 enable" "0,1"
bitfld.long 0x4 13.--15. "DISNUM,Number of conversions in discontinuous mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 12. "DISIC,Discontinuous mode on inserted channels" "0,1"
newline
bitfld.long 0x4 11. "DISRC,Discontinuous mode on routine channels" "0,1"
bitfld.long 0x4 10. "ICA,Inserted sequence convert automatically" "0,1"
bitfld.long 0x4 9. "WD0SC,When in scan mode analog watchdog 0 is effective on a single channel" "0,1"
bitfld.long 0x4 8. "SM,Scan mode" "0,1"
bitfld.long 0x4 7. "EOICIE,Interrupt enable for EOIC" "0,1"
bitfld.long 0x4 6. "WDE0IE,Interrupt enable for WDE0" "0,1"
bitfld.long 0x4 5. "EOCIE,Interrupt enable for EOC" "0,1"
hexmask.long.byte 0x4 0.--4. 1. "WD0CHSEL,Analog watchdog 0 channel select"
line.long 0x8 "CTL1,Control register 1"
bitfld.long 0x8 30. "SWRCST,Software start on routine channel" "0,1"
bitfld.long 0x8 28.--29. "ETMRC,External trigger mode for routine channel" "0,1,2,3"
bitfld.long 0x8 27. "CALMOD,ADC calibration mode" "0,1"
bitfld.long 0x8 22. "SWICST,Software start on inserted channel" "0,1"
bitfld.long 0x8 20.--21. "ETMIC,External trigger mode for inserted channel" "0,1,2,3"
bitfld.long 0x8 18. "MVMC,Mean value mode Configuration" "0,1"
bitfld.long 0x8 17. "WAIEN,Weighted averaging in inserted sequence mean value mode enable" "0,1"
bitfld.long 0x8 16. "GAINEN,Gain mode enable" "0,1"
newline
bitfld.long 0x8 12. "HPDFCFG,HPDF mode configuration" "0,1"
bitfld.long 0x8 11. "DAL,Data alignment" "0,1"
bitfld.long 0x8 10. "EOCM,End of conversion mode" "0,1"
bitfld.long 0x8 9. "DDM,DMA disable mode" "0,1"
bitfld.long 0x8 8. "DMA,DMA request enable" "0,1"
bitfld.long 0x8 4.--6. "CALNUM,Calibration Times" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 3. "RSTCLB,Reset calibration" "0,1"
bitfld.long 0x8 2. "CLB,ADC calibration" "0,1"
newline
bitfld.long 0x8 1. "CTN,Continuous mode" "0,1"
bitfld.long 0x8 0. "ADCON,ADC ON" "0,1"
line.long 0xC "IOFF0,Inserted channel data offset registe 0"
hexmask.long.tbyte 0xC 0.--23. 1. "IOFF,Data offset for inserted channel x"
line.long 0x10 "IOFF1,Inserted channel data offset registe 1"
hexmask.long.tbyte 0x10 0.--23. 1. "IOFF,Data offset for inserted channel x"
line.long 0x14 "IOFF2,Inserted channel data offset registe 2"
hexmask.long.tbyte 0x14 0.--23. 1. "IOFF,Data offset for inserted channel x"
line.long 0x18 "IOFF3,Inserted channel data offset registe 3"
hexmask.long.tbyte 0x18 0.--23. 1. "IOFF,Data offset for inserted channel x"
line.long 0x1C "WDHT0,Watchdog high threshold register 0"
hexmask.long.tbyte 0x1C 0.--21. 1. "WDHT0,High threshold for analog watchdog 0"
line.long 0x20 "WDLT0,Watchdog low threshold register 0"
hexmask.long.tbyte 0x20 0.--21. 1. "WDLT0,Low threshold for analog watchdog 0"
line.long 0x24 "RSQ0,Routine sequence register 0"
hexmask.long.byte 0x24 20.--23. 1. "RL,Routine sequence length"
hexmask.long.word 0x24 5.--14. 1. "RSMP15,Routine channel sample time"
hexmask.long.byte 0x24 0.--4. 1. "RSQ15,refer to RSQ0[4:0] description"
line.long 0x28 "RSQ1,Routine sequence register 1"
hexmask.long.word 0x28 21.--30. 1. "RSMP14,Routine channel sample time"
hexmask.long.byte 0x28 16.--20. 1. "RSQ14,refer to RSQ0[4:0] description"
hexmask.long.word 0x28 5.--14. 1. "RSMP13,Routine channel sample time"
hexmask.long.byte 0x28 0.--4. 1. "RSQ13,refer to RSQ0[4:0] description"
line.long 0x2C "RSQ2,Routine sequence register 2"
hexmask.long.word 0x2C 21.--30. 1. "RSMP12,Routine channel sample time"
hexmask.long.byte 0x2C 16.--20. 1. "RSQ12,refer to RSQ0[4:0] description"
hexmask.long.word 0x2C 5.--14. 1. "RSMP11,Routine channel sample time"
hexmask.long.byte 0x2C 0.--4. 1. "RSQ11,refer to RSQ0[4:0] description"
line.long 0x30 "RSQ3,Routine sequence register 3"
hexmask.long.word 0x30 21.--30. 1. "RSMP10,Routine channel sample time"
hexmask.long.byte 0x30 16.--20. 1. "RSQ10,refer to RSQ0[4:0] description"
hexmask.long.word 0x30 5.--14. 1. "RSMP9,Routine channel sample time"
hexmask.long.byte 0x30 0.--4. 1. "RSQ9,refer to RSQ0[4:0] description"
line.long 0x34 "RSQ4,Routine sequence register 4"
hexmask.long.word 0x34 21.--30. 1. "RSMP8,Routine channel sample time"
hexmask.long.byte 0x34 16.--20. 1. "RSQ8,refer to RSQ0[4:0] description"
hexmask.long.word 0x34 5.--14. 1. "RSMP7,Routine channel sample time"
hexmask.long.byte 0x34 0.--4. 1. "RSQ7,refer to RSQ0[4:0] description"
line.long 0x38 "RSQ5,Routine sequence register 5"
hexmask.long.word 0x38 21.--30. 1. "RSMP6,Routine channel sample time"
hexmask.long.byte 0x38 16.--20. 1. "RSQ6,refer to RSQ0[4:0] description"
hexmask.long.word 0x38 5.--14. 1. "RSMP5,Routine channel sample time"
hexmask.long.byte 0x38 0.--4. 1. "RSQ5,refer to RSQ0[4:0] description"
line.long 0x3C "RSQ6,Routine sequence register 6"
hexmask.long.word 0x3C 21.--30. 1. "RSMP4,Routine channel sample time"
hexmask.long.byte 0x3C 16.--20. 1. "RSQ4,refer to RSQ0[4:0] description"
hexmask.long.word 0x3C 5.--14. 1. "RSMP3,Routine channel sample time"
hexmask.long.byte 0x3C 0.--4. 1. "RSQ3,refer to RSQ0[4:0] description"
line.long 0x40 "RSQ7,Routine sequence register 7"
hexmask.long.word 0x40 21.--30. 1. "RSMP2,Routine channel sample time"
hexmask.long.byte 0x40 16.--20. 1. "RSQ2,refer to RSQ0[4:0] description"
hexmask.long.word 0x40 5.--14. 1. "RSMP1,Routine channel sample time"
hexmask.long.byte 0x40 0.--4. 1. "RSQ1,refer to RSQ0[4:0] description"
line.long 0x44 "RSQ8,Routine sequence register 8"
hexmask.long.word 0x44 5.--14. 1. "RSMP0,Routine channel sample time"
hexmask.long.byte 0x44 0.--4. 1. "RSQ0,The channel number (0"
line.long 0x48 "ISQ0,Inserted sequence register 0"
bitfld.long 0x48 20.--21. "IL,Inserted sequence length" "0,1,2,3"
hexmask.long.word 0x48 5.--14. 1. "ISMP3,Inserted channel sample time"
hexmask.long.byte 0x48 0.--4. 1. "ISQ3,refer to ISQ0[4:0] description"
line.long 0x4C "ISQ1,Inserted sequence register 1"
hexmask.long.word 0x4C 21.--30. 1. "ISMP2,Inserted channel sample time"
hexmask.long.byte 0x4C 16.--20. 1. "ISQ2,refer to ISQ0[4:0] description"
hexmask.long.word 0x4C 5.--14. 1. "ISMP1,Inserted channel sample time"
hexmask.long.byte 0x4C 0.--4. 1. "ISQ1,refer to ISQ0[4:0] description"
line.long 0x50 "ISQ2,Inserted sequence register 2"
hexmask.long.word 0x50 5.--14. 1. "ISMP0,Inserted channel sample time"
hexmask.long.byte 0x50 0.--4. 1. "ISQ0,The channel number (0"
rgroup.long 0x54++0x13
line.long 0x0 "IDATA0,Inserted data registe 0"
hexmask.long 0x0 0.--31. 1. "IDATAn,Inserted number n conversion data"
line.long 0x4 "IDATA1,Inserted data registe 1"
hexmask.long 0x4 0.--31. 1. "IDATAn,Inserted number n conversion data"
line.long 0x8 "IDATA2,Inserted data registe 2"
hexmask.long 0x8 0.--31. 1. "IDATAn,Inserted number n conversion data"
line.long 0xC "IDATA3,Inserted data registe 3"
hexmask.long 0xC 0.--31. 1. "IDATAn,Inserted number n conversion data"
line.long 0x10 "RDATA,Routine data register"
hexmask.long 0x10 0.--31. 1. "RDATA,Routine channel data"
group.long 0x80++0x3
line.long 0x0 "OVSAMPCTL,Oversample control register"
hexmask.long.word 0x0 16.--25. 1. "OVSR,Oversampling ratio"
bitfld.long 0x0 9. "TOVS,Triggered oversampling" "0,1"
hexmask.long.byte 0x0 5.--8. 1. "OVSS,Oversampling shift"
bitfld.long 0x0 0. "OVSEN,Oversampling Enable" "0,1"
group.long 0xA0++0x1B
line.long 0x0 "WD1SR,Watchdog 1 Channel Selection Register"
hexmask.long.tbyte 0x0 0.--21. 1. "AWD1CS,Analog watchdog 1 channel selection"
line.long 0x4 "WD2SR,Watchdog 2 Channel Selection Register"
hexmask.long.tbyte 0x4 0.--21. 1. "AWD2CS,Analog watchdog 2 channel selection"
line.long 0x8 "WDHT1,Watchdog high threshold register1"
hexmask.long.tbyte 0x8 0.--21. 1. "WDHT1,High threshold for analog watchdog 1"
line.long 0xC "WDLT1,Watchdog low threshold register1"
hexmask.long.tbyte 0xC 0.--21. 1. "WDLT1,Low threshold for analog watchdog 1"
line.long 0x10 "WDHT2,Watchdog high threshold register2"
hexmask.long.tbyte 0x10 0.--21. 1. "WDHT2,High threshold for analog watchdog 2"
line.long 0x14 "WDLT2,Watchdog low threshold register2"
hexmask.long.tbyte 0x14 0.--21. 1. "WDLT2,Low threshold for analog watchdog 2"
line.long 0x18 "DIFCTL,Differential mode control register"
hexmask.long.tbyte 0x18 0.--21. 1. "DIFCTL,Differential mode for channel 21"
group.long 0xC0++0x3
line.long 0x0 "GAINCFG,Gain configure register"
hexmask.long.word 0x0 0.--13. 1. "GAIN,Gain factor"
rgroup.long 0x300++0x3
line.long 0x0 "SSTAT,Summary status register"
bitfld.long 0x0 15. "ADC1_ROVF,This bit is the mirror image of the ROVF bit of ADC1" "0,1"
bitfld.long 0x0 14. "ADC1_STRC,This bit is the mirror image of the STRC bit of ADC1" "0,1"
bitfld.long 0x0 13. "ADC1_STIC,This bit is the mirror image of the STIC bit of ADC1" "0,1"
bitfld.long 0x0 12. "ADC1_EOIC,This bit is the mirror image of the EOIC bit of ADC1" "0,1"
bitfld.long 0x0 11. "ADC1_EOC,This bit is the mirror image of the EOC bit of ADC1" "0,1"
bitfld.long 0x0 10. "ADC1_WDE2,This bit is the mirror image of the WDE2 bit of ADC1" "0,1"
bitfld.long 0x0 9. "ADC1_WDE1,This bit is the mirror image of the WDE1 bit of ADC1" "0,1"
bitfld.long 0x0 8. "ADC1_WDE0,This bit is the mirror image of the WDE0 bit of ADC1" "0,1"
group.long 0x304++0x3
line.long 0x0 "SYNCCTL,Sync control register"
hexmask.long.byte 0x0 20.--23. 1. "ADCCK,ADC clock prescaler"
hexmask.long.byte 0x0 16.--19. 1. "ADCSCK,ADC sync clock mode"
bitfld.long 0x0 14.--15. "SYNCDMA,ADC sync DMA mode selection" "0,1,2,3"
bitfld.long 0x0 13. "SYNCDDM,ADC sync DMA disable mode" "0,1"
hexmask.long.byte 0x0 8.--11. 1. "SYNCDLY,ADC sync delay"
hexmask.long.byte 0x0 0.--4. 1. "SYNCM,ADC sync mode"
rgroup.long 0x308++0x3
line.long 0x0 "SYNCDATA,Sync routine data register"
hexmask.long.word 0x0 16.--31. 1. "SYNCDATA1,Routine data 1 in ADC sync mode"
hexmask.long.word 0x0 0.--15. 1. "SYNCDATA0,Routine data 0 in ADC sync mode"
tree.end
tree "ADC2"
base ad:0x50000800
group.long 0x0++0x53
line.long 0x0 "STAT,Status register"
bitfld.long 0x0 31. "WDE2,Analog watchdog 2 event flag" "0,1"
bitfld.long 0x0 30. "WDE1,Analog watchdog 1 event flag" "0,1"
bitfld.long 0x0 5. "ROVF,Routine data register overflow" "0,1"
bitfld.long 0x0 4. "STRC,Start flag of routine sequence" "0,1"
bitfld.long 0x0 3. "STIC,Start flag of inserted sequence" "0,1"
bitfld.long 0x0 2. "EOIC,End of inserted sequence conversion flag" "0,1"
bitfld.long 0x0 1. "EOC,End of sequence conversion flag" "0,1"
bitfld.long 0x0 0. "WDE0,Analog watchdog 0 event flag" "0,1"
line.long 0x4 "CTL0,Control register 0"
bitfld.long 0x4 31. "WDE2IE,Interrupt enable for WDE2" "0,1"
bitfld.long 0x4 30. "WDE1IE,Interrupt enable for WDE1" "0,1"
bitfld.long 0x4 26. "ROVFIE,Interrupt enable for ROVF" "0,1"
bitfld.long 0x4 24.--25. "DRES,ADC data resolution" "0,1,2,3"
bitfld.long 0x4 23. "RWD0EN,Routine channel analog watchdog 0 enable" "0,1"
bitfld.long 0x4 13.--15. "DISNUM,Number of conversions in discontinuous mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 12. "DISIC,Discontinuous mode on inserted channels" "0,1"
bitfld.long 0x4 11. "DISRC,Discontinuous mode on routine channels" "0,1"
newline
bitfld.long 0x4 10. "ICA,Inserted sequence convert automatically" "0,1"
bitfld.long 0x4 9. "WD0SC,When in scan mode analog watchdog 0 is effective on a single channel" "0,1"
bitfld.long 0x4 8. "SM,Scan mode" "0,1"
bitfld.long 0x4 7. "EOICIE,Interrupt enable for EOIC" "0,1"
bitfld.long 0x4 6. "WDE0IE,Interrupt enable for WDE0" "0,1"
bitfld.long 0x4 5. "EOCIE,Interrupt enable for EOC" "0,1"
hexmask.long.byte 0x4 0.--4. 1. "WD0CHSEL,Analog watchdog 0 channel select"
line.long 0x8 "CTL1,Control register 1"
bitfld.long 0x8 31. "TSVEN2,This bit can be set or cleared by software in ADC2" "0,1"
bitfld.long 0x8 30. "SWRCST,Software start on routine channel" "0,1"
bitfld.long 0x8 28.--29. "ETMRC,External trigger mode for routine channel" "0,1,2,3"
bitfld.long 0x8 27. "CALMOD,ADC calibration mode" "0,1"
bitfld.long 0x8 25. "VBATEN,This bit can be set or cleared by software in ADC0 and ADC2" "0,1"
bitfld.long 0x8 24. "INREFEN,This bit can be set or cleared by software in ADC0" "0,1"
bitfld.long 0x8 23. "TSVEN1,This bit can be set or cleared by software in ADC0" "0,1"
bitfld.long 0x8 22. "SWICST,Software start on inserted channel" "0,1"
newline
bitfld.long 0x8 20.--21. "ETMIC,External trigger mode for inserted channel" "0,1,2,3"
bitfld.long 0x8 18. "MVMC,Mean value mode Configuration" "0,1"
bitfld.long 0x8 17. "WAIEN,Weighted averaging in inserted sequence mean value mode enable" "0,1"
bitfld.long 0x8 16. "GAINEN,Gain mode enable" "0,1"
bitfld.long 0x8 12. "HPDFCFG,HPDF mode configuration" "0,1"
bitfld.long 0x8 11. "DAL,Data alignment" "0,1"
bitfld.long 0x8 10. "EOCM,End of conversion mode" "0,1"
bitfld.long 0x8 9. "DDM,DMA disable mode" "0,1"
newline
bitfld.long 0x8 8. "DMA,DMA request enable" "0,1"
bitfld.long 0x8 4.--6. "CALNUM,Calibration Times" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 3. "RSTCLB,Reset calibration" "0,1"
bitfld.long 0x8 2. "CLB,ADC calibration" "0,1"
bitfld.long 0x8 1. "CTN,Continuous mode" "0,1"
bitfld.long 0x8 0. "ADCON,ADC ON" "0,1"
line.long 0xC "IOFF0,Inserted channel data offset registe 0"
hexmask.long.tbyte 0xC 0.--23. 1. "IOFF,Data offset for inserted channel x"
line.long 0x10 "IOFF1,Inserted channel data offset registe 1"
hexmask.long.tbyte 0x10 0.--23. 1. "IOFF,Data offset for inserted channel x"
line.long 0x14 "IOFF2,Inserted channel data offset registe 2"
hexmask.long.tbyte 0x14 0.--23. 1. "IOFF,Data offset for inserted channel x"
line.long 0x18 "IOFF3,Inserted channel data offset registe 3"
hexmask.long.tbyte 0x18 0.--23. 1. "IOFF,Data offset for inserted channel x"
line.long 0x1C "WDHT0,Watchdog high threshold register 0"
hexmask.long.tbyte 0x1C 0.--21. 1. "WDHT0,High threshold for analog watchdog 0"
line.long 0x20 "WDLT0,Watchdog low threshold register 0"
hexmask.long.tbyte 0x20 0.--21. 1. "WDLT0,Low threshold for analog watchdog 0"
line.long 0x24 "RSQ0,Routine sequence register 0"
hexmask.long.byte 0x24 20.--23. 1. "RL,Routine sequence length"
hexmask.long.word 0x24 5.--14. 1. "RSMP15,Routine channel sample time"
hexmask.long.byte 0x24 0.--4. 1. "RSQ15,refer to RSQ0[4:0] description"
line.long 0x28 "RSQ1,Routine sequence register 1"
hexmask.long.word 0x28 21.--30. 1. "RSMP14,Routine channel sample time"
hexmask.long.byte 0x28 16.--20. 1. "RSQ14,refer to RSQ0[4:0] description"
hexmask.long.word 0x28 5.--14. 1. "RSMP13,Routine channel sample time"
hexmask.long.byte 0x28 0.--4. 1. "RSQ13,refer to RSQ0[4:0] description"
line.long 0x2C "RSQ2,Routine sequence register 2"
hexmask.long.word 0x2C 21.--30. 1. "RSMP12,Routine channel sample time"
hexmask.long.byte 0x2C 16.--20. 1. "RSQ12,refer to RSQ0[4:0] description"
hexmask.long.word 0x2C 5.--14. 1. "RSMP11,Routine channel sample time"
hexmask.long.byte 0x2C 0.--4. 1. "RSQ11,refer to RSQ0[4:0] description"
line.long 0x30 "RSQ3,Routine sequence register 3"
hexmask.long.word 0x30 21.--30. 1. "RSMP10,Routine channel sample time"
hexmask.long.byte 0x30 16.--20. 1. "RSQ10,refer to RSQ0[4:0] description"
hexmask.long.word 0x30 5.--14. 1. "RSMP9,Routine channel sample time"
hexmask.long.byte 0x30 0.--4. 1. "RSQ9,refer to RSQ0[4:0] description"
line.long 0x34 "RSQ4,Routine sequence register 4"
hexmask.long.word 0x34 21.--30. 1. "RSMP8,Routine channel sample time"
hexmask.long.byte 0x34 16.--20. 1. "RSQ8,refer to RSQ0[4:0] description"
hexmask.long.word 0x34 5.--14. 1. "RSMP7,Routine channel sample time"
hexmask.long.byte 0x34 0.--4. 1. "RSQ7,refer to RSQ0[4:0] description"
line.long 0x38 "RSQ5,Routine sequence register 5"
hexmask.long.word 0x38 21.--30. 1. "RSMP6,Routine channel sample time"
hexmask.long.byte 0x38 16.--20. 1. "RSQ6,refer to RSQ0[4:0] description"
hexmask.long.word 0x38 5.--14. 1. "RSMP5,Routine channel sample time"
hexmask.long.byte 0x38 0.--4. 1. "RSQ5,refer to RSQ0[4:0] description"
line.long 0x3C "RSQ6,Routine sequence register 6"
hexmask.long.word 0x3C 21.--30. 1. "RSMP4,Routine channel sample time"
hexmask.long.byte 0x3C 16.--20. 1. "RSQ4,refer to RSQ0[4:0] description"
hexmask.long.word 0x3C 5.--14. 1. "RSMP3,Routine channel sample time"
hexmask.long.byte 0x3C 0.--4. 1. "RSQ3,refer to RSQ0[4:0] description"
line.long 0x40 "RSQ7,Routine sequence register 7"
hexmask.long.word 0x40 21.--30. 1. "RSMP2,Routine channel sample time"
hexmask.long.byte 0x40 16.--20. 1. "RSQ2,refer to RSQ0[4:0] description"
hexmask.long.word 0x40 5.--14. 1. "RSMP1,Routine channel sample time"
hexmask.long.byte 0x40 0.--4. 1. "RSQ1,refer to RSQ0[4:0] description"
line.long 0x44 "RSQ8,Routine sequence register 8"
hexmask.long.word 0x44 5.--14. 1. "RSMP0,Routine channel sample time"
hexmask.long.byte 0x44 0.--4. 1. "RSQ0,The channel number (0"
line.long 0x48 "ISQ0,Inserted sequence register 0"
bitfld.long 0x48 20.--21. "IL,Inserted sequence length" "0,1,2,3"
hexmask.long.word 0x48 5.--14. 1. "ISMP3,Inserted channel sample time"
hexmask.long.byte 0x48 0.--4. 1. "ISQ3,refer to ISQ0[4:0] description"
line.long 0x4C "ISQ1,Inserted sequence register 1"
hexmask.long.word 0x4C 21.--30. 1. "ISMP2,Inserted channel sample time"
hexmask.long.byte 0x4C 16.--20. 1. "ISQ2,refer to ISQ0[4:0] description"
hexmask.long.word 0x4C 5.--14. 1. "ISMP1,Inserted channel sample time"
hexmask.long.byte 0x4C 0.--4. 1. "ISQ1,refer to ISQ0[4:0] description"
line.long 0x50 "ISQ2,Inserted sequence register 2"
hexmask.long.word 0x50 5.--14. 1. "ISMP0,Inserted channel sample time"
hexmask.long.byte 0x50 0.--4. 1. "ISQ0,The channel number (0"
rgroup.long 0x54++0x13
line.long 0x0 "IDATA0,Inserted data registe 0"
hexmask.long 0x0 0.--31. 1. "IDATAn,Inserted number n conversion data"
line.long 0x4 "IDATA1,Inserted data registe 1"
hexmask.long 0x4 0.--31. 1. "IDATAn,Inserted number n conversion data"
line.long 0x8 "IDATA2,Inserted data registe 2"
hexmask.long 0x8 0.--31. 1. "IDATAn,Inserted number n conversion data"
line.long 0xC "IDATA3,Inserted data registe 3"
hexmask.long 0xC 0.--31. 1. "IDATAn,Inserted number n conversion data"
line.long 0x10 "RDATA,Routine data register"
hexmask.long 0x10 0.--31. 1. "RDATA,Routine channel data"
group.long 0x80++0x3
line.long 0x0 "OVSAMPCTL,Oversample control register"
hexmask.long.word 0x0 16.--25. 1. "OVSR,Oversampling ratio"
bitfld.long 0x0 9. "TOVS,Triggered oversampling" "0,1"
hexmask.long.byte 0x0 5.--8. 1. "OVSS,Oversampling shift"
bitfld.long 0x0 0. "OVSEN,Oversampling Enable" "0,1"
group.long 0xA0++0x1B
line.long 0x0 "WD1SR,Watchdog 1 Channel Selection Register"
hexmask.long.tbyte 0x0 0.--21. 1. "AWD1CS,Analog watchdog 1 channel selection"
line.long 0x4 "WD2SR,Watchdog 2 Channel Selection Register"
hexmask.long.tbyte 0x4 0.--21. 1. "AWD2CS,Analog watchdog 2 channel selection"
line.long 0x8 "WDHT1,Watchdog high threshold register1"
hexmask.long.tbyte 0x8 0.--21. 1. "WDHT1,High threshold for analog watchdog 1"
line.long 0xC "WDLT1,Watchdog low threshold register1"
hexmask.long.tbyte 0xC 0.--21. 1. "WDLT1,Low threshold for analog watchdog 1"
line.long 0x10 "WDHT2,Watchdog high threshold register2"
hexmask.long.tbyte 0x10 0.--21. 1. "WDHT2,High threshold for analog watchdog 2"
line.long 0x14 "WDLT2,Watchdog low threshold register2"
hexmask.long.tbyte 0x14 0.--21. 1. "WDLT2,Low threshold for analog watchdog 2"
line.long 0x18 "DIFCTL,Differential mode control register"
hexmask.long.tbyte 0x18 0.--21. 1. "DIFCTL,Differential mode for channel 21"
group.long 0xC0++0x3
line.long 0x0 "GAINCFG,Gain configure register"
hexmask.long.word 0x0 0.--13. 1. "GAIN,Gain factor"
rgroup.long 0x300++0x3
line.long 0x0 "SSTAT,Summary status register"
bitfld.long 0x0 23. "ADC2_ROVF,This bit is the mirror image of the ROVF bit of ADC2" "0,1"
bitfld.long 0x0 22. "ADC2_STRC,This bit is the mirror image of the STRC bit of ADC2" "0,1"
bitfld.long 0x0 21. "ADC2_STIC,This bit is the mirror image of the STIC bit of ADC2" "0,1"
bitfld.long 0x0 20. "ADC2_EOIC,This bit is the mirror image of the EOIC bit of ADC2" "0,1"
bitfld.long 0x0 19. "ADC2_EOC,This bit is the mirror image of the EOC bit of ADC2" "0,1"
bitfld.long 0x0 18. "ADC2_WDE2,This bit is the mirror image of the WDE2 bit of ADC2" "0,1"
bitfld.long 0x0 17. "ADC2_WDE1,This bit is the mirror image of the WDE1 bit of ADC2" "0,1"
bitfld.long 0x0 16. "ADC2_WDE0,This bit is the mirror image of the WDE0 bit of ADC2" "0,1"
group.long 0x304++0x3
line.long 0x0 "SYNCCTL,Sync control register"
hexmask.long.byte 0x0 20.--23. 1. "ADCCK,ADC clock prescaler"
hexmask.long.byte 0x0 16.--19. 1. "ADCSCK,ADC sync clock mode"
bitfld.long 0x0 14.--15. "SYNCDMA,ADC sync DMA mode selection" "0,1,2,3"
bitfld.long 0x0 13. "SYNCDDM,ADC sync DMA disable mode" "0,1"
hexmask.long.byte 0x0 8.--11. 1. "SYNCDLY,ADC sync delay"
hexmask.long.byte 0x0 0.--4. 1. "SYNCM,ADC sync mode"
rgroup.long 0x308++0x3
line.long 0x0 "SYNCDATA,Sync routine data register"
hexmask.long.word 0x0 16.--31. 1. "SYNCDATA1,Routine data 1 in ADC sync mode"
hexmask.long.word 0x0 0.--15. 1. "SYNCDATA0,Routine data 0 in ADC sync mode"
tree.end
tree "ADC3"
base ad:0x50000C00
group.long 0x0++0x53
line.long 0x0 "STAT,Status register"
bitfld.long 0x0 31. "WDE2,Analog watchdog 2 event flag" "0,1"
bitfld.long 0x0 30. "WDE1,Analog watchdog 1 event flag" "0,1"
bitfld.long 0x0 5. "ROVF,Routine data register overflow" "0,1"
bitfld.long 0x0 4. "STRC,Start flag of routine sequence" "0,1"
bitfld.long 0x0 3. "STIC,Start flag of inserted sequence" "0,1"
bitfld.long 0x0 2. "EOIC,End of inserted sequence conversion flag" "0,1"
bitfld.long 0x0 1. "EOC,End of sequence conversion flag" "0,1"
bitfld.long 0x0 0. "WDE0,Analog watchdog 0 event flag" "0,1"
line.long 0x4 "CTL0,Control register 0"
bitfld.long 0x4 31. "WDE2IE,Interrupt enable for WDE2" "0,1"
bitfld.long 0x4 30. "WDE1IE,Interrupt enable for WDE1" "0,1"
bitfld.long 0x4 26. "ROVFIE,Interrupt enable for ROVF" "0,1"
bitfld.long 0x4 24.--25. "DRES,ADC data resolution" "0,1,2,3"
bitfld.long 0x4 23. "RWD0EN,Routine channel analog watchdog 0 enable" "0,1"
bitfld.long 0x4 22. "IWD0EN,Inserted channel analog watchdog 0 enable" "0,1"
bitfld.long 0x4 13.--15. "DISNUM,Number of conversions in discontinuous mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 12. "DISIC,Discontinuous mode on inserted channels" "0,1"
newline
bitfld.long 0x4 11. "DISRC,Discontinuous mode on routine channels" "0,1"
bitfld.long 0x4 10. "ICA,Inserted sequence convert automatically" "0,1"
bitfld.long 0x4 9. "WD0SC,When in scan mode analog watchdog 0 is effective on a single channel" "0,1"
bitfld.long 0x4 8. "SM,Scan mode" "0,1"
bitfld.long 0x4 7. "EOICIE,Interrupt enable for EOIC" "0,1"
bitfld.long 0x4 6. "WDE0IE,Interrupt enable for WDE0" "0,1"
bitfld.long 0x4 5. "EOCIE,Interrupt enable for EOC" "0,1"
hexmask.long.byte 0x4 0.--4. 1. "WD0CHSEL,Analog watchdog 0 channel select"
line.long 0x8 "CTL1,Control register 1"
bitfld.long 0x8 30. "SWRCST,Software start on routine channel" "0,1"
bitfld.long 0x8 28.--29. "ETMRC,External trigger mode for routine channel" "0,1,2,3"
bitfld.long 0x8 27. "CALMOD,ADC calibration mode" "0,1"
bitfld.long 0x8 22. "SWICST,Software start on inserted channel" "0,1"
bitfld.long 0x8 20.--21. "ETMIC,External trigger mode for inserted channel" "0,1,2,3"
bitfld.long 0x8 18. "MVMC,Mean value mode Configuration" "0,1"
bitfld.long 0x8 17. "WAIEN,Weighted averaging in inserted sequence mean value mode enable" "0,1"
bitfld.long 0x8 16. "GAINEN,Gain mode enable" "0,1"
newline
bitfld.long 0x8 12. "HPDFCFG,HPDF mode configuration" "0,1"
bitfld.long 0x8 11. "DAL,Data alignment" "0,1"
bitfld.long 0x8 10. "EOCM,End of conversion mode" "0,1"
bitfld.long 0x8 9. "DDM,DMA disable mode" "0,1"
bitfld.long 0x8 8. "DMA,DMA request enable" "0,1"
bitfld.long 0x8 4.--6. "CALNUM,Calibration Times" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 3. "RSTCLB,Reset calibration" "0,1"
bitfld.long 0x8 2. "CLB,ADC calibration" "0,1"
newline
bitfld.long 0x8 1. "CTN,Continuous mode" "0,1"
bitfld.long 0x8 0. "ADCON,ADC ON" "0,1"
line.long 0xC "IOFF0,Inserted channel data offset registe 0"
hexmask.long.tbyte 0xC 0.--23. 1. "IOFF,Data offset for inserted channel x"
line.long 0x10 "IOFF1,Inserted channel data offset registe 1"
hexmask.long.tbyte 0x10 0.--23. 1. "IOFF,Data offset for inserted channel x"
line.long 0x14 "IOFF2,Inserted channel data offset registe 2"
hexmask.long.tbyte 0x14 0.--23. 1. "IOFF,Data offset for inserted channel x"
line.long 0x18 "IOFF3,Inserted channel data offset registe 3"
hexmask.long.tbyte 0x18 0.--23. 1. "IOFF,Data offset for inserted channel x"
line.long 0x1C "WDHT0,Watchdog high threshold register 0"
hexmask.long.tbyte 0x1C 0.--21. 1. "WDHT0,High threshold for analog watchdog 0"
line.long 0x20 "WDLT0,Watchdog low threshold register 0"
hexmask.long.tbyte 0x20 0.--21. 1. "WDLT0,Low threshold for analog watchdog 0"
line.long 0x24 "RSQ0,Routine sequence register 0"
hexmask.long.byte 0x24 20.--23. 1. "RL,Routine sequence length"
hexmask.long.word 0x24 5.--14. 1. "RSMP15,Routine channel sample time"
hexmask.long.byte 0x24 0.--4. 1. "RSQ15,refer to RSQ0[4:0] description"
line.long 0x28 "RSQ1,Routine sequence register 1"
hexmask.long.word 0x28 21.--30. 1. "RSMP14,Routine channel sample time"
hexmask.long.byte 0x28 16.--20. 1. "RSQ14,refer to RSQ0[4:0] description"
hexmask.long.word 0x28 5.--14. 1. "RSMP13,Routine channel sample time"
hexmask.long.byte 0x28 0.--4. 1. "RSQ13,refer to RSQ0[4:0] description"
line.long 0x2C "RSQ2,Routine sequence register 2"
hexmask.long.word 0x2C 21.--30. 1. "RSMP12,Routine channel sample time"
hexmask.long.byte 0x2C 16.--20. 1. "RSQ12,refer to RSQ0[4:0] description"
hexmask.long.word 0x2C 5.--14. 1. "RSMP11,Routine channel sample time"
hexmask.long.byte 0x2C 0.--4. 1. "RSQ11,refer to RSQ0[4:0] description"
line.long 0x30 "RSQ3,Routine sequence register 3"
hexmask.long.word 0x30 21.--30. 1. "RSMP10,Routine channel sample time"
hexmask.long.byte 0x30 16.--20. 1. "RSQ10,refer to RSQ0[4:0] description"
hexmask.long.word 0x30 5.--14. 1. "RSMP9,Routine channel sample time"
hexmask.long.byte 0x30 0.--4. 1. "RSQ9,refer to RSQ0[4:0] description"
line.long 0x34 "RSQ4,Routine sequence register 4"
hexmask.long.word 0x34 21.--30. 1. "RSMP8,Routine channel sample time"
hexmask.long.byte 0x34 16.--20. 1. "RSQ8,refer to RSQ0[4:0] description"
hexmask.long.word 0x34 5.--14. 1. "RSMP7,Routine channel sample time"
hexmask.long.byte 0x34 0.--4. 1. "RSQ7,refer to RSQ0[4:0] description"
line.long 0x38 "RSQ5,Routine sequence register 5"
hexmask.long.word 0x38 21.--30. 1. "RSMP6,Routine channel sample time"
hexmask.long.byte 0x38 16.--20. 1. "RSQ6,refer to RSQ0[4:0] description"
hexmask.long.word 0x38 5.--14. 1. "RSMP5,Routine channel sample time"
hexmask.long.byte 0x38 0.--4. 1. "RSQ5,refer to RSQ0[4:0] description"
line.long 0x3C "RSQ6,Routine sequence register 6"
hexmask.long.word 0x3C 21.--30. 1. "RSMP4,Routine channel sample time"
hexmask.long.byte 0x3C 16.--20. 1. "RSQ4,refer to RSQ0[4:0] description"
hexmask.long.word 0x3C 5.--14. 1. "RSMP3,Routine channel sample time"
hexmask.long.byte 0x3C 0.--4. 1. "RSQ3,refer to RSQ0[4:0] description"
line.long 0x40 "RSQ7,Routine sequence register 7"
hexmask.long.word 0x40 21.--30. 1. "RSMP2,Routine channel sample time"
hexmask.long.byte 0x40 16.--20. 1. "RSQ2,refer to RSQ0[4:0] description"
hexmask.long.word 0x40 5.--14. 1. "RSMP1,Routine channel sample time"
hexmask.long.byte 0x40 0.--4. 1. "RSQ1,refer to RSQ0[4:0] description"
line.long 0x44 "RSQ8,Routine sequence register 8"
hexmask.long.word 0x44 5.--14. 1. "RSMP0,Routine channel sample time"
hexmask.long.byte 0x44 0.--4. 1. "RSQ0,The channel number (0"
line.long 0x48 "ISQ0,Inserted sequence register 0"
bitfld.long 0x48 20.--21. "IL,Inserted sequence length" "0,1,2,3"
hexmask.long.word 0x48 5.--14. 1. "ISMP3,Inserted channel sample time"
hexmask.long.byte 0x48 0.--4. 1. "ISQ3,refer to ISQ0[4:0] description"
line.long 0x4C "ISQ1,Inserted sequence register 1"
hexmask.long.word 0x4C 21.--30. 1. "ISMP2,Inserted channel sample time"
hexmask.long.byte 0x4C 16.--20. 1. "ISQ2,refer to ISQ0[4:0] description"
hexmask.long.word 0x4C 5.--14. 1. "ISMP1,Inserted channel sample time"
hexmask.long.byte 0x4C 0.--4. 1. "ISQ1,refer to ISQ0[4:0] description"
line.long 0x50 "ISQ2,Inserted sequence register 2"
hexmask.long.word 0x50 5.--14. 1. "ISMP0,Inserted channel sample time"
hexmask.long.byte 0x50 0.--4. 1. "ISQ0,The channel number (0"
rgroup.long 0x54++0x13
line.long 0x0 "IDATA0,Inserted data registe 0"
hexmask.long 0x0 0.--31. 1. "IDATAn,Inserted number n conversion data"
line.long 0x4 "IDATA1,Inserted data registe 1"
hexmask.long 0x4 0.--31. 1. "IDATAn,Inserted number n conversion data"
line.long 0x8 "IDATA2,Inserted data registe 2"
hexmask.long 0x8 0.--31. 1. "IDATAn,Inserted number n conversion data"
line.long 0xC "IDATA3,Inserted data registe 3"
hexmask.long 0xC 0.--31. 1. "IDATAn,Inserted number n conversion data"
line.long 0x10 "RDATA,Routine data register"
hexmask.long 0x10 0.--31. 1. "RDATA,Routine channel data"
group.long 0x80++0x3
line.long 0x0 "OVSAMPCTL,Oversample control register"
hexmask.long.word 0x0 16.--25. 1. "OVSR,Oversampling ratio"
bitfld.long 0x0 9. "TOVS,Triggered oversampling" "0,1"
hexmask.long.byte 0x0 5.--8. 1. "OVSS,Oversampling shift"
bitfld.long 0x0 0. "OVSEN,Oversampling Enable" "0,1"
group.long 0xA0++0x1B
line.long 0x0 "WD1SR,Watchdog 1 Channel Selection Register"
hexmask.long.tbyte 0x0 0.--21. 1. "AWD1CS,Analog watchdog 1 channel selection"
line.long 0x4 "WD2SR,Watchdog 2 Channel Selection Register"
hexmask.long.tbyte 0x4 0.--21. 1. "AWD2CS,Analog watchdog 2 channel selection"
line.long 0x8 "WDHT1,Watchdog high threshold register1"
hexmask.long.tbyte 0x8 0.--21. 1. "WDHT1,High threshold for analog watchdog 1"
line.long 0xC "WDLT1,Watchdog low threshold register1"
hexmask.long.tbyte 0xC 0.--21. 1. "WDLT1,Low threshold for analog watchdog 1"
line.long 0x10 "WDHT2,Watchdog high threshold register2"
hexmask.long.tbyte 0x10 0.--21. 1. "WDHT2,High threshold for analog watchdog 2"
line.long 0x14 "WDLT2,Watchdog low threshold register2"
hexmask.long.tbyte 0x14 0.--21. 1. "WDLT2,Low threshold for analog watchdog 2"
line.long 0x18 "DIFCTL,Differential mode control register"
hexmask.long.tbyte 0x18 0.--21. 1. "DIFCTL,Differential mode for channel 21"
group.long 0xC0++0x3
line.long 0x0 "GAINCFG,Gain configure register"
hexmask.long.word 0x0 0.--13. 1. "GAIN,Gain factor"
rgroup.long 0x300++0x3
line.long 0x0 "SSTAT,Summary status register"
bitfld.long 0x0 31. "ADC3_ROVF,This bit is the mirror image of the ROVF bit of ADC3" "0,1"
bitfld.long 0x0 30. "ADC3_STRC,This bit is the mirror image of the STRC bit of ADC3" "0,1"
bitfld.long 0x0 29. "ADC3_STIC,This bit is the mirror image of the STIC bit of ADC3" "0,1"
bitfld.long 0x0 28. "ADC3_EOIC,This bit is the mirror image of the EOIC bit of ADC3" "0,1"
bitfld.long 0x0 27. "ADC3_EOC,This bit is the mirror image of the EOC bit of ADC3" "0,1"
bitfld.long 0x0 26. "ADC3_WDE2,This bit is the mirror image of the WDE2 bit of ADC3" "0,1"
bitfld.long 0x0 25. "ADC3_WDE1,This bit is the mirror image of the WDE1 bit of ADC3" "0,1"
bitfld.long 0x0 24. "ADC3_WDE0,This bit is the mirror image of the WDE0 bit of ADC3" "0,1"
group.long 0x304++0x3
line.long 0x0 "SYNCCTL,Sync control register"
hexmask.long.byte 0x0 20.--23. 1. "ADCCK,ADC clock prescaler"
hexmask.long.byte 0x0 16.--19. 1. "ADCSCK,ADC sync clock mode"
bitfld.long 0x0 14.--15. "SYNCDMA,ADC sync DMA mode selection" "0,1,2,3"
bitfld.long 0x0 13. "SYNCDDM,ADC sync DMA disable mode" "0,1"
hexmask.long.byte 0x0 8.--11. 1. "SYNCDLY,ADC sync delay"
hexmask.long.byte 0x0 0.--4. 1. "SYNCM,ADC sync mode"
rgroup.long 0x308++0x3
line.long 0x0 "SYNCDATA,Sync routine data register"
hexmask.long.word 0x0 16.--31. 1. "SYNCDATA1,Routine data 1 in ADC sync mode"
hexmask.long.word 0x0 0.--15. 1. "SYNCDATA0,Routine data 0 in ADC sync mode"
tree.end
tree.end
tree "CAN (Controller Area Network)"
base ad:0x0
tree "CAN0"
base ad:0x4001A000
group.long 0x0++0xB
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 31. "CANDIS,CAN disable" "0,1"
bitfld.long 0x0 30. "INAMOD,Inactive mode enable" "0,1"
bitfld.long 0x0 29. "RFEN,Rx FIFO enable" "0,1"
bitfld.long 0x0 28. "HALT,Halt CAN" "0,1"
rbitfld.long 0x0 27. "NRDY,Not ready" "0,1"
bitfld.long 0x0 25. "SWRST,Software reset" "0,1"
rbitfld.long 0x0 24. "INAS,Inactive mode state" "0,1"
newline
bitfld.long 0x0 21. "WERREN,Error warning enable" "0,1"
rbitfld.long 0x0 20. "LPS,Low power state" "0,1"
bitfld.long 0x0 19. "PNEN,Pretended Networking mode enable" "0,1"
rbitfld.long 0x0 18. "PNS,Pretended Networking state" "0,1"
bitfld.long 0x0 17. "SRDIS,Self reception disable" "0,1"
bitfld.long 0x0 16. "RPFQEN,Rx private filters enable and Rx mailbox queue enable" "0,1"
bitfld.long 0x0 15. "DMAEN,DMA enable" "0,1"
newline
bitfld.long 0x0 14. "PNMOD,Pretended Networking mode selection" "0,1"
bitfld.long 0x0 13. "LAPRIOEN,Local arbitration priority enable" "0,1"
bitfld.long 0x0 12. "MST,Mailbox stop transmission" "0,1"
bitfld.long 0x0 11. "FDEN,CAN FD operation enable" "0,1"
bitfld.long 0x0 8.--9. "FS,Format selection" "0,1,2,3"
hexmask.long.byte 0x0 0.--4. 1. "MSZ,Memory size"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 15. "BOIE,Bus off interrupt enable" "0,1"
bitfld.long 0x4 14. "ERRSIE,Error summary interrupt enable" "0,1"
bitfld.long 0x4 12. "LSCMOD,Loopback and silent communication mode" "0,1"
bitfld.long 0x4 11. "TWERRIE,Tx error warning interrupt enable" "0,1"
bitfld.long 0x4 10. "RWERRIE,Rx error warning interrupt enable" "0,1"
bitfld.long 0x4 8. "BSSSEL,Bit sampling synchronization select" "0,1"
bitfld.long 0x4 7. "BSPMOD,Bit sampling mode" "0,1"
newline
bitfld.long 0x4 6. "ABORDIS,Automatic Bus off recovery not enable" "0,1"
bitfld.long 0x4 5. "TSYNC,Time synchronization enable" "0,1"
bitfld.long 0x4 4. "MTO,Mailbox transmission order" "0,1"
bitfld.long 0x4 3. "MMOD,Monitor mode" "0,1"
line.long 0x8 "TIMER,Timer register"
hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value"
group.long 0x10++0x3
line.long 0x0 "RMPUBF,Receive mailbox public filter register"
bitfld.long 0x0 31. "MFD31,Mailbox filter data" "0,1"
bitfld.long 0x0 30. "MFD30,Mailbox filter data" "0,1"
bitfld.long 0x0 29. "MFD29,Mailbox filter data" "0,1"
bitfld.long 0x0 28. "MFD28,Mailbox filter data" "0,1"
bitfld.long 0x0 27. "MFD27,Mailbox filter data" "0,1"
bitfld.long 0x0 26. "MFD26,Mailbox filter data" "0,1"
bitfld.long 0x0 25. "MFD25,Mailbox filter data" "0,1"
newline
bitfld.long 0x0 24. "MFD24,Mailbox filter data" "0,1"
bitfld.long 0x0 23. "MFD23,Mailbox filter data" "0,1"
bitfld.long 0x0 22. "MFD22,Mailbox filter data" "0,1"
bitfld.long 0x0 21. "MFD21,Mailbox filter data" "0,1"
bitfld.long 0x0 20. "MFD20,Mailbox filter data" "0,1"
bitfld.long 0x0 19. "MFD19,Mailbox filter data" "0,1"
bitfld.long 0x0 18. "MFD18,Mailbox filter data" "0,1"
newline
bitfld.long 0x0 17. "MFD17,Mailbox filter data" "0,1"
bitfld.long 0x0 16. "MFD16,Mailbox filter data" "0,1"
bitfld.long 0x0 15. "MFD15,Mailbox filter data" "0,1"
bitfld.long 0x0 14. "MFD14,Mailbox filter data" "0,1"
bitfld.long 0x0 13. "MFD13,Mailbox filter data" "0,1"
bitfld.long 0x0 12. "MFD12,Mailbox filter data" "0,1"
bitfld.long 0x0 11. "MFD11,Mailbox filter data" "0,1"
newline
bitfld.long 0x0 10. "MFD10,Mailbox filter data" "0,1"
bitfld.long 0x0 9. "MFD9,Mailbox filter data" "0,1"
bitfld.long 0x0 8. "MFD8,Mailbox filter data" "0,1"
bitfld.long 0x0 7. "MFD7,Mailbox filter data" "0,1"
bitfld.long 0x0 6. "MFD6,Mailbox filter data" "0,1"
bitfld.long 0x0 5. "MFD5,Mailbox filter data" "0,1"
bitfld.long 0x0 4. "MFD4,Mailbox filter data" "0,1"
newline
bitfld.long 0x0 3. "MFD3,Mailbox filter data" "0,1"
bitfld.long 0x0 2. "MFD2,Mailbox filter data" "0,1"
bitfld.long 0x0 1. "MFD1,Mailbox filter data" "0,1"
bitfld.long 0x0 0. "MFD0,Mailbox filter data" "0,1"
group.long 0x1C++0x7
line.long 0x0 "ERR0,Error register 0"
hexmask.long.byte 0x0 24.--31. 1. "REFCNT,Receive error counter for data phase of FD frames with BRS bit set"
hexmask.long.byte 0x0 16.--23. 1. "TEFCNT,Transmit error count for the data phase of FD frames with BRS bit set"
hexmask.long.byte 0x0 8.--15. 1. "RECNT,Receive error count defined by the CAN standard"
hexmask.long.byte 0x0 0.--7. 1. "TECNT,Transmit error count defined by the CAN standard"
line.long 0x4 "ERR1,Error register 1"
bitfld.long 0x4 31. "BRFERR,Bit recessive error in data phase of FD frames with the BRS bit set" "0,1"
bitfld.long 0x4 30. "BDFERR,Bit dominant error in data phase of FD frames with the BRS bit set" "0,1"
bitfld.long 0x4 28. "CRCFERR,CRC error in data phase of FD frames with the BRS bit set" "0,1"
bitfld.long 0x4 27. "FMFERR,Form error in data phase of FD frames with the BRS bit set" "0,1"
bitfld.long 0x4 26. "STFFERR,Stuff error in data phase of FD frames with the BRS bit set" "0,1"
bitfld.long 0x4 21. "ERROVR,Error overrun" "0,1"
bitfld.long 0x4 20. "ERRFSF,Error summary flag for data phase of FD frames with BRS bit set" "0,1"
newline
bitfld.long 0x4 19. "BORF,Bus off recovery flag" "0,1"
rbitfld.long 0x4 18. "SYN,Synchronization flag" "0,1"
bitfld.long 0x4 17. "TWERRIF,Tx error warning interrupt flag" "0,1"
bitfld.long 0x4 16. "RWERRIF,Rx error warning interrupt flag" "0,1"
bitfld.long 0x4 15. "BRERR,Bit recessive error for all format frames" "0,1"
bitfld.long 0x4 14. "BDERR,Bit dominant error for all format frames" "0,1"
bitfld.long 0x4 13. "ACKERR,ACK error" "0,1"
newline
bitfld.long 0x4 12. "CRCERR,CRC error" "0,1"
bitfld.long 0x4 11. "FMERR,Form error" "0,1"
bitfld.long 0x4 10. "STFERR,Stuff error" "0,1"
rbitfld.long 0x4 9. "TWERRF,Tx error warning flag" "0,1"
rbitfld.long 0x4 8. "RWERRF,Rx error warning flag" "0,1"
rbitfld.long 0x4 7. "IDLEF,IDLE flag" "0,1"
rbitfld.long 0x4 6. "TS,Transmitting state" "0,1"
newline
rbitfld.long 0x4 4.--5. "ERRSI,Error state indicator" "0,1,2,3"
rbitfld.long 0x4 3. "RS,Receiving state" "0,1"
bitfld.long 0x4 2. "BOF,Bus off flag" "0,1"
bitfld.long 0x4 1. "ERRSF,Error summary flag" "0,1"
group.long 0x28++0x3
line.long 0x0 "INTEN,Interrupt enable register"
bitfld.long 0x0 31. "MIE31,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 30. "MIE30,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 29. "MIE29,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 28. "MIE28,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 27. "MIE27,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 26. "MIE26,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 25. "MIE25,Message transmission and reception interrupt enable" "0,1"
newline
bitfld.long 0x0 24. "MIE24,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 23. "MIE23,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 22. "MIE22,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 21. "MIE21,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 20. "MIE20,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 19. "MIE19,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 18. "MIE18,Message transmission and reception interrupt enable" "0,1"
newline
bitfld.long 0x0 17. "MIE17,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 16. "MIE16,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 15. "MIE15,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 14. "MIE14,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 13. "MIE13,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 12. "MIE12,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 11. "MIE11,Message transmission and reception interrupt enable" "0,1"
newline
bitfld.long 0x0 10. "MIE10,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 9. "MIE9,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 8. "MIE8,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 7. "MIE7,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 6. "MIE6,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 5. "MIE5,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 4. "MIE4,Message transmission and reception interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "MIE3,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 2. "MIE2,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 1. "MIE1,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 0. "MIE0,Message transmission and reception interrupt enable" "0,1"
group.long 0x30++0x7
line.long 0x0 "STAT,Status register"
bitfld.long 0x0 31. "MS31,Mailbox 23 state" "0,1"
bitfld.long 0x0 30. "MS30,Mailbox 22 state" "0,1"
bitfld.long 0x0 29. "MS29,Mailbox 21 state" "0,1"
bitfld.long 0x0 28. "MS28,Mailbox 20 state" "0,1"
bitfld.long 0x0 27. "MS27,Mailbox 19 state" "0,1"
bitfld.long 0x0 26. "MS26,Mailbox 18 state" "0,1"
bitfld.long 0x0 25. "MS25,Mailbox 17 state" "0,1"
newline
bitfld.long 0x0 24. "MS24,Mailbox 16 state" "0,1"
bitfld.long 0x0 23. "MS23,Mailbox 15 state" "0,1"
bitfld.long 0x0 22. "MS22,Mailbox 14 state" "0,1"
bitfld.long 0x0 21. "MS21,Mailbox 13 state" "0,1"
bitfld.long 0x0 20. "MS20,Mailbox 12 state" "0,1"
bitfld.long 0x0 19. "MS19,Mailbox 11 state" "0,1"
bitfld.long 0x0 18. "MS18,Mailbox 10 state" "0,1"
newline
bitfld.long 0x0 17. "MS17,Mailbox 9 state" "0,1"
bitfld.long 0x0 16. "MS16,Mailbox 8 state" "0,1"
bitfld.long 0x0 15. "MS15,Mailbox 7 state" "0,1"
bitfld.long 0x0 14. "MS14,Mailbox 6 state" "0,1"
bitfld.long 0x0 13. "MS13,Mailbox 5 state" "0,1"
bitfld.long 0x0 12. "MS12,Mailbox 4 state" "0,1"
bitfld.long 0x0 11. "MS11,Mailbox 3 state" "0,1"
newline
bitfld.long 0x0 10. "MS10,Mailbox 2 state" "0,1"
bitfld.long 0x0 9. "MS9,Mailbox 1 state" "0,1"
bitfld.long 0x0 8. "MS8,Mailbox 0 state" "0,1"
bitfld.long 0x0 7. "MS7_RFO,Mailbox 7 state / Rx FIFO overflow" "0,1"
bitfld.long 0x0 6. "MS6_RFW,Mailbox 6 state / Rx FIFO warning" "0,1"
bitfld.long 0x0 5. "MS5_RFNE,Mailbox 5 state / Rx FIFO not empty" "0,1"
bitfld.long 0x0 4. "MS4_RES,Mailbox 4 state / Reserved" "0,1"
newline
bitfld.long 0x0 3. "MS3_RES,Mailbox 3 state / Reserved" "0,1"
bitfld.long 0x0 2. "MS2_RES,Mailbox 2 state / Reserved" "0,1"
bitfld.long 0x0 1. "MS1_RES,Mailbox 1 state / Reserved" "0,1"
bitfld.long 0x0 0. "MS0_RFC,Mailbox 0 state / Clear Rx FIFO bit" "0,1"
line.long 0x4 "CTL2,Control register 2"
bitfld.long 0x4 31. "ERRFSIE,Error summary interrupt enable bit for data phase of FD frames with BRS bit set" "0,1"
bitfld.long 0x4 30. "BORIE,Bus off recovery interrupt enable" "0,1"
hexmask.long.byte 0x4 24.--27. 1. "RFFN,Rx FIFO filter number"
hexmask.long.byte 0x4 19.--23. 1. "ASD,Arbitration start delay"
bitfld.long 0x4 18. "RFO,Receive filter order" "0,1"
bitfld.long 0x4 17. "RRFRMS,Remote request frame is stored" "0,1"
bitfld.long 0x4 16. "IDERTR_RMF,IDE and RTR field filter type for Rx mailbox reception" "0,1"
newline
bitfld.long 0x4 15. "ITSRC,Internal counter source" "0,1"
bitfld.long 0x4 14. "PREEN,Protocol exception detection enable by CAN standard" "0,1"
bitfld.long 0x4 12. "ISO,ISO CAN FD" "0,1"
bitfld.long 0x4 11. "EFDIS,Edge filtering disable" "0,1"
rgroup.long 0x44++0x3
line.long 0x0 "CRCC,CRC for classical frame register"
hexmask.long.byte 0x0 16.--20. 1. "ANTM,Associated number of mailbox for transmitting the CRCTC[14:0] value"
hexmask.long.word 0x0 0.--14. 1. "CRCTC,Transmitted CRC value for classical frames"
group.long 0x48++0x3
line.long 0x0 "RFIFOPUBF,Receive FIFO public filter register"
bitfld.long 0x0 31. "FFD31,Rx FIFO filter data" "0,1"
bitfld.long 0x0 30. "FFD30,Rx FIFO filter data" "0,1"
bitfld.long 0x0 29. "FFD29,Rx FIFO filter data" "0,1"
bitfld.long 0x0 27.--28. "FFD27,Rx FIFO filter data" "0,1,2,3"
bitfld.long 0x0 26. "FFD26,Rx FIFO filter data" "0,1"
bitfld.long 0x0 25. "FFD25,Rx FIFO filter data" "0,1"
bitfld.long 0x0 24. "FFD24,Rx FIFO filter data" "0,1"
newline
bitfld.long 0x0 23. "FFD23,Rx FIFO filter data" "0,1"
bitfld.long 0x0 22. "FFD22,Rx FIFO filter data" "0,1"
bitfld.long 0x0 21. "FFD21,Rx FIFO filter data" "0,1"
bitfld.long 0x0 20. "FFD20,Rx FIFO filter data" "0,1"
bitfld.long 0x0 19. "FFD19,Rx FIFO filter data" "0,1"
bitfld.long 0x0 18. "FFD18,Rx FIFO filter data" "0,1"
bitfld.long 0x0 17. "FFD17,Rx FIFO filter data" "0,1"
newline
bitfld.long 0x0 16. "FFD16,Rx FIFO filter data" "0,1"
bitfld.long 0x0 15. "FFD15,Rx FIFO filter data" "0,1"
bitfld.long 0x0 14. "FFD14,Rx FIFO filter data" "0,1"
bitfld.long 0x0 13. "FFD13,Rx FIFO filter data" "0,1"
bitfld.long 0x0 12. "FFD12,Rx FIFO filter data" "0,1"
bitfld.long 0x0 11. "FFD11,Rx FIFO filter data" "0,1"
bitfld.long 0x0 10. "FFD10,Rx FIFO filter data" "0,1"
newline
bitfld.long 0x0 9. "FFD9,Rx FIFO filter data" "0,1"
bitfld.long 0x0 8. "FFD8,Rx FIFO filter data" "0,1"
bitfld.long 0x0 7. "FFD7,Rx FIFO filter data" "0,1"
bitfld.long 0x0 6. "FFD6,Rx FIFO filter data" "0,1"
bitfld.long 0x0 5. "FFD5,Rx FIFO filter data" "0,1"
bitfld.long 0x0 4. "FFD4,Rx FIFO filter data" "0,1"
bitfld.long 0x0 3. "FFD3,Rx FIFO filter data" "0,1"
newline
bitfld.long 0x0 2. "FFD2,Rx FIFO filter data" "0,1"
bitfld.long 0x0 1. "FFD1,Rx FIFO filter data" "0,1"
bitfld.long 0x0 0. "FFD0,Rx FIFO filter data" "0,1"
rgroup.long 0x4C++0x3
line.long 0x0 "RFIFOIFMN,Receive FIFO identifier filter matching number register"
hexmask.long.word 0x0 0.--8. 1. "IDFMN,Identifier filter matching number"
group.long 0x50++0x3
line.long 0x0 "BT,Bit timing register"
hexmask.long.word 0x0 21.--30. 1. "BAUDPSC,Baud rate prescaler"
hexmask.long.byte 0x0 16.--20. 1. "SJW,Resynchronization jump width"
hexmask.long.byte 0x0 10.--15. 1. "PTS,Propagation time segment"
hexmask.long.byte 0x0 5.--9. 1. "PBS1,Phase buffer segment 1"
hexmask.long.byte 0x0 0.--4. 1. "PBS2,Phase buffer segment 2"
group.long 0x880++0x7F
line.long 0x0 "RFIFOMPF0,Receive FIFO/mailbox private filter 0 register"
bitfld.long 0x0 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x0 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x0 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x0 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x0 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x0 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x4 "RFIFOMPF1,Receive FIFO/mailbox private filter 1 register"
bitfld.long 0x4 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x4 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x8 "RFIFOMPF2,Receive FIFO/mailbox private filter 2 register"
bitfld.long 0x8 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x8 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x8 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x8 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x8 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x8 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0xC "RFIFOMPF3,Receive FIFO/mailbox private filter 3 register"
bitfld.long 0xC 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0xC 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0xC 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0xC 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0xC 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0xC 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x10 "RFIFOMPF4,Receive FIFO/mailbox private filter 4 register"
bitfld.long 0x10 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x10 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x10 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x10 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x10 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x10 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x14 "RFIFOMPF5,Receive FIFO/mailbox private filter 5 register"
bitfld.long 0x14 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x14 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x14 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x14 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x14 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x14 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x18 "RFIFOMPF6,Receive FIFO/mailbox private filter 6 register"
bitfld.long 0x18 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x18 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x18 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x18 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x18 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x18 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x1C "RFIFOMPF7,Receive FIFO/mailbox private filter 7 register"
bitfld.long 0x1C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x1C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x1C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x1C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x1C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x1C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x20 "RFIFOMPF8,Receive FIFO/mailbox private filter 8 register"
bitfld.long 0x20 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x20 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x20 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x20 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x20 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x20 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x24 "RFIFOMPF9,Receive FIFO/mailbox private filter 9 register"
bitfld.long 0x24 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x24 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x24 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x24 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x24 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x24 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x28 "RFIFOMPF10,Receive FIFO/mailbox private filter 10 register"
bitfld.long 0x28 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x28 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x28 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x28 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x28 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x28 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x2C "RFIFOMPF11,Receive FIFO/mailbox private filter 11 register"
bitfld.long 0x2C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x2C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x2C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x2C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x2C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x2C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x30 "RFIFOMPF12,Receive FIFO/mailbox private filter 12 register"
bitfld.long 0x30 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x30 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x30 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x30 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x30 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x30 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x34 "RFIFOMPF13,Receive FIFO/mailbox private filter 13 register"
bitfld.long 0x34 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x34 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x34 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x34 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x34 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x34 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x38 "RFIFOMPF14,Receive FIFO/mailbox private filter 14 register"
bitfld.long 0x38 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x38 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x38 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x38 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x38 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x38 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x3C "RFIFOMPF15,Receive FIFO/mailbox private filter 15 register"
bitfld.long 0x3C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x3C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x3C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x3C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x3C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x3C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x40 "RFIFOMPF16,Receive FIFO/mailbox private filter 16 register"
bitfld.long 0x40 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x40 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x40 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x40 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x40 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x40 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x44 "RFIFOMPF17,Receive FIFO/mailbox private filter 17 register"
bitfld.long 0x44 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x44 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x44 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x44 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x44 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x44 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x48 "RFIFOMPF18,Receive FIFO/mailbox private filter 18 register"
bitfld.long 0x48 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x48 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x48 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x48 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x48 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x48 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x4C "RFIFOMPF19,Receive FIFO/mailbox private filter 19 register"
bitfld.long 0x4C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x4C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x50 "RFIFOMPF20,Receive FIFO/mailbox private filter 20 register"
bitfld.long 0x50 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x50 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x50 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x50 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x50 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x50 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x54 "RFIFOMPF21,Receive FIFO/mailbox private filter 21 register"
bitfld.long 0x54 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x54 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x54 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x54 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x54 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x54 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x58 "RFIFOMPF22,Receive FIFO/mailbox private filter 22 register"
bitfld.long 0x58 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x58 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x58 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x58 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x58 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x58 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x5C "RFIFOMPF23,Receive FIFO/mailbox private filter 23 register"
bitfld.long 0x5C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x5C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x5C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x5C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x5C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x5C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x60 "RFIFOMPF24,Receive FIFO/mailbox private filter 24 register"
bitfld.long 0x60 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x60 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x60 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x60 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x60 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x60 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x64 "RFIFOMPF25,Receive FIFO/mailbox private filter 25 register"
bitfld.long 0x64 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x64 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x64 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x64 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x64 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x64 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x68 "RFIFOMPF26,Receive FIFO/mailbox private filter 26 register"
bitfld.long 0x68 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x68 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x68 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x68 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x68 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x68 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x6C "RFIFOMPF27,Receive FIFO/mailbox private filter 27 register"
bitfld.long 0x6C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x6C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x6C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x6C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x6C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x6C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x70 "RFIFOMPF28,Receive FIFO/mailbox private filter 28 register"
bitfld.long 0x70 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x70 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x70 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x70 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x70 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x70 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x74 "RFIFOMPF29,Receive FIFO/mailbox private filter 29 register"
bitfld.long 0x74 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x74 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x74 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x74 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x74 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x74 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x78 "RFIFOMPF30,Receive FIFO/mailbox private filter 30 register"
bitfld.long 0x78 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x78 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x78 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x78 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x78 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x78 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x7C "RFIFOMPF31,Receive FIFO/mailbox private filter 31 register"
bitfld.long 0x7C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x7C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x7C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x7C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x7C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x7C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
group.long 0xB00++0x27
line.long 0x0 "PN_CTL0,Pretended Networking mode control register 0"
bitfld.long 0x0 17. "WTOIE,Wakeup timeout interrupt enable" "0,1"
bitfld.long 0x0 16. "WMIE,Wakeup match interrupt enable" "0,1"
hexmask.long.byte 0x0 8.--15. 1. "NMM,Number of messages matching times"
bitfld.long 0x0 4.--5. "DATAFT,DATA field filtering type in Pretended Networking mode" "0,1,2,3"
bitfld.long 0x0 2.--3. "IDFT,ID field filtering type in Pretended Networking mode" "0,1,2,3"
bitfld.long 0x0 0.--1. "FFT,Frame filtering type in Pretended Networking mode" "0,1,2,3"
line.long 0x4 "PN_TO,Pretended Networking mode timeout register"
hexmask.long.word 0x4 0.--15. 1. "WTO,Wakeup timeout"
line.long 0x8 "PN_STAT,Pretended Networking mode status register"
bitfld.long 0x8 17. "WTOS,Wakeup timeout flag status" "0,1"
bitfld.long 0x8 16. "WMS,Wakeup match flag status" "0,1"
hexmask.long.byte 0x8 8.--15. 1. "MMCNT,Matching message counter in Pretended Networking mode"
rbitfld.long 0x8 7. "MMCNTS,Matching message counter state" "0,1"
line.long 0xC "PN_EID0,Pretended Networking mode expected identifier 0 register"
bitfld.long 0xC 30. "EIDE,Expected IDE in Pretended Networking mode" "0,1"
bitfld.long 0xC 29. "ERTR,Expected RTR in Pretended Networking mode" "0,1"
hexmask.long 0xC 0.--28. 1. "EID_ELT,Expected ID field / expected ID low threshold in Pretended Networking mode"
line.long 0x10 "PN_EDLC,Pretended Networking mode expected DLC register"
hexmask.long.byte 0x10 16.--19. 1. "DLCELT,DLC expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x10 0.--3. 1. "DLCEHT,DLC expected high threshold in Pretended Networking mode"
line.long 0x14 "PN_EDL0,Pretended Networking mode expected data low 0 register"
hexmask.long.byte 0x14 24.--31. 1. "DB0ELT,Data byte 0 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x14 16.--23. 1. "DB1ELT,Data byte 1 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x14 8.--15. 1. "DB2ELT,Data byte 2 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x14 0.--7. 1. "DB3ELT,Data byte 3 expected low threshold in Pretended Networking mode"
line.long 0x18 "PN_EDL1,Pretended Networking mode expected data low 1 register"
hexmask.long.byte 0x18 24.--31. 1. "DB4ELT,Data byte 4 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x18 16.--23. 1. "DB5ELT,Data byte 5 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x18 8.--15. 1. "DB6ELT,Data byte 6 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x18 0.--7. 1. "DB7ELT,Data byte 7 expected low threshold in Pretended Networking mode"
line.long 0x1C "PN_IFEID1,Pretended Networking mode identifier filter / expected identifier 1 register"
bitfld.long 0x1C 30. "IDEFD,IDE filter data in Pretended Networking mode" "0,1"
bitfld.long 0x1C 29. "RTRFD,RTR filter data in Pretended Networking mode" "0,1"
hexmask.long 0x1C 0.--28. 1. "IDFD_EHT,ID filter data / ID expected high threshold in Pretended Networking mode"
line.long 0x20 "PN_DF0EDH0,Pretended Networking mode data 0 filter / expected data high 0 register"
hexmask.long.byte 0x20 24.--31. 1. "DB0FD_EHT,Data byte 0 filter data / Data byte 0 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x20 16.--23. 1. "DB1FD_EHT,Data byte 1 filter data / Data byte 1 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x20 8.--15. 1. "DB2FD_EHT,Data byte 2 filter data / Data byte 2 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x20 0.--7. 1. "DB3FD_EHT,Data byte 3 filter data / Data byte 2 expected high threshold in Pretended Networking mode"
line.long 0x24 "PN_DF1EDH1,Pretended Networking mode data 1 filter / expected data high 1 register"
hexmask.long.byte 0x24 24.--31. 1. "DB4FD_HTF,Data byte 4 filter data / Data byte 4 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x24 16.--23. 1. "DB5FD_HTF,Data byte 5 filter data / Data byte 5 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x24 8.--15. 1. "DB6FD_HTF,Data byte 6 filter data / Data byte 6 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x24 0.--7. 1. "DB7FD_HTF,Data byte 7 filter data / Data byte 7 expected high threshold in Pretended Networking mode"
rgroup.long 0xB40++0x3F
line.long 0x0 "PN_RWM0CS,Pretended Networking mode received wakeup mailbox 0 control status information register"
bitfld.long 0x0 22. "RSRR,Received SRR bit" "0,1"
bitfld.long 0x0 21. "RIDE,Received IDE bit" "0,1"
bitfld.long 0x0 20. "RRTR,Received RTR bit" "0,1"
hexmask.long.byte 0x0 16.--19. 1. "RDLC,Received DLC bits"
line.long 0x4 "PN_RWM0I,Pretended Networking mode received wakeup mailbox 0 identifier register"
hexmask.long 0x4 0.--28. 1. "RID,Received ID bits"
line.long 0x8 "PN_RWM0D0,Pretended Networking mode received wakeup mailbox 0 data 0 register"
hexmask.long.byte 0x8 24.--31. 1. "RDB0,Received data byte 0"
hexmask.long.byte 0x8 16.--23. 1. "RDB1,Received data byte 1"
hexmask.long.byte 0x8 8.--15. 1. "RDB2,Received data byte 2"
hexmask.long.byte 0x8 0.--7. 1. "RDB3,Received data byte 3"
line.long 0xC "PN_RWM0D1,Pretended Networking mode received wakeup mailbox 0 data 1 register"
hexmask.long.byte 0xC 24.--31. 1. "RDB4,Received data byte 4"
hexmask.long.byte 0xC 16.--23. 1. "RDB5,Received data byte 5"
hexmask.long.byte 0xC 8.--15. 1. "RDB6,Received data byte 6"
hexmask.long.byte 0xC 0.--7. 1. "RDB7,Received data byte 7"
line.long 0x10 "PN_RWM1CS,Pretended Networking mode received wakeup mailbox 1 control status information register"
bitfld.long 0x10 22. "RSRR,Received SRR bit" "0,1"
bitfld.long 0x10 21. "RIDE,Received IDE bit" "0,1"
bitfld.long 0x10 20. "RRTR,Received RTR bit" "0,1"
hexmask.long.byte 0x10 16.--19. 1. "RDLC,Received DLC bits"
line.long 0x14 "PN_RWM1I,Pretended Networking mode received wakeup mailbox 1 identifier register"
hexmask.long 0x14 0.--28. 1. "RID,Received ID bits"
line.long 0x18 "PN_RWM1D0,Pretended Networking mode received wakeup mailbox 1 data 0 register"
hexmask.long.byte 0x18 24.--31. 1. "RDB0,Received data byte 0"
hexmask.long.byte 0x18 16.--23. 1. "RDB1,Received data byte 1"
hexmask.long.byte 0x18 8.--15. 1. "RDB2,Received data byte 2"
hexmask.long.byte 0x18 0.--7. 1. "RDB3,Received data byte 3"
line.long 0x1C "PN_RWM1D1,Pretended Networking mode received wakeup mailbox 1 data 1 register"
hexmask.long.byte 0x1C 24.--31. 1. "RDB4,Received data byte 4"
hexmask.long.byte 0x1C 16.--23. 1. "RDB5,Received data byte 5"
hexmask.long.byte 0x1C 8.--15. 1. "RDB6,Received data byte 6"
hexmask.long.byte 0x1C 0.--7. 1. "RDB7,Received data byte 7"
line.long 0x20 "PN_RWM2CS,Pretended Networking mode received wakeup mailbox 2 control status information register"
bitfld.long 0x20 22. "RSRR,Received SRR bit" "0,1"
bitfld.long 0x20 21. "RIDE,Received IDE bit" "0,1"
bitfld.long 0x20 20. "RRTR,Received RTR bit" "0,1"
hexmask.long.byte 0x20 16.--19. 1. "RDLC,Received DLC bits"
line.long 0x24 "PN_RWM2I,Pretended Networking mode received wakeup mailbox 2 identifier register"
hexmask.long 0x24 0.--28. 1. "RID,Received ID bits"
line.long 0x28 "PN_RWM2D0,Pretended Networking mode received wakeup mailbox 2 data 0 register"
hexmask.long.byte 0x28 24.--31. 1. "RDB0,Received data byte 0"
hexmask.long.byte 0x28 16.--23. 1. "RDB1,Received data byte 1"
hexmask.long.byte 0x28 8.--15. 1. "RDB2,Received data byte 2"
hexmask.long.byte 0x28 0.--7. 1. "RDB3,Received data byte 3"
line.long 0x2C "PN_RWM2D1,Pretended Networking mode received wakeup mailbox 2 data 1 register"
hexmask.long.byte 0x2C 24.--31. 1. "RDB4,Received data byte 4"
hexmask.long.byte 0x2C 16.--23. 1. "RDB5,Received data byte 5"
hexmask.long.byte 0x2C 8.--15. 1. "RDB6,Received data byte 6"
hexmask.long.byte 0x2C 0.--7. 1. "RDB7,Received data byte 7"
line.long 0x30 "PN_RWM3CS,Pretended Networking mode received wakeup mailbox 3 control status information register"
bitfld.long 0x30 22. "RSRR,Received SRR bit" "0,1"
bitfld.long 0x30 21. "RIDE,Received IDE bit" "0,1"
bitfld.long 0x30 20. "RRTR,Received RTR bit" "0,1"
hexmask.long.byte 0x30 16.--19. 1. "RDLC,Received DLC bits"
line.long 0x34 "PN_RWM3I,Pretended Networking mode received wakeup mailbox 3 identifier register"
hexmask.long 0x34 0.--28. 1. "RID,Received ID bits"
line.long 0x38 "PN_RWM3D0,Pretended Networking mode received wakeup mailbox 3 data 0 register"
hexmask.long.byte 0x38 24.--31. 1. "RDB0,Received data byte 0"
hexmask.long.byte 0x38 16.--23. 1. "RDB1,Received data byte 1"
hexmask.long.byte 0x38 8.--15. 1. "RDB2,Received data byte 2"
hexmask.long.byte 0x38 0.--7. 1. "RDB3,Received data byte 3"
line.long 0x3C "PN_RWM3D1,Pretended Networking mode received wakeup mailbox 3 data 1 register"
hexmask.long.byte 0x3C 24.--31. 1. "RDB4,Received data byte 4"
hexmask.long.byte 0x3C 16.--23. 1. "RDB5,Received data byte 5"
hexmask.long.byte 0x3C 8.--15. 1. "RDB6,Received data byte 6"
hexmask.long.byte 0x3C 0.--7. 1. "RDB7,Received data byte 7"
group.long 0xC00++0x7
line.long 0x0 "FDCTL,FD control register"
bitfld.long 0x0 31. "BRSEN,Bit rate of data switch enable" "0,1"
bitfld.long 0x0 16.--17. "MDSZ,Mailbox data size" "0,1,2,3"
bitfld.long 0x0 15. "TDCEN,Transmitter delay compensation enable" "0,1"
bitfld.long 0x0 14. "TDCS,Transmitter delay compensation status" "0,1"
hexmask.long.byte 0x0 8.--12. 1. "TDCO,Transmitter delay compensation offset"
hexmask.long.byte 0x0 0.--5. 1. "TDCV,Transmitter delay compensation value"
line.long 0x4 "FDBT,FD bit timing register"
hexmask.long.word 0x4 20.--29. 1. "DBAUDPSC,Baud rate prescaler for data bit time"
bitfld.long 0x4 16.--18. "DSJW,Resynchronization jump width for data bit time" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 10.--14. 1. "DPTS,Propagation time segment for data bit time"
bitfld.long 0x4 5.--7. "DPBS1,Phase buffer segment 1 for data bit time" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "DPBS2,Phase buffer segment 2 for data bit time" "0,1,2,3,4,5,6,7"
rgroup.long 0xC08++0x3
line.long 0x0 "CRCCFD,CRC for classical and FD frame register"
hexmask.long.byte 0x0 24.--28. 1. "ANTM,Associated number of mailbox for transmitting the CRCTCI[20:0] value"
hexmask.long.tbyte 0x0 0.--20. 1. "CRCTCI,Transmitted CRC value for classical and ISO / non-ISO FD frames"
tree.end
tree "CAN1"
base ad:0x4001B000
group.long 0x0++0xB
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 31. "CANDIS,CAN disable" "0,1"
bitfld.long 0x0 30. "INAMOD,Inactive mode enable" "0,1"
bitfld.long 0x0 29. "RFEN,Rx FIFO enable" "0,1"
bitfld.long 0x0 28. "HALT,Halt CAN" "0,1"
rbitfld.long 0x0 27. "NRDY,Not ready" "0,1"
bitfld.long 0x0 25. "SWRST,Software reset" "0,1"
rbitfld.long 0x0 24. "INAS,Inactive mode state" "0,1"
newline
bitfld.long 0x0 21. "WERREN,Error warning enable" "0,1"
rbitfld.long 0x0 20. "LPS,Low power state" "0,1"
bitfld.long 0x0 19. "PNEN,Pretended Networking mode enable" "0,1"
rbitfld.long 0x0 18. "PNS,Pretended Networking state" "0,1"
bitfld.long 0x0 17. "SRDIS,Self reception disable" "0,1"
bitfld.long 0x0 16. "RPFQEN,Rx private filters enable and Rx mailbox queue enable" "0,1"
bitfld.long 0x0 15. "DMAEN,DMA enable" "0,1"
newline
bitfld.long 0x0 14. "PNMOD,Pretended Networking mode selection" "0,1"
bitfld.long 0x0 13. "LAPRIOEN,Local arbitration priority enable" "0,1"
bitfld.long 0x0 12. "MST,Mailbox stop transmission" "0,1"
bitfld.long 0x0 11. "FDEN,CAN FD operation enable" "0,1"
bitfld.long 0x0 8.--9. "FS,Format selection" "0,1,2,3"
hexmask.long.byte 0x0 0.--4. 1. "MSZ,Memory size"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 15. "BOIE,Bus off interrupt enable" "0,1"
bitfld.long 0x4 14. "ERRSIE,Error summary interrupt enable" "0,1"
bitfld.long 0x4 12. "LSCMOD,Loopback and silent communication mode" "0,1"
bitfld.long 0x4 11. "TWERRIE,Tx error warning interrupt enable" "0,1"
bitfld.long 0x4 10. "RWERRIE,Rx error warning interrupt enable" "0,1"
bitfld.long 0x4 8. "BSSSEL,Bit sampling synchronization select" "0,1"
bitfld.long 0x4 7. "BSPMOD,Bit sampling mode" "0,1"
newline
bitfld.long 0x4 6. "ABORDIS,Automatic Bus off recovery not enable" "0,1"
bitfld.long 0x4 5. "TSYNC,Time synchronization enable" "0,1"
bitfld.long 0x4 4. "MTO,Mailbox transmission order" "0,1"
bitfld.long 0x4 3. "MMOD,Monitor mode" "0,1"
line.long 0x8 "TIMER,Timer register"
hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value"
group.long 0x10++0x3
line.long 0x0 "RMPUBF,Receive mailbox public filter register"
bitfld.long 0x0 31. "MFD31,Mailbox filter data" "0,1"
bitfld.long 0x0 30. "MFD30,Mailbox filter data" "0,1"
bitfld.long 0x0 29. "MFD29,Mailbox filter data" "0,1"
bitfld.long 0x0 28. "MFD28,Mailbox filter data" "0,1"
bitfld.long 0x0 27. "MFD27,Mailbox filter data" "0,1"
bitfld.long 0x0 26. "MFD26,Mailbox filter data" "0,1"
bitfld.long 0x0 25. "MFD25,Mailbox filter data" "0,1"
newline
bitfld.long 0x0 24. "MFD24,Mailbox filter data" "0,1"
bitfld.long 0x0 23. "MFD23,Mailbox filter data" "0,1"
bitfld.long 0x0 22. "MFD22,Mailbox filter data" "0,1"
bitfld.long 0x0 21. "MFD21,Mailbox filter data" "0,1"
bitfld.long 0x0 20. "MFD20,Mailbox filter data" "0,1"
bitfld.long 0x0 19. "MFD19,Mailbox filter data" "0,1"
bitfld.long 0x0 18. "MFD18,Mailbox filter data" "0,1"
newline
bitfld.long 0x0 17. "MFD17,Mailbox filter data" "0,1"
bitfld.long 0x0 16. "MFD16,Mailbox filter data" "0,1"
bitfld.long 0x0 15. "MFD15,Mailbox filter data" "0,1"
bitfld.long 0x0 14. "MFD14,Mailbox filter data" "0,1"
bitfld.long 0x0 13. "MFD13,Mailbox filter data" "0,1"
bitfld.long 0x0 12. "MFD12,Mailbox filter data" "0,1"
bitfld.long 0x0 11. "MFD11,Mailbox filter data" "0,1"
newline
bitfld.long 0x0 10. "MFD10,Mailbox filter data" "0,1"
bitfld.long 0x0 9. "MFD9,Mailbox filter data" "0,1"
bitfld.long 0x0 8. "MFD8,Mailbox filter data" "0,1"
bitfld.long 0x0 7. "MFD7,Mailbox filter data" "0,1"
bitfld.long 0x0 6. "MFD6,Mailbox filter data" "0,1"
bitfld.long 0x0 5. "MFD5,Mailbox filter data" "0,1"
bitfld.long 0x0 4. "MFD4,Mailbox filter data" "0,1"
newline
bitfld.long 0x0 3. "MFD3,Mailbox filter data" "0,1"
bitfld.long 0x0 2. "MFD2,Mailbox filter data" "0,1"
bitfld.long 0x0 1. "MFD1,Mailbox filter data" "0,1"
bitfld.long 0x0 0. "MFD0,Mailbox filter data" "0,1"
group.long 0x1C++0x7
line.long 0x0 "ERR0,Error register 0"
hexmask.long.byte 0x0 24.--31. 1. "REFCNT,Receive error counter for data phase of FD frames with BRS bit set"
hexmask.long.byte 0x0 16.--23. 1. "TEFCNT,Transmit error count for the data phase of FD frames with BRS bit set"
hexmask.long.byte 0x0 8.--15. 1. "RECNT,Receive error count defined by the CAN standard"
hexmask.long.byte 0x0 0.--7. 1. "TECNT,Transmit error count defined by the CAN standard"
line.long 0x4 "ERR1,Error register 1"
bitfld.long 0x4 31. "BRFERR,Bit recessive error in data phase of FD frames with the BRS bit set" "0,1"
bitfld.long 0x4 30. "BDFERR,Bit dominant error in data phase of FD frames with the BRS bit set" "0,1"
bitfld.long 0x4 28. "CRCFERR,CRC error in data phase of FD frames with the BRS bit set" "0,1"
bitfld.long 0x4 27. "FMFERR,Form error in data phase of FD frames with the BRS bit set" "0,1"
bitfld.long 0x4 26. "STFFERR,Stuff error in data phase of FD frames with the BRS bit set" "0,1"
bitfld.long 0x4 21. "ERROVR,Error overrun" "0,1"
bitfld.long 0x4 20. "ERRFSF,Error summary flag for data phase of FD frames with BRS bit set" "0,1"
newline
bitfld.long 0x4 19. "BORF,Bus off recovery flag" "0,1"
rbitfld.long 0x4 18. "SYN,Synchronization flag" "0,1"
bitfld.long 0x4 17. "TWERRIF,Tx error warning interrupt flag" "0,1"
bitfld.long 0x4 16. "RWERRIF,Rx error warning interrupt flag" "0,1"
bitfld.long 0x4 15. "BRERR,Bit recessive error for all format frames" "0,1"
bitfld.long 0x4 14. "BDERR,Bit dominant error for all format frames" "0,1"
bitfld.long 0x4 13. "ACKERR,ACK error" "0,1"
newline
bitfld.long 0x4 12. "CRCERR,CRC error" "0,1"
bitfld.long 0x4 11. "FMERR,Form error" "0,1"
bitfld.long 0x4 10. "STFERR,Stuff error" "0,1"
rbitfld.long 0x4 9. "TWERRF,Tx error warning flag" "0,1"
rbitfld.long 0x4 8. "RWERRF,Rx error warning flag" "0,1"
rbitfld.long 0x4 7. "IDLEF,IDLE flag" "0,1"
rbitfld.long 0x4 6. "TS,Transmitting state" "0,1"
newline
rbitfld.long 0x4 4.--5. "ERRSI,Error state indicator" "0,1,2,3"
rbitfld.long 0x4 3. "RS,Receiving state" "0,1"
bitfld.long 0x4 2. "BOF,Bus off flag" "0,1"
bitfld.long 0x4 1. "ERRSF,Error summary flag" "0,1"
group.long 0x28++0x3
line.long 0x0 "INTEN,Interrupt enable register"
bitfld.long 0x0 31. "MIE31,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 30. "MIE30,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 29. "MIE29,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 28. "MIE28,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 27. "MIE27,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 26. "MIE26,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 25. "MIE25,Message transmission and reception interrupt enable" "0,1"
newline
bitfld.long 0x0 24. "MIE24,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 23. "MIE23,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 22. "MIE22,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 21. "MIE21,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 20. "MIE20,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 19. "MIE19,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 18. "MIE18,Message transmission and reception interrupt enable" "0,1"
newline
bitfld.long 0x0 17. "MIE17,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 16. "MIE16,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 15. "MIE15,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 14. "MIE14,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 13. "MIE13,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 12. "MIE12,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 11. "MIE11,Message transmission and reception interrupt enable" "0,1"
newline
bitfld.long 0x0 10. "MIE10,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 9. "MIE9,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 8. "MIE8,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 7. "MIE7,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 6. "MIE6,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 5. "MIE5,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 4. "MIE4,Message transmission and reception interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "MIE3,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 2. "MIE2,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 1. "MIE1,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 0. "MIE0,Message transmission and reception interrupt enable" "0,1"
group.long 0x30++0x7
line.long 0x0 "STAT,Status register"
bitfld.long 0x0 31. "MS31,Mailbox 23 state" "0,1"
bitfld.long 0x0 30. "MS30,Mailbox 22 state" "0,1"
bitfld.long 0x0 29. "MS29,Mailbox 21 state" "0,1"
bitfld.long 0x0 28. "MS28,Mailbox 20 state" "0,1"
bitfld.long 0x0 27. "MS27,Mailbox 19 state" "0,1"
bitfld.long 0x0 26. "MS26,Mailbox 18 state" "0,1"
bitfld.long 0x0 25. "MS25,Mailbox 17 state" "0,1"
newline
bitfld.long 0x0 24. "MS24,Mailbox 16 state" "0,1"
bitfld.long 0x0 23. "MS23,Mailbox 15 state" "0,1"
bitfld.long 0x0 22. "MS22,Mailbox 14 state" "0,1"
bitfld.long 0x0 21. "MS21,Mailbox 13 state" "0,1"
bitfld.long 0x0 20. "MS20,Mailbox 12 state" "0,1"
bitfld.long 0x0 19. "MS19,Mailbox 11 state" "0,1"
bitfld.long 0x0 18. "MS18,Mailbox 10 state" "0,1"
newline
bitfld.long 0x0 17. "MS17,Mailbox 9 state" "0,1"
bitfld.long 0x0 16. "MS16,Mailbox 8 state" "0,1"
bitfld.long 0x0 15. "MS15,Mailbox 7 state" "0,1"
bitfld.long 0x0 14. "MS14,Mailbox 6 state" "0,1"
bitfld.long 0x0 13. "MS13,Mailbox 5 state" "0,1"
bitfld.long 0x0 12. "MS12,Mailbox 4 state" "0,1"
bitfld.long 0x0 11. "MS11,Mailbox 3 state" "0,1"
newline
bitfld.long 0x0 10. "MS10,Mailbox 2 state" "0,1"
bitfld.long 0x0 9. "MS9,Mailbox 1 state" "0,1"
bitfld.long 0x0 8. "MS8,Mailbox 0 state" "0,1"
bitfld.long 0x0 7. "MS7_RFO,Mailbox 7 state / Rx FIFO overflow" "0,1"
bitfld.long 0x0 6. "MS6_RFW,Mailbox 6 state / Rx FIFO warning" "0,1"
bitfld.long 0x0 5. "MS5_RFNE,Mailbox 5 state / Rx FIFO not empty" "0,1"
bitfld.long 0x0 4. "MS4_RES,Mailbox 4 state / Reserved" "0,1"
newline
bitfld.long 0x0 3. "MS3_RES,Mailbox 3 state / Reserved" "0,1"
bitfld.long 0x0 2. "MS2_RES,Mailbox 2 state / Reserved" "0,1"
bitfld.long 0x0 1. "MS1_RES,Mailbox 1 state / Reserved" "0,1"
bitfld.long 0x0 0. "MS0_RFC,Mailbox 0 state / Clear Rx FIFO bit" "0,1"
line.long 0x4 "CTL2,Control register 2"
bitfld.long 0x4 31. "ERRFSIE,Error summary interrupt enable bit for data phase of FD frames with BRS bit set" "0,1"
bitfld.long 0x4 30. "BORIE,Bus off recovery interrupt enable" "0,1"
hexmask.long.byte 0x4 24.--27. 1. "RFFN,Rx FIFO filter number"
hexmask.long.byte 0x4 19.--23. 1. "ASD,Arbitration start delay"
bitfld.long 0x4 18. "RFO,Receive filter order" "0,1"
bitfld.long 0x4 17. "RRFRMS,Remote request frame is stored" "0,1"
bitfld.long 0x4 16. "IDERTR_RMF,IDE and RTR field filter type for Rx mailbox reception" "0,1"
newline
bitfld.long 0x4 15. "ITSRC,Internal counter source" "0,1"
bitfld.long 0x4 14. "PREEN,Protocol exception detection enable by CAN standard" "0,1"
bitfld.long 0x4 12. "ISO,ISO CAN FD" "0,1"
bitfld.long 0x4 11. "EFDIS,Edge filtering disable" "0,1"
rgroup.long 0x44++0x3
line.long 0x0 "CRCC,CRC for classical frame register"
hexmask.long.byte 0x0 16.--20. 1. "ANTM,Associated number of mailbox for transmitting the CRCTC[14:0] value"
hexmask.long.word 0x0 0.--14. 1. "CRCTC,Transmitted CRC value for classical frames"
group.long 0x48++0x3
line.long 0x0 "RFIFOPUBF,Receive FIFO public filter register"
bitfld.long 0x0 31. "FFD31,Rx FIFO filter data" "0,1"
bitfld.long 0x0 30. "FFD30,Rx FIFO filter data" "0,1"
bitfld.long 0x0 29. "FFD29,Rx FIFO filter data" "0,1"
bitfld.long 0x0 27.--28. "FFD27,Rx FIFO filter data" "0,1,2,3"
bitfld.long 0x0 26. "FFD26,Rx FIFO filter data" "0,1"
bitfld.long 0x0 25. "FFD25,Rx FIFO filter data" "0,1"
bitfld.long 0x0 24. "FFD24,Rx FIFO filter data" "0,1"
newline
bitfld.long 0x0 23. "FFD23,Rx FIFO filter data" "0,1"
bitfld.long 0x0 22. "FFD22,Rx FIFO filter data" "0,1"
bitfld.long 0x0 21. "FFD21,Rx FIFO filter data" "0,1"
bitfld.long 0x0 20. "FFD20,Rx FIFO filter data" "0,1"
bitfld.long 0x0 19. "FFD19,Rx FIFO filter data" "0,1"
bitfld.long 0x0 18. "FFD18,Rx FIFO filter data" "0,1"
bitfld.long 0x0 17. "FFD17,Rx FIFO filter data" "0,1"
newline
bitfld.long 0x0 16. "FFD16,Rx FIFO filter data" "0,1"
bitfld.long 0x0 15. "FFD15,Rx FIFO filter data" "0,1"
bitfld.long 0x0 14. "FFD14,Rx FIFO filter data" "0,1"
bitfld.long 0x0 13. "FFD13,Rx FIFO filter data" "0,1"
bitfld.long 0x0 12. "FFD12,Rx FIFO filter data" "0,1"
bitfld.long 0x0 11. "FFD11,Rx FIFO filter data" "0,1"
bitfld.long 0x0 10. "FFD10,Rx FIFO filter data" "0,1"
newline
bitfld.long 0x0 9. "FFD9,Rx FIFO filter data" "0,1"
bitfld.long 0x0 8. "FFD8,Rx FIFO filter data" "0,1"
bitfld.long 0x0 7. "FFD7,Rx FIFO filter data" "0,1"
bitfld.long 0x0 6. "FFD6,Rx FIFO filter data" "0,1"
bitfld.long 0x0 5. "FFD5,Rx FIFO filter data" "0,1"
bitfld.long 0x0 4. "FFD4,Rx FIFO filter data" "0,1"
bitfld.long 0x0 3. "FFD3,Rx FIFO filter data" "0,1"
newline
bitfld.long 0x0 2. "FFD2,Rx FIFO filter data" "0,1"
bitfld.long 0x0 1. "FFD1,Rx FIFO filter data" "0,1"
bitfld.long 0x0 0. "FFD0,Rx FIFO filter data" "0,1"
rgroup.long 0x4C++0x3
line.long 0x0 "RFIFOIFMN,Receive FIFO identifier filter matching number register"
hexmask.long.word 0x0 0.--8. 1. "IDFMN,Identifier filter matching number"
group.long 0x50++0x3
line.long 0x0 "BT,Bit timing register"
hexmask.long.word 0x0 21.--30. 1. "BAUDPSC,Baud rate prescaler"
hexmask.long.byte 0x0 16.--20. 1. "SJW,Resynchronization jump width"
hexmask.long.byte 0x0 10.--15. 1. "PTS,Propagation time segment"
hexmask.long.byte 0x0 5.--9. 1. "PBS1,Phase buffer segment 1"
hexmask.long.byte 0x0 0.--4. 1. "PBS2,Phase buffer segment 2"
group.long 0x880++0x7F
line.long 0x0 "RFIFOMPF0,Receive FIFO/mailbox private filter 0 register"
bitfld.long 0x0 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x0 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x0 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x0 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x0 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x0 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x4 "RFIFOMPF1,Receive FIFO/mailbox private filter 1 register"
bitfld.long 0x4 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x4 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x8 "RFIFOMPF2,Receive FIFO/mailbox private filter 2 register"
bitfld.long 0x8 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x8 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x8 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x8 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x8 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x8 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0xC "RFIFOMPF3,Receive FIFO/mailbox private filter 3 register"
bitfld.long 0xC 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0xC 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0xC 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0xC 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0xC 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0xC 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x10 "RFIFOMPF4,Receive FIFO/mailbox private filter 4 register"
bitfld.long 0x10 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x10 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x10 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x10 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x10 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x10 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x14 "RFIFOMPF5,Receive FIFO/mailbox private filter 5 register"
bitfld.long 0x14 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x14 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x14 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x14 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x14 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x14 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x18 "RFIFOMPF6,Receive FIFO/mailbox private filter 6 register"
bitfld.long 0x18 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x18 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x18 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x18 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x18 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x18 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x1C "RFIFOMPF7,Receive FIFO/mailbox private filter 7 register"
bitfld.long 0x1C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x1C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x1C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x1C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x1C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x1C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x20 "RFIFOMPF8,Receive FIFO/mailbox private filter 8 register"
bitfld.long 0x20 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x20 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x20 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x20 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x20 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x20 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x24 "RFIFOMPF9,Receive FIFO/mailbox private filter 9 register"
bitfld.long 0x24 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x24 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x24 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x24 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x24 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x24 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x28 "RFIFOMPF10,Receive FIFO/mailbox private filter 10 register"
bitfld.long 0x28 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x28 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x28 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x28 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x28 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x28 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x2C "RFIFOMPF11,Receive FIFO/mailbox private filter 11 register"
bitfld.long 0x2C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x2C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x2C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x2C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x2C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x2C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x30 "RFIFOMPF12,Receive FIFO/mailbox private filter 12 register"
bitfld.long 0x30 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x30 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x30 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x30 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x30 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x30 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x34 "RFIFOMPF13,Receive FIFO/mailbox private filter 13 register"
bitfld.long 0x34 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x34 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x34 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x34 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x34 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x34 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x38 "RFIFOMPF14,Receive FIFO/mailbox private filter 14 register"
bitfld.long 0x38 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x38 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x38 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x38 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x38 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x38 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x3C "RFIFOMPF15,Receive FIFO/mailbox private filter 15 register"
bitfld.long 0x3C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x3C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x3C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x3C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x3C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x3C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x40 "RFIFOMPF16,Receive FIFO/mailbox private filter 16 register"
bitfld.long 0x40 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x40 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x40 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x40 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x40 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x40 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x44 "RFIFOMPF17,Receive FIFO/mailbox private filter 17 register"
bitfld.long 0x44 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x44 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x44 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x44 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x44 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x44 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x48 "RFIFOMPF18,Receive FIFO/mailbox private filter 18 register"
bitfld.long 0x48 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x48 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x48 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x48 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x48 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x48 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x4C "RFIFOMPF19,Receive FIFO/mailbox private filter 19 register"
bitfld.long 0x4C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x4C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x50 "RFIFOMPF20,Receive FIFO/mailbox private filter 20 register"
bitfld.long 0x50 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x50 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x50 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x50 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x50 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x50 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x54 "RFIFOMPF21,Receive FIFO/mailbox private filter 21 register"
bitfld.long 0x54 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x54 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x54 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x54 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x54 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x54 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x58 "RFIFOMPF22,Receive FIFO/mailbox private filter 22 register"
bitfld.long 0x58 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x58 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x58 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x58 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x58 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x58 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x5C "RFIFOMPF23,Receive FIFO/mailbox private filter 23 register"
bitfld.long 0x5C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x5C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x5C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x5C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x5C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x5C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x60 "RFIFOMPF24,Receive FIFO/mailbox private filter 24 register"
bitfld.long 0x60 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x60 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x60 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x60 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x60 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x60 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x64 "RFIFOMPF25,Receive FIFO/mailbox private filter 25 register"
bitfld.long 0x64 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x64 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x64 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x64 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x64 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x64 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x68 "RFIFOMPF26,Receive FIFO/mailbox private filter 26 register"
bitfld.long 0x68 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x68 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x68 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x68 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x68 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x68 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x6C "RFIFOMPF27,Receive FIFO/mailbox private filter 27 register"
bitfld.long 0x6C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x6C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x6C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x6C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x6C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x6C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x70 "RFIFOMPF28,Receive FIFO/mailbox private filter 28 register"
bitfld.long 0x70 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x70 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x70 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x70 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x70 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x70 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x74 "RFIFOMPF29,Receive FIFO/mailbox private filter 29 register"
bitfld.long 0x74 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x74 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x74 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x74 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x74 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x74 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x78 "RFIFOMPF30,Receive FIFO/mailbox private filter 30 register"
bitfld.long 0x78 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x78 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x78 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x78 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x78 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x78 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x7C "RFIFOMPF31,Receive FIFO/mailbox private filter 31 register"
bitfld.long 0x7C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x7C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x7C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x7C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x7C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x7C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
group.long 0xB00++0x27
line.long 0x0 "PN_CTL0,Pretended Networking mode control register 0"
bitfld.long 0x0 17. "WTOIE,Wakeup timeout interrupt enable" "0,1"
bitfld.long 0x0 16. "WMIE,Wakeup match interrupt enable" "0,1"
hexmask.long.byte 0x0 8.--15. 1. "NMM,Number of messages matching times"
bitfld.long 0x0 4.--5. "DATAFT,DATA field filtering type in Pretended Networking mode" "0,1,2,3"
bitfld.long 0x0 2.--3. "IDFT,ID field filtering type in Pretended Networking mode" "0,1,2,3"
bitfld.long 0x0 0.--1. "FFT,Frame filtering type in Pretended Networking mode" "0,1,2,3"
line.long 0x4 "PN_TO,Pretended Networking mode timeout register"
hexmask.long.word 0x4 0.--15. 1. "WTO,Wakeup timeout"
line.long 0x8 "PN_STAT,Pretended Networking mode status register"
bitfld.long 0x8 17. "WTOS,Wakeup timeout flag status" "0,1"
bitfld.long 0x8 16. "WMS,Wakeup match flag status" "0,1"
hexmask.long.byte 0x8 8.--15. 1. "MMCNT,Matching message counter in Pretended Networking mode"
rbitfld.long 0x8 7. "MMCNTS,Matching message counter state" "0,1"
line.long 0xC "PN_EID0,Pretended Networking mode expected identifier 0 register"
bitfld.long 0xC 30. "EIDE,Expected IDE in Pretended Networking mode" "0,1"
bitfld.long 0xC 29. "ERTR,Expected RTR in Pretended Networking mode" "0,1"
hexmask.long 0xC 0.--28. 1. "EID_ELT,Expected ID field / expected ID low threshold in Pretended Networking mode"
line.long 0x10 "PN_EDLC,Pretended Networking mode expected DLC register"
hexmask.long.byte 0x10 16.--19. 1. "DLCELT,DLC expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x10 0.--3. 1. "DLCEHT,DLC expected high threshold in Pretended Networking mode"
line.long 0x14 "PN_EDL0,Pretended Networking mode expected data low 0 register"
hexmask.long.byte 0x14 24.--31. 1. "DB0ELT,Data byte 0 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x14 16.--23. 1. "DB1ELT,Data byte 1 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x14 8.--15. 1. "DB2ELT,Data byte 2 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x14 0.--7. 1. "DB3ELT,Data byte 3 expected low threshold in Pretended Networking mode"
line.long 0x18 "PN_EDL1,Pretended Networking mode expected data low 1 register"
hexmask.long.byte 0x18 24.--31. 1. "DB4ELT,Data byte 4 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x18 16.--23. 1. "DB5ELT,Data byte 5 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x18 8.--15. 1. "DB6ELT,Data byte 6 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x18 0.--7. 1. "DB7ELT,Data byte 7 expected low threshold in Pretended Networking mode"
line.long 0x1C "PN_IFEID1,Pretended Networking mode identifier filter / expected identifier 1 register"
bitfld.long 0x1C 30. "IDEFD,IDE filter data in Pretended Networking mode" "0,1"
bitfld.long 0x1C 29. "RTRFD,RTR filter data in Pretended Networking mode" "0,1"
hexmask.long 0x1C 0.--28. 1. "IDFD_EHT,ID filter data / ID expected high threshold in Pretended Networking mode"
line.long 0x20 "PN_DF0EDH0,Pretended Networking mode data 0 filter / expected data high 0 register"
hexmask.long.byte 0x20 24.--31. 1. "DB0FD_EHT,Data byte 0 filter data / Data byte 0 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x20 16.--23. 1. "DB1FD_EHT,Data byte 1 filter data / Data byte 1 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x20 8.--15. 1. "DB2FD_EHT,Data byte 2 filter data / Data byte 2 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x20 0.--7. 1. "DB3FD_EHT,Data byte 3 filter data / Data byte 2 expected high threshold in Pretended Networking mode"
line.long 0x24 "PN_DF1EDH1,Pretended Networking mode data 1 filter / expected data high 1 register"
hexmask.long.byte 0x24 24.--31. 1. "DB4FD_HTF,Data byte 4 filter data / Data byte 4 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x24 16.--23. 1. "DB5FD_HTF,Data byte 5 filter data / Data byte 5 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x24 8.--15. 1. "DB6FD_HTF,Data byte 6 filter data / Data byte 6 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x24 0.--7. 1. "DB7FD_HTF,Data byte 7 filter data / Data byte 7 expected high threshold in Pretended Networking mode"
rgroup.long 0xB40++0x3F
line.long 0x0 "PN_RWM0CS,Pretended Networking mode received wakeup mailbox 0 control status information register"
bitfld.long 0x0 22. "RSRR,Received SRR bit" "0,1"
bitfld.long 0x0 21. "RIDE,Received IDE bit" "0,1"
bitfld.long 0x0 20. "RRTR,Received RTR bit" "0,1"
hexmask.long.byte 0x0 16.--19. 1. "RDLC,Received DLC bits"
line.long 0x4 "PN_RWM0I,Pretended Networking mode received wakeup mailbox 0 identifier register"
hexmask.long 0x4 0.--28. 1. "RID,Received ID bits"
line.long 0x8 "PN_RWM0D0,Pretended Networking mode received wakeup mailbox 0 data 0 register"
hexmask.long.byte 0x8 24.--31. 1. "RDB0,Received data byte 0"
hexmask.long.byte 0x8 16.--23. 1. "RDB1,Received data byte 1"
hexmask.long.byte 0x8 8.--15. 1. "RDB2,Received data byte 2"
hexmask.long.byte 0x8 0.--7. 1. "RDB3,Received data byte 3"
line.long 0xC "PN_RWM0D1,Pretended Networking mode received wakeup mailbox 0 data 1 register"
hexmask.long.byte 0xC 24.--31. 1. "RDB4,Received data byte 4"
hexmask.long.byte 0xC 16.--23. 1. "RDB5,Received data byte 5"
hexmask.long.byte 0xC 8.--15. 1. "RDB6,Received data byte 6"
hexmask.long.byte 0xC 0.--7. 1. "RDB7,Received data byte 7"
line.long 0x10 "PN_RWM1CS,Pretended Networking mode received wakeup mailbox 1 control status information register"
bitfld.long 0x10 22. "RSRR,Received SRR bit" "0,1"
bitfld.long 0x10 21. "RIDE,Received IDE bit" "0,1"
bitfld.long 0x10 20. "RRTR,Received RTR bit" "0,1"
hexmask.long.byte 0x10 16.--19. 1. "RDLC,Received DLC bits"
line.long 0x14 "PN_RWM1I,Pretended Networking mode received wakeup mailbox 1 identifier register"
hexmask.long 0x14 0.--28. 1. "RID,Received ID bits"
line.long 0x18 "PN_RWM1D0,Pretended Networking mode received wakeup mailbox 1 data 0 register"
hexmask.long.byte 0x18 24.--31. 1. "RDB0,Received data byte 0"
hexmask.long.byte 0x18 16.--23. 1. "RDB1,Received data byte 1"
hexmask.long.byte 0x18 8.--15. 1. "RDB2,Received data byte 2"
hexmask.long.byte 0x18 0.--7. 1. "RDB3,Received data byte 3"
line.long 0x1C "PN_RWM1D1,Pretended Networking mode received wakeup mailbox 1 data 1 register"
hexmask.long.byte 0x1C 24.--31. 1. "RDB4,Received data byte 4"
hexmask.long.byte 0x1C 16.--23. 1. "RDB5,Received data byte 5"
hexmask.long.byte 0x1C 8.--15. 1. "RDB6,Received data byte 6"
hexmask.long.byte 0x1C 0.--7. 1. "RDB7,Received data byte 7"
line.long 0x20 "PN_RWM2CS,Pretended Networking mode received wakeup mailbox 2 control status information register"
bitfld.long 0x20 22. "RSRR,Received SRR bit" "0,1"
bitfld.long 0x20 21. "RIDE,Received IDE bit" "0,1"
bitfld.long 0x20 20. "RRTR,Received RTR bit" "0,1"
hexmask.long.byte 0x20 16.--19. 1. "RDLC,Received DLC bits"
line.long 0x24 "PN_RWM2I,Pretended Networking mode received wakeup mailbox 2 identifier register"
hexmask.long 0x24 0.--28. 1. "RID,Received ID bits"
line.long 0x28 "PN_RWM2D0,Pretended Networking mode received wakeup mailbox 2 data 0 register"
hexmask.long.byte 0x28 24.--31. 1. "RDB0,Received data byte 0"
hexmask.long.byte 0x28 16.--23. 1. "RDB1,Received data byte 1"
hexmask.long.byte 0x28 8.--15. 1. "RDB2,Received data byte 2"
hexmask.long.byte 0x28 0.--7. 1. "RDB3,Received data byte 3"
line.long 0x2C "PN_RWM2D1,Pretended Networking mode received wakeup mailbox 2 data 1 register"
hexmask.long.byte 0x2C 24.--31. 1. "RDB4,Received data byte 4"
hexmask.long.byte 0x2C 16.--23. 1. "RDB5,Received data byte 5"
hexmask.long.byte 0x2C 8.--15. 1. "RDB6,Received data byte 6"
hexmask.long.byte 0x2C 0.--7. 1. "RDB7,Received data byte 7"
line.long 0x30 "PN_RWM3CS,Pretended Networking mode received wakeup mailbox 3 control status information register"
bitfld.long 0x30 22. "RSRR,Received SRR bit" "0,1"
bitfld.long 0x30 21. "RIDE,Received IDE bit" "0,1"
bitfld.long 0x30 20. "RRTR,Received RTR bit" "0,1"
hexmask.long.byte 0x30 16.--19. 1. "RDLC,Received DLC bits"
line.long 0x34 "PN_RWM3I,Pretended Networking mode received wakeup mailbox 3 identifier register"
hexmask.long 0x34 0.--28. 1. "RID,Received ID bits"
line.long 0x38 "PN_RWM3D0,Pretended Networking mode received wakeup mailbox 3 data 0 register"
hexmask.long.byte 0x38 24.--31. 1. "RDB0,Received data byte 0"
hexmask.long.byte 0x38 16.--23. 1. "RDB1,Received data byte 1"
hexmask.long.byte 0x38 8.--15. 1. "RDB2,Received data byte 2"
hexmask.long.byte 0x38 0.--7. 1. "RDB3,Received data byte 3"
line.long 0x3C "PN_RWM3D1,Pretended Networking mode received wakeup mailbox 3 data 1 register"
hexmask.long.byte 0x3C 24.--31. 1. "RDB4,Received data byte 4"
hexmask.long.byte 0x3C 16.--23. 1. "RDB5,Received data byte 5"
hexmask.long.byte 0x3C 8.--15. 1. "RDB6,Received data byte 6"
hexmask.long.byte 0x3C 0.--7. 1. "RDB7,Received data byte 7"
group.long 0xC00++0x7
line.long 0x0 "FDCTL,FD control register"
bitfld.long 0x0 31. "BRSEN,Bit rate of data switch enable" "0,1"
bitfld.long 0x0 16.--17. "MDSZ,Mailbox data size" "0,1,2,3"
bitfld.long 0x0 15. "TDCEN,Transmitter delay compensation enable" "0,1"
bitfld.long 0x0 14. "TDCS,Transmitter delay compensation status" "0,1"
hexmask.long.byte 0x0 8.--12. 1. "TDCO,Transmitter delay compensation offset"
hexmask.long.byte 0x0 0.--5. 1. "TDCV,Transmitter delay compensation value"
line.long 0x4 "FDBT,FD bit timing register"
hexmask.long.word 0x4 20.--29. 1. "DBAUDPSC,Baud rate prescaler for data bit time"
bitfld.long 0x4 16.--18. "DSJW,Resynchronization jump width for data bit time" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 10.--14. 1. "DPTS,Propagation time segment for data bit time"
bitfld.long 0x4 5.--7. "DPBS1,Phase buffer segment 1 for data bit time" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "DPBS2,Phase buffer segment 2 for data bit time" "0,1,2,3,4,5,6,7"
rgroup.long 0xC08++0x3
line.long 0x0 "CRCCFD,CRC for classical and FD frame register"
hexmask.long.byte 0x0 24.--28. 1. "ANTM,Associated number of mailbox for transmitting the CRCTCI[20:0] value"
hexmask.long.tbyte 0x0 0.--20. 1. "CRCTCI,Transmitted CRC value for classical and ISO / non-ISO FD frames"
tree.end
tree "CAN2"
base ad:0x4001C000
group.long 0x0++0xB
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 31. "CANDIS,CAN disable" "0,1"
bitfld.long 0x0 30. "INAMOD,Inactive mode enable" "0,1"
bitfld.long 0x0 29. "RFEN,Rx FIFO enable" "0,1"
bitfld.long 0x0 28. "HALT,Halt CAN" "0,1"
rbitfld.long 0x0 27. "NRDY,Not ready" "0,1"
bitfld.long 0x0 25. "SWRST,Software reset" "0,1"
rbitfld.long 0x0 24. "INAS,Inactive mode state" "0,1"
newline
bitfld.long 0x0 21. "WERREN,Error warning enable" "0,1"
rbitfld.long 0x0 20. "LPS,Low power state" "0,1"
bitfld.long 0x0 19. "PNEN,Pretended Networking mode enable" "0,1"
rbitfld.long 0x0 18. "PNS,Pretended Networking state" "0,1"
bitfld.long 0x0 17. "SRDIS,Self reception disable" "0,1"
bitfld.long 0x0 16. "RPFQEN,Rx private filters enable and Rx mailbox queue enable" "0,1"
bitfld.long 0x0 15. "DMAEN,DMA enable" "0,1"
newline
bitfld.long 0x0 14. "PNMOD,Pretended Networking mode selection" "0,1"
bitfld.long 0x0 13. "LAPRIOEN,Local arbitration priority enable" "0,1"
bitfld.long 0x0 12. "MST,Mailbox stop transmission" "0,1"
bitfld.long 0x0 11. "FDEN,CAN FD operation enable" "0,1"
bitfld.long 0x0 8.--9. "FS,Format selection" "0,1,2,3"
hexmask.long.byte 0x0 0.--4. 1. "MSZ,Memory size"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 15. "BOIE,Bus off interrupt enable" "0,1"
bitfld.long 0x4 14. "ERRSIE,Error summary interrupt enable" "0,1"
bitfld.long 0x4 12. "LSCMOD,Loopback and silent communication mode" "0,1"
bitfld.long 0x4 11. "TWERRIE,Tx error warning interrupt enable" "0,1"
bitfld.long 0x4 10. "RWERRIE,Rx error warning interrupt enable" "0,1"
bitfld.long 0x4 8. "BSSSEL,Bit sampling synchronization select" "0,1"
bitfld.long 0x4 7. "BSPMOD,Bit sampling mode" "0,1"
newline
bitfld.long 0x4 6. "ABORDIS,Automatic Bus off recovery not enable" "0,1"
bitfld.long 0x4 5. "TSYNC,Time synchronization enable" "0,1"
bitfld.long 0x4 4. "MTO,Mailbox transmission order" "0,1"
bitfld.long 0x4 3. "MMOD,Monitor mode" "0,1"
line.long 0x8 "TIMER,Timer register"
hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value"
group.long 0x10++0x3
line.long 0x0 "RMPUBF,Receive mailbox public filter register"
bitfld.long 0x0 31. "MFD31,Mailbox filter data" "0,1"
bitfld.long 0x0 30. "MFD30,Mailbox filter data" "0,1"
bitfld.long 0x0 29. "MFD29,Mailbox filter data" "0,1"
bitfld.long 0x0 28. "MFD28,Mailbox filter data" "0,1"
bitfld.long 0x0 27. "MFD27,Mailbox filter data" "0,1"
bitfld.long 0x0 26. "MFD26,Mailbox filter data" "0,1"
bitfld.long 0x0 25. "MFD25,Mailbox filter data" "0,1"
newline
bitfld.long 0x0 24. "MFD24,Mailbox filter data" "0,1"
bitfld.long 0x0 23. "MFD23,Mailbox filter data" "0,1"
bitfld.long 0x0 22. "MFD22,Mailbox filter data" "0,1"
bitfld.long 0x0 21. "MFD21,Mailbox filter data" "0,1"
bitfld.long 0x0 20. "MFD20,Mailbox filter data" "0,1"
bitfld.long 0x0 19. "MFD19,Mailbox filter data" "0,1"
bitfld.long 0x0 18. "MFD18,Mailbox filter data" "0,1"
newline
bitfld.long 0x0 17. "MFD17,Mailbox filter data" "0,1"
bitfld.long 0x0 16. "MFD16,Mailbox filter data" "0,1"
bitfld.long 0x0 15. "MFD15,Mailbox filter data" "0,1"
bitfld.long 0x0 14. "MFD14,Mailbox filter data" "0,1"
bitfld.long 0x0 13. "MFD13,Mailbox filter data" "0,1"
bitfld.long 0x0 12. "MFD12,Mailbox filter data" "0,1"
bitfld.long 0x0 11. "MFD11,Mailbox filter data" "0,1"
newline
bitfld.long 0x0 10. "MFD10,Mailbox filter data" "0,1"
bitfld.long 0x0 9. "MFD9,Mailbox filter data" "0,1"
bitfld.long 0x0 8. "MFD8,Mailbox filter data" "0,1"
bitfld.long 0x0 7. "MFD7,Mailbox filter data" "0,1"
bitfld.long 0x0 6. "MFD6,Mailbox filter data" "0,1"
bitfld.long 0x0 5. "MFD5,Mailbox filter data" "0,1"
bitfld.long 0x0 4. "MFD4,Mailbox filter data" "0,1"
newline
bitfld.long 0x0 3. "MFD3,Mailbox filter data" "0,1"
bitfld.long 0x0 2. "MFD2,Mailbox filter data" "0,1"
bitfld.long 0x0 1. "MFD1,Mailbox filter data" "0,1"
bitfld.long 0x0 0. "MFD0,Mailbox filter data" "0,1"
group.long 0x1C++0x7
line.long 0x0 "ERR0,Error register 0"
hexmask.long.byte 0x0 24.--31. 1. "REFCNT,Receive error counter for data phase of FD frames with BRS bit set"
hexmask.long.byte 0x0 16.--23. 1. "TEFCNT,Transmit error count for the data phase of FD frames with BRS bit set"
hexmask.long.byte 0x0 8.--15. 1. "RECNT,Receive error count defined by the CAN standard"
hexmask.long.byte 0x0 0.--7. 1. "TECNT,Transmit error count defined by the CAN standard"
line.long 0x4 "ERR1,Error register 1"
bitfld.long 0x4 31. "BRFERR,Bit recessive error in data phase of FD frames with the BRS bit set" "0,1"
bitfld.long 0x4 30. "BDFERR,Bit dominant error in data phase of FD frames with the BRS bit set" "0,1"
bitfld.long 0x4 28. "CRCFERR,CRC error in data phase of FD frames with the BRS bit set" "0,1"
bitfld.long 0x4 27. "FMFERR,Form error in data phase of FD frames with the BRS bit set" "0,1"
bitfld.long 0x4 26. "STFFERR,Stuff error in data phase of FD frames with the BRS bit set" "0,1"
bitfld.long 0x4 21. "ERROVR,Error overrun" "0,1"
bitfld.long 0x4 20. "ERRFSF,Error summary flag for data phase of FD frames with BRS bit set" "0,1"
newline
bitfld.long 0x4 19. "BORF,Bus off recovery flag" "0,1"
rbitfld.long 0x4 18. "SYN,Synchronization flag" "0,1"
bitfld.long 0x4 17. "TWERRIF,Tx error warning interrupt flag" "0,1"
bitfld.long 0x4 16. "RWERRIF,Rx error warning interrupt flag" "0,1"
bitfld.long 0x4 15. "BRERR,Bit recessive error for all format frames" "0,1"
bitfld.long 0x4 14. "BDERR,Bit dominant error for all format frames" "0,1"
bitfld.long 0x4 13. "ACKERR,ACK error" "0,1"
newline
bitfld.long 0x4 12. "CRCERR,CRC error" "0,1"
bitfld.long 0x4 11. "FMERR,Form error" "0,1"
bitfld.long 0x4 10. "STFERR,Stuff error" "0,1"
rbitfld.long 0x4 9. "TWERRF,Tx error warning flag" "0,1"
rbitfld.long 0x4 8. "RWERRF,Rx error warning flag" "0,1"
rbitfld.long 0x4 7. "IDLEF,IDLE flag" "0,1"
rbitfld.long 0x4 6. "TS,Transmitting state" "0,1"
newline
rbitfld.long 0x4 4.--5. "ERRSI,Error state indicator" "0,1,2,3"
rbitfld.long 0x4 3. "RS,Receiving state" "0,1"
bitfld.long 0x4 2. "BOF,Bus off flag" "0,1"
bitfld.long 0x4 1. "ERRSF,Error summary flag" "0,1"
group.long 0x28++0x3
line.long 0x0 "INTEN,Interrupt enable register"
bitfld.long 0x0 31. "MIE31,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 30. "MIE30,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 29. "MIE29,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 28. "MIE28,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 27. "MIE27,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 26. "MIE26,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 25. "MIE25,Message transmission and reception interrupt enable" "0,1"
newline
bitfld.long 0x0 24. "MIE24,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 23. "MIE23,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 22. "MIE22,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 21. "MIE21,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 20. "MIE20,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 19. "MIE19,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 18. "MIE18,Message transmission and reception interrupt enable" "0,1"
newline
bitfld.long 0x0 17. "MIE17,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 16. "MIE16,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 15. "MIE15,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 14. "MIE14,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 13. "MIE13,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 12. "MIE12,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 11. "MIE11,Message transmission and reception interrupt enable" "0,1"
newline
bitfld.long 0x0 10. "MIE10,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 9. "MIE9,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 8. "MIE8,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 7. "MIE7,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 6. "MIE6,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 5. "MIE5,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 4. "MIE4,Message transmission and reception interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "MIE3,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 2. "MIE2,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 1. "MIE1,Message transmission and reception interrupt enable" "0,1"
bitfld.long 0x0 0. "MIE0,Message transmission and reception interrupt enable" "0,1"
group.long 0x30++0x7
line.long 0x0 "STAT,Status register"
bitfld.long 0x0 31. "MS31,Mailbox 23 state" "0,1"
bitfld.long 0x0 30. "MS30,Mailbox 22 state" "0,1"
bitfld.long 0x0 29. "MS29,Mailbox 21 state" "0,1"
bitfld.long 0x0 28. "MS28,Mailbox 20 state" "0,1"
bitfld.long 0x0 27. "MS27,Mailbox 19 state" "0,1"
bitfld.long 0x0 26. "MS26,Mailbox 18 state" "0,1"
bitfld.long 0x0 25. "MS25,Mailbox 17 state" "0,1"
newline
bitfld.long 0x0 24. "MS24,Mailbox 16 state" "0,1"
bitfld.long 0x0 23. "MS23,Mailbox 15 state" "0,1"
bitfld.long 0x0 22. "MS22,Mailbox 14 state" "0,1"
bitfld.long 0x0 21. "MS21,Mailbox 13 state" "0,1"
bitfld.long 0x0 20. "MS20,Mailbox 12 state" "0,1"
bitfld.long 0x0 19. "MS19,Mailbox 11 state" "0,1"
bitfld.long 0x0 18. "MS18,Mailbox 10 state" "0,1"
newline
bitfld.long 0x0 17. "MS17,Mailbox 9 state" "0,1"
bitfld.long 0x0 16. "MS16,Mailbox 8 state" "0,1"
bitfld.long 0x0 15. "MS15,Mailbox 7 state" "0,1"
bitfld.long 0x0 14. "MS14,Mailbox 6 state" "0,1"
bitfld.long 0x0 13. "MS13,Mailbox 5 state" "0,1"
bitfld.long 0x0 12. "MS12,Mailbox 4 state" "0,1"
bitfld.long 0x0 11. "MS11,Mailbox 3 state" "0,1"
newline
bitfld.long 0x0 10. "MS10,Mailbox 2 state" "0,1"
bitfld.long 0x0 9. "MS9,Mailbox 1 state" "0,1"
bitfld.long 0x0 8. "MS8,Mailbox 0 state" "0,1"
bitfld.long 0x0 7. "MS7_RFO,Mailbox 7 state / Rx FIFO overflow" "0,1"
bitfld.long 0x0 6. "MS6_RFW,Mailbox 6 state / Rx FIFO warning" "0,1"
bitfld.long 0x0 5. "MS5_RFNE,Mailbox 5 state / Rx FIFO not empty" "0,1"
bitfld.long 0x0 4. "MS4_RES,Mailbox 4 state / Reserved" "0,1"
newline
bitfld.long 0x0 3. "MS3_RES,Mailbox 3 state / Reserved" "0,1"
bitfld.long 0x0 2. "MS2_RES,Mailbox 2 state / Reserved" "0,1"
bitfld.long 0x0 1. "MS1_RES,Mailbox 1 state / Reserved" "0,1"
bitfld.long 0x0 0. "MS0_RFC,Mailbox 0 state / Clear Rx FIFO bit" "0,1"
line.long 0x4 "CTL2,Control register 2"
bitfld.long 0x4 31. "ERRFSIE,Error summary interrupt enable bit for data phase of FD frames with BRS bit set" "0,1"
bitfld.long 0x4 30. "BORIE,Bus off recovery interrupt enable" "0,1"
hexmask.long.byte 0x4 24.--27. 1. "RFFN,Rx FIFO filter number"
hexmask.long.byte 0x4 19.--23. 1. "ASD,Arbitration start delay"
bitfld.long 0x4 18. "RFO,Receive filter order" "0,1"
bitfld.long 0x4 17. "RRFRMS,Remote request frame is stored" "0,1"
bitfld.long 0x4 16. "IDERTR_RMF,IDE and RTR field filter type for Rx mailbox reception" "0,1"
newline
bitfld.long 0x4 15. "ITSRC,Internal counter source" "0,1"
bitfld.long 0x4 14. "PREEN,Protocol exception detection enable by CAN standard" "0,1"
bitfld.long 0x4 12. "ISO,ISO CAN FD" "0,1"
bitfld.long 0x4 11. "EFDIS,Edge filtering disable" "0,1"
rgroup.long 0x44++0x3
line.long 0x0 "CRCC,CRC for classical frame register"
hexmask.long.byte 0x0 16.--20. 1. "ANTM,Associated number of mailbox for transmitting the CRCTC[14:0] value"
hexmask.long.word 0x0 0.--14. 1. "CRCTC,Transmitted CRC value for classical frames"
group.long 0x48++0x3
line.long 0x0 "RFIFOPUBF,Receive FIFO public filter register"
bitfld.long 0x0 31. "FFD31,Rx FIFO filter data" "0,1"
bitfld.long 0x0 30. "FFD30,Rx FIFO filter data" "0,1"
bitfld.long 0x0 29. "FFD29,Rx FIFO filter data" "0,1"
bitfld.long 0x0 27.--28. "FFD27,Rx FIFO filter data" "0,1,2,3"
bitfld.long 0x0 26. "FFD26,Rx FIFO filter data" "0,1"
bitfld.long 0x0 25. "FFD25,Rx FIFO filter data" "0,1"
bitfld.long 0x0 24. "FFD24,Rx FIFO filter data" "0,1"
newline
bitfld.long 0x0 23. "FFD23,Rx FIFO filter data" "0,1"
bitfld.long 0x0 22. "FFD22,Rx FIFO filter data" "0,1"
bitfld.long 0x0 21. "FFD21,Rx FIFO filter data" "0,1"
bitfld.long 0x0 20. "FFD20,Rx FIFO filter data" "0,1"
bitfld.long 0x0 19. "FFD19,Rx FIFO filter data" "0,1"
bitfld.long 0x0 18. "FFD18,Rx FIFO filter data" "0,1"
bitfld.long 0x0 17. "FFD17,Rx FIFO filter data" "0,1"
newline
bitfld.long 0x0 16. "FFD16,Rx FIFO filter data" "0,1"
bitfld.long 0x0 15. "FFD15,Rx FIFO filter data" "0,1"
bitfld.long 0x0 14. "FFD14,Rx FIFO filter data" "0,1"
bitfld.long 0x0 13. "FFD13,Rx FIFO filter data" "0,1"
bitfld.long 0x0 12. "FFD12,Rx FIFO filter data" "0,1"
bitfld.long 0x0 11. "FFD11,Rx FIFO filter data" "0,1"
bitfld.long 0x0 10. "FFD10,Rx FIFO filter data" "0,1"
newline
bitfld.long 0x0 9. "FFD9,Rx FIFO filter data" "0,1"
bitfld.long 0x0 8. "FFD8,Rx FIFO filter data" "0,1"
bitfld.long 0x0 7. "FFD7,Rx FIFO filter data" "0,1"
bitfld.long 0x0 6. "FFD6,Rx FIFO filter data" "0,1"
bitfld.long 0x0 5. "FFD5,Rx FIFO filter data" "0,1"
bitfld.long 0x0 4. "FFD4,Rx FIFO filter data" "0,1"
bitfld.long 0x0 3. "FFD3,Rx FIFO filter data" "0,1"
newline
bitfld.long 0x0 2. "FFD2,Rx FIFO filter data" "0,1"
bitfld.long 0x0 1. "FFD1,Rx FIFO filter data" "0,1"
bitfld.long 0x0 0. "FFD0,Rx FIFO filter data" "0,1"
rgroup.long 0x4C++0x3
line.long 0x0 "RFIFOIFMN,Receive FIFO identifier filter matching number register"
hexmask.long.word 0x0 0.--8. 1. "IDFMN,Identifier filter matching number"
group.long 0x50++0x3
line.long 0x0 "BT,Bit timing register"
hexmask.long.word 0x0 21.--30. 1. "BAUDPSC,Baud rate prescaler"
hexmask.long.byte 0x0 16.--20. 1. "SJW,Resynchronization jump width"
hexmask.long.byte 0x0 10.--15. 1. "PTS,Propagation time segment"
hexmask.long.byte 0x0 5.--9. 1. "PBS1,Phase buffer segment 1"
hexmask.long.byte 0x0 0.--4. 1. "PBS2,Phase buffer segment 2"
group.long 0x880++0x7F
line.long 0x0 "RFIFOMPF0,Receive FIFO/mailbox private filter 0 register"
bitfld.long 0x0 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x0 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x0 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x0 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x0 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x0 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x0 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x4 "RFIFOMPF1,Receive FIFO/mailbox private filter 1 register"
bitfld.long 0x4 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x4 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x8 "RFIFOMPF2,Receive FIFO/mailbox private filter 2 register"
bitfld.long 0x8 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x8 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x8 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x8 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x8 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x8 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x8 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0xC "RFIFOMPF3,Receive FIFO/mailbox private filter 3 register"
bitfld.long 0xC 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0xC 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0xC 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0xC 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0xC 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0xC 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0xC 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x10 "RFIFOMPF4,Receive FIFO/mailbox private filter 4 register"
bitfld.long 0x10 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x10 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x10 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x10 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x10 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x10 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x10 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x14 "RFIFOMPF5,Receive FIFO/mailbox private filter 5 register"
bitfld.long 0x14 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x14 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x14 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x14 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x14 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x14 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x14 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x18 "RFIFOMPF6,Receive FIFO/mailbox private filter 6 register"
bitfld.long 0x18 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x18 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x18 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x18 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x18 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x18 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x18 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x1C "RFIFOMPF7,Receive FIFO/mailbox private filter 7 register"
bitfld.long 0x1C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x1C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x1C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x1C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x1C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x1C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x1C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x20 "RFIFOMPF8,Receive FIFO/mailbox private filter 8 register"
bitfld.long 0x20 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x20 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x20 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x20 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x20 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x20 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x20 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x24 "RFIFOMPF9,Receive FIFO/mailbox private filter 9 register"
bitfld.long 0x24 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x24 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x24 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x24 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x24 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x24 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x24 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x28 "RFIFOMPF10,Receive FIFO/mailbox private filter 10 register"
bitfld.long 0x28 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x28 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x28 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x28 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x28 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x28 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x28 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x2C "RFIFOMPF11,Receive FIFO/mailbox private filter 11 register"
bitfld.long 0x2C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x2C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x2C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x2C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x2C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x2C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x2C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x30 "RFIFOMPF12,Receive FIFO/mailbox private filter 12 register"
bitfld.long 0x30 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x30 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x30 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x30 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x30 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x30 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x30 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x34 "RFIFOMPF13,Receive FIFO/mailbox private filter 13 register"
bitfld.long 0x34 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x34 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x34 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x34 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x34 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x34 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x34 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x38 "RFIFOMPF14,Receive FIFO/mailbox private filter 14 register"
bitfld.long 0x38 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x38 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x38 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x38 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x38 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x38 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x38 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x3C "RFIFOMPF15,Receive FIFO/mailbox private filter 15 register"
bitfld.long 0x3C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x3C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x3C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x3C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x3C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x3C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x3C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x40 "RFIFOMPF16,Receive FIFO/mailbox private filter 16 register"
bitfld.long 0x40 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x40 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x40 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x40 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x40 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x40 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x40 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x44 "RFIFOMPF17,Receive FIFO/mailbox private filter 17 register"
bitfld.long 0x44 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x44 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x44 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x44 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x44 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x44 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x44 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x48 "RFIFOMPF18,Receive FIFO/mailbox private filter 18 register"
bitfld.long 0x48 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x48 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x48 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x48 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x48 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x48 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x48 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x4C "RFIFOMPF19,Receive FIFO/mailbox private filter 19 register"
bitfld.long 0x4C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x4C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x4C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x4C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x50 "RFIFOMPF20,Receive FIFO/mailbox private filter 20 register"
bitfld.long 0x50 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x50 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x50 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x50 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x50 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x50 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x50 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x54 "RFIFOMPF21,Receive FIFO/mailbox private filter 21 register"
bitfld.long 0x54 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x54 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x54 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x54 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x54 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x54 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x54 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x58 "RFIFOMPF22,Receive FIFO/mailbox private filter 22 register"
bitfld.long 0x58 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x58 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x58 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x58 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x58 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x58 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x58 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x5C "RFIFOMPF23,Receive FIFO/mailbox private filter 23 register"
bitfld.long 0x5C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x5C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x5C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x5C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x5C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x5C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x5C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x60 "RFIFOMPF24,Receive FIFO/mailbox private filter 24 register"
bitfld.long 0x60 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x60 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x60 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x60 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x60 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x60 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x60 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x64 "RFIFOMPF25,Receive FIFO/mailbox private filter 25 register"
bitfld.long 0x64 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x64 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x64 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x64 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x64 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x64 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x64 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x68 "RFIFOMPF26,Receive FIFO/mailbox private filter 26 register"
bitfld.long 0x68 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x68 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x68 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x68 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x68 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x68 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x68 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x6C "RFIFOMPF27,Receive FIFO/mailbox private filter 27 register"
bitfld.long 0x6C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x6C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x6C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x6C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x6C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x6C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x6C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x70 "RFIFOMPF28,Receive FIFO/mailbox private filter 28 register"
bitfld.long 0x70 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x70 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x70 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x70 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x70 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x70 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x70 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x74 "RFIFOMPF29,Receive FIFO/mailbox private filter 29 register"
bitfld.long 0x74 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x74 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x74 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x74 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x74 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x74 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x74 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x78 "RFIFOMPF30,Receive FIFO/mailbox private filter 30 register"
bitfld.long 0x78 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x78 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x78 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x78 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x78 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x78 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x78 0. "FMFD0,FIFO/mailbox filter data" "0,1"
line.long 0x7C "RFIFOMPF31,Receive FIFO/mailbox private filter 31 register"
bitfld.long 0x7C 31. "FMFD31,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 30. "FMFD30,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 29. "FMFD29,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 27.--28. "FMFD27,FIFO/mailbox filter data" "0,1,2,3"
bitfld.long 0x7C 26. "FMFD26,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 25. "FMFD25,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 24. "FMFD24,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x7C 23. "FMFD23,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 22. "FMFD22,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 21. "FMFD21,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 20. "FMFD20,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 19. "FMFD19,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 18. "FMFD18,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 17. "FMFD17,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x7C 16. "FMFD16,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 15. "FMFD15,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 14. "FMFD14,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 13. "FMFD13,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 12. "FMFD12,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 11. "FMFD11,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 10. "FMFD10,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x7C 9. "FMFD9,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 8. "FMFD8,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 7. "FMFD7,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 6. "FMFD6,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 5. "FMFD5,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 4. "FMFD4,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 3. "FMFD3,FIFO/mailbox filter data" "0,1"
newline
bitfld.long 0x7C 2. "FMFD2,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 1. "FMFD1,FIFO/mailbox filter data" "0,1"
bitfld.long 0x7C 0. "FMFD0,FIFO/mailbox filter data" "0,1"
group.long 0xB00++0x27
line.long 0x0 "PN_CTL0,Pretended Networking mode control register 0"
bitfld.long 0x0 17. "WTOIE,Wakeup timeout interrupt enable" "0,1"
bitfld.long 0x0 16. "WMIE,Wakeup match interrupt enable" "0,1"
hexmask.long.byte 0x0 8.--15. 1. "NMM,Number of messages matching times"
bitfld.long 0x0 4.--5. "DATAFT,DATA field filtering type in Pretended Networking mode" "0,1,2,3"
bitfld.long 0x0 2.--3. "IDFT,ID field filtering type in Pretended Networking mode" "0,1,2,3"
bitfld.long 0x0 0.--1. "FFT,Frame filtering type in Pretended Networking mode" "0,1,2,3"
line.long 0x4 "PN_TO,Pretended Networking mode timeout register"
hexmask.long.word 0x4 0.--15. 1. "WTO,Wakeup timeout"
line.long 0x8 "PN_STAT,Pretended Networking mode status register"
bitfld.long 0x8 17. "WTOS,Wakeup timeout flag status" "0,1"
bitfld.long 0x8 16. "WMS,Wakeup match flag status" "0,1"
hexmask.long.byte 0x8 8.--15. 1. "MMCNT,Matching message counter in Pretended Networking mode"
rbitfld.long 0x8 7. "MMCNTS,Matching message counter state" "0,1"
line.long 0xC "PN_EID0,Pretended Networking mode expected identifier 0 register"
bitfld.long 0xC 30. "EIDE,Expected IDE in Pretended Networking mode" "0,1"
bitfld.long 0xC 29. "ERTR,Expected RTR in Pretended Networking mode" "0,1"
hexmask.long 0xC 0.--28. 1. "EID_ELT,Expected ID field / expected ID low threshold in Pretended Networking mode"
line.long 0x10 "PN_EDLC,Pretended Networking mode expected DLC register"
hexmask.long.byte 0x10 16.--19. 1. "DLCELT,DLC expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x10 0.--3. 1. "DLCEHT,DLC expected high threshold in Pretended Networking mode"
line.long 0x14 "PN_EDL0,Pretended Networking mode expected data low 0 register"
hexmask.long.byte 0x14 24.--31. 1. "DB0ELT,Data byte 0 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x14 16.--23. 1. "DB1ELT,Data byte 1 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x14 8.--15. 1. "DB2ELT,Data byte 2 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x14 0.--7. 1. "DB3ELT,Data byte 3 expected low threshold in Pretended Networking mode"
line.long 0x18 "PN_EDL1,Pretended Networking mode expected data low 1 register"
hexmask.long.byte 0x18 24.--31. 1. "DB4ELT,Data byte 4 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x18 16.--23. 1. "DB5ELT,Data byte 5 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x18 8.--15. 1. "DB6ELT,Data byte 6 expected low threshold in Pretended Networking mode"
hexmask.long.byte 0x18 0.--7. 1. "DB7ELT,Data byte 7 expected low threshold in Pretended Networking mode"
line.long 0x1C "PN_IFEID1,Pretended Networking mode identifier filter / expected identifier 1 register"
bitfld.long 0x1C 30. "IDEFD,IDE filter data in Pretended Networking mode" "0,1"
bitfld.long 0x1C 29. "RTRFD,RTR filter data in Pretended Networking mode" "0,1"
hexmask.long 0x1C 0.--28. 1. "IDFD_EHT,ID filter data / ID expected high threshold in Pretended Networking mode"
line.long 0x20 "PN_DF0EDH0,Pretended Networking mode data 0 filter / expected data high 0 register"
hexmask.long.byte 0x20 24.--31. 1. "DB0FD_EHT,Data byte 0 filter data / Data byte 0 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x20 16.--23. 1. "DB1FD_EHT,Data byte 1 filter data / Data byte 1 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x20 8.--15. 1. "DB2FD_EHT,Data byte 2 filter data / Data byte 2 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x20 0.--7. 1. "DB3FD_EHT,Data byte 3 filter data / Data byte 2 expected high threshold in Pretended Networking mode"
line.long 0x24 "PN_DF1EDH1,Pretended Networking mode data 1 filter / expected data high 1 register"
hexmask.long.byte 0x24 24.--31. 1. "DB4FD_HTF,Data byte 4 filter data / Data byte 4 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x24 16.--23. 1. "DB5FD_HTF,Data byte 5 filter data / Data byte 5 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x24 8.--15. 1. "DB6FD_HTF,Data byte 6 filter data / Data byte 6 expected high threshold in Pretended Networking mode"
hexmask.long.byte 0x24 0.--7. 1. "DB7FD_HTF,Data byte 7 filter data / Data byte 7 expected high threshold in Pretended Networking mode"
rgroup.long 0xB40++0x3F
line.long 0x0 "PN_RWM0CS,Pretended Networking mode received wakeup mailbox 0 control status information register"
bitfld.long 0x0 22. "RSRR,Received SRR bit" "0,1"
bitfld.long 0x0 21. "RIDE,Received IDE bit" "0,1"
bitfld.long 0x0 20. "RRTR,Received RTR bit" "0,1"
hexmask.long.byte 0x0 16.--19. 1. "RDLC,Received DLC bits"
line.long 0x4 "PN_RWM0I,Pretended Networking mode received wakeup mailbox 0 identifier register"
hexmask.long 0x4 0.--28. 1. "RID,Received ID bits"
line.long 0x8 "PN_RWM0D0,Pretended Networking mode received wakeup mailbox 0 data 0 register"
hexmask.long.byte 0x8 24.--31. 1. "RDB0,Received data byte 0"
hexmask.long.byte 0x8 16.--23. 1. "RDB1,Received data byte 1"
hexmask.long.byte 0x8 8.--15. 1. "RDB2,Received data byte 2"
hexmask.long.byte 0x8 0.--7. 1. "RDB3,Received data byte 3"
line.long 0xC "PN_RWM0D1,Pretended Networking mode received wakeup mailbox 0 data 1 register"
hexmask.long.byte 0xC 24.--31. 1. "RDB4,Received data byte 4"
hexmask.long.byte 0xC 16.--23. 1. "RDB5,Received data byte 5"
hexmask.long.byte 0xC 8.--15. 1. "RDB6,Received data byte 6"
hexmask.long.byte 0xC 0.--7. 1. "RDB7,Received data byte 7"
line.long 0x10 "PN_RWM1CS,Pretended Networking mode received wakeup mailbox 1 control status information register"
bitfld.long 0x10 22. "RSRR,Received SRR bit" "0,1"
bitfld.long 0x10 21. "RIDE,Received IDE bit" "0,1"
bitfld.long 0x10 20. "RRTR,Received RTR bit" "0,1"
hexmask.long.byte 0x10 16.--19. 1. "RDLC,Received DLC bits"
line.long 0x14 "PN_RWM1I,Pretended Networking mode received wakeup mailbox 1 identifier register"
hexmask.long 0x14 0.--28. 1. "RID,Received ID bits"
line.long 0x18 "PN_RWM1D0,Pretended Networking mode received wakeup mailbox 1 data 0 register"
hexmask.long.byte 0x18 24.--31. 1. "RDB0,Received data byte 0"
hexmask.long.byte 0x18 16.--23. 1. "RDB1,Received data byte 1"
hexmask.long.byte 0x18 8.--15. 1. "RDB2,Received data byte 2"
hexmask.long.byte 0x18 0.--7. 1. "RDB3,Received data byte 3"
line.long 0x1C "PN_RWM1D1,Pretended Networking mode received wakeup mailbox 1 data 1 register"
hexmask.long.byte 0x1C 24.--31. 1. "RDB4,Received data byte 4"
hexmask.long.byte 0x1C 16.--23. 1. "RDB5,Received data byte 5"
hexmask.long.byte 0x1C 8.--15. 1. "RDB6,Received data byte 6"
hexmask.long.byte 0x1C 0.--7. 1. "RDB7,Received data byte 7"
line.long 0x20 "PN_RWM2CS,Pretended Networking mode received wakeup mailbox 2 control status information register"
bitfld.long 0x20 22. "RSRR,Received SRR bit" "0,1"
bitfld.long 0x20 21. "RIDE,Received IDE bit" "0,1"
bitfld.long 0x20 20. "RRTR,Received RTR bit" "0,1"
hexmask.long.byte 0x20 16.--19. 1. "RDLC,Received DLC bits"
line.long 0x24 "PN_RWM2I,Pretended Networking mode received wakeup mailbox 2 identifier register"
hexmask.long 0x24 0.--28. 1. "RID,Received ID bits"
line.long 0x28 "PN_RWM2D0,Pretended Networking mode received wakeup mailbox 2 data 0 register"
hexmask.long.byte 0x28 24.--31. 1. "RDB0,Received data byte 0"
hexmask.long.byte 0x28 16.--23. 1. "RDB1,Received data byte 1"
hexmask.long.byte 0x28 8.--15. 1. "RDB2,Received data byte 2"
hexmask.long.byte 0x28 0.--7. 1. "RDB3,Received data byte 3"
line.long 0x2C "PN_RWM2D1,Pretended Networking mode received wakeup mailbox 2 data 1 register"
hexmask.long.byte 0x2C 24.--31. 1. "RDB4,Received data byte 4"
hexmask.long.byte 0x2C 16.--23. 1. "RDB5,Received data byte 5"
hexmask.long.byte 0x2C 8.--15. 1. "RDB6,Received data byte 6"
hexmask.long.byte 0x2C 0.--7. 1. "RDB7,Received data byte 7"
line.long 0x30 "PN_RWM3CS,Pretended Networking mode received wakeup mailbox 3 control status information register"
bitfld.long 0x30 22. "RSRR,Received SRR bit" "0,1"
bitfld.long 0x30 21. "RIDE,Received IDE bit" "0,1"
bitfld.long 0x30 20. "RRTR,Received RTR bit" "0,1"
hexmask.long.byte 0x30 16.--19. 1. "RDLC,Received DLC bits"
line.long 0x34 "PN_RWM3I,Pretended Networking mode received wakeup mailbox 3 identifier register"
hexmask.long 0x34 0.--28. 1. "RID,Received ID bits"
line.long 0x38 "PN_RWM3D0,Pretended Networking mode received wakeup mailbox 3 data 0 register"
hexmask.long.byte 0x38 24.--31. 1. "RDB0,Received data byte 0"
hexmask.long.byte 0x38 16.--23. 1. "RDB1,Received data byte 1"
hexmask.long.byte 0x38 8.--15. 1. "RDB2,Received data byte 2"
hexmask.long.byte 0x38 0.--7. 1. "RDB3,Received data byte 3"
line.long 0x3C "PN_RWM3D1,Pretended Networking mode received wakeup mailbox 3 data 1 register"
hexmask.long.byte 0x3C 24.--31. 1. "RDB4,Received data byte 4"
hexmask.long.byte 0x3C 16.--23. 1. "RDB5,Received data byte 5"
hexmask.long.byte 0x3C 8.--15. 1. "RDB6,Received data byte 6"
hexmask.long.byte 0x3C 0.--7. 1. "RDB7,Received data byte 7"
group.long 0xC00++0x7
line.long 0x0 "FDCTL,FD control register"
bitfld.long 0x0 31. "BRSEN,Bit rate of data switch enable" "0,1"
bitfld.long 0x0 16.--17. "MDSZ,Mailbox data size" "0,1,2,3"
bitfld.long 0x0 15. "TDCEN,Transmitter delay compensation enable" "0,1"
bitfld.long 0x0 14. "TDCS,Transmitter delay compensation status" "0,1"
hexmask.long.byte 0x0 8.--12. 1. "TDCO,Transmitter delay compensation offset"
hexmask.long.byte 0x0 0.--5. 1. "TDCV,Transmitter delay compensation value"
line.long 0x4 "FDBT,FD bit timing register"
hexmask.long.word 0x4 20.--29. 1. "DBAUDPSC,Baud rate prescaler for data bit time"
bitfld.long 0x4 16.--18. "DSJW,Resynchronization jump width for data bit time" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 10.--14. 1. "DPTS,Propagation time segment for data bit time"
bitfld.long 0x4 5.--7. "DPBS1,Phase buffer segment 1 for data bit time" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "DPBS2,Phase buffer segment 2 for data bit time" "0,1,2,3,4,5,6,7"
rgroup.long 0xC08++0x3
line.long 0x0 "CRCCFD,CRC for classical and FD frame register"
hexmask.long.byte 0x0 24.--28. 1. "ANTM,Associated number of mailbox for transmitting the CRCTCI[20:0] value"
hexmask.long.tbyte 0x0 0.--20. 1. "CRCTCI,Transmitted CRC value for classical and ISO / non-ISO FD frames"
tree.end
tree.end
tree "CAU (Cryptographic Acceleration Unit)"
base ad:0x48021000
group.long 0x0++0x3
line.long 0x0 "CTL,Control register"
hexmask.long.byte 0x0 20.--23. 1. "NBPILB,Number of bytes padding in last block of payload"
bitfld.long 0x0 19. "ALGM_3,Encryption/decryption algorithm mode bit 3" "0,1"
bitfld.long 0x0 16.--17. "GCM_CCMPH,GCM CCM phase" "0,1,2,3"
bitfld.long 0x0 15. "CAUEN,CAU Enable" "0,1"
bitfld.long 0x0 14. "FFLUSH,Flush FIFO" "0,1"
bitfld.long 0x0 8.--9. "KEYM,AES key size mode configuration" "0,1,2,3"
bitfld.long 0x0 6.--7. "DATAM,Data swapping type mode configuration" "0,1,2,3"
bitfld.long 0x0 3.--5. "ALGM,Encryption/decryption algorithm mode bit 0 to bit 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 2. "CAUDIR,CAU direction" "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "STAT0,Status register 0"
bitfld.long 0x0 4. "BUSY,Busy bit" "0,1"
bitfld.long 0x0 3. "OFU,Output FIFO is full" "0,1"
bitfld.long 0x0 2. "ONE,Output FIFO is not empty" "0,1"
bitfld.long 0x0 1. "INF,Input FIFO is not full" "0,1"
bitfld.long 0x0 0. "IEM,Input FIFO is empty" "0,1"
group.long 0x8++0x3
line.long 0x0 "DI,Data input register"
hexmask.long 0x0 0.--31. 1. "DI,Data input"
rgroup.long 0xC++0x3
line.long 0x0 "DO,Data output register"
hexmask.long 0x0 0.--31. 1. "DO,Data output"
group.long 0x10++0x7
line.long 0x0 "DMAEN,DMA enable register"
bitfld.long 0x0 1. "DMAOEN,DMA output enable" "0,1"
bitfld.long 0x0 0. "DMAIEN,DMA input enable" "0,1"
line.long 0x4 "INTEN,Interrupt enable register"
bitfld.long 0x4 1. "OINTEN,OUT FIFO interrupt enable" "0,1"
bitfld.long 0x4 0. "IINTEN,IN FIFO interrupt enable" "0,1"
rgroup.long 0x18++0x3
line.long 0x0 "STAT1,Status register 1"
bitfld.long 0x0 1. "OSTA,OUT FIFO interrupt status" "0,1"
bitfld.long 0x0 0. "ISTA,IN FIFO interrupt status" "0,1"
group.long 0x1C++0x3
line.long 0x0 "INTF,Interrupt flag register"
rbitfld.long 0x0 1. "OINTF,OUT FIFO enabled interrupt flag" "0,1"
bitfld.long 0x0 0. "IINTF,IN FIFO enabled interrupt flag" "0,1"
wgroup.long 0x20++0x1F
line.long 0x0 "KEY0H,CAU key register"
hexmask.long 0x0 0.--31. 1. "KEY0H,Key for DES TDES AES"
line.long 0x4 "KEY0L,CAU key register"
hexmask.long 0x4 0.--31. 1. "KEY0L,Key for DES TDES AES"
line.long 0x8 "KEY1H,CAU key register"
hexmask.long 0x8 0.--31. 1. "KEY1H,Key for DES TDES AES"
line.long 0xC "KEY1L,CAU key register"
hexmask.long 0xC 0.--31. 1. "KEY1L,Key for DES TDES AES"
line.long 0x10 "KEY2H,CAU key register"
hexmask.long 0x10 0.--31. 1. "KEY2H,Key for DES TDES AES"
line.long 0x14 "KEY2L,CAU key register"
hexmask.long 0x14 0.--31. 1. "KEY2L,Key for DES TDES AES"
line.long 0x18 "KEY3H,CAU key register"
hexmask.long 0x18 0.--31. 1. "KEY3H,Key for DES TDES AES"
line.long 0x1C "KEY3L,CAU key register"
hexmask.long 0x1C 0.--31. 1. "KEY3L,Key for DES TDES AES"
group.long 0x40++0x4F
line.long 0x0 "IV0H,CAU initialization register"
hexmask.long 0x0 0.--31. 1. "IV0H,The initialization vector for DES TDES AES"
line.long 0x4 "IV0L,CAU initialization register"
hexmask.long 0x4 0.--31. 1. "IV0L,The initialization vector for DES TDES AES"
line.long 0x8 "IV1H,CAU initialization register"
hexmask.long 0x8 0.--31. 1. "IV1H,The initialization vector for DES TDES AES"
line.long 0xC "IV1L,CAU initialization register"
hexmask.long 0xC 0.--31. 1. "IV1L,The initialization vector for DES TDES AES"
line.long 0x10 "GCMCCMCTXS0,GCM or CCM mode context switch register 0"
hexmask.long 0x10 0.--31. 1. "CTX0,The internal status of the CAU core"
line.long 0x14 "GCMCCMCTXS1,GCM or CCM mode context switch register 1"
hexmask.long 0x14 0.--31. 1. "CTX1,The internal status of the CAU core"
line.long 0x18 "GCMCCMCTXS2,GCM or CCM mode context switch register 2"
hexmask.long 0x18 0.--31. 1. "CTX2,The internal status of the CAU core"
line.long 0x1C "GCMCCMCTXS3,GCM or CCM mode context switch register 3"
hexmask.long 0x1C 0.--31. 1. "CTX3,The internal status of the CAU core"
line.long 0x20 "GCMCCMCTXS4,GCM or CCM mode context switch register 4"
hexmask.long 0x20 0.--31. 1. "CTX4,The internal status of the CAU core"
line.long 0x24 "GCMCCMCTXS5,GCM or CCM mode context switch register 5"
hexmask.long 0x24 0.--31. 1. "CTX5,The internal status of the CAU core"
line.long 0x28 "GCMCCMCTXS6,GCM or CCM mode context switch register 6"
hexmask.long 0x28 0.--31. 1. "CTX6,The internal status of the CAU core"
line.long 0x2C "GCMCCMCTXS7,GCM or CCM mode context switch register 7"
hexmask.long 0x2C 0.--31. 1. "CTX7,The internal status of the CAU core"
line.long 0x30 "GCMCTXS0,GCM mode context switch register 0"
hexmask.long 0x30 0.--31. 1. "CTX0,The internal status of the CAU core"
line.long 0x34 "GCMCTXS1,GCM mode context switch register 1"
hexmask.long 0x34 0.--31. 1. "CTX1,The internal status of the CAU core"
line.long 0x38 "GCMCTXS2,GCM mode context switch register 2"
hexmask.long 0x38 0.--31. 1. "CTX2,The internal status of the CAU core"
line.long 0x3C "GCMCTXS3,GCM mode context switch register 3"
hexmask.long 0x3C 0.--31. 1. "CTX3,The internal status of the CAU core"
line.long 0x40 "GCMCTXS4,GCM mode context switch register 4"
hexmask.long 0x40 0.--31. 1. "CTX4,The internal status of the CAU core"
line.long 0x44 "GCMCTXS5,GCM mode context switch register 5"
hexmask.long 0x44 0.--31. 1. "CTX5,The internal status of the CAU core"
line.long 0x48 "GCMCTXS6,GCM mode context switch register 6"
hexmask.long 0x48 0.--31. 1. "CTX6,The internal status of the CAU core"
line.long 0x4C "GCMCTXS7,GCM mode context switch register 7"
hexmask.long 0x4C 0.--31. 1. "CTX7,The internal status of the CAU core"
tree.end
tree "CLA (Configurable Logic Array)"
base ad:0x40038000
group.long 0x0++0xB
line.long 0x0 "GCTL,Global control register"
bitfld.long 0x0 3. "CLA3EN,CLA3 unit enable" "0,1"
bitfld.long 0x0 2. "CLA2EN,CLA2 unit enable" "0,1"
bitfld.long 0x0 1. "CLA1EN,CLA1 unit enable" "0,1"
bitfld.long 0x0 0. "CLA0EN,CLA0 unit enable" "0,1"
line.long 0x4 "INTE,Interrupt enable register"
bitfld.long 0x4 7. "CLA3PIE,CLA3 unit posedge interrupt enable" "0,1"
bitfld.long 0x4 6. "CLA3NIE,CLA3 unit negedge interrupt enable" "0,1"
bitfld.long 0x4 5. "CLA2PIE,CLA2 unit posedge interrupt enable" "0,1"
bitfld.long 0x4 4. "CLA2NIE,CLA2 unit negedge interrupt enable" "0,1"
bitfld.long 0x4 3. "CLA1PIE,CLA1 unit posedge interrupt enable" "0,1"
bitfld.long 0x4 2. "CLA1NIE,CLA1 unit negedge interrupt enable" "0,1"
bitfld.long 0x4 1. "CLA0PIE,CLA0 unit posedge interrupt enable" "0,1"
bitfld.long 0x4 0. "CLA0NIE,CLA0 unit negedge interrupt enable" "0,1"
line.long 0x8 "INTF,Interrupt flag register"
bitfld.long 0x8 7. "CLA3PF,CLA3 unit posedge flag" "0,1"
bitfld.long 0x8 6. "CLA3NF,CLA3 unit negedge flag" "0,1"
bitfld.long 0x8 5. "CLA2PF,CLA2 unit posedge flag" "0,1"
bitfld.long 0x8 4. "CLA2NF,CLA2 unit negedge flag" "0,1"
bitfld.long 0x8 3. "CLA1PF,CLA1 unit posedge flag" "0,1"
bitfld.long 0x8 2. "CLA1NF,CLA1 unit negedge flag" "0,1"
bitfld.long 0x8 1. "CLA0PF,CLA0 unit posedge flag" "0,1"
bitfld.long 0x8 0. "CLA0NF,CLA0 unit negedge flag" "0,1"
rgroup.long 0xC++0x3
line.long 0x0 "STAT,Status register"
bitfld.long 0x0 3. "CLA3OUT,CLA3 unit output state" "0,1"
bitfld.long 0x0 2. "CLA2OUT,CLA2 unit output state" "0,1"
bitfld.long 0x0 1. "CLA1OUT,CLA1 unit output state" "0,1"
bitfld.long 0x0 0. "CLA0OUT,CLA0 unit output state" "0,1"
group.long 0x10++0x2F
line.long 0x0 "CLA0_SIGS,Signal selection register 0"
hexmask.long.byte 0x0 4.--7. 1. "SIGS0,Signal Selector 0 input selection"
hexmask.long.byte 0x0 0.--3. 1. "SIGS1,Signal Selector 1 input selection"
line.long 0x4 "CLA0_LCUCTL,LCU control register 0"
hexmask.long.byte 0x4 0.--7. 1. "LCUCTL,LCU control"
line.long 0x8 "CLA0_CTL,Control register 0"
bitfld.long 0x8 7. "OSEL,Output selection" "0,1"
bitfld.long 0x8 6. "OEN,Output enable" "0,1"
bitfld.long 0x8 3. "FFRST,Flip-flop output reset" "0,1"
bitfld.long 0x8 2. "CPOL,Clock polarity of Flip-flop" "0,1"
bitfld.long 0x8 0.--1. "CSEL,Flip-flop clock source selection" "0,1,2,3"
line.long 0xC "CLA1_SIGS,Signal selection register 1"
hexmask.long.byte 0xC 4.--7. 1. "SIGS0,Signal Selector 0 input selection"
hexmask.long.byte 0xC 0.--3. 1. "SIGS1,Signal Selector 1 input selection"
line.long 0x10 "CLA1_LCUCTL,LCU control register 1"
hexmask.long.byte 0x10 0.--7. 1. "LCU,LCU control"
line.long 0x14 "CLA1_CTL,Control register 1"
bitfld.long 0x14 7. "OSEL,Output selection" "0,1"
bitfld.long 0x14 6. "OEN,Output enable" "0,1"
bitfld.long 0x14 3. "FFRST,Flip-flop output reset" "0,1"
bitfld.long 0x14 2. "CPOL,Clock polarity of Flip-flop" "0,1"
bitfld.long 0x14 0.--1. "CSEL,Flip-flop clock source selection" "0,1,2,3"
line.long 0x18 "CLA2_SIGS,Signal selection register 2"
hexmask.long.byte 0x18 4.--7. 1. "SIGS0,Signal Selector 0 input selection"
hexmask.long.byte 0x18 0.--3. 1. "SIGS1,Signal Selector 1 input selection"
line.long 0x1C "CLA2_LCUCTL,LCU control register 2"
hexmask.long.byte 0x1C 0.--7. 1. "LCU,LCU control"
line.long 0x20 "CLA2_CTL,Control register 2"
bitfld.long 0x20 7. "OSEL,Output selection" "0,1"
bitfld.long 0x20 6. "OEN,Output enable" "0,1"
bitfld.long 0x20 3. "FFRST,Flip-flop output reset" "0,1"
bitfld.long 0x20 2. "CPOL,Clock polarity of Flip-flop" "0,1"
bitfld.long 0x20 0.--1. "CSEL,Flip-flop clock source selection" "0,1,2,3"
line.long 0x24 "CLA3_SIGS,Signal selection register 3"
hexmask.long.byte 0x24 4.--7. 1. "SIGS0,Signal Selector 0 input selection"
hexmask.long.byte 0x24 0.--3. 1. "SIGS1,Signal Selector 1 input selection"
line.long 0x28 "CLA3_LCUCTL,LCU control register 3"
hexmask.long.byte 0x28 0.--7. 1. "LCU,LCU control"
line.long 0x2C "CLA3_CTL,Control register 3"
bitfld.long 0x2C 7. "OSEL,Output selection" "0,1"
bitfld.long 0x2C 6. "OEN,Output enable" "0,1"
bitfld.long 0x2C 3. "FFRST,Flip-flop output reset" "0,1"
bitfld.long 0x2C 2. "CPOL,Clock polarity of Flip-flop" "0,1"
bitfld.long 0x2C 0.--1. "CSEL,Flip-flop clock source selection" "0,1,2,3"
tree.end
tree "CMP (Comparator)"
base ad:0x40017C00
group.long 0x0++0x3
line.long 0x0 "STAT,CMP status register"
bitfld.long 0x0 23. "CMP7IF,CMP7 interrupt flag" "0,1"
bitfld.long 0x0 22. "CMP6IF,CMP6 interrupt flag" "0,1"
bitfld.long 0x0 21. "CMP5IF,CMP5 interrupt flag" "0,1"
bitfld.long 0x0 20. "CMP4IF,CMP4 interrupt flag" "0,1"
bitfld.long 0x0 19. "CMP3IF,CMP3 interrupt flag" "0,1"
bitfld.long 0x0 18. "CMP2IF,CMP2 interrupt flag" "0,1"
bitfld.long 0x0 17. "CMP1IF,CMP1 interrupt flag" "0,1"
bitfld.long 0x0 16. "CMP0IF,CMP0 interrupt flag" "0,1"
rbitfld.long 0x0 7. "CMP7O,CMP7 output state" "0,1"
rbitfld.long 0x0 6. "CMP6O,CMP6 output state" "0,1"
newline
rbitfld.long 0x0 5. "CMP5O,CMP5 output state" "0,1"
rbitfld.long 0x0 4. "CMP4O,CMP4 output state" "0,1"
rbitfld.long 0x0 3. "CMP3O,CMP3 output state" "0,1"
rbitfld.long 0x0 2. "CMP2O,CMP2 output state" "0,1"
rbitfld.long 0x0 1. "CMP1O,CMP1 output state" "0,1"
rbitfld.long 0x0 0. "CMP0O,CMP0 output state" "0,1"
wgroup.long 0x4++0x3
line.long 0x0 "IFC,CMP interrupt flag clear register"
bitfld.long 0x0 23. "CMP7IC,CMP7 interrupt flag clear" "0,1"
bitfld.long 0x0 22. "CMP6IC,CMP6 interrupt flag clear" "0,1"
bitfld.long 0x0 21. "CMP5IC,CMP5 interrupt flag clear" "0,1"
bitfld.long 0x0 20. "CMP4IC,CMP4 interrupt flag clear" "0,1"
bitfld.long 0x0 19. "CMP3IC,CMP3 interrupt flag clear" "0,1"
bitfld.long 0x0 18. "CMP2IC,CMP2 interrupt flag clear" "0,1"
bitfld.long 0x0 17. "CMP1IC,CMP1 interrupt flag clear" "0,1"
bitfld.long 0x0 16. "CMP0IC,CMP0 interrupt flag clear" "0,1"
group.long 0x8++0x1F
line.long 0x0 "CMP0_CS,CMP0 control/status register"
bitfld.long 0x0 31. "CMP0LK,CMP0 lock" "0,1"
hexmask.long.byte 0x0 24.--27. 1. "CMP0BLK,CMP0 output blanking source"
bitfld.long 0x0 20. "CMP0PSEL,CMP0_IP input selection" "0,1"
bitfld.long 0x0 16.--18. "CMP0MSEL,CMP0_IM internal input selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 8.--10. "CMP0HST,CMP0 hysteresis" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 7. "CMP0RSTMD,CMP0 reset mode" "0,1"
bitfld.long 0x0 6. "CMP0INTEN,CMP0 interrupt enable" "0,1"
bitfld.long 0x0 3. "CMP0PL,Polarity of CMP0 output" "0,1"
bitfld.long 0x0 2. "CMP0SEN,Voltage scaler enable bit" "0,1"
bitfld.long 0x0 1. "CMP0BEN,Scaler bridge enable bit" "0,1"
newline
bitfld.long 0x0 0. "CMP0EN,CMP0 enable" "0,1"
line.long 0x4 "CMP1_CS,CMP1 control/status register"
bitfld.long 0x4 31. "CMP1LK,CMP1 lock" "0,1"
hexmask.long.byte 0x4 24.--27. 1. "CMP1BLK,CMP1 output blanking source"
bitfld.long 0x4 20. "CMP1PSEL,CMP1_IP input selection" "0,1"
bitfld.long 0x4 16.--18. "CMP1MSEL,CMP1_IM internal input selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 8.--10. "CMP1HST,CMP1 hysteresis" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 7. "CMP1RSTMD,CMP1 reset mode" "0,1"
bitfld.long 0x4 6. "CMP1INTEN,CMP1 interrupt enable" "0,1"
bitfld.long 0x4 3. "CMP1PL,Polarity of CMP1 output" "0,1"
bitfld.long 0x4 2. "CMP1SEN,Voltage scaler enable bit" "0,1"
bitfld.long 0x4 1. "CMP1BEN,Scaler bridge enable bit" "0,1"
newline
bitfld.long 0x4 0. "CMP1EN,CMP1 enable" "0,1"
line.long 0x8 "CMP2_CS,CMP2 control/status register"
bitfld.long 0x8 31. "CMP2LK,CMP2 lock" "0,1"
hexmask.long.byte 0x8 24.--27. 1. "CMP2BLK,CMP2 output blanking source"
bitfld.long 0x8 20. "CMP2PSEL,CMP2_IP input selection" "0,1"
bitfld.long 0x8 16.--18. "CMP2MSEL,CMP2_IM internal input selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 8.--10. "CMP2HST,CMP2 hysteresis" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 7. "CMP2RSTMD,CMP2 reset mode" "0,1"
bitfld.long 0x8 6. "CMP2INTEN,CMP2 interrupt enable" "0,1"
bitfld.long 0x8 3. "CMP2PL,Polarity of CMP2 output" "0,1"
bitfld.long 0x8 2. "CMP2SEN,Voltage scaler enable bit" "0,1"
bitfld.long 0x8 1. "CMP2BEN,Scaler bridge enable bit" "0,1"
newline
bitfld.long 0x8 0. "CMP2EN,CMP2 enable" "0,1"
line.long 0xC "CMP3_CS,CMP3 control/status register"
bitfld.long 0xC 31. "CMP3LK,CMP3 lock" "0,1"
hexmask.long.byte 0xC 24.--27. 1. "CMP3BLK,CMP3 output blanking source"
bitfld.long 0xC 20. "CMP3PSEL,CMP3_IP input selection" "0,1"
bitfld.long 0xC 16.--18. "CMP3MSEL,CMP3_IM internal input selection" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 8.--10. "CMP3HST,CMP3 hysteresis" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 7. "CMP3RSTMD,CMP3 reset mode" "0,1"
bitfld.long 0xC 6. "CMP3INTEN,CMP3 interrupt enable" "0,1"
bitfld.long 0xC 3. "CMP3PL,Polarity of CMP3 output" "0,1"
bitfld.long 0xC 2. "CMP3SEN,Voltage scaler enable bit" "0,1"
bitfld.long 0xC 1. "CMP3BEN,Scaler bridge enable bit" "0,1"
newline
bitfld.long 0xC 0. "CMP3EN,CMP3 enable" "0,1"
line.long 0x10 "CMP4_CS,CMP4 control/status register"
bitfld.long 0x10 31. "CMP4LK,CMP4 lock" "0,1"
hexmask.long.byte 0x10 24.--27. 1. "CMP4BLK,CMP4 output blanking source"
bitfld.long 0x10 20. "CMP4PSEL,CMP4_IP input selection" "0,1"
bitfld.long 0x10 16.--18. "CMP4MSEL,CMP4_IM internal input selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 8.--10. "CMP4HST,CMP4 hysteresis" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 7. "CMP4RSTMD,CMP4 reset mode" "0,1"
bitfld.long 0x10 6. "CMP4INTEN,CMP4 interrupt enable" "0,1"
bitfld.long 0x10 3. "CMP4PL,Polarity of CMP4 output" "0,1"
bitfld.long 0x10 2. "CMP3SEN,Voltage scaler enable bit" "0,1"
bitfld.long 0x10 1. "CMP3BEN,Scaler bridge enable bit" "0,1"
newline
bitfld.long 0x10 0. "CMP4EN,CMP4 enable" "0,1"
line.long 0x14 "CMP5_CS,CMP5 control/status register"
bitfld.long 0x14 31. "CMP5LK,CMP5 lock" "0,1"
hexmask.long.byte 0x14 24.--27. 1. "CMP5BLK,CMP5 output blanking source"
bitfld.long 0x14 20. "CMP5PSEL,CMP5_IP input selection" "0,1"
bitfld.long 0x14 16.--18. "CMP5MSEL,CMP5_IM internal input selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 8.--10. "CMP5HST,CMP5 hysteresis" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 7. "CMP5RSTMD,CMP5 reset mode" "0,1"
bitfld.long 0x14 6. "CMP5INTEN,CMP5 interrupt enable" "0,1"
bitfld.long 0x14 3. "CMP5PL,Polarity of CMP5 output" "0,1"
bitfld.long 0x14 2. "CMP5SEN,Voltage scaler enable bit" "0,1"
bitfld.long 0x14 1. "CMP5BEN,Scaler bridge enable bit" "0,1"
newline
bitfld.long 0x14 0. "CMP5EN,CMP5 enable" "0,1"
line.long 0x18 "CMP6_CS,CMP6 control/status register"
bitfld.long 0x18 31. "CMP6LK,CMP6 lock" "0,1"
hexmask.long.byte 0x18 24.--27. 1. "CMP6BLK,CMP6 output blanking source"
bitfld.long 0x18 20. "CMP6PSEL,CMP6_IP input selection" "0,1"
bitfld.long 0x18 16.--18. "CMP6MSEL,CMP6_IM internal input selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 8.--10. "CMP6HST,CMP6 hysteresis" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 7. "CMP6RSTMD,CMP6 reset mode" "0,1"
bitfld.long 0x18 6. "CMP6INTEN,CMP6 interrupt enable" "0,1"
bitfld.long 0x18 3. "CMP6PL,Polarity of CMP6 output" "0,1"
bitfld.long 0x18 2. "CMP6SEN,Voltage scaler enable bit" "0,1"
bitfld.long 0x18 1. "CMP6BEN,Scaler bridge enable bit" "0,1"
newline
bitfld.long 0x18 0. "CMP6EN,CMP6 enable" "0,1"
line.long 0x1C "CMP7_CS,CMP7 control/status register"
bitfld.long 0x1C 31. "CMP7LK,CMP7 lock" "0,1"
hexmask.long.byte 0x1C 24.--27. 1. "CMP7BLK,CMP7 output blanking source"
bitfld.long 0x1C 20.--21. "CMP7PSEL,CMP7_IP input selection" "0,1,2,3"
bitfld.long 0x1C 16.--18. "CMP7MSEL,CMP7_IM internal input selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 8.--10. "CMP7HST,CMP7 hysteresis" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 7. "CMP7RSTMD,CMP7 reset mode" "0,1"
bitfld.long 0x1C 6. "CMP7INTEN,CMP7 interrupt enable" "0,1"
bitfld.long 0x1C 3. "CMP7PL,Polarity of CMP7 output" "0,1"
bitfld.long 0x1C 2. "CMP7SEN,Voltage scaler enable bit" "0,1"
bitfld.long 0x1C 1. "CMP7BEN,Scaler bridge enable bit" "0,1"
newline
bitfld.long 0x1C 0. "CMP7EN,CMP7 enable" "0,1"
tree.end
tree "CPDM (Clock Phase Delay Module)"
base ad:0x48022800
group.long 0x0++0x7
line.long 0x0 "CTL,Control register"
bitfld.long 0x0 1. "DLSEN,CPDM delay line sample module enable bit" "0,1"
bitfld.long 0x0 0. "CPDMEN,CPDM enable bit" "0,1"
line.long 0x4 "CFG,Configuration register"
rbitfld.long 0x4 31. "DLLENF,Valid mark of delay line length" "0,1"
hexmask.long.word 0x4 16.--27. 1. "DLLEN,Delay line length"
hexmask.long.byte 0x4 8.--14. 1. "DLSTCNT,Defines a delay step count for a unit delay UNIT"
hexmask.long.byte 0x4 0.--3. 1. "CPSEL,Output clock phase selection"
tree.end
tree "CRC (Cyclic Redundancy Check Calculation Unit)"
base ad:0x40023000
group.long 0x0++0xB
line.long 0x0 "DATA,Data register"
hexmask.long 0x0 0.--31. 1. "DATA,CRC calculation result bits"
line.long 0x4 "FDATA,Free data register"
hexmask.long.byte 0x4 0.--7. 1. "FDATA,Free data register bits"
line.long 0x8 "CTL,Control register"
bitfld.long 0x8 7. "REV_O,Reverse output data value in bit order" "0,1"
bitfld.long 0x8 5.--6. "REV_I,Reverse type for input data" "0,1,2,3"
bitfld.long 0x8 3.--4. "PS,Size of polynomial" "0,1,2,3"
bitfld.long 0x8 0. "RST,reset bit" "0,1"
group.long 0x10++0x7
line.long 0x0 "IDATA,Initialization data register"
hexmask.long 0x0 0.--31. 1. "IDATA,Configurable initial CRC data value"
line.long 0x4 "POLY,Polynomial register"
hexmask.long 0x4 0.--31. 1. "POLY,User configurable polynomial value"
tree.end
tree "DAC (Digital-to-Analog Converter)"
base ad:0x0
tree "DAC0"
base ad:0x50001000
group.long 0x0++0x3
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 31. "DRSTMD1,DAC_OUT1 reset mode" "0,1"
bitfld.long 0x0 30. "CALEN1,DAC_OUT1 calibration enable" "0,1"
bitfld.long 0x0 29. "DDUDRIE1,DAC_OUT1 DMA underrun interrupt enable" "0,1"
bitfld.long 0x0 28. "DDMAEN1,DAC_OUT1 DMA enable" "0,1"
hexmask.long.byte 0x0 24.--27. 1. "DWBW1,DAC_OUT1 noise wave bit width"
bitfld.long 0x0 22.--23. "DWM1,DAC_OUT1 noise wave mode" "0,1,2,3"
bitfld.long 0x0 18.--19. "DTSEL1,DAC_OUT1 trigger selection" "0,1,2,3"
newline
bitfld.long 0x0 17. "DTEN1,DAC_OUT1 trigger enable" "0,1"
bitfld.long 0x0 16. "DEN1,DAC_OUT1 enable" "0,1"
bitfld.long 0x0 15. "DRSTMD0,DAC_OUT0 reset mode" "0,1"
bitfld.long 0x0 14. "CALEN0,DAC_OUT0 calibration enable" "0,1"
bitfld.long 0x0 13. "DDUDRIE0,DAC_OUT0 DMA underrun interrupt enable" "0,1"
bitfld.long 0x0 12. "DDMAEN0,DAC_OUT0 DMA enable" "0,1"
hexmask.long.byte 0x0 8.--11. 1. "DWBW0,DAC_OUT0 noise wave bit width"
newline
bitfld.long 0x0 6.--7. "DWM0,DAC_OUT0 noise wave mode" "0,1,2,3"
bitfld.long 0x0 2.--3. "DTSEL0,DAC_OUT0 trigger selection" "0,1,2,3"
bitfld.long 0x0 1. "DTEN0,DAC_OUT0 trigger enable" "0,1"
bitfld.long 0x0 0. "DEN0,DAC_OUT0 enable" "0,1"
wgroup.long 0x4++0x3
line.long 0x0 "SWT,Software trigger register"
bitfld.long 0x0 17. "SWSTTR1,DAC_OUT1 sawtooth step-up/down software trigger" "0,1"
bitfld.long 0x0 16. "SWSTTR0,DAC_OUT0 sawtooth step-up/down software trigger" "0,1"
bitfld.long 0x0 1. "SWTR1,DAC_OUT1 software trigger cleared by hardware" "0,1"
bitfld.long 0x0 0. "SWTR0,DAC_OUT0 software trigger cleared by hardware" "0,1"
group.long 0x8++0x23
line.long 0x0 "OUT0_R12DH,DAC_OUT0 12-bit right-aligned data holding register"
hexmask.long.word 0x0 0.--11. 1. "OUT0_DH,DAC_OUT0 12-bit right-aligned data"
line.long 0x4 "OUT0_L12DH,DAC_OUT0 12-bit left-aligned data holding register"
hexmask.long.word 0x4 4.--15. 1. "OUT0_DH,DAC_OUT0 12-bit left-aligned data"
line.long 0x8 "OUT0_R8DH,DAC_OUT0 8-bit right-aligned data holding register"
hexmask.long.byte 0x8 0.--7. 1. "OUT0_DH,DAC_OUT0 8-bit right-aligned data"
line.long 0xC "OUT1_R12DH,DAC_OUT1 12-bit right-aligned data holding register"
hexmask.long.word 0xC 0.--11. 1. "OUT1_DH,DAC_OUT1 12-bit right-aligned data"
line.long 0x10 "OUT1_L12DH,DAC_OUT1 12-bit left-aligned data holding register"
hexmask.long.word 0x10 4.--15. 1. "OUT1_DH,DAC_OUT1 12-bit left-aligned data"
line.long 0x14 "OUT1_R8DH,DAC_OUT1 8-bit right-aligned data holding register"
hexmask.long.byte 0x14 0.--7. 1. "OUT1_DH,DAC_OUT1 8-bit right-aligned data"
line.long 0x18 "DACC_R12DH,DAC concurrent mode 12-bit right-aligned data holding register"
hexmask.long.word 0x18 16.--27. 1. "OUT1_DH,DAC_OUT1 12-bit right-aligned data"
hexmask.long.word 0x18 0.--11. 1. "OUT0_DH,DAC_OUT0 12-bit right-aligned data"
line.long 0x1C "DACC_L12DH,DAC concurrent mode 12-bit left-aligned data holding register"
hexmask.long.word 0x1C 20.--31. 1. "OUT1_DH,DAC_OUT1 12-bit left-aligned data"
hexmask.long.word 0x1C 4.--15. 1. "OUT0_DH,DAC_OUT0 12-bit left-aligned data"
line.long 0x20 "DACC_R8DH,DAC concurrent mode 8-bit right-aligned data holding register"
hexmask.long.byte 0x20 8.--15. 1. "OUT1_DH,DAC_OUT1 8-bit right-aligned data"
hexmask.long.byte 0x20 0.--7. 1. "OUT0_DH,DAC_OUT0 8-bit right-aligned data"
rgroup.long 0x2C++0x7
line.long 0x0 "OUT0_DO,DAC_OUT0 data output register"
hexmask.long.word 0x0 0.--11. 1. "OUT0_DO,DAC_OUT0 data output"
line.long 0x4 "OUT1_DO,DAC_OUT1 data output register"
hexmask.long.word 0x4 0.--11. 1. "OUT1_DO,DAC_OUT1 data output"
group.long 0x34++0x1B
line.long 0x0 "STAT0,DAC status register 0"
rbitfld.long 0x0 31. "BWT1,DAC_OUT1 TSAMP1[9:0] writing busy flag" "0,1"
rbitfld.long 0x0 30. "CALF1,DAC_OUT1 calibration offset flag" "0,1"
bitfld.long 0x0 29. "DDUDR1,DAC_OUT1 DMA underrun flag set by hardware cleared by software write 1" "0,1"
rbitfld.long 0x0 15. "BWT0,DAC_OUT0 TSAMP0[9:0] writing busy flag" "0,1"
rbitfld.long 0x0 14. "CALF0,DAC_OUT0 calibration offset flag" "0,1"
bitfld.long 0x0 13. "DDUDR0,DAC_OUT0 DMA underrun flag" "0,1"
line.long 0x4 "CALR,DAC calibration Register"
hexmask.long.byte 0x4 16.--20. 1. "OTV1,DAC_OUT1 offset calibration value"
hexmask.long.byte 0x4 0.--4. 1. "OTV0,DAC_OUT0 offset calibration value"
line.long 0x8 "MDCR,DAC mode control register"
bitfld.long 0x8 25. "DHFMT1,DAC_OUT1 data format written in data holding register" "0,1"
bitfld.long 0x8 16.--18. "MODE1,DAC_OUT1 mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 9. "DHFMT0,DAC_OUT0 data format written in data holding register" "0,1"
bitfld.long 0x8 0.--2. "MODE0,DAC_OUT0 mode" "0,1,2,3,4,5,6,7"
line.long 0xC "SKSTR0,DAC sample and keep sample time register 0"
hexmask.long.word 0xC 0.--9. 1. "TSAMP0,DAC_OUT0 sample time"
line.long 0x10 "SKSTR1,DAC sample and keep sample time register 1"
hexmask.long.word 0x10 0.--9. 1. "TSAMP1,DAC_OUT1 sample time"
line.long 0x14 "SKKTR,DAC sample and keep keep time register"
hexmask.long.word 0x14 16.--25. 1. "TKEEP1,DAC_OUT1 keep time (only available in sample and keep mode)"
hexmask.long.word 0x14 0.--9. 1. "TKEEP0,DAC_OUT0 keep time (only available in sample and keep mode)"
line.long 0x18 "SKRTR,DAC sample and keep refresh time register"
hexmask.long.byte 0x18 16.--23. 1. "TREF1,DAC_OUT1 refresh time (only available in sample and keep mode)"
hexmask.long.byte 0x18 0.--7. 1. "TREF0,DAC_OUT refresh time (only available in sample and keep mode)"
group.long 0x58++0xB
line.long 0x0 "OUT0_SAW,DAC_OUT0 sawtooth register"
hexmask.long.word 0x0 16.--31. 1. "SAWSTEP0,DAC_OUT0 sawtooth step value"
bitfld.long 0x0 12. "SAWDIR0,DAC_OUT0 sawtooth step direction" "0,1"
hexmask.long.word 0x0 0.--11. 1. "SAWINIT0,DAC_OUT0 sawtooth initial value"
line.long 0x4 "OUT1_SAW,DAC_OUT1 sawtooth register"
hexmask.long.word 0x4 16.--31. 1. "SAWSTEP1,DAC_OUT1 sawtooth step value"
bitfld.long 0x4 12. "SAWDIR1,DAC_OUT1 sawtooth step direction" "0,1"
hexmask.long.word 0x4 0.--11. 1. "SAWINIT1,DAC_OUT1 sawtooth initial value"
line.long 0x8 "SAWMDR,DAC sawtooth mode register"
bitfld.long 0x8 24.--25. "SAWSTEPTSEL1,DAC_OUT1 sawtooth step-up/down trigger selection" "0,1,2,3"
bitfld.long 0x8 16.--17. "SAWRSTTSEL1,DAC_OUT1 sawtooth reset to initial value trigger selection" "0,1,2,3"
bitfld.long 0x8 8.--9. "SAWSTEPTSEL0,DAC_OUT0 sawtooth step-up/down trigger selection" "0,1,2,3"
bitfld.long 0x8 0.--1. "SAWRSTTSEL0,DAC_OUT0 sawtooth reset to initial value trigger selection" "0,1,2,3"
tree.end
tree "DAC1"
base ad:0x50001400
group.long 0x0++0x3
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 31. "DRSTMD1,DAC_OUT1 reset mode" "0,1"
bitfld.long 0x0 30. "CALEN1,DAC_OUT1 calibration enable" "0,1"
bitfld.long 0x0 29. "DDUDRIE1,DAC_OUT1 DMA underrun interrupt enable" "0,1"
bitfld.long 0x0 28. "DDMAEN1,DAC_OUT1 DMA enable" "0,1"
hexmask.long.byte 0x0 24.--27. 1. "DWBW1,DAC_OUT1 noise wave bit width"
bitfld.long 0x0 22.--23. "DWM1,DAC_OUT1 noise wave mode" "0,1,2,3"
bitfld.long 0x0 18.--19. "DTSEL1,DAC_OUT1 trigger selection" "0,1,2,3"
newline
bitfld.long 0x0 17. "DTEN1,DAC_OUT1 trigger enable" "0,1"
bitfld.long 0x0 16. "DEN1,DAC_OUT1 enable" "0,1"
bitfld.long 0x0 15. "DRSTMD0,DAC_OUT0 reset mode" "0,1"
bitfld.long 0x0 14. "CALEN0,DAC_OUT0 calibration enable" "0,1"
bitfld.long 0x0 13. "DDUDRIE0,DAC_OUT0 DMA underrun interrupt enable" "0,1"
bitfld.long 0x0 12. "DDMAEN0,DAC_OUT0 DMA enable" "0,1"
hexmask.long.byte 0x0 8.--11. 1. "DWBW0,DAC_OUT0 noise wave bit width"
newline
bitfld.long 0x0 6.--7. "DWM0,DAC_OUT0 noise wave mode" "0,1,2,3"
bitfld.long 0x0 2.--3. "DTSEL0,DAC_OUT0 trigger selection" "0,1,2,3"
bitfld.long 0x0 1. "DTEN0,DAC_OUT0 trigger enable" "0,1"
bitfld.long 0x0 0. "DEN0,DAC_OUT0 enable" "0,1"
wgroup.long 0x4++0x3
line.long 0x0 "SWT,Software trigger register"
bitfld.long 0x0 17. "SWSTTR1,DAC_OUT1 sawtooth step-up/down software trigger" "0,1"
bitfld.long 0x0 16. "SWSTTR0,DAC_OUT0 sawtooth step-up/down software trigger" "0,1"
bitfld.long 0x0 1. "SWTR1,DAC_OUT1 software trigger cleared by hardware" "0,1"
bitfld.long 0x0 0. "SWTR0,DAC_OUT0 software trigger cleared by hardware" "0,1"
group.long 0x8++0x23
line.long 0x0 "OUT0_R12DH,DAC_OUT0 12-bit right-aligned data holding register"
hexmask.long.word 0x0 0.--11. 1. "OUT0_DH,DAC_OUT0 12-bit right-aligned data"
line.long 0x4 "OUT0_L12DH,DAC_OUT0 12-bit left-aligned data holding register"
hexmask.long.word 0x4 4.--15. 1. "OUT0_DH,DAC_OUT0 12-bit left-aligned data"
line.long 0x8 "OUT0_R8DH,DAC_OUT0 8-bit right-aligned data holding register"
hexmask.long.byte 0x8 0.--7. 1. "OUT0_DH,DAC_OUT0 8-bit right-aligned data"
line.long 0xC "OUT1_R12DH,DAC_OUT1 12-bit right-aligned data holding register"
hexmask.long.word 0xC 0.--11. 1. "OUT1_DH,DAC_OUT1 12-bit right-aligned data"
line.long 0x10 "OUT1_L12DH,DAC_OUT1 12-bit left-aligned data holding register"
hexmask.long.word 0x10 4.--15. 1. "OUT1_DH,DAC_OUT1 12-bit left-aligned data"
line.long 0x14 "OUT1_R8DH,DAC_OUT1 8-bit right-aligned data holding register"
hexmask.long.byte 0x14 0.--7. 1. "OUT1_DH,DAC_OUT1 8-bit right-aligned data"
line.long 0x18 "DACC_R12DH,DAC concurrent mode 12-bit right-aligned data holding register"
hexmask.long.word 0x18 16.--27. 1. "OUT1_DH,DAC_OUT1 12-bit right-aligned data"
hexmask.long.word 0x18 0.--11. 1. "OUT0_DH,DAC_OUT0 12-bit right-aligned data"
line.long 0x1C "DACC_L12DH,DAC concurrent mode 12-bit left-aligned data holding register"
hexmask.long.word 0x1C 20.--31. 1. "OUT1_DH,DAC_OUT1 12-bit left-aligned data"
hexmask.long.word 0x1C 4.--15. 1. "OUT0_DH,DAC_OUT0 12-bit left-aligned data"
line.long 0x20 "DACC_R8DH,DAC concurrent mode 8-bit right-aligned data holding register"
hexmask.long.byte 0x20 8.--15. 1. "OUT1_DH,DAC_OUT1 8-bit right-aligned data"
hexmask.long.byte 0x20 0.--7. 1. "OUT0_DH,DAC_OUT0 8-bit right-aligned data"
rgroup.long 0x2C++0x7
line.long 0x0 "OUT0_DO,DAC_OUT0 data output register"
hexmask.long.word 0x0 0.--11. 1. "OUT0_DO,DAC_OUT0 data output"
line.long 0x4 "OUT1_DO,DAC_OUT1 data output register"
hexmask.long.word 0x4 0.--11. 1. "OUT1_DO,DAC_OUT1 data output"
group.long 0x34++0x1B
line.long 0x0 "STAT0,DAC status register 0"
rbitfld.long 0x0 31. "BWT1,DAC_OUT1 TSAMP1[9:0] writing busy flag" "0,1"
rbitfld.long 0x0 30. "CALF1,DAC_OUT1 calibration offset flag" "0,1"
bitfld.long 0x0 29. "DDUDR1,DAC_OUT1 DMA underrun flag set by hardware cleared by software write 1" "0,1"
rbitfld.long 0x0 15. "BWT0,DAC_OUT0 TSAMP0[9:0] writing busy flag" "0,1"
rbitfld.long 0x0 14. "CALF0,DAC_OUT0 calibration offset flag" "0,1"
bitfld.long 0x0 13. "DDUDR0,DAC_OUT0 DMA underrun flag" "0,1"
line.long 0x4 "CALR,DAC calibration Register"
hexmask.long.byte 0x4 16.--20. 1. "OTV1,DAC_OUT1 offset calibration value"
hexmask.long.byte 0x4 0.--4. 1. "OTV0,DAC_OUT0 offset calibration value"
line.long 0x8 "MDCR,DAC mode control register"
bitfld.long 0x8 25. "DHFMT1,DAC_OUT1 data format written in data holding register" "0,1"
bitfld.long 0x8 16.--18. "MODE1,DAC_OUT1 mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 9. "DHFMT0,DAC_OUT0 data format written in data holding register" "0,1"
bitfld.long 0x8 0.--2. "MODE0,DAC_OUT0 mode" "0,1,2,3,4,5,6,7"
line.long 0xC "SKSTR0,DAC sample and keep sample time register 0"
hexmask.long.word 0xC 0.--9. 1. "TSAMP0,DAC_OUT0 sample time"
line.long 0x10 "SKSTR1,DAC sample and keep sample time register 1"
hexmask.long.word 0x10 0.--9. 1. "TSAMP1,DAC_OUT1 sample time"
line.long 0x14 "SKKTR,DAC sample and keep keep time register"
hexmask.long.word 0x14 16.--25. 1. "TKEEP1,DAC_OUT1 keep time (only available in sample and keep mode)"
hexmask.long.word 0x14 0.--9. 1. "TKEEP0,DAC_OUT0 keep time (only available in sample and keep mode)"
line.long 0x18 "SKRTR,DAC sample and keep refresh time register"
hexmask.long.byte 0x18 16.--23. 1. "TREF1,DAC_OUT1 refresh time (only available in sample and keep mode)"
hexmask.long.byte 0x18 0.--7. 1. "TREF0,DAC_OUT refresh time (only available in sample and keep mode)"
group.long 0x58++0xB
line.long 0x0 "OUT0_SAW,DAC_OUT0 sawtooth register"
hexmask.long.word 0x0 16.--31. 1. "SAWSTEP0,DAC_OUT0 sawtooth step value"
bitfld.long 0x0 12. "SAWDIR0,DAC_OUT0 sawtooth step direction" "0,1"
hexmask.long.word 0x0 0.--11. 1. "SAWINIT0,DAC_OUT0 sawtooth initial value"
line.long 0x4 "OUT1_SAW,DAC_OUT1 sawtooth register"
hexmask.long.word 0x4 16.--31. 1. "SAWSTEP1,DAC_OUT1 sawtooth step value"
bitfld.long 0x4 12. "SAWDIR1,DAC_OUT1 sawtooth step direction" "0,1"
hexmask.long.word 0x4 0.--11. 1. "SAWINIT1,DAC_OUT1 sawtooth initial value"
line.long 0x8 "SAWMDR,DAC sawtooth mode register"
bitfld.long 0x8 24.--25. "SAWSTEPTSEL1,DAC_OUT1 sawtooth step-up/down trigger selection" "0,1,2,3"
bitfld.long 0x8 16.--17. "SAWRSTTSEL1,DAC_OUT1 sawtooth reset to initial value trigger selection" "0,1,2,3"
bitfld.long 0x8 8.--9. "SAWSTEPTSEL0,DAC_OUT0 sawtooth step-up/down trigger selection" "0,1,2,3"
bitfld.long 0x8 0.--1. "SAWRSTTSEL0,DAC_OUT0 sawtooth reset to initial value trigger selection" "0,1,2,3"
tree.end
tree "DAC2"
base ad:0x50001800
group.long 0x0++0x3
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 31. "DRSTMD1,DAC_OUT1 reset mode" "0,1"
bitfld.long 0x0 30. "CALEN1,DAC_OUT1 calibration enable" "0,1"
bitfld.long 0x0 29. "DDUDRIE1,DAC_OUT1 DMA underrun interrupt enable" "0,1"
bitfld.long 0x0 28. "DDMAEN1,DAC_OUT1 DMA enable" "0,1"
hexmask.long.byte 0x0 24.--27. 1. "DWBW1,DAC_OUT1 noise wave bit width"
bitfld.long 0x0 22.--23. "DWM1,DAC_OUT1 noise wave mode" "0,1,2,3"
bitfld.long 0x0 18.--19. "DTSEL1,DAC_OUT1 trigger selection" "0,1,2,3"
newline
bitfld.long 0x0 17. "DTEN1,DAC_OUT1 trigger enable" "0,1"
bitfld.long 0x0 16. "DEN1,DAC_OUT1 enable" "0,1"
bitfld.long 0x0 15. "DRSTMD0,DAC_OUT0 reset mode" "0,1"
bitfld.long 0x0 14. "CALEN0,DAC_OUT0 calibration enable" "0,1"
bitfld.long 0x0 13. "DDUDRIE0,DAC_OUT0 DMA underrun interrupt enable" "0,1"
bitfld.long 0x0 12. "DDMAEN0,DAC_OUT0 DMA enable" "0,1"
hexmask.long.byte 0x0 8.--11. 1. "DWBW0,DAC_OUT0 noise wave bit width"
newline
bitfld.long 0x0 6.--7. "DWM0,DAC_OUT0 noise wave mode" "0,1,2,3"
bitfld.long 0x0 2.--3. "DTSEL0,DAC_OUT0 trigger selection" "0,1,2,3"
bitfld.long 0x0 1. "DTEN0,DAC_OUT0 trigger enable" "0,1"
bitfld.long 0x0 0. "DEN0,DAC_OUT0 enable" "0,1"
wgroup.long 0x4++0x3
line.long 0x0 "SWT,Software trigger register"
bitfld.long 0x0 17. "SWSTTR1,DAC_OUT1 sawtooth step-up/down software trigger" "0,1"
bitfld.long 0x0 16. "SWSTTR0,DAC_OUT0 sawtooth step-up/down software trigger" "0,1"
bitfld.long 0x0 1. "SWTR1,DAC_OUT1 software trigger cleared by hardware" "0,1"
bitfld.long 0x0 0. "SWTR0,DAC_OUT0 software trigger cleared by hardware" "0,1"
group.long 0x8++0x23
line.long 0x0 "OUT0_R12DH,DAC_OUT0 12-bit right-aligned data holding register"
hexmask.long.word 0x0 0.--11. 1. "OUT0_DH,DAC_OUT0 12-bit right-aligned data"
line.long 0x4 "OUT0_L12DH,DAC_OUT0 12-bit left-aligned data holding register"
hexmask.long.word 0x4 4.--15. 1. "OUT0_DH,DAC_OUT0 12-bit left-aligned data"
line.long 0x8 "OUT0_R8DH,DAC_OUT0 8-bit right-aligned data holding register"
hexmask.long.byte 0x8 0.--7. 1. "OUT0_DH,DAC_OUT0 8-bit right-aligned data"
line.long 0xC "OUT1_R12DH,DAC_OUT1 12-bit right-aligned data holding register"
hexmask.long.word 0xC 0.--11. 1. "OUT1_DH,DAC_OUT1 12-bit right-aligned data"
line.long 0x10 "OUT1_L12DH,DAC_OUT1 12-bit left-aligned data holding register"
hexmask.long.word 0x10 4.--15. 1. "OUT1_DH,DAC_OUT1 12-bit left-aligned data"
line.long 0x14 "OUT1_R8DH,DAC_OUT1 8-bit right-aligned data holding register"
hexmask.long.byte 0x14 0.--7. 1. "OUT1_DH,DAC_OUT1 8-bit right-aligned data"
line.long 0x18 "DACC_R12DH,DAC concurrent mode 12-bit right-aligned data holding register"
hexmask.long.word 0x18 16.--27. 1. "OUT1_DH,DAC_OUT1 12-bit right-aligned data"
hexmask.long.word 0x18 0.--11. 1. "OUT0_DH,DAC_OUT0 12-bit right-aligned data"
line.long 0x1C "DACC_L12DH,DAC concurrent mode 12-bit left-aligned data holding register"
hexmask.long.word 0x1C 20.--31. 1. "OUT1_DH,DAC_OUT1 12-bit left-aligned data"
hexmask.long.word 0x1C 4.--15. 1. "OUT0_DH,DAC_OUT0 12-bit left-aligned data"
line.long 0x20 "DACC_R8DH,DAC concurrent mode 8-bit right-aligned data holding register"
hexmask.long.byte 0x20 8.--15. 1. "OUT1_DH,DAC_OUT1 8-bit right-aligned data"
hexmask.long.byte 0x20 0.--7. 1. "OUT0_DH,DAC_OUT0 8-bit right-aligned data"
rgroup.long 0x2C++0x7
line.long 0x0 "OUT0_DO,DAC_OUT0 data output register"
hexmask.long.word 0x0 0.--11. 1. "OUT0_DO,DAC_OUT0 data output"
line.long 0x4 "OUT1_DO,DAC_OUT1 data output register"
hexmask.long.word 0x4 0.--11. 1. "OUT1_DO,DAC_OUT1 data output"
group.long 0x34++0x1B
line.long 0x0 "STAT0,DAC status register 0"
rbitfld.long 0x0 31. "BWT1,DAC_OUT1 TSAMP1[9:0] writing busy flag" "0,1"
rbitfld.long 0x0 30. "CALF1,DAC_OUT1 calibration offset flag" "0,1"
bitfld.long 0x0 29. "DDUDR1,DAC_OUT1 DMA underrun flag set by hardware cleared by software write 1" "0,1"
rbitfld.long 0x0 15. "BWT0,DAC_OUT0 TSAMP0[9:0] writing busy flag" "0,1"
rbitfld.long 0x0 14. "CALF0,DAC_OUT0 calibration offset flag" "0,1"
bitfld.long 0x0 13. "DDUDR0,DAC_OUT0 DMA underrun flag" "0,1"
line.long 0x4 "CALR,DAC calibration Register"
hexmask.long.byte 0x4 16.--20. 1. "OTV1,DAC_OUT1 offset calibration value"
hexmask.long.byte 0x4 0.--4. 1. "OTV0,DAC_OUT0 offset calibration value"
line.long 0x8 "MDCR,DAC mode control register"
bitfld.long 0x8 25. "DHFMT1,DAC_OUT1 data format written in data holding register" "0,1"
bitfld.long 0x8 16.--18. "MODE1,DAC_OUT1 mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 9. "DHFMT0,DAC_OUT0 data format written in data holding register" "0,1"
bitfld.long 0x8 0.--2. "MODE0,DAC_OUT0 mode" "0,1,2,3,4,5,6,7"
line.long 0xC "SKSTR0,DAC sample and keep sample time register 0"
hexmask.long.word 0xC 0.--9. 1. "TSAMP0,DAC_OUT0 sample time"
line.long 0x10 "SKSTR1,DAC sample and keep sample time register 1"
hexmask.long.word 0x10 0.--9. 1. "TSAMP1,DAC_OUT1 sample time"
line.long 0x14 "SKKTR,DAC sample and keep keep time register"
hexmask.long.word 0x14 16.--25. 1. "TKEEP1,DAC_OUT1 keep time (only available in sample and keep mode)"
hexmask.long.word 0x14 0.--9. 1. "TKEEP0,DAC_OUT0 keep time (only available in sample and keep mode)"
line.long 0x18 "SKRTR,DAC sample and keep refresh time register"
hexmask.long.byte 0x18 16.--23. 1. "TREF1,DAC_OUT1 refresh time (only available in sample and keep mode)"
hexmask.long.byte 0x18 0.--7. 1. "TREF0,DAC_OUT refresh time (only available in sample and keep mode)"
group.long 0x58++0xB
line.long 0x0 "OUT0_SAW,DAC_OUT0 sawtooth register"
hexmask.long.word 0x0 16.--31. 1. "SAWSTEP0,DAC_OUT0 sawtooth step value"
bitfld.long 0x0 12. "SAWDIR0,DAC_OUT0 sawtooth step direction" "0,1"
hexmask.long.word 0x0 0.--11. 1. "SAWINIT0,DAC_OUT0 sawtooth initial value"
line.long 0x4 "OUT1_SAW,DAC_OUT1 sawtooth register"
hexmask.long.word 0x4 16.--31. 1. "SAWSTEP1,DAC_OUT1 sawtooth step value"
bitfld.long 0x4 12. "SAWDIR1,DAC_OUT1 sawtooth step direction" "0,1"
hexmask.long.word 0x4 0.--11. 1. "SAWINIT1,DAC_OUT1 sawtooth initial value"
line.long 0x8 "SAWMDR,DAC sawtooth mode register"
bitfld.long 0x8 24.--25. "SAWSTEPTSEL1,DAC_OUT1 sawtooth step-up/down trigger selection" "0,1,2,3"
bitfld.long 0x8 16.--17. "SAWRSTTSEL1,DAC_OUT1 sawtooth reset to initial value trigger selection" "0,1,2,3"
bitfld.long 0x8 8.--9. "SAWSTEPTSEL0,DAC_OUT0 sawtooth step-up/down trigger selection" "0,1,2,3"
bitfld.long 0x8 0.--1. "SAWRSTTSEL0,DAC_OUT0 sawtooth reset to initial value trigger selection" "0,1,2,3"
tree.end
tree "DAC3"
base ad:0x50001C00
group.long 0x0++0x3
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 31. "DRSTMD1,DAC_OUT1 reset mode" "0,1"
bitfld.long 0x0 30. "CALEN1,DAC_OUT1 calibration enable" "0,1"
bitfld.long 0x0 29. "DDUDRIE1,DAC_OUT1 DMA underrun interrupt enable" "0,1"
bitfld.long 0x0 28. "DDMAEN1,DAC_OUT1 DMA enable" "0,1"
hexmask.long.byte 0x0 24.--27. 1. "DWBW1,DAC_OUT1 noise wave bit width"
bitfld.long 0x0 22.--23. "DWM1,DAC_OUT1 noise wave mode" "0,1,2,3"
bitfld.long 0x0 18.--19. "DTSEL1,DAC_OUT1 trigger selection" "0,1,2,3"
newline
bitfld.long 0x0 17. "DTEN1,DAC_OUT1 trigger enable" "0,1"
bitfld.long 0x0 16. "DEN1,DAC_OUT1 enable" "0,1"
bitfld.long 0x0 15. "DRSTMD0,DAC_OUT0 reset mode" "0,1"
bitfld.long 0x0 14. "CALEN0,DAC_OUT0 calibration enable" "0,1"
bitfld.long 0x0 13. "DDUDRIE0,DAC_OUT0 DMA underrun interrupt enable" "0,1"
bitfld.long 0x0 12. "DDMAEN0,DAC_OUT0 DMA enable" "0,1"
hexmask.long.byte 0x0 8.--11. 1. "DWBW0,DAC_OUT0 noise wave bit width"
newline
bitfld.long 0x0 6.--7. "DWM0,DAC_OUT0 noise wave mode" "0,1,2,3"
bitfld.long 0x0 2.--3. "DTSEL0,DAC_OUT0 trigger selection" "0,1,2,3"
bitfld.long 0x0 1. "DTEN0,DAC_OUT0 trigger enable" "0,1"
bitfld.long 0x0 0. "DEN0,DAC_OUT0 enable" "0,1"
wgroup.long 0x4++0x3
line.long 0x0 "SWT,Software trigger register"
bitfld.long 0x0 17. "SWSTTR1,DAC_OUT1 sawtooth step-up/down software trigger" "0,1"
bitfld.long 0x0 16. "SWSTTR0,DAC_OUT0 sawtooth step-up/down software trigger" "0,1"
bitfld.long 0x0 1. "SWTR1,DAC_OUT1 software trigger cleared by hardware" "0,1"
bitfld.long 0x0 0. "SWTR0,DAC_OUT0 software trigger cleared by hardware" "0,1"
group.long 0x8++0x23
line.long 0x0 "OUT0_R12DH,DAC_OUT0 12-bit right-aligned data holding register"
hexmask.long.word 0x0 0.--11. 1. "OUT0_DH,DAC_OUT0 12-bit right-aligned data"
line.long 0x4 "OUT0_L12DH,DAC_OUT0 12-bit left-aligned data holding register"
hexmask.long.word 0x4 4.--15. 1. "OUT0_DH,DAC_OUT0 12-bit left-aligned data"
line.long 0x8 "OUT0_R8DH,DAC_OUT0 8-bit right-aligned data holding register"
hexmask.long.byte 0x8 0.--7. 1. "OUT0_DH,DAC_OUT0 8-bit right-aligned data"
line.long 0xC "OUT1_R12DH,DAC_OUT1 12-bit right-aligned data holding register"
hexmask.long.word 0xC 0.--11. 1. "OUT1_DH,DAC_OUT1 12-bit right-aligned data"
line.long 0x10 "OUT1_L12DH,DAC_OUT1 12-bit left-aligned data holding register"
hexmask.long.word 0x10 4.--15. 1. "OUT1_DH,DAC_OUT1 12-bit left-aligned data"
line.long 0x14 "OUT1_R8DH,DAC_OUT1 8-bit right-aligned data holding register"
hexmask.long.byte 0x14 0.--7. 1. "OUT1_DH,DAC_OUT1 8-bit right-aligned data"
line.long 0x18 "DACC_R12DH,DAC concurrent mode 12-bit right-aligned data holding register"
hexmask.long.word 0x18 16.--27. 1. "OUT1_DH,DAC_OUT1 12-bit right-aligned data"
hexmask.long.word 0x18 0.--11. 1. "OUT0_DH,DAC_OUT0 12-bit right-aligned data"
line.long 0x1C "DACC_L12DH,DAC concurrent mode 12-bit left-aligned data holding register"
hexmask.long.word 0x1C 20.--31. 1. "OUT1_DH,DAC_OUT1 12-bit left-aligned data"
hexmask.long.word 0x1C 4.--15. 1. "OUT0_DH,DAC_OUT0 12-bit left-aligned data"
line.long 0x20 "DACC_R8DH,DAC concurrent mode 8-bit right-aligned data holding register"
hexmask.long.byte 0x20 8.--15. 1. "OUT1_DH,DAC_OUT1 8-bit right-aligned data"
hexmask.long.byte 0x20 0.--7. 1. "OUT0_DH,DAC_OUT0 8-bit right-aligned data"
rgroup.long 0x2C++0x7
line.long 0x0 "OUT0_DO,DAC_OUT0 data output register"
hexmask.long.word 0x0 0.--11. 1. "OUT0_DO,DAC_OUT0 data output"
line.long 0x4 "OUT1_DO,DAC_OUT1 data output register"
hexmask.long.word 0x4 0.--11. 1. "OUT1_DO,DAC_OUT1 data output"
group.long 0x34++0x1B
line.long 0x0 "STAT0,DAC status register 0"
rbitfld.long 0x0 31. "BWT1,DAC_OUT1 TSAMP1[9:0] writing busy flag" "0,1"
rbitfld.long 0x0 30. "CALF1,DAC_OUT1 calibration offset flag" "0,1"
bitfld.long 0x0 29. "DDUDR1,DAC_OUT1 DMA underrun flag set by hardware cleared by software write 1" "0,1"
rbitfld.long 0x0 15. "BWT0,DAC_OUT0 TSAMP0[9:0] writing busy flag" "0,1"
rbitfld.long 0x0 14. "CALF0,DAC_OUT0 calibration offset flag" "0,1"
bitfld.long 0x0 13. "DDUDR0,DAC_OUT0 DMA underrun flag" "0,1"
line.long 0x4 "CALR,DAC calibration Register"
hexmask.long.byte 0x4 16.--20. 1. "OTV1,DAC_OUT1 offset calibration value"
hexmask.long.byte 0x4 0.--4. 1. "OTV0,DAC_OUT0 offset calibration value"
line.long 0x8 "MDCR,DAC mode control register"
bitfld.long 0x8 25. "DHFMT1,DAC_OUT1 data format written in data holding register" "0,1"
bitfld.long 0x8 16.--18. "MODE1,DAC_OUT1 mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 9. "DHFMT0,DAC_OUT0 data format written in data holding register" "0,1"
bitfld.long 0x8 0.--2. "MODE0,DAC_OUT0 mode" "0,1,2,3,4,5,6,7"
line.long 0xC "SKSTR0,DAC sample and keep sample time register 0"
hexmask.long.word 0xC 0.--9. 1. "TSAMP0,DAC_OUT0 sample time"
line.long 0x10 "SKSTR1,DAC sample and keep sample time register 1"
hexmask.long.word 0x10 0.--9. 1. "TSAMP1,DAC_OUT1 sample time"
line.long 0x14 "SKKTR,DAC sample and keep keep time register"
hexmask.long.word 0x14 16.--25. 1. "TKEEP1,DAC_OUT1 keep time (only available in sample and keep mode)"
hexmask.long.word 0x14 0.--9. 1. "TKEEP0,DAC_OUT0 keep time (only available in sample and keep mode)"
line.long 0x18 "SKRTR,DAC sample and keep refresh time register"
hexmask.long.byte 0x18 16.--23. 1. "TREF1,DAC_OUT1 refresh time (only available in sample and keep mode)"
hexmask.long.byte 0x18 0.--7. 1. "TREF0,DAC_OUT refresh time (only available in sample and keep mode)"
group.long 0x58++0xB
line.long 0x0 "OUT0_SAW,DAC_OUT0 sawtooth register"
hexmask.long.word 0x0 16.--31. 1. "SAWSTEP0,DAC_OUT0 sawtooth step value"
bitfld.long 0x0 12. "SAWDIR0,DAC_OUT0 sawtooth step direction" "0,1"
hexmask.long.word 0x0 0.--11. 1. "SAWINIT0,DAC_OUT0 sawtooth initial value"
line.long 0x4 "OUT1_SAW,DAC_OUT1 sawtooth register"
hexmask.long.word 0x4 16.--31. 1. "SAWSTEP1,DAC_OUT1 sawtooth step value"
bitfld.long 0x4 12. "SAWDIR1,DAC_OUT1 sawtooth step direction" "0,1"
hexmask.long.word 0x4 0.--11. 1. "SAWINIT1,DAC_OUT1 sawtooth initial value"
line.long 0x8 "SAWMDR,DAC sawtooth mode register"
bitfld.long 0x8 24.--25. "SAWSTEPTSEL1,DAC_OUT1 sawtooth step-up/down trigger selection" "0,1,2,3"
bitfld.long 0x8 16.--17. "SAWRSTTSEL1,DAC_OUT1 sawtooth reset to initial value trigger selection" "0,1,2,3"
bitfld.long 0x8 8.--9. "SAWSTEPTSEL0,DAC_OUT0 sawtooth step-up/down trigger selection" "0,1,2,3"
bitfld.long 0x8 0.--1. "SAWRSTTSEL0,DAC_OUT0 sawtooth reset to initial value trigger selection" "0,1,2,3"
tree.end
tree.end
tree "DBG (Debug)"
base ad:0xE0044000
rgroup.long 0x0++0x3
line.long 0x0 "ID,ID code register"
hexmask.long 0x0 0.--31. 1. "ID_CODE,DBG ID code register"
group.long 0x4++0xB
line.long 0x0 "CTL0,Control register0"
bitfld.long 0x0 5. "TRACE_IOEN,Trace pin allocation enable" "0,1"
bitfld.long 0x0 2. "STB_HOLD,Standby mode hold bit" "0,1"
bitfld.long 0x0 1. "DSLP_HOLD,Deep-sleep mode hold bit" "0,1"
bitfld.long 0x0 0. "SLP_HOLD,Sleep mode hold bit" "0,1"
line.long 0x4 "CTL1,Control register1"
bitfld.long 0x4 31. "LPTIMER_HOLD,LPTIMER hold bit" "0,1"
bitfld.long 0x4 24. "I2C3_HOLD,I2C3 hold bit" "0,1"
bitfld.long 0x4 23. "I2C2_HOLD,I2C2 hold bit" "0,1"
bitfld.long 0x4 22. "I2C1_HOLD,I2C1 hold bit" "0,1"
bitfld.long 0x4 21. "I2C0_HOLD,I2C0 hold bit" "0,1"
bitfld.long 0x4 12. "FWDGT_HOLD,FWDGT hold bit" "0,1"
bitfld.long 0x4 11. "WWDGT_HOLD,WWDGT hold bit" "0,1"
bitfld.long 0x4 10. "RTC_HOLD,RTC hold bit" "0,1"
newline
bitfld.long 0x4 5. "TIMER6_HOLD,TIMER6 hold bit" "0,1"
bitfld.long 0x4 4. "TIMER5_HOLD,TIMER5 hold bit" "0,1"
bitfld.long 0x4 3. "TIMER4_HOLD,TIMER4 hold bit" "0,1"
bitfld.long 0x4 2. "TIMER3_HOLD,TIMER3 hold bit" "0,1"
bitfld.long 0x4 1. "TIMER2_HOLD,TIMER2 hold bit" "0,1"
bitfld.long 0x4 0. "TIMER1_HOLD,TIMER1 hold bit" "0,1"
line.long 0x8 "CTL2,Control register2"
bitfld.long 0x8 26. "HRTIMER_HOLD,HRTIMER hold bit" "0,1"
bitfld.long 0x8 20. "TIMER19_HOLD,TIMER19 hold bit" "0,1"
bitfld.long 0x8 18. "TIMER16_HOLD,TIMER16 hold bit" "0,1"
bitfld.long 0x8 17. "TIMER15_HOLD,TIMER15 hold bit" "0,1"
bitfld.long 0x8 16. "TIMER14_HOLD,TIMER14 hold bit" "0,1"
bitfld.long 0x8 13. "TIMER7_HOLD,TIMER7 hold bit" "0,1"
bitfld.long 0x8 11. "TIMER0_HOLD,TIMER0 hold bit" "0,1"
bitfld.long 0x8 2. "CAN2_HOLD,CAN2 hold bit" "0,1"
newline
bitfld.long 0x8 1. "CAN1_HOLD,CAN1 hold bit" "0,1"
bitfld.long 0x8 0. "CAN0_HOLD,CAN0 hold bit" "0,1"
tree.end
tree "DMA (Direct Memory Access)"
base ad:0x0
tree "DMA0"
base ad:0x40020000
rgroup.long 0x0++0x3
line.long 0x0 "INTF,Interrupt flag register"
bitfld.long 0x0 27. "ERRIF6,Error flag of channel 6" "0,1"
bitfld.long 0x0 26. "HTFIF6,Half transfer finish flag of channel 6" "0,1"
bitfld.long 0x0 25. "FTFIF6,Full Transfer finish flag of channel 6" "0,1"
bitfld.long 0x0 24. "GIF6,Global interrupt flag of channel 6" "0,1"
bitfld.long 0x0 23. "ERRIF5,Error flag of channel 5" "0,1"
bitfld.long 0x0 22. "HTFIF5,Half transfer finish flag of channel 5" "0,1"
bitfld.long 0x0 21. "FTFIF5,Full Transfer finish flag of channel 5" "0,1"
bitfld.long 0x0 20. "GIF5,Global interrupt flag of channel 5" "0,1"
bitfld.long 0x0 19. "ERRIF4,Error flag of channel 4" "0,1"
bitfld.long 0x0 18. "HTFIF4,Half transfer finish flag of channel 4" "0,1"
bitfld.long 0x0 17. "FTFIF4,Full Transfer finish flag of channel 4" "0,1"
newline
bitfld.long 0x0 16. "GIF4,Global interrupt flag of channel 4" "0,1"
bitfld.long 0x0 15. "ERRIF3,Error flag of channel 3" "0,1"
bitfld.long 0x0 14. "HTFIF3,Half transfer finish flag of channel 3" "0,1"
bitfld.long 0x0 13. "FTFIF3,Full Transfer finish flag of channel 3" "0,1"
bitfld.long 0x0 12. "GIF3,Global interrupt flag of channel 3" "0,1"
bitfld.long 0x0 11. "ERRIF2,Error flag of channel 2" "0,1"
bitfld.long 0x0 10. "HTFIF2,Half transfer finish flag of channel 2" "0,1"
bitfld.long 0x0 9. "FTFIF2,Full Transfer finish flag of channel 2" "0,1"
bitfld.long 0x0 8. "GIF2,Global interrupt flag of channel 2" "0,1"
bitfld.long 0x0 7. "ERRIF1,Error flag of channel 1" "0,1"
bitfld.long 0x0 6. "HTFIF1,Half transfer finish flag of channel 1" "0,1"
newline
bitfld.long 0x0 5. "FTFIF1,Full Transfer finish flag of channel 1" "0,1"
bitfld.long 0x0 4. "GIF1,Global interrupt flag of channel 1" "0,1"
bitfld.long 0x0 3. "ERRIF0,Error flag of channel 0" "0,1"
bitfld.long 0x0 2. "HTFIF0,Half transfer finish flag of channel 0" "0,1"
bitfld.long 0x0 1. "FTFIF0,Full Transfer finish flag of channel 0" "0,1"
bitfld.long 0x0 0. "GIF0,Global interrupt flag of channel 0" "0,1"
wgroup.long 0x4++0x3
line.long 0x0 "INTC,Interrupt flag clear register"
bitfld.long 0x0 27. "ERRIFC6,Clear bit for error flag of channel 6" "0,1"
bitfld.long 0x0 26. "HTFIFC6,Clear bit for half transfer finish flag of channel 6" "0,1"
bitfld.long 0x0 25. "FTFIFC6,Clear bit for full transfer finish flag of channel 6" "0,1"
bitfld.long 0x0 24. "GIFC6,Clear global interrupt flag of channel 6" "0,1"
bitfld.long 0x0 23. "ERRIFC5,Clear bit for error flag of channel 5" "0,1"
bitfld.long 0x0 22. "HTFIFC5,Clear bit for half transfer finish flag of channel 5" "0,1"
bitfld.long 0x0 21. "FTFIFC5,Clear bit for full transfer finish flag of channel 5" "0,1"
bitfld.long 0x0 20. "GIFC5,Clear global interrupt flag of channel 5" "0,1"
bitfld.long 0x0 19. "ERRIFC4,Clear bit for error flag of channel 4" "0,1"
bitfld.long 0x0 18. "HTFIFC4,Clear bit for half transfer finish flag of channel 4" "0,1"
bitfld.long 0x0 17. "FTFIFC4,Clear bit for full transfer finish flag of channel 4" "0,1"
newline
bitfld.long 0x0 16. "GIFC4,Clear global interrupt flag of channel 4" "0,1"
bitfld.long 0x0 15. "ERRIFC3,Clear bit for error flag of channel 3" "0,1"
bitfld.long 0x0 14. "HTFIFC3,Clear bit for half transfer finish flag of channel 3" "0,1"
bitfld.long 0x0 13. "FTFIFC3,Clear bit for full transfer finish flag of channel 3" "0,1"
bitfld.long 0x0 12. "GIFC3,Clear global interrupt flag of channel 3" "0,1"
bitfld.long 0x0 11. "ERRIFC2,Clear bit for error flag of channel 2" "0,1"
bitfld.long 0x0 10. "HTFIC2,Clear bit for half transfer finish flag of channel 2" "0,1"
bitfld.long 0x0 9. "FTFIFC2,Clear bit for full transfer finish flag of channel 2" "0,1"
bitfld.long 0x0 8. "GIFC2,Clear global interrupt flag of channel 2" "0,1"
bitfld.long 0x0 7. "ERRIFC1,Clear bit for error flag of channel 1" "0,1"
bitfld.long 0x0 6. "HTFIFC1,Clear bit for half transfer finish flag of channel 1" "0,1"
newline
bitfld.long 0x0 5. "FTFIFC1,Clear bit for full transfer finish flag of channel 1" "0,1"
bitfld.long 0x0 4. "GIFC1,Clear global interrupt flag of channel 1" "0,1"
bitfld.long 0x0 3. "ERRIFC0,Clear bit for error flag of channel 0" "0,1"
bitfld.long 0x0 2. "HTFIFC0,Clear bit for half transfer finish flag of channel 0" "0,1"
bitfld.long 0x0 1. "FTFIFC0,Clear bit for full transfer finish flag of channel 0" "0,1"
bitfld.long 0x0 0. "GIFC0,Clear global interrupt flag of channel 0" "0,1"
group.long 0x8++0xF
line.long 0x0 "CH0CTL,Channel 0 control register"
bitfld.long 0x0 14. "M2M,Memory to Memory mode" "0,1"
bitfld.long 0x0 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x0 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x0 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
bitfld.long 0x0 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x0 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x0 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x0 4. "DIR,Transfer direction" "0,1"
bitfld.long 0x0 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x0 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x0 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
newline
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
line.long 0x4 "CH0CNT,Channel 0 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,Transfer counter"
line.long 0x8 "CH0PADDR,Channel 0 peripheral base address register"
hexmask.long 0x8 0.--31. 1. "PADDR,Peripheral base address"
line.long 0xC "CH0MADDR,Channel 0 memory base address register"
hexmask.long 0xC 0.--31. 1. "MADDR,Memory base address"
group.long 0x1C++0xF
line.long 0x0 "CH1CTL,Channel 1 control register"
bitfld.long 0x0 14. "M2M,Memory to Memory mode" "0,1"
bitfld.long 0x0 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x0 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x0 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
bitfld.long 0x0 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x0 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x0 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x0 4. "DIR,Transfer direction" "0,1"
bitfld.long 0x0 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x0 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x0 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
newline
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
line.long 0x4 "CH1CNT,Channel 1 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,Transfer counter"
line.long 0x8 "CH1PADDR,Channel 1 peripheral base address register"
hexmask.long 0x8 0.--31. 1. "PADDR,Peripheral base address"
line.long 0xC "CH1MADDR,Channel 1 memory base address register"
hexmask.long 0xC 0.--31. 1. "MADDR,Memory base address"
group.long 0x30++0xF
line.long 0x0 "CH2CTL,Channel 2 control register"
bitfld.long 0x0 14. "M2M,Memory to Memory mode" "0,1"
bitfld.long 0x0 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x0 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x0 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
bitfld.long 0x0 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x0 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x0 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x0 4. "DIR,Transfer direction" "0,1"
bitfld.long 0x0 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x0 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x0 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
newline
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
line.long 0x4 "CH2CNT,Channel 2 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,Transfer counter"
line.long 0x8 "CH2PADDR,Channel 2 peripheral base address register"
hexmask.long 0x8 0.--31. 1. "PADDR,Peripheral base address"
line.long 0xC "CH2MADDR,Channel 2 memory base address register"
hexmask.long 0xC 0.--31. 1. "MADDR,Memory base address"
group.long 0x44++0xF
line.long 0x0 "CH3CTL,Channel 3 control register"
bitfld.long 0x0 14. "M2M,Memory to Memory mode" "0,1"
bitfld.long 0x0 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x0 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x0 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
bitfld.long 0x0 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x0 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x0 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x0 4. "DIR,Transfer direction" "0,1"
bitfld.long 0x0 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x0 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x0 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
newline
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
line.long 0x4 "CH3CNT,Channel 3 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,Transfer counter"
line.long 0x8 "CH3PADDR,Channel 3 peripheral base address register"
hexmask.long 0x8 0.--31. 1. "PADDR,Peripheral base address"
line.long 0xC "CH3MADDR,Channel 3 memory base address register"
hexmask.long 0xC 0.--31. 1. "MADDR,Memory base address"
group.long 0x58++0xF
line.long 0x0 "CH4CTL,Channel 4 control register"
bitfld.long 0x0 14. "M2M,Memory to Memory mode" "0,1"
bitfld.long 0x0 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x0 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x0 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
bitfld.long 0x0 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x0 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x0 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x0 4. "DIR,Transfer direction" "0,1"
bitfld.long 0x0 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x0 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x0 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
newline
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
line.long 0x4 "CH4CNT,Channel 4 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,Transfer counter"
line.long 0x8 "CH4PADDR,Channel 4 peripheral base address register"
hexmask.long 0x8 0.--31. 1. "PADDR,Peripheral base address"
line.long 0xC "CH4MADDR,Channel 4 memory base address register"
hexmask.long 0xC 0.--31. 1. "MADDR,Memory base address"
group.long 0x6C++0xF
line.long 0x0 "CH5CTL,Channel 5 control register"
bitfld.long 0x0 14. "M2M,Memory to Memory mode" "0,1"
bitfld.long 0x0 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x0 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x0 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
bitfld.long 0x0 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x0 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x0 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x0 4. "DIR,Transfer direction" "0,1"
bitfld.long 0x0 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x0 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x0 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
newline
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
line.long 0x4 "CH5CNT,Channel 5 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,Transfer counter"
line.long 0x8 "CH5PADDR,Channel 5 peripheral base address register"
hexmask.long 0x8 0.--31. 1. "PADDR,Peripheral base address"
line.long 0xC "CH5MADDR,Channel 5 memory base address register"
hexmask.long 0xC 0.--31. 1. "MADDR,Memory base address"
group.long 0x80++0xF
line.long 0x0 "CH6CTL,Channel 6 control register"
bitfld.long 0x0 14. "M2M,Memory to Memory mode" "0,1"
bitfld.long 0x0 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x0 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x0 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
bitfld.long 0x0 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x0 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x0 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x0 4. "DIR,Transfer direction" "0,1"
bitfld.long 0x0 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x0 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x0 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
newline
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
line.long 0x4 "CH6CNT,Channel 6 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,Transfer counter"
line.long 0x8 "CH6PADDR,Channel 6 peripheral base address register"
hexmask.long 0x8 0.--31. 1. "PADDR,Peripheral base address"
line.long 0xC "CH6MADDR,Channel 6 memory base address register"
hexmask.long 0xC 0.--31. 1. "MADDR,Memory base address"
tree.end
tree "DMA1"
base ad:0x40020400
rgroup.long 0x0++0x3
line.long 0x0 "INTF,Interrupt flag register"
bitfld.long 0x0 27. "ERRIF6,Error flag of channel 6" "0,1"
bitfld.long 0x0 26. "HTFIF6,Half transfer finish flag of channel 6" "0,1"
bitfld.long 0x0 25. "FTFIF6,Full Transfer finish flag of channel 6" "0,1"
bitfld.long 0x0 24. "GIF6,Global interrupt flag of channel 6" "0,1"
bitfld.long 0x0 23. "ERRIF5,Error flag of channel 5" "0,1"
bitfld.long 0x0 22. "HTFIF5,Half transfer finish flag of channel 5" "0,1"
bitfld.long 0x0 21. "FTFIF5,Full Transfer finish flag of channel 5" "0,1"
bitfld.long 0x0 20. "GIF5,Global interrupt flag of channel 5" "0,1"
bitfld.long 0x0 19. "ERRIF4,Error flag of channel 4" "0,1"
bitfld.long 0x0 18. "HTFIF4,Half transfer finish flag of channel 4" "0,1"
bitfld.long 0x0 17. "FTFIF4,Full Transfer finish flag of channel 4" "0,1"
newline
bitfld.long 0x0 16. "GIF4,Global interrupt flag of channel 4" "0,1"
bitfld.long 0x0 15. "ERRIF3,Error flag of channel 3" "0,1"
bitfld.long 0x0 14. "HTFIF3,Half transfer finish flag of channel 3" "0,1"
bitfld.long 0x0 13. "FTFIF3,Full Transfer finish flag of channel 3" "0,1"
bitfld.long 0x0 12. "GIF3,Global interrupt flag of channel 3" "0,1"
bitfld.long 0x0 11. "ERRIF2,Error flag of channel 2" "0,1"
bitfld.long 0x0 10. "HTFIF2,Half transfer finish flag of channel 2" "0,1"
bitfld.long 0x0 9. "FTFIF2,Full Transfer finish flag of channel 2" "0,1"
bitfld.long 0x0 8. "GIF2,Global interrupt flag of channel 2" "0,1"
bitfld.long 0x0 7. "ERRIF1,Error flag of channel 1" "0,1"
bitfld.long 0x0 6. "HTFIF1,Half transfer finish flag of channel 1" "0,1"
newline
bitfld.long 0x0 5. "FTFIF1,Full Transfer finish flag of channel 1" "0,1"
bitfld.long 0x0 4. "GIF1,Global interrupt flag of channel 1" "0,1"
bitfld.long 0x0 3. "ERRIF0,Error flag of channel 0" "0,1"
bitfld.long 0x0 2. "HTFIF0,Half transfer finish flag of channel 0" "0,1"
bitfld.long 0x0 1. "FTFIF0,Full Transfer finish flag of channel 0" "0,1"
bitfld.long 0x0 0. "GIF0,Global interrupt flag of channel 0" "0,1"
wgroup.long 0x4++0x3
line.long 0x0 "INTC,Interrupt flag clear register"
bitfld.long 0x0 27. "ERRIFC6,Clear bit for error flag of channel 6" "0,1"
bitfld.long 0x0 26. "HTFIFC6,Clear bit for half transfer finish flag of channel 6" "0,1"
bitfld.long 0x0 25. "FTFIFC6,Clear bit for full transfer finish flag of channel 6" "0,1"
bitfld.long 0x0 24. "GIFC6,Clear global interrupt flag of channel 6" "0,1"
bitfld.long 0x0 23. "ERRIFC5,Clear bit for error flag of channel 5" "0,1"
bitfld.long 0x0 22. "HTFIFC5,Clear bit for half transfer finish flag of channel 5" "0,1"
bitfld.long 0x0 21. "FTFIFC5,Clear bit for full transfer finish flag of channel 5" "0,1"
bitfld.long 0x0 20. "GIFC5,Clear global interrupt flag of channel 5" "0,1"
bitfld.long 0x0 19. "ERRIFC4,Clear bit for error flag of channel 4" "0,1"
bitfld.long 0x0 18. "HTFIFC4,Clear bit for half transfer finish flag of channel 4" "0,1"
bitfld.long 0x0 17. "FTFIFC4,Clear bit for full transfer finish flag of channel 4" "0,1"
newline
bitfld.long 0x0 16. "GIFC4,Clear global interrupt flag of channel 4" "0,1"
bitfld.long 0x0 15. "ERRIFC3,Clear bit for error flag of channel 3" "0,1"
bitfld.long 0x0 14. "HTFIFC3,Clear bit for half transfer finish flag of channel 3" "0,1"
bitfld.long 0x0 13. "FTFIFC3,Clear bit for full transfer finish flag of channel 3" "0,1"
bitfld.long 0x0 12. "GIFC3,Clear global interrupt flag of channel 3" "0,1"
bitfld.long 0x0 11. "ERRIFC2,Clear bit for error flag of channel 2" "0,1"
bitfld.long 0x0 10. "HTFIC2,Clear bit for half transfer finish flag of channel 2" "0,1"
bitfld.long 0x0 9. "FTFIFC2,Clear bit for full transfer finish flag of channel 2" "0,1"
bitfld.long 0x0 8. "GIFC2,Clear global interrupt flag of channel 2" "0,1"
bitfld.long 0x0 7. "ERRIFC1,Clear bit for error flag of channel 1" "0,1"
bitfld.long 0x0 6. "HTFIFC1,Clear bit for half transfer finish flag of channel 1" "0,1"
newline
bitfld.long 0x0 5. "FTFIFC1,Clear bit for full transfer finish flag of channel 1" "0,1"
bitfld.long 0x0 4. "GIFC1,Clear global interrupt flag of channel 1" "0,1"
bitfld.long 0x0 3. "ERRIFC0,Clear bit for error flag of channel 0" "0,1"
bitfld.long 0x0 2. "HTFIFC0,Clear bit for half transfer finish flag of channel 0" "0,1"
bitfld.long 0x0 1. "FTFIFC0,Clear bit for full transfer finish flag of channel 0" "0,1"
bitfld.long 0x0 0. "GIFC0,Clear global interrupt flag of channel 0" "0,1"
group.long 0x8++0xF
line.long 0x0 "CH0CTL,Channel 0 control register"
bitfld.long 0x0 14. "M2M,Memory to Memory mode" "0,1"
bitfld.long 0x0 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x0 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x0 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
bitfld.long 0x0 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x0 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x0 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x0 4. "DIR,Transfer direction" "0,1"
bitfld.long 0x0 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x0 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x0 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
newline
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
line.long 0x4 "CH0CNT,Channel 0 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,Transfer counter"
line.long 0x8 "CH0PADDR,Channel 0 peripheral base address register"
hexmask.long 0x8 0.--31. 1. "PADDR,Peripheral base address"
line.long 0xC "CH0MADDR,Channel 0 memory base address register"
hexmask.long 0xC 0.--31. 1. "MADDR,Memory base address"
group.long 0x1C++0xF
line.long 0x0 "CH1CTL,Channel 1 control register"
bitfld.long 0x0 14. "M2M,Memory to Memory mode" "0,1"
bitfld.long 0x0 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x0 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x0 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
bitfld.long 0x0 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x0 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x0 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x0 4. "DIR,Transfer direction" "0,1"
bitfld.long 0x0 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x0 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x0 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
newline
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
line.long 0x4 "CH1CNT,Channel 1 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,Transfer counter"
line.long 0x8 "CH1PADDR,Channel 1 peripheral base address register"
hexmask.long 0x8 0.--31. 1. "PADDR,Peripheral base address"
line.long 0xC "CH1MADDR,Channel 1 memory base address register"
hexmask.long 0xC 0.--31. 1. "MADDR,Memory base address"
group.long 0x30++0xF
line.long 0x0 "CH2CTL,Channel 2 control register"
bitfld.long 0x0 14. "M2M,Memory to Memory mode" "0,1"
bitfld.long 0x0 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x0 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x0 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
bitfld.long 0x0 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x0 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x0 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x0 4. "DIR,Transfer direction" "0,1"
bitfld.long 0x0 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x0 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x0 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
newline
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
line.long 0x4 "CH2CNT,Channel 2 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,Transfer counter"
line.long 0x8 "CH2PADDR,Channel 2 peripheral base address register"
hexmask.long 0x8 0.--31. 1. "PADDR,Peripheral base address"
line.long 0xC "CH2MADDR,Channel 2 memory base address register"
hexmask.long 0xC 0.--31. 1. "MADDR,Memory base address"
group.long 0x44++0xF
line.long 0x0 "CH3CTL,Channel 3 control register"
bitfld.long 0x0 14. "M2M,Memory to Memory mode" "0,1"
bitfld.long 0x0 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x0 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x0 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
bitfld.long 0x0 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x0 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x0 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x0 4. "DIR,Transfer direction" "0,1"
bitfld.long 0x0 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x0 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x0 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
newline
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
line.long 0x4 "CH3CNT,Channel 3 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,Transfer counter"
line.long 0x8 "CH3PADDR,Channel 3 peripheral base address register"
hexmask.long 0x8 0.--31. 1. "PADDR,Peripheral base address"
line.long 0xC "CH3MADDR,Channel 3 memory base address register"
hexmask.long 0xC 0.--31. 1. "MADDR,Memory base address"
group.long 0x58++0xF
line.long 0x0 "CH4CTL,Channel 4 control register"
bitfld.long 0x0 14. "M2M,Memory to Memory mode" "0,1"
bitfld.long 0x0 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x0 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x0 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
bitfld.long 0x0 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x0 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x0 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x0 4. "DIR,Transfer direction" "0,1"
bitfld.long 0x0 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x0 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x0 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
newline
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
line.long 0x4 "CH4CNT,Channel 4 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,Transfer counter"
line.long 0x8 "CH4PADDR,Channel 4 peripheral base address register"
hexmask.long 0x8 0.--31. 1. "PADDR,Peripheral base address"
line.long 0xC "CH4MADDR,Channel 4 memory base address register"
hexmask.long 0xC 0.--31. 1. "MADDR,Memory base address"
group.long 0x6C++0xF
line.long 0x0 "CH5CTL,Channel 5 control register"
bitfld.long 0x0 14. "M2M,Memory to Memory mode" "0,1"
bitfld.long 0x0 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x0 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x0 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
bitfld.long 0x0 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x0 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x0 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x0 4. "DIR,Transfer direction" "0,1"
bitfld.long 0x0 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x0 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x0 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
newline
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
line.long 0x4 "CH5CNT,Channel 5 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,Transfer counter"
line.long 0x8 "CH5PADDR,Channel 5 peripheral base address register"
hexmask.long 0x8 0.--31. 1. "PADDR,Peripheral base address"
line.long 0xC "CH5MADDR,Channel 5 memory base address register"
hexmask.long 0xC 0.--31. 1. "MADDR,Memory base address"
group.long 0x80++0xF
line.long 0x0 "CH6CTL,Channel 6 control register"
bitfld.long 0x0 14. "M2M,Memory to Memory mode" "0,1"
bitfld.long 0x0 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x0 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x0 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
bitfld.long 0x0 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x0 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x0 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x0 4. "DIR,Transfer direction" "0,1"
bitfld.long 0x0 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x0 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x0 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
newline
bitfld.long 0x0 0. "CHEN,Channel enable" "0,1"
line.long 0x4 "CH6CNT,Channel 6 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,Transfer counter"
line.long 0x8 "CH6PADDR,Channel 6 peripheral base address register"
hexmask.long 0x8 0.--31. 1. "PADDR,Peripheral base address"
line.long 0xC "CH6MADDR,Channel 6 memory base address register"
hexmask.long 0xC 0.--31. 1. "MADDR,Memory base address"
tree.end
tree.end
tree "DMAMUX (DMA Request Multiplexer)"
base ad:0x40020800
group.long 0x0++0x37
line.long 0x0 "RM_CH0CFG,Request multiplexer channel 0 configuration register"
hexmask.long.byte 0x0 24.--28. 1. "SYNCID,Synchronization input identification"
hexmask.long.byte 0x0 19.--23. 1. "NBR,Number of DMA requests to forward"
bitfld.long 0x0 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
bitfld.long 0x0 16. "SYNCEN,Synchronization enable" "0,1"
bitfld.long 0x0 9. "EVGEN,Event generation enable" "0,1"
bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "MUXID,Multiplexer input identification"
line.long 0x4 "RM_CH1CFG,Request multiplexer channel 1 configuration register"
hexmask.long.byte 0x4 24.--28. 1. "SYNCID,Synchronization input identification"
hexmask.long.byte 0x4 19.--23. 1. "NBR,Number of DMA requests to forward"
bitfld.long 0x4 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
bitfld.long 0x4 16. "SYNCEN,Synchronization enable" "0,1"
bitfld.long 0x4 9. "EVGEN,Event generation enable" "0,1"
bitfld.long 0x4 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
hexmask.long.byte 0x4 0.--7. 1. "MUXID,Multiplexer input identification"
line.long 0x8 "RM_CH2CFG,Request multiplexer channel 2 configuration register"
hexmask.long.byte 0x8 24.--28. 1. "SYNCID,Synchronization input identification"
hexmask.long.byte 0x8 19.--23. 1. "NBR,Number of DMA requests to forward"
bitfld.long 0x8 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
bitfld.long 0x8 16. "SYNCEN,Synchronization enable" "0,1"
bitfld.long 0x8 9. "EVGEN,Event generation enable" "0,1"
bitfld.long 0x8 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
hexmask.long.byte 0x8 0.--7. 1. "MUXID,Multiplexer input identification"
line.long 0xC "RM_CH3CFG,Request multiplexer channel 3 configuration register"
hexmask.long.byte 0xC 24.--28. 1. "SYNCID,Synchronization input identification"
hexmask.long.byte 0xC 19.--23. 1. "NBR,Number of DMA requests to forward"
bitfld.long 0xC 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
bitfld.long 0xC 16. "SYNCEN,Synchronization enable" "0,1"
bitfld.long 0xC 9. "EVGEN,Event generation enable" "0,1"
bitfld.long 0xC 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
hexmask.long.byte 0xC 0.--7. 1. "MUXID,Multiplexer input identification"
line.long 0x10 "RM_CH4CFG,Request multiplexer channel 4 configuration register"
hexmask.long.byte 0x10 24.--28. 1. "SYNCID,Synchronization input identification"
hexmask.long.byte 0x10 19.--23. 1. "NBR,Number of DMA requests to forward"
bitfld.long 0x10 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
bitfld.long 0x10 16. "SYNCEN,Synchronization enable" "0,1"
bitfld.long 0x10 9. "EVGEN,Event generation enable" "0,1"
bitfld.long 0x10 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "MUXID,Multiplexer input identification"
line.long 0x14 "RM_CH5CFG,Request multiplexer channel 5 configuration register"
hexmask.long.byte 0x14 24.--28. 1. "SYNCID,Synchronization input identification"
hexmask.long.byte 0x14 19.--23. 1. "NBR,Number of DMA requests to forward"
bitfld.long 0x14 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
bitfld.long 0x14 16. "SYNCEN,Synchronization enable" "0,1"
bitfld.long 0x14 9. "EVGEN,Event generation enable" "0,1"
bitfld.long 0x14 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "MUXID,Multiplexer input identification"
line.long 0x18 "RM_CH6CFG,Request multiplexer channel 6 configuration register"
hexmask.long.byte 0x18 24.--28. 1. "SYNCID,Synchronization input identification"
hexmask.long.byte 0x18 19.--23. 1. "NBR,Number of DMA requests to forward"
bitfld.long 0x18 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
bitfld.long 0x18 16. "SYNCEN,Synchronization enable" "0,1"
bitfld.long 0x18 9. "EVGEN,Event generation enable" "0,1"
bitfld.long 0x18 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
hexmask.long.byte 0x18 0.--7. 1. "MUXID,Multiplexer input identification"
line.long 0x1C "RM_CH7CFG,Request multiplexer channel 7 configuration register"
hexmask.long.byte 0x1C 24.--28. 1. "SYNCID,Synchronization input identification"
hexmask.long.byte 0x1C 19.--23. 1. "NBR,Number of DMA requests to forward"
bitfld.long 0x1C 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
bitfld.long 0x1C 16. "SYNCEN,Synchronization enable" "0,1"
bitfld.long 0x1C 9. "EVGEN,Event generation enable" "0,1"
bitfld.long 0x1C 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
hexmask.long.byte 0x1C 0.--7. 1. "MUXID,Multiplexer input identification"
line.long 0x20 "RM_CH8CFG,Request multiplexer channel 8 configuration register"
hexmask.long.byte 0x20 24.--28. 1. "SYNCID,Synchronization input identification"
hexmask.long.byte 0x20 19.--23. 1. "NBR,Number of DMA requests to forward"
bitfld.long 0x20 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
bitfld.long 0x20 16. "SYNCEN,Synchronization enable" "0,1"
bitfld.long 0x20 9. "EVGEN,Event generation enable" "0,1"
bitfld.long 0x20 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
hexmask.long.byte 0x20 0.--7. 1. "MUXID,Multiplexer input identification"
line.long 0x24 "RM_CH9CFG,Request multiplexer channel 9 configuration register"
hexmask.long.byte 0x24 24.--28. 1. "SYNCID,Synchronization input identification"
hexmask.long.byte 0x24 19.--23. 1. "NBR,Number of DMA requests to forward"
bitfld.long 0x24 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
bitfld.long 0x24 16. "SYNCEN,Synchronization enable" "0,1"
bitfld.long 0x24 9. "EVGEN,Event generation enable" "0,1"
bitfld.long 0x24 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
hexmask.long.byte 0x24 0.--7. 1. "MUXID,Multiplexer input identification"
line.long 0x28 "RM_CH10CFG,Request multiplexer channel 10 configuration register"
hexmask.long.byte 0x28 24.--28. 1. "SYNCID,Synchronization input identification"
hexmask.long.byte 0x28 19.--23. 1. "NBR,Number of DMA requests to forward"
bitfld.long 0x28 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
bitfld.long 0x28 16. "SYNCEN,Synchronization enable" "0,1"
bitfld.long 0x28 9. "EVGEN,Event generation enable" "0,1"
bitfld.long 0x28 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
hexmask.long.byte 0x28 0.--7. 1. "MUXID,Multiplexer input identification"
line.long 0x2C "RM_CH11CFG,Request multiplexer channel 11 configuration register"
hexmask.long.byte 0x2C 24.--28. 1. "SYNCID,Synchronization input identification"
hexmask.long.byte 0x2C 19.--23. 1. "NBR,Number of DMA requests to forward"
bitfld.long 0x2C 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
bitfld.long 0x2C 16. "SYNCEN,Synchronization enable" "0,1"
bitfld.long 0x2C 9. "EVGEN,Event generation enable" "0,1"
bitfld.long 0x2C 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
hexmask.long.byte 0x2C 0.--7. 1. "MUXID,Multiplexer input identification"
line.long 0x30 "RM_CH12CFG,Request multiplexer channel 12 configuration register"
hexmask.long.byte 0x30 24.--28. 1. "SYNCID,Synchronization input identification"
hexmask.long.byte 0x30 19.--23. 1. "NBR,Number of DMA requests to forward"
bitfld.long 0x30 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
bitfld.long 0x30 16. "SYNCEN,Synchronization enable" "0,1"
bitfld.long 0x30 9. "EVGEN,Event generation enable" "0,1"
bitfld.long 0x30 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
hexmask.long.byte 0x30 0.--7. 1. "MUXID,Multiplexer input identification"
line.long 0x34 "RM_CH13CFG,Request multiplexer channel 13 configuration register"
hexmask.long.byte 0x34 24.--28. 1. "SYNCID,Synchronization input identification"
hexmask.long.byte 0x34 19.--23. 1. "NBR,Number of DMA requests to forward"
bitfld.long 0x34 17.--18. "SYNCP,Synchronization input polarity" "0,1,2,3"
bitfld.long 0x34 16. "SYNCEN,Synchronization enable" "0,1"
bitfld.long 0x34 9. "EVGEN,Event generation enable" "0,1"
bitfld.long 0x34 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
hexmask.long.byte 0x34 0.--7. 1. "MUXID,Multiplexer input identification"
rgroup.long 0x80++0x3
line.long 0x0 "RM_INTF,Request multiplexer channel interrupt flag register"
bitfld.long 0x0 13. "SOIF13,Synchronization overrun event flag of request multiplexer channel 13" "0,1"
bitfld.long 0x0 12. "SOIF12,Synchronization overrun event flag of request multiplexer channel 12" "0,1"
bitfld.long 0x0 11. "SOIF11,Synchronization overrun event flag of request multiplexer channel 11" "0,1"
bitfld.long 0x0 10. "SOIF10,Synchronization overrun event flag of request multiplexer channel 10" "0,1"
bitfld.long 0x0 9. "SOIF9,Synchronization overrun event flag of request multiplexer channel 9" "0,1"
bitfld.long 0x0 8. "SOIF8,Synchronization overrun event flag of request multiplexer channel 8" "0,1"
bitfld.long 0x0 7. "SOIF7,Synchronization overrun event flag of request multiplexer channel 7" "0,1"
bitfld.long 0x0 6. "SOIF6,Synchronization overrun event flag of request multiplexer channel 6" "0,1"
bitfld.long 0x0 5. "SOIF5,Synchronization overrun event flag of request multiplexer channel 5" "0,1"
bitfld.long 0x0 4. "SOIF4,Synchronization overrun event flag of request multiplexer channel 4" "0,1"
bitfld.long 0x0 3. "SOIF3,Synchronization overrun event flag of request multiplexer channel 3" "0,1"
newline
bitfld.long 0x0 2. "SOIF2,Synchronization overrun event flag of request multiplexer channel 2" "0,1"
bitfld.long 0x0 1. "SOIF1,Synchronization overrun event flag of request multiplexer channel 1" "0,1"
bitfld.long 0x0 0. "SOIF0,Synchronization overrun event flag of request multiplexer channel 0" "0,1"
wgroup.long 0x84++0x3
line.long 0x0 "RM_INTC,Request multiplexer channel interrupt flag clear register"
bitfld.long 0x0 13. "SOIFC13,Clear bit for synchronization overrun event flag of request multiplexer channel 13" "0,1"
bitfld.long 0x0 12. "SOIFC12,Clear bit for synchronization overrun event flag of request multiplexer channel 12" "0,1"
bitfld.long 0x0 11. "SOIFC11,Clear bit for synchronization overrun event flag of request multiplexer channel 11" "0,1"
bitfld.long 0x0 10. "SOIFC10,Clear bit for synchronization overrun event flag of request multiplexer channel 10" "0,1"
bitfld.long 0x0 9. "SOIFC9,Clear bit for synchronization overrun event flag of request multiplexer channel 9" "0,1"
bitfld.long 0x0 8. "SOIFC8,Clear bit for synchronization overrun event flag of request multiplexer channel 8" "0,1"
bitfld.long 0x0 7. "SOIFC7,Clear bit for synchronization overrun event flag of request multiplexer channel 7" "0,1"
bitfld.long 0x0 6. "SOIFC6,Clear bit for synchronization overrun event flag of request multiplexer channel 6" "0,1"
bitfld.long 0x0 5. "SOIFC5,Clear bit for synchronization overrun event flag of request multiplexer channel 5" "0,1"
bitfld.long 0x0 4. "SOIFC4,Clear bit for synchronization overrun event flag of request multiplexer channel 4" "0,1"
bitfld.long 0x0 3. "SOIFC3,Clear bit for synchronization overrun event flag of request multiplexer channel 3" "0,1"
newline
bitfld.long 0x0 2. "SOIFC2,Clear bit for synchronization overrun event flag of request multiplexer channel 2" "0,1"
bitfld.long 0x0 1. "SOIFC1,Clear bit for synchronization overrun event flag of request multiplexer channel 1" "0,1"
bitfld.long 0x0 0. "SOIFC0,Clear bit for synchronization overrun event flag of request multiplexer channel 0" "0,1"
group.long 0x100++0xF
line.long 0x0 "RG_CH0CFG,Request generator channel 0 configuration register"
hexmask.long.byte 0x0 19.--23. 1. "NBRG,Number of DMA requests to be generated"
bitfld.long 0x0 17.--18. "RGTP,DMA request generator trigger polarity" "0,1,2,3"
bitfld.long 0x0 16. "RGEN,DMA request generator channel x enable" "0,1"
bitfld.long 0x0 8. "TOIE,Trigger overrun interrupt enable" "0,1"
hexmask.long.byte 0x0 0.--4. 1. "TID,Trigger input identification"
line.long 0x4 "RG_CH1CFG,Request generator channel 1 configuration register"
hexmask.long.byte 0x4 19.--23. 1. "NBRG,Number of DMA requests to be generated"
bitfld.long 0x4 17.--18. "RGTP,DMA request generator trigger polarity" "0,1,2,3"
bitfld.long 0x4 16. "RGEN,DMA request generator channel x enable" "0,1"
bitfld.long 0x4 8. "TOIE,Trigger overrun interrupt enable" "0,1"
hexmask.long.byte 0x4 0.--4. 1. "TID,Trigger input identification"
line.long 0x8 "RG_CH2CFG,Request generator channel 2 configuration register"
hexmask.long.byte 0x8 19.--23. 1. "NBRG,Number of DMA requests to be generated"
bitfld.long 0x8 17.--18. "RGTP,DMA request generator trigger polarity" "0,1,2,3"
bitfld.long 0x8 16. "RGEN,DMA request generator channel x enable" "0,1"
bitfld.long 0x8 8. "TOIE,Trigger overrun interrupt enable" "0,1"
hexmask.long.byte 0x8 0.--4. 1. "TID,Trigger input identification"
line.long 0xC "RG_CH3CFG,Request generator channel 3 configuration register"
hexmask.long.byte 0xC 19.--23. 1. "NBRG,Number of DMA requests to be generated"
bitfld.long 0xC 17.--18. "RGTP,DMA request generator trigger polarity" "0,1,2,3"
bitfld.long 0xC 16. "RGEN,DMA request generator channel x enable" "0,1"
bitfld.long 0xC 8. "TOIE,Trigger overrun interrupt enable" "0,1"
hexmask.long.byte 0xC 0.--4. 1. "TID,Trigger input identification"
rgroup.long 0x140++0x3
line.long 0x0 "RG_INTF,Request generator interrupt flag register"
bitfld.long 0x0 3. "TOIF3,Trigger overrun event flag of request generator channel 3" "0,1"
bitfld.long 0x0 2. "TOIF2,Trigger overrun event flag of request generator channel 2" "0,1"
bitfld.long 0x0 1. "TOIF1,Trigger overrun event flag of request generator channel 1" "0,1"
bitfld.long 0x0 0. "TOIF0,Trigger overrun event flag of request generator channel 0" "0,1"
wgroup.long 0x144++0x3
line.long 0x0 "RG_INTC,Request generator interrupt flag clear register"
bitfld.long 0x0 3. "TOIFC3,Clear bit for trigger overrun event flag of request generator channel 3" "0,1"
bitfld.long 0x0 2. "TOIFC2,Clear bit for trigger overrun event flag of request generator channel 2" "0,1"
bitfld.long 0x0 1. "TOIFC1,Clear bit for trigger overrun event flag of request generator channel 1" "0,1"
bitfld.long 0x0 0. "TOIFC0,Clear bit for trigger overrun event flag of request generator channel 0" "0,1"
tree.end
tree "EXMC (External Memory Controller)"
base ad:0xA0000000
group.long 0x0++0x3
line.long 0x0 "SNCTL0,SRAM/NOR Flash control registe 0"
bitfld.long 0x0 22.--23. "BLSET,NBL(Byte lane) setup time" "0,1,2,3"
bitfld.long 0x0 21. "WFIFODIS,Write FIFO disabled" "0,1"
bitfld.long 0x0 20. "CCK,Consecutive Clock" "0,1"
bitfld.long 0x0 19. "SYNCWR,Synchronous write" "0,1"
bitfld.long 0x0 16.--18. "CPS,CRAM page size" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "ASYNCWAIT,Asynchronous wait" "0,1"
bitfld.long 0x0 14. "EXMODEN,Extended mode enable" "0,1"
bitfld.long 0x0 13. "NRWTEN,NWAIT signal enable" "0,1"
bitfld.long 0x0 12. "WEN,Write enable" "0,1"
newline
bitfld.long 0x0 11. "NRWTCFG,NWAIT signal configuration only work in synchronous mode" "0,1"
bitfld.long 0x0 10. "WRAPEN,Wrapped burst mode enable" "0,1"
bitfld.long 0x0 9. "NRWTPOL,NWAIT signal polarity" "0,1"
bitfld.long 0x0 8. "SBRSTEN,Synchronous burst enable" "0,1"
bitfld.long 0x0 6. "NREN,NOR Flash access enable" "0,1"
bitfld.long 0x0 4.--5. "NRW,NOR region memory data bus width" "0,1,2,3"
bitfld.long 0x0 2.--3. "NRTP,NOR region memory type" "0,1,2,3"
bitfld.long 0x0 1. "NRMUX,NOR region memory address/data multiplexing" "0,1"
bitfld.long 0x0 0. "NRBKEN,NOR region enable" "0,1"
group.long 0x8++0x3
line.long 0x0 "SNCTL1,SRAM/NOR Flash control registe 1"
bitfld.long 0x0 22.--23. "BLSET,NBL(Byte lane) setup time" "0,1,2,3"
bitfld.long 0x0 21. "WFIFODIS,Write FIFO disabled" "0,1"
bitfld.long 0x0 20. "CCK,Consecutive Clock" "0,1"
bitfld.long 0x0 19. "SYNCWR,Synchronous write" "0,1"
bitfld.long 0x0 16.--18. "CPS,CRAM page size" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "ASYNCWAIT,Asynchronous wait" "0,1"
bitfld.long 0x0 14. "EXMODEN,Extended mode enable" "0,1"
bitfld.long 0x0 13. "NRWTEN,NWAIT signal enable" "0,1"
bitfld.long 0x0 12. "WEN,Write enable" "0,1"
newline
bitfld.long 0x0 11. "NRWTCFG,NWAIT signal configuration only work in synchronous mode" "0,1"
bitfld.long 0x0 10. "WRAPEN,Wrapped burst mode enable" "0,1"
bitfld.long 0x0 9. "NRWTPOL,NWAIT signal polarity" "0,1"
bitfld.long 0x0 8. "SBRSTEN,Synchronous burst enable" "0,1"
bitfld.long 0x0 6. "NREN,NOR Flash access enable" "0,1"
bitfld.long 0x0 4.--5. "NRW,NOR region memory data bus width" "0,1,2,3"
bitfld.long 0x0 2.--3. "NRTP,NOR region memory type" "0,1,2,3"
bitfld.long 0x0 1. "NRMUX,NOR region memory address/data multiplexing" "0,1"
bitfld.long 0x0 0. "NRBKEN,NOR region enable" "0,1"
group.long 0x10++0x3
line.long 0x0 "SNCTL2,SRAM/NOR Flash control registe 2"
bitfld.long 0x0 22.--23. "BLSET,NBL(Byte lane) setup time" "0,1,2,3"
bitfld.long 0x0 21. "WFIFODIS,Write FIFO disabled" "0,1"
bitfld.long 0x0 20. "CCK,Consecutive Clock" "0,1"
bitfld.long 0x0 19. "SYNCWR,Synchronous write" "0,1"
bitfld.long 0x0 16.--18. "CPS,CRAM page size" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "ASYNCWAIT,Asynchronous wait" "0,1"
bitfld.long 0x0 14. "EXMODEN,Extended mode enable" "0,1"
bitfld.long 0x0 13. "NRWTEN,NWAIT signal enable" "0,1"
bitfld.long 0x0 12. "WEN,Write enable" "0,1"
newline
bitfld.long 0x0 11. "NRWTCFG,NWAIT signal configuration only work in synchronous mode" "0,1"
bitfld.long 0x0 10. "WRAPEN,Wrapped burst mode enable" "0,1"
bitfld.long 0x0 9. "NRWTPOL,NWAIT signal polarity" "0,1"
bitfld.long 0x0 8. "SBRSTEN,Synchronous burst enable" "0,1"
bitfld.long 0x0 6. "NREN,NOR Flash access enable" "0,1"
bitfld.long 0x0 4.--5. "NRW,NOR region memory data bus width" "0,1,2,3"
bitfld.long 0x0 2.--3. "NRTP,NOR region memory type" "0,1,2,3"
bitfld.long 0x0 1. "NRMUX,NOR region memory address/data multiplexing" "0,1"
bitfld.long 0x0 0. "NRBKEN,NOR region enable" "0,1"
group.long 0x18++0x3
line.long 0x0 "SNCTL3,SRAM/NOR Flash control registe 3"
bitfld.long 0x0 22.--23. "BLSET,NBL(Byte lane) setup time" "0,1,2,3"
bitfld.long 0x0 21. "WFIFODIS,Write FIFO disabled" "0,1"
bitfld.long 0x0 20. "CCK,Consecutive Clock" "0,1"
bitfld.long 0x0 19. "SYNCWR,Synchronous write" "0,1"
bitfld.long 0x0 16.--18. "CPS,CRAM page size" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "ASYNCWAIT,Asynchronous wait" "0,1"
bitfld.long 0x0 14. "EXMODEN,Extended mode enable" "0,1"
bitfld.long 0x0 13. "NRWTEN,NWAIT signal enable" "0,1"
bitfld.long 0x0 12. "WEN,Write enable" "0,1"
newline
bitfld.long 0x0 11. "NRWTCFG,NWAIT signal configuration only work in synchronous mode" "0,1"
bitfld.long 0x0 10. "WRAPEN,Wrapped burst mode enable" "0,1"
bitfld.long 0x0 9. "NRWTPOL,NWAIT signal polarity" "0,1"
bitfld.long 0x0 8. "SBRSTEN,Synchronous burst enable" "0,1"
bitfld.long 0x0 6. "NREN,NOR Flash access enable" "0,1"
bitfld.long 0x0 4.--5. "NRW,NOR region memory data bus width" "0,1,2,3"
bitfld.long 0x0 2.--3. "NRTP,NOR region memory type" "0,1,2,3"
bitfld.long 0x0 1. "NRMUX,NOR region memory address/data multiplexing" "0,1"
bitfld.long 0x0 0. "NRBKEN,NOR region enable" "0,1"
group.long 0x4++0x3
line.long 0x0 "SNTCFG0,SRAM/NOR Flash timing configuration registe 0"
bitfld.long 0x0 28.--29. "ASYNCMOD,Asynchronous access mode" "0,1,2,3"
hexmask.long.byte 0x0 24.--27. 1. "DLAT,Data latency for NOR Flash"
hexmask.long.byte 0x0 20.--23. 1. "CKDIV,Synchronous clock divide ratio"
hexmask.long.byte 0x0 16.--19. 1. "BUSLAT,Bus latency"
hexmask.long.byte 0x0 8.--15. 1. "DSET,Data setup time"
hexmask.long.byte 0x0 4.--7. 1. "AHLD,Address hold time"
hexmask.long.byte 0x0 0.--3. 1. "ASET,Address setup time"
group.long 0xC++0x3
line.long 0x0 "SNTCFG1,SRAM/NOR Flash timing configuration registe 1"
bitfld.long 0x0 28.--29. "ASYNCMOD,Asynchronous access mode" "0,1,2,3"
hexmask.long.byte 0x0 24.--27. 1. "DLAT,Data latency for NOR Flash"
hexmask.long.byte 0x0 20.--23. 1. "CKDIV,Synchronous clock divide ratio"
hexmask.long.byte 0x0 16.--19. 1. "BUSLAT,Bus latency"
hexmask.long.byte 0x0 8.--15. 1. "DSET,Data setup time"
hexmask.long.byte 0x0 4.--7. 1. "AHLD,Address hold time"
hexmask.long.byte 0x0 0.--3. 1. "ASET,Address setup time"
group.long 0x14++0x3
line.long 0x0 "SNTCFG2,SRAM/NOR Flash timing configuration registe 2"
bitfld.long 0x0 28.--29. "ASYNCMOD,Asynchronous access mode" "0,1,2,3"
hexmask.long.byte 0x0 24.--27. 1. "DLAT,Data latency for NOR Flash"
hexmask.long.byte 0x0 20.--23. 1. "CKDIV,Synchronous clock divide ratio"
hexmask.long.byte 0x0 16.--19. 1. "BUSLAT,Bus latency"
hexmask.long.byte 0x0 8.--15. 1. "DSET,Data setup time"
hexmask.long.byte 0x0 4.--7. 1. "AHLD,Address hold time"
hexmask.long.byte 0x0 0.--3. 1. "ASET,Address setup time"
group.long 0x1C++0x3
line.long 0x0 "SNTCFG3,SRAM/NOR Flash timing configuration registe 3"
bitfld.long 0x0 28.--29. "ASYNCMOD,Asynchronous access mode" "0,1,2,3"
hexmask.long.byte 0x0 24.--27. 1. "DLAT,Data latency for NOR Flash"
hexmask.long.byte 0x0 20.--23. 1. "CKDIV,Synchronous clock divide ratio"
hexmask.long.byte 0x0 16.--19. 1. "BUSLAT,Bus latency"
hexmask.long.byte 0x0 8.--15. 1. "DSET,Data setup time"
hexmask.long.byte 0x0 4.--7. 1. "AHLD,Address hold time"
hexmask.long.byte 0x0 0.--3. 1. "ASET,Address setup time"
group.long 0x104++0x3
line.long 0x0 "SNWTCFG0,SRAM/NOR Flash write timing configuration registe 0"
bitfld.long 0x0 28.--29. "WASYNCMOD,Asynchronous access mode" "0,1,2,3"
hexmask.long.byte 0x0 16.--19. 1. "WBUSLAT,Bus latency"
hexmask.long.byte 0x0 8.--15. 1. "WDSET,Data setup time"
hexmask.long.byte 0x0 4.--7. 1. "WAHLD,Address hold time"
hexmask.long.byte 0x0 0.--3. 1. "WASET,Address setup time"
group.long 0x10C++0x3
line.long 0x0 "SNWTCFG1,SRAM/NOR Flash write timing configuration registe 1"
bitfld.long 0x0 28.--29. "WASYNCMOD,Asynchronous access mode" "0,1,2,3"
hexmask.long.byte 0x0 16.--19. 1. "WBUSLAT,Bus latency"
hexmask.long.byte 0x0 8.--15. 1. "WDSET,Data setup time"
hexmask.long.byte 0x0 4.--7. 1. "WAHLD,Address hold time"
hexmask.long.byte 0x0 0.--3. 1. "WASET,Address setup time"
group.long 0x114++0x3
line.long 0x0 "SNWTCFG2,SRAM/NOR Flash write timing configuration registe 2"
bitfld.long 0x0 28.--29. "WASYNCMOD,Asynchronous access mode" "0,1,2,3"
hexmask.long.byte 0x0 16.--19. 1. "WBUSLAT,Bus latency"
hexmask.long.byte 0x0 8.--15. 1. "WDSET,Data setup time"
hexmask.long.byte 0x0 4.--7. 1. "WAHLD,Address hold time"
hexmask.long.byte 0x0 0.--3. 1. "WASET,Address setup time"
group.long 0x11C++0x3
line.long 0x0 "SNWTCFG3,SRAM/NOR Flash write timing configuration registe 3"
bitfld.long 0x0 28.--29. "WASYNCMOD,Asynchronous access mode" "0,1,2,3"
hexmask.long.byte 0x0 16.--19. 1. "WBUSLAT,Bus latency"
hexmask.long.byte 0x0 8.--15. 1. "WDSET,Data setup time"
hexmask.long.byte 0x0 4.--7. 1. "WAHLD,Address hold time"
hexmask.long.byte 0x0 0.--3. 1. "WASET,Address setup time"
rgroup.long 0x84++0x3
line.long 0x0 "SNSTAT,SRAM/NOR flash status registers"
bitfld.long 0x0 6. "FIFOEPT,FIFO empty flag" "0,1"
group.long 0x300++0xF
line.long 0x0 "SNLATDEC0,SRAM/NOR flash data latency decrease register 0"
bitfld.long 0x0 0.--2. "LATDEC,Data latency decrease for NOR Flash" "0,1,2,3,4,5,6,7"
line.long 0x4 "SNLATDEC1,SRAM/NOR flash data latency decrease register 1"
bitfld.long 0x4 0.--2. "LATDEC,Data latency decrease for NOR Flash" "0,1,2,3,4,5,6,7"
line.long 0x8 "SNLATDEC2,SRAM/NOR flash data latency decrease register 2"
bitfld.long 0x8 0.--2. "LATDEC,Data latency decrease for NOR Flash" "0,1,2,3,4,5,6,7"
line.long 0xC "SNLATDEC3,SRAM/NOR flash data latency decrease register 3"
bitfld.long 0xC 0.--2. "LATDEC,Data latency decrease for NOR Flash" "0,1,2,3,4,5,6,7"
tree.end
tree "EXTI (External Interrupt/Event Controller)"
base ad:0x40010400
group.long 0x0++0x2F
line.long 0x0 "INTEN0,Interrupt enable register 0"
bitfld.long 0x0 31. "INTEN31,Interrupt enable bit 31" "0,1"
bitfld.long 0x0 30. "INTEN30,Interrupt enable bit 30" "0,1"
bitfld.long 0x0 29. "INTEN29,Interrupt enable bit 29" "0,1"
bitfld.long 0x0 28. "INTEN28,Interrupt enable bit 28" "0,1"
bitfld.long 0x0 27. "INTEN27,Interrupt enable bit 27" "0,1"
bitfld.long 0x0 26. "INTEN26,Interrupt enable bit 26" "0,1"
bitfld.long 0x0 25. "INTEN25,Interrupt enable bit 25" "0,1"
bitfld.long 0x0 24. "INTEN24,Interrupt enable bit 24" "0,1"
bitfld.long 0x0 23. "INTEN23,Interrupt enable bit 23" "0,1"
bitfld.long 0x0 22. "INTEN22,Interrupt enable bit 22" "0,1"
bitfld.long 0x0 21. "INTEN21,Interrupt enable bit 21" "0,1"
bitfld.long 0x0 20. "INTEN20,Interrupt enable bit 20" "0,1"
newline
bitfld.long 0x0 19. "INTEN19,Interrupt enable bit 19" "0,1"
bitfld.long 0x0 18. "INTEN18,Interrupt enable bit 18" "0,1"
bitfld.long 0x0 17. "INTEN17,Interrupt enable bit 17" "0,1"
bitfld.long 0x0 16. "INTEN16,Interrupt enable bit 16" "0,1"
bitfld.long 0x0 15. "INTEN15,Interrupt enable bit 15" "0,1"
bitfld.long 0x0 14. "INTEN14,Interrupt enable bit 14" "0,1"
bitfld.long 0x0 13. "INTEN13,Interrupt enable bit 13" "0,1"
bitfld.long 0x0 12. "INTEN12,Interrupt enable bit 12" "0,1"
bitfld.long 0x0 11. "INTEN11,Interrupt enable bit 11" "0,1"
bitfld.long 0x0 10. "INTEN10,Interrupt enable bit 10" "0,1"
bitfld.long 0x0 9. "INTEN9,Interrupt enable bit 9" "0,1"
bitfld.long 0x0 8. "INTEN8,Interrupt enable bit 8" "0,1"
newline
bitfld.long 0x0 7. "INTEN7,Interrupt enable bit 7" "0,1"
bitfld.long 0x0 6. "INTEN6,Interrupt enable bit 6" "0,1"
bitfld.long 0x0 5. "INTEN5,Interrupt enable bit 5" "0,1"
bitfld.long 0x0 4. "INTEN4,Interrupt enable bit 4" "0,1"
bitfld.long 0x0 3. "INTEN3,Interrupt enable bit 3" "0,1"
bitfld.long 0x0 2. "INTEN2,Interrupt enable bit 2" "0,1"
bitfld.long 0x0 1. "INTEN1,Interrupt enable bit 1" "0,1"
bitfld.long 0x0 0. "INTEN0,Interrupt enable bit 0" "0,1"
line.long 0x4 "EVEN0,Event enable register 0"
bitfld.long 0x4 31. "EVEN31,Event enable bit 31" "0,1"
bitfld.long 0x4 30. "EVEN30,Event enable bit 30" "0,1"
bitfld.long 0x4 29. "EVEN29,Event enable bit 29" "0,1"
bitfld.long 0x4 28. "EVEN28,Event enable bit 28" "0,1"
bitfld.long 0x4 27. "EVEN27,Event enable bit 27" "0,1"
bitfld.long 0x4 26. "EVEN26,Event enable bit 26" "0,1"
bitfld.long 0x4 25. "EVEN25,Event enable bit 25" "0,1"
bitfld.long 0x4 24. "EVEN24,Event enable bit 24" "0,1"
bitfld.long 0x4 23. "EVEN23,Event enable bit 23" "0,1"
bitfld.long 0x4 22. "EVEN22,Event enable bit 22" "0,1"
bitfld.long 0x4 21. "EVEN21,Event enable bit 21" "0,1"
bitfld.long 0x4 20. "EVEN20,Event enable bit 20" "0,1"
newline
bitfld.long 0x4 19. "EVEN19,Event enable bit 19" "0,1"
bitfld.long 0x4 18. "EVEN18,Event enable bit 18" "0,1"
bitfld.long 0x4 17. "EVEN17,Event enable bit 17" "0,1"
bitfld.long 0x4 16. "EVEN16,Event enable bit 16" "0,1"
bitfld.long 0x4 15. "EVEN15,Event enable bit 15" "0,1"
bitfld.long 0x4 14. "EVEN14,Event enable bit 14" "0,1"
bitfld.long 0x4 13. "EVEN13,Event enable bit 13" "0,1"
bitfld.long 0x4 12. "EVEN12,Event enable bit 12" "0,1"
bitfld.long 0x4 11. "EVEN11,Event enable bit 11" "0,1"
bitfld.long 0x4 10. "EVEN10,Event enable bit 10" "0,1"
bitfld.long 0x4 9. "EVEN9,Event enable bit 9" "0,1"
bitfld.long 0x4 8. "EVEN8,Event enable bit 8" "0,1"
newline
bitfld.long 0x4 7. "EVEN7,Event enable bit 7" "0,1"
bitfld.long 0x4 6. "EVEN6,Event enable bit 6" "0,1"
bitfld.long 0x4 5. "EVEN5,Event enable bit 5" "0,1"
bitfld.long 0x4 4. "EVEN4,Event enable bit 4" "0,1"
bitfld.long 0x4 3. "EVEN3,Event enable bit 3" "0,1"
bitfld.long 0x4 2. "EVEN2,Event enable bit 2" "0,1"
bitfld.long 0x4 1. "EVEN1,Event enable bit 1" "0,1"
bitfld.long 0x4 0. "EVEN0,Event enable bit 0" "0,1"
line.long 0x8 "RTEN0,Rising edge trigger enable register 0"
bitfld.long 0x8 31. "RTEN31,Rising edge trigger enable bit 31" "0,1"
bitfld.long 0x8 30. "RTEN30,Rising edge trigger enable bit 30" "0,1"
bitfld.long 0x8 29. "RTEN29,Rising edge trigger enable bit 29" "0,1"
bitfld.long 0x8 28. "RTEN28,Rising edge trigger enable bit 28" "0,1"
bitfld.long 0x8 27. "RTEN27,Rising edge trigger enable bit 27" "0,1"
bitfld.long 0x8 26. "RTEN26,Rising edge trigger enable bit 26" "0,1"
bitfld.long 0x8 25. "RTEN25,Rising edge trigger enable bit 25" "0,1"
bitfld.long 0x8 24. "RTEN24,Rising edge trigger enable bit 24" "0,1"
bitfld.long 0x8 23. "RTEN23,Rising edge trigger enable bit 23" "0,1"
bitfld.long 0x8 22. "RTEN22,Rising edge trigger enable bit 22" "0,1"
bitfld.long 0x8 21. "RTEN21,Rising edge trigger enable bit 21" "0,1"
bitfld.long 0x8 20. "RTEN20,Rising edge trigger enable bit 20" "0,1"
newline
bitfld.long 0x8 19. "RTEN19,Rising edge trigger enable bit 19" "0,1"
bitfld.long 0x8 18. "RTEN18,Rising edge trigger enable bit 18" "0,1"
bitfld.long 0x8 17. "RTEN17,Rising edge trigger enable bit 17" "0,1"
bitfld.long 0x8 16. "RTEN16,Rising edge trigger enable bit 16" "0,1"
bitfld.long 0x8 15. "RTEN15,Rising edge trigger enable bit 15" "0,1"
bitfld.long 0x8 14. "RTEN14,Rising edge trigger enable bit 14" "0,1"
bitfld.long 0x8 13. "RTEN13,Rising edge trigger enable bit 13" "0,1"
bitfld.long 0x8 12. "RTEN12,Rising edge trigger enable bit 12" "0,1"
bitfld.long 0x8 11. "RTEN11,Rising edge trigger enable bit 11" "0,1"
bitfld.long 0x8 10. "RTEN10,Rising edge trigger enable bit 10" "0,1"
bitfld.long 0x8 9. "RTEN9,Rising edge trigger enable bit 9" "0,1"
bitfld.long 0x8 8. "RTEN8,Rising edge trigger enable bit 8" "0,1"
newline
bitfld.long 0x8 7. "RTEN7,Rising edge trigger enable bit 7" "0,1"
bitfld.long 0x8 6. "RTEN6,Rising edge trigger enable bit 6" "0,1"
bitfld.long 0x8 5. "RTEN5,Rising edge trigger enable bit 5" "0,1"
bitfld.long 0x8 4. "RTEN4,Rising edge trigger enable bit 4" "0,1"
bitfld.long 0x8 3. "RTEN3,Rising edge trigger enable bit 3" "0,1"
bitfld.long 0x8 2. "RTEN2,Rising edge trigger enable bit 2" "0,1"
bitfld.long 0x8 1. "RTEN1,Rising edge trigger enable bit 1" "0,1"
bitfld.long 0x8 0. "RTEN0,Rising edge trigger enable bit 0" "0,1"
line.long 0xC "FTEN0,Falling edge trigger enable register 0"
bitfld.long 0xC 31. "FTEN31,Falling edge trigger enable bit 31" "0,1"
bitfld.long 0xC 30. "FTEN30,Falling edge trigger enable bit 30" "0,1"
bitfld.long 0xC 29. "FTEN29,Falling edge trigger enable bit 29" "0,1"
bitfld.long 0xC 28. "FTEN28,Falling edge trigger enable bit 28" "0,1"
bitfld.long 0xC 27. "FTEN27,Falling edge trigger enable bit 27" "0,1"
bitfld.long 0xC 26. "FTEN26,Falling edge trigger enable bit 26" "0,1"
bitfld.long 0xC 25. "FTEN25,Falling edge trigger enable bit 25" "0,1"
bitfld.long 0xC 24. "FTEN24,Falling edge trigger enable bit 24" "0,1"
bitfld.long 0xC 23. "FTEN23,Falling edge trigger enable bit 23" "0,1"
bitfld.long 0xC 22. "FTEN22,Falling edge trigger enable bit 22" "0,1"
bitfld.long 0xC 21. "FTEN21,Falling edge trigger enable bit 21" "0,1"
bitfld.long 0xC 20. "FTEN20,Falling edge trigger enable bit 20" "0,1"
newline
bitfld.long 0xC 19. "FTEN19,Falling edge trigger enable bit 19" "0,1"
bitfld.long 0xC 18. "FTEN18,Falling edge trigger enable bit 18" "0,1"
bitfld.long 0xC 17. "FTEN17,Falling edge trigger enable bit 17" "0,1"
bitfld.long 0xC 16. "FTEN16,Falling edge trigger enable bit 16" "0,1"
bitfld.long 0xC 15. "FTEN15,Falling edge trigger enable bit 15" "0,1"
bitfld.long 0xC 14. "FTEN14,Falling edge trigger enable bit 14" "0,1"
bitfld.long 0xC 13. "FTEN13,Falling edge trigger enable bit 13" "0,1"
bitfld.long 0xC 12. "FTEN12,Falling edge trigger enable bit 12" "0,1"
bitfld.long 0xC 11. "FTEN11,Falling edge trigger enable bit 11" "0,1"
bitfld.long 0xC 10. "FTEN10,Falling edge trigger enable bit 10" "0,1"
bitfld.long 0xC 9. "FTEN9,Falling edge trigger enable bit 9" "0,1"
bitfld.long 0xC 8. "FTEN8,Falling edge trigger enable bit 8" "0,1"
newline
bitfld.long 0xC 7. "FTEN7,Falling edge trigger enable bit 7" "0,1"
bitfld.long 0xC 6. "FTEN6,Falling edge trigger enable bit 6" "0,1"
bitfld.long 0xC 5. "FTEN5,Falling edge trigger enable bit 5" "0,1"
bitfld.long 0xC 4. "FTEN4,Falling edge trigger enable bit 4" "0,1"
bitfld.long 0xC 3. "FTEN3,Falling edge trigger enable bit 3" "0,1"
bitfld.long 0xC 2. "FTEN2,Falling edge trigger enable bit 2" "0,1"
bitfld.long 0xC 1. "FTEN1,Falling edge trigger enable bit 1" "0,1"
bitfld.long 0xC 0. "FTEN0,Falling edge trigger enable bit 0" "0,1"
line.long 0x10 "SWIEV0,Software interrupt event register 0"
bitfld.long 0x10 31. "SWIEV31,Interrupt/Event software trigger bit 31" "0,1"
bitfld.long 0x10 30. "SWIEV30,Interrupt/Event software trigger bit 30" "0,1"
bitfld.long 0x10 29. "SWIEV29,Interrupt/Event software trigger bit 29" "0,1"
bitfld.long 0x10 28. "SWIEV28,Interrupt/Event software trigger bit 28" "0,1"
bitfld.long 0x10 27. "SWIEV27,Interrupt/Event software trigger bit 27" "0,1"
bitfld.long 0x10 26. "SWIEV26,Interrupt/Event software trigger bit 26" "0,1"
bitfld.long 0x10 25. "SWIEV25,Interrupt/Event software trigger bit 25" "0,1"
bitfld.long 0x10 24. "SWIEV24,Interrupt/Event software trigger bit 24" "0,1"
bitfld.long 0x10 23. "SWIEV23,Interrupt/Event software trigger bit 23" "0,1"
bitfld.long 0x10 22. "SWIEV22,Interrupt/Event software trigger bit 22" "0,1"
bitfld.long 0x10 21. "SWIEV21,Interrupt/Event software trigger bit 21" "0,1"
bitfld.long 0x10 20. "SWIEV20,Interrupt/Event software trigger bit 20" "0,1"
newline
bitfld.long 0x10 19. "SWIEV19,Interrupt/Event software trigger bit 19" "0,1"
bitfld.long 0x10 18. "SWIEV18,Interrupt/Event software trigger bit 18" "0,1"
bitfld.long 0x10 17. "SWIEV17,Interrupt/Event software trigger bit 17" "0,1"
bitfld.long 0x10 16. "SWIEV16,Interrupt/Event software trigger bit 16" "0,1"
bitfld.long 0x10 15. "SWIEV15,Interrupt/Event software trigger bit 15" "0,1"
bitfld.long 0x10 14. "SWIEV14,Interrupt/Event software trigger bit 14" "0,1"
bitfld.long 0x10 13. "SWIEV13,Interrupt/Event software trigger bit 13" "0,1"
bitfld.long 0x10 12. "SWIEV12,Interrupt/Event software trigger bit 12" "0,1"
bitfld.long 0x10 11. "SWIEV11,Interrupt/Event software trigger bit 11" "0,1"
bitfld.long 0x10 10. "SWIEV10,Interrupt/Event software trigger bit 10" "0,1"
bitfld.long 0x10 9. "SWIEV9,Interrupt/Event software trigger bit 9" "0,1"
bitfld.long 0x10 8. "SWIEV8,Interrupt/Event software trigger bit 8" "0,1"
newline
bitfld.long 0x10 7. "SWIEV7,Interrupt/Event software trigger bit 7" "0,1"
bitfld.long 0x10 6. "SWIEV6,Interrupt/Event software trigger bit 6" "0,1"
bitfld.long 0x10 5. "SWIEV5,Interrupt/Event software trigger bit 5" "0,1"
bitfld.long 0x10 4. "SWIEV4,Interrupt/Event software trigger bit 4" "0,1"
bitfld.long 0x10 3. "SWIEV3,Interrupt/Event software trigger bit 3" "0,1"
bitfld.long 0x10 2. "SWIEV2,Interrupt/Event software trigger bit 2" "0,1"
bitfld.long 0x10 1. "SWIEV1,Interrupt/Event software trigger bit 1" "0,1"
bitfld.long 0x10 0. "SWIEV0,Interrupt/Event software trigger bit 0" "0,1"
line.long 0x14 "PD0,Pending register 0"
bitfld.long 0x14 31. "PD31,Interrupt pending status bit 31" "0,1"
bitfld.long 0x14 30. "PD30,Interrupt pending status bit 30" "0,1"
bitfld.long 0x14 29. "PD29,Interrupt pending status bit 29" "0,1"
bitfld.long 0x14 28. "PD28,Interrupt pending status bit 28" "0,1"
bitfld.long 0x14 27. "PD27,Interrupt pending status bit 27" "0,1"
bitfld.long 0x14 26. "PD26,Interrupt pending status bit 26" "0,1"
bitfld.long 0x14 25. "PD25,Interrupt pending status bit 25" "0,1"
bitfld.long 0x14 24. "PD24,Interrupt pending status bit 24" "0,1"
bitfld.long 0x14 23. "PD23,Interrupt pending status bit 23" "0,1"
bitfld.long 0x14 22. "PD22,Interrupt pending status bit 22" "0,1"
bitfld.long 0x14 21. "PD21,Interrupt pending status bit 21" "0,1"
bitfld.long 0x14 20. "PD20,Interrupt pending status bit 20" "0,1"
newline
bitfld.long 0x14 19. "PD19,Interrupt pending status bit 19" "0,1"
bitfld.long 0x14 18. "PD18,Interrupt pending status bit 18" "0,1"
bitfld.long 0x14 17. "PD17,Interrupt pending status bit 17" "0,1"
bitfld.long 0x14 16. "PD16,Interrupt pending status bit 16" "0,1"
bitfld.long 0x14 15. "PD15,Interrupt pending status bit 15" "0,1"
bitfld.long 0x14 14. "PD14,Interrupt pending status bit 14" "0,1"
bitfld.long 0x14 13. "PD13,Interrupt pending status bit 13" "0,1"
bitfld.long 0x14 12. "PD12,Interrupt pending status bit 12" "0,1"
bitfld.long 0x14 11. "PD11,Interrupt pending status bit 11" "0,1"
bitfld.long 0x14 10. "PD10,Interrupt pending status bit 10" "0,1"
bitfld.long 0x14 9. "PD9,Interrupt pending status bit 9" "0,1"
bitfld.long 0x14 8. "PD8,Interrupt pending status bit 8" "0,1"
newline
bitfld.long 0x14 7. "PD7,Interrupt pending status bit 7" "0,1"
bitfld.long 0x14 6. "PD6,Interrupt pending status bit 6" "0,1"
bitfld.long 0x14 5. "PD5,Interrupt pending status bit 5" "0,1"
bitfld.long 0x14 4. "PD4,Interrupt pending status bit 4" "0,1"
bitfld.long 0x14 3. "PD3,Interrupt pending status bit 3" "0,1"
bitfld.long 0x14 2. "PD2,Interrupt pending status bit 2" "0,1"
bitfld.long 0x14 1. "PD1,Interrupt pending status bit 1" "0,1"
bitfld.long 0x14 0. "PD0,Interrupt pending status bit 0" "0,1"
line.long 0x18 "INTEN1,Interrupt enable register 1"
bitfld.long 0x18 6. "INTEN38,Interrupt enable bit 6" "0,1"
bitfld.long 0x18 5. "INTEN37,Interrupt enable bit 5" "0,1"
bitfld.long 0x18 4. "INTEN36,Interrupt enable bit 4" "0,1"
bitfld.long 0x18 3. "INTEN35,Interrupt enable bit 3" "0,1"
bitfld.long 0x18 2. "INTEN34,Interrupt enable bit 2" "0,1"
bitfld.long 0x18 1. "INTEN33,Interrupt enable bit 1" "0,1"
bitfld.long 0x18 0. "INTEN32,Interrupt enable bit 0" "0,1"
line.long 0x1C "EVEN1,Event enable register 1"
bitfld.long 0x1C 6. "EVEN38,Event enable bit 6" "0,1"
bitfld.long 0x1C 5. "EVEN37,Event enable bit 5" "0,1"
bitfld.long 0x1C 4. "EVEN36,Event enable bit 4" "0,1"
bitfld.long 0x1C 3. "EVEN35,Event enable bit 3" "0,1"
bitfld.long 0x1C 2. "EVEN34,Event enable bit 2" "0,1"
bitfld.long 0x1C 1. "EVEN33,Event enable bit 1" "0,1"
bitfld.long 0x1C 0. "EVEN32,Event enable bit 0" "0,1"
line.long 0x20 "RTEN1,Rising edge trigger enable register 1"
bitfld.long 0x20 6. "RTEN38,Rising edge trigger enable 6" "0,1"
bitfld.long 0x20 5. "RTEN37,Rising edge trigger enable 5" "0,1"
bitfld.long 0x20 4. "RTEN36,Rising edge trigger enable 4" "0,1"
bitfld.long 0x20 3. "RTEN35,Rising edge trigger enable 3" "0,1"
bitfld.long 0x20 2. "RTEN34,Rising edge trigger enable 2" "0,1"
bitfld.long 0x20 1. "RTEN33,Rising edge trigger enable 1" "0,1"
bitfld.long 0x20 0. "RTEN32,Rising edge trigger enable 0" "0,1"
line.long 0x24 "FTEN1,Falling edge trigger enable register 1"
bitfld.long 0x24 6. "FTEN38,Falling edge trigger enable 6" "0,1"
bitfld.long 0x24 5. "FTEN37,Falling edge trigger enable 5" "0,1"
bitfld.long 0x24 4. "FTEN36,Falling edge trigger enable 4" "0,1"
bitfld.long 0x24 3. "FTEN35,Falling edge trigger enable 3" "0,1"
bitfld.long 0x24 2. "FTEN34,Falling edge trigger enable 2" "0,1"
bitfld.long 0x24 1. "FTEN33,Falling edge trigger enable 1" "0,1"
bitfld.long 0x24 0. "FTEN32,Falling edge trigger enable 0" "0,1"
line.long 0x28 "SWIEV1,Software interrupt event register 1"
bitfld.long 0x28 6. "SWIEV38,Interrupt / Event software trigger 6" "0,1"
bitfld.long 0x28 5. "SWIEV37,Interrupt / Event software trigger 5" "0,1"
bitfld.long 0x28 4. "SWIEV36,Interrupt / Event software trigger 4" "0,1"
bitfld.long 0x28 3. "SWIEV35,Interrupt / Event software trigger 3" "0,1"
bitfld.long 0x28 2. "SWIEV34,Interrupt / Event software trigger 2" "0,1"
bitfld.long 0x28 1. "SWIEV33,Interrupt / Event software trigger 1" "0,1"
bitfld.long 0x28 0. "SWIEV32,Interrupt / Event software trigger 0" "0,1"
line.long 0x2C "PD1,Pending register 1"
bitfld.long 0x2C 6. "PD38,Interrupt pending status 6" "0,1"
bitfld.long 0x2C 5. "PD37,Interrupt pending status 5" "0,1"
bitfld.long 0x2C 4. "PD36,Interrupt pending status 4" "0,1"
bitfld.long 0x2C 3. "PD35,Interrupt pending status 3" "0,1"
bitfld.long 0x2C 2. "PD34,Interrupt pending status 2" "0,1"
bitfld.long 0x2C 1. "PD33,Interrupt pending status 1" "0,1"
bitfld.long 0x2C 0. "PD32,Interrupt pending status 0" "0,1"
tree.end
tree "FAC (Filter Arithmetic Accelerator)"
base ad:0x48024800
group.long 0x0++0x13
line.long 0x0 "X0BCFG,FAC X0 buffer configure register"
bitfld.long 0x0 24.--25. "X0_WBFF,Watermark for buffer full flag" "0,1,2,3"
hexmask.long.byte 0x0 8.--15. 1. "X0B_BSIZE,X0 buffer allocated size the number of feed-forward taps in the filter"
hexmask.long.byte 0x0 0.--7. 1. "X0B_BADDR,X0 buffer base address"
line.long 0x4 "X1BCFG,FAC X1 buffer configure register"
hexmask.long.byte 0x4 8.--15. 1. "X1B_SIZE,X1 buffer allocated size"
hexmask.long.byte 0x4 0.--7. 1. "X1B_ADDR,X1 buffer base address"
line.long 0x8 "YBCFG,FAC Y buffer configure register"
bitfld.long 0x8 24.--25. "Y_WBEF,Watermark for buffer empty flag" "0,1,2,3"
hexmask.long.byte 0x8 8.--15. 1. "YB_SIZE,Y buffer allocated size"
hexmask.long.byte 0x8 0.--7. 1. "YB_ADDR,Y buffer base address"
line.long 0xC "PARACFG,FAC Parameter configure register"
bitfld.long 0xC 31. "EXE,Execution" "0,1"
hexmask.long.byte 0xC 24.--30. 1. "FUN,Function"
hexmask.long.byte 0xC 16.--23. 1. "IPR,Input parameter R"
hexmask.long.byte 0xC 8.--15. 1. "IPQ,Input parameter Q"
hexmask.long.byte 0xC 0.--7. 1. "IPP,Input parameter P"
line.long 0x10 "CTL,FAC Control register"
bitfld.long 0x10 16. "RST,Reset FAC unit" "0,1"
bitfld.long 0x10 15. "CPEN,Clipping enable" "0,1"
bitfld.long 0x10 14. "FLTEN,Floating point format enable" "0,1"
bitfld.long 0x10 9. "DWEN,DMA write channel enable" "0,1"
bitfld.long 0x10 8. "DREN,DMA read channel enable" "0,1"
bitfld.long 0x10 5. "GSTEIE,Gain saturation error interrupt enable" "0,1"
bitfld.long 0x10 4. "STEIE,Saturation error interrupt enable" "0,1"
bitfld.long 0x10 3. "UFEIE,Underflow error interrupt enable" "0,1"
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bitfld.long 0x10 2. "OFEIE,Overflow error interrupt enable" "0,1"
bitfld.long 0x10 1. "WIE,Write interrupt enable" "0,1"
bitfld.long 0x10 0. "RIE,Read interrupt enable" "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "STAT,FAC Status register"
bitfld.long 0x0 11. "GSTEF,Gain saturation error flag it is set when gain exceed range" "0,1"
bitfld.long 0x0 10. "STEF,Saturation error flag" "0,1"
bitfld.long 0x0 9. "UFEF,Underflow error flag" "0,1"
bitfld.long 0x0 8. "OFEF,Overflow error flag" "0,1"
bitfld.long 0x0 1. "X0BFF,X0 buffer full flag" "0,1"
bitfld.long 0x0 0. "YBEFF,Y buffer empty flag" "0,1"
group.long 0x18++0x3
line.long 0x0 "WDATA,FAC write data register"
hexmask.long.word 0x0 0.--15. 1. "WDATA,Write data"
rgroup.long 0x1C++0x3
line.long 0x0 "RDATA,FAC read data register"
hexmask.long 0x0 0.--31. 1. "RDATA,Read data"
tree.end
tree "FFT (Fast Fourier Transform)"
base ad:0x40025000
group.long 0x0++0x17
line.long 0x0 "CSR,Control and status register"
rbitfld.long 0x0 31. "DMABSY,DMA Busy" "0,1"
bitfld.long 0x0 30. "CCF,FFT calculation completion flag" "0,1"
bitfld.long 0x0 29. "CCIE,FFT calculation completion interrupt enable" "0,1"
bitfld.long 0x0 28. "TAEIF,Transfer access error interrupt flag" "0,1"
bitfld.long 0x0 27. "TAEIE,Transfer access error interrupt enable" "0,1"
bitfld.long 0x0 13.--14. "IMSEL,Image input source select" "0,1,2,3"
hexmask.long.byte 0x0 9.--12. 1. "DOWNSAMP,Input data down sample selection"
bitfld.long 0x0 8. "WINEN,Window function enable" "0,1"
newline
bitfld.long 0x0 4. "IFFTMODE,IFFT mode enable" "0,1"
bitfld.long 0x0 1.--3. "NUMPT,Number of FFT Point" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "FFTEN,FFT enable" "0,1"
line.long 0x4 "RESADDR,Real start address register"
hexmask.long 0x4 0.--31. 1. "RESADDR,FFT real start address"
line.long 0x8 "IMSADDR,Image start address register"
hexmask.long 0x8 0.--31. 1. "IMSADDR,FFT image start address"
line.long 0xC "WSADDR,Window start address register"
hexmask.long 0xC 0.--31. 1. "FFT_WSADDR,FFT window start address"
line.long 0x10 "OSADDR,Output start address register"
hexmask.long 0x10 0.--31. 1. "FFT_OSADDR,FFT output start address"
line.long 0x14 "LOOPLEN,Loop length register"
hexmask.long.word 0x14 16.--31. 1. "INDEX,The index of DMA loop buffer"
hexmask.long.word 0x14 0.--15. 1. "LENGTH,The DMA loop buffer length of the FFT input data"
tree.end
tree "FMC (Flash Memory Controller)"
base ad:0x40022000
group.long 0x0++0x3
line.long 0x0 "WS,Wait state register"
bitfld.long 0x0 18. "DBGEN,This bit is used to enable/disable the debugger by software" "0,1"
bitfld.long 0x0 14. "SLP_MDSEL,Flash power-down mode during sleep mode" "0,1"
bitfld.long 0x0 13. "RUN_MDSEL,Flash power-down mode during run mode" "0,1"
bitfld.long 0x0 12. "DCRST,Data cache reset" "0,1"
bitfld.long 0x0 11. "ICRST,Instruction cache reset" "0,1"
bitfld.long 0x0 10. "DCEN,Data cache enable" "0,1"
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bitfld.long 0x0 9. "ICEN,Instruction cache enable" "0,1"
bitfld.long 0x0 8. "PFEN,Pre-fetch enable" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "WSCNT,Wait state counter register"
wgroup.long 0x4++0xB
line.long 0x0 "RUNKEY,Unlock flash mode during run mode key register"
hexmask.long 0x0 0.--31. 1. "RUN_KEY,RUN_MDSEL unlock register"
line.long 0x4 "KEY,Unlock key register"
hexmask.long 0x4 0.--31. 1. "KEY,FMC_CTL unlock register"
line.long 0x8 "OBKEY,Option byte unlock key register"
hexmask.long 0x8 0.--31. 1. "OBKEY,FMC_CTL option bytes operation unlock register"
group.long 0x10++0xB
line.long 0x0 "STAT,Status register"
rbitfld.long 0x0 16. "BUSY,The flash is busy bit" "0,1"
bitfld.long 0x0 15. "OBERR,Option byte read error bit" "0,1"
bitfld.long 0x0 14. "RPERR,Read protection error flag bit" "0,1"
bitfld.long 0x0 7. "PGSERR,Program sequence error flag bit" "0,1"
bitfld.long 0x0 6. "PGMERR,Program size not match error flag bit" "0,1"
bitfld.long 0x0 5. "PGAERR,Program alignment error flag bit" "0,1"
newline
bitfld.long 0x0 4. "WPERR,Erase / program protection error flag bit" "0,1"
bitfld.long 0x0 3. "PGERR,Program error flag bit" "0,1"
bitfld.long 0x0 1. "OPRERR,Operation error flag bit" "0,1"
bitfld.long 0x0 0. "ENDF,End of operation flag bit" "0,1"
line.long 0x4 "CTL,Control register"
bitfld.long 0x4 31. "LK,FMC_CTL lock bit" "0,1"
bitfld.long 0x4 30. "OBLK,FMC_OBCTL lock bit" "0,1"
bitfld.long 0x4 29. "SCR1,Bank1 secure user area enable bit" "0,1"
bitfld.long 0x4 28. "SCR0,Bank0 secure user area enable bit" "0,1"
bitfld.long 0x4 27. "OBRLD,Option byte reload bit" "0,1"
bitfld.long 0x4 26. "RPERRIE,Read protection error interrupt enable bit" "0,1"
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bitfld.long 0x4 25. "ERRIE,OPRERR error interrupt enable bit" "0,1"
bitfld.long 0x4 24. "ENDIE,End of operation interrupt enable bit" "0,1"
bitfld.long 0x4 17. "OBSTART,Send option byte change command to FMC bit" "0,1"
bitfld.long 0x4 16. "START,Send erase command to FMC bit" "0,1"
bitfld.long 0x4 15. "MER1,Main flash mass erase for bank1 command bit" "0,1"
bitfld.long 0x4 12. "BKSEL,Bank number selection for page erase" "0,1"
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hexmask.long.byte 0x4 3.--10. 1. "PNSEL,Page number selection"
bitfld.long 0x4 2. "MER0,Main flash mass erase for bank0 command bit" "0,1"
bitfld.long 0x4 1. "PER,Main flash page erase command bit" "0,1"
bitfld.long 0x4 0. "PG,Main flash page program command bit" "0,1"
line.long 0x8 "ECCCS,ECC control and status register"
bitfld.long 0x8 31. "ECCDET0,Two bit errors detected flag" "0,1"
bitfld.long 0x8 30. "ECCCOR0,One-bit error detected and corrected flag" "0,1"
bitfld.long 0x8 29. "ECCDET1,Two bit errors detected flag" "0,1"
bitfld.long 0x8 28. "ECCCOR1,One-bit error detected and corrected flag" "0,1"
bitfld.long 0x8 24. "ECCCORIE,One-bit error correction interrupt enable" "0,1"
rbitfld.long 0x8 22. "SYS_ECC,If an ECC error correction or double ECC error is detected in bootloader this bit will be set" "0,1"
newline
rbitfld.long 0x8 21. "BK_ECC,ECC fail bank" "0,1"
hexmask.long.tbyte 0x8 0.--18. 1. "ECCADDR,ECC fail address"
group.long 0x20++0x13
line.long 0x0 "OBCTL,Option byte control register"
bitfld.long 0x0 28.--29. "NRST_MDSEL,NRST pin mode selection" "0,1,2,3"
bitfld.long 0x0 27. "nBOOT0,BOOT0 option bit" "0,1"
bitfld.long 0x0 26. "nSWBT0,Software BOOT0 disable" "0,1"
bitfld.long 0x0 25. "TCMSRAM_ERS,TCM SRAM erase if system reset" "0,1"
bitfld.long 0x0 24. "SRAM_ECCEN,SRAM and TCM SRAM ECC disable" "0,1"
bitfld.long 0x0 23. "nBOOT1,Boot1 configuration bit" "0,1"
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bitfld.long 0x0 22. "DBS,Double banks or single bank selection" "0,1"
bitfld.long 0x0 20. "BB,Option byte boot bank value" "0,1"
bitfld.long 0x0 18. "FWDGSPD_STDBY,FWDGT suspend option in standby mode configuration bit" "0,1"
bitfld.long 0x0 17. "FWDGSPD_DPSLP,FWDGT suspend option in deepsleep mode configuration bit" "0,1"
bitfld.long 0x0 16. "nFWDG_HW,Free watchdog configuration bit" "0,1"
bitfld.long 0x0 15. "FMC_SWP,FMC memory mapping swap" "0,1"
newline
bitfld.long 0x0 13. "nRST_STDBY,Option byte standby reset value" "0,1"
bitfld.long 0x0 12. "nRST_DPSLP,Option byte deepsleep reset value" "0,1"
bitfld.long 0x0 8.--9. "BOR_TH,BOR threshold status bits" "0,1,2,3"
hexmask.long.byte 0x0 0.--7. 1. "SPC,Security protection level option byte status bits"
line.long 0x4 "DCRP_SADDR0,DCRP start address register 0"
hexmask.long.word 0x4 0.--14. 1. "DCRP0_SADDR,DCRP area start address offset configuration bits for bank0"
line.long 0x8 "DCRP_EADDR0,DCRP end address register 0"
bitfld.long 0x8 31. "DCRP_EREN,DCRP area erase enable configuration bit" "0,1"
hexmask.long.word 0x8 0.--14. 1. "DCRP0_EADDR,DCRP area end address offset configuration bits for bank0"
line.long 0xC "BK0WP0,Bank0 erase/program protection area 0 register"
hexmask.long.byte 0xC 16.--23. 1. "BK0WP0_EADDR,WP first area end offset"
hexmask.long.byte 0xC 0.--7. 1. "BK0WP0_SADDR,WP first area start offset"
line.long 0x10 "BK0WP1,Bank0 erase/program protection area 1 register"
hexmask.long.byte 0x10 16.--23. 1. "BK0WP1_EADDR,WP second area end offset"
hexmask.long.byte 0x10 0.--7. 1. "BK0WP1_SADDR,WP second area start offset"
group.long 0x44++0xF
line.long 0x0 "DCRP_SADDR1,DCRP start address register 1"
hexmask.long.word 0x0 0.--14. 1. "DCRP1_SADDR,DCRP area start address offset configuration bits for bank1"
line.long 0x4 "DCRP_EADDR1,DCRP end address register 1"
hexmask.long.word 0x4 0.--14. 1. "DCRP1_EAREA,DCRP area end address offset configuration bits for bank1"
line.long 0x8 "BK1WP0,Bank1 erase/program protection area 0 register"
hexmask.long.byte 0x8 16.--23. 1. "BK1WP0_EADDR,WP third area end offset"
hexmask.long.byte 0x8 0.--7. 1. "BK1WP0_SADDR,WP third area start offset"
line.long 0xC "BK1WP1,Bank1 erase/program protection area 1 register"
hexmask.long.byte 0xC 16.--23. 1. "BK1WP1_EADDR,WP fourth area end offset"
hexmask.long.byte 0xC 0.--7. 1. "BK1WP1_SADDR,WP fourth area start offset"
group.long 0x70++0x7
line.long 0x0 "BK0SCR,Bank0 secure user area register"
bitfld.long 0x0 16. "BOOTLK,This bit is set to force boot from user flash area" "0,1"
hexmask.long.word 0x0 0.--8. 1. "SCR_PAGE_CNT0,Configure the number of pages in the bank0 secure user area"
line.long 0x4 "BK1SCR,Bank1 secure user area register"
hexmask.long.word 0x4 0.--8. 1. "SCR_PAGE_CNT1,Configure the number of pages in the bank1 secure user area"
rgroup.long 0x100++0x3
line.long 0x0 "PID,Product ID register"
hexmask.long 0x0 0.--31. 1. "PID,Product reserved ID code register"
tree.end
tree "FWDGT (Free Watchdog Timer)"
base ad:0x40003000
wgroup.long 0x0++0x3
line.long 0x0 "CTL,Control register"
hexmask.long.word 0x0 0.--15. 1. "CMD,Key value"
group.long 0x4++0x7
line.long 0x0 "PSC,Prescaler register"
bitfld.long 0x0 0.--2. "PSC,Prescaler divider" "0,1,2,3,4,5,6,7"
line.long 0x4 "RLD,Reload register"
hexmask.long.word 0x4 0.--11. 1. "RLD,Watchdog counter reload value"
rgroup.long 0xC++0x3
line.long 0x0 "STAT,Status register"
bitfld.long 0x0 2. "WUD,Watchdog counter window value update" "0,1"
bitfld.long 0x0 1. "RUD,Watchdog counter reload value update" "0,1"
bitfld.long 0x0 0. "PUD,Watchdog prescaler value update" "0,1"
group.long 0x10++0x3
line.long 0x0 "WND,Window register"
hexmask.long.word 0x0 0.--11. 1. "WND,Watchdog counter window value"
tree.end
tree "GPIO (General Purpose I/Os)"
base ad:0x0
tree "GPIOA"
base ad:0x48000000
group.long 0x0++0xF
line.long 0x0 "CTL,Port control register"
bitfld.long 0x0 30.--31. "CTL15,Pin 15 configuration bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "CTL14,Pin 14 configuration bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "CTL13,Pin 13 configuration bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "CTL12,Pin 12 configuration bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "CTL11,Pin 11 configuration bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "CTL10,Pin 10 configuration bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "CTL9,Pin 9 configuration bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "CTL8,Pin 8 configuration bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "CTL7,Pin 7 configuration bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "CTL6,Pin 6 configuration bits" "0,1,2,3"
bitfld.long 0x0 10.--11. "CTL5,Pin 5 configuration bits" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CTL4,Pin 4 configuration bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "CTL3,Pin 3 configuration bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "CTL2,Pin 2 configuration bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "CTL1,Pin 1 configuration bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "CTL0,Pin 0 configuration bits" "0,1,2,3"
line.long 0x4 "OMODE,Port output mode register"
bitfld.long 0x4 15. "OM15,Pin 15 output mode bit" "0,1"
bitfld.long 0x4 14. "OM14,Pin 14 output mode bit" "0,1"
bitfld.long 0x4 13. "OM13,Pin 13 output mode bit" "0,1"
bitfld.long 0x4 12. "OM12,Pin 12 output mode bit" "0,1"
bitfld.long 0x4 11. "OM11,Pin 11 output mode bit" "0,1"
bitfld.long 0x4 10. "OM10,Pin 10 output mode bit" "0,1"
bitfld.long 0x4 9. "OM9,Pin 9 output mode bit" "0,1"
bitfld.long 0x4 8. "OM8,Pin 8 output mode bit" "0,1"
bitfld.long 0x4 7. "OM7,Pin 7 output mode bit" "0,1"
bitfld.long 0x4 6. "OM6,Pin 6 output mode bit" "0,1"
bitfld.long 0x4 5. "OM5,Pin 5 output mode bit" "0,1"
newline
bitfld.long 0x4 4. "OM4,Pin 4 output mode bit" "0,1"
bitfld.long 0x4 3. "OM3,Pin 3 output mode bit" "0,1"
bitfld.long 0x4 2. "OM2,Pin 2 output mode bit" "0,1"
bitfld.long 0x4 1. "OM1,Pin 1 output mode bit" "0,1"
bitfld.long 0x4 0. "OM0,Pin 0 output mode bit" "0,1"
line.long 0x8 "OSPD,Port output speed register"
bitfld.long 0x8 30.--31. "OSPD15,Pin 15 output max speed bits" "0,1,2,3"
bitfld.long 0x8 28.--29. "OSPD14,Pin 14 output max speed bits" "0,1,2,3"
bitfld.long 0x8 26.--27. "OSPD13,Pin 13 output max speed bits" "0,1,2,3"
bitfld.long 0x8 24.--25. "OSPD12,Pin 12 output max speed bits" "0,1,2,3"
bitfld.long 0x8 22.--23. "OSPD11,Pin 11 output max speed bits" "0,1,2,3"
bitfld.long 0x8 20.--21. "OSPD10,Pin 10 output max speed bits" "0,1,2,3"
bitfld.long 0x8 18.--19. "OSPD9,Pin 9 output max speed bits" "0,1,2,3"
bitfld.long 0x8 16.--17. "OSPD8,Pin 8 output max speed bits" "0,1,2,3"
bitfld.long 0x8 14.--15. "OSPD7,Pin 7 output max speed bits" "0,1,2,3"
bitfld.long 0x8 12.--13. "OSPD6,Pin 6 output max speed bits" "0,1,2,3"
bitfld.long 0x8 10.--11. "OSPD5,Pin 5 output max speed bits" "0,1,2,3"
newline
bitfld.long 0x8 8.--9. "OSPD4,Pin 4 output max speed bits" "0,1,2,3"
bitfld.long 0x8 6.--7. "OSPD3,Pin 3 output max speed bits" "0,1,2,3"
bitfld.long 0x8 4.--5. "OSPD2,Pin 2 output max speed bits" "0,1,2,3"
bitfld.long 0x8 2.--3. "OSPD1,Pin 1 output max speed bits" "0,1,2,3"
bitfld.long 0x8 0.--1. "OSPD0,Pin 0 output max speed bits" "0,1,2,3"
line.long 0xC "PUD,Port pull-up/down register"
bitfld.long 0xC 30.--31. "PUD15,Pin 15 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 28.--29. "PUD14,Pin 14 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 26.--27. "PUD13,Pin 13 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 24.--25. "PUD12,Pin 12 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 22.--23. "PUD11,Pin 11 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 20.--21. "PUD10,Pin 10 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 18.--19. "PUD9,Pin 9 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 16.--17. "PUD8,Pin 8 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 14.--15. "PUD7,Pin 7 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 12.--13. "PUD6,Pin 6 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 10.--11. "PUD5,Pin 5 pull-up or pull-down bits" "0,1,2,3"
newline
bitfld.long 0xC 8.--9. "PUD4,Pin 4 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 6.--7. "PUD3,Pin 3 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 4.--5. "PUD2,Pin 2 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 2.--3. "PUD1,Pin 1 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 0.--1. "PUD0,Pin 0 pull-up or pull-down bits" "0,1,2,3"
rgroup.long 0x10++0x3
line.long 0x0 "ISTAT,Port input status register"
bitfld.long 0x0 15. "ISTAT15,Port input status" "0,1"
bitfld.long 0x0 14. "ISTAT14,Port input status" "0,1"
bitfld.long 0x0 13. "ISTAT13,Port input status" "0,1"
bitfld.long 0x0 12. "ISTAT12,Port input status" "0,1"
bitfld.long 0x0 11. "ISTAT11,Port input status" "0,1"
bitfld.long 0x0 10. "ISTAT10,Port input status" "0,1"
bitfld.long 0x0 9. "ISTAT9,Port input status" "0,1"
bitfld.long 0x0 8. "ISTAT8,Port input status" "0,1"
bitfld.long 0x0 7. "ISTAT7,Port input status" "0,1"
bitfld.long 0x0 6. "ISTAT6,Port input status" "0,1"
bitfld.long 0x0 5. "ISTAT5,Port input status" "0,1"
newline
bitfld.long 0x0 4. "ISTAT4,Port input status" "0,1"
bitfld.long 0x0 3. "ISTAT3,Port input status" "0,1"
bitfld.long 0x0 2. "ISTAT2,Port input status" "0,1"
bitfld.long 0x0 1. "ISTAT1,Port input status" "0,1"
bitfld.long 0x0 0. "ISTAT0,Port input status" "0,1"
group.long 0x14++0x3
line.long 0x0 "OCTL,Port output control register"
bitfld.long 0x0 15. "OCTL15,Port output control" "0,1"
bitfld.long 0x0 14. "OCTL14,Port output control" "0,1"
bitfld.long 0x0 13. "OCTL13,Port output control" "0,1"
bitfld.long 0x0 12. "OCTL12,Port output control" "0,1"
bitfld.long 0x0 11. "OCTL11,Port output control" "0,1"
bitfld.long 0x0 10. "OCTL10,Port output control" "0,1"
bitfld.long 0x0 9. "OCTL9,Port output control" "0,1"
bitfld.long 0x0 8. "OCTL8,Port output control" "0,1"
bitfld.long 0x0 7. "OCTL7,Port output control" "0,1"
bitfld.long 0x0 6. "OCTL6,Port output control" "0,1"
bitfld.long 0x0 5. "OCTL5,Port output control" "0,1"
newline
bitfld.long 0x0 4. "OCTL4,Port output control" "0,1"
bitfld.long 0x0 3. "OCTL3,Port output control" "0,1"
bitfld.long 0x0 2. "OCTL2,Port output control" "0,1"
bitfld.long 0x0 1. "OCTL1,Port output control" "0,1"
bitfld.long 0x0 0. "OCTL0,Port output control" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "BOP,Port bit operate register"
bitfld.long 0x0 31. "CR15,Port clear bit y" "0,1"
bitfld.long 0x0 30. "CR14,Port clear bit y" "0,1"
bitfld.long 0x0 29. "CR13,Port clear bit y" "0,1"
bitfld.long 0x0 28. "CR12,Port clear bit y" "0,1"
bitfld.long 0x0 27. "CR11,Port clear bit y" "0,1"
bitfld.long 0x0 26. "CR10,Port clear bit y" "0,1"
bitfld.long 0x0 25. "CR9,Port clear bit y" "0,1"
bitfld.long 0x0 24. "CR8,Port clear bit y" "0,1"
bitfld.long 0x0 23. "CR7,Port clear bit y" "0,1"
bitfld.long 0x0 22. "CR6,Port clear bit y" "0,1"
bitfld.long 0x0 21. "CR5,Port clear bit y" "0,1"
newline
bitfld.long 0x0 20. "CR4,Port clear bit y" "0,1"
bitfld.long 0x0 19. "CR3,Port clear bit y" "0,1"
bitfld.long 0x0 18. "CR2,Port clear bit y" "0,1"
bitfld.long 0x0 17. "CR1,Port clear bit y" "0,1"
bitfld.long 0x0 16. "CR0,Port clear bit y" "0,1"
bitfld.long 0x0 15. "BOP15,Port set bit y" "0,1"
bitfld.long 0x0 14. "BOP14,Port set bit y" "0,1"
bitfld.long 0x0 13. "BOP13,Port set bit y" "0,1"
bitfld.long 0x0 12. "BOP12,Port set bit y" "0,1"
bitfld.long 0x0 11. "BOP11,Port set bit y" "0,1"
bitfld.long 0x0 10. "BOP10,Port set bit y" "0,1"
newline
bitfld.long 0x0 9. "BOP9,Port set bit y" "0,1"
bitfld.long 0x0 8. "BOP8,Port set bit y" "0,1"
bitfld.long 0x0 7. "BOP7,Port set bit y" "0,1"
bitfld.long 0x0 6. "BOP6,Port set bit y" "0,1"
bitfld.long 0x0 5. "BOP5,Port set bit y" "0,1"
bitfld.long 0x0 4. "BOP4,Port set bit y" "0,1"
bitfld.long 0x0 3. "BOP3,Port set bit y" "0,1"
bitfld.long 0x0 2. "BOP2,Port set bit y" "0,1"
bitfld.long 0x0 1. "BOP1,Port set bit y" "0,1"
bitfld.long 0x0 0. "BOP0,Port set bit y" "0,1"
group.long 0x1C++0xB
line.long 0x0 "LOCK,Port configuration lock register"
bitfld.long 0x0 16. "LKK,Lock key" "0,1"
bitfld.long 0x0 15. "LK15,LOCK key writing sequence:" "0,1"
bitfld.long 0x0 14. "LK14,Port lock bit y" "0,1"
bitfld.long 0x0 13. "LK13,Port lock bit y" "0,1"
bitfld.long 0x0 12. "LK12,Port lock bit y" "0,1"
bitfld.long 0x0 11. "LK11,Port lock bit y" "0,1"
bitfld.long 0x0 10. "LK10,Port lock bit y" "0,1"
bitfld.long 0x0 9. "LK9,Port lock bit y" "0,1"
bitfld.long 0x0 8. "LK8,Port lock bit y" "0,1"
bitfld.long 0x0 7. "LK7,Port lock bit y" "0,1"
bitfld.long 0x0 6. "LK6,Port lock bit y" "0,1"
newline
bitfld.long 0x0 5. "LK5,Port lock bit y" "0,1"
bitfld.long 0x0 4. "LK4,Port lock bit y" "0,1"
bitfld.long 0x0 3. "LK3,Port lock bit y" "0,1"
bitfld.long 0x0 2. "LK2,Port lock bit y" "0,1"
bitfld.long 0x0 1. "LK1,Port lock bit y" "0,1"
bitfld.long 0x0 0. "LK0,Port lock bit y" "0,1"
line.long 0x4 "AFSEL0,Alternate function selected register 0"
hexmask.long.byte 0x4 28.--31. 1. "SEL7,Pin 7 alternate function selected"
hexmask.long.byte 0x4 24.--27. 1. "SEL6,Pin 6 alternate function selected"
hexmask.long.byte 0x4 20.--23. 1. "SEL5,Pin 5 alternate function selected"
hexmask.long.byte 0x4 16.--19. 1. "SEL4,Pin 4 alternate function selected"
hexmask.long.byte 0x4 12.--15. 1. "SEL3,Pin 3 alternate function selected"
hexmask.long.byte 0x4 8.--11. 1. "SEL2,Pin 2 alternate function selected"
hexmask.long.byte 0x4 4.--7. 1. "SEL1,Pin 1 alternate function selected"
hexmask.long.byte 0x4 0.--3. 1. "SEL0,Pin 0 alternate function selected"
line.long 0x8 "AFSEL1,Alternate function selected register 1"
hexmask.long.byte 0x8 28.--31. 1. "SEL15,Pin 15 alternate function selected"
hexmask.long.byte 0x8 24.--27. 1. "SEL14,Pin 14 alternate function selected"
hexmask.long.byte 0x8 20.--23. 1. "SEL13,Pin 13 alternate function selected"
hexmask.long.byte 0x8 16.--19. 1. "SEL12,Pin 12 alternate function selected"
hexmask.long.byte 0x8 12.--15. 1. "SEL11,Pin 1 alternate function selected"
hexmask.long.byte 0x8 8.--11. 1. "SEL10,Pin 10 alternate function selected"
hexmask.long.byte 0x8 4.--7. 1. "SEL9,Pin 9 alternate function selected"
hexmask.long.byte 0x8 0.--3. 1. "SEL8,Pin 8 alternate function selected"
wgroup.long 0x28++0x7
line.long 0x0 "BC,Bit clear register"
bitfld.long 0x0 15. "CR15,Port clear bit 15" "0,1"
bitfld.long 0x0 14. "CR14,Port clear bit 14" "0,1"
bitfld.long 0x0 13. "CR13,Port clear bit 13" "0,1"
bitfld.long 0x0 12. "CR12,Port clear bit 12" "0,1"
bitfld.long 0x0 11. "CR11,Port clear bit 11" "0,1"
bitfld.long 0x0 10. "CR10,Port clear bit 10" "0,1"
bitfld.long 0x0 9. "CR9,Port clear bit 9" "0,1"
bitfld.long 0x0 8. "CR8,Port clear bit 8" "0,1"
bitfld.long 0x0 7. "CR7,Port clear bit 7" "0,1"
bitfld.long 0x0 6. "CR6,Port clear bit 6" "0,1"
bitfld.long 0x0 5. "CR5,Port clear bit 5" "0,1"
newline
bitfld.long 0x0 4. "CR4,Port clear bit 4" "0,1"
bitfld.long 0x0 3. "CR3,Port clear bit 3" "0,1"
bitfld.long 0x0 2. "CR2,Port clear bit 2" "0,1"
bitfld.long 0x0 1. "CR1,Port clear bit 1" "0,1"
bitfld.long 0x0 0. "CR0,Port clear bit 0" "0,1"
line.long 0x4 "TG,Port bit toggle register"
bitfld.long 0x4 15. "TG15,Port toggle bit 15" "0,1"
bitfld.long 0x4 14. "TG14,Port toggle bit 14" "0,1"
bitfld.long 0x4 13. "TG13,Port toggle bit 13" "0,1"
bitfld.long 0x4 12. "TG12,Port toggle bit 12" "0,1"
bitfld.long 0x4 11. "TG11,Port toggle bit 11" "0,1"
bitfld.long 0x4 10. "TG10,Port toggle bit 10" "0,1"
bitfld.long 0x4 9. "TG9,Port toggle bit 9" "0,1"
bitfld.long 0x4 8. "TG8,Port toggle bit 8" "0,1"
bitfld.long 0x4 7. "TG7,Port toggle bit 7" "0,1"
bitfld.long 0x4 6. "TG6,Port toggle bit 6" "0,1"
bitfld.long 0x4 5. "TG5,Port toggle bit 5" "0,1"
newline
bitfld.long 0x4 4. "TG4,Port toggle bit 4" "0,1"
bitfld.long 0x4 3. "TG3,Port toggle bit 3" "0,1"
bitfld.long 0x4 2. "TG2,Port toggle bit 2" "0,1"
bitfld.long 0x4 1. "TG1,Port toggle bit 1" "0,1"
bitfld.long 0x4 0. "TG0,Port toggle bit 0" "0,1"
group.long 0x30++0x7
line.long 0x0 "IFL,Input filtering register"
hexmask.long.byte 0x0 8.--15. 1. "FLPRD1,Filter sampling period for GPIO8 to GPIO15:"
hexmask.long.byte 0x0 0.--7. 1. "FLPRD0,Filter sampling period for GPIO1 to GPIO7:"
line.long 0x4 "IFTP,Input filtering type register"
bitfld.long 0x4 30.--31. "IFTP15,Pin 15 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 28.--29. "IFTP14,Pin 14 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 26.--27. "IFTP13,Pin 13 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 24.--25. "IFTP12,Pin 12 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 22.--23. "IFTP11,Pin 11 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 20.--21. "IFTP10,Pin 10 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 18.--19. "IFTP9,Pin 9 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 16.--17. "IFTP8,Pin 8 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 14.--15. "IFTP7,Pin 7 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 12.--13. "IFTP6,Pin 6 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 10.--11. "IFTP5,Pin 5 input filtering type bits" "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "IFTP4,Pin 4 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 6.--7. "IFTP3,Pin 3 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 4.--5. "IFTP2,Pin 2 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 2.--3. "IFTP1,Pin 1 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 0.--1. "IFTP0,Pin 0 input filtering type bits" "0,1,2,3"
tree.end
tree "GPIOB"
base ad:0x48000400
group.long 0x0++0xF
line.long 0x0 "CTL,Port control register"
bitfld.long 0x0 30.--31. "CTL15,Pin 15 configuration bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "CTL14,Pin 14 configuration bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "CTL13,Pin 13 configuration bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "CTL12,Pin 12 configuration bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "CTL11,Pin 11 configuration bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "CTL10,Pin 10 configuration bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "CTL9,Pin 9 configuration bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "CTL8,Pin 8 configuration bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "CTL7,Pin 7 configuration bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "CTL6,Pin 6 configuration bits" "0,1,2,3"
bitfld.long 0x0 10.--11. "CTL5,Pin 5 configuration bits" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CTL4,Pin 4 configuration bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "CTL3,Pin 3 configuration bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "CTL2,Pin 2 configuration bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "CTL1,Pin 1 configuration bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "CTL0,Pin 0 configuration bits" "0,1,2,3"
line.long 0x4 "OMODE,Port output mode register"
bitfld.long 0x4 15. "OM15,Pin 15 output mode bit" "0,1"
bitfld.long 0x4 14. "OM14,Pin 14 output mode bit" "0,1"
bitfld.long 0x4 13. "OM13,Pin 13 output mode bit" "0,1"
bitfld.long 0x4 12. "OM12,Pin 12 output mode bit" "0,1"
bitfld.long 0x4 11. "OM11,Pin 11 output mode bit" "0,1"
bitfld.long 0x4 10. "OM10,Pin 10 output mode bit" "0,1"
bitfld.long 0x4 9. "OM9,Pin 9 output mode bit" "0,1"
bitfld.long 0x4 8. "OM8,Pin 8 output mode bit" "0,1"
bitfld.long 0x4 7. "OM7,Pin 7 output mode bit" "0,1"
bitfld.long 0x4 6. "OM6,Pin 6 output mode bit" "0,1"
bitfld.long 0x4 5. "OM5,Pin 5 output mode bit" "0,1"
newline
bitfld.long 0x4 4. "OM4,Pin 4 output mode bit" "0,1"
bitfld.long 0x4 3. "OM3,Pin 3 output mode bit" "0,1"
bitfld.long 0x4 2. "OM2,Pin 2 output mode bit" "0,1"
bitfld.long 0x4 1. "OM1,Pin 1 output mode bit" "0,1"
bitfld.long 0x4 0. "OM0,Pin 0 output mode bit" "0,1"
line.long 0x8 "OSPD,Port output speed register"
bitfld.long 0x8 30.--31. "OSPD15,Pin 15 output max speed bits" "0,1,2,3"
bitfld.long 0x8 28.--29. "OSPD14,Pin 14 output max speed bits" "0,1,2,3"
bitfld.long 0x8 26.--27. "OSPD13,Pin 13 output max speed bits" "0,1,2,3"
bitfld.long 0x8 24.--25. "OSPD12,Pin 12 output max speed bits" "0,1,2,3"
bitfld.long 0x8 22.--23. "OSPD11,Pin 11 output max speed bits" "0,1,2,3"
bitfld.long 0x8 20.--21. "OSPD10,Pin 10 output max speed bits" "0,1,2,3"
bitfld.long 0x8 18.--19. "OSPD9,Pin 9 output max speed bits" "0,1,2,3"
bitfld.long 0x8 16.--17. "OSPD8,Pin 8 output max speed bits" "0,1,2,3"
bitfld.long 0x8 14.--15. "OSPD7,Pin 7 output max speed bits" "0,1,2,3"
bitfld.long 0x8 12.--13. "OSPD6,Pin 6 output max speed bits" "0,1,2,3"
bitfld.long 0x8 10.--11. "OSPD5,Pin 5 output max speed bits" "0,1,2,3"
newline
bitfld.long 0x8 8.--9. "OSPD4,Pin 4 output max speed bits" "0,1,2,3"
bitfld.long 0x8 6.--7. "OSPD3,Pin 3 output max speed bits" "0,1,2,3"
bitfld.long 0x8 4.--5. "OSPD2,Pin 2 output max speed bits" "0,1,2,3"
bitfld.long 0x8 2.--3. "OSPD1,Pin 1 output max speed bits" "0,1,2,3"
bitfld.long 0x8 0.--1. "OSPD0,Pin 0 output max speed bits" "0,1,2,3"
line.long 0xC "PUD,Port pull-up/down register"
bitfld.long 0xC 30.--31. "PUD15,Pin 15 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 28.--29. "PUD14,Pin 14 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 26.--27. "PUD13,Pin 13 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 24.--25. "PUD12,Pin 12 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 22.--23. "PUD11,Pin 11 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 20.--21. "PUD10,Pin 10 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 18.--19. "PUD9,Pin 9 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 16.--17. "PUD8,Pin 8 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 14.--15. "PUD7,Pin 7 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 12.--13. "PUD6,Pin 6 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 10.--11. "PUD5,Pin 5 pull-up or pull-down bits" "0,1,2,3"
newline
bitfld.long 0xC 8.--9. "PUD4,Pin 4 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 6.--7. "PUD3,Pin 3 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 4.--5. "PUD2,Pin 2 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 2.--3. "PUD1,Pin 1 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 0.--1. "PUD0,Pin 0 pull-up or pull-down bits" "0,1,2,3"
rgroup.long 0x10++0x3
line.long 0x0 "ISTAT,Port input status register"
bitfld.long 0x0 15. "ISTAT15,Port input status" "0,1"
bitfld.long 0x0 14. "ISTAT14,Port input status" "0,1"
bitfld.long 0x0 13. "ISTAT13,Port input status" "0,1"
bitfld.long 0x0 12. "ISTAT12,Port input status" "0,1"
bitfld.long 0x0 11. "ISTAT11,Port input status" "0,1"
bitfld.long 0x0 10. "ISTAT10,Port input status" "0,1"
bitfld.long 0x0 9. "ISTAT9,Port input status" "0,1"
bitfld.long 0x0 8. "ISTAT8,Port input status" "0,1"
bitfld.long 0x0 7. "ISTAT7,Port input status" "0,1"
bitfld.long 0x0 6. "ISTAT6,Port input status" "0,1"
bitfld.long 0x0 5. "ISTAT5,Port input status" "0,1"
newline
bitfld.long 0x0 4. "ISTAT4,Port input status" "0,1"
bitfld.long 0x0 3. "ISTAT3,Port input status" "0,1"
bitfld.long 0x0 2. "ISTAT2,Port input status" "0,1"
bitfld.long 0x0 1. "ISTAT1,Port input status" "0,1"
bitfld.long 0x0 0. "ISTAT0,Port input status" "0,1"
group.long 0x14++0x3
line.long 0x0 "OCTL,Port output control register"
bitfld.long 0x0 15. "OCTL15,Port output control" "0,1"
bitfld.long 0x0 14. "OCTL14,Port output control" "0,1"
bitfld.long 0x0 13. "OCTL13,Port output control" "0,1"
bitfld.long 0x0 12. "OCTL12,Port output control" "0,1"
bitfld.long 0x0 11. "OCTL11,Port output control" "0,1"
bitfld.long 0x0 10. "OCTL10,Port output control" "0,1"
bitfld.long 0x0 9. "OCTL9,Port output control" "0,1"
bitfld.long 0x0 8. "OCTL8,Port output control" "0,1"
bitfld.long 0x0 7. "OCTL7,Port output control" "0,1"
bitfld.long 0x0 6. "OCTL6,Port output control" "0,1"
bitfld.long 0x0 5. "OCTL5,Port output control" "0,1"
newline
bitfld.long 0x0 4. "OCTL4,Port output control" "0,1"
bitfld.long 0x0 3. "OCTL3,Port output control" "0,1"
bitfld.long 0x0 2. "OCTL2,Port output control" "0,1"
bitfld.long 0x0 1. "OCTL1,Port output control" "0,1"
bitfld.long 0x0 0. "OCTL0,Port output control" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "BOP,Port bit operate register"
bitfld.long 0x0 31. "CR15,Port clear bit y" "0,1"
bitfld.long 0x0 30. "CR14,Port clear bit y" "0,1"
bitfld.long 0x0 29. "CR13,Port clear bit y" "0,1"
bitfld.long 0x0 28. "CR12,Port clear bit y" "0,1"
bitfld.long 0x0 27. "CR11,Port clear bit y" "0,1"
bitfld.long 0x0 26. "CR10,Port clear bit y" "0,1"
bitfld.long 0x0 25. "CR9,Port clear bit y" "0,1"
bitfld.long 0x0 24. "CR8,Port clear bit y" "0,1"
bitfld.long 0x0 23. "CR7,Port clear bit y" "0,1"
bitfld.long 0x0 22. "CR6,Port clear bit y" "0,1"
bitfld.long 0x0 21. "CR5,Port clear bit y" "0,1"
newline
bitfld.long 0x0 20. "CR4,Port clear bit y" "0,1"
bitfld.long 0x0 19. "CR3,Port clear bit y" "0,1"
bitfld.long 0x0 18. "CR2,Port clear bit y" "0,1"
bitfld.long 0x0 17. "CR1,Port clear bit y" "0,1"
bitfld.long 0x0 16. "CR0,Port clear bit y" "0,1"
bitfld.long 0x0 15. "BOP15,Port set bit y" "0,1"
bitfld.long 0x0 14. "BOP14,Port set bit y" "0,1"
bitfld.long 0x0 13. "BOP13,Port set bit y" "0,1"
bitfld.long 0x0 12. "BOP12,Port set bit y" "0,1"
bitfld.long 0x0 11. "BOP11,Port set bit y" "0,1"
bitfld.long 0x0 10. "BOP10,Port set bit y" "0,1"
newline
bitfld.long 0x0 9. "BOP9,Port set bit y" "0,1"
bitfld.long 0x0 8. "BOP8,Port set bit y" "0,1"
bitfld.long 0x0 7. "BOP7,Port set bit y" "0,1"
bitfld.long 0x0 6. "BOP6,Port set bit y" "0,1"
bitfld.long 0x0 5. "BOP5,Port set bit y" "0,1"
bitfld.long 0x0 4. "BOP4,Port set bit y" "0,1"
bitfld.long 0x0 3. "BOP3,Port set bit y" "0,1"
bitfld.long 0x0 2. "BOP2,Port set bit y" "0,1"
bitfld.long 0x0 1. "BOP1,Port set bit y" "0,1"
bitfld.long 0x0 0. "BOP0,Port set bit y" "0,1"
group.long 0x1C++0xB
line.long 0x0 "LOCK,Port configuration lock register"
bitfld.long 0x0 16. "LKK,Lock key" "0,1"
bitfld.long 0x0 15. "LK15,LOCK key writing sequence:" "0,1"
bitfld.long 0x0 14. "LK14,Port lock bit y" "0,1"
bitfld.long 0x0 13. "LK13,Port lock bit y" "0,1"
bitfld.long 0x0 12. "LK12,Port lock bit y" "0,1"
bitfld.long 0x0 11. "LK11,Port lock bit y" "0,1"
bitfld.long 0x0 10. "LK10,Port lock bit y" "0,1"
bitfld.long 0x0 9. "LK9,Port lock bit y" "0,1"
bitfld.long 0x0 8. "LK8,Port lock bit y" "0,1"
bitfld.long 0x0 7. "LK7,Port lock bit y" "0,1"
bitfld.long 0x0 6. "LK6,Port lock bit y" "0,1"
newline
bitfld.long 0x0 5. "LK5,Port lock bit y" "0,1"
bitfld.long 0x0 4. "LK4,Port lock bit y" "0,1"
bitfld.long 0x0 3. "LK3,Port lock bit y" "0,1"
bitfld.long 0x0 2. "LK2,Port lock bit y" "0,1"
bitfld.long 0x0 1. "LK1,Port lock bit y" "0,1"
bitfld.long 0x0 0. "LK0,Port lock bit y" "0,1"
line.long 0x4 "AFSEL0,Alternate function selected register 0"
hexmask.long.byte 0x4 28.--31. 1. "SEL7,Pin 7 alternate function selected"
hexmask.long.byte 0x4 24.--27. 1. "SEL6,Pin 6 alternate function selected"
hexmask.long.byte 0x4 20.--23. 1. "SEL5,Pin 5 alternate function selected"
hexmask.long.byte 0x4 16.--19. 1. "SEL4,Pin 4 alternate function selected"
hexmask.long.byte 0x4 12.--15. 1. "SEL3,Pin 3 alternate function selected"
hexmask.long.byte 0x4 8.--11. 1. "SEL2,Pin 2 alternate function selected"
hexmask.long.byte 0x4 4.--7. 1. "SEL1,Pin 1 alternate function selected"
hexmask.long.byte 0x4 0.--3. 1. "SEL0,Pin 0 alternate function selected"
line.long 0x8 "AFSEL1,Alternate function selected register 1"
hexmask.long.byte 0x8 28.--31. 1. "SEL15,Pin 15 alternate function selected"
hexmask.long.byte 0x8 24.--27. 1. "SEL14,Pin 14 alternate function selected"
hexmask.long.byte 0x8 20.--23. 1. "SEL13,Pin 13 alternate function selected"
hexmask.long.byte 0x8 16.--19. 1. "SEL12,Pin 12 alternate function selected"
hexmask.long.byte 0x8 12.--15. 1. "SEL11,Pin 1 alternate function selected"
hexmask.long.byte 0x8 8.--11. 1. "SEL10,Pin 10 alternate function selected"
hexmask.long.byte 0x8 4.--7. 1. "SEL9,Pin 9 alternate function selected"
hexmask.long.byte 0x8 0.--3. 1. "SEL8,Pin 8 alternate function selected"
wgroup.long 0x28++0x7
line.long 0x0 "BC,Bit clear register"
bitfld.long 0x0 15. "CR15,Port clear bit 15" "0,1"
bitfld.long 0x0 14. "CR14,Port clear bit 14" "0,1"
bitfld.long 0x0 13. "CR13,Port clear bit 13" "0,1"
bitfld.long 0x0 12. "CR12,Port clear bit 12" "0,1"
bitfld.long 0x0 11. "CR11,Port clear bit 11" "0,1"
bitfld.long 0x0 10. "CR10,Port clear bit 10" "0,1"
bitfld.long 0x0 9. "CR9,Port clear bit 9" "0,1"
bitfld.long 0x0 8. "CR8,Port clear bit 8" "0,1"
bitfld.long 0x0 7. "CR7,Port clear bit 7" "0,1"
bitfld.long 0x0 6. "CR6,Port clear bit 6" "0,1"
bitfld.long 0x0 5. "CR5,Port clear bit 5" "0,1"
newline
bitfld.long 0x0 4. "CR4,Port clear bit 4" "0,1"
bitfld.long 0x0 3. "CR3,Port clear bit 3" "0,1"
bitfld.long 0x0 2. "CR2,Port clear bit 2" "0,1"
bitfld.long 0x0 1. "CR1,Port clear bit 1" "0,1"
bitfld.long 0x0 0. "CR0,Port clear bit 0" "0,1"
line.long 0x4 "TG,Port bit toggle register"
bitfld.long 0x4 15. "TG15,Port toggle bit 15" "0,1"
bitfld.long 0x4 14. "TG14,Port toggle bit 14" "0,1"
bitfld.long 0x4 13. "TG13,Port toggle bit 13" "0,1"
bitfld.long 0x4 12. "TG12,Port toggle bit 12" "0,1"
bitfld.long 0x4 11. "TG11,Port toggle bit 11" "0,1"
bitfld.long 0x4 10. "TG10,Port toggle bit 10" "0,1"
bitfld.long 0x4 9. "TG9,Port toggle bit 9" "0,1"
bitfld.long 0x4 8. "TG8,Port toggle bit 8" "0,1"
bitfld.long 0x4 7. "TG7,Port toggle bit 7" "0,1"
bitfld.long 0x4 6. "TG6,Port toggle bit 6" "0,1"
bitfld.long 0x4 5. "TG5,Port toggle bit 5" "0,1"
newline
bitfld.long 0x4 4. "TG4,Port toggle bit 4" "0,1"
bitfld.long 0x4 3. "TG3,Port toggle bit 3" "0,1"
bitfld.long 0x4 2. "TG2,Port toggle bit 2" "0,1"
bitfld.long 0x4 1. "TG1,Port toggle bit 1" "0,1"
bitfld.long 0x4 0. "TG0,Port toggle bit 0" "0,1"
group.long 0x30++0x7
line.long 0x0 "IFL,Input filtering register"
hexmask.long.byte 0x0 8.--15. 1. "FLPRD1,Filter sampling period for GPIO8 to GPIO15:"
hexmask.long.byte 0x0 0.--7. 1. "FLPRD0,Filter sampling period for GPIO1 to GPIO7:"
line.long 0x4 "IFTP,Input filtering type register"
bitfld.long 0x4 30.--31. "IFTP15,Pin 15 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 28.--29. "IFTP14,Pin 14 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 26.--27. "IFTP13,Pin 13 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 24.--25. "IFTP12,Pin 12 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 22.--23. "IFTP11,Pin 11 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 20.--21. "IFTP10,Pin 10 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 18.--19. "IFTP9,Pin 9 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 16.--17. "IFTP8,Pin 8 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 14.--15. "IFTP7,Pin 7 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 12.--13. "IFTP6,Pin 6 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 10.--11. "IFTP5,Pin 5 input filtering type bits" "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "IFTP4,Pin 4 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 6.--7. "IFTP3,Pin 3 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 4.--5. "IFTP2,Pin 2 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 2.--3. "IFTP1,Pin 1 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 0.--1. "IFTP0,Pin 0 input filtering type bits" "0,1,2,3"
tree.end
tree "GPIOC"
base ad:0x48000800
group.long 0x0++0xF
line.long 0x0 "CTL,Port control register"
bitfld.long 0x0 30.--31. "CTL15,Pin 15 configuration bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "CTL14,Pin 14 configuration bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "CTL13,Pin 13 configuration bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "CTL12,Pin 12 configuration bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "CTL11,Pin 11 configuration bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "CTL10,Pin 10 configuration bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "CTL9,Pin 9 configuration bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "CTL8,Pin 8 configuration bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "CTL7,Pin 7 configuration bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "CTL6,Pin 6 configuration bits" "0,1,2,3"
bitfld.long 0x0 10.--11. "CTL5,Pin 5 configuration bits" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CTL4,Pin 4 configuration bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "CTL3,Pin 3 configuration bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "CTL2,Pin 2 configuration bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "CTL1,Pin 1 configuration bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "CTL0,Pin 0 configuration bits" "0,1,2,3"
line.long 0x4 "OMODE,Port output mode register"
bitfld.long 0x4 15. "OM15,Pin 15 output mode bit" "0,1"
bitfld.long 0x4 14. "OM14,Pin 14 output mode bit" "0,1"
bitfld.long 0x4 13. "OM13,Pin 13 output mode bit" "0,1"
bitfld.long 0x4 12. "OM12,Pin 12 output mode bit" "0,1"
bitfld.long 0x4 11. "OM11,Pin 11 output mode bit" "0,1"
bitfld.long 0x4 10. "OM10,Pin 10 output mode bit" "0,1"
bitfld.long 0x4 9. "OM9,Pin 9 output mode bit" "0,1"
bitfld.long 0x4 8. "OM8,Pin 8 output mode bit" "0,1"
bitfld.long 0x4 7. "OM7,Pin 7 output mode bit" "0,1"
bitfld.long 0x4 6. "OM6,Pin 6 output mode bit" "0,1"
bitfld.long 0x4 5. "OM5,Pin 5 output mode bit" "0,1"
newline
bitfld.long 0x4 4. "OM4,Pin 4 output mode bit" "0,1"
bitfld.long 0x4 3. "OM3,Pin 3 output mode bit" "0,1"
bitfld.long 0x4 2. "OM2,Pin 2 output mode bit" "0,1"
bitfld.long 0x4 1. "OM1,Pin 1 output mode bit" "0,1"
bitfld.long 0x4 0. "OM0,Pin 0 output mode bit" "0,1"
line.long 0x8 "OSPD,Port output speed register"
bitfld.long 0x8 30.--31. "OSPD15,Pin 15 output max speed bits" "0,1,2,3"
bitfld.long 0x8 28.--29. "OSPD14,Pin 14 output max speed bits" "0,1,2,3"
bitfld.long 0x8 26.--27. "OSPD13,Pin 13 output max speed bits" "0,1,2,3"
bitfld.long 0x8 24.--25. "OSPD12,Pin 12 output max speed bits" "0,1,2,3"
bitfld.long 0x8 22.--23. "OSPD11,Pin 11 output max speed bits" "0,1,2,3"
bitfld.long 0x8 20.--21. "OSPD10,Pin 10 output max speed bits" "0,1,2,3"
bitfld.long 0x8 18.--19. "OSPD9,Pin 9 output max speed bits" "0,1,2,3"
bitfld.long 0x8 16.--17. "OSPD8,Pin 8 output max speed bits" "0,1,2,3"
bitfld.long 0x8 14.--15. "OSPD7,Pin 7 output max speed bits" "0,1,2,3"
bitfld.long 0x8 12.--13. "OSPD6,Pin 6 output max speed bits" "0,1,2,3"
bitfld.long 0x8 10.--11. "OSPD5,Pin 5 output max speed bits" "0,1,2,3"
newline
bitfld.long 0x8 8.--9. "OSPD4,Pin 4 output max speed bits" "0,1,2,3"
bitfld.long 0x8 6.--7. "OSPD3,Pin 3 output max speed bits" "0,1,2,3"
bitfld.long 0x8 4.--5. "OSPD2,Pin 2 output max speed bits" "0,1,2,3"
bitfld.long 0x8 2.--3. "OSPD1,Pin 1 output max speed bits" "0,1,2,3"
bitfld.long 0x8 0.--1. "OSPD0,Pin 0 output max speed bits" "0,1,2,3"
line.long 0xC "PUD,Port pull-up/down register"
bitfld.long 0xC 30.--31. "PUD15,Pin 15 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 28.--29. "PUD14,Pin 14 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 26.--27. "PUD13,Pin 13 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 24.--25. "PUD12,Pin 12 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 22.--23. "PUD11,Pin 11 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 20.--21. "PUD10,Pin 10 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 18.--19. "PUD9,Pin 9 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 16.--17. "PUD8,Pin 8 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 14.--15. "PUD7,Pin 7 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 12.--13. "PUD6,Pin 6 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 10.--11. "PUD5,Pin 5 pull-up or pull-down bits" "0,1,2,3"
newline
bitfld.long 0xC 8.--9. "PUD4,Pin 4 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 6.--7. "PUD3,Pin 3 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 4.--5. "PUD2,Pin 2 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 2.--3. "PUD1,Pin 1 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 0.--1. "PUD0,Pin 0 pull-up or pull-down bits" "0,1,2,3"
rgroup.long 0x10++0x3
line.long 0x0 "ISTAT,Port input status register"
bitfld.long 0x0 15. "ISTAT15,Port input status" "0,1"
bitfld.long 0x0 14. "ISTAT14,Port input status" "0,1"
bitfld.long 0x0 13. "ISTAT13,Port input status" "0,1"
bitfld.long 0x0 12. "ISTAT12,Port input status" "0,1"
bitfld.long 0x0 11. "ISTAT11,Port input status" "0,1"
bitfld.long 0x0 10. "ISTAT10,Port input status" "0,1"
bitfld.long 0x0 9. "ISTAT9,Port input status" "0,1"
bitfld.long 0x0 8. "ISTAT8,Port input status" "0,1"
bitfld.long 0x0 7. "ISTAT7,Port input status" "0,1"
bitfld.long 0x0 6. "ISTAT6,Port input status" "0,1"
bitfld.long 0x0 5. "ISTAT5,Port input status" "0,1"
newline
bitfld.long 0x0 4. "ISTAT4,Port input status" "0,1"
bitfld.long 0x0 3. "ISTAT3,Port input status" "0,1"
bitfld.long 0x0 2. "ISTAT2,Port input status" "0,1"
bitfld.long 0x0 1. "ISTAT1,Port input status" "0,1"
bitfld.long 0x0 0. "ISTAT0,Port input status" "0,1"
group.long 0x14++0x3
line.long 0x0 "OCTL,Port output control register"
bitfld.long 0x0 15. "OCTL15,Port output control" "0,1"
bitfld.long 0x0 14. "OCTL14,Port output control" "0,1"
bitfld.long 0x0 13. "OCTL13,Port output control" "0,1"
bitfld.long 0x0 12. "OCTL12,Port output control" "0,1"
bitfld.long 0x0 11. "OCTL11,Port output control" "0,1"
bitfld.long 0x0 10. "OCTL10,Port output control" "0,1"
bitfld.long 0x0 9. "OCTL9,Port output control" "0,1"
bitfld.long 0x0 8. "OCTL8,Port output control" "0,1"
bitfld.long 0x0 7. "OCTL7,Port output control" "0,1"
bitfld.long 0x0 6. "OCTL6,Port output control" "0,1"
bitfld.long 0x0 5. "OCTL5,Port output control" "0,1"
newline
bitfld.long 0x0 4. "OCTL4,Port output control" "0,1"
bitfld.long 0x0 3. "OCTL3,Port output control" "0,1"
bitfld.long 0x0 2. "OCTL2,Port output control" "0,1"
bitfld.long 0x0 1. "OCTL1,Port output control" "0,1"
bitfld.long 0x0 0. "OCTL0,Port output control" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "BOP,Port bit operate register"
bitfld.long 0x0 31. "CR15,Port clear bit y" "0,1"
bitfld.long 0x0 30. "CR14,Port clear bit y" "0,1"
bitfld.long 0x0 29. "CR13,Port clear bit y" "0,1"
bitfld.long 0x0 28. "CR12,Port clear bit y" "0,1"
bitfld.long 0x0 27. "CR11,Port clear bit y" "0,1"
bitfld.long 0x0 26. "CR10,Port clear bit y" "0,1"
bitfld.long 0x0 25. "CR9,Port clear bit y" "0,1"
bitfld.long 0x0 24. "CR8,Port clear bit y" "0,1"
bitfld.long 0x0 23. "CR7,Port clear bit y" "0,1"
bitfld.long 0x0 22. "CR6,Port clear bit y" "0,1"
bitfld.long 0x0 21. "CR5,Port clear bit y" "0,1"
newline
bitfld.long 0x0 20. "CR4,Port clear bit y" "0,1"
bitfld.long 0x0 19. "CR3,Port clear bit y" "0,1"
bitfld.long 0x0 18. "CR2,Port clear bit y" "0,1"
bitfld.long 0x0 17. "CR1,Port clear bit y" "0,1"
bitfld.long 0x0 16. "CR0,Port clear bit y" "0,1"
bitfld.long 0x0 15. "BOP15,Port set bit y" "0,1"
bitfld.long 0x0 14. "BOP14,Port set bit y" "0,1"
bitfld.long 0x0 13. "BOP13,Port set bit y" "0,1"
bitfld.long 0x0 12. "BOP12,Port set bit y" "0,1"
bitfld.long 0x0 11. "BOP11,Port set bit y" "0,1"
bitfld.long 0x0 10. "BOP10,Port set bit y" "0,1"
newline
bitfld.long 0x0 9. "BOP9,Port set bit y" "0,1"
bitfld.long 0x0 8. "BOP8,Port set bit y" "0,1"
bitfld.long 0x0 7. "BOP7,Port set bit y" "0,1"
bitfld.long 0x0 6. "BOP6,Port set bit y" "0,1"
bitfld.long 0x0 5. "BOP5,Port set bit y" "0,1"
bitfld.long 0x0 4. "BOP4,Port set bit y" "0,1"
bitfld.long 0x0 3. "BOP3,Port set bit y" "0,1"
bitfld.long 0x0 2. "BOP2,Port set bit y" "0,1"
bitfld.long 0x0 1. "BOP1,Port set bit y" "0,1"
bitfld.long 0x0 0. "BOP0,Port set bit y" "0,1"
group.long 0x1C++0xB
line.long 0x0 "LOCK,Port configuration lock register"
bitfld.long 0x0 16. "LKK,Lock key" "0,1"
bitfld.long 0x0 15. "LK15,LOCK key writing sequence:" "0,1"
bitfld.long 0x0 14. "LK14,Port lock bit y" "0,1"
bitfld.long 0x0 13. "LK13,Port lock bit y" "0,1"
bitfld.long 0x0 12. "LK12,Port lock bit y" "0,1"
bitfld.long 0x0 11. "LK11,Port lock bit y" "0,1"
bitfld.long 0x0 10. "LK10,Port lock bit y" "0,1"
bitfld.long 0x0 9. "LK9,Port lock bit y" "0,1"
bitfld.long 0x0 8. "LK8,Port lock bit y" "0,1"
bitfld.long 0x0 7. "LK7,Port lock bit y" "0,1"
bitfld.long 0x0 6. "LK6,Port lock bit y" "0,1"
newline
bitfld.long 0x0 5. "LK5,Port lock bit y" "0,1"
bitfld.long 0x0 4. "LK4,Port lock bit y" "0,1"
bitfld.long 0x0 3. "LK3,Port lock bit y" "0,1"
bitfld.long 0x0 2. "LK2,Port lock bit y" "0,1"
bitfld.long 0x0 1. "LK1,Port lock bit y" "0,1"
bitfld.long 0x0 0. "LK0,Port lock bit y" "0,1"
line.long 0x4 "AFSEL0,Alternate function selected register 0"
hexmask.long.byte 0x4 28.--31. 1. "SEL7,Pin 7 alternate function selected"
hexmask.long.byte 0x4 24.--27. 1. "SEL6,Pin 6 alternate function selected"
hexmask.long.byte 0x4 20.--23. 1. "SEL5,Pin 5 alternate function selected"
hexmask.long.byte 0x4 16.--19. 1. "SEL4,Pin 4 alternate function selected"
hexmask.long.byte 0x4 12.--15. 1. "SEL3,Pin 3 alternate function selected"
hexmask.long.byte 0x4 8.--11. 1. "SEL2,Pin 2 alternate function selected"
hexmask.long.byte 0x4 4.--7. 1. "SEL1,Pin 1 alternate function selected"
hexmask.long.byte 0x4 0.--3. 1. "SEL0,Pin 0 alternate function selected"
line.long 0x8 "AFSEL1,Alternate function selected register 1"
hexmask.long.byte 0x8 28.--31. 1. "SEL15,Pin 15 alternate function selected"
hexmask.long.byte 0x8 24.--27. 1. "SEL14,Pin 14 alternate function selected"
hexmask.long.byte 0x8 20.--23. 1. "SEL13,Pin 13 alternate function selected"
hexmask.long.byte 0x8 16.--19. 1. "SEL12,Pin 12 alternate function selected"
hexmask.long.byte 0x8 12.--15. 1. "SEL11,Pin 1 alternate function selected"
hexmask.long.byte 0x8 8.--11. 1. "SEL10,Pin 10 alternate function selected"
hexmask.long.byte 0x8 4.--7. 1. "SEL9,Pin 9 alternate function selected"
hexmask.long.byte 0x8 0.--3. 1. "SEL8,Pin 8 alternate function selected"
wgroup.long 0x28++0x7
line.long 0x0 "BC,Bit clear register"
bitfld.long 0x0 15. "CR15,Port clear bit 15" "0,1"
bitfld.long 0x0 14. "CR14,Port clear bit 14" "0,1"
bitfld.long 0x0 13. "CR13,Port clear bit 13" "0,1"
bitfld.long 0x0 12. "CR12,Port clear bit 12" "0,1"
bitfld.long 0x0 11. "CR11,Port clear bit 11" "0,1"
bitfld.long 0x0 10. "CR10,Port clear bit 10" "0,1"
bitfld.long 0x0 9. "CR9,Port clear bit 9" "0,1"
bitfld.long 0x0 8. "CR8,Port clear bit 8" "0,1"
bitfld.long 0x0 7. "CR7,Port clear bit 7" "0,1"
bitfld.long 0x0 6. "CR6,Port clear bit 6" "0,1"
bitfld.long 0x0 5. "CR5,Port clear bit 5" "0,1"
newline
bitfld.long 0x0 4. "CR4,Port clear bit 4" "0,1"
bitfld.long 0x0 3. "CR3,Port clear bit 3" "0,1"
bitfld.long 0x0 2. "CR2,Port clear bit 2" "0,1"
bitfld.long 0x0 1. "CR1,Port clear bit 1" "0,1"
bitfld.long 0x0 0. "CR0,Port clear bit 0" "0,1"
line.long 0x4 "TG,Port bit toggle register"
bitfld.long 0x4 15. "TG15,Port toggle bit 15" "0,1"
bitfld.long 0x4 14. "TG14,Port toggle bit 14" "0,1"
bitfld.long 0x4 13. "TG13,Port toggle bit 13" "0,1"
bitfld.long 0x4 12. "TG12,Port toggle bit 12" "0,1"
bitfld.long 0x4 11. "TG11,Port toggle bit 11" "0,1"
bitfld.long 0x4 10. "TG10,Port toggle bit 10" "0,1"
bitfld.long 0x4 9. "TG9,Port toggle bit 9" "0,1"
bitfld.long 0x4 8. "TG8,Port toggle bit 8" "0,1"
bitfld.long 0x4 7. "TG7,Port toggle bit 7" "0,1"
bitfld.long 0x4 6. "TG6,Port toggle bit 6" "0,1"
bitfld.long 0x4 5. "TG5,Port toggle bit 5" "0,1"
newline
bitfld.long 0x4 4. "TG4,Port toggle bit 4" "0,1"
bitfld.long 0x4 3. "TG3,Port toggle bit 3" "0,1"
bitfld.long 0x4 2. "TG2,Port toggle bit 2" "0,1"
bitfld.long 0x4 1. "TG1,Port toggle bit 1" "0,1"
bitfld.long 0x4 0. "TG0,Port toggle bit 0" "0,1"
group.long 0x30++0x7
line.long 0x0 "IFL,Input filtering register"
hexmask.long.byte 0x0 8.--15. 1. "FLPRD1,Filter sampling period for GPIO8 to GPIO15:"
hexmask.long.byte 0x0 0.--7. 1. "FLPRD0,Filter sampling period for GPIO1 to GPIO7:"
line.long 0x4 "IFTP,Input filtering type register"
bitfld.long 0x4 30.--31. "IFTP15,Pin 15 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 28.--29. "IFTP14,Pin 14 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 26.--27. "IFTP13,Pin 13 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 24.--25. "IFTP12,Pin 12 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 22.--23. "IFTP11,Pin 11 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 20.--21. "IFTP10,Pin 10 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 18.--19. "IFTP9,Pin 9 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 16.--17. "IFTP8,Pin 8 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 14.--15. "IFTP7,Pin 7 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 12.--13. "IFTP6,Pin 6 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 10.--11. "IFTP5,Pin 5 input filtering type bits" "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "IFTP4,Pin 4 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 6.--7. "IFTP3,Pin 3 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 4.--5. "IFTP2,Pin 2 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 2.--3. "IFTP1,Pin 1 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 0.--1. "IFTP0,Pin 0 input filtering type bits" "0,1,2,3"
tree.end
tree "GPIOD"
base ad:0x48000C00
group.long 0x0++0xF
line.long 0x0 "CTL,Port control register"
bitfld.long 0x0 30.--31. "CTL15,Pin 15 configuration bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "CTL14,Pin 14 configuration bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "CTL13,Pin 13 configuration bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "CTL12,Pin 12 configuration bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "CTL11,Pin 11 configuration bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "CTL10,Pin 10 configuration bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "CTL9,Pin 9 configuration bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "CTL8,Pin 8 configuration bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "CTL7,Pin 7 configuration bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "CTL6,Pin 6 configuration bits" "0,1,2,3"
bitfld.long 0x0 10.--11. "CTL5,Pin 5 configuration bits" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CTL4,Pin 4 configuration bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "CTL3,Pin 3 configuration bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "CTL2,Pin 2 configuration bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "CTL1,Pin 1 configuration bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "CTL0,Pin 0 configuration bits" "0,1,2,3"
line.long 0x4 "OMODE,Port output mode register"
bitfld.long 0x4 15. "OM15,Pin 15 output mode bit" "0,1"
bitfld.long 0x4 14. "OM14,Pin 14 output mode bit" "0,1"
bitfld.long 0x4 13. "OM13,Pin 13 output mode bit" "0,1"
bitfld.long 0x4 12. "OM12,Pin 12 output mode bit" "0,1"
bitfld.long 0x4 11. "OM11,Pin 11 output mode bit" "0,1"
bitfld.long 0x4 10. "OM10,Pin 10 output mode bit" "0,1"
bitfld.long 0x4 9. "OM9,Pin 9 output mode bit" "0,1"
bitfld.long 0x4 8. "OM8,Pin 8 output mode bit" "0,1"
bitfld.long 0x4 7. "OM7,Pin 7 output mode bit" "0,1"
bitfld.long 0x4 6. "OM6,Pin 6 output mode bit" "0,1"
bitfld.long 0x4 5. "OM5,Pin 5 output mode bit" "0,1"
newline
bitfld.long 0x4 4. "OM4,Pin 4 output mode bit" "0,1"
bitfld.long 0x4 3. "OM3,Pin 3 output mode bit" "0,1"
bitfld.long 0x4 2. "OM2,Pin 2 output mode bit" "0,1"
bitfld.long 0x4 1. "OM1,Pin 1 output mode bit" "0,1"
bitfld.long 0x4 0. "OM0,Pin 0 output mode bit" "0,1"
line.long 0x8 "OSPD,Port output speed register"
bitfld.long 0x8 30.--31. "OSPD15,Pin 15 output max speed bits" "0,1,2,3"
bitfld.long 0x8 28.--29. "OSPD14,Pin 14 output max speed bits" "0,1,2,3"
bitfld.long 0x8 26.--27. "OSPD13,Pin 13 output max speed bits" "0,1,2,3"
bitfld.long 0x8 24.--25. "OSPD12,Pin 12 output max speed bits" "0,1,2,3"
bitfld.long 0x8 22.--23. "OSPD11,Pin 11 output max speed bits" "0,1,2,3"
bitfld.long 0x8 20.--21. "OSPD10,Pin 10 output max speed bits" "0,1,2,3"
bitfld.long 0x8 18.--19. "OSPD9,Pin 9 output max speed bits" "0,1,2,3"
bitfld.long 0x8 16.--17. "OSPD8,Pin 8 output max speed bits" "0,1,2,3"
bitfld.long 0x8 14.--15. "OSPD7,Pin 7 output max speed bits" "0,1,2,3"
bitfld.long 0x8 12.--13. "OSPD6,Pin 6 output max speed bits" "0,1,2,3"
bitfld.long 0x8 10.--11. "OSPD5,Pin 5 output max speed bits" "0,1,2,3"
newline
bitfld.long 0x8 8.--9. "OSPD4,Pin 4 output max speed bits" "0,1,2,3"
bitfld.long 0x8 6.--7. "OSPD3,Pin 3 output max speed bits" "0,1,2,3"
bitfld.long 0x8 4.--5. "OSPD2,Pin 2 output max speed bits" "0,1,2,3"
bitfld.long 0x8 2.--3. "OSPD1,Pin 1 output max speed bits" "0,1,2,3"
bitfld.long 0x8 0.--1. "OSPD0,Pin 0 output max speed bits" "0,1,2,3"
line.long 0xC "PUD,Port pull-up/down register"
bitfld.long 0xC 30.--31. "PUD15,Pin 15 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 28.--29. "PUD14,Pin 14 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 26.--27. "PUD13,Pin 13 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 24.--25. "PUD12,Pin 12 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 22.--23. "PUD11,Pin 11 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 20.--21. "PUD10,Pin 10 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 18.--19. "PUD9,Pin 9 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 16.--17. "PUD8,Pin 8 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 14.--15. "PUD7,Pin 7 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 12.--13. "PUD6,Pin 6 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 10.--11. "PUD5,Pin 5 pull-up or pull-down bits" "0,1,2,3"
newline
bitfld.long 0xC 8.--9. "PUD4,Pin 4 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 6.--7. "PUD3,Pin 3 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 4.--5. "PUD2,Pin 2 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 2.--3. "PUD1,Pin 1 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 0.--1. "PUD0,Pin 0 pull-up or pull-down bits" "0,1,2,3"
rgroup.long 0x10++0x3
line.long 0x0 "ISTAT,Port input status register"
bitfld.long 0x0 15. "ISTAT15,Port input status" "0,1"
bitfld.long 0x0 14. "ISTAT14,Port input status" "0,1"
bitfld.long 0x0 13. "ISTAT13,Port input status" "0,1"
bitfld.long 0x0 12. "ISTAT12,Port input status" "0,1"
bitfld.long 0x0 11. "ISTAT11,Port input status" "0,1"
bitfld.long 0x0 10. "ISTAT10,Port input status" "0,1"
bitfld.long 0x0 9. "ISTAT9,Port input status" "0,1"
bitfld.long 0x0 8. "ISTAT8,Port input status" "0,1"
bitfld.long 0x0 7. "ISTAT7,Port input status" "0,1"
bitfld.long 0x0 6. "ISTAT6,Port input status" "0,1"
bitfld.long 0x0 5. "ISTAT5,Port input status" "0,1"
newline
bitfld.long 0x0 4. "ISTAT4,Port input status" "0,1"
bitfld.long 0x0 3. "ISTAT3,Port input status" "0,1"
bitfld.long 0x0 2. "ISTAT2,Port input status" "0,1"
bitfld.long 0x0 1. "ISTAT1,Port input status" "0,1"
bitfld.long 0x0 0. "ISTAT0,Port input status" "0,1"
group.long 0x14++0x3
line.long 0x0 "OCTL,Port output control register"
bitfld.long 0x0 15. "OCTL15,Port output control" "0,1"
bitfld.long 0x0 14. "OCTL14,Port output control" "0,1"
bitfld.long 0x0 13. "OCTL13,Port output control" "0,1"
bitfld.long 0x0 12. "OCTL12,Port output control" "0,1"
bitfld.long 0x0 11. "OCTL11,Port output control" "0,1"
bitfld.long 0x0 10. "OCTL10,Port output control" "0,1"
bitfld.long 0x0 9. "OCTL9,Port output control" "0,1"
bitfld.long 0x0 8. "OCTL8,Port output control" "0,1"
bitfld.long 0x0 7. "OCTL7,Port output control" "0,1"
bitfld.long 0x0 6. "OCTL6,Port output control" "0,1"
bitfld.long 0x0 5. "OCTL5,Port output control" "0,1"
newline
bitfld.long 0x0 4. "OCTL4,Port output control" "0,1"
bitfld.long 0x0 3. "OCTL3,Port output control" "0,1"
bitfld.long 0x0 2. "OCTL2,Port output control" "0,1"
bitfld.long 0x0 1. "OCTL1,Port output control" "0,1"
bitfld.long 0x0 0. "OCTL0,Port output control" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "BOP,Port bit operate register"
bitfld.long 0x0 31. "CR15,Port clear bit y" "0,1"
bitfld.long 0x0 30. "CR14,Port clear bit y" "0,1"
bitfld.long 0x0 29. "CR13,Port clear bit y" "0,1"
bitfld.long 0x0 28. "CR12,Port clear bit y" "0,1"
bitfld.long 0x0 27. "CR11,Port clear bit y" "0,1"
bitfld.long 0x0 26. "CR10,Port clear bit y" "0,1"
bitfld.long 0x0 25. "CR9,Port clear bit y" "0,1"
bitfld.long 0x0 24. "CR8,Port clear bit y" "0,1"
bitfld.long 0x0 23. "CR7,Port clear bit y" "0,1"
bitfld.long 0x0 22. "CR6,Port clear bit y" "0,1"
bitfld.long 0x0 21. "CR5,Port clear bit y" "0,1"
newline
bitfld.long 0x0 20. "CR4,Port clear bit y" "0,1"
bitfld.long 0x0 19. "CR3,Port clear bit y" "0,1"
bitfld.long 0x0 18. "CR2,Port clear bit y" "0,1"
bitfld.long 0x0 17. "CR1,Port clear bit y" "0,1"
bitfld.long 0x0 16. "CR0,Port clear bit y" "0,1"
bitfld.long 0x0 15. "BOP15,Port set bit y" "0,1"
bitfld.long 0x0 14. "BOP14,Port set bit y" "0,1"
bitfld.long 0x0 13. "BOP13,Port set bit y" "0,1"
bitfld.long 0x0 12. "BOP12,Port set bit y" "0,1"
bitfld.long 0x0 11. "BOP11,Port set bit y" "0,1"
bitfld.long 0x0 10. "BOP10,Port set bit y" "0,1"
newline
bitfld.long 0x0 9. "BOP9,Port set bit y" "0,1"
bitfld.long 0x0 8. "BOP8,Port set bit y" "0,1"
bitfld.long 0x0 7. "BOP7,Port set bit y" "0,1"
bitfld.long 0x0 6. "BOP6,Port set bit y" "0,1"
bitfld.long 0x0 5. "BOP5,Port set bit y" "0,1"
bitfld.long 0x0 4. "BOP4,Port set bit y" "0,1"
bitfld.long 0x0 3. "BOP3,Port set bit y" "0,1"
bitfld.long 0x0 2. "BOP2,Port set bit y" "0,1"
bitfld.long 0x0 1. "BOP1,Port set bit y" "0,1"
bitfld.long 0x0 0. "BOP0,Port set bit y" "0,1"
group.long 0x1C++0xB
line.long 0x0 "LOCK,Port configuration lock register"
bitfld.long 0x0 16. "LKK,Lock key" "0,1"
bitfld.long 0x0 15. "LK15,LOCK key writing sequence:" "0,1"
bitfld.long 0x0 14. "LK14,Port lock bit y" "0,1"
bitfld.long 0x0 13. "LK13,Port lock bit y" "0,1"
bitfld.long 0x0 12. "LK12,Port lock bit y" "0,1"
bitfld.long 0x0 11. "LK11,Port lock bit y" "0,1"
bitfld.long 0x0 10. "LK10,Port lock bit y" "0,1"
bitfld.long 0x0 9. "LK9,Port lock bit y" "0,1"
bitfld.long 0x0 8. "LK8,Port lock bit y" "0,1"
bitfld.long 0x0 7. "LK7,Port lock bit y" "0,1"
bitfld.long 0x0 6. "LK6,Port lock bit y" "0,1"
newline
bitfld.long 0x0 5. "LK5,Port lock bit y" "0,1"
bitfld.long 0x0 4. "LK4,Port lock bit y" "0,1"
bitfld.long 0x0 3. "LK3,Port lock bit y" "0,1"
bitfld.long 0x0 2. "LK2,Port lock bit y" "0,1"
bitfld.long 0x0 1. "LK1,Port lock bit y" "0,1"
bitfld.long 0x0 0. "LK0,Port lock bit y" "0,1"
line.long 0x4 "AFSEL0,Alternate function selected register 0"
hexmask.long.byte 0x4 28.--31. 1. "SEL7,Pin 7 alternate function selected"
hexmask.long.byte 0x4 24.--27. 1. "SEL6,Pin 6 alternate function selected"
hexmask.long.byte 0x4 20.--23. 1. "SEL5,Pin 5 alternate function selected"
hexmask.long.byte 0x4 16.--19. 1. "SEL4,Pin 4 alternate function selected"
hexmask.long.byte 0x4 12.--15. 1. "SEL3,Pin 3 alternate function selected"
hexmask.long.byte 0x4 8.--11. 1. "SEL2,Pin 2 alternate function selected"
hexmask.long.byte 0x4 4.--7. 1. "SEL1,Pin 1 alternate function selected"
hexmask.long.byte 0x4 0.--3. 1. "SEL0,Pin 0 alternate function selected"
line.long 0x8 "AFSEL1,Alternate function selected register 1"
hexmask.long.byte 0x8 28.--31. 1. "SEL15,Pin 15 alternate function selected"
hexmask.long.byte 0x8 24.--27. 1. "SEL14,Pin 14 alternate function selected"
hexmask.long.byte 0x8 20.--23. 1. "SEL13,Pin 13 alternate function selected"
hexmask.long.byte 0x8 16.--19. 1. "SEL12,Pin 12 alternate function selected"
hexmask.long.byte 0x8 12.--15. 1. "SEL11,Pin 1 alternate function selected"
hexmask.long.byte 0x8 8.--11. 1. "SEL10,Pin 10 alternate function selected"
hexmask.long.byte 0x8 4.--7. 1. "SEL9,Pin 9 alternate function selected"
hexmask.long.byte 0x8 0.--3. 1. "SEL8,Pin 8 alternate function selected"
wgroup.long 0x28++0x7
line.long 0x0 "BC,Bit clear register"
bitfld.long 0x0 15. "CR15,Port clear bit 15" "0,1"
bitfld.long 0x0 14. "CR14,Port clear bit 14" "0,1"
bitfld.long 0x0 13. "CR13,Port clear bit 13" "0,1"
bitfld.long 0x0 12. "CR12,Port clear bit 12" "0,1"
bitfld.long 0x0 11. "CR11,Port clear bit 11" "0,1"
bitfld.long 0x0 10. "CR10,Port clear bit 10" "0,1"
bitfld.long 0x0 9. "CR9,Port clear bit 9" "0,1"
bitfld.long 0x0 8. "CR8,Port clear bit 8" "0,1"
bitfld.long 0x0 7. "CR7,Port clear bit 7" "0,1"
bitfld.long 0x0 6. "CR6,Port clear bit 6" "0,1"
bitfld.long 0x0 5. "CR5,Port clear bit 5" "0,1"
newline
bitfld.long 0x0 4. "CR4,Port clear bit 4" "0,1"
bitfld.long 0x0 3. "CR3,Port clear bit 3" "0,1"
bitfld.long 0x0 2. "CR2,Port clear bit 2" "0,1"
bitfld.long 0x0 1. "CR1,Port clear bit 1" "0,1"
bitfld.long 0x0 0. "CR0,Port clear bit 0" "0,1"
line.long 0x4 "TG,Port bit toggle register"
bitfld.long 0x4 15. "TG15,Port toggle bit 15" "0,1"
bitfld.long 0x4 14. "TG14,Port toggle bit 14" "0,1"
bitfld.long 0x4 13. "TG13,Port toggle bit 13" "0,1"
bitfld.long 0x4 12. "TG12,Port toggle bit 12" "0,1"
bitfld.long 0x4 11. "TG11,Port toggle bit 11" "0,1"
bitfld.long 0x4 10. "TG10,Port toggle bit 10" "0,1"
bitfld.long 0x4 9. "TG9,Port toggle bit 9" "0,1"
bitfld.long 0x4 8. "TG8,Port toggle bit 8" "0,1"
bitfld.long 0x4 7. "TG7,Port toggle bit 7" "0,1"
bitfld.long 0x4 6. "TG6,Port toggle bit 6" "0,1"
bitfld.long 0x4 5. "TG5,Port toggle bit 5" "0,1"
newline
bitfld.long 0x4 4. "TG4,Port toggle bit 4" "0,1"
bitfld.long 0x4 3. "TG3,Port toggle bit 3" "0,1"
bitfld.long 0x4 2. "TG2,Port toggle bit 2" "0,1"
bitfld.long 0x4 1. "TG1,Port toggle bit 1" "0,1"
bitfld.long 0x4 0. "TG0,Port toggle bit 0" "0,1"
group.long 0x30++0x7
line.long 0x0 "IFL,Input filtering register"
hexmask.long.byte 0x0 8.--15. 1. "FLPRD1,Filter sampling period for GPIO8 to GPIO15:"
hexmask.long.byte 0x0 0.--7. 1. "FLPRD0,Filter sampling period for GPIO1 to GPIO7:"
line.long 0x4 "IFTP,Input filtering type register"
bitfld.long 0x4 30.--31. "IFTP15,Pin 15 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 28.--29. "IFTP14,Pin 14 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 26.--27. "IFTP13,Pin 13 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 24.--25. "IFTP12,Pin 12 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 22.--23. "IFTP11,Pin 11 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 20.--21. "IFTP10,Pin 10 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 18.--19. "IFTP9,Pin 9 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 16.--17. "IFTP8,Pin 8 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 14.--15. "IFTP7,Pin 7 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 12.--13. "IFTP6,Pin 6 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 10.--11. "IFTP5,Pin 5 input filtering type bits" "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "IFTP4,Pin 4 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 6.--7. "IFTP3,Pin 3 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 4.--5. "IFTP2,Pin 2 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 2.--3. "IFTP1,Pin 1 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 0.--1. "IFTP0,Pin 0 input filtering type bits" "0,1,2,3"
tree.end
tree "GPIOE"
base ad:0x48001000
group.long 0x0++0xF
line.long 0x0 "CTL,Port control register"
bitfld.long 0x0 30.--31. "CTL15,Pin 15 configuration bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "CTL14,Pin 14 configuration bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "CTL13,Pin 13 configuration bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "CTL12,Pin 12 configuration bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "CTL11,Pin 11 configuration bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "CTL10,Pin 10 configuration bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "CTL9,Pin 9 configuration bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "CTL8,Pin 8 configuration bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "CTL7,Pin 7 configuration bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "CTL6,Pin 6 configuration bits" "0,1,2,3"
bitfld.long 0x0 10.--11. "CTL5,Pin 5 configuration bits" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CTL4,Pin 4 configuration bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "CTL3,Pin 3 configuration bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "CTL2,Pin 2 configuration bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "CTL1,Pin 1 configuration bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "CTL0,Pin 0 configuration bits" "0,1,2,3"
line.long 0x4 "OMODE,Port output mode register"
bitfld.long 0x4 15. "OM15,Pin 15 output mode bit" "0,1"
bitfld.long 0x4 14. "OM14,Pin 14 output mode bit" "0,1"
bitfld.long 0x4 13. "OM13,Pin 13 output mode bit" "0,1"
bitfld.long 0x4 12. "OM12,Pin 12 output mode bit" "0,1"
bitfld.long 0x4 11. "OM11,Pin 11 output mode bit" "0,1"
bitfld.long 0x4 10. "OM10,Pin 10 output mode bit" "0,1"
bitfld.long 0x4 9. "OM9,Pin 9 output mode bit" "0,1"
bitfld.long 0x4 8. "OM8,Pin 8 output mode bit" "0,1"
bitfld.long 0x4 7. "OM7,Pin 7 output mode bit" "0,1"
bitfld.long 0x4 6. "OM6,Pin 6 output mode bit" "0,1"
bitfld.long 0x4 5. "OM5,Pin 5 output mode bit" "0,1"
newline
bitfld.long 0x4 4. "OM4,Pin 4 output mode bit" "0,1"
bitfld.long 0x4 3. "OM3,Pin 3 output mode bit" "0,1"
bitfld.long 0x4 2. "OM2,Pin 2 output mode bit" "0,1"
bitfld.long 0x4 1. "OM1,Pin 1 output mode bit" "0,1"
bitfld.long 0x4 0. "OM0,Pin 0 output mode bit" "0,1"
line.long 0x8 "OSPD,Port output speed register"
bitfld.long 0x8 30.--31. "OSPD15,Pin 15 output max speed bits" "0,1,2,3"
bitfld.long 0x8 28.--29. "OSPD14,Pin 14 output max speed bits" "0,1,2,3"
bitfld.long 0x8 26.--27. "OSPD13,Pin 13 output max speed bits" "0,1,2,3"
bitfld.long 0x8 24.--25. "OSPD12,Pin 12 output max speed bits" "0,1,2,3"
bitfld.long 0x8 22.--23. "OSPD11,Pin 11 output max speed bits" "0,1,2,3"
bitfld.long 0x8 20.--21. "OSPD10,Pin 10 output max speed bits" "0,1,2,3"
bitfld.long 0x8 18.--19. "OSPD9,Pin 9 output max speed bits" "0,1,2,3"
bitfld.long 0x8 16.--17. "OSPD8,Pin 8 output max speed bits" "0,1,2,3"
bitfld.long 0x8 14.--15. "OSPD7,Pin 7 output max speed bits" "0,1,2,3"
bitfld.long 0x8 12.--13. "OSPD6,Pin 6 output max speed bits" "0,1,2,3"
bitfld.long 0x8 10.--11. "OSPD5,Pin 5 output max speed bits" "0,1,2,3"
newline
bitfld.long 0x8 8.--9. "OSPD4,Pin 4 output max speed bits" "0,1,2,3"
bitfld.long 0x8 6.--7. "OSPD3,Pin 3 output max speed bits" "0,1,2,3"
bitfld.long 0x8 4.--5. "OSPD2,Pin 2 output max speed bits" "0,1,2,3"
bitfld.long 0x8 2.--3. "OSPD1,Pin 1 output max speed bits" "0,1,2,3"
bitfld.long 0x8 0.--1. "OSPD0,Pin 0 output max speed bits" "0,1,2,3"
line.long 0xC "PUD,Port pull-up/down register"
bitfld.long 0xC 30.--31. "PUD15,Pin 15 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 28.--29. "PUD14,Pin 14 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 26.--27. "PUD13,Pin 13 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 24.--25. "PUD12,Pin 12 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 22.--23. "PUD11,Pin 11 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 20.--21. "PUD10,Pin 10 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 18.--19. "PUD9,Pin 9 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 16.--17. "PUD8,Pin 8 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 14.--15. "PUD7,Pin 7 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 12.--13. "PUD6,Pin 6 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 10.--11. "PUD5,Pin 5 pull-up or pull-down bits" "0,1,2,3"
newline
bitfld.long 0xC 8.--9. "PUD4,Pin 4 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 6.--7. "PUD3,Pin 3 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 4.--5. "PUD2,Pin 2 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 2.--3. "PUD1,Pin 1 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 0.--1. "PUD0,Pin 0 pull-up or pull-down bits" "0,1,2,3"
rgroup.long 0x10++0x3
line.long 0x0 "ISTAT,Port input status register"
bitfld.long 0x0 15. "ISTAT15,Port input status" "0,1"
bitfld.long 0x0 14. "ISTAT14,Port input status" "0,1"
bitfld.long 0x0 13. "ISTAT13,Port input status" "0,1"
bitfld.long 0x0 12. "ISTAT12,Port input status" "0,1"
bitfld.long 0x0 11. "ISTAT11,Port input status" "0,1"
bitfld.long 0x0 10. "ISTAT10,Port input status" "0,1"
bitfld.long 0x0 9. "ISTAT9,Port input status" "0,1"
bitfld.long 0x0 8. "ISTAT8,Port input status" "0,1"
bitfld.long 0x0 7. "ISTAT7,Port input status" "0,1"
bitfld.long 0x0 6. "ISTAT6,Port input status" "0,1"
bitfld.long 0x0 5. "ISTAT5,Port input status" "0,1"
newline
bitfld.long 0x0 4. "ISTAT4,Port input status" "0,1"
bitfld.long 0x0 3. "ISTAT3,Port input status" "0,1"
bitfld.long 0x0 2. "ISTAT2,Port input status" "0,1"
bitfld.long 0x0 1. "ISTAT1,Port input status" "0,1"
bitfld.long 0x0 0. "ISTAT0,Port input status" "0,1"
group.long 0x14++0x3
line.long 0x0 "OCTL,Port output control register"
bitfld.long 0x0 15. "OCTL15,Port output control" "0,1"
bitfld.long 0x0 14. "OCTL14,Port output control" "0,1"
bitfld.long 0x0 13. "OCTL13,Port output control" "0,1"
bitfld.long 0x0 12. "OCTL12,Port output control" "0,1"
bitfld.long 0x0 11. "OCTL11,Port output control" "0,1"
bitfld.long 0x0 10. "OCTL10,Port output control" "0,1"
bitfld.long 0x0 9. "OCTL9,Port output control" "0,1"
bitfld.long 0x0 8. "OCTL8,Port output control" "0,1"
bitfld.long 0x0 7. "OCTL7,Port output control" "0,1"
bitfld.long 0x0 6. "OCTL6,Port output control" "0,1"
bitfld.long 0x0 5. "OCTL5,Port output control" "0,1"
newline
bitfld.long 0x0 4. "OCTL4,Port output control" "0,1"
bitfld.long 0x0 3. "OCTL3,Port output control" "0,1"
bitfld.long 0x0 2. "OCTL2,Port output control" "0,1"
bitfld.long 0x0 1. "OCTL1,Port output control" "0,1"
bitfld.long 0x0 0. "OCTL0,Port output control" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "BOP,Port bit operate register"
bitfld.long 0x0 31. "CR15,Port clear bit y" "0,1"
bitfld.long 0x0 30. "CR14,Port clear bit y" "0,1"
bitfld.long 0x0 29. "CR13,Port clear bit y" "0,1"
bitfld.long 0x0 28. "CR12,Port clear bit y" "0,1"
bitfld.long 0x0 27. "CR11,Port clear bit y" "0,1"
bitfld.long 0x0 26. "CR10,Port clear bit y" "0,1"
bitfld.long 0x0 25. "CR9,Port clear bit y" "0,1"
bitfld.long 0x0 24. "CR8,Port clear bit y" "0,1"
bitfld.long 0x0 23. "CR7,Port clear bit y" "0,1"
bitfld.long 0x0 22. "CR6,Port clear bit y" "0,1"
bitfld.long 0x0 21. "CR5,Port clear bit y" "0,1"
newline
bitfld.long 0x0 20. "CR4,Port clear bit y" "0,1"
bitfld.long 0x0 19. "CR3,Port clear bit y" "0,1"
bitfld.long 0x0 18. "CR2,Port clear bit y" "0,1"
bitfld.long 0x0 17. "CR1,Port clear bit y" "0,1"
bitfld.long 0x0 16. "CR0,Port clear bit y" "0,1"
bitfld.long 0x0 15. "BOP15,Port set bit y" "0,1"
bitfld.long 0x0 14. "BOP14,Port set bit y" "0,1"
bitfld.long 0x0 13. "BOP13,Port set bit y" "0,1"
bitfld.long 0x0 12. "BOP12,Port set bit y" "0,1"
bitfld.long 0x0 11. "BOP11,Port set bit y" "0,1"
bitfld.long 0x0 10. "BOP10,Port set bit y" "0,1"
newline
bitfld.long 0x0 9. "BOP9,Port set bit y" "0,1"
bitfld.long 0x0 8. "BOP8,Port set bit y" "0,1"
bitfld.long 0x0 7. "BOP7,Port set bit y" "0,1"
bitfld.long 0x0 6. "BOP6,Port set bit y" "0,1"
bitfld.long 0x0 5. "BOP5,Port set bit y" "0,1"
bitfld.long 0x0 4. "BOP4,Port set bit y" "0,1"
bitfld.long 0x0 3. "BOP3,Port set bit y" "0,1"
bitfld.long 0x0 2. "BOP2,Port set bit y" "0,1"
bitfld.long 0x0 1. "BOP1,Port set bit y" "0,1"
bitfld.long 0x0 0. "BOP0,Port set bit y" "0,1"
group.long 0x1C++0xB
line.long 0x0 "LOCK,Port configuration lock register"
bitfld.long 0x0 16. "LKK,Lock key" "0,1"
bitfld.long 0x0 15. "LK15,LOCK key writing sequence:" "0,1"
bitfld.long 0x0 14. "LK14,Port lock bit y" "0,1"
bitfld.long 0x0 13. "LK13,Port lock bit y" "0,1"
bitfld.long 0x0 12. "LK12,Port lock bit y" "0,1"
bitfld.long 0x0 11. "LK11,Port lock bit y" "0,1"
bitfld.long 0x0 10. "LK10,Port lock bit y" "0,1"
bitfld.long 0x0 9. "LK9,Port lock bit y" "0,1"
bitfld.long 0x0 8. "LK8,Port lock bit y" "0,1"
bitfld.long 0x0 7. "LK7,Port lock bit y" "0,1"
bitfld.long 0x0 6. "LK6,Port lock bit y" "0,1"
newline
bitfld.long 0x0 5. "LK5,Port lock bit y" "0,1"
bitfld.long 0x0 4. "LK4,Port lock bit y" "0,1"
bitfld.long 0x0 3. "LK3,Port lock bit y" "0,1"
bitfld.long 0x0 2. "LK2,Port lock bit y" "0,1"
bitfld.long 0x0 1. "LK1,Port lock bit y" "0,1"
bitfld.long 0x0 0. "LK0,Port lock bit y" "0,1"
line.long 0x4 "AFSEL0,Alternate function selected register 0"
hexmask.long.byte 0x4 28.--31. 1. "SEL7,Pin 7 alternate function selected"
hexmask.long.byte 0x4 24.--27. 1. "SEL6,Pin 6 alternate function selected"
hexmask.long.byte 0x4 20.--23. 1. "SEL5,Pin 5 alternate function selected"
hexmask.long.byte 0x4 16.--19. 1. "SEL4,Pin 4 alternate function selected"
hexmask.long.byte 0x4 12.--15. 1. "SEL3,Pin 3 alternate function selected"
hexmask.long.byte 0x4 8.--11. 1. "SEL2,Pin 2 alternate function selected"
hexmask.long.byte 0x4 4.--7. 1. "SEL1,Pin 1 alternate function selected"
hexmask.long.byte 0x4 0.--3. 1. "SEL0,Pin 0 alternate function selected"
line.long 0x8 "AFSEL1,Alternate function selected register 1"
hexmask.long.byte 0x8 28.--31. 1. "SEL15,Pin 15 alternate function selected"
hexmask.long.byte 0x8 24.--27. 1. "SEL14,Pin 14 alternate function selected"
hexmask.long.byte 0x8 20.--23. 1. "SEL13,Pin 13 alternate function selected"
hexmask.long.byte 0x8 16.--19. 1. "SEL12,Pin 12 alternate function selected"
hexmask.long.byte 0x8 12.--15. 1. "SEL11,Pin 1 alternate function selected"
hexmask.long.byte 0x8 8.--11. 1. "SEL10,Pin 10 alternate function selected"
hexmask.long.byte 0x8 4.--7. 1. "SEL9,Pin 9 alternate function selected"
hexmask.long.byte 0x8 0.--3. 1. "SEL8,Pin 8 alternate function selected"
wgroup.long 0x28++0x7
line.long 0x0 "BC,Bit clear register"
bitfld.long 0x0 15. "CR15,Port clear bit 15" "0,1"
bitfld.long 0x0 14. "CR14,Port clear bit 14" "0,1"
bitfld.long 0x0 13. "CR13,Port clear bit 13" "0,1"
bitfld.long 0x0 12. "CR12,Port clear bit 12" "0,1"
bitfld.long 0x0 11. "CR11,Port clear bit 11" "0,1"
bitfld.long 0x0 10. "CR10,Port clear bit 10" "0,1"
bitfld.long 0x0 9. "CR9,Port clear bit 9" "0,1"
bitfld.long 0x0 8. "CR8,Port clear bit 8" "0,1"
bitfld.long 0x0 7. "CR7,Port clear bit 7" "0,1"
bitfld.long 0x0 6. "CR6,Port clear bit 6" "0,1"
bitfld.long 0x0 5. "CR5,Port clear bit 5" "0,1"
newline
bitfld.long 0x0 4. "CR4,Port clear bit 4" "0,1"
bitfld.long 0x0 3. "CR3,Port clear bit 3" "0,1"
bitfld.long 0x0 2. "CR2,Port clear bit 2" "0,1"
bitfld.long 0x0 1. "CR1,Port clear bit 1" "0,1"
bitfld.long 0x0 0. "CR0,Port clear bit 0" "0,1"
line.long 0x4 "TG,Port bit toggle register"
bitfld.long 0x4 15. "TG15,Port toggle bit 15" "0,1"
bitfld.long 0x4 14. "TG14,Port toggle bit 14" "0,1"
bitfld.long 0x4 13. "TG13,Port toggle bit 13" "0,1"
bitfld.long 0x4 12. "TG12,Port toggle bit 12" "0,1"
bitfld.long 0x4 11. "TG11,Port toggle bit 11" "0,1"
bitfld.long 0x4 10. "TG10,Port toggle bit 10" "0,1"
bitfld.long 0x4 9. "TG9,Port toggle bit 9" "0,1"
bitfld.long 0x4 8. "TG8,Port toggle bit 8" "0,1"
bitfld.long 0x4 7. "TG7,Port toggle bit 7" "0,1"
bitfld.long 0x4 6. "TG6,Port toggle bit 6" "0,1"
bitfld.long 0x4 5. "TG5,Port toggle bit 5" "0,1"
newline
bitfld.long 0x4 4. "TG4,Port toggle bit 4" "0,1"
bitfld.long 0x4 3. "TG3,Port toggle bit 3" "0,1"
bitfld.long 0x4 2. "TG2,Port toggle bit 2" "0,1"
bitfld.long 0x4 1. "TG1,Port toggle bit 1" "0,1"
bitfld.long 0x4 0. "TG0,Port toggle bit 0" "0,1"
group.long 0x30++0x7
line.long 0x0 "IFL,Input filtering register"
hexmask.long.byte 0x0 8.--15. 1. "FLPRD1,Filter sampling period for GPIO8 to GPIO15:"
hexmask.long.byte 0x0 0.--7. 1. "FLPRD0,Filter sampling period for GPIO1 to GPIO7:"
line.long 0x4 "IFTP,Input filtering type register"
bitfld.long 0x4 30.--31. "IFTP15,Pin 15 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 28.--29. "IFTP14,Pin 14 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 26.--27. "IFTP13,Pin 13 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 24.--25. "IFTP12,Pin 12 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 22.--23. "IFTP11,Pin 11 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 20.--21. "IFTP10,Pin 10 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 18.--19. "IFTP9,Pin 9 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 16.--17. "IFTP8,Pin 8 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 14.--15. "IFTP7,Pin 7 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 12.--13. "IFTP6,Pin 6 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 10.--11. "IFTP5,Pin 5 input filtering type bits" "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "IFTP4,Pin 4 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 6.--7. "IFTP3,Pin 3 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 4.--5. "IFTP2,Pin 2 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 2.--3. "IFTP1,Pin 1 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 0.--1. "IFTP0,Pin 0 input filtering type bits" "0,1,2,3"
tree.end
tree "GPIOF"
base ad:0x48001400
group.long 0x0++0xF
line.long 0x0 "CTL,Port control register"
bitfld.long 0x0 30.--31. "CTL15,Pin 15 configuration bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "CTL14,Pin 14 configuration bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "CTL13,Pin 13 configuration bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "CTL12,Pin 12 configuration bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "CTL11,Pin 11 configuration bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "CTL10,Pin 10 configuration bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "CTL9,Pin 9 configuration bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "CTL8,Pin 8 configuration bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "CTL7,Pin 7 configuration bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "CTL6,Pin 6 configuration bits" "0,1,2,3"
bitfld.long 0x0 10.--11. "CTL5,Pin 5 configuration bits" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CTL4,Pin 4 configuration bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "CTL3,Pin 3 configuration bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "CTL2,Pin 2 configuration bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "CTL1,Pin 1 configuration bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "CTL0,Pin 0 configuration bits" "0,1,2,3"
line.long 0x4 "OMODE,Port output mode register"
bitfld.long 0x4 15. "OM15,Pin 15 output mode bit" "0,1"
bitfld.long 0x4 14. "OM14,Pin 14 output mode bit" "0,1"
bitfld.long 0x4 13. "OM13,Pin 13 output mode bit" "0,1"
bitfld.long 0x4 12. "OM12,Pin 12 output mode bit" "0,1"
bitfld.long 0x4 11. "OM11,Pin 11 output mode bit" "0,1"
bitfld.long 0x4 10. "OM10,Pin 10 output mode bit" "0,1"
bitfld.long 0x4 9. "OM9,Pin 9 output mode bit" "0,1"
bitfld.long 0x4 8. "OM8,Pin 8 output mode bit" "0,1"
bitfld.long 0x4 7. "OM7,Pin 7 output mode bit" "0,1"
bitfld.long 0x4 6. "OM6,Pin 6 output mode bit" "0,1"
bitfld.long 0x4 5. "OM5,Pin 5 output mode bit" "0,1"
newline
bitfld.long 0x4 4. "OM4,Pin 4 output mode bit" "0,1"
bitfld.long 0x4 3. "OM3,Pin 3 output mode bit" "0,1"
bitfld.long 0x4 2. "OM2,Pin 2 output mode bit" "0,1"
bitfld.long 0x4 1. "OM1,Pin 1 output mode bit" "0,1"
bitfld.long 0x4 0. "OM0,Pin 0 output mode bit" "0,1"
line.long 0x8 "OSPD,Port output speed register"
bitfld.long 0x8 30.--31. "OSPD15,Pin 15 output max speed bits" "0,1,2,3"
bitfld.long 0x8 28.--29. "OSPD14,Pin 14 output max speed bits" "0,1,2,3"
bitfld.long 0x8 26.--27. "OSPD13,Pin 13 output max speed bits" "0,1,2,3"
bitfld.long 0x8 24.--25. "OSPD12,Pin 12 output max speed bits" "0,1,2,3"
bitfld.long 0x8 22.--23. "OSPD11,Pin 11 output max speed bits" "0,1,2,3"
bitfld.long 0x8 20.--21. "OSPD10,Pin 10 output max speed bits" "0,1,2,3"
bitfld.long 0x8 18.--19. "OSPD9,Pin 9 output max speed bits" "0,1,2,3"
bitfld.long 0x8 16.--17. "OSPD8,Pin 8 output max speed bits" "0,1,2,3"
bitfld.long 0x8 14.--15. "OSPD7,Pin 7 output max speed bits" "0,1,2,3"
bitfld.long 0x8 12.--13. "OSPD6,Pin 6 output max speed bits" "0,1,2,3"
bitfld.long 0x8 10.--11. "OSPD5,Pin 5 output max speed bits" "0,1,2,3"
newline
bitfld.long 0x8 8.--9. "OSPD4,Pin 4 output max speed bits" "0,1,2,3"
bitfld.long 0x8 6.--7. "OSPD3,Pin 3 output max speed bits" "0,1,2,3"
bitfld.long 0x8 4.--5. "OSPD2,Pin 2 output max speed bits" "0,1,2,3"
bitfld.long 0x8 2.--3. "OSPD1,Pin 1 output max speed bits" "0,1,2,3"
bitfld.long 0x8 0.--1. "OSPD0,Pin 0 output max speed bits" "0,1,2,3"
line.long 0xC "PUD,Port pull-up/down register"
bitfld.long 0xC 30.--31. "PUD15,Pin 15 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 28.--29. "PUD14,Pin 14 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 26.--27. "PUD13,Pin 13 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 24.--25. "PUD12,Pin 12 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 22.--23. "PUD11,Pin 11 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 20.--21. "PUD10,Pin 10 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 18.--19. "PUD9,Pin 9 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 16.--17. "PUD8,Pin 8 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 14.--15. "PUD7,Pin 7 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 12.--13. "PUD6,Pin 6 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 10.--11. "PUD5,Pin 5 pull-up or pull-down bits" "0,1,2,3"
newline
bitfld.long 0xC 8.--9. "PUD4,Pin 4 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 6.--7. "PUD3,Pin 3 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 4.--5. "PUD2,Pin 2 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 2.--3. "PUD1,Pin 1 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 0.--1. "PUD0,Pin 0 pull-up or pull-down bits" "0,1,2,3"
rgroup.long 0x10++0x3
line.long 0x0 "ISTAT,Port input status register"
bitfld.long 0x0 15. "ISTAT15,Port input status" "0,1"
bitfld.long 0x0 14. "ISTAT14,Port input status" "0,1"
bitfld.long 0x0 13. "ISTAT13,Port input status" "0,1"
bitfld.long 0x0 12. "ISTAT12,Port input status" "0,1"
bitfld.long 0x0 11. "ISTAT11,Port input status" "0,1"
bitfld.long 0x0 10. "ISTAT10,Port input status" "0,1"
bitfld.long 0x0 9. "ISTAT9,Port input status" "0,1"
bitfld.long 0x0 8. "ISTAT8,Port input status" "0,1"
bitfld.long 0x0 7. "ISTAT7,Port input status" "0,1"
bitfld.long 0x0 6. "ISTAT6,Port input status" "0,1"
bitfld.long 0x0 5. "ISTAT5,Port input status" "0,1"
newline
bitfld.long 0x0 4. "ISTAT4,Port input status" "0,1"
bitfld.long 0x0 3. "ISTAT3,Port input status" "0,1"
bitfld.long 0x0 2. "ISTAT2,Port input status" "0,1"
bitfld.long 0x0 1. "ISTAT1,Port input status" "0,1"
bitfld.long 0x0 0. "ISTAT0,Port input status" "0,1"
group.long 0x14++0x3
line.long 0x0 "OCTL,Port output control register"
bitfld.long 0x0 15. "OCTL15,Port output control" "0,1"
bitfld.long 0x0 14. "OCTL14,Port output control" "0,1"
bitfld.long 0x0 13. "OCTL13,Port output control" "0,1"
bitfld.long 0x0 12. "OCTL12,Port output control" "0,1"
bitfld.long 0x0 11. "OCTL11,Port output control" "0,1"
bitfld.long 0x0 10. "OCTL10,Port output control" "0,1"
bitfld.long 0x0 9. "OCTL9,Port output control" "0,1"
bitfld.long 0x0 8. "OCTL8,Port output control" "0,1"
bitfld.long 0x0 7. "OCTL7,Port output control" "0,1"
bitfld.long 0x0 6. "OCTL6,Port output control" "0,1"
bitfld.long 0x0 5. "OCTL5,Port output control" "0,1"
newline
bitfld.long 0x0 4. "OCTL4,Port output control" "0,1"
bitfld.long 0x0 3. "OCTL3,Port output control" "0,1"
bitfld.long 0x0 2. "OCTL2,Port output control" "0,1"
bitfld.long 0x0 1. "OCTL1,Port output control" "0,1"
bitfld.long 0x0 0. "OCTL0,Port output control" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "BOP,Port bit operate register"
bitfld.long 0x0 31. "CR15,Port clear bit y" "0,1"
bitfld.long 0x0 30. "CR14,Port clear bit y" "0,1"
bitfld.long 0x0 29. "CR13,Port clear bit y" "0,1"
bitfld.long 0x0 28. "CR12,Port clear bit y" "0,1"
bitfld.long 0x0 27. "CR11,Port clear bit y" "0,1"
bitfld.long 0x0 26. "CR10,Port clear bit y" "0,1"
bitfld.long 0x0 25. "CR9,Port clear bit y" "0,1"
bitfld.long 0x0 24. "CR8,Port clear bit y" "0,1"
bitfld.long 0x0 23. "CR7,Port clear bit y" "0,1"
bitfld.long 0x0 22. "CR6,Port clear bit y" "0,1"
bitfld.long 0x0 21. "CR5,Port clear bit y" "0,1"
newline
bitfld.long 0x0 20. "CR4,Port clear bit y" "0,1"
bitfld.long 0x0 19. "CR3,Port clear bit y" "0,1"
bitfld.long 0x0 18. "CR2,Port clear bit y" "0,1"
bitfld.long 0x0 17. "CR1,Port clear bit y" "0,1"
bitfld.long 0x0 16. "CR0,Port clear bit y" "0,1"
bitfld.long 0x0 15. "BOP15,Port set bit y" "0,1"
bitfld.long 0x0 14. "BOP14,Port set bit y" "0,1"
bitfld.long 0x0 13. "BOP13,Port set bit y" "0,1"
bitfld.long 0x0 12. "BOP12,Port set bit y" "0,1"
bitfld.long 0x0 11. "BOP11,Port set bit y" "0,1"
bitfld.long 0x0 10. "BOP10,Port set bit y" "0,1"
newline
bitfld.long 0x0 9. "BOP9,Port set bit y" "0,1"
bitfld.long 0x0 8. "BOP8,Port set bit y" "0,1"
bitfld.long 0x0 7. "BOP7,Port set bit y" "0,1"
bitfld.long 0x0 6. "BOP6,Port set bit y" "0,1"
bitfld.long 0x0 5. "BOP5,Port set bit y" "0,1"
bitfld.long 0x0 4. "BOP4,Port set bit y" "0,1"
bitfld.long 0x0 3. "BOP3,Port set bit y" "0,1"
bitfld.long 0x0 2. "BOP2,Port set bit y" "0,1"
bitfld.long 0x0 1. "BOP1,Port set bit y" "0,1"
bitfld.long 0x0 0. "BOP0,Port set bit y" "0,1"
group.long 0x1C++0xB
line.long 0x0 "LOCK,Port configuration lock register"
bitfld.long 0x0 16. "LKK,Lock key" "0,1"
bitfld.long 0x0 15. "LK15,LOCK key writing sequence:" "0,1"
bitfld.long 0x0 14. "LK14,Port lock bit y" "0,1"
bitfld.long 0x0 13. "LK13,Port lock bit y" "0,1"
bitfld.long 0x0 12. "LK12,Port lock bit y" "0,1"
bitfld.long 0x0 11. "LK11,Port lock bit y" "0,1"
bitfld.long 0x0 10. "LK10,Port lock bit y" "0,1"
bitfld.long 0x0 9. "LK9,Port lock bit y" "0,1"
bitfld.long 0x0 8. "LK8,Port lock bit y" "0,1"
bitfld.long 0x0 7. "LK7,Port lock bit y" "0,1"
bitfld.long 0x0 6. "LK6,Port lock bit y" "0,1"
newline
bitfld.long 0x0 5. "LK5,Port lock bit y" "0,1"
bitfld.long 0x0 4. "LK4,Port lock bit y" "0,1"
bitfld.long 0x0 3. "LK3,Port lock bit y" "0,1"
bitfld.long 0x0 2. "LK2,Port lock bit y" "0,1"
bitfld.long 0x0 1. "LK1,Port lock bit y" "0,1"
bitfld.long 0x0 0. "LK0,Port lock bit y" "0,1"
line.long 0x4 "AFSEL0,Alternate function selected register 0"
hexmask.long.byte 0x4 28.--31. 1. "SEL7,Pin 7 alternate function selected"
hexmask.long.byte 0x4 24.--27. 1. "SEL6,Pin 6 alternate function selected"
hexmask.long.byte 0x4 20.--23. 1. "SEL5,Pin 5 alternate function selected"
hexmask.long.byte 0x4 16.--19. 1. "SEL4,Pin 4 alternate function selected"
hexmask.long.byte 0x4 12.--15. 1. "SEL3,Pin 3 alternate function selected"
hexmask.long.byte 0x4 8.--11. 1. "SEL2,Pin 2 alternate function selected"
hexmask.long.byte 0x4 4.--7. 1. "SEL1,Pin 1 alternate function selected"
hexmask.long.byte 0x4 0.--3. 1. "SEL0,Pin 0 alternate function selected"
line.long 0x8 "AFSEL1,Alternate function selected register 1"
hexmask.long.byte 0x8 28.--31. 1. "SEL15,Pin 15 alternate function selected"
hexmask.long.byte 0x8 24.--27. 1. "SEL14,Pin 14 alternate function selected"
hexmask.long.byte 0x8 20.--23. 1. "SEL13,Pin 13 alternate function selected"
hexmask.long.byte 0x8 16.--19. 1. "SEL12,Pin 12 alternate function selected"
hexmask.long.byte 0x8 12.--15. 1. "SEL11,Pin 1 alternate function selected"
hexmask.long.byte 0x8 8.--11. 1. "SEL10,Pin 10 alternate function selected"
hexmask.long.byte 0x8 4.--7. 1. "SEL9,Pin 9 alternate function selected"
hexmask.long.byte 0x8 0.--3. 1. "SEL8,Pin 8 alternate function selected"
wgroup.long 0x28++0x7
line.long 0x0 "BC,Bit clear register"
bitfld.long 0x0 15. "CR15,Port clear bit 15" "0,1"
bitfld.long 0x0 14. "CR14,Port clear bit 14" "0,1"
bitfld.long 0x0 13. "CR13,Port clear bit 13" "0,1"
bitfld.long 0x0 12. "CR12,Port clear bit 12" "0,1"
bitfld.long 0x0 11. "CR11,Port clear bit 11" "0,1"
bitfld.long 0x0 10. "CR10,Port clear bit 10" "0,1"
bitfld.long 0x0 9. "CR9,Port clear bit 9" "0,1"
bitfld.long 0x0 8. "CR8,Port clear bit 8" "0,1"
bitfld.long 0x0 7. "CR7,Port clear bit 7" "0,1"
bitfld.long 0x0 6. "CR6,Port clear bit 6" "0,1"
bitfld.long 0x0 5. "CR5,Port clear bit 5" "0,1"
newline
bitfld.long 0x0 4. "CR4,Port clear bit 4" "0,1"
bitfld.long 0x0 3. "CR3,Port clear bit 3" "0,1"
bitfld.long 0x0 2. "CR2,Port clear bit 2" "0,1"
bitfld.long 0x0 1. "CR1,Port clear bit 1" "0,1"
bitfld.long 0x0 0. "CR0,Port clear bit 0" "0,1"
line.long 0x4 "TG,Port bit toggle register"
bitfld.long 0x4 15. "TG15,Port toggle bit 15" "0,1"
bitfld.long 0x4 14. "TG14,Port toggle bit 14" "0,1"
bitfld.long 0x4 13. "TG13,Port toggle bit 13" "0,1"
bitfld.long 0x4 12. "TG12,Port toggle bit 12" "0,1"
bitfld.long 0x4 11. "TG11,Port toggle bit 11" "0,1"
bitfld.long 0x4 10. "TG10,Port toggle bit 10" "0,1"
bitfld.long 0x4 9. "TG9,Port toggle bit 9" "0,1"
bitfld.long 0x4 8. "TG8,Port toggle bit 8" "0,1"
bitfld.long 0x4 7. "TG7,Port toggle bit 7" "0,1"
bitfld.long 0x4 6. "TG6,Port toggle bit 6" "0,1"
bitfld.long 0x4 5. "TG5,Port toggle bit 5" "0,1"
newline
bitfld.long 0x4 4. "TG4,Port toggle bit 4" "0,1"
bitfld.long 0x4 3. "TG3,Port toggle bit 3" "0,1"
bitfld.long 0x4 2. "TG2,Port toggle bit 2" "0,1"
bitfld.long 0x4 1. "TG1,Port toggle bit 1" "0,1"
bitfld.long 0x4 0. "TG0,Port toggle bit 0" "0,1"
group.long 0x30++0x7
line.long 0x0 "IFL,Input filtering register"
hexmask.long.byte 0x0 8.--15. 1. "FLPRD1,Filter sampling period for GPIO8 to GPIO15:"
hexmask.long.byte 0x0 0.--7. 1. "FLPRD0,Filter sampling period for GPIO1 to GPIO7:"
line.long 0x4 "IFTP,Input filtering type register"
bitfld.long 0x4 30.--31. "IFTP15,Pin 15 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 28.--29. "IFTP14,Pin 14 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 26.--27. "IFTP13,Pin 13 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 24.--25. "IFTP12,Pin 12 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 22.--23. "IFTP11,Pin 11 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 20.--21. "IFTP10,Pin 10 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 18.--19. "IFTP9,Pin 9 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 16.--17. "IFTP8,Pin 8 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 14.--15. "IFTP7,Pin 7 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 12.--13. "IFTP6,Pin 6 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 10.--11. "IFTP5,Pin 5 input filtering type bits" "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "IFTP4,Pin 4 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 6.--7. "IFTP3,Pin 3 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 4.--5. "IFTP2,Pin 2 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 2.--3. "IFTP1,Pin 1 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 0.--1. "IFTP0,Pin 0 input filtering type bits" "0,1,2,3"
tree.end
tree "GPIOG"
base ad:0x48001800
group.long 0x0++0xF
line.long 0x0 "CTL,Port control register"
bitfld.long 0x0 30.--31. "CTL15,Pin 15 configuration bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "CTL14,Pin 14 configuration bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "CTL13,Pin 13 configuration bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "CTL12,Pin 12 configuration bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "CTL11,Pin 11 configuration bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "CTL10,Pin 10 configuration bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "CTL9,Pin 9 configuration bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "CTL8,Pin 8 configuration bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "CTL7,Pin 7 configuration bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "CTL6,Pin 6 configuration bits" "0,1,2,3"
bitfld.long 0x0 10.--11. "CTL5,Pin 5 configuration bits" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CTL4,Pin 4 configuration bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "CTL3,Pin 3 configuration bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "CTL2,Pin 2 configuration bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "CTL1,Pin 1 configuration bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "CTL0,Pin 0 configuration bits" "0,1,2,3"
line.long 0x4 "OMODE,Port output mode register"
bitfld.long 0x4 15. "OM15,Pin 15 output mode bit" "0,1"
bitfld.long 0x4 14. "OM14,Pin 14 output mode bit" "0,1"
bitfld.long 0x4 13. "OM13,Pin 13 output mode bit" "0,1"
bitfld.long 0x4 12. "OM12,Pin 12 output mode bit" "0,1"
bitfld.long 0x4 11. "OM11,Pin 11 output mode bit" "0,1"
bitfld.long 0x4 10. "OM10,Pin 10 output mode bit" "0,1"
bitfld.long 0x4 9. "OM9,Pin 9 output mode bit" "0,1"
bitfld.long 0x4 8. "OM8,Pin 8 output mode bit" "0,1"
bitfld.long 0x4 7. "OM7,Pin 7 output mode bit" "0,1"
bitfld.long 0x4 6. "OM6,Pin 6 output mode bit" "0,1"
bitfld.long 0x4 5. "OM5,Pin 5 output mode bit" "0,1"
newline
bitfld.long 0x4 4. "OM4,Pin 4 output mode bit" "0,1"
bitfld.long 0x4 3. "OM3,Pin 3 output mode bit" "0,1"
bitfld.long 0x4 2. "OM2,Pin 2 output mode bit" "0,1"
bitfld.long 0x4 1. "OM1,Pin 1 output mode bit" "0,1"
bitfld.long 0x4 0. "OM0,Pin 0 output mode bit" "0,1"
line.long 0x8 "OSPD,Port output speed register"
bitfld.long 0x8 30.--31. "OSPD15,Pin 15 output max speed bits" "0,1,2,3"
bitfld.long 0x8 28.--29. "OSPD14,Pin 14 output max speed bits" "0,1,2,3"
bitfld.long 0x8 26.--27. "OSPD13,Pin 13 output max speed bits" "0,1,2,3"
bitfld.long 0x8 24.--25. "OSPD12,Pin 12 output max speed bits" "0,1,2,3"
bitfld.long 0x8 22.--23. "OSPD11,Pin 11 output max speed bits" "0,1,2,3"
bitfld.long 0x8 20.--21. "OSPD10,Pin 10 output max speed bits" "0,1,2,3"
bitfld.long 0x8 18.--19. "OSPD9,Pin 9 output max speed bits" "0,1,2,3"
bitfld.long 0x8 16.--17. "OSPD8,Pin 8 output max speed bits" "0,1,2,3"
bitfld.long 0x8 14.--15. "OSPD7,Pin 7 output max speed bits" "0,1,2,3"
bitfld.long 0x8 12.--13. "OSPD6,Pin 6 output max speed bits" "0,1,2,3"
bitfld.long 0x8 10.--11. "OSPD5,Pin 5 output max speed bits" "0,1,2,3"
newline
bitfld.long 0x8 8.--9. "OSPD4,Pin 4 output max speed bits" "0,1,2,3"
bitfld.long 0x8 6.--7. "OSPD3,Pin 3 output max speed bits" "0,1,2,3"
bitfld.long 0x8 4.--5. "OSPD2,Pin 2 output max speed bits" "0,1,2,3"
bitfld.long 0x8 2.--3. "OSPD1,Pin 1 output max speed bits" "0,1,2,3"
bitfld.long 0x8 0.--1. "OSPD0,Pin 0 output max speed bits" "0,1,2,3"
line.long 0xC "PUD,Port pull-up/down register"
bitfld.long 0xC 30.--31. "PUD15,Pin 15 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 28.--29. "PUD14,Pin 14 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 26.--27. "PUD13,Pin 13 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 24.--25. "PUD12,Pin 12 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 22.--23. "PUD11,Pin 11 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 20.--21. "PUD10,Pin 10 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 18.--19. "PUD9,Pin 9 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 16.--17. "PUD8,Pin 8 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 14.--15. "PUD7,Pin 7 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 12.--13. "PUD6,Pin 6 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 10.--11. "PUD5,Pin 5 pull-up or pull-down bits" "0,1,2,3"
newline
bitfld.long 0xC 8.--9. "PUD4,Pin 4 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 6.--7. "PUD3,Pin 3 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 4.--5. "PUD2,Pin 2 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 2.--3. "PUD1,Pin 1 pull-up or pull-down bits" "0,1,2,3"
bitfld.long 0xC 0.--1. "PUD0,Pin 0 pull-up or pull-down bits" "0,1,2,3"
rgroup.long 0x10++0x3
line.long 0x0 "ISTAT,Port input status register"
bitfld.long 0x0 15. "ISTAT15,Port input status" "0,1"
bitfld.long 0x0 14. "ISTAT14,Port input status" "0,1"
bitfld.long 0x0 13. "ISTAT13,Port input status" "0,1"
bitfld.long 0x0 12. "ISTAT12,Port input status" "0,1"
bitfld.long 0x0 11. "ISTAT11,Port input status" "0,1"
bitfld.long 0x0 10. "ISTAT10,Port input status" "0,1"
bitfld.long 0x0 9. "ISTAT9,Port input status" "0,1"
bitfld.long 0x0 8. "ISTAT8,Port input status" "0,1"
bitfld.long 0x0 7. "ISTAT7,Port input status" "0,1"
bitfld.long 0x0 6. "ISTAT6,Port input status" "0,1"
bitfld.long 0x0 5. "ISTAT5,Port input status" "0,1"
newline
bitfld.long 0x0 4. "ISTAT4,Port input status" "0,1"
bitfld.long 0x0 3. "ISTAT3,Port input status" "0,1"
bitfld.long 0x0 2. "ISTAT2,Port input status" "0,1"
bitfld.long 0x0 1. "ISTAT1,Port input status" "0,1"
bitfld.long 0x0 0. "ISTAT0,Port input status" "0,1"
group.long 0x14++0x3
line.long 0x0 "OCTL,Port output control register"
bitfld.long 0x0 15. "OCTL15,Port output control" "0,1"
bitfld.long 0x0 14. "OCTL14,Port output control" "0,1"
bitfld.long 0x0 13. "OCTL13,Port output control" "0,1"
bitfld.long 0x0 12. "OCTL12,Port output control" "0,1"
bitfld.long 0x0 11. "OCTL11,Port output control" "0,1"
bitfld.long 0x0 10. "OCTL10,Port output control" "0,1"
bitfld.long 0x0 9. "OCTL9,Port output control" "0,1"
bitfld.long 0x0 8. "OCTL8,Port output control" "0,1"
bitfld.long 0x0 7. "OCTL7,Port output control" "0,1"
bitfld.long 0x0 6. "OCTL6,Port output control" "0,1"
bitfld.long 0x0 5. "OCTL5,Port output control" "0,1"
newline
bitfld.long 0x0 4. "OCTL4,Port output control" "0,1"
bitfld.long 0x0 3. "OCTL3,Port output control" "0,1"
bitfld.long 0x0 2. "OCTL2,Port output control" "0,1"
bitfld.long 0x0 1. "OCTL1,Port output control" "0,1"
bitfld.long 0x0 0. "OCTL0,Port output control" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "BOP,Port bit operate register"
bitfld.long 0x0 31. "CR15,Port clear bit y" "0,1"
bitfld.long 0x0 30. "CR14,Port clear bit y" "0,1"
bitfld.long 0x0 29. "CR13,Port clear bit y" "0,1"
bitfld.long 0x0 28. "CR12,Port clear bit y" "0,1"
bitfld.long 0x0 27. "CR11,Port clear bit y" "0,1"
bitfld.long 0x0 26. "CR10,Port clear bit y" "0,1"
bitfld.long 0x0 25. "CR9,Port clear bit y" "0,1"
bitfld.long 0x0 24. "CR8,Port clear bit y" "0,1"
bitfld.long 0x0 23. "CR7,Port clear bit y" "0,1"
bitfld.long 0x0 22. "CR6,Port clear bit y" "0,1"
bitfld.long 0x0 21. "CR5,Port clear bit y" "0,1"
newline
bitfld.long 0x0 20. "CR4,Port clear bit y" "0,1"
bitfld.long 0x0 19. "CR3,Port clear bit y" "0,1"
bitfld.long 0x0 18. "CR2,Port clear bit y" "0,1"
bitfld.long 0x0 17. "CR1,Port clear bit y" "0,1"
bitfld.long 0x0 16. "CR0,Port clear bit y" "0,1"
bitfld.long 0x0 15. "BOP15,Port set bit y" "0,1"
bitfld.long 0x0 14. "BOP14,Port set bit y" "0,1"
bitfld.long 0x0 13. "BOP13,Port set bit y" "0,1"
bitfld.long 0x0 12. "BOP12,Port set bit y" "0,1"
bitfld.long 0x0 11. "BOP11,Port set bit y" "0,1"
bitfld.long 0x0 10. "BOP10,Port set bit y" "0,1"
newline
bitfld.long 0x0 9. "BOP9,Port set bit y" "0,1"
bitfld.long 0x0 8. "BOP8,Port set bit y" "0,1"
bitfld.long 0x0 7. "BOP7,Port set bit y" "0,1"
bitfld.long 0x0 6. "BOP6,Port set bit y" "0,1"
bitfld.long 0x0 5. "BOP5,Port set bit y" "0,1"
bitfld.long 0x0 4. "BOP4,Port set bit y" "0,1"
bitfld.long 0x0 3. "BOP3,Port set bit y" "0,1"
bitfld.long 0x0 2. "BOP2,Port set bit y" "0,1"
bitfld.long 0x0 1. "BOP1,Port set bit y" "0,1"
bitfld.long 0x0 0. "BOP0,Port set bit y" "0,1"
group.long 0x1C++0xB
line.long 0x0 "LOCK,Port configuration lock register"
bitfld.long 0x0 16. "LKK,Lock key" "0,1"
bitfld.long 0x0 15. "LK15,LOCK key writing sequence:" "0,1"
bitfld.long 0x0 14. "LK14,Port lock bit y" "0,1"
bitfld.long 0x0 13. "LK13,Port lock bit y" "0,1"
bitfld.long 0x0 12. "LK12,Port lock bit y" "0,1"
bitfld.long 0x0 11. "LK11,Port lock bit y" "0,1"
bitfld.long 0x0 10. "LK10,Port lock bit y" "0,1"
bitfld.long 0x0 9. "LK9,Port lock bit y" "0,1"
bitfld.long 0x0 8. "LK8,Port lock bit y" "0,1"
bitfld.long 0x0 7. "LK7,Port lock bit y" "0,1"
bitfld.long 0x0 6. "LK6,Port lock bit y" "0,1"
newline
bitfld.long 0x0 5. "LK5,Port lock bit y" "0,1"
bitfld.long 0x0 4. "LK4,Port lock bit y" "0,1"
bitfld.long 0x0 3. "LK3,Port lock bit y" "0,1"
bitfld.long 0x0 2. "LK2,Port lock bit y" "0,1"
bitfld.long 0x0 1. "LK1,Port lock bit y" "0,1"
bitfld.long 0x0 0. "LK0,Port lock bit y" "0,1"
line.long 0x4 "AFSEL0,Alternate function selected register 0"
hexmask.long.byte 0x4 28.--31. 1. "SEL7,Pin 7 alternate function selected"
hexmask.long.byte 0x4 24.--27. 1. "SEL6,Pin 6 alternate function selected"
hexmask.long.byte 0x4 20.--23. 1. "SEL5,Pin 5 alternate function selected"
hexmask.long.byte 0x4 16.--19. 1. "SEL4,Pin 4 alternate function selected"
hexmask.long.byte 0x4 12.--15. 1. "SEL3,Pin 3 alternate function selected"
hexmask.long.byte 0x4 8.--11. 1. "SEL2,Pin 2 alternate function selected"
hexmask.long.byte 0x4 4.--7. 1. "SEL1,Pin 1 alternate function selected"
hexmask.long.byte 0x4 0.--3. 1. "SEL0,Pin 0 alternate function selected"
line.long 0x8 "AFSEL1,Alternate function selected register 1"
hexmask.long.byte 0x8 28.--31. 1. "SEL15,Pin 15 alternate function selected"
hexmask.long.byte 0x8 24.--27. 1. "SEL14,Pin 14 alternate function selected"
hexmask.long.byte 0x8 20.--23. 1. "SEL13,Pin 13 alternate function selected"
hexmask.long.byte 0x8 16.--19. 1. "SEL12,Pin 12 alternate function selected"
hexmask.long.byte 0x8 12.--15. 1. "SEL11,Pin 1 alternate function selected"
hexmask.long.byte 0x8 8.--11. 1. "SEL10,Pin 10 alternate function selected"
hexmask.long.byte 0x8 4.--7. 1. "SEL9,Pin 9 alternate function selected"
hexmask.long.byte 0x8 0.--3. 1. "SEL8,Pin 8 alternate function selected"
wgroup.long 0x28++0x7
line.long 0x0 "BC,Bit clear register"
bitfld.long 0x0 15. "CR15,Port clear bit 15" "0,1"
bitfld.long 0x0 14. "CR14,Port clear bit 14" "0,1"
bitfld.long 0x0 13. "CR13,Port clear bit 13" "0,1"
bitfld.long 0x0 12. "CR12,Port clear bit 12" "0,1"
bitfld.long 0x0 11. "CR11,Port clear bit 11" "0,1"
bitfld.long 0x0 10. "CR10,Port clear bit 10" "0,1"
bitfld.long 0x0 9. "CR9,Port clear bit 9" "0,1"
bitfld.long 0x0 8. "CR8,Port clear bit 8" "0,1"
bitfld.long 0x0 7. "CR7,Port clear bit 7" "0,1"
bitfld.long 0x0 6. "CR6,Port clear bit 6" "0,1"
bitfld.long 0x0 5. "CR5,Port clear bit 5" "0,1"
newline
bitfld.long 0x0 4. "CR4,Port clear bit 4" "0,1"
bitfld.long 0x0 3. "CR3,Port clear bit 3" "0,1"
bitfld.long 0x0 2. "CR2,Port clear bit 2" "0,1"
bitfld.long 0x0 1. "CR1,Port clear bit 1" "0,1"
bitfld.long 0x0 0. "CR0,Port clear bit 0" "0,1"
line.long 0x4 "TG,Port bit toggle register"
bitfld.long 0x4 15. "TG15,Port toggle bit 15" "0,1"
bitfld.long 0x4 14. "TG14,Port toggle bit 14" "0,1"
bitfld.long 0x4 13. "TG13,Port toggle bit 13" "0,1"
bitfld.long 0x4 12. "TG12,Port toggle bit 12" "0,1"
bitfld.long 0x4 11. "TG11,Port toggle bit 11" "0,1"
bitfld.long 0x4 10. "TG10,Port toggle bit 10" "0,1"
bitfld.long 0x4 9. "TG9,Port toggle bit 9" "0,1"
bitfld.long 0x4 8. "TG8,Port toggle bit 8" "0,1"
bitfld.long 0x4 7. "TG7,Port toggle bit 7" "0,1"
bitfld.long 0x4 6. "TG6,Port toggle bit 6" "0,1"
bitfld.long 0x4 5. "TG5,Port toggle bit 5" "0,1"
newline
bitfld.long 0x4 4. "TG4,Port toggle bit 4" "0,1"
bitfld.long 0x4 3. "TG3,Port toggle bit 3" "0,1"
bitfld.long 0x4 2. "TG2,Port toggle bit 2" "0,1"
bitfld.long 0x4 1. "TG1,Port toggle bit 1" "0,1"
bitfld.long 0x4 0. "TG0,Port toggle bit 0" "0,1"
group.long 0x30++0x7
line.long 0x0 "IFL,Input filtering register"
hexmask.long.byte 0x0 8.--15. 1. "FLPRD1,Filter sampling period for GPIO8 to GPIO15:"
hexmask.long.byte 0x0 0.--7. 1. "FLPRD0,Filter sampling period for GPIO1 to GPIO7:"
line.long 0x4 "IFTP,Input filtering type register"
bitfld.long 0x4 30.--31. "IFTP15,Pin 15 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 28.--29. "IFTP14,Pin 14 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 26.--27. "IFTP13,Pin 13 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 24.--25. "IFTP12,Pin 12 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 22.--23. "IFTP11,Pin 11 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 20.--21. "IFTP10,Pin 10 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 18.--19. "IFTP9,Pin 9 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 16.--17. "IFTP8,Pin 8 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 14.--15. "IFTP7,Pin 7 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 12.--13. "IFTP6,Pin 6 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 10.--11. "IFTP5,Pin 5 input filtering type bits" "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "IFTP4,Pin 4 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 6.--7. "IFTP3,Pin 3 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 4.--5. "IFTP2,Pin 2 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 2.--3. "IFTP1,Pin 1 input filtering type bits" "0,1,2,3"
bitfld.long 0x4 0.--1. "IFTP0,Pin 0 input filtering type bits" "0,1,2,3"
tree.end
tree.end
tree "HPDF (High Performance Digital Filter)"
base ad:0x40017000
group.long 0x0++0x3
line.long 0x0 "CH0CTL,Channel 0 control regist"
bitfld.long 0x0 31. "HPDFEN,Global enable for HPDF interface" "0,1"
bitfld.long 0x0 30. "CKOUTSEL,Serial clock output source selection" "0,1"
bitfld.long 0x0 29. "CKOUTDM,Serial clock output duty mode" "0,1"
hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Serial clock output divider"
bitfld.long 0x0 14.--15. "DPM,Data packing mode for HPDF_CHxPDI register" "0,1,2,3"
bitfld.long 0x0 12.--13. "CMSD,Channel x multiplexer select input data source" "0,1,2,3"
bitfld.long 0x0 8. "CHPINSEL,Channel inputs pins selection" "0,1"
bitfld.long 0x0 7. "CHEN,Channel x enable" "0,1"
bitfld.long 0x0 6. "CKLEN,Clock loss detector enable" "0,1"
newline
bitfld.long 0x0 5. "MMEN,Malfunction monitor enable" "0,1"
bitfld.long 0x0 2.--3. "SPICKSS,SPI clock source select" "0,1,2,3"
bitfld.long 0x0 0.--1. "SITYP,Serial interface type" "0,1,2,3"
group.long 0x20++0x3
line.long 0x0 "CH1CTL,Channel 1 control regist"
bitfld.long 0x0 14.--15. "DPM,Data packing mode for HPDF_CHxPDI register" "0,1,2,3"
bitfld.long 0x0 12.--13. "CMSD,Channel x multiplexer select input data source" "0,1,2,3"
bitfld.long 0x0 8. "CHPINSEL,Channel inputs pins selection" "0,1"
bitfld.long 0x0 7. "CHEN,Channel x enable" "0,1"
bitfld.long 0x0 6. "CKLEN,Clock loss detector enable" "0,1"
bitfld.long 0x0 5. "MMEN,Malfunction monitor enable" "0,1"
bitfld.long 0x0 2.--3. "SPICKSS,SPI clock source select" "0,1,2,3"
bitfld.long 0x0 0.--1. "SITYP,Serial interface type" "0,1,2,3"
group.long 0x40++0x3
line.long 0x0 "CH2CTL,Channel 2 control regist"
bitfld.long 0x0 14.--15. "DPM,Data packing mode for HPDF_CHxPDI register" "0,1,2,3"
bitfld.long 0x0 12.--13. "CMSD,Channel x multiplexer select input data source" "0,1,2,3"
bitfld.long 0x0 8. "CHPINSEL,Channel inputs pins selection" "0,1"
bitfld.long 0x0 7. "CHEN,Channel x enable" "0,1"
bitfld.long 0x0 6. "CKLEN,Clock loss detector enable" "0,1"
bitfld.long 0x0 5. "MMEN,Malfunction monitor enable" "0,1"
bitfld.long 0x0 2.--3. "SPICKSS,SPI clock source select" "0,1,2,3"
bitfld.long 0x0 0.--1. "SITYP,Serial interface type" "0,1,2,3"
group.long 0x60++0x3
line.long 0x0 "CH3CTL,Channel 3 control regist"
bitfld.long 0x0 14.--15. "DPM,Data packing mode for HPDF_CHxPDI register" "0,1,2,3"
bitfld.long 0x0 12.--13. "CMSD,Channel x multiplexer select input data source" "0,1,2,3"
bitfld.long 0x0 8. "CHPINSEL,Channel inputs pins selection" "0,1"
bitfld.long 0x0 7. "CHEN,Channel x enable" "0,1"
bitfld.long 0x0 6. "CKLEN,Clock loss detector enable" "0,1"
bitfld.long 0x0 5. "MMEN,Malfunction monitor enable" "0,1"
bitfld.long 0x0 2.--3. "SPICKSS,SPI clock source select" "0,1,2,3"
bitfld.long 0x0 0.--1. "SITYP,Serial interface type" "0,1,2,3"
group.long 0x80++0x3
line.long 0x0 "CH4CTL,Channel 4 control regist"
bitfld.long 0x0 14.--15. "DPM,Data packing mode for HPDF_CHxPDI register" "0,1,2,3"
bitfld.long 0x0 12.--13. "CMSD,Channel x multiplexer select input data source" "0,1,2,3"
bitfld.long 0x0 8. "CHPINSEL,Channel inputs pins selection" "0,1"
bitfld.long 0x0 7. "CHEN,Channel x enable" "0,1"
bitfld.long 0x0 6. "CKLEN,Clock loss detector enable" "0,1"
bitfld.long 0x0 5. "MMEN,Malfunction monitor enable" "0,1"
bitfld.long 0x0 2.--3. "SPICKSS,SPI clock source select" "0,1,2,3"
bitfld.long 0x0 0.--1. "SITYP,Serial interface type" "0,1,2,3"
group.long 0xA0++0x3
line.long 0x0 "CH5CTL,Channel 5 control regist"
bitfld.long 0x0 14.--15. "DPM,Data packing mode for HPDF_CHxPDI register" "0,1,2,3"
bitfld.long 0x0 12.--13. "CMSD,Channel x multiplexer select input data source" "0,1,2,3"
bitfld.long 0x0 8. "CHPINSEL,Channel inputs pins selection" "0,1"
bitfld.long 0x0 7. "CHEN,Channel x enable" "0,1"
bitfld.long 0x0 6. "CKLEN,Clock loss detector enable" "0,1"
bitfld.long 0x0 5. "MMEN,Malfunction monitor enable" "0,1"
bitfld.long 0x0 2.--3. "SPICKSS,SPI clock source select" "0,1,2,3"
bitfld.long 0x0 0.--1. "SITYP,Serial interface type" "0,1,2,3"
group.long 0xC0++0x3
line.long 0x0 "CH6CTL,Channel 6 control regist"
bitfld.long 0x0 14.--15. "DPM,Data packing mode for HPDF_CHxPDI register" "0,1,2,3"
bitfld.long 0x0 12.--13. "CMSD,Channel x multiplexer select input data source" "0,1,2,3"
bitfld.long 0x0 8. "CHPINSEL,Channel inputs pins selection" "0,1"
bitfld.long 0x0 7. "CHEN,Channel x enable" "0,1"
bitfld.long 0x0 6. "CKLEN,Clock loss detector enable" "0,1"
bitfld.long 0x0 5. "MMEN,Malfunction monitor enable" "0,1"
bitfld.long 0x0 2.--3. "SPICKSS,SPI clock source select" "0,1,2,3"
bitfld.long 0x0 0.--1. "SITYP,Serial interface type" "0,1,2,3"
group.long 0xE0++0x3
line.long 0x0 "CH7CTL,Channel 7 control regist"
bitfld.long 0x0 14.--15. "DPM,Data packing mode for HPDF_CHxPDI register" "0,1,2,3"
bitfld.long 0x0 12.--13. "CMSD,Channel x multiplexer select input data source" "0,1,2,3"
bitfld.long 0x0 8. "CHPINSEL,Channel inputs pins selection" "0,1"
bitfld.long 0x0 7. "CHEN,Channel x enable" "0,1"
bitfld.long 0x0 6. "CKLEN,Clock loss detector enable" "0,1"
bitfld.long 0x0 5. "MMEN,Malfunction monitor enable" "0,1"
bitfld.long 0x0 2.--3. "SPICKSS,SPI clock source select" "0,1,2,3"
bitfld.long 0x0 0.--1. "SITYP,Serial interface type" "0,1,2,3"
group.long 0x4++0x3
line.long 0x0 "CH0CFG0,Channel 0 configuration register"
hexmask.long.tbyte 0x0 8.--31. 1. "CALOFF,24-bit calibration offset"
hexmask.long.byte 0x0 3.--7. 1. "DTRS,Data right bit-shift"
group.long 0x24++0x3
line.long 0x0 "CH1CFG0,Channel 1 configuration register"
hexmask.long.tbyte 0x0 8.--31. 1. "CALOFF,24-bit calibration offset"
hexmask.long.byte 0x0 3.--7. 1. "DTRS,Data right bit-shift"
group.long 0x44++0x3
line.long 0x0 "CH2CFG0,Channel 2 configuration register"
hexmask.long.tbyte 0x0 8.--31. 1. "CALOFF,24-bit calibration offset"
hexmask.long.byte 0x0 3.--7. 1. "DTRS,Data right bit-shift"
group.long 0x64++0x3
line.long 0x0 "CH3CFG0,Channel 3 configuration register"
hexmask.long.tbyte 0x0 8.--31. 1. "CALOFF,24-bit calibration offset"
hexmask.long.byte 0x0 3.--7. 1. "DTRS,Data right bit-shift"
group.long 0x84++0x3
line.long 0x0 "CH4CFG0,Channel 4 configuration register"
hexmask.long.tbyte 0x0 8.--31. 1. "CALOFF,24-bit calibration offset"
hexmask.long.byte 0x0 3.--7. 1. "DTRS,Data right bit-shift"
group.long 0xA4++0x3
line.long 0x0 "CH5CFG0,Channel 5 configuration register"
hexmask.long.tbyte 0x0 8.--31. 1. "CALOFF,24-bit calibration offset"
hexmask.long.byte 0x0 3.--7. 1. "DTRS,Data right bit-shift"
group.long 0xC4++0x3
line.long 0x0 "CH6CFG0,Channel 6 configuration register"
hexmask.long.tbyte 0x0 8.--31. 1. "CALOFF,24-bit calibration offset"
hexmask.long.byte 0x0 3.--7. 1. "DTRS,Data right bit-shift"
group.long 0xE4++0x3
line.long 0x0 "CH7CFG0,Channel 7 configuration register"
hexmask.long.tbyte 0x0 8.--31. 1. "CALOFF,24-bit calibration offset"
hexmask.long.byte 0x0 3.--7. 1. "DTRS,Data right bit-shift"
group.long 0x8++0x3
line.long 0x0 "CH0CFG1,Channel 0 configuration register"
bitfld.long 0x0 22.--23. "TMSFO,Threshold monitor Sinc filter order selection" "0,1,2,3"
hexmask.long.byte 0x0 16.--20. 1. "TMFOR,Threshold monitor filter oversampling rate (decimation rate)"
hexmask.long.byte 0x0 12.--15. 1. "MMBSD,Malfunction monitor break signal distribution"
hexmask.long.byte 0x0 0.--7. 1. "MMCT,Malfunction monitor counter threshold"
group.long 0x28++0x3
line.long 0x0 "CH1CFG1,Channel 1 configuration register"
bitfld.long 0x0 22.--23. "TMSFO,Threshold monitor Sinc filter order selection" "0,1,2,3"
hexmask.long.byte 0x0 16.--20. 1. "TMFOR,Threshold monitor filter oversampling rate (decimation rate)"
hexmask.long.byte 0x0 12.--15. 1. "MMBSD,Malfunction monitor break signal distribution"
hexmask.long.byte 0x0 0.--7. 1. "MMCT,Malfunction monitor counter threshold"
group.long 0x48++0x3
line.long 0x0 "CH2CFG1,Channel 2 configuration register"
bitfld.long 0x0 22.--23. "TMSFO,Threshold monitor Sinc filter order selection" "0,1,2,3"
hexmask.long.byte 0x0 16.--20. 1. "TMFOR,Threshold monitor filter oversampling rate (decimation rate)"
hexmask.long.byte 0x0 12.--15. 1. "MMBSD,Malfunction monitor break signal distribution"
hexmask.long.byte 0x0 0.--7. 1. "MMCT,Malfunction monitor counter threshold"
group.long 0x68++0x3
line.long 0x0 "CH3CFG1,Channel 3 configuration register"
bitfld.long 0x0 22.--23. "TMSFO,Threshold monitor Sinc filter order selection" "0,1,2,3"
hexmask.long.byte 0x0 16.--20. 1. "TMFOR,Threshold monitor filter oversampling rate (decimation rate)"
hexmask.long.byte 0x0 12.--15. 1. "MMBSD,Malfunction monitor break signal distribution"
hexmask.long.byte 0x0 0.--7. 1. "MMCT,Malfunction monitor counter threshold"
group.long 0x88++0x3
line.long 0x0 "CH4CFG1,Channel 4 configuration register"
bitfld.long 0x0 22.--23. "TMSFO,Threshold monitor Sinc filter order selection" "0,1,2,3"
hexmask.long.byte 0x0 16.--20. 1. "TMFOR,Threshold monitor filter oversampling rate (decimation rate)"
hexmask.long.byte 0x0 12.--15. 1. "MMBSD,Malfunction monitor break signal distribution"
hexmask.long.byte 0x0 0.--7. 1. "MMCT,Malfunction monitor counter threshold"
group.long 0xA8++0x3
line.long 0x0 "CH5CFG1,Channel 5 configuration register"
bitfld.long 0x0 22.--23. "TMSFO,Threshold monitor Sinc filter order selection" "0,1,2,3"
hexmask.long.byte 0x0 16.--20. 1. "TMFOR,Threshold monitor filter oversampling rate (decimation rate)"
hexmask.long.byte 0x0 12.--15. 1. "MMBSD,Malfunction monitor break signal distribution"
hexmask.long.byte 0x0 0.--7. 1. "MMCT,Malfunction monitor counter threshold"
group.long 0xC8++0x3
line.long 0x0 "CH6CFG1,Channel 6 configuration register"
bitfld.long 0x0 22.--23. "TMSFO,Threshold monitor Sinc filter order selection" "0,1,2,3"
hexmask.long.byte 0x0 16.--20. 1. "TMFOR,Threshold monitor filter oversampling rate (decimation rate)"
hexmask.long.byte 0x0 12.--15. 1. "MMBSD,Malfunction monitor break signal distribution"
hexmask.long.byte 0x0 0.--7. 1. "MMCT,Malfunction monitor counter threshold"
group.long 0xE8++0x3
line.long 0x0 "CH7CFG1,Channel 7 configuration register"
bitfld.long 0x0 22.--23. "TMSFO,Threshold monitor Sinc filter order selection" "0,1,2,3"
hexmask.long.byte 0x0 16.--20. 1. "TMFOR,Threshold monitor filter oversampling rate (decimation rate)"
hexmask.long.byte 0x0 12.--15. 1. "MMBSD,Malfunction monitor break signal distribution"
hexmask.long.byte 0x0 0.--7. 1. "MMCT,Malfunction monitor counter threshold"
rgroup.long 0xC++0x3
line.long 0x0 "CH0TMFDT,Channel 0 threshold monitor filter data regist"
hexmask.long.word 0x0 0.--15. 1. "TMDATA,Threshold monitor data"
rgroup.long 0x2C++0x3
line.long 0x0 "CH1TMFDT,Channel 1 threshold monitor filter data regist"
hexmask.long.word 0x0 0.--15. 1. "TMDATA,Threshold monitor data"
rgroup.long 0x4C++0x3
line.long 0x0 "CH2TMFDT,Channel 2 threshold monitor filter data regist"
hexmask.long.word 0x0 0.--15. 1. "TMDATA,Threshold monitor data"
rgroup.long 0x6C++0x3
line.long 0x0 "CH3TMFDT,Channel 3 threshold monitor filter data regist"
hexmask.long.word 0x0 0.--15. 1. "TMDATA,Threshold monitor data"
rgroup.long 0x8C++0x3
line.long 0x0 "CH4TMFDT,Channel 4 threshold monitor filter data regist"
hexmask.long.word 0x0 0.--15. 1. "TMDATA,Threshold monitor data"
rgroup.long 0xAC++0x3
line.long 0x0 "CH5TMFDT,Channel 5 threshold monitor filter data regist"
hexmask.long.word 0x0 0.--15. 1. "TMDATA,Threshold monitor data"
rgroup.long 0xCC++0x3
line.long 0x0 "CH6TMFDT,Channel 6 threshold monitor filter data regist"
hexmask.long.word 0x0 0.--15. 1. "TMDATA,Threshold monitor data"
rgroup.long 0xEC++0x3
line.long 0x0 "CH7TMFDT,Channel 7 threshold monitor filter data regist"
hexmask.long.word 0x0 0.--15. 1. "TMDATA,Threshold monitor data"
group.long 0x10++0x3
line.long 0x0 "CH0PDI,Channel 0 parallel data input regist"
hexmask.long.word 0x0 16.--31. 1. "DATAIN1,Data input for channel x or channel x+1"
hexmask.long.word 0x0 0.--15. 1. "DATAIN0,Data input for channel x"
group.long 0x30++0x3
line.long 0x0 "CH1PDI,Channel 1 parallel data input regist"
hexmask.long.word 0x0 16.--31. 1. "DATAIN1,Data input for channel x or channel x+1"
hexmask.long.word 0x0 0.--15. 1. "DATAIN0,Data input for channel x"
group.long 0x50++0x3
line.long 0x0 "CH2PDI,Channel 2 parallel data input regist"
hexmask.long.word 0x0 16.--31. 1. "DATAIN1,Data input for channel x or channel x+1"
hexmask.long.word 0x0 0.--15. 1. "DATAIN0,Data input for channel x"
group.long 0x70++0x3
line.long 0x0 "CH3PDI,Channel 3 parallel data input regist"
hexmask.long.word 0x0 16.--31. 1. "DATAIN1,Data input for channel x or channel x+1"
hexmask.long.word 0x0 0.--15. 1. "DATAIN0,Data input for channel x"
group.long 0x90++0x3
line.long 0x0 "CH4PDI,Channel 4 parallel data input regist"
hexmask.long.word 0x0 16.--31. 1. "DATAIN1,Data input for channel x or channel x+1"
hexmask.long.word 0x0 0.--15. 1. "DATAIN0,Data input for channel x"
group.long 0xB0++0x3
line.long 0x0 "CH5PDI,Channel 5 parallel data input regist"
hexmask.long.word 0x0 16.--31. 1. "DATAIN1,Data input for channel x or channel x+1"
hexmask.long.word 0x0 0.--15. 1. "DATAIN0,Data input for channel x"
group.long 0xD0++0x3
line.long 0x0 "CH6PDI,Channel 6 parallel data input regist"
hexmask.long.word 0x0 16.--31. 1. "DATAIN1,Data input for channel x or channel x+1"
hexmask.long.word 0x0 0.--15. 1. "DATAIN0,Data input for channel x"
group.long 0xF0++0x3
line.long 0x0 "CH7PDI,Channel 7 parallel data input regist"
hexmask.long.word 0x0 16.--31. 1. "DATAIN1,Data input for channel x or channel x+1"
hexmask.long.word 0x0 0.--15. 1. "DATAIN0,Data input for channel x"
group.long 0x14++0x3
line.long 0x0 "CH0PS,Channel 0 pulse skip regist"
hexmask.long.byte 0x0 0.--5. 1. "PLSK,Pulses to skip for input data skipping function"
group.long 0x34++0x3
line.long 0x0 "CH1PS,Channel 1 pulse skip regist"
hexmask.long.byte 0x0 0.--5. 1. "PLSK,Pulses to skip for input data skipping function"
group.long 0x54++0x3
line.long 0x0 "CH2PS,Channel 2 pulse skip regist"
hexmask.long.byte 0x0 0.--5. 1. "PLSK,Pulses to skip for input data skipping function"
group.long 0x74++0x3
line.long 0x0 "CH3PS,Channel 3 pulse skip regist"
hexmask.long.byte 0x0 0.--5. 1. "PLSK,Pulses to skip for input data skipping function"
group.long 0x94++0x3
line.long 0x0 "CH4PS,Channel 4 pulse skip regist"
hexmask.long.byte 0x0 0.--5. 1. "PLSK,Pulses to skip for input data skipping function"
group.long 0xB4++0x3
line.long 0x0 "CH5PS,Channel 5 pulse skip regist"
hexmask.long.byte 0x0 0.--5. 1. "PLSK,Pulses to skip for input data skipping function"
group.long 0xD4++0x3
line.long 0x0 "CH6PS,Channel 6 pulse skip regist"
hexmask.long.byte 0x0 0.--5. 1. "PLSK,Pulses to skip for input data skipping function"
group.long 0xF4++0x3
line.long 0x0 "CH7PS,Channel 7 pulse skip regist"
hexmask.long.byte 0x0 0.--5. 1. "PLSK,Pulses to skip for input data skipping function"
group.long 0x100++0x3
line.long 0x0 "FLT0CTL0,Filter 0 control register"
bitfld.long 0x0 30. "TMFM,Threshold monitor fast mode" "0,1"
bitfld.long 0x0 29. "FAST,Fast conversion mode for regular conversions" "0,1"
bitfld.long 0x0 24.--26. "RCS,Regular conversion channel selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 21. "RCDMAEN,DMA channel enabled to read data for the regular conversion" "0,1"
bitfld.long 0x0 19. "RCSYN,Regular conversion synchronously with HPDF_FLT0" "0,1"
bitfld.long 0x0 18. "RCCM,Regular conversions continuous mode" "0,1"
bitfld.long 0x0 17. "SRCS,Start regular channel conversion by software" "0,1"
bitfld.long 0x0 13.--14. "ICTEEN,Inserted conversions trigger edge enable" "0,1,2,3"
hexmask.long.byte 0x0 8.--12. 1. "ICTSSEL,Inserted conversions trigger signal selection"
newline
bitfld.long 0x0 5. "ICDMAEN,DMA channel enabled to read data for the inserted channel group" "0,1"
bitfld.long 0x0 4. "SCMOD,Scan conversion mode of inserted conversions" "0,1"
bitfld.long 0x0 3. "ICSYN,Inserted conversion synchronously with the HPDF_FLT0 SICC trigger" "0,1"
bitfld.long 0x0 1. "SICC,Start inserted group channel conversion" "0,1"
bitfld.long 0x0 0. "FLTEN,HPDF_FLTy enable" "0,1"
group.long 0x180++0x3
line.long 0x0 "FLT1CTL0,Filter 1 control register"
bitfld.long 0x0 30. "TMFM,Threshold monitor fast mode" "0,1"
bitfld.long 0x0 29. "FAST,Fast conversion mode for regular conversions" "0,1"
bitfld.long 0x0 24.--26. "RCS,Regular conversion channel selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 21. "RCDMAEN,DMA channel enabled to read data for the regular conversion" "0,1"
bitfld.long 0x0 19. "RCSYN,Regular conversion synchronously with HPDF_FLT0" "0,1"
bitfld.long 0x0 18. "RCCM,Regular conversions continuous mode" "0,1"
bitfld.long 0x0 17. "SRCS,Start regular channel conversion by software" "0,1"
bitfld.long 0x0 13.--14. "ICTEEN,Inserted conversions trigger edge enable" "0,1,2,3"
hexmask.long.byte 0x0 8.--12. 1. "ICTSSEL,Inserted conversions trigger signal selection"
newline
bitfld.long 0x0 5. "ICDMAEN,DMA channel enabled to read data for the inserted channel group" "0,1"
bitfld.long 0x0 4. "SCMOD,Scan conversion mode of inserted conversions" "0,1"
bitfld.long 0x0 3. "ICSYN,Inserted conversion synchronously with the HPDF_FLT0 SICC trigger" "0,1"
bitfld.long 0x0 1. "SICC,Start inserted group channel conversion" "0,1"
bitfld.long 0x0 0. "FLTEN,HPDF_FLTy enable" "0,1"
group.long 0x200++0x3
line.long 0x0 "FLT2CTL0,Filter 2 control register"
bitfld.long 0x0 30. "TMFM,Threshold monitor fast mode" "0,1"
bitfld.long 0x0 29. "FAST,Fast conversion mode for regular conversions" "0,1"
bitfld.long 0x0 24.--26. "RCS,Regular conversion channel selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 21. "RCDMAEN,DMA channel enabled to read data for the regular conversion" "0,1"
bitfld.long 0x0 19. "RCSYN,Regular conversion synchronously with HPDF_FLT0" "0,1"
bitfld.long 0x0 18. "RCCM,Regular conversions continuous mode" "0,1"
bitfld.long 0x0 17. "SRCS,Start regular channel conversion by software" "0,1"
bitfld.long 0x0 13.--14. "ICTEEN,Inserted conversions trigger edge enable" "0,1,2,3"
hexmask.long.byte 0x0 8.--12. 1. "ICTSSEL,Inserted conversions trigger signal selection"
newline
bitfld.long 0x0 5. "ICDMAEN,DMA channel enabled to read data for the inserted channel group" "0,1"
bitfld.long 0x0 4. "SCMOD,Scan conversion mode of inserted conversions" "0,1"
bitfld.long 0x0 3. "ICSYN,Inserted conversion synchronously with the HPDF_FLT0 SICC trigger" "0,1"
bitfld.long 0x0 1. "SICC,Start inserted group channel conversion" "0,1"
bitfld.long 0x0 0. "FLTEN,HPDF_FLTy enable" "0,1"
group.long 0x280++0x3
line.long 0x0 "FLT3CTL0,Filter 3 control register"
bitfld.long 0x0 30. "TMFM,Threshold monitor fast mode" "0,1"
bitfld.long 0x0 29. "FAST,Fast conversion mode for regular conversions" "0,1"
bitfld.long 0x0 24.--26. "RCS,Regular conversion channel selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 21. "RCDMAEN,DMA channel enabled to read data for the regular conversion" "0,1"
bitfld.long 0x0 19. "RCSYN,Regular conversion synchronously with HPDF_FLT0" "0,1"
bitfld.long 0x0 18. "RCCM,Regular conversions continuous mode" "0,1"
bitfld.long 0x0 17. "SRCS,Start regular channel conversion by software" "0,1"
bitfld.long 0x0 13.--14. "ICTEEN,Inserted conversions trigger edge enable" "0,1,2,3"
hexmask.long.byte 0x0 8.--12. 1. "ICTSSEL,Inserted conversions trigger signal selection"
newline
bitfld.long 0x0 5. "ICDMAEN,DMA channel enabled to read data for the inserted channel group" "0,1"
bitfld.long 0x0 4. "SCMOD,Scan conversion mode of inserted conversions" "0,1"
bitfld.long 0x0 3. "ICSYN,Inserted conversion synchronously with the HPDF_FLT0 SICC trigger" "0,1"
bitfld.long 0x0 1. "SICC,Start inserted group channel conversion" "0,1"
bitfld.long 0x0 0. "FLTEN,HPDF_FLTy enable" "0,1"
group.long 0x104++0x3
line.long 0x0 "FLT0CTL1,Filter 0 control register"
hexmask.long.byte 0x0 16.--23. 1. "TMCHEN,Threshold monitor channel enable"
hexmask.long.byte 0x0 8.--15. 1. "EMCS,Extremes monitor channel selection"
bitfld.long 0x0 6. "CKLIE,Clock loss interrupt enable" "0,1"
bitfld.long 0x0 5. "MMIE,Malfunction monitor interrupt enable" "0,1"
bitfld.long 0x0 4. "TMIE,Threshold monitor interrupt enable" "0,1"
bitfld.long 0x0 3. "RCDOIE,Regular conversion data overflow interrupt enable" "0,1"
bitfld.long 0x0 2. "ICDOIE,Inserted conversion data overflow interrupt enable" "0,1"
bitfld.long 0x0 1. "RCEIE,Regular conversion end interrupt enable" "0,1"
bitfld.long 0x0 0. "ICEIE,Inserted conversion end interrupt enable" "0,1"
group.long 0x184++0x3
line.long 0x0 "FLT1CTL1,Filter 1 control register"
hexmask.long.byte 0x0 16.--23. 1. "TMCHEN,Threshold monitor channel enable"
hexmask.long.byte 0x0 8.--15. 1. "EMCS,Extremes monitor channel selection"
bitfld.long 0x0 6. "CKLIE,Clock loss interrupt enable" "0,1"
bitfld.long 0x0 5. "MMIE,Malfunction monitor interrupt enable" "0,1"
bitfld.long 0x0 4. "TMIE,Threshold monitor interrupt enable" "0,1"
bitfld.long 0x0 3. "RCDOIE,Regular conversion data overflow interrupt enable" "0,1"
bitfld.long 0x0 2. "ICDOIE,Inserted conversion data overflow interrupt enable" "0,1"
bitfld.long 0x0 1. "RCEIE,Regular conversion end interrupt enable" "0,1"
bitfld.long 0x0 0. "ICEIE,Inserted conversion end interrupt enable" "0,1"
group.long 0x204++0x3
line.long 0x0 "FLT2CTL1,Filter 2 control register"
hexmask.long.byte 0x0 16.--23. 1. "TMCHEN,Threshold monitor channel enable"
hexmask.long.byte 0x0 8.--15. 1. "EMCS,Extremes monitor channel selection"
bitfld.long 0x0 6. "CKLIE,Clock loss interrupt enable" "0,1"
bitfld.long 0x0 5. "MMIE,Malfunction monitor interrupt enable" "0,1"
bitfld.long 0x0 4. "TMIE,Threshold monitor interrupt enable" "0,1"
bitfld.long 0x0 3. "RCDOIE,Regular conversion data overflow interrupt enable" "0,1"
bitfld.long 0x0 2. "ICDOIE,Inserted conversion data overflow interrupt enable" "0,1"
bitfld.long 0x0 1. "RCEIE,Regular conversion end interrupt enable" "0,1"
bitfld.long 0x0 0. "ICEIE,Inserted conversion end interrupt enable" "0,1"
group.long 0x284++0x3
line.long 0x0 "FLT3CTL1,Filter 2 control register"
hexmask.long.byte 0x0 16.--23. 1. "TMCHEN,Threshold monitor channel enable"
hexmask.long.byte 0x0 8.--15. 1. "EMCS,Extremes monitor channel selection"
bitfld.long 0x0 6. "CKLIE,Clock loss interrupt enable" "0,1"
bitfld.long 0x0 5. "MMIE,Malfunction monitor interrupt enable" "0,1"
bitfld.long 0x0 4. "TMIE,Threshold monitor interrupt enable" "0,1"
bitfld.long 0x0 3. "RCDOIE,Regular conversion data overflow interrupt enable" "0,1"
bitfld.long 0x0 2. "ICDOIE,Inserted conversion data overflow interrupt enable" "0,1"
bitfld.long 0x0 1. "RCEIE,Regular conversion end interrupt enable" "0,1"
bitfld.long 0x0 0. "ICEIE,Inserted conversion end interrupt enable" "0,1"
rgroup.long 0x108++0x3
line.long 0x0 "FLT0STAT,Filter 0 status regist"
hexmask.long.byte 0x0 24.--31. 1. "MMF,Malfunction monitor flag"
hexmask.long.byte 0x0 16.--23. 1. "CKLF,Clock loss flag"
bitfld.long 0x0 14. "RCPF,Regular conversion in progress flag" "0,1"
bitfld.long 0x0 13. "ICPF,Inserted conversion in progress flag" "0,1"
bitfld.long 0x0 4. "TMEOF,Threshold monitor event occurred flag" "0,1"
bitfld.long 0x0 3. "RCDOF,Regular conversion data overflow flag" "0,1"
bitfld.long 0x0 2. "ICDOF,Inserted conversion data overflow flag" "0,1"
bitfld.long 0x0 1. "RCEF,Regular conversion end flag" "0,1"
bitfld.long 0x0 0. "ICEF,Inserted conversion end flag" "0,1"
rgroup.long 0x188++0x3
line.long 0x0 "FLT1STAT,Filter 1 status regist"
hexmask.long.byte 0x0 24.--31. 1. "MMF,Malfunction monitor flag"
hexmask.long.byte 0x0 16.--23. 1. "CKLF,Clock loss flag"
bitfld.long 0x0 14. "RCPF,Regular conversion in progress flag" "0,1"
bitfld.long 0x0 13. "ICPF,Inserted conversion in progress flag" "0,1"
bitfld.long 0x0 4. "TMEOF,Threshold monitor event occurred flag" "0,1"
bitfld.long 0x0 3. "RCDOF,Regular conversion data overflow flag" "0,1"
bitfld.long 0x0 2. "ICDOF,Inserted conversion data overflow flag" "0,1"
bitfld.long 0x0 1. "RCEF,Regular conversion end flag" "0,1"
bitfld.long 0x0 0. "ICEF,Inserted conversion end flag" "0,1"
rgroup.long 0x208++0x3
line.long 0x0 "FLT2STAT,Filter 2 status regist"
hexmask.long.byte 0x0 24.--31. 1. "MMF,Malfunction monitor flag"
hexmask.long.byte 0x0 16.--23. 1. "CKLF,Clock loss flag"
bitfld.long 0x0 14. "RCPF,Regular conversion in progress flag" "0,1"
bitfld.long 0x0 13. "ICPF,Inserted conversion in progress flag" "0,1"
bitfld.long 0x0 4. "TMEOF,Threshold monitor event occurred flag" "0,1"
bitfld.long 0x0 3. "RCDOF,Regular conversion data overflow flag" "0,1"
bitfld.long 0x0 2. "ICDOF,Inserted conversion data overflow flag" "0,1"
bitfld.long 0x0 1. "RCEF,Regular conversion end flag" "0,1"
bitfld.long 0x0 0. "ICEF,Inserted conversion end flag" "0,1"
rgroup.long 0x288++0x3
line.long 0x0 "FLT3STAT,Filter 3 status regist"
hexmask.long.byte 0x0 24.--31. 1. "MMF,Malfunction monitor flag"
hexmask.long.byte 0x0 16.--23. 1. "CKLF,Clock loss flag"
bitfld.long 0x0 14. "RCPF,Regular conversion in progress flag" "0,1"
bitfld.long 0x0 13. "ICPF,Inserted conversion in progress flag" "0,1"
bitfld.long 0x0 4. "TMEOF,Threshold monitor event occurred flag" "0,1"
bitfld.long 0x0 3. "RCDOF,Regular conversion data overflow flag" "0,1"
bitfld.long 0x0 2. "ICDOF,Inserted conversion data overflow flag" "0,1"
bitfld.long 0x0 1. "RCEF,Regular conversion end flag" "0,1"
bitfld.long 0x0 0. "ICEF,Inserted conversion end flag" "0,1"
group.long 0x10C++0x3
line.long 0x0 "FLT0INTC,Filter 0 interrupt flag clear regist"
hexmask.long.byte 0x0 24.--31. 1. "MMFC,Clear the malfunction monitor flag"
hexmask.long.byte 0x0 16.--23. 1. "CKLFC,Clear the clock loss flag"
bitfld.long 0x0 3. "RCDOFC,Clear the regular conversion data overflow flag" "0,1"
bitfld.long 0x0 2. "ICDOFC,Clear the inserted conversion data overflow flag" "0,1"
group.long 0x18C++0x3
line.long 0x0 "FLT1INTC,Filter 1 interrupt flag clear regist"
hexmask.long.byte 0x0 24.--31. 1. "MMFC,Clear the malfunction monitor flag"
hexmask.long.byte 0x0 16.--23. 1. "CKLFC,Clear the clock loss flag"
bitfld.long 0x0 3. "RCDOFC,Clear the regular conversion data overflow flag" "0,1"
bitfld.long 0x0 2. "ICDOFC,Clear the inserted conversion data overflow flag" "0,1"
group.long 0x20C++0x3
line.long 0x0 "FLT2INTC,Filter 2 interrupt flag clear regist"
hexmask.long.byte 0x0 24.--31. 1. "MMFC,Clear the malfunction monitor flag"
hexmask.long.byte 0x0 16.--23. 1. "CKLFC,Clear the clock loss flag"
bitfld.long 0x0 3. "RCDOFC,Clear the regular conversion data overflow flag" "0,1"
bitfld.long 0x0 2. "ICDOFC,Clear the inserted conversion data overflow flag" "0,1"
group.long 0x28C++0x3
line.long 0x0 "FLT3INTC,Filter 3 interrupt flag clear regist"
hexmask.long.byte 0x0 24.--31. 1. "MMFC,Clear the malfunction monitor flag"
hexmask.long.byte 0x0 16.--23. 1. "CKLFC,Clear the clock loss flag"
bitfld.long 0x0 3. "RCDOFC,Clear the regular conversion data overflow flag" "0,1"
bitfld.long 0x0 2. "ICDOFC,Clear the inserted conversion data overflow flag" "0,1"
group.long 0x110++0x3
line.long 0x0 "FLT0ICGS,Filter 0 inserted channel group selection regist"
hexmask.long.byte 0x0 0.--7. 1. "ICGSEL,Inserted channel group selection"
group.long 0x190++0x3
line.long 0x0 "FLT1ICGS,Filter 1 inserted channel group selection regist"
hexmask.long.byte 0x0 0.--7. 1. "ICGSEL,Inserted channel group selection"
group.long 0x210++0x3
line.long 0x0 "FLT2ICGS,Filter 2 inserted channel group selection regist"
hexmask.long.byte 0x0 0.--7. 1. "ICGSEL,Inserted channel group selection"
group.long 0x290++0x3
line.long 0x0 "FLT3ICGS,Filter 3 inserted channel group selection regist"
hexmask.long.byte 0x0 0.--7. 1. "ICGSEL,Inserted channel group selection"
group.long 0x114++0x3
line.long 0x0 "FLT0SFCFG,Filter 0 sinc filter configuration regist"
bitfld.long 0x0 29.--31. "SFO,Sinc filter order" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0 16.--25. 1. "SFOR,Sinc filter oversampling ratio (decimation rate)"
hexmask.long.byte 0x0 0.--7. 1. "IOR,Integrator oversampling ratio"
group.long 0x194++0x3
line.long 0x0 "FLT1SFCFG,Filter 1 sinc filter configuration regist"
bitfld.long 0x0 29.--31. "SFO,Sinc filter order" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0 16.--25. 1. "SFOR,Sinc filter oversampling ratio (decimation rate)"
hexmask.long.byte 0x0 0.--7. 1. "IOR,Integrator oversampling ratio"
group.long 0x214++0x3
line.long 0x0 "FLT2SFCFG,Filter 2 sinc filter configuration regist"
bitfld.long 0x0 29.--31. "SFO,Sinc filter order" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0 16.--25. 1. "SFOR,Sinc filter oversampling ratio (decimation rate)"
hexmask.long.byte 0x0 0.--7. 1. "IOR,Integrator oversampling ratio"
group.long 0x294++0x3
line.long 0x0 "FLT3SFCFG,Filter 3 sinc filter configuration regist"
bitfld.long 0x0 29.--31. "SFO,Sinc filter order" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0 16.--25. 1. "SFOR,Sinc filter oversampling ratio (decimation rate)"
hexmask.long.byte 0x0 0.--7. 1. "IOR,Integrator oversampling ratio"
rgroup.long 0x118++0x3
line.long 0x0 "FLT0IDATA,Filter 0 inserted group conversion data regist"
hexmask.long.tbyte 0x0 8.--31. 1. "IDATA,Inserted group conversion data"
bitfld.long 0x0 0.--2. "ICCH,Inserted channel most recently converted" "0,1,2,3,4,5,6,7"
rgroup.long 0x198++0x3
line.long 0x0 "FLT1IDATA,Filter 1 inserted group conversion data regist"
hexmask.long.tbyte 0x0 8.--31. 1. "IDATA,Inserted group conversion data"
bitfld.long 0x0 0.--2. "ICCH,Inserted channel most recently converted" "0,1,2,3,4,5,6,7"
rgroup.long 0x218++0x3
line.long 0x0 "FLT2IDATA,Filter 2 inserted group conversion data regist"
hexmask.long.tbyte 0x0 8.--31. 1. "IDATA,Inserted group conversion data"
bitfld.long 0x0 0.--2. "ICCH,Inserted channel most recently converted" "0,1,2,3,4,5,6,7"
rgroup.long 0x298++0x3
line.long 0x0 "FLT3IDATA,Filter 3 inserted group conversion data regist"
hexmask.long.tbyte 0x0 8.--31. 1. "IDATA,Inserted group conversion data"
bitfld.long 0x0 0.--2. "ICCH,Inserted channel most recently converted" "0,1,2,3,4,5,6,7"
rgroup.long 0x11C++0x3
line.long 0x0 "FLT0RDATA,Filter 0 regular channel conversion data regist"
hexmask.long.tbyte 0x0 8.--31. 1. "RDATA,Regular channel conversion data"
bitfld.long 0x0 4. "RCHPDT,Regular channel pending data" "0,1"
bitfld.long 0x0 0.--2. "RCCH,Regular channel most recently converted" "0,1,2,3,4,5,6,7"
rgroup.long 0x19C++0x3
line.long 0x0 "FLT1RDATA,Filter 1 regular channel conversion data regist"
hexmask.long.tbyte 0x0 8.--31. 1. "RDATA,Regular channel conversion data"
bitfld.long 0x0 4. "RCHPDT,Regular channel pending data" "0,1"
bitfld.long 0x0 0.--2. "RCCH,Regular channel most recently converted" "0,1,2,3,4,5,6,7"
rgroup.long 0x21C++0x3
line.long 0x0 "FLT2RDATA,Filter 0 regular channel conversion data regist"
hexmask.long.tbyte 0x0 8.--31. 1. "RDATA,Regular channel conversion data"
bitfld.long 0x0 4. "RCHPDT,Regular channel pending data" "0,1"
bitfld.long 0x0 0.--2. "RCCH,Regular channel most recently converted" "0,1,2,3,4,5,6,7"
rgroup.long 0x29C++0x3
line.long 0x0 "FLT3RDATA,Filter 3 regular channel conversion data regist"
hexmask.long.tbyte 0x0 8.--31. 1. "RDATA,Regular channel conversion data"
bitfld.long 0x0 4. "RCHPDT,Regular channel pending data" "0,1"
bitfld.long 0x0 0.--2. "RCCH,Regular channel most recently converted" "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x0 "FLT0TMHT,Filter 0 threshold monitor high threshold regist"
hexmask.long.tbyte 0x0 8.--31. 1. "HTVAL,Threshold monitor high threshold value"
hexmask.long.byte 0x0 0.--3. 1. "HTBSD,High threshold event break signal distribution"
group.long 0x1A0++0x3
line.long 0x0 "FLT1TMHT,Filter 1 threshold monitor high threshold regist"
hexmask.long.tbyte 0x0 8.--31. 1. "HTVAL,Threshold monitor high threshold value"
hexmask.long.byte 0x0 0.--3. 1. "HTBSD,High threshold event break signal distribution"
group.long 0x220++0x3
line.long 0x0 "FLT2TMHT,Filter 2 threshold monitor high threshold regist"
hexmask.long.tbyte 0x0 8.--31. 1. "HTVAL,Threshold monitor high threshold value"
hexmask.long.byte 0x0 0.--3. 1. "HTBSD,High threshold event break signal distribution"
group.long 0x2A0++0x3
line.long 0x0 "FLT3TMHT,Filter 3 threshold monitor high threshold regist"
hexmask.long.tbyte 0x0 8.--31. 1. "HTVAL,Threshold monitor high threshold value"
hexmask.long.byte 0x0 0.--3. 1. "HTBSD,High threshold event break signal distribution"
group.long 0x124++0x3
line.long 0x0 "FLT0TMLT,Filter 0 threshold monitor low threshold regist"
hexmask.long.tbyte 0x0 8.--31. 1. "LTVAL,Threshold monitor low threshold value"
hexmask.long.byte 0x0 0.--3. 1. "LTBSD,Low threshold event break signal distribution"
group.long 0x1A4++0x3
line.long 0x0 "FLT1TMLT,Filter 1 threshold monitor low threshold regist"
hexmask.long.tbyte 0x0 8.--31. 1. "LTVAL,Threshold monitor low threshold value"
hexmask.long.byte 0x0 0.--3. 1. "LTBSD,Low threshold event break signal distribution"
group.long 0x224++0x3
line.long 0x0 "FLT2TMLT,Filter 2 threshold monitor low threshold regist"
hexmask.long.tbyte 0x0 8.--31. 1. "LTVAL,Threshold monitor low threshold value"
hexmask.long.byte 0x0 0.--3. 1. "LTBSD,Low threshold event break signal distribution"
group.long 0x2A4++0x3
line.long 0x0 "FLT3TMLT,Filter 3 threshold monitor low threshold regist"
hexmask.long.tbyte 0x0 8.--31. 1. "LTVAL,Threshold monitor low threshold value"
hexmask.long.byte 0x0 0.--3. 1. "LTBSD,Low threshold event break signal distribution"
rgroup.long 0x128++0x3
line.long 0x0 "FLT0TMSTAT,Filter 0 threshold monitor status regist"
hexmask.long.byte 0x0 8.--15. 1. "HTF,Threshold monitor high threshold flag"
hexmask.long.byte 0x0 0.--7. 1. "LTF,Threshold monitor low threshold flag"
rgroup.long 0x1A8++0x3
line.long 0x0 "FLT1TMSTAT,Filter 1 threshold monitor status regist"
hexmask.long.byte 0x0 8.--15. 1. "HTF,Threshold monitor high threshold flag"
hexmask.long.byte 0x0 0.--7. 1. "LTF,Threshold monitor low threshold flag"
rgroup.long 0x228++0x3
line.long 0x0 "FLT2TMSTAT,Filter 2 threshold monitor status regist"
hexmask.long.byte 0x0 8.--15. 1. "HTF,Threshold monitor high threshold flag"
hexmask.long.byte 0x0 0.--7. 1. "LTF,Threshold monitor low threshold flag"
rgroup.long 0x3A8++0x3
line.long 0x0 "FLT3TMSTAT,Filter 3 threshold monitor status regist"
hexmask.long.byte 0x0 8.--15. 1. "HTF,Threshold monitor high threshold flag"
hexmask.long.byte 0x0 0.--7. 1. "LTF,Threshold monitor low threshold flag"
group.long 0x12C++0x3
line.long 0x0 "FLT0TMFC,Filter 0 threshold monitor flag clear regist"
hexmask.long.byte 0x0 8.--15. 1. "HTFC,Clear the threshold monitor high threshold flag"
hexmask.long.byte 0x0 0.--7. 1. "LTFC,Clear the threshold monitor low threshold flag"
group.long 0x1AC++0x3
line.long 0x0 "FLT1TMFC,Filter 1 threshold monitor flag clear regist"
hexmask.long.byte 0x0 8.--15. 1. "HTFC,Clear the threshold monitor high threshold flag"
hexmask.long.byte 0x0 0.--7. 1. "LTFC,Clear the threshold monitor low threshold flag"
group.long 0x22C++0x3
line.long 0x0 "FLT2TMFC,Filter 2 threshold monitor flag clear regist"
hexmask.long.byte 0x0 8.--15. 1. "HTFC,Clear the threshold monitor high threshold flag"
hexmask.long.byte 0x0 0.--7. 1. "LTFC,Clear the threshold monitor low threshold flag"
group.long 0x2AC++0x3
line.long 0x0 "FLT3TMFC,Filter 3 threshold monitor flag clear regist"
hexmask.long.byte 0x0 8.--15. 1. "HTFC,Clear the threshold monitor high threshold flag"
hexmask.long.byte 0x0 0.--7. 1. "LTFC,Clear the threshold monitor low threshold flag"
rgroup.long 0x130++0x3
line.long 0x0 "FLT0EMMAX,Filter 0 extremes monitor maximum regist"
hexmask.long.tbyte 0x0 8.--31. 1. "MAXVAL,Extremes monitor maximum value"
bitfld.long 0x0 0.--2. "MAXDC,Extremes monitor maximum data channel" "0,1,2,3,4,5,6,7"
rgroup.long 0x1B0++0x3
line.long 0x0 "FLT1EMMAX,Filter 1 extremes monitor maximum regist"
hexmask.long.tbyte 0x0 8.--31. 1. "MAXVAL,Extremes monitor maximum value"
bitfld.long 0x0 0.--2. "MAXDC,Extremes monitor maximum data channel" "0,1,2,3,4,5,6,7"
rgroup.long 0x230++0x3
line.long 0x0 "FLT2EMMAX,Filter 2 extremes monitor maximum regist"
hexmask.long.tbyte 0x0 8.--31. 1. "MAXVAL,Extremes monitor maximum value"
bitfld.long 0x0 0.--2. "MAXDC,Extremes monitor maximum data channel" "0,1,2,3,4,5,6,7"
rgroup.long 0x2B0++0x3
line.long 0x0 "FLT3EMMAX,Filter 3 extremes monitor maximum regist"
hexmask.long.tbyte 0x0 8.--31. 1. "MAXVAL,Extremes monitor maximum value"
bitfld.long 0x0 0.--2. "MAXDC,Extremes monitor maximum data channel" "0,1,2,3,4,5,6,7"
rgroup.long 0x134++0x3
line.long 0x0 "FLT0EMMIN,Filter 0 extremes monitor minimum regist"
hexmask.long.tbyte 0x0 8.--31. 1. "MINVAL,Extremes monitor minimum value"
bitfld.long 0x0 0.--2. "MINDC,Extremes monitor minimum data channel" "0,1,2,3,4,5,6,7"
rgroup.long 0x1B4++0x3
line.long 0x0 "FLT1EMMIN,Filter 1 extremes monitor minimum regist"
hexmask.long.tbyte 0x0 8.--31. 1. "MINVAL,Extremes monitor minimum value"
bitfld.long 0x0 0.--2. "MINDC,Extremes monitor minimum data channel" "0,1,2,3,4,5,6,7"
rgroup.long 0x234++0x3
line.long 0x0 "FLT2EMMIN,Filter 2 extremes monitor minimum regist"
hexmask.long.tbyte 0x0 8.--31. 1. "MINVAL,Extremes monitor minimum value"
bitfld.long 0x0 0.--2. "MINDC,Extremes monitor minimum data channel" "0,1,2,3,4,5,6,7"
rgroup.long 0x2B4++0x3
line.long 0x0 "FLT3EMMIN,Filter 3 extremes monitor minimum regist"
hexmask.long.tbyte 0x0 8.--31. 1. "MINVAL,Extremes monitor minimum value"
bitfld.long 0x0 0.--2. "MINDC,Extremes monitor minimum data channel" "0,1,2,3,4,5,6,7"
rgroup.long 0x138++0x3
line.long 0x0 "FLT0CT,Filter 0 conversion timer register"
hexmask.long 0x0 4.--31. 1. "CTCNT,Extremes monitor minimum value"
rgroup.long 0x1B8++0x3
line.long 0x0 "FLT1CT,Filter 1 conversion timer register"
hexmask.long 0x0 4.--31. 1. "CTCNT,Extremes monitor minimum value"
rgroup.long 0x238++0x3
line.long 0x0 "FLT2CT,Filter 2 conversion timer register"
hexmask.long 0x0 4.--31. 1. "CTCNT,Extremes monitor minimum value"
rgroup.long 0x2B8++0x3
line.long 0x0 "FLT3CT,Filter 3 conversion timer register"
hexmask.long 0x0 4.--31. 1. "CTCNT,Timer counting conversion time"
tree.end
tree "HRTIMER (High-Resolution Timer)"
base ad:0x0
tree "HRTIMER_COMMON"
base ad:0x40015B80
group.long 0x0++0x7
line.long 0x0 "CTL0,HRTIMER control register 0"
bitfld.long 0x0 31. "ADTG3USRC_3,HRTIMER_ADTRIG3 update source" "0,1"
bitfld.long 0x0 30. "ADTG2USRC_3,HRTIMER_ADTRIG2 update source" "0,1"
bitfld.long 0x0 29. "ADTG1USRC_3,HRTIMER_ADTRIG1 update source" "0,1"
bitfld.long 0x0 28. "ADTG0USRC_3,HRTIMER_ADTRIG0 update source" "0,1"
bitfld.long 0x0 25.--27. "ADTG3USRC0_2,HRTIMER_ADTRIG3 update source" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 22.--24. "ADTG2USRC0_2,HRTIMER_ADTRIG2 update source" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 19.--21. "ADTG1USRC0_2,HRTIMER_ADTRIG1 update source" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16.--18. "ADTG0USRC0_2,HRTIMER_ADTRIG0 update source" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 8. "ST7UPDIS,Slave_TIMER7 update disable" "0,1"
bitfld.long 0x0 7. "ST6UPDIS,Slave_TIMER6 update disable" "0,1"
bitfld.long 0x0 6. "ST5UPDIS,Slave_TIMER5 update disable" "0,1"
bitfld.long 0x0 5. "ST4UPDIS,Slave_TIMER4 update disable" "0,1"
bitfld.long 0x0 4. "ST3UPDIS,Slave_TIMER3 update disable" "0,1"
bitfld.long 0x0 3. "ST2UPDIS,Slave_TIMER2 update disable" "0,1"
newline
bitfld.long 0x0 2. "ST1UPDIS,Slave_TIMER1 update disable" "0,1"
bitfld.long 0x0 1. "ST0UPDIS,Slave_TIMER0 update disable" "0,1"
bitfld.long 0x0 0. "MTUPDIS,Master_TIMER update disable" "0,1"
line.long 0x4 "CTL1,HRTIMER control register 1"
bitfld.long 0x4 29. "ST7SRST,Slave_TIMER7 software reset" "0,1"
bitfld.long 0x4 28. "ST7SUP,Slave_TIMER7 software update" "0,1"
bitfld.long 0x4 23. "EXC7,Exchange Slave_TIMER7 outputs" "0,1"
bitfld.long 0x4 22. "EXC6,Exchange Slave_TIMER6 outputs" "0,1"
bitfld.long 0x4 21. "EXC5,Exchange Slave_TIMER5 outputs" "0,1"
bitfld.long 0x4 20. "EXC4,Exchange Slave_TIMER4 outputs" "0,1"
bitfld.long 0x4 19. "EXC3,Exchange Slave_TIMER3 outputs" "0,1"
newline
bitfld.long 0x4 18. "EXC2,Exchange Slave_TIMER2 outputs" "0,1"
bitfld.long 0x4 17. "EXC1,Exchange Slave_TIMER1 outputs" "0,1"
bitfld.long 0x4 16. "EXC0,Exchange Slave_TIMER0 outputs" "0,1"
bitfld.long 0x4 15. "ST6SRST,Slave_TIMER6 software reset" "0,1"
bitfld.long 0x4 14. "ST5SRST,Slave_TIMER5 software reset" "0,1"
bitfld.long 0x4 13. "ST4SRST,Slave_TIMER4 software reset" "0,1"
bitfld.long 0x4 12. "ST3SRST,Slave_TIMER3 software reset" "0,1"
newline
bitfld.long 0x4 11. "ST2SRST,Slave_TIMER2 software reset" "0,1"
bitfld.long 0x4 10. "ST1SRST,Slave_TIMER1 software reset" "0,1"
bitfld.long 0x4 9. "ST0SRST,Slave_TIMER0 software reset" "0,1"
bitfld.long 0x4 8. "MTSRST,Master_TIMER software reset" "0,1"
bitfld.long 0x4 7. "ST6SUP,Slave_TIMER6 software update" "0,1"
bitfld.long 0x4 6. "ST5SUP,Slave_TIMER5 software update" "0,1"
bitfld.long 0x4 5. "ST4SUP,Slave_TIMER4 software update" "0,1"
newline
bitfld.long 0x4 4. "ST3SUP,Slave_TIMER3 software update" "0,1"
bitfld.long 0x4 3. "ST2SUP,Slave_TIMER2 software update" "0,1"
bitfld.long 0x4 2. "ST1SUP,Slave_TIMER1 software update" "0,1"
bitfld.long 0x4 1. "ST0SUP,Slave_TIMER0 software update" "0,1"
bitfld.long 0x4 0. "MTSUP,Master_TIMER software update" "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "INTF,HRTIMER interrupt flag register"
bitfld.long 0x0 17. "BMPERIF,Bunch mode period interrupt flag" "0,1"
bitfld.long 0x0 16. "DLLCALIF,DLL calibration completed interrupt flag" "0,1"
bitfld.long 0x0 8. "FLT7IF,Fault 7 interrupt flag" "0,1"
bitfld.long 0x0 7. "FLT6IF,Fault 6 interrupt flag" "0,1"
bitfld.long 0x0 6. "FLT5IF,Fault 5 interrupt flag" "0,1"
bitfld.long 0x0 5. "SYSFLTIF,System fault interrupt flag" "0,1"
bitfld.long 0x0 4. "FLT4IF,Fault 4 interrupt flag" "0,1"
newline
bitfld.long 0x0 3. "FLT3IF,Fault 3 interrupt flag" "0,1"
bitfld.long 0x0 2. "FLT2IF,Fault 2 interrupt flag" "0,1"
bitfld.long 0x0 1. "FLT1IF,Fault 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "FLT0IF,Fault 0 interrupt flag" "0,1"
wgroup.long 0xC++0x3
line.long 0x0 "INTC,HRTIMER interrupt flag clear register"
bitfld.long 0x0 17. "BMPERIFC,Clear bunch mode period interrupt flag" "0,1"
bitfld.long 0x0 16. "DLLCALIFC,Clear DLL calibration completed interrupt flag" "0,1"
bitfld.long 0x0 8. "FLT7IFC,Clear fault 7 interrupt flag" "0,1"
bitfld.long 0x0 7. "FLT6IFC,Clear fault 6 interrupt flag" "0,1"
bitfld.long 0x0 6. "FLT5IFC,Clear fault 5 interrupt flag" "0,1"
bitfld.long 0x0 5. "SYSFLTIFC,Clear system fault interrupt flag" "0,1"
bitfld.long 0x0 4. "FLT4IFC,Clear fault 4 interrupt flag" "0,1"
newline
bitfld.long 0x0 3. "FLT3IFC,Clear fault 3 interrupt flag" "0,1"
bitfld.long 0x0 2. "FLT2IFC,Clear fault 2 interrupt flag" "0,1"
bitfld.long 0x0 1. "FLT1IFC,Clear fault 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "FLT0IFC,Clear fault 0 interrupt flag" "0,1"
group.long 0x10++0x7
line.long 0x0 "INTEN,HRTIMER interrupt enable register"
bitfld.long 0x0 17. "BMPERIE,Bunch mode period interrupt enable" "0,1"
bitfld.long 0x0 16. "DLLCALIE,DLL calibration completed interrupt enable" "0,1"
bitfld.long 0x0 8. "FLT7IE,fault 7 interrupt enable" "0,1"
bitfld.long 0x0 7. "FLT6IE,fault 6 interrupt enable" "0,1"
bitfld.long 0x0 6. "FLT5IE,fault 5 interrupt enable" "0,1"
bitfld.long 0x0 5. "SYSFLTIE,System fault interrupt enable" "0,1"
bitfld.long 0x0 4. "FLT4IE,fault 4 interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "FLT3IE,fault 3 interrupt enable" "0,1"
bitfld.long 0x0 2. "FLT2IE,fault 2 interrupt enable" "0,1"
bitfld.long 0x0 1. "FLT1IE,fault 1 interrupt enable" "0,1"
bitfld.long 0x0 0. "FLT0IE,fault 0 interrupt enable" "0,1"
line.long 0x4 "CHOUTEN,HRTIMER channel output enable register"
bitfld.long 0x4 15. "ST7CH1EN,Slave_TIMER7 channel 1 output (ST7CH1_O) enable" "0,1"
bitfld.long 0x4 14. "ST7CH0EN,Slave_TIMER7 channel 0 output (ST7CH0_O) enable" "0,1"
bitfld.long 0x4 13. "ST6CH1EN,Slave_TIMER6 channel 1 output (ST6CH1_O) enable" "0,1"
bitfld.long 0x4 12. "ST6CH0EN,Slave_TIMER6 channel 0 output (ST6CH0_O) enable" "0,1"
bitfld.long 0x4 11. "ST5CH1EN,Slave_TIMER5 channel 1 output (ST5CH1_O) enable" "0,1"
bitfld.long 0x4 10. "ST5CH0EN,Slave_TIMER5 channel 0 output (ST5CH0_O) enable" "0,1"
bitfld.long 0x4 9. "ST4CH1EN,Slave_TIMER4 channel 1 output (ST4CH1_O) enable" "0,1"
newline
bitfld.long 0x4 8. "ST4CH0EN,Slave_TIMER4 channel 0 output (ST4CH0_O) enable" "0,1"
bitfld.long 0x4 7. "ST3CH1EN,Slave_TIMER3 channel 1 output (ST3CH1_O) enable" "0,1"
bitfld.long 0x4 6. "ST3CH0EN,Slave_TIMER3 channel 0 output (ST3CH0_O) enable" "0,1"
bitfld.long 0x4 5. "ST2CH1EN,Slave_TIMER2 channel 1 output (ST2CH1_O) enable" "0,1"
bitfld.long 0x4 4. "ST2CH0EN,Slave_TIMER2 channel 0 output (ST2CH0_O) enable" "0,1"
bitfld.long 0x4 3. "ST1CH1EN,Slave_TIMER1 channel 1 output (ST1CH1_O) enable" "0,1"
bitfld.long 0x4 2. "ST1CH0EN,Slave_TIMER1 channel 0 output (ST1CH0_O) enable" "0,1"
newline
bitfld.long 0x4 1. "ST0CH1EN,Slave_TIMER0 channel 1 output (ST0CH1_O) enable" "0,1"
bitfld.long 0x4 0. "ST0CH0EN,Slave_TIMER0 channel 0 output (ST0CH0_O) enable" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "CHOUTDIS,HRTIMER channel output disable register"
bitfld.long 0x0 15. "ST7CH1DIS,Slave_TIMER7 channel 1 output (ST7CH1_O) disable" "0,1"
bitfld.long 0x0 14. "ST7CH0DIS,Slave_TIMER7 channel 0 output (ST7CH0_O) disable" "0,1"
bitfld.long 0x0 13. "ST6CH1DIS,Slave_TIMER6 channel 1 output (ST6CH1_O) disable" "0,1"
bitfld.long 0x0 12. "ST6CH0DIS,Slave_TIMER6 channel 0 output (ST6CH0_O) disable" "0,1"
bitfld.long 0x0 11. "ST5CH1DIS,Slave_TIMER5 channel 1 output (ST5CH1_O) disable" "0,1"
bitfld.long 0x0 10. "ST5CH0DIS,Slave_TIMER5 channel 0 output (ST5CH0_O) disable" "0,1"
bitfld.long 0x0 9. "ST4CH1DIS,Slave_TIMER4 channel 1 output (ST4CH1_O) disable" "0,1"
newline
bitfld.long 0x0 8. "ST4CH0DIS,Slave_TIMER4 channel 0 output (ST4CH0_O) disable" "0,1"
bitfld.long 0x0 7. "ST3CH1DIS,Slave_TIMER3 channel 1 output (ST3CH1_O) disable" "0,1"
bitfld.long 0x0 6. "ST3CH0DIS,Slave_TIMER3 channel 0 output (ST3CH0_O) disable" "0,1"
bitfld.long 0x0 5. "ST2CH1DIS,Slave_TIMER2 channel 1 output (ST2CH1_O) disable" "0,1"
bitfld.long 0x0 4. "ST2CH0DIS,Slave_TIMER2 channel 0 output (ST2CH0_O) disable" "0,1"
bitfld.long 0x0 3. "ST1CH1DIS,Slave_TIMER1 channel 1 output (ST1CH1_O) disable" "0,1"
bitfld.long 0x0 2. "ST1CH0DIS,Slave_TIMER1 channel 0 output (ST1CH0_O) disable" "0,1"
newline
bitfld.long 0x0 1. "ST0CH1DIS,Slave_TIMER0 channel 1 output (ST0CH1_O) disable" "0,1"
bitfld.long 0x0 0. "ST0CH0DIS,Slave_TIMER0 channel 0 output (ST0CH0_O) disable" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "CHOUTDISF,HRTIMER channel output disable flag register"
bitfld.long 0x0 15. "ST7CH1DISF,Slave_TIMER7 channel 1 output (ST7CH1_O) disable flag" "0,1"
bitfld.long 0x0 14. "ST7CH0DISF,Slave_TIMER7 channel 0 output (ST7CH0_O) disable flag" "0,1"
bitfld.long 0x0 13. "ST6CH1DISF,Slave_TIMER6 channel 1 output (ST6CH1_O) disable flag" "0,1"
bitfld.long 0x0 12. "ST6CH0DISF,Slave_TIMER6 channel 0 output (ST6CH0_O) disable flag" "0,1"
bitfld.long 0x0 11. "ST5CH1DISF,Slave_TIMER5 channel 1 output (ST5CH1_O) disable flag" "0,1"
bitfld.long 0x0 10. "ST5CH0DISF,Slave_TIMER5 channel 0 output (ST5CH0_O) disable flag" "0,1"
bitfld.long 0x0 9. "ST4CH1DISF,Slave_TIMER4 channel 1 output (ST4CH1_O) disable flag" "0,1"
newline
bitfld.long 0x0 8. "ST4CH0DISF,Slave_TIMER4 channel 0 output (ST4CH0_O) disable flag" "0,1"
bitfld.long 0x0 7. "ST3CH1DISF,Slave_TIMER3 channel 1 output (ST3CH1_O) disable flag" "0,1"
bitfld.long 0x0 6. "ST3CH0DISF,Slave_TIMER3 channel 0 output (ST3CH0_O) disable flag" "0,1"
bitfld.long 0x0 5. "ST2CH1DISF,Slave_TIMER2 channel 1 output (ST2CH1_O) disable flag" "0,1"
bitfld.long 0x0 4. "ST2CH0DISF,Slave_TIMER2 channel 0 output (ST2CH0_O) disable flag" "0,1"
bitfld.long 0x0 3. "ST1CH1DISF,Slave_TIMER1 channel 1 output (ST1CH1_O) disable flag" "0,1"
bitfld.long 0x0 2. "ST1CH0DISF,Slave_TIMER1 channel 0 output (ST1CH0_O) disable flag" "0,1"
newline
bitfld.long 0x0 1. "ST0CH1DISF,Slave_TIMER0 channel 1 output (ST0CH1_O) disable flag" "0,1"
bitfld.long 0x0 0. "ST0CH0DISF,Slave_TIMER0 channel 0 output (ST0CH0_O) disable flag" "0,1"
group.long 0x20++0x4F
line.long 0x0 "BMCTL,HRTIMER bunch mode control register"
bitfld.long 0x0 31. "BMOPTF,Bunch mode operating flag" "0,1"
bitfld.long 0x0 24. "BMST7,Slave_TIMER7 bunch mode" "0,1"
bitfld.long 0x0 23. "BMST6,Slave_TIMER6 bunch mode" "0,1"
bitfld.long 0x0 22. "BMST5,Slave_TIMER5 bunch mode" "0,1"
bitfld.long 0x0 21. "BMST4,Slave_TIMER4 bunch mode" "0,1"
bitfld.long 0x0 20. "BMST3,Slave_TIMER3 bunch mode" "0,1"
bitfld.long 0x0 19. "BMST2,Slave_TIMER2 bunch mode" "0,1"
newline
bitfld.long 0x0 18. "BMST1,Slave_TIMER1 bunch mode" "0,1"
bitfld.long 0x0 17. "BMST0,Slave_TIMER0 bunch mode" "0,1"
bitfld.long 0x0 16. "BMMT,Master_TIMER bunch mode" "0,1"
bitfld.long 0x0 10. "BMSE,Bunch mode shadow enable" "0,1"
hexmask.long.byte 0x0 6.--9. 1. "BMPSC,Bunch mode clock division"
hexmask.long.byte 0x0 2.--5. 1. "BMCLKS,Bunch mode clock source"
bitfld.long 0x0 1. "BMCTN,Continuous mode in bunch mode" "0,1"
newline
bitfld.long 0x0 0. "BMEN,Bunch mode enable" "0,1"
line.long 0x4 "BMSTRG,HRTIMER bunch mode start trigger register"
bitfld.long 0x4 31. "CISGN,Chip internal signal triggers bunch mode operation" "0,1"
bitfld.long 0x4 30. "EXEV7,External event 7 triggers bunch mode operation" "0,1"
bitfld.long 0x4 29. "EXEV6,External event 6 triggers bunch mode operation" "0,1"
bitfld.long 0x4 28. "ST3EXEV7,Slave_TIMER3 period event following external event 7 triggers bunch mode operation" "0,1"
bitfld.long 0x4 27. "ST0EXEV6,Slave_TIMER0 period event following external event 6 triggers bunch mode operation" "0,1"
bitfld.long 0x4 26. "ST4CMP1,Slave_TIMER4 compare 1 event triggers bunch mode operation" "0,1"
bitfld.long 0x4 25. "ST4CMP0,Slave_TIMER4 compare 0 event triggers bunch mode operation" "0,1"
newline
bitfld.long 0x4 24. "ST4REP,Slave_TIMER4 repetition event triggers bunch mode operation" "0,1"
bitfld.long 0x4 23. "ST4RST,Slave_TIMER4 reset event triggers bunch mode operation" "0,1"
bitfld.long 0x4 22. "ST3CMP1,Slave_TIMER3 compare 1 event triggers bunch mode operation" "0,1"
bitfld.long 0x4 21. "ST3CMP0,Slave_TIMER3 compare 0 event triggers bunch mode operation" "0,1"
bitfld.long 0x4 20. "ST3REP,Slave_TIMER3 repetition event triggers bunch mode operation" "0,1"
bitfld.long 0x4 19. "ST3RST,Slave_TIMER3 reset event triggers bunch mode operation" "0,1"
bitfld.long 0x4 18. "ST2CMP1,Slave_TIMER2 compare 1 event triggers bunch mode operation" "0,1"
newline
bitfld.long 0x4 17. "ST2CMP0,Slave_TIMER2 compare 0 event triggers bunch mode operation" "0,1"
bitfld.long 0x4 16. "ST2REP,Slave_TIMER2 repetition event triggers bunch mode operation" "0,1"
bitfld.long 0x4 15. "ST2RST,Slave_TIMER2 reset event triggers bunch mode operation" "0,1"
bitfld.long 0x4 14. "ST1CMP1,Slave_TIMER1 compare 1 event triggers bunch mode operation" "0,1"
bitfld.long 0x4 13. "ST1CMP0,Slave_TIMER1 compare 0 event triggers bunch mode operation" "0,1"
bitfld.long 0x4 12. "ST1REP,Slave_TIMER1 repetition event triggers bunch mode operation" "0,1"
bitfld.long 0x4 11. "ST1RST,Slave_TIMER1 reset event triggers bunch mode operation" "0,1"
newline
bitfld.long 0x4 10. "ST0CMP1,Slave_TIMER0 compare 1 event triggers bunch mode operation" "0,1"
bitfld.long 0x4 9. "ST0CMP0,Slave_TIMER0 compare 0 event triggers bunch mode operation" "0,1"
bitfld.long 0x4 8. "ST0REP,Slave_TIMER0 repetition event triggers bunch mode operation" "0,1"
bitfld.long 0x4 7. "ST0RST,Slave_TIMER0 reset event triggers bunch mode operation" "0,1"
bitfld.long 0x4 6. "MTCMP3,Master_TIMER compare 3 event triggers bunch mode operation" "0,1"
bitfld.long 0x4 5. "MTCMP2,Master_TIMER compare 2 event triggers bunch mode operation" "0,1"
bitfld.long 0x4 4. "MTCMP1,Master_TIMER compare 1 event triggers bunch mode operation" "0,1"
newline
bitfld.long 0x4 3. "MTCMP0,Master_TIMER compare 0 event triggers bunch mode operation" "0,1"
bitfld.long 0x4 2. "MTREP,Master_TIMER repetition event triggers bunch mode operation" "0,1"
bitfld.long 0x4 1. "MTRST,Master_TIMER reset event triggers bunch mode operation" "0,1"
bitfld.long 0x4 0. "SWTRG,Software triggers bunch mode operation" "0,1"
line.long 0x8 "BMCMPV,HRTIMER bunch mode compare value register"
hexmask.long.word 0x8 0.--15. 1. "BMCMPVAL,Bunch mode compare value"
line.long 0xC "BMCAR,HRTIMER bunch mode counter auto reload register"
hexmask.long.word 0xC 0.--15. 1. "BMCARL,Bunch mode counter auto reload value"
line.long 0x10 "EXEVCFG0,HRTIMER external event configuration register 0"
bitfld.long 0x10 29. "EXEV4FAST,External Event 4 fast mode" "0,1"
bitfld.long 0x10 27.--28. "EXEV4EG,External event 4 edge sensitivity" "0,1,2,3"
bitfld.long 0x10 26. "EXEV4P,External event 4 polarity" "0,1"
bitfld.long 0x10 24.--25. "EXEV4SRC,External event 4 source" "0,1,2,3"
bitfld.long 0x10 23. "EXEV3FAST,External Event 3 fast mode" "0,1"
bitfld.long 0x10 21.--22. "EXEV3EG,External event 3 edge sensitivity" "0,1,2,3"
bitfld.long 0x10 20. "EXEV3P,External event 3 polarity" "0,1"
newline
bitfld.long 0x10 18.--19. "EXEV3SRC,External event 3 source" "0,1,2,3"
bitfld.long 0x10 17. "EXEV2FAST,External Event 2 fast mode" "0,1"
bitfld.long 0x10 15.--16. "EXEV2EG,External event 2 edge sensitivity" "0,1,2,3"
bitfld.long 0x10 14. "EXEV2P,External event 2 polarity" "0,1"
bitfld.long 0x10 12.--13. "EXEV2SRC,External event 2 source" "0,1,2,3"
bitfld.long 0x10 11. "EXEV1FAST,External Event 1 fast mode" "0,1"
bitfld.long 0x10 9.--10. "EXEV1EG,External event 1 edge sensitivity" "0,1,2,3"
newline
bitfld.long 0x10 8. "EXEV1P,External event 1 polarity" "0,1"
bitfld.long 0x10 6.--7. "EXEV1SRC,External event 1 source" "0,1,2,3"
bitfld.long 0x10 5. "EXEV0FAST,External Event 0 fast mode" "0,1"
bitfld.long 0x10 3.--4. "EXEV0EG,External event 0 edge sensitivity" "0,1,2,3"
bitfld.long 0x10 2. "EXEV0P,External event 0 polarity" "0,1"
bitfld.long 0x10 0.--1. "EXEV0SRC,External event 0 source" "0,1,2,3"
line.long 0x14 "EXEVCFG1,HRTIMER external event configuration register 1"
bitfld.long 0x14 27.--28. "EXEV9EG,External event 9 edge sensitivity" "0,1,2,3"
bitfld.long 0x14 26. "EXEV9P,External event 9 polarity" "0,1"
bitfld.long 0x14 24.--25. "EXEV9SRC,External event 9 source" "0,1,2,3"
bitfld.long 0x14 21.--22. "EXEV8EG,External event 8 edge sensitivity" "0,1,2,3"
bitfld.long 0x14 20. "EXEV8P,External event 8 polarity" "0,1"
bitfld.long 0x14 18.--19. "EXEV8SRC,External event 8 source" "0,1,2,3"
bitfld.long 0x14 15.--16. "EXEV7EG,External event 7 edge sensitivity" "0,1,2,3"
newline
bitfld.long 0x14 14. "EXEV7P,External event 7 polarity" "0,1"
bitfld.long 0x14 12.--13. "EXEV7SRC,External event 7 source" "0,1,2,3"
bitfld.long 0x14 9.--10. "EXEV6EG,External event 6 edge sensitivity" "0,1,2,3"
bitfld.long 0x14 8. "EXEV6P,External event 6 polarity" "0,1"
bitfld.long 0x14 6.--7. "EXEV6SRC,External event 6 source" "0,1,2,3"
bitfld.long 0x14 3.--4. "EXEV5EG,External event 5 edge sensitivity" "0,1,2,3"
bitfld.long 0x14 2. "EXEV5P,External event 5 polarity" "0,1"
newline
bitfld.long 0x14 0.--1. "EXEV5SRC,External event 5 source" "0,1,2,3"
line.long 0x18 "EXEVDFCTL,HRTIMER external event digital filter control register"
bitfld.long 0x18 30.--31. "EXEVFDIV,External event clock division" "0,1,2,3"
hexmask.long.byte 0x18 24.--27. 1. "EXEV9FC,External event 9 filter control"
hexmask.long.byte 0x18 18.--21. 1. "EXEV8FC,External event 8 filter control"
hexmask.long.byte 0x18 12.--15. 1. "EXEV7FC,External event 7 filter control"
hexmask.long.byte 0x18 6.--9. 1. "EXEV6FC,External event 6 filter control"
hexmask.long.byte 0x18 0.--3. 1. "EXEV5FC,External event 5 filter control"
line.long 0x1C "ADCTRIGS0,HRTIMER trigger source 0 to ADC register"
bitfld.long 0x1C 31. "TRG0ST4PER,HRTIMER_ADCTRIG0 on Slave_TIMER4 period event" "0,1"
bitfld.long 0x1C 30. "TRG0ST4C3,HRTIMER_ADCTRIG0 on Slave_TIMER4 compare 3 event" "0,1"
bitfld.long 0x1C 29. "TRG0ST4C2,HRTIMER_ADCTRIG0 on Slave_TIMER4 compare 2 event" "0,1"
bitfld.long 0x1C 28. "TRG0ST4C1,HRTIMER_ADCTRIG0 on Slave_TIMER4 compare 1 event" "0,1"
bitfld.long 0x1C 27. "TRG0ST3PER,HRTIMER_ADCTRIG0 on Slave_TIMER3 period event" "0,1"
bitfld.long 0x1C 26. "TRG0ST3C3,HRTIMER_ADCTRIG0 on Slave_TIMER3 compare 3 event" "0,1"
bitfld.long 0x1C 25. "TRG0ST3C2,HRTIMER_ADCTRIG0 on Slave_TIMER3 compare 2 event" "0,1"
newline
bitfld.long 0x1C 24. "TRG0ST3C1,HRTIMER_ADCTRIG0 on Slave_TIMER3 compare 1 event" "0,1"
bitfld.long 0x1C 23. "TRG0ST2PER,HRTIMER_ADCTRIG0 on Slave_TIMER2 period event" "0,1"
bitfld.long 0x1C 22. "TRG0ST2C3,HRTIMER_ADCTRIG0 on Slave_TIMER2 compare 3 event" "0,1"
bitfld.long 0x1C 21. "TRG0ST2C2,HRTIMER_ADCTRIG0 on Slave_TIMER2 compare 2 event" "0,1"
bitfld.long 0x1C 20. "TRG0ST2C1,HRTIMER_ADCTRIG0 on Slave_TIMER2 compare 1 event" "0,1"
bitfld.long 0x1C 19. "TRG0ST1RST,HRTIMER_ADCTRIG0 on Slave_TIMER1 reset" "0,1"
bitfld.long 0x1C 18. "TRG0ST1PER,HRTIMER_ADCTRIG0 on Slave_TIMER1 period event" "0,1"
newline
bitfld.long 0x1C 17. "TRG0ST1C3,HRTIMER_ADCTRIG0 on Slave_TIMER1 compare 3 event" "0,1"
bitfld.long 0x1C 16. "TRG0ST1C2,HRTIMER_ADCTRIG0 on Slave_TIMER1 compare 2 event" "0,1"
bitfld.long 0x1C 15. "TRG0ST1C1,HRTIMER_ADCTRIG0 on Slave_TIMER1 compare 1 event" "0,1"
bitfld.long 0x1C 14. "TRG0ST0RST,HRTIMER_ADCTRIG0 on Slave_TIMER0 reset" "0,1"
bitfld.long 0x1C 13. "TRG0ST0PER,HRTIMER_ADCTRIG0 on Slave_TIMER0 period event" "0,1"
bitfld.long 0x1C 12. "TRG0ST0C3,HRTIMER_ADCTRIG0 on Slave_TIMER0 compare 3 event" "0,1"
bitfld.long 0x1C 11. "TRG0ST0C2,HRTIMER_ADCTRIG0 on Slave_TIMER0 compare 2 event" "0,1"
newline
bitfld.long 0x1C 10. "TRG0ST0C1,HRTIMER_ADCTRIG0 on Slave_TIMER0 compare 1 event" "0,1"
bitfld.long 0x1C 9. "TRG0EXEV4,HRTIMER_ADCTRIG0 on external event 4" "0,1"
bitfld.long 0x1C 8. "TRG0EXEV3,HRTIMER_ADCTRIG0 on external event 3" "0,1"
bitfld.long 0x1C 7. "TRG0EXEV2,HRTIMER_ADCTRIG0 on external event 2" "0,1"
bitfld.long 0x1C 6. "TRG0EXEV1,HRTIMER_ADCTRIG0 on external event 1" "0,1"
bitfld.long 0x1C 5. "TRG0EXEV0,HRTIMER_ADCTRIG0 on external event 0" "0,1"
bitfld.long 0x1C 4. "TRG0MTPER,HRTIMER_ADCTRIG0 on Master_TIMER period event" "0,1"
newline
bitfld.long 0x1C 3. "TRG0MTC3,HRTIMER_ADCTRIG0 on Master_TIMER compare 3 event" "0,1"
bitfld.long 0x1C 2. "TRG0MTC2,HRTIMER_ADCTRIG0 on Master_TIMER compare 2 event" "0,1"
bitfld.long 0x1C 1. "TRG0MTC1,HRTIMER_ADCTRIG0 on Master_TIMER compare 1 event" "0,1"
bitfld.long 0x1C 0. "TRG0MTC0,HRTIMER_ADCTRIG0 on Master_TIMER compare 0 event" "0,1"
line.long 0x20 "ADCTRIGS1,HRTIMER trigger source 1 to ADC register"
bitfld.long 0x20 31. "TRG1ST4RST,HRTIMER_ADCTRIG1 on Slave_TIMER4 reset" "0,1"
bitfld.long 0x20 30. "TRG1ST4C3,HRTIMER_ADCTRIG1 on Slave_TIMER4 compare 3 event" "0,1"
bitfld.long 0x20 29. "TRG1ST4C2,HRTIMER_ADCTRIG1 on Slave_TIMER4 compare 2 event" "0,1"
bitfld.long 0x20 28. "TRG1ST4C1,HRTIMER_ADCTRIG1 on Slave_TIMER4 compare 1 event" "0,1"
bitfld.long 0x20 27. "TRG1ST3RST,HRTIMER_ADCTRIG1 on Slave_TIMER3 reset" "0,1"
bitfld.long 0x20 26. "TRG1ST3PER,HRTIMER_ADCTRIG1 on Slave_TIMER3 period event" "0,1"
bitfld.long 0x20 25. "TRG1ST3C3,HRTIMER_ADCTRIG1 on Slave_TIMER3 compare 3 event" "0,1"
newline
bitfld.long 0x20 24. "TRG1ST3C2,HRTIMER_ADCTRIG1 on Slave_TIMER3 compare 2 event" "0,1"
bitfld.long 0x20 23. "TRG1ST3C1,HRTIMER_ADCTRIG1 on Slave_TIMER3 compare 1 event" "0,1"
bitfld.long 0x20 22. "TRG1ST2RST,HRTIMER_ADCTRIG1 on Slave_TIMER2 reset" "0,1"
bitfld.long 0x20 21. "TRG1ST2PER,HRTIMER_ADCTRIG1 on Slave_TIMER2 period event" "0,1"
bitfld.long 0x20 20. "TRG1ST2C3,HRTIMER_ADCTRIG1 on Slave_TIMER2 compare 3 event" "0,1"
bitfld.long 0x20 19. "TRG1ST2C2,HRTIMER_ADCTRIG1 on Slave_TIMER2 compare 2 event" "0,1"
bitfld.long 0x20 18. "TRG1ST2C1,HRTIMER_ADCTRIG1 on Slave_TIMER2 compare 1 event" "0,1"
newline
bitfld.long 0x20 17. "TRG1ST1PER,HRTIMER_ADCTRIG1 on Slave_TIMER1 period event" "0,1"
bitfld.long 0x20 16. "TRG1ST1C3,HRTIMER_ADCTRIG1 on Slave_TIMER1 compare 3 event" "0,1"
bitfld.long 0x20 15. "TRG1ST1C2,HRTIMER_ADCTRIG1 on Slave_TIMER1 compare 2 event" "0,1"
bitfld.long 0x20 14. "TRG1ST1C1,HRTIMER_ADCTRIG1 on Slave_TIMER1 compare 1 event" "0,1"
bitfld.long 0x20 13. "TRG1ST0PER,HRTIMER_ADCTRIG1 on Slave_TIMER0 period event" "0,1"
bitfld.long 0x20 12. "TRG1ST0C3,HRTIMER_ADCTRIG1 on Slave_TIMER0 compare 3 event" "0,1"
bitfld.long 0x20 11. "TRG1ST0C2,HRTIMER_ADCTRIG1 on Slave_TIMER0 compare 2 event" "0,1"
newline
bitfld.long 0x20 10. "TRG1ST0C1,HRTIMER_ADCTRIG1 on Slave_TIMER0 compare 1 event" "0,1"
bitfld.long 0x20 9. "TRG1EXEV9,HRTIMER_ADCTRIG1 on external event 9" "0,1"
bitfld.long 0x20 8. "TRG1EXEV8,HRTIMER_ADCTRIG1 on external event 8" "0,1"
bitfld.long 0x20 7. "TRG1EXEV7,HRTIMER_ADCTRIG1 on external event 7" "0,1"
bitfld.long 0x20 6. "TRG1EXEV6,HRTIMER_ADCTRIG1 on external event 6" "0,1"
bitfld.long 0x20 5. "TRG1EXEV5,HRTIMER_ADCTRIG1 on external event 5" "0,1"
bitfld.long 0x20 4. "TRG1MTPER,HRTIMER_ADCTRIG1 on Master_TIMER period event" "0,1"
newline
bitfld.long 0x20 3. "TRG1MTC3,HRTIMER_ADCTRIG1 on Master_TIMER compare 3 event" "0,1"
bitfld.long 0x20 2. "TRG1MTC2,HRTIMER_ADCTRIG1 on Master_TIMER compare 2 event" "0,1"
bitfld.long 0x20 1. "TRG1MTC1,HRTIMER_ADCTRIG1 on Master_TIMER compare 1 event" "0,1"
bitfld.long 0x20 0. "TRG1MTC0,HRTIMER_ADCTRIG1 on Master_TIMER compare 0 event" "0,1"
line.long 0x24 "ADCTRIGS2,HRTIMER trigger source 2 to ADC register"
bitfld.long 0x24 31. "TRG2ST4PER,HRTIMER_ADCTRIG2 on Slave_TIMER4 period event" "0,1"
bitfld.long 0x24 30. "TRG2ST4C3,HRTIMER_ADCTRIG2 on Slave_TIMER4 compare 3 event" "0,1"
bitfld.long 0x24 29. "TRG2ST4C2,HRTIMER_ADCTRIG2 on Slave_TIMER4 compare 2 event" "0,1"
bitfld.long 0x24 28. "TRG2ST4C1,HRTIMER_ADCTRIG2 on Slave_TIMER4 compare 1 event" "0,1"
bitfld.long 0x24 27. "TRG2ST3PER,HRTIMER_ADCTRIG2 on Slave_TIMER3 period event" "0,1"
bitfld.long 0x24 26. "TRG2ST3C3,HRTIMER_ADCTRIG2 on Slave_TIMER3 compare 3 event" "0,1"
bitfld.long 0x24 25. "TRG2ST3C2,HRTIMER_ADCTRIG2 on Slave_TIMER3 compare 2 event" "0,1"
newline
bitfld.long 0x24 24. "TRG2ST3C1,HRTIMER_ADCTRIG2 on Slave_TIMER3 compare 1 event" "0,1"
bitfld.long 0x24 23. "TRG2ST2PER,HRTIMER_ADCTRIG2 on Slave_TIMER2 period event" "0,1"
bitfld.long 0x24 22. "TRG2ST2C3,HRTIMER_ADCTRIG2 on Slave_TIMER2 compare 3 event" "0,1"
bitfld.long 0x24 21. "TRG2ST2C2,HRTIMER_ADCTRIG2 on Slave_TIMER2 compare 2 event" "0,1"
bitfld.long 0x24 20. "TRG2ST2C1,HRTIMER_ADCTRIG2 on Slave_TIMER2 compare 1 event" "0,1"
bitfld.long 0x24 19. "TRG2ST1RST,HRTIMER_ADCTRIG2 on Slave_TIMER1 reset" "0,1"
bitfld.long 0x24 18. "TRG2ST1PER,HRTIMER_ADCTRIG2 on Slave_TIMER1 period event" "0,1"
newline
bitfld.long 0x24 17. "TRG2ST1C3,HRTIMER_ADCTRIG2 on Slave_TIMER1 compare 3 event" "0,1"
bitfld.long 0x24 16. "TRG2ST1C2,HRTIMER_ADCTRIG2 on Slave_TIMER1 compare 2 event" "0,1"
bitfld.long 0x24 15. "TRG2ST1C1,HRTIMER_ADCTRIG2 on Slave_TIMER1 compare 1 event" "0,1"
bitfld.long 0x24 14. "TRG2ST0RST,HRTIMER_ADCTRIG2 on Slave_TIMER0 reset" "0,1"
bitfld.long 0x24 13. "TRG2ST0PER,HRTIMER_ADCTRIG2 on Slave_TIMER0 period event" "0,1"
bitfld.long 0x24 12. "TRG2ST0C3,HRTIMER_ADCTRIG2 on Slave_TIMER0 compare 3 event" "0,1"
bitfld.long 0x24 11. "TRG2ST0C2,HRTIMER_ADCTRIG2 on Slave_TIMER0 compare 2 event" "0,1"
newline
bitfld.long 0x24 10. "TRG2ST0C1,HRTIMER_ADCTRIG2 on Slave_TIMER0 compare 1 event" "0,1"
bitfld.long 0x24 9. "TRG2EXEV4,HRTIMER_ADCTRIG2 on external event 4" "0,1"
bitfld.long 0x24 8. "TRG2EXEV3,HRTIMER_ADCTRIG2 on external event 3" "0,1"
bitfld.long 0x24 7. "TRG2EXEV2,HRTIMER_ADCTRIG2 on external event 2" "0,1"
bitfld.long 0x24 6. "TRG2EXEV1,HRTIMER_ADCTRIG2 on external event 1" "0,1"
bitfld.long 0x24 5. "TRG2EXEV0,HRTIMER_ADCTRIG2 on external event 0" "0,1"
bitfld.long 0x24 4. "TRG2MTPER,HRTIMER_ADCTRIG2 on Master_TIMER period event" "0,1"
newline
bitfld.long 0x24 3. "TRG2MTC3,HRTIMER_ADCTRIG2 on Master_TIMER compare 3 event" "0,1"
bitfld.long 0x24 2. "TRG2MTC2,HRTIMER_ADCTRIG2 on Master_TIMER compare 2 event" "0,1"
bitfld.long 0x24 1. "TRG2MTC1,HRTIMER_ADCTRIG2 on Master_TIMER compare 1 event" "0,1"
bitfld.long 0x24 0. "TRG2MTC0,HRTIMER_ADCTRIG2 on Master_TIMER compare 0 event" "0,1"
line.long 0x28 "ADCTRIGS3,HRTIMER trigger source 3 to ADC register"
bitfld.long 0x28 31. "TRG3ST4RST,HRTIMER_ADCTRG3 on Slave_TIMER4 reset" "0,1"
bitfld.long 0x28 30. "TRG3ST4C3,HRTIMER_ADCTRG3 on Slave_TIMER4 compare 3 event" "0,1"
bitfld.long 0x28 29. "TRG3ST4C2,HRTIMER_ADCTRG3 on Slave_TIMER4 compare 2 event" "0,1"
bitfld.long 0x28 28. "TRG3ST4C1,HRTIMER_ADCTRG3 on Slave_TIMER4 compare 1 event" "0,1"
bitfld.long 0x28 27. "TRG3ST3RST,HRTIMER_ADCTRG3 on Slave_TIMER3 reset" "0,1"
bitfld.long 0x28 26. "TRG3ST3PER,HRTIMER_ADCTRG3 on Slave_TIMER3 period event" "0,1"
bitfld.long 0x28 25. "TRG3ST3C3,HRTIMER_ADCTRG3 on Slave_TIMER3 compare 3 event" "0,1"
newline
bitfld.long 0x28 24. "TRG3ST3C2,HRTIMER_ADCTRG3 on Slave_TIMER3 compare 2 event" "0,1"
bitfld.long 0x28 23. "TRG3ST3C1,HRTIMER_ADCTRG3 on Slave_TIMER3 compare 1 event" "0,1"
bitfld.long 0x28 22. "TRG3ST2RST,HRTIMER_ADCTRG3 on Slave_TIMER2 reset" "0,1"
bitfld.long 0x28 21. "TRG3ST2PER,HRTIMER_ADCTRG3 on Slave_TIMER2 period event" "0,1"
bitfld.long 0x28 20. "TRG3ST2C3,HRTIMER_ADCTRG3 on Slave_TIMER2 compare 3 event" "0,1"
bitfld.long 0x28 19. "TRG3ST2C2,HRTIMER_ADCTRG3 on Slave_TIMER2 compare 2 event" "0,1"
bitfld.long 0x28 18. "TRG3ST2C1,HRTIMER_ADCTRG3 on Slave_TIMER2 compare 1 event" "0,1"
newline
bitfld.long 0x28 17. "TRG3ST1PER,HRTIMER_ADCTRG3 on Slave_TIMER1 period event" "0,1"
bitfld.long 0x28 16. "TRG3ST1C3,HRTIMER_ADCTRG3 on Slave_TIMER1 compare 3 event" "0,1"
bitfld.long 0x28 15. "TRG3ST1C2,HRTIMER_ADCTRG3 on Slave_TIMER1 compare 2 event" "0,1"
bitfld.long 0x28 14. "TRG3ST1C1,HRTIMER_ADCTRG3 on Slave_TIMER1 compare 1 event" "0,1"
bitfld.long 0x28 13. "TRG3ST0PER,HRTIMER_ADCTRG3 on Slave_TIMER0 period event" "0,1"
bitfld.long 0x28 12. "TRG3ST0C3,HRTIMER_ADCTRG3 on Slave_TIMER0 compare 3 event" "0,1"
bitfld.long 0x28 11. "TRG3ST0C2,HRTIMER_ADCTRG3 on Slave_TIMER0 compare 2 event" "0,1"
newline
bitfld.long 0x28 10. "TRG3ST0C1,HRTIMER_ADCTRG3 on Slave_TIMER0 compare 1 event" "0,1"
bitfld.long 0x28 9. "TRG3EXEV9,HRTIMER_ADCTRG3 on external event 9" "0,1"
bitfld.long 0x28 8. "TRG3EXEV8,HRTIMER_ADCTRG3 on external event 8" "0,1"
bitfld.long 0x28 7. "TRG3EXEV7,HRTIMER_ADCTRG3 on external event 7" "0,1"
bitfld.long 0x28 6. "TRG3EXEV6,HRTIMER_ADCTRG3 on external event 6" "0,1"
bitfld.long 0x28 5. "TRG3EXEV5,HRTIMER_ADCTRG3 on external event 5" "0,1"
bitfld.long 0x28 4. "TRG3MTPER,HRTIMER_ADCTRG3 on Master_TIMER period event" "0,1"
newline
bitfld.long 0x28 3. "TRG3MTC3,HRTIMER_ADCTRG3 on Master_TIMER compare 3 event" "0,1"
bitfld.long 0x28 2. "TRG3MTC2,HRTIMER_ADCTRG3 on Master_TIMER compare 2 event" "0,1"
bitfld.long 0x28 1. "TRG3MTC1,HRTIMER_ADCTRG3 on Master_TIMER compare 1 event" "0,1"
bitfld.long 0x28 0. "TRG3MTC0,HRTIMER_ADCTRG3 on Master_TIMER compare 0 event" "0,1"
line.long 0x2C "DLLCCTL,HRTIMER DLL calibration control register"
bitfld.long 0x2C 2.--3. "CLBPER,DLL calibration period" "0,1,2,3"
bitfld.long 0x2C 1. "CLBPEREN,DLL periodic calibration enable" "0,1"
bitfld.long 0x2C 0. "CLBSTRT,DLL calibration start once" "0,1"
line.long 0x30 "FLTINCFG0,HRTIMER fault input configuration register 0"
bitfld.long 0x30 31. "FLT3INPROT,Protect fault 3 input configuration" "0,1"
hexmask.long.byte 0x30 27.--30. 1. "FLT3INFC,Fault 3 input filter control"
bitfld.long 0x30 26. "FLT3INSRC_0,Fault 3 input source" "0,1"
bitfld.long 0x30 25. "FLT3INP,Fault 3 input polarity" "0,1"
bitfld.long 0x30 24. "FLT3INEN,Fault 3 input enable" "0,1"
bitfld.long 0x30 23. "FLT2INPROT,Protect fault 2 input configuration" "0,1"
hexmask.long.byte 0x30 19.--22. 1. "FLT2INFC,Fault 2 input filter control"
newline
bitfld.long 0x30 18. "FLT2INSRC_0,Fault 2 input source" "0,1"
bitfld.long 0x30 17. "FLT2INP,Fault 2 input polarity" "0,1"
bitfld.long 0x30 16. "FLT2INEN,Fault 2 input enable" "0,1"
bitfld.long 0x30 15. "FLT1INPROT,Protect fault 1 input configuration" "0,1"
hexmask.long.byte 0x30 11.--14. 1. "FLT1INFC,Fault 1 input filter control"
bitfld.long 0x30 10. "FLT1INSRC_0,Fault 1 input source" "0,1"
bitfld.long 0x30 9. "FLT1INP,Fault 1 input polarity" "0,1"
newline
bitfld.long 0x30 8. "FLT1INEN,Fault 1 input enable" "0,1"
bitfld.long 0x30 7. "FLT0INPROT,Protect fault 0 input configuration" "0,1"
hexmask.long.byte 0x30 3.--6. 1. "FLT0INFC,Fault 0 input filter control"
bitfld.long 0x30 2. "FLT0INSRC_0,Fault 0 input source combine with FLT0INSRC[1]" "0,1"
bitfld.long 0x30 1. "FLT0INP,Fault 0 input polarity" "0,1"
bitfld.long 0x30 0. "FLT0INEN,Fault 0 input enable" "0,1"
line.long 0x34 "FLTINCFG1,HRTIMER fault input configuration register 1"
bitfld.long 0x34 24.--25. "FLTFDIV,Fault input clock division" "0,1,2,3"
bitfld.long 0x34 23. "FLT7INSRC_1,Fault 7 input source" "0,1"
bitfld.long 0x34 22. "FLT6INSRC_1,Fault 6 input source" "0,1"
bitfld.long 0x34 21. "FLT5INSRC_1,Fault 5 input source" "0,1"
bitfld.long 0x34 20. "FLT4INSRC_1,Fault 4 input source" "0,1"
bitfld.long 0x34 19. "FLT3INSRC_1,Fault 3 input source" "0,1"
bitfld.long 0x34 18. "FLT2INSRC_1,Fault 2 input source" "0,1"
newline
bitfld.long 0x34 17. "FLT1INSRC_1,Fault 1 input source" "0,1"
bitfld.long 0x34 16. "FLT0INSRC_1,Fault 0 input source" "0,1"
bitfld.long 0x34 15. "FLT5INPROT,Protect fault 5 input configuration" "0,1"
hexmask.long.byte 0x34 11.--14. 1. "FLT5INFC,Fault 5 input filter control"
bitfld.long 0x34 10. "FLT5INSRC_0,Fault 5 input source" "0,1"
bitfld.long 0x34 9. "FLT5INP,Fault 5 input polarity" "0,1"
bitfld.long 0x34 8. "FLT5INEN,Fault 5 input enable" "0,1"
newline
bitfld.long 0x34 7. "FLT4INPROT,Protect fault 4 input configuration" "0,1"
hexmask.long.byte 0x34 3.--6. 1. "FLT4INFC,Fault 4 input filter control"
bitfld.long 0x34 2. "FLT4INSRC_0,Fault 4 input source" "0,1"
bitfld.long 0x34 1. "FLT4INP,Fault 4 input polarity" "0,1"
bitfld.long 0x34 0. "FLT4INEN,Fault 4 input enable" "0,1"
line.long 0x38 "DMAUPMTR,HRTIMER DMA update Master_TIMER register"
bitfld.long 0x38 9. "MTCMP3V,HRTIMER_MTCMP3V update by DMA mode" "0,1"
bitfld.long 0x38 8. "MTCMP2V,HRTIMER_MTCMP2V update by DMA mode" "0,1"
bitfld.long 0x38 7. "MTCMP1V,HRTIMER_MTCMP1V update by DMA mode" "0,1"
bitfld.long 0x38 6. "MTCMP0V,HRTIMER_MTCMP0V update by DMA mode" "0,1"
bitfld.long 0x38 5. "MTCREP,HRTIMER_MTCREP update by DMA mode" "0,1"
bitfld.long 0x38 4. "MTCAR,HRTIMER_MTCAR update by DMA mode" "0,1"
bitfld.long 0x38 3. "MTCNT,HRTIMER_MTCNT update by DMA mode" "0,1"
newline
bitfld.long 0x38 2. "MTDMAINTEN,HRTIMER_MTDMAINTEN update by DMA mode" "0,1"
bitfld.long 0x38 1. "MTINTC,HRTIMER_MTINTC update by DMA mode" "0,1"
bitfld.long 0x38 0. "MTCTL0,HRTIMER_MTCTL0 update by DMA mode" "0,1"
line.long 0x3C "DMAUPST0R,HRTIMER DMA update Slave_TIMERx regist 0"
bitfld.long 0x3C 31. "ST0ACTL,HRTIMER_ST0ACTL update by DMA mode" "0,1"
bitfld.long 0x3C 22. "ST0EXEVFCFG2,HRTIMER_ST0EXEVFCFG2 update by DMA mode" "0,1"
bitfld.long 0x3C 21. "ST0CTL1,HRTIMER_ST0CTL1 update by DMA mode" "0,1"
bitfld.long 0x3C 20. "ST0FLTCTL,HRTIMER_ST0FLTCTL update by DMA mode" "0,1"
bitfld.long 0x3C 19. "ST0CHOCTL,HRTIMER_ST0CHOCTL update by DMA mode" "0,1"
bitfld.long 0x3C 18. "ST0CSCTL,HRTIMER_ST0CSCTL update by DMA mode" "0,1"
bitfld.long 0x3C 17. "ST0CNTRST,HRTIMER_ST0CNTRST update by DMA mode" "0,1"
newline
bitfld.long 0x3C 16. "ST0EXEVFCFG1,HRTIMER_ST0EXEVFCFG1update by DMA mode" "0,1"
bitfld.long 0x3C 15. "ST0EXEVFCFG0,HRTIMER_ST0EXEVFCFG0update by DMA mode" "0,1"
bitfld.long 0x3C 14. "ST0CH1RST,HRTIMER_ST0CH1RST update by DMA mode" "0,1"
bitfld.long 0x3C 13. "ST0CH1SET,HRTIMER_ST0CH1SET update by DMA mode" "0,1"
bitfld.long 0x3C 12. "ST0CH0RST,HRTIMER_ST0CH0RST update by DMA mode" "0,1"
bitfld.long 0x3C 11. "ST0CH0SET,HRTIMER_ST0CH0SET update by DMA mode" "0,1"
bitfld.long 0x3C 10. "ST0DTCTL,HRTIMER_ST0DTCTL update by DMA mode" "0,1"
newline
bitfld.long 0x3C 9. "ST0CMP3V,HRTIMER_ST0CMP3V update by DMA mode" "0,1"
bitfld.long 0x3C 8. "ST0CMP2V,HRTIMER_ST0CMP2V update by DMA mode" "0,1"
bitfld.long 0x3C 7. "ST0CMP1V,HRTIMER_ST0CMP1V update by DMA mode" "0,1"
bitfld.long 0x3C 6. "ST0CMP0V,HRTIMER_ST0CMP0V update by DMA mode" "0,1"
bitfld.long 0x3C 5. "ST0CREP,HRTIMER_ST0CREP update by DMA mode" "0,1"
bitfld.long 0x3C 4. "ST0CAR,HRTIMER_ST0CAR update by DMA mode" "0,1"
bitfld.long 0x3C 3. "ST0CNT,HRTIMER_ST0CNT update by DMA mode" "0,1"
newline
bitfld.long 0x3C 2. "ST0DMAINTEN,HRTIMER_ST0DMAINTEN update by DMA mode" "0,1"
bitfld.long 0x3C 1. "ST0INTC,HRTIMER_ST0INTC update by DMA mode" "0,1"
bitfld.long 0x3C 0. "ST0CTL0,HRTIMER_ST0CTL0 update by DMA mode" "0,1"
line.long 0x40 "DMAUPST1R,HRTIMER DMA update Slave_TIMERx regist 1"
bitfld.long 0x40 31. "ST1ACTL,HRTIMER_ST1ACTL update by DMA mode" "0,1"
bitfld.long 0x40 22. "ST1EXEVFCFG2,HRTIMER_ST1EXEVFCFG2 update by DMA mode" "0,1"
bitfld.long 0x40 21. "ST1CTL1,HRTIMER_ST1CTL1 update by DMA mode" "0,1"
bitfld.long 0x40 20. "ST1FLTCTL,HRTIMER_ST1FLTCTL update by DMA mode" "0,1"
bitfld.long 0x40 19. "ST1CHOCTL,HRTIMER_ST1CHOCTL update by DMA mode" "0,1"
bitfld.long 0x40 18. "ST1CSCTL,HRTIMER_ST1CSCTL update by DMA mode" "0,1"
bitfld.long 0x40 17. "ST1CNTRST,HRTIMER_ST1CNTRST update by DMA mode" "0,1"
newline
bitfld.long 0x40 16. "ST1EXEVFCFG1,HRTIMER_ST1EXEVFCFG1update by DMA mode" "0,1"
bitfld.long 0x40 15. "ST1EXEVFCFG0,HRTIMER_ST1EXEVFCFG0update by DMA mode" "0,1"
bitfld.long 0x40 14. "ST1CH1RST,HRTIMER_ST1CH1RST update by DMA mode" "0,1"
bitfld.long 0x40 13. "ST1CH1SET,HRTIMER_ST1CH1SET update by DMA mode" "0,1"
bitfld.long 0x40 12. "ST1CH0RST,HRTIMER_ST1CH0RST update by DMA mode" "0,1"
bitfld.long 0x40 11. "ST1CH0SET,HRTIMER_ST1CH0SET update by DMA mode" "0,1"
bitfld.long 0x40 10. "ST1DTCTL,HRTIMER_ST1DTCTL update by DMA mode" "0,1"
newline
bitfld.long 0x40 9. "ST1CMP3V,HRTIMER_ST1CMP3V update by DMA mode" "0,1"
bitfld.long 0x40 8. "ST1CMP2V,HRTIMER_ST1CMP2V update by DMA mode" "0,1"
bitfld.long 0x40 7. "ST1CMP1V,HRTIMER_ST1CMP1V update by DMA mode" "0,1"
bitfld.long 0x40 6. "ST1CMP0V,HRTIMER_ST1CMP0V update by DMA mode" "0,1"
bitfld.long 0x40 5. "ST1CREP,HRTIMER_ST1CREP update by DMA mode" "0,1"
bitfld.long 0x40 4. "ST1CAR,HRTIMER_ST1CAR update by DMA mode" "0,1"
bitfld.long 0x40 3. "ST1CNT,HRTIMER_ST1CNT update by DMA mode" "0,1"
newline
bitfld.long 0x40 2. "ST1DMAINTEN,HRTIMER_ST1DMAINTEN update by DMA mode" "0,1"
bitfld.long 0x40 1. "ST1INTC,HRTIMER_ST1INTC update by DMA mode" "0,1"
bitfld.long 0x40 0. "ST1CTL0,HRTIMER_ST1CTL0 update by DMA mode" "0,1"
line.long 0x44 "DMAUPST2R,HRTIMER DMA update Slave_TIMERx regist 2"
bitfld.long 0x44 31. "ST2ACTL,HRTIMER_ST2ACTL update by DMA mode" "0,1"
bitfld.long 0x44 22. "ST2EXEVFCFG2,HRTIMER_ST2EXEVFCFG2 update by DMA mode" "0,1"
bitfld.long 0x44 21. "ST2CTL1,HRTIMER_ST2CTL1 update by DMA mode" "0,1"
bitfld.long 0x44 20. "ST2FLTCTL,HRTIMER_ST2FLTCTL update by DMA mode" "0,1"
bitfld.long 0x44 19. "ST2CHOCTL,HRTIMER_ST2CHOCTL update by DMA mode" "0,1"
bitfld.long 0x44 18. "ST2CSCTL,HRTIMER_ST2CSCTL update by DMA mode" "0,1"
bitfld.long 0x44 17. "ST2CNTRST,HRTIMER_ST2CNTRST update by DMA mode" "0,1"
newline
bitfld.long 0x44 16. "ST2EXEVFCFG1,HRTIMER_ST2EXEVFCFG1update by DMA mode" "0,1"
bitfld.long 0x44 15. "ST2EXEVFCFG0,HRTIMER_ST2EXEVFCFG0update by DMA mode" "0,1"
bitfld.long 0x44 14. "ST2CH1RST,HRTIMER_ST2CH1RST update by DMA mode" "0,1"
bitfld.long 0x44 13. "ST2CH1SET,HRTIMER_ST2CH1SET update by DMA mode" "0,1"
bitfld.long 0x44 12. "ST2CH0RST,HRTIMER_ST2CH0RST update by DMA mode" "0,1"
bitfld.long 0x44 11. "ST2CH0SET,HRTIMER_ST2CH0SET update by DMA mode" "0,1"
bitfld.long 0x44 10. "ST2DTCTL,HRTIMER_ST2DTCTL update by DMA mode" "0,1"
newline
bitfld.long 0x44 9. "ST2CMP3V,HRTIMER_ST2CMP3V update by DMA mode" "0,1"
bitfld.long 0x44 8. "ST2CMP2V,HRTIMER_ST2CMP2V update by DMA mode" "0,1"
bitfld.long 0x44 7. "ST2CMP1V,HRTIMER_ST2CMP1V update by DMA mode" "0,1"
bitfld.long 0x44 6. "ST2CMP0V,HRTIMER_ST2CMP0V update by DMA mode" "0,1"
bitfld.long 0x44 5. "ST2CREP,HRTIMER_ST2CREP update by DMA mode" "0,1"
bitfld.long 0x44 4. "ST2CAR,HRTIMER_ST2CAR update by DMA mode" "0,1"
bitfld.long 0x44 3. "ST2CNT,HRTIMER_ST2CNT update by DMA mode" "0,1"
newline
bitfld.long 0x44 2. "ST2DMAINTEN,HRTIMER_ST2DMAINTEN update by DMA mode" "0,1"
bitfld.long 0x44 1. "ST2INTC,HRTIMER_ST2INTC update by DMA mode" "0,1"
bitfld.long 0x44 0. "ST2CTL0,HRTIMER_ST2CTL0 update by DMA mode" "0,1"
line.long 0x48 "DMAUPST3R,HRTIMER DMA update Slave_TIMERx regist 3"
bitfld.long 0x48 31. "ST3ACTL,HRTIMER_ST3ACTL update by DMA mode" "0,1"
bitfld.long 0x48 22. "ST3EXEVFCFG2,HRTIMER_ST3EXEVFCFG2 update by DMA mode" "0,1"
bitfld.long 0x48 21. "ST3CTL1,HRTIMER_ST3CTL1 update by DMA mode" "0,1"
bitfld.long 0x48 20. "ST3FLTCTL,HRTIMER_ST3FLTCTL update by DMA mode" "0,1"
bitfld.long 0x48 19. "ST3CHOCTL,HRTIMER_ST3CHOCTL update by DMA mode" "0,1"
bitfld.long 0x48 18. "ST3CSCTL,HRTIMER_ST3CSCTL update by DMA mode" "0,1"
bitfld.long 0x48 17. "ST3CNTRST,HRTIMER_ST3CNTRST update by DMA mode" "0,1"
newline
bitfld.long 0x48 16. "ST3EXEVFCFG1,HRTIMER_ST3EXEVFCFG1update by DMA mode" "0,1"
bitfld.long 0x48 15. "ST3EXEVFCFG0,HRTIMER_ST3EXEVFCFG0update by DMA mode" "0,1"
bitfld.long 0x48 14. "ST3CH1RST,HRTIMER_ST3CH1RST update by DMA mode" "0,1"
bitfld.long 0x48 13. "ST3CH1SET,HRTIMER_ST3CH1SET update by DMA mode" "0,1"
bitfld.long 0x48 12. "ST3CH0RST,HRTIMER_ST3CH0RST update by DMA mode" "0,1"
bitfld.long 0x48 11. "ST3CH0SET,HRTIMER_ST3CH0SET update by DMA mode" "0,1"
bitfld.long 0x48 10. "ST3DTCTL,HRTIMER_ST3DTCTL update by DMA mode" "0,1"
newline
bitfld.long 0x48 9. "ST3CMP3V,HRTIMER_ST3CMP3V update by DMA mode" "0,1"
bitfld.long 0x48 8. "ST3CMP2V,HRTIMER_ST3CMP2V update by DMA mode" "0,1"
bitfld.long 0x48 7. "ST3CMP1V,HRTIMER_ST3CMP1V update by DMA mode" "0,1"
bitfld.long 0x48 6. "ST3CMP0V,HRTIMER_ST3CMP0V update by DMA mode" "0,1"
bitfld.long 0x48 5. "ST3CREP,HRTIMER_ST3CREP update by DMA mode" "0,1"
bitfld.long 0x48 4. "ST3CAR,HRTIMER_ST3CAR update by DMA mode" "0,1"
bitfld.long 0x48 3. "ST3CNT,HRTIMER_ST3CNT update by DMA mode" "0,1"
newline
bitfld.long 0x48 2. "ST3DMAINTEN,HRTIMER_ST3DMAINTEN update by DMA mode" "0,1"
bitfld.long 0x48 1. "ST3INTC,HRTIMER_ST3INTC update by DMA mode" "0,1"
bitfld.long 0x48 0. "ST3CTL0,HRTIMER_ST3CTL0 update by DMA mode" "0,1"
line.long 0x4C "DMAUPST4R,HRTIMER DMA update Slave_TIMERx regist 4"
bitfld.long 0x4C 31. "ST4ACTL,HRTIMER_ST4ACTL update by DMA mode" "0,1"
bitfld.long 0x4C 22. "ST4EXEVFCFG2,HRTIMER_ST4EXEVFCFG2 update by DMA mode" "0,1"
bitfld.long 0x4C 21. "ST4CTL1,HRTIMER_ST4CTL1 update by DMA mode" "0,1"
bitfld.long 0x4C 20. "ST4FLTCTL,HRTIMER_ST4FLTCTL update by DMA mode" "0,1"
bitfld.long 0x4C 19. "ST4CHOCTL,HRTIMER_ST4CHOCTL update by DMA mode" "0,1"
bitfld.long 0x4C 18. "ST4CSCTL,HRTIMER_ST4CSCTL update by DMA mode" "0,1"
bitfld.long 0x4C 17. "ST4CNTRST,HRTIMER_ST4CNTRST update by DMA mode" "0,1"
newline
bitfld.long 0x4C 16. "ST4EXEVFCFG1,HRTIMER_ST4EXEVFCFG1update by DMA mode" "0,1"
bitfld.long 0x4C 15. "ST4EXEVFCFG0,HRTIMER_ST4EXEVFCFG0update by DMA mode" "0,1"
bitfld.long 0x4C 14. "ST4CH1RST,HRTIMER_ST4CH1RST update by DMA mode" "0,1"
bitfld.long 0x4C 13. "ST4CH1SET,HRTIMER_ST4CH1SET update by DMA mode" "0,1"
bitfld.long 0x4C 12. "ST4CH0RST,HRTIMER_ST4CH0RST update by DMA mode" "0,1"
bitfld.long 0x4C 11. "ST4CH0SET,HRTIMER_ST4CH0SET update by DMA mode" "0,1"
bitfld.long 0x4C 10. "ST4DTCTL,HRTIMER_ST4DTCTL update by DMA mode" "0,1"
newline
bitfld.long 0x4C 9. "ST4CMP3V,HRTIMER_ST4CMP3V update by DMA mode" "0,1"
bitfld.long 0x4C 8. "ST4CMP2V,HRTIMER_ST4CMP2V update by DMA mode" "0,1"
bitfld.long 0x4C 7. "ST4CMP1V,HRTIMER_ST4CMP1V update by DMA mode" "0,1"
bitfld.long 0x4C 6. "ST4CMP0V,HRTIMER_ST4CMP0V update by DMA mode" "0,1"
bitfld.long 0x4C 5. "ST4CREP,HRTIMER_ST4CREP update by DMA mode" "0,1"
bitfld.long 0x4C 4. "ST4CAR,HRTIMER_ST4CAR update by DMA mode" "0,1"
bitfld.long 0x4C 3. "ST4CNT,HRTIMER_ST4CNT update by DMA mode" "0,1"
newline
bitfld.long 0x4C 2. "ST4DMAINTEN,HRTIMER_ST4DMAINTEN update by DMA mode" "0,1"
bitfld.long 0x4C 1. "ST4INTC,HRTIMER_ST4INTC update by DMA mode" "0,1"
bitfld.long 0x4C 0. "ST4CTL0,HRTIMER_ST4CTL0 update by DMA mode" "0,1"
group.long 0x74++0x3
line.long 0x0 "DMAUPST5R,HRTIMER DMA update Slave_TIMERx regist 5"
bitfld.long 0x0 31. "ST5ACTL,HRTIMER_ST5ACTL update by DMA mode" "0,1"
bitfld.long 0x0 22. "ST5EXEVFCFG2,HRTIMER_ST5EXEVFCFG2 update by DMA mode" "0,1"
bitfld.long 0x0 21. "ST5CTL1,HRTIMER_ST5CTL1 update by DMA mode" "0,1"
bitfld.long 0x0 20. "ST5FLTCTL,HRTIMER_ST5FLTCTL update by DMA mode" "0,1"
bitfld.long 0x0 19. "ST5CHOCTL,HRTIMER_ST5CHOCTL update by DMA mode" "0,1"
bitfld.long 0x0 18. "ST5CSCTL,HRTIMER_ST5CSCTL update by DMA mode" "0,1"
bitfld.long 0x0 17. "ST5CNTRST,HRTIMER_ST5CNTRST update by DMA mode" "0,1"
newline
bitfld.long 0x0 16. "ST5EXEVFCFG1,HRTIMER_ST5EXEVFCFG1update by DMA mode" "0,1"
bitfld.long 0x0 15. "ST5EXEVFCFG0,HRTIMER_ST5EXEVFCFG0update by DMA mode" "0,1"
bitfld.long 0x0 14. "ST5CH1RST,HRTIMER_ST5CH1RST update by DMA mode" "0,1"
bitfld.long 0x0 13. "ST5CH1SET,HRTIMER_ST5CH1SET update by DMA mode" "0,1"
bitfld.long 0x0 12. "ST5CH0RST,HRTIMER_ST5CH0RST update by DMA mode" "0,1"
bitfld.long 0x0 11. "ST5CH0SET,HRTIMER_ST5CH0SET update by DMA mode" "0,1"
bitfld.long 0x0 10. "ST5DTCTL,HRTIMER_ST5DTCTL update by DMA mode" "0,1"
newline
bitfld.long 0x0 9. "ST5CMP3V,HRTIMER_ST5CMP3V update by DMA mode" "0,1"
bitfld.long 0x0 8. "ST5CMP2V,HRTIMER_ST5CMP2V update by DMA mode" "0,1"
bitfld.long 0x0 7. "ST5CMP1V,HRTIMER_ST5CMP1V update by DMA mode" "0,1"
bitfld.long 0x0 6. "ST5CMP0V,HRTIMER_ST5CMP0V update by DMA mode" "0,1"
bitfld.long 0x0 5. "ST5CREP,HRTIMER_ST5CREP update by DMA mode" "0,1"
bitfld.long 0x0 4. "ST5CAR,HRTIMER_ST5CAR update by DMA mode" "0,1"
bitfld.long 0x0 3. "ST5CNT,HRTIMER_ST5CNT update by DMA mode" "0,1"
newline
bitfld.long 0x0 2. "ST5DMAINTEN,HRTIMER_ST5DMAINTEN update by DMA mode" "0,1"
bitfld.long 0x0 1. "ST5INTC,HRTIMER_ST5INTC update by DMA mode" "0,1"
bitfld.long 0x0 0. "ST5CTL0,HRTIMER_ST5CTL0 update by DMA mode" "0,1"
group.long 0x100++0x7
line.long 0x0 "DMAUPST6R,HRTIMER DMA update Slave_TIMERx regist 6"
bitfld.long 0x0 31. "ST6ACTL,HRTIMER_ST6ACTL update by DMA mode" "0,1"
bitfld.long 0x0 22. "ST6EXEVFCFG2,HRTIMER_ST6EXEVFCFG2 update by DMA mode" "0,1"
bitfld.long 0x0 21. "ST6CTL1,HRTIMER_ST6CTL1 update by DMA mode" "0,1"
bitfld.long 0x0 20. "ST6FLTCTL,HRTIMER_ST6FLTCTL update by DMA mode" "0,1"
bitfld.long 0x0 19. "ST6CHOCTL,HRTIMER_ST6CHOCTL update by DMA mode" "0,1"
bitfld.long 0x0 18. "ST6CSCTL,HRTIMER_ST6CSCTL update by DMA mode" "0,1"
bitfld.long 0x0 17. "ST6CNTRST,HRTIMER_ST6CNTRST update by DMA mode" "0,1"
newline
bitfld.long 0x0 16. "ST6EXEVFCFG1,HRTIMER_ST6EXEVFCFG1update by DMA mode" "0,1"
bitfld.long 0x0 15. "ST6EXEVFCFG0,HRTIMER_ST6EXEVFCFG0update by DMA mode" "0,1"
bitfld.long 0x0 14. "ST6CH1RST,HRTIMER_ST6CH1RST update by DMA mode" "0,1"
bitfld.long 0x0 13. "ST6CH1SET,HRTIMER_ST6CH1SET update by DMA mode" "0,1"
bitfld.long 0x0 12. "ST6CH0RST,HRTIMER_ST6CH0RST update by DMA mode" "0,1"
bitfld.long 0x0 11. "ST6CH0SET,HRTIMER_ST6CH0SET update by DMA mode" "0,1"
bitfld.long 0x0 10. "ST6DTCTL,HRTIMER_ST6DTCTL update by DMA mode" "0,1"
newline
bitfld.long 0x0 9. "ST6CMP3V,HRTIMER_ST6CMP3V update by DMA mode" "0,1"
bitfld.long 0x0 8. "ST6CMP2V,HRTIMER_ST6CMP2V update by DMA mode" "0,1"
bitfld.long 0x0 7. "ST6CMP1V,HRTIMER_ST6CMP1V update by DMA mode" "0,1"
bitfld.long 0x0 6. "ST6CMP0V,HRTIMER_ST6CMP0V update by DMA mode" "0,1"
bitfld.long 0x0 5. "ST6CREP,HRTIMER_ST6CREP update by DMA mode" "0,1"
bitfld.long 0x0 4. "ST6CAR,HRTIMER_ST6CAR update by DMA mode" "0,1"
bitfld.long 0x0 3. "ST6CNT,HRTIMER_ST6CNT update by DMA mode" "0,1"
newline
bitfld.long 0x0 2. "ST6DMAINTEN,HRTIMER_ST6DMAINTEN update by DMA mode" "0,1"
bitfld.long 0x0 1. "ST6INTC,HRTIMER_ST6INTC update by DMA mode" "0,1"
bitfld.long 0x0 0. "ST6CTL0,HRTIMER_ST6CTL0 update by DMA mode" "0,1"
line.long 0x4 "DMAUPST7R,HRTIMER DMA update Slave_TIMERx regist 7"
bitfld.long 0x4 31. "ST7ACTL,HRTIMER_ST7ACTL update by DMA mode" "0,1"
bitfld.long 0x4 22. "ST7EXEVFCFG2,HRTIMER_ST7EXEVFCFG2 update by DMA mode" "0,1"
bitfld.long 0x4 21. "ST7CTL1,HRTIMER_ST7CTL1 update by DMA mode" "0,1"
bitfld.long 0x4 20. "ST7FLTCTL,HRTIMER_ST7FLTCTL update by DMA mode" "0,1"
bitfld.long 0x4 19. "ST7CHOCTL,HRTIMER_ST7CHOCTL update by DMA mode" "0,1"
bitfld.long 0x4 18. "ST7CSCTL,HRTIMER_ST7CSCTL update by DMA mode" "0,1"
bitfld.long 0x4 17. "ST7CNTRST,HRTIMER_ST7CNTRST update by DMA mode" "0,1"
newline
bitfld.long 0x4 16. "ST7EXEVFCFG1,HRTIMER_ST7EXEVFCFG1update by DMA mode" "0,1"
bitfld.long 0x4 15. "ST7EXEVFCFG0,HRTIMER_ST7EXEVFCFG0update by DMA mode" "0,1"
bitfld.long 0x4 14. "ST7CH1RST,HRTIMER_ST7CH1RST update by DMA mode" "0,1"
bitfld.long 0x4 13. "ST7CH1SET,HRTIMER_ST7CH1SET update by DMA mode" "0,1"
bitfld.long 0x4 12. "ST7CH0RST,HRTIMER_ST7CH0RST update by DMA mode" "0,1"
bitfld.long 0x4 11. "ST7CH0SET,HRTIMER_ST7CH0SET update by DMA mode" "0,1"
bitfld.long 0x4 10. "ST7DTCTL,HRTIMER_ST7DTCTL update by DMA mode" "0,1"
newline
bitfld.long 0x4 9. "ST7CMP3V,HRTIMER_ST7CMP3V update by DMA mode" "0,1"
bitfld.long 0x4 8. "ST7CMP2V,HRTIMER_ST7CMP2V update by DMA mode" "0,1"
bitfld.long 0x4 7. "ST7CMP1V,HRTIMER_ST7CMP1V update by DMA mode" "0,1"
bitfld.long 0x4 6. "ST7CMP0V,HRTIMER_ST7CMP0V update by DMA mode" "0,1"
bitfld.long 0x4 5. "ST7CREP,HRTIMER_ST7CREP update by DMA mode" "0,1"
bitfld.long 0x4 4. "ST7CAR,HRTIMER_ST7CAR update by DMA mode" "0,1"
bitfld.long 0x4 3. "ST7CNT,HRTIMER_ST7CNT update by DMA mode" "0,1"
newline
bitfld.long 0x4 2. "ST7DMAINTEN,HRTIMER_ST7DMAINTEN update by DMA mode" "0,1"
bitfld.long 0x4 1. "ST7INTC,HRTIMER_ST7INTC update by DMA mode" "0,1"
bitfld.long 0x4 0. "ST7CTL0,HRTIMER_ST7CTL0 update by DMA mode" "0,1"
wgroup.long 0x70++0x3
line.long 0x0 "DMATB,HRTIMER DMA transfer buffer register"
hexmask.long 0x0 0.--31. 1. "DMATB,DMA transfer buffer"
group.long 0x78++0x17
line.long 0x0 "ADCEXTTRG,HRTIMER ADC extended trigger register"
hexmask.long.byte 0x0 26.--30. 1. "ADC9TRG,ADC trigger 9 selection This bit selects the ADC trigger 9 source"
hexmask.long.byte 0x0 21.--25. 1. "ADC8TRG,ADC trigger 8 selection This bit selects the ADC trigger 8 source"
hexmask.long.byte 0x0 16.--20. 1. "ADC7TRG,ADC trigger 7 selection This bit selects the ADC trigger 7 source"
hexmask.long.byte 0x0 10.--14. 1. "ADC6TRG,ADC trigger 6 selection This bit selects the ADC trigger 6 source"
hexmask.long.byte 0x0 5.--9. 1. "ADC5TRG,ADC trigger 5 selection This bit selects the ADC trigger 5 source"
hexmask.long.byte 0x0 0.--4. 1. "ADC4TRG,ADC trigger 4 selection This bit selects the ADC trigger 4 source"
line.long 0x4 "ADCTRGUPD,HRTIMER ADC trigger update register"
hexmask.long.byte 0x4 20.--23. 1. "ADTG9USRC,ADC trigger 9 update source"
hexmask.long.byte 0x4 16.--19. 1. "ADTG8USRC,ADC trigger 8 update source"
hexmask.long.byte 0x4 12.--15. 1. "ADTG7USRC,ADC trigger 7 update source"
hexmask.long.byte 0x4 8.--11. 1. "ADTG6USRC,ADC trigger 6update source"
hexmask.long.byte 0x4 4.--7. 1. "ADTG5USRC,ADC trigger5 update source"
hexmask.long.byte 0x4 0.--3. 1. "ADTG4USRC,ADC4TRG update source"
line.long 0x8 "ADCPSCR0,HRTIMER ADC post scaler registe register 0"
hexmask.long.byte 0x8 24.--28. 1. "ADC4PSC,ADC trigger 4 prescaler"
hexmask.long.byte 0x8 18.--22. 1. "ADC3PSC,ADC trigger 3 prescaler"
hexmask.long.byte 0x8 12.--16. 1. "ADC2PSC,ADC trigger 2 prescaler"
hexmask.long.byte 0x8 6.--10. 1. "ADC1PSC,ADC trigger 1 prescaler"
hexmask.long.byte 0x8 0.--4. 1. "ADC0PSC,ADC trigger 0 prescaler"
line.long 0xC "ADCPSCR1,HRTIMER ADC post scaler registe register 1"
hexmask.long.byte 0xC 24.--28. 1. "ADC9PSC,ADC trigger 9 prescaler"
hexmask.long.byte 0xC 18.--22. 1. "ADC8PSC,ADC trigger 8 prescaler"
hexmask.long.byte 0xC 12.--16. 1. "ADC7PSC,ADC trigger 7 prescaler"
hexmask.long.byte 0xC 6.--10. 1. "ADC6PSC,ADC trigger 6 prescaler"
hexmask.long.byte 0xC 0.--4. 1. "ADC5PSC,ADC trigger 5 prescaler"
line.long 0x10 "FLTINCFG2,HRTIMER fault input configuration register 2"
bitfld.long 0x10 31. "FLT3RST,Fault 3 reset mode" "0,1"
bitfld.long 0x10 30. "FLT3CNTRST,Fault 3 counter reset" "0,1"
hexmask.long.byte 0x10 26.--29. 1. "FLT3CNT,Fault 3 counter"
bitfld.long 0x10 25. "FLT3BLKS,Fault 3 blanking source" "0,1"
bitfld.long 0x10 24. "FLT3BLKEN,Fault 3 blanking enable" "0,1"
bitfld.long 0x10 23. "FLT2RST,Fault 2 reset mode" "0,1"
bitfld.long 0x10 22. "FLT2CNTRST,Fault 2 counter reset" "0,1"
newline
hexmask.long.byte 0x10 18.--21. 1. "FLT2CNT,Fault 2 counter"
bitfld.long 0x10 17. "FLT2BLKS,Fault 2 blanking source" "0,1"
bitfld.long 0x10 16. "FLT2BLKEN,Fault 3 blanking enable" "0,1"
bitfld.long 0x10 15. "FLT1RST,Fault 1 reset mode" "0,1"
bitfld.long 0x10 14. "FLT1CNTRST,Fault 1 counter reset" "0,1"
hexmask.long.byte 0x10 10.--13. 1. "FLT1CNT,Fault 1 counter"
bitfld.long 0x10 9. "FLT1BLKS,Fault 1 blanking source" "0,1"
newline
bitfld.long 0x10 8. "FLT1BLKEN,Fault 1 blanking enable" "0,1"
bitfld.long 0x10 7. "FLT0RST,Fault 0 reset mode:" "0,1"
bitfld.long 0x10 6. "FLT0CNTRST,Fault 0 counter reset" "0,1"
hexmask.long.byte 0x10 2.--5. 1. "FLT0CNT,Fault 0 Counter:"
bitfld.long 0x10 1. "FLT0BLKS,Fault 0 blanking source" "0,1"
bitfld.long 0x10 0. "FLT0BLKEN,Fault 0 blanking enable" "0,1"
line.long 0x14 "FLTINCFG3,HRTIMER fault input configuration register 3"
bitfld.long 0x14 31. "FLT7RST,Fault 7 reset mode" "0,1"
bitfld.long 0x14 30. "FLT7CNTRST,Fault 7 counter reset" "0,1"
hexmask.long.byte 0x14 26.--29. 1. "FLT7CNT,Fault 7 counter"
bitfld.long 0x14 25. "FLT7BLKS,Fault 7 blanking source" "0,1"
bitfld.long 0x14 24. "FLT7BLKEN,Fault 7 blanking enable" "0,1"
bitfld.long 0x14 23. "FLT6RST,Fault 6 reset mode" "0,1"
bitfld.long 0x14 22. "FLT6CNTRST,Fault 6 counter reset" "0,1"
newline
hexmask.long.byte 0x14 18.--21. 1. "FLT6CNT,Fault 6 counter"
bitfld.long 0x14 17. "FLT6BLKS,Fault 6 blanking source" "0,1"
bitfld.long 0x14 16. "FLT6BLKEN,Fault 6 blanking enable" "0,1"
bitfld.long 0x14 15. "FLT5RST,Fault 5 reset mode" "0,1"
bitfld.long 0x14 14. "FLT5CNTRST,Fault 5 counter reset" "0,1"
hexmask.long.byte 0x14 10.--13. 1. "FLT5CNT,Fault 5 counter"
bitfld.long 0x14 9. "FLT5BLKS,Fault 5 blanking source" "0,1"
newline
bitfld.long 0x14 8. "FLT5BLKEN,Fault 5 blanking enable" "0,1"
bitfld.long 0x14 7. "FLT4RST,Fault 4 reset mode" "0,1"
bitfld.long 0x14 6. "FLT4CNTRST,Fault 4 counter reset" "0,1"
hexmask.long.byte 0x14 2.--5. 1. "FLT4CNT,Fault 4 counter"
bitfld.long 0x14 1. "FLT4BLKS,Fault 4 blanking source" "0,1"
bitfld.long 0x14 0. "FLT4BLKEN,Fault 4 blanking enable" "0,1"
group.long 0x108++0x1B
line.long 0x0 "BMSTRGA,HRTIMER bunch mode start trigger add register"
bitfld.long 0x0 11. "ST7CMP1,Slave_TIMER7 compare 1 event triggers bunch mode operation" "0,1"
bitfld.long 0x0 10. "ST7CMP0,Slave_TIMER7 compare 0 event triggers bunch mode operation" "0,1"
bitfld.long 0x0 9. "ST7REP,Slave_TIMER7 repetition event triggers bunch mode operation" "0,1"
bitfld.long 0x0 8. "ST7RST,Slave_TIMER7 reset event triggers bunch mode operation" "0,1"
bitfld.long 0x0 7. "ST6CMP1,Slave_TIMER6 compare 1 event triggers bunch mode operation" "0,1"
bitfld.long 0x0 6. "ST6CMP0,Slave_TIMER6 compare 0 event triggers bunch mode operation" "0,1"
bitfld.long 0x0 5. "ST6REP,Slave_TIMER6 repetition event triggers bunch mode operation" "0,1"
newline
bitfld.long 0x0 4. "ST6RST,Slave_TIMER6 reset event triggers bunch mode operation" "0,1"
bitfld.long 0x0 3. "ST5CMP1,Slave_TIMER5 compare 1 event triggers bunch mode operation" "0,1"
bitfld.long 0x0 2. "ST5CMP0,Slave_TIMER5 compare 0 event triggers bunch mode operation" "0,1"
bitfld.long 0x0 1. "ST5REP,Slave_TIMER5 repetition event triggers bunch mode operation" "0,1"
bitfld.long 0x0 0. "ST5RST,Slave_TIMER5 reset event triggers bunch mode operation" "0,1"
line.long 0x4 "FLTINCFG4,HRTIMER fault input configuration register 4"
bitfld.long 0x4 15. "FLT7INPROT,Protect fault 7 input configuration" "0,1"
hexmask.long.byte 0x4 11.--14. 1. "FLT7INFC,Fault 7 input filter control"
bitfld.long 0x4 10. "FLT7INSRC_0,Fault 7 input source" "0,1"
bitfld.long 0x4 9. "FLT7INP,Fault 7 input polarity" "0,1"
bitfld.long 0x4 8. "FLT7INEN,Fault 7 input enable" "0,1"
bitfld.long 0x4 7. "FLT6INPROT,Protect fault 6 input configuration" "0,1"
hexmask.long.byte 0x4 3.--6. 1. "FLT6INFC,Fault 6 input filter control"
newline
bitfld.long 0x4 2. "FLT6INSRC_0,Fault 6 input source" "0,1"
bitfld.long 0x4 1. "FLT6INP,Fault 6 input polarity" "0,1"
bitfld.long 0x4 0. "FLT6INEN,Fault 6 input enable" "0,1"
line.long 0x8 "ADCEXTTRGA,HRTIMER ADC extended trigger add register"
bitfld.long 0x8 5. "ADC9TRG_5,ADC trigger 9 selection This bit selects the ADC trigger 9 source" "0,1"
bitfld.long 0x8 4. "ADC8TRG_5,ADC trigger 8 selection This bit selects the ADC trigger 8 source" "0,1"
bitfld.long 0x8 3. "ADC7TRG_5,ADC trigger 7 selection This bit selects the ADC trigger 7 source" "0,1"
bitfld.long 0x8 2. "ADC6TRG_5,ADC trigger 6 selection This bit selects the ADC trigger 6 source" "0,1"
bitfld.long 0x8 1. "ADC5TRG_5,ADC trigger 5 selection This bit selects the ADC trigger 5 source" "0,1"
bitfld.long 0x8 0. "ADC4TRG_5,ADC trigger 4 selection This bit selects the ADC trigger 4 source" "0,1"
line.long 0xC "ADCTRIGS0A,HRTIMER trigger source 0 to ADC add register"
bitfld.long 0xC 20. "TRG0ST7RST,HRTIMER_ADCTRIG0 on Slave_TIMER7 reset" "0,1"
bitfld.long 0xC 19. "TRG0ST7PER,HRTIMER_ADCTRIG0 on Slave_TIMER7 period event" "0,1"
bitfld.long 0xC 18. "TRG0ST7C3,HRTIMER_ADCTRG0 on Slave_TIMER7 compare 3 event" "0,1"
bitfld.long 0xC 17. "TRG0ST7C2,HRTIMER_ADCTRG0 on Slave_TIMER7 compare 2 event" "0,1"
bitfld.long 0xC 16. "TRG0ST7C1,HRTIMER_ADCTRG0 on Slave_TIMER7 compare 1 event" "0,1"
bitfld.long 0xC 12. "TRG0ST6RST,HRTIMER_ADCTRIG0 on Slave_TIMER6 reset" "0,1"
bitfld.long 0xC 11. "TRG0ST6PER,HRTIMER_ADCTRIG0 on Slave_TIMER6 period event" "0,1"
newline
bitfld.long 0xC 10. "TRG0ST6C3,HRTIMER_ADCTRG0 on Slave_TIMER6 compare 3 event" "0,1"
bitfld.long 0xC 9. "TRG0ST6C2,HRTIMER_ADCTRG0 on Slave_TIMER6 compare 2 event" "0,1"
bitfld.long 0xC 8. "TRG0ST6C1,HRTIMER_ADCTRG0 on Slave_TIMER6 compare 1 event" "0,1"
bitfld.long 0xC 4. "TRG0ST5RST,HRTIMER_ADCTRIG0 on Slave_TIMER5 reset" "0,1"
bitfld.long 0xC 3. "TRG0ST5PER,HRTIMER_ADCTRIG0 on Slave_TIMER5 period event" "0,1"
bitfld.long 0xC 2. "TRG0ST5C3,HRTIMER_ADCTRG0 on Slave_TIMER5 compare 3 event" "0,1"
bitfld.long 0xC 1. "TRG0ST5C2,HRTIMER_ADCTRG0 on Slave_TIMER5 compare 2 event" "0,1"
newline
bitfld.long 0xC 0. "TRG0ST5C1,HRTIMER_ADCTRG0 on Slave_TIMER5 compare 1 event" "0,1"
line.long 0x10 "ADCTRIGS1A,HRTIMER trigger source 1 to ADC add register"
bitfld.long 0x10 20. "TRG1ST7RST,HRTIMER_ADCTRIG1 on Slave_TIMER7 reset" "0,1"
bitfld.long 0x10 19. "TRG1ST7PER,HRTIMER_ADCTRIG1 on Slave_TIMER7 period event" "0,1"
bitfld.long 0x10 18. "TRG1ST7C3,HRTIMER_ADCTRG1 on Slave_TIMER7 compare 3 event" "0,1"
bitfld.long 0x10 17. "TRG1ST7C2,HRTIMER_ADCTRG1 on Slave_TIMER7 compare 2 event" "0,1"
bitfld.long 0x10 16. "TRG1ST7C1,HRTIMER_ADCTRG1 on Slave_TIMER7 compare 1 event" "0,1"
bitfld.long 0x10 12. "TRG1ST6RST,HRTIMER_ADCTRIG1 on Slave_TIMER6 reset" "0,1"
bitfld.long 0x10 11. "TRG1ST6PER,HRTIMER_ADCTRIG1 on Slave_TIMER6 period event" "0,1"
newline
bitfld.long 0x10 10. "TRG1ST6C3,HRTIMER_ADCTRG1 on Slave_TIMER6 compare 3 event" "0,1"
bitfld.long 0x10 9. "TRG1ST6C2,HRTIMER_ADCTRG1 on Slave_TIMER6 compare 2 event" "0,1"
bitfld.long 0x10 8. "TRG1ST6C1,HRTIMER_ADCTRG1 on Slave_TIMER6 compare 1 event" "0,1"
bitfld.long 0x10 4. "TRG1ST5RST,HRTIMER_ADCTRIG1 on Slave_TIMER5 reset" "0,1"
bitfld.long 0x10 3. "TRG1ST5PER,HRTIMER_ADCTRIG1 on Slave_TIMER5 period event" "0,1"
bitfld.long 0x10 2. "TRG1ST5C3,HRTIMER_ADCTRG1 on Slave_TIMER5 compare 3 event" "0,1"
bitfld.long 0x10 1. "TRG1ST5C2,HRTIMER_ADCTRG1 on Slave_TIMER5 compare 2 event" "0,1"
newline
bitfld.long 0x10 0. "TRG1ST5C1,HRTIMER_ADCTRG1 on Slave_TIMER5 compare 1 event" "0,1"
line.long 0x14 "ADCTRIGS2A,HRTIMER trigger source 2 to ADC add register"
bitfld.long 0x14 20. "TRG2ST7RST,HRTIMER_ADCTRIG2 on Slave_TIMER7 reset" "0,1"
bitfld.long 0x14 19. "TRG2ST7PER,HRTIMER_ADCTRIG2 on Slave_TIMER7 period event" "0,1"
bitfld.long 0x14 18. "TRG2ST7C3,HRTIMER_ADCTRG2 on Slave_TIMER7 compare 3 event" "0,1"
bitfld.long 0x14 17. "TRG2ST7C2,HRTIMER_ADCTRG2 on Slave_TIMER7 compare 2 event" "0,1"
bitfld.long 0x14 16. "TRG2ST7C1,HRTIMER_ADCTRG2 on Slave_TIMER7 compare 1 event" "0,1"
bitfld.long 0x14 12. "TRG2ST6RST,HRTIMER_ADCTRIG2 on Slave_TIMER6 reset" "0,1"
bitfld.long 0x14 11. "TRG2ST6PER,HRTIMER_ADCTRIG2 on Slave_TIMER6 period event" "0,1"
newline
bitfld.long 0x14 10. "TRG2ST6C3,HRTIMER_ADCTRG2 on Slave_TIMER6 compare 3 event" "0,1"
bitfld.long 0x14 9. "TRG2ST6C2,HRTIMER_ADCTRG2 on Slave_TIMER6 compare 2 event" "0,1"
bitfld.long 0x14 8. "TRG2ST6C1,HRTIMER_ADCTRG2 on Slave_TIMER6 compare 1 event" "0,1"
bitfld.long 0x14 4. "TRG2ST5RST,HRTIMER_ADCTRIG2 on Slave_TIMER5 reset" "0,1"
bitfld.long 0x14 3. "TRG2ST5PER,HRTIMER_ADCTRIG2 on Slave_TIMER5 period event" "0,1"
bitfld.long 0x14 2. "TRG2ST5C3,HRTIMER_ADCTRG2 on Slave_TIMER5 compare 3 event" "0,1"
bitfld.long 0x14 1. "TRG2ST5C2,HRTIMER_ADCTRG2 on Slave_TIMER5 compare 2 event" "0,1"
newline
bitfld.long 0x14 0. "TRG2ST5C1,HRTIMER_ADCTRG2 on Slave_TIMER5 compare 1 event" "0,1"
line.long 0x18 "ADCTRIGS3A,HRTIMER trigger source 3 to ADC add register"
bitfld.long 0x18 20. "TRG3ST7RST,HRTIMER_ADCTRIG3 on Slave_TIMER7 reset" "0,1"
bitfld.long 0x18 19. "TRG3ST7PER,HRTIMER_ADCTRIG3 on Slave_TIMER7 period event" "0,1"
bitfld.long 0x18 18. "TRG3ST7C3,HRTIMER_ADCTRG3 on Slave_TIMER7 compare 3 event" "0,1"
bitfld.long 0x18 17. "TRG3ST7C2,HRTIMER_ADCTRG3 on Slave_TIMER7 compare 2 event" "0,1"
bitfld.long 0x18 16. "TRG3ST7C1,HRTIMER_ADCTRG3 on Slave_TIMER7 compare 1 event" "0,1"
bitfld.long 0x18 12. "TRG3ST6RST,HRTIMER_ADCTRIG3 on Slave_TIMER6 reset" "0,1"
bitfld.long 0x18 11. "TRG3ST6PER,HRTIMER_ADCTRIG3 on Slave_TIMER6 period event" "0,1"
newline
bitfld.long 0x18 10. "TRG3ST6C3,HRTIMER_ADCTRG3 on Slave_TIMER6 compare 3 event" "0,1"
bitfld.long 0x18 9. "TRG3ST6C2,HRTIMER_ADCTRG3 on Slave_TIMER6 compare 2 event" "0,1"
bitfld.long 0x18 8. "TRG3ST6C1,HRTIMER_ADCTRG3 on Slave_TIMER6 compare 1 event" "0,1"
bitfld.long 0x18 4. "TRG3ST5RST,HRTIMER_ADCTRIG3 on Slave_TIMER5 reset" "0,1"
bitfld.long 0x18 3. "TRG3ST5PER,HRTIMER_ADCTRIG3 on Slave_TIMER5 period event" "0,1"
bitfld.long 0x18 2. "TRG3ST5C3,HRTIMER_ADCTRG3 on Slave_TIMER5 compare 3 event" "0,1"
bitfld.long 0x18 1. "TRG3ST5C2,HRTIMER_ADCTRG3 on Slave_TIMER5 compare 2 event" "0,1"
newline
bitfld.long 0x18 0. "TRG3ST5C1,HRTIMER_ADCTRG3 on Slave_TIMER5 compare 1 event" "0,1"
tree.end
tree "HRTIMER_MASTER_TIMER"
base ad:0x40015800
group.long 0x0++0x3
line.long 0x0 "MTCTL0,HRTIMER Master_TIMER control register 0"
bitfld.long 0x0 30.--31. "UPSEL,Update event selection" "0,1,2,3"
bitfld.long 0x0 29. "UPREP,Update event generated by repetition event" "0,1"
bitfld.long 0x0 27. "SHWEN,Shadow registers enable" "0,1"
bitfld.long 0x0 25.--26. "DACTRGS,Trigger source to DAC" "0,1,2,3"
bitfld.long 0x0 24. "ST7CEN,The counter of Slave_TIMER7 enable" "0,1"
bitfld.long 0x0 23. "ST6CEN,The counter of Slave_TIMER6 enable" "0,1"
bitfld.long 0x0 22. "ST5CEN,The counter of Slave_TIMER5 enable" "0,1"
bitfld.long 0x0 21. "ST4CEN,The counter of Slave_TIMER4 enable" "0,1"
bitfld.long 0x0 20. "ST3CEN,The counter of Slave_TIMER3 enable" "0,1"
bitfld.long 0x0 19. "ST2CEN,The counter of Slave_TIMER2 enable" "0,1"
bitfld.long 0x0 18. "ST1CEN,The counter of Slave_TIMER1 enable" "0,1"
newline
bitfld.long 0x0 17. "ST0CEN,The counter of Slave_TIMER0 enable" "0,1"
bitfld.long 0x0 16. "MTCEN,The counter of Master_TIMER enable" "0,1"
bitfld.long 0x0 14.--15. "SYNOSRC,Synchronization output source" "0,1,2,3"
bitfld.long 0x0 12.--13. "SYNOPLS,Synchronization output pulse" "0,1,2,3"
bitfld.long 0x0 11. "SYNISTRT,Synchronization input start counter" "0,1"
bitfld.long 0x0 10. "SYNIRST,Synchronization input reset counter" "0,1"
bitfld.long 0x0 8.--9. "SYNISRC,Synchronization input source" "0,1,2,3"
bitfld.long 0x0 6.--7. "ALTM,Alternate mode" "0,1,2,3"
bitfld.long 0x0 5. "HALFM,Half mode" "0,1"
bitfld.long 0x0 4. "CNTRSTM,Counter reset mode" "0,1"
bitfld.long 0x0 3. "CTNM,Continuous mode" "0,1"
newline
bitfld.long 0x0 0.--2. "CNTCKDIV,Counter clock division" "0,1,2,3,4,5,6,7"
rgroup.long 0x4++0x3
line.long 0x0 "MTINTF,HRTIMER Master_TIMER interrupt flag register"
bitfld.long 0x0 6. "UPIF,Update interrupt flag" "0,1"
bitfld.long 0x0 5. "SYNIIF,Synchronization input interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIF,Repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IF,Compare 3 interrupt flag" "0,1"
bitfld.long 0x0 2. "CMP2IF,Compare 2 interrupt flag" "0,1"
bitfld.long 0x0 1. "CMP1IF,Compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IF,Compare 0 interrupt flag" "0,1"
wgroup.long 0x8++0x3
line.long 0x0 "MTINTC,HRTIMER Master_TIMER interrupt flag clear register"
bitfld.long 0x0 6. "UPIFC,Clear update interrupt flag" "0,1"
bitfld.long 0x0 5. "SYNIIFC,Clear synchronization input interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIFC,Clear repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IFC,Clear compare 3 interrupt flag" "0,1"
bitfld.long 0x0 2. "CMP2IFC,Clear compare 2 interrupt flag" "0,1"
bitfld.long 0x0 1. "CMP1IFC,Clear compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IFC,Clear compare 0 interrupt flag" "0,1"
group.long 0xC++0x13
line.long 0x0 "MTDMAINTEN,HRTIMER Master_TIMER DMA and interrupt enable register"
bitfld.long 0x0 22. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x0 21. "SYNIDEN,Synchronization input DMA request enable" "0,1"
bitfld.long 0x0 20. "REPDEN,Repetition DMA request enable" "0,1"
bitfld.long 0x0 19. "CMP3DEN,Compare 3 DMA request enable" "0,1"
bitfld.long 0x0 18. "CMP2DEN,Compare 2 DMA request enable" "0,1"
bitfld.long 0x0 17. "CMP1DEN,Compare 1 DMA request enable" "0,1"
bitfld.long 0x0 16. "CMP0DEN,Compare 0 DMA request enable" "0,1"
bitfld.long 0x0 6. "UPIE,Update interrupt enable" "0,1"
bitfld.long 0x0 5. "SYNIIE,Synchronization input interrupt enable" "0,1"
bitfld.long 0x0 4. "REPIE,Repetition interrupt enable" "0,1"
bitfld.long 0x0 3. "CMP3IE,Compare 3 interrupt enable" "0,1"
newline
bitfld.long 0x0 2. "CMP2IE,Compare 2 interrupt enable" "0,1"
bitfld.long 0x0 1. "CMP1IE,Compare 1 interrupt enable" "0,1"
bitfld.long 0x0 0. "CMP0IE,Compare 0 interrupt enable" "0,1"
line.long 0x4 "MTCNT,HRTIMER Master_TIMER counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,The current counter value"
line.long 0x8 "MTCAR,HRTIMER Master_TIMER counter auto reload register"
hexmask.long.word 0x8 0.--15. 1. "CARL,Counter auto reload value"
line.long 0xC "MTCREP,HRTIMER Master_TIMER counter repetition register"
hexmask.long.byte 0xC 0.--7. 1. "CREP,Counter repetition value"
line.long 0x10 "MTCMP0V,HRTIMER Master_TIMER compare 0 value register"
hexmask.long.word 0x10 0.--15. 1. "CMP0VAL,Compare 0 value"
group.long 0x24++0xB
line.long 0x0 "MTCMP1V,HRTIMER Master_TIMER compare 1 value register"
hexmask.long.word 0x0 0.--15. 1. "CMP1VAL,Compare 1 value"
line.long 0x4 "MTCMP2V,HRTIMER Master_TIMER compare 2 value register"
hexmask.long.word 0x4 0.--15. 1. "CMP2VAL,Compare 2 value"
line.long 0x8 "MTCMP3V,HRTIMER Master_TIMER compare 3 value register"
hexmask.long.word 0x8 0.--15. 1. "CMP3VAL,Compare 3 value"
tree.end
tree "HRTIMER_SLAVE_TIMER0"
base ad:0x40015880
group.long 0x0++0x3
line.long 0x0 "ST0CTL0,HRTIMER Slave_TIMER0 control register 0"
hexmask.long.byte 0x0 28.--31. 1. "UPSEL,Update event selection"
bitfld.long 0x0 27. "SHWEN,Shadow registers enable" "0,1"
bitfld.long 0x0 25.--26. "DACTRGS,Trigger source to DAC" "0,1,2,3"
bitfld.long 0x0 24. "UPBMT,Update by Master_TIMER update event" "0,1"
bitfld.long 0x0 23. "UPBST4,Update by Slave_TIMER4 update event" "0,1"
bitfld.long 0x0 22. "UPBST3,Update by Slave_TIMER3 update event" "0,1"
newline
bitfld.long 0x0 21. "UPBST2,Update by Slave_TIMER2 update event" "0,1"
bitfld.long 0x0 20. "UPBST1,Update by Slave_TIMER1 update event" "0,1"
bitfld.long 0x0 19. "UPBST0,Update by Slave_TIMER0 update event" "0,1"
bitfld.long 0x0 18. "UPRST,Update event generated by reset event" "0,1"
bitfld.long 0x0 17. "UPREP,Update event generated by repetition event" "0,1"
bitfld.long 0x0 16. "UPBST5,Update by Slave_TIMER5 update event" "0,1"
newline
bitfld.long 0x0 14.--15. "DELCMP3M,Compare 3 delayed mode" "0,1,2,3"
bitfld.long 0x0 12.--13. "DELCMP1M,Compare 1 delayed mode" "0,1,2,3"
bitfld.long 0x0 11. "SYNISTRT,Synchronous input start timer" "0,1"
bitfld.long 0x0 10. "SYNIRST,Synchronous input reset timer" "0,1"
bitfld.long 0x0 9. "RSYNUPD,Re-synchronized update" "0,1"
bitfld.long 0x0 7.--8. "ALTM,Alternate mode" "0,1,2,3"
newline
bitfld.long 0x0 6. "BLNMEN,Balanced mode enable" "0,1"
bitfld.long 0x0 5. "HALFM,Half mode" "0,1"
bitfld.long 0x0 4. "CNTRSTM,Counter reset mode" "0,1"
bitfld.long 0x0 3. "CTNM,Continuous mode" "0,1"
bitfld.long 0x0 0.--2. "CNTCKDIV,Counter clock division" "0,1,2,3,4,5,6,7"
rgroup.long 0x4++0x3
line.long 0x0 "ST0INTF,HRTIMER Slave_TIMER0 interrupt flag register"
bitfld.long 0x0 31. "DIR,Direction" "0,1"
bitfld.long 0x0 21. "CH1F,Channel 1 output flag" "0,1"
bitfld.long 0x0 20. "CH0F,Channel 0 output flag" "0,1"
bitfld.long 0x0 19. "CH1SF,Channel 1 output state flag" "0,1"
bitfld.long 0x0 18. "CH0SF,Channel 0 output state flag" "0,1"
bitfld.long 0x0 17. "BLNIF,Balanced IDLE flag" "0,1"
newline
bitfld.long 0x0 16. "CBLNF,Current balanced flag" "0,1"
bitfld.long 0x0 14. "DLYIIF,Delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x0 13. "RSTIF,Counter reset interrupt flag" "0,1"
bitfld.long 0x0 12. "CH1ONAIF,Channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x0 11. "CH1OAIF,Channel 1 output active interrupt flag" "0,1"
bitfld.long 0x0 10. "CH0ONAIF,Channel 0 output inactive interrupt flag" "0,1"
newline
bitfld.long 0x0 9. "CH0OAIF,Channel 0 output active interrupt flag" "0,1"
bitfld.long 0x0 8. "CAP1IF,Capture 1 interrupt flag" "0,1"
bitfld.long 0x0 7. "CAP0IF,Capture 0 interrupt flag" "0,1"
bitfld.long 0x0 6. "UPIF,Update interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIF,Repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IF,Compare 3 interrupt flag" "0,1"
newline
bitfld.long 0x0 2. "CMP2IF,Compare 2 interrupt flag" "0,1"
bitfld.long 0x0 1. "CMP1IF,Compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IF,Compare 0 interrupt flag" "0,1"
wgroup.long 0x8++0x3
line.long 0x0 "ST0INTC,HRTIMER Slave_TIMER0 interrupt flag clear register"
bitfld.long 0x0 14. "DLYIIFC,Clear delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x0 13. "RSTIFC,Clear counter reset interrupt flag" "0,1"
bitfld.long 0x0 12. "CH1ONAIFC,Clear channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x0 11. "CH1OAIFC,Clear channel 1 output active interrupt flag" "0,1"
bitfld.long 0x0 10. "CH0ONAIFC,Clear channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x0 9. "CH0OAIFC,Clear channel 0 output active interrupt flag" "0,1"
newline
bitfld.long 0x0 8. "CAP1IFC,Clear capture 1 interrupt flag" "0,1"
bitfld.long 0x0 7. "CAP0IFC,Clear capture 0 interrupt flag" "0,1"
bitfld.long 0x0 6. "UPIFC,Clear update interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIFC,Clear repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IFC,Clear compare 3 interrupt flag" "0,1"
bitfld.long 0x0 2. "CMP2IFC,Clear compare 2 interrupt flag" "0,1"
newline
bitfld.long 0x0 1. "CMP1IFC,Clear compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IFC,Clear compare 0 interrupt flag" "0,1"
group.long 0xC++0x23
line.long 0x0 "ST0DMAINTEN,HRTIMER Slave_TIMER0 DMA and interrupt enable register"
bitfld.long 0x0 30. "DLYIDEN,Delayed IDLE mode entry DMA request enable" "0,1"
bitfld.long 0x0 29. "RSTDEN,Counter reset DMA request enable" "0,1"
bitfld.long 0x0 28. "CH1ONADEN,Channel 1 output inactive DMA request enable" "0,1"
bitfld.long 0x0 27. "CH1OADEN,Channel 1 output active DMA request enable" "0,1"
bitfld.long 0x0 26. "CH0ONADEN,Channel 0 output inactive DMA request enable" "0,1"
bitfld.long 0x0 25. "CH0OADEN,Channel 0 output active DMA request enable" "0,1"
newline
bitfld.long 0x0 24. "CAP1DEN,Capture 1 DMA request enable" "0,1"
bitfld.long 0x0 23. "CAP0DEN,Capture 0 DMA request enable" "0,1"
bitfld.long 0x0 22. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x0 20. "REPDEN,Repetition DMA request enable" "0,1"
bitfld.long 0x0 19. "CMP3DEN,Compare 3 DMA request enable" "0,1"
bitfld.long 0x0 18. "CMP2DEN,Compare 2 DMA request enable" "0,1"
newline
bitfld.long 0x0 17. "CMP1DEN,Compare 1 DMA request enable" "0,1"
bitfld.long 0x0 16. "CMP0DEN,Compare 0 DMA request enable" "0,1"
bitfld.long 0x0 14. "DLYIIE,Delayed IDLE mode entry interrupt enable" "0,1"
bitfld.long 0x0 13. "RSTIE,Counter reset interrupt enable" "0,1"
bitfld.long 0x0 12. "CH1ONAIE,Channel 1 output inactive interrupt enable" "0,1"
bitfld.long 0x0 11. "CH1OAIE,Channel 1 output active interrupt enable" "0,1"
newline
bitfld.long 0x0 10. "CH0ONAIE,Channel 0 output inactive interrupt enable" "0,1"
bitfld.long 0x0 9. "CH0OAIE,Channel 0 output active interrupt enable" "0,1"
bitfld.long 0x0 8. "CAP1IE,Capture 1 interrupt enable" "0,1"
bitfld.long 0x0 7. "CAP0IE,Capture 0 interrupt enable" "0,1"
bitfld.long 0x0 6. "UPIE,Update interrupt enable" "0,1"
bitfld.long 0x0 4. "REPIE,Repetition interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "CMP3IE,Compare 3 interrupt enable" "0,1"
bitfld.long 0x0 2. "CMP2IE,Compare 2 interrupt enable" "0,1"
bitfld.long 0x0 1. "CMP1IE,Compare 1 interrupt enable" "0,1"
bitfld.long 0x0 0. "CMP0IE,Compare 0 interrupt enable" "0,1"
line.long 0x4 "ST0CNT,HRTIMER Slave_TIMER0 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,The current counter value"
line.long 0x8 "ST0CAR,HRTIMER Slave_TIMER0 counter auto reload register"
hexmask.long.word 0x8 0.--15. 1. "CARL,Counter auto reload value"
line.long 0xC "ST0CREP,HRTIMER Slave_TIMER0 counter repetition register"
hexmask.long.byte 0xC 0.--7. 1. "CREP,Counter repetition value"
line.long 0x10 "ST0CMP0V,HRTIMER Slave_TIMER0 compare 0 value register"
hexmask.long.word 0x10 0.--15. 1. "CMP0VAL,Compare 0 value"
line.long 0x14 "ST0CMP0CP,HRTIMER Slave_TIMER0 compare 0 composite register"
hexmask.long.byte 0x14 16.--23. 1. "CREP,Counter repetition value"
hexmask.long.word 0x14 0.--15. 1. "CMP0VAL,Compare 0 value"
line.long 0x18 "ST0CMP1V,HRTIMER Slave_TIMER0 compare 1 value register"
hexmask.long.word 0x18 0.--15. 1. "CMP1VAL,Compare 1 value"
line.long 0x1C "ST0CMP2V,HRTIMER Slave_TIMER0 compare 2 value register"
hexmask.long.word 0x1C 0.--15. 1. "CMP2VAL,Compare 2 value"
line.long 0x20 "ST0CMP3V,HRTIMER Slave_TIMER0 compare 3 value register"
hexmask.long.word 0x20 0.--15. 1. "CMP3VAL,Compare 3 value"
rgroup.long 0x30++0x7
line.long 0x0 "ST0CAP0V,HRTIMER Slave_TIMER0 capture 0 value register"
bitfld.long 0x0 16. "DIR,Slave_timer 0 capture 1 direction status" "0,1"
hexmask.long.word 0x0 0.--15. 1. "CAP0VAL,Capture 0 value"
line.long 0x4 "ST0CAP1V,HRTIMER Slave_TIMER0 capture 1 value register"
bitfld.long 0x4 16. "DIR,Slave_Timer 0 capture 1 direction status" "0,1"
hexmask.long.word 0x4 0.--15. 1. "CAP1VAL,Capture 1 value"
group.long 0x38++0x47
line.long 0x0 "ST0DTCTL,HRTIMER Slave_TIMER0 dead-time control register"
bitfld.long 0x0 31. "DTFSVPROT,Dead-time falling edge protection for value and sign" "0,1"
bitfld.long 0x0 30. "DTFSPROT,Dead-time falling edge protection for sign" "0,1"
bitfld.long 0x0 25. "DTFS,The sign of falling edge dead-time value" "0,1"
hexmask.long.word 0x0 16.--24. 1. "DTFCFG,Falling edge dead-time value"
bitfld.long 0x0 15. "DTRSVPROT,Dead-time rising edge protection for value and sign" "0,1"
bitfld.long 0x0 14. "DTRSPROT,Dead-time rising edge protection for sign" "0,1"
newline
hexmask.long.byte 0x0 10.--13. 1. "DTGCKDIV,Dead time clock division"
bitfld.long 0x0 9. "DTRS,The sign of rising edge dead-time value" "0,1"
hexmask.long.word 0x0 0.--8. 1. "DTRCFG,Rising edge dead-time value"
line.long 0x4 "ST0CH0SET,HRTIMER Slave_TIMER0 channel 0 set request register"
bitfld.long 0x4 31. "CH0SUP,Update event generates channel 0 set request" "0,1"
bitfld.long 0x4 30. "CH0SEXEV9,External event 9 generates channel 0 set request" "0,1"
bitfld.long 0x4 29. "CH0SEXEV8,External event 8 generates channel 0 set request" "0,1"
bitfld.long 0x4 28. "CH0SEXEV7,External event 7 generates channel 0 set request" "0,1"
bitfld.long 0x4 27. "CH0SEXEV6,External event 6 generates channel 0 set request" "0,1"
bitfld.long 0x4 26. "CH0SEXEV5,External event 5 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 25. "CH0SEXEV4,External event 4 generates channel 0 set request" "0,1"
bitfld.long 0x4 24. "CH0SEXEV3,External event 3 generates channel 0 set request" "0,1"
bitfld.long 0x4 23. "CH0SEXEV2,External event 2 generates channel 0 set request" "0,1"
bitfld.long 0x4 22. "CH0SEXEV1,External event 1 generates channel 0 set request" "0,1"
bitfld.long 0x4 21. "CH0SEXEV0,External event 0 generates channel 0 set request" "0,1"
bitfld.long 0x4 20. "CH0SSTEV8,interconnection event 8 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 19. "CH0SSTEV7,interconnection event 7 generates channel 0 set request" "0,1"
bitfld.long 0x4 18. "CH0SSTEV6,interconnection event 6 generates channel 0 set request" "0,1"
bitfld.long 0x4 17. "CH0SSTEV5,interconnection event 5 generates channel 0 set request" "0,1"
bitfld.long 0x4 16. "CH0SSTEV4,interconnection event 4 generates channel 0 set request" "0,1"
bitfld.long 0x4 15. "CH0SSTEV3,interconnection event 3 generates channel 0 set request" "0,1"
bitfld.long 0x4 14. "CH0SSTEV2,interconnection event 2 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 13. "CH0SSTEV1,interconnection event 1 generates channel 0 set request" "0,1"
bitfld.long 0x4 12. "CH0SSTEV0,interconnection event 0 generates channel 0 set request" "0,1"
bitfld.long 0x4 11. "CH0SMTCMP3,Master_TIMER compare 3 event generates channel 0 set request" "0,1"
bitfld.long 0x4 10. "CH0SMTCMP2,Master_TIMER compare 2 event generates channel 0 set request" "0,1"
bitfld.long 0x4 9. "CH0SMTCMP1,Master_TIMER compare 1 event generates channel 0 set request" "0,1"
bitfld.long 0x4 8. "CH0SMTCMP0,Master_TIMER compare 0 event generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 7. "CH0SMTPER,Master_TIMER period event generates channel 0 set request" "0,1"
bitfld.long 0x4 6. "CH0SCMP3,compare 3 event generates channel 0 set request" "0,1"
bitfld.long 0x4 5. "CH0SCMP2,compare 2 event generates channel 0 set request" "0,1"
bitfld.long 0x4 4. "CH0SCMP1,compare 1 event generates channel 0 set request" "0,1"
bitfld.long 0x4 3. "CH0SCMP0,compare 0 event generates channel 0 set request" "0,1"
bitfld.long 0x4 2. "CH0SPER,period event generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 1. "CH0SRST,reset event generates channel 0 set request" "0,1"
bitfld.long 0x4 0. "CH0SSEV,Software event generates channel 0 set request" "0,1"
line.long 0x8 "ST0CH0RST,HRTIMER Slave_TIMER0 channel 0 reset request register"
bitfld.long 0x8 31. "CH0RSUP,Update event generates channel 0 reset request" "0,1"
bitfld.long 0x8 30. "CH0RSEXEV9,External event 9 generates channel 0 reset request" "0,1"
bitfld.long 0x8 29. "CH0RSEXEV8,External event 8 generates channel 0 reset request" "0,1"
bitfld.long 0x8 28. "CH0RSEXEV7,External event 7 generates channel 0 reset request" "0,1"
bitfld.long 0x8 27. "CH0RSEXEV6,External event 6 generates channel 0 reset request" "0,1"
bitfld.long 0x8 26. "CH0RSEXEV5,External event 5 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 25. "CH0RSEXEV4,External event 4 generates channel 0 reset request" "0,1"
bitfld.long 0x8 24. "CH0RSEXEV3,External event 3 generates channel 0 reset request" "0,1"
bitfld.long 0x8 23. "CH0RSEXEV2,External event 2 generates channel 0 reset request" "0,1"
bitfld.long 0x8 22. "CH0RSEXEV1,External event 1 generates channel 0 reset request" "0,1"
bitfld.long 0x8 21. "CH0RSEXEV0,External event 0 generates channel 0 reset request" "0,1"
bitfld.long 0x8 20. "CH0RSSTEV8,interconnection event 8 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 19. "CH0RSSTEV7,interconnection event 7 generates channel 0 reset request" "0,1"
bitfld.long 0x8 18. "CH0RSSTEV6,interconnection event 6 generates channel 0 reset request" "0,1"
bitfld.long 0x8 17. "CH0RSSTEV5,interconnection event 5 generates channel 0 reset request" "0,1"
bitfld.long 0x8 16. "CH0RSSTEV4,interconnection event 4 generates channel 0 reset request" "0,1"
bitfld.long 0x8 15. "CH0RSSTEV3,interconnection event 3 generates channel 0 reset request" "0,1"
bitfld.long 0x8 14. "CH0RSSTEV2,interconnection event 2 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 13. "CH0RSSTEV1,interconnection event 1 generates channel 0 reset request" "0,1"
bitfld.long 0x8 12. "CH0RSSTEV0,interconnection event 0 generates channel 0 reset request" "0,1"
bitfld.long 0x8 11. "CH0RSMTCMP3,Master_TIMER compare 3 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 10. "CH0RSMTCMP2,Master_TIMER compare 2 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 9. "CH0RSMTCMP1,Master_TIMER compare 1 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 8. "CH0RSMTCMP0,Master_TIMER compare 0 event generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 7. "CH0RSMTPER,Master_TIMER period event generates channel 0 reset request" "0,1"
bitfld.long 0x8 6. "CH0RSCMP3,compare 3 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 5. "CH0RSCMP2,compare 2 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 4. "CH0RSCMP1,compare 1 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 3. "CH0RSCMP0,compare 0 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 2. "CH0RSPER,period event generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 1. "CH0RSRST,reset event generates channel 0 reset request" "0,1"
bitfld.long 0x8 0. "CH0RSSEV,Software event generates channel 0 reset request" "0,1"
line.long 0xC "ST0CH1SET,HRTIMER Slave_TIMER0 channel 1 set request register"
bitfld.long 0xC 31. "CH1SUP,Update event generates channel 1 set request" "0,1"
bitfld.long 0xC 30. "CH1SEXEV9,External event 9 generates channel 1 set request" "0,1"
bitfld.long 0xC 29. "CH1SEXEV8,External event 8 generates channel 1 set request" "0,1"
bitfld.long 0xC 28. "CH1SEXEV7,External event 7 generates channel 1 set request" "0,1"
bitfld.long 0xC 27. "CH1SEXEV6,External event 6 generates channel 1 set request" "0,1"
bitfld.long 0xC 26. "CH1SEXEV5,External event 5 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 25. "CH1SEXEV4,External event 4 generates channel 1 set request" "0,1"
bitfld.long 0xC 24. "CH1SEXEV3,External event 3 generates channel 1 set request" "0,1"
bitfld.long 0xC 23. "CH1SEXEV2,External event 2 generates channel 1 set request" "0,1"
bitfld.long 0xC 22. "CH1SEXEV1,External event 1 generates channel 1 set request" "0,1"
bitfld.long 0xC 21. "CH1SEXEV0,External event 0 generates channel 1 set request" "0,1"
bitfld.long 0xC 20. "CH1SSTEV8,interconnection event 8 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 19. "CH1SSTEV7,interconnection event 7 generates channel 1 set request" "0,1"
bitfld.long 0xC 18. "CH1SSTEV6,interconnection event 6 generates channel 1 set request" "0,1"
bitfld.long 0xC 17. "CH1SSTEV5,interconnection event 5 generates channel 1 set request" "0,1"
bitfld.long 0xC 16. "CH1SSTEV4,interconnection event 4 generates channel 1 set request" "0,1"
bitfld.long 0xC 15. "CH1SSTEV3,interconnection event 3 generates channel 1 set request" "0,1"
bitfld.long 0xC 14. "CH1SSTEV2,interconnection event 2 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 13. "CH1SSTEV1,interconnection event 1 generates channel 1 set request" "0,1"
bitfld.long 0xC 12. "CH1SSTEV0,interconnection event 0 generates channel 1 set request" "0,1"
bitfld.long 0xC 11. "CH1SMTCMP3,Master_TIMER compare 3 event generates channel 1 set request" "0,1"
bitfld.long 0xC 10. "CH1SMTCMP2,Master_TIMER compare 2 event generates channel 1 set request" "0,1"
bitfld.long 0xC 9. "CH1SMTCMP1,Master_TIMER compare 1 event generates channel 1 set request" "0,1"
bitfld.long 0xC 8. "CH1SMTCMP0,Master_TIMER compare 0 event generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 7. "CH1SMTPER,Master_TIMER period event generates channel 1 set request" "0,1"
bitfld.long 0xC 6. "CH1SCMP3,compare 3 event generates channel 1 set request" "0,1"
bitfld.long 0xC 5. "CH1SCMP2,compare 2 event generates channel 1 set request" "0,1"
bitfld.long 0xC 4. "CH1SCMP1,compare 1 event generates channel 1 set request" "0,1"
bitfld.long 0xC 3. "CH1SCMP0,compare 0 event generates channel 1 set request" "0,1"
bitfld.long 0xC 2. "CH1SPER,period event generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 1. "CH1SRST,reset event generates channel 1 set request" "0,1"
bitfld.long 0xC 0. "CH1SSEV,Software event generates channel 1 set request" "0,1"
line.long 0x10 "ST0CH1RST,HRTIMER Slave_TIMER0 channel 1 reset request register"
bitfld.long 0x10 31. "CH1RSUP,Update event generates channel 1 reset request" "0,1"
bitfld.long 0x10 30. "CH1RSEXEV9,External event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x10 29. "CH1RSEXEV8,External event 8 generates channel 1 reset request" "0,1"
bitfld.long 0x10 28. "CH1RSEXEV7,External event 7 generates channel 1 reset request" "0,1"
bitfld.long 0x10 27. "CH1RSEXEV6,External event 6 generates channel 1 reset request" "0,1"
bitfld.long 0x10 26. "CH1RSEXEV5,External event 5 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 25. "CH1RSEXEV4,External event 4 generates channel 1 reset request" "0,1"
bitfld.long 0x10 24. "CH1RSEXEV3,External event 3 generates channel 1 reset request" "0,1"
bitfld.long 0x10 23. "CH1RSEXEV2,External event 2 generates channel 1 reset request" "0,1"
bitfld.long 0x10 22. "CH1RSEXEV1,External event 1 generates channel 1 reset request" "0,1"
bitfld.long 0x10 21. "CH1RSEXEV0,External event 0 generates channel 1 reset request" "0,1"
bitfld.long 0x10 20. "CH1RSSTEV8,interconnection event 8 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 19. "CH1RSSTEV7,interconnection event 7 generates channel 1 reset request" "0,1"
bitfld.long 0x10 18. "CH1RSSTEV6,interconnection event 6 generates channel 1 reset request" "0,1"
bitfld.long 0x10 17. "CH1RSSTEV5,interconnection event 5 generates channel 1 reset request" "0,1"
bitfld.long 0x10 16. "CH1RSSTEV4,interconnection event 4 generates channel 1 reset request" "0,1"
bitfld.long 0x10 15. "CH1RSSTEV3,interconnection event 3 generates channel 1 reset request" "0,1"
bitfld.long 0x10 14. "CH1RSSTEV2,interconnection event 2 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 13. "CH1RSSTEV1,interconnection event 1 generates channel 1 reset request" "0,1"
bitfld.long 0x10 12. "CH1RSSTEV0,interconnection event 0 generates channel 1 reset request" "0,1"
bitfld.long 0x10 11. "CH1RSMTCMP3,Master_TIMER compare 3 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 10. "CH1RSMTCMP2,Master_TIMER compare 2 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 9. "CH1RSMTCMP1,Master_TIMER compare 1 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 8. "CH1RSMTCMP0,Master_TIMER compare 0 event generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 7. "CH1RSMTPER,Master_TIMER period event generates channel 1 reset request" "0,1"
bitfld.long 0x10 6. "CH1RSCMP3,compare 3 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 5. "CH1RSCMP2,compare 2 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 4. "CH1RSCMP1,compare 1 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 3. "CH1RSCMP0,compare 0 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 2. "CH1RSPER,period event generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 1. "CH1RSRST,reset event generates channel 1 reset request" "0,1"
bitfld.long 0x10 0. "CH1RSSEV,Software event generates channel 1 reset request" "0,1"
line.long 0x14 "ST0EXEVFCFG0,HRTIMER Slave_TIMER0 external event filter configuration register 0"
hexmask.long.byte 0x14 25.--29. 1. "EXEV4FM,External event 4 filter mode"
bitfld.long 0x14 24. "EXEV4MEEN,External event 4 memorized enable" "0,1"
hexmask.long.byte 0x14 19.--23. 1. "EXEV3FM,External event 3 filter mode"
bitfld.long 0x14 18. "EXEV3MEEN,External event 3 memorized enable" "0,1"
hexmask.long.byte 0x14 13.--17. 1. "EXEV2FM,External event 2 filter mode"
bitfld.long 0x14 12. "EXEV2MEEN,External event 2 memorized enable" "0,1"
newline
hexmask.long.byte 0x14 7.--11. 1. "EXEV1FM,External event 1 filter mode"
bitfld.long 0x14 6. "EXEV1MEEN,External event 1 memorized enable" "0,1"
hexmask.long.byte 0x14 1.--5. 1. "EXEV0FM,External event 0 filter mode"
bitfld.long 0x14 0. "EXEV0MEEN,External event 0 memory" "0,1"
line.long 0x18 "ST0EXEVFCFG1,HRTIMER Slave_TIMER0 external event filter configuration register 1"
hexmask.long.byte 0x18 25.--29. 1. "EXEV9FM,External event 9 filter mode"
bitfld.long 0x18 24. "EXEV9MEEN,External event 9 memorized enable" "0,1"
hexmask.long.byte 0x18 19.--23. 1. "EXEV8FM,External event 8 filter mode"
bitfld.long 0x18 18. "EXEV8MEEN,External event 8 memorized enable" "0,1"
hexmask.long.byte 0x18 13.--17. 1. "EXEV7FM,External event 7 filter mode"
bitfld.long 0x18 12. "EXEV7MEEN,External event 7 memorized enable" "0,1"
newline
hexmask.long.byte 0x18 7.--11. 1. "EXEV6FM,External event 6 filter mode"
bitfld.long 0x18 6. "EXEV6MEEN,External event 6 memorized enable" "0,1"
hexmask.long.byte 0x18 1.--5. 1. "EXEV5FM,External event 5 filter mode"
bitfld.long 0x18 0. "EXEV5MEEN,External event 0 memorized enable" "0,1"
line.long 0x1C "ST0CNTRST,HRTIMER Slave_TIMER0 counter reset register"
bitfld.long 0x1C 31. "ST5CMP1RST,Slave_TIMER5 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 30. "ST4CMP3RST,Slave_TIMER4 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 29. "ST4CMP1RST,Slave_TIMER4 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 28. "ST4CMP0RST,Slave_TIMER4 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 27. "ST3CMP3RST,Slave_TIMER3 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 26. "ST3CMP1RST,Slave_TIMER3 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x1C 25. "ST3CMP0RST,Slave_TIMER3 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 24. "ST2CMP3RST,Slave_TIMER2 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 23. "ST2CMP1RST,Slave_TIMER2 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 22. "ST2CMP0RST,Slave_TIMER2 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 21. "ST1CMP3RST,Slave_TIMER1 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 20. "ST1CMP1RST,Slave_TIMER1 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x1C 19. "ST1CMP0RST,Slave_TIMER1 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 18. "EXEV9RST,External event 9 resets counter" "0,1"
bitfld.long 0x1C 17. "EXEV8RST,External event 8 resets counter" "0,1"
bitfld.long 0x1C 16. "EXEV7RST,External event 7 resets counter" "0,1"
bitfld.long 0x1C 15. "EXEV6RST,External event 6 resets counter" "0,1"
bitfld.long 0x1C 14. "EXEV5RST,External event 5 resets counter" "0,1"
newline
bitfld.long 0x1C 13. "EXEV4RST,External event 4 resets counter" "0,1"
bitfld.long 0x1C 12. "EXEV3RST,External event 3 resets counter" "0,1"
bitfld.long 0x1C 11. "EXEV2RST,External event 2 resets counter" "0,1"
bitfld.long 0x1C 10. "EXEV1RST,External event 1 resets counter" "0,1"
bitfld.long 0x1C 9. "EXEV0RST,External event 0 resets counter" "0,1"
bitfld.long 0x1C 8. "MTCMP3RST,Master_TIMER compare 3 event resets counter" "0,1"
newline
bitfld.long 0x1C 7. "MTCMP2RST,Master_TIMER compare 2 event resets counter" "0,1"
bitfld.long 0x1C 6. "MTCMP1RST,Master_TIMER compare 1 event resets counter" "0,1"
bitfld.long 0x1C 5. "MTCMP0RST,Master_TIMER compare 0 event resets counter" "0,1"
bitfld.long 0x1C 4. "MTPERRST,Master_TIMER period event resets counter" "0,1"
bitfld.long 0x1C 3. "CMP3RST,Slave_TIMER0 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 2. "CMP1RST,Slave_TIMER0 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x1C 1. "UPRST,Slave_TIMER0 update event resets counter" "0,1"
bitfld.long 0x1C 0. "ST5CMP0RST,Slave_TIMER5 compare 0 event resets counter" "0,1"
line.long 0x20 "ST0CSCTL,HRTIMER Slave_TIMER0 carrier-signal control register"
hexmask.long.byte 0x20 7.--10. 1. "CSFSTPW,First carrier-signal pulse width"
bitfld.long 0x20 4.--6. "CSDTY,Carrier signal duty cycle" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x20 0.--3. 1. "CSPRD,Carrier signal period"
line.long 0x24 "ST0CAP0TRG,HRTIMER Slave_TIMER0 capture 0 trigger register"
bitfld.long 0x24 31. "CP0BST4CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x24 30. "CP0BST4CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x24 29. "CP0BST4NA,Capture 0 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 28. "CP0BST4A,Capture 0 triggered by ST4CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 27. "CP0BST3CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x24 26. "CP0BST3CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER3" "0,1"
newline
bitfld.long 0x24 25. "CP0BST3NA,Capture 0 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 24. "CP0BST3A,Capture 0 triggered by ST3CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 23. "CP0BST2CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x24 22. "CP0BST2CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x24 21. "CP0BST2NA,Capture 0 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 20. "CP0BST2A,Capture 0 triggered by ST2CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x24 19. "CP0BST1CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x24 18. "CP0BST1CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x24 17. "CP0BST1NA,Capture 0 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 16. "CP0BST1A,Capture 0 triggered by ST1CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
bitfld.long 0x24 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
newline
bitfld.long 0x24 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x24 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
bitfld.long 0x24 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x24 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x24 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x24 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x24 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x24 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x24 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x24 0. "CP0BSW,Capture 0 triggered by software" "0,1"
line.long 0x28 "ST0CAP1TRG,HRTIMER Slave_TIMER0 capture 1 trigger register"
bitfld.long 0x28 31. "CP1BST4CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x28 30. "CP1BST4CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x28 29. "CP1BST4NA,Capture 1 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 28. "CP1BST4A,Capture 1 triggered by ST4CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 27. "CP1BST3CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x28 26. "CP1BST3CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER3" "0,1"
newline
bitfld.long 0x28 25. "CP1BST3NA,Capture 1 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 24. "CP1BST3A,Capture 1 triggered by ST3CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 23. "CP1BST2CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x28 22. "CP1BST2CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x28 21. "CP1BST2NA,Capture 1 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 20. "CP1BST2A,Capture 1 triggered by ST2CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x28 19. "CP1BST1CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x28 18. "CP1BST1CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x28 17. "CP1BST1NA,Capture 1 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 16. "CP1BST1A,Capture 1 triggered by ST1CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
bitfld.long 0x28 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
newline
bitfld.long 0x28 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
bitfld.long 0x28 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
bitfld.long 0x28 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x28 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x28 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x28 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
newline
bitfld.long 0x28 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
bitfld.long 0x28 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x28 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x28 0. "CP1BSW,Capture 1 triggered by software" "0,1"
line.long 0x2C "ST0CHOCTL,HRTIMER Slave_TIMER0 channel output control register"
bitfld.long 0x2C 23. "BMCH1DTI,Channel 1 dead-time insert in bunch mode" "0,1"
bitfld.long 0x2C 22. "CH1CSEN,Channel 1 carrier-signal mode enable" "0,1"
bitfld.long 0x2C 20.--21. "CH1FLTOS,Channel 1 Fault output state" "0,1,2,3"
bitfld.long 0x2C 19. "ISO1,channel 1 output idle state" "0,1"
bitfld.long 0x2C 18. "BMCH1IEN,Channel 1 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x2C 17. "CH1P,Channel 1 output polarity" "0,1"
newline
bitfld.long 0x2C 14. "BALIAR,Balanced Idle Automatic Resumption" "0,1"
bitfld.long 0x2C 10.--12. "DLYISCH,Delayed IDLE source and channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x2C 9. "DLYISMEN,Delayed IDLE state mode enable" "0,1"
bitfld.long 0x2C 8. "DTEN,Dead time enable" "0,1"
bitfld.long 0x2C 7. "BMCH0DTI,Channel 0 dead-time insert in bunch mode" "0,1"
bitfld.long 0x2C 6. "CH0CSEN,Channel 0 carrier-signal mode enable" "0,1"
newline
bitfld.long 0x2C 4.--5. "CH0FLTOS,Channel 0 Fault output state" "0,1,2,3"
bitfld.long 0x2C 3. "ISO0,Channel 0 output idle state" "0,1"
bitfld.long 0x2C 2. "BMCH0IEN,Channel 0 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x2C 1. "CH0P,Channel 0 output polarity" "0,1"
line.long 0x30 "ST0FLTCTL,HRTIMER Slave_TIMER0 fault control register"
bitfld.long 0x30 31. "FLTENPROT,Protect fault enable" "0,1"
bitfld.long 0x30 7. "FLT7EN,Fault 7 enable" "0,1"
bitfld.long 0x30 6. "FLT6EN,Fault 6 enable" "0,1"
bitfld.long 0x30 5. "FLT5EN,Fault 5 enable" "0,1"
bitfld.long 0x30 4. "FLT4EN,Fault 4 enable" "0,1"
bitfld.long 0x30 3. "FLT3EN,Fault 3 enable" "0,1"
newline
bitfld.long 0x30 2. "FLT2EN,Fault 2 enable" "0,1"
bitfld.long 0x30 1. "FLT1EN,Fault 1 enable" "0,1"
bitfld.long 0x30 0. "FLT0EN,Fault 0 enable" "0,1"
line.long 0x34 "ST0CTL1,HRTIMER Slave_TIMER0 control register 1"
bitfld.long 0x34 20. "TRGHALFM,Triggered-half mode" "0,1"
bitfld.long 0x34 17. "IMUPD2V,Immediately update compare 2 value PWM mode" "0,1"
bitfld.long 0x34 16. "IMUPD0V,Immediately update compare 0 value PWM mode" "0,1"
bitfld.long 0x34 14.--15. "FEROVM,Fault and event roll-over mode" "0,1,2,3"
bitfld.long 0x34 12.--13. "BMROVM,Bunch mode roll-over mode" "0,1,2,3"
bitfld.long 0x34 10.--11. "ADCROVM,ADC roll-over mode" "0,1,2,3"
newline
bitfld.long 0x34 8.--9. "OUTROVM,Output roll-over mode" "0,1,2,3"
bitfld.long 0x34 6.--7. "ROVM,Roll-over mode" "0,1,2,3"
bitfld.long 0x34 4. "CAM,Center-aligned counting mode" "0,1"
bitfld.long 0x34 2. "TRIG1M,This bit defines when TRIG1M is generated" "0,1"
bitfld.long 0x34 1. "TRIG0M,This bit defines when TRIG0M is generated" "0,1"
bitfld.long 0x34 0. "TRIGEN,Two trigger enable" "0,1"
line.long 0x38 "ST0EXEVFCFG2,HRTIMER Slave_TIMER0 external event filter configuration register 2"
hexmask.long.byte 0x38 26.--31. 1. "EXEVXCNT,External event X counter value"
hexmask.long.byte 0x38 8.--13. 1. "EXEVXCNTTHR,External event X counter threshold"
hexmask.long.byte 0x38 4.--7. 1. "EXEVXSEL,External event X selection This bit determines the source of external event X"
bitfld.long 0x38 2. "EXEVXRSTM,External event X reset mode" "0,1"
bitfld.long 0x38 1. "EXEVXCRST,External event X counter reset" "0,1"
bitfld.long 0x38 0. "EXEVXCEN,External event X counter enable" "0,1"
line.long 0x3C "ST0CAPTRGCOM,HRTIMER Slave_TIMER0 capture trigger combination register"
bitfld.long 0x3C 27. "CP1BST7CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 26. "CP1BST7CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 25. "CP1BST7NA,Capture 1 triggered by ST7CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 24. "CP1BST7A,Capture 1 triggered by ST7CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 23. "CP1BST6CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER6" "0,1"
bitfld.long 0x3C 22. "CP1BST6CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER6" "0,1"
newline
bitfld.long 0x3C 21. "CP1BST6NA,Capture 1 triggered by ST6CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 20. "CP1BST6A,Capture 1 triggered by ST6CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 19. "CP1BST5CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 18. "CP1BST5CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 17. "CP1BST5NA,Capture 1 triggered by ST5CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 16. "CP1BST5A,Capture 1 triggered by ST5CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x3C 11. "CP0BST7CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 10. "CP0BST7CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 9. "CP0BST7NA,Capture 0 triggered by ST7CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 8. "CP0BST7A,Capture 0 triggered by ST7CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 7. "CP0BST6CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER6" "0,1"
bitfld.long 0x3C 6. "CP0BST6CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER6" "0,1"
newline
bitfld.long 0x3C 5. "CP0BST6NA,Capture 0 triggered by ST6CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 4. "CP0BST6A,Capture 0 triggered by ST6CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 3. "CP0BST5CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 2. "CP0BST5CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 1. "CP0BST5NA,Capture 0 triggered by ST5CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 0. "CP0BST5A,Capture 0 triggered by ST5CH0_O output inactive to active transition" "0,1"
line.long 0x40 "ST0CNTRSTA,HRTIMER Slave_TIMER0 counter reset and channel 0/1 set/reset request add register"
bitfld.long 0x40 29. "CH1RSSTCNTRST,Slave_TIMER0 counter reset generates channel 1 reset request" "0,1"
bitfld.long 0x40 28. "CH0RSSTCNTRST,Slave_TIMER0 counter reset generates channel 0 reset request" "0,1"
bitfld.long 0x40 27. "CH1RSSTEV10,Slave_TIMER0 interconnection event 10 generates channel 1 reset request" "0,1"
bitfld.long 0x40 26. "CH1RSSTEV9,Slave_TIMER0 interconnection event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x40 25. "CH0RSSTEV10,Slave_TIMER0 interconnection event 10 generates channel 0 reset request" "0,1"
bitfld.long 0x40 24. "CH0RSSTEV9,Slave_TIMER0 interconnection event 9 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x40 21. "CH1SSTCNTRST,Slave_TIMER0 counter reset generates channel 1 reset request" "0,1"
bitfld.long 0x40 20. "CH0SSTCNTRST,Slave_TIMER0 counter reset generates channel 0 reset request" "0,1"
bitfld.long 0x40 19. "CH1SSTEV10,Slave_TIMER0 interconnection event 10 generates channel 1 reset request" "0,1"
bitfld.long 0x40 18. "CH1SSTEV9,Slave_TIMER0 interconnection event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x40 17. "CH0SSTEV10,Slave_TIMER0 interconnection event 10 generates channel 0 set request" "0,1"
bitfld.long 0x40 16. "CH0SSTEV9,Slave_TIMER0 interconnection event 9 generates channel 1 set request" "0,1"
newline
bitfld.long 0x40 6. "ST7CMP3RST,Slave_TIMER7 compare 3 event resets counter" "0,1"
bitfld.long 0x40 5. "ST7CMP1RST,Slave_TIMER7 compare 1 event resets counter" "0,1"
bitfld.long 0x40 4. "ST7CMP0RST,Slave_TIMER7 compare 0 event resets counter" "0,1"
bitfld.long 0x40 3. "ST6CMP3RST,Slave_TIMER6 compare 3 event resets counter" "0,1"
bitfld.long 0x40 2. "ST6CMP1RST,Slave_TIMER6 compare 1 event resets counter" "0,1"
bitfld.long 0x40 1. "ST6CMP0RST,Slave_TIMER6 compare 0 event resets counter" "0,1"
newline
bitfld.long 0x40 0. "ST5CMP3RST,Slave_TIMER5 compare 3 event resets counter" "0,1"
line.long 0x44 "ST0ACTL,HRTIMER Slave_TIMER0 additional control register"
hexmask.long.byte 0x44 25.--31. 1. "DTFCFG,Falling edge dead-time value configure"
hexmask.long.byte 0x44 9.--15. 1. "DTRCFG,Rising edge dead-time value configure"
bitfld.long 0x44 1. "UPBST7,Update by Slave_TIMER7 update event" "0,1"
bitfld.long 0x44 0. "UPBST6,Update by Slave_TIMER6 update event" "0,1"
tree.end
tree "HRTIMER_SLAVE_TIMER1"
base ad:0x40015900
group.long 0x0++0x3
line.long 0x0 "ST1CTL0,HRTIMER Slave_TIMER1 control register 0"
hexmask.long.byte 0x0 28.--31. 1. "UPSEL,Update event selection"
bitfld.long 0x0 27. "SHWEN,Shadow registers enable" "0,1"
bitfld.long 0x0 25.--26. "DACTRGS,Trigger source to DAC" "0,1,2,3"
bitfld.long 0x0 24. "UPBMT,Update by Master_TIMER update event" "0,1"
bitfld.long 0x0 23. "UPBST4,Update by Slave_TIMER4 update event" "0,1"
bitfld.long 0x0 22. "UPBST3,Update by Slave_TIMER3 update event" "0,1"
newline
bitfld.long 0x0 21. "UPBST2,Update by Slave_TIMER2 update event" "0,1"
bitfld.long 0x0 20. "UPBST1,Update by Slave_TIMER1 update event" "0,1"
bitfld.long 0x0 19. "UPBST0,Update by Slave_TIMER0 update event" "0,1"
bitfld.long 0x0 18. "UPRST,Update event generated by reset event" "0,1"
bitfld.long 0x0 17. "UPREP,Update event generated by repetition event" "0,1"
bitfld.long 0x0 16. "UPBST5,Update by Slave_TIMER5 update event" "0,1"
newline
bitfld.long 0x0 14.--15. "DELCMP3M,Compare 3 delayed mode" "0,1,2,3"
bitfld.long 0x0 12.--13. "DELCMP1M,Compare 1 delayed mode" "0,1,2,3"
bitfld.long 0x0 11. "SYNISTRT,Synchronous input start timer" "0,1"
bitfld.long 0x0 10. "SYNIRST,Synchronous input reset timer" "0,1"
bitfld.long 0x0 9. "RSYNUPD,Re-synchronized update" "0,1"
bitfld.long 0x0 7.--8. "ALTM,Alternate mode" "0,1,2,3"
newline
bitfld.long 0x0 6. "BLNMEN,Balanced mode enable" "0,1"
bitfld.long 0x0 5. "HALFM,Half mode" "0,1"
bitfld.long 0x0 4. "CNTRSTM,Counter reset mode" "0,1"
bitfld.long 0x0 3. "CTNM,Continuous mode" "0,1"
bitfld.long 0x0 0.--2. "CNTCKDIV,Counter clock division" "0,1,2,3,4,5,6,7"
rgroup.long 0x4++0x3
line.long 0x0 "ST1INTF,HRTIMER Slave_TIMER1 interrupt flag register"
bitfld.long 0x0 31. "DIR,Direction" "0,1"
bitfld.long 0x0 21. "CH1F,Channel 1 output flag" "0,1"
bitfld.long 0x0 20. "CH0F,Channel 0 output flag" "0,1"
bitfld.long 0x0 19. "CH1SF,Channel 1 output state flag" "0,1"
bitfld.long 0x0 18. "CH0SF,Channel 0 output state flag" "0,1"
bitfld.long 0x0 17. "BLNIF,Balanced IDLE flag" "0,1"
newline
bitfld.long 0x0 16. "CBLNF,Current balanced flag" "0,1"
bitfld.long 0x0 14. "DLYIIF,Delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x0 13. "RSTIF,Counter reset interrupt flag" "0,1"
bitfld.long 0x0 12. "CH1ONAIF,Channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x0 11. "CH1OAIF,Channel 1 output active interrupt flag" "0,1"
bitfld.long 0x0 10. "CH0ONAIF,Channel 0 output inactive interrupt flag" "0,1"
newline
bitfld.long 0x0 9. "CH0OAIF,Channel 0 output active interrupt flag" "0,1"
bitfld.long 0x0 8. "CAP1IF,Capture 1 interrupt flag" "0,1"
bitfld.long 0x0 7. "CAP0IF,Capture 0 interrupt flag" "0,1"
bitfld.long 0x0 6. "UPIF,Update interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIF,Repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IF,Compare 3 interrupt flag" "0,1"
newline
bitfld.long 0x0 2. "CMP2IF,Compare 2 interrupt flag" "0,1"
bitfld.long 0x0 1. "CMP1IF,Compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IF,Compare 0 interrupt flag" "0,1"
wgroup.long 0x8++0x3
line.long 0x0 "ST1INTC,HRTIMER Slave_TIMER1 interrupt flag clear register"
bitfld.long 0x0 14. "DLYIIFC,Clear delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x0 13. "RSTIFC,Clear counter reset interrupt flag" "0,1"
bitfld.long 0x0 12. "CH1ONAIFC,Clear channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x0 11. "CH1OAIFC,Clear channel 1 output active interrupt flag" "0,1"
bitfld.long 0x0 10. "CH0ONAIFC,Clear channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x0 9. "CH0OAIFC,Clear channel 0 output active interrupt flag" "0,1"
newline
bitfld.long 0x0 8. "CAP1IFC,Clear capture 1 interrupt flag" "0,1"
bitfld.long 0x0 7. "CAP0IFC,Clear capture 0 interrupt flag" "0,1"
bitfld.long 0x0 6. "UPIFC,Clear update interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIFC,Clear repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IFC,Clear compare 3 interrupt flag" "0,1"
bitfld.long 0x0 2. "CMP2IFC,Clear compare 2 interrupt flag" "0,1"
newline
bitfld.long 0x0 1. "CMP1IFC,Clear compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IFC,Clear compare 0 interrupt flag" "0,1"
group.long 0xC++0x23
line.long 0x0 "ST1DMAINTEN,HRTIMER Slave_TIMER1 DMA and interrupt enable register"
bitfld.long 0x0 30. "DLYIDEN,Delayed IDLE mode entry DMA request enable" "0,1"
bitfld.long 0x0 29. "RSTDEN,Counter reset DMA request enable" "0,1"
bitfld.long 0x0 28. "CH1ONADEN,Channel 1 output inactive DMA request enable" "0,1"
bitfld.long 0x0 27. "CH1OADEN,Channel 1 output active DMA request enable" "0,1"
bitfld.long 0x0 26. "CH0ONADEN,Channel 0 output inactive DMA request enable" "0,1"
bitfld.long 0x0 25. "CH0OADEN,Channel 0 output active DMA request enable" "0,1"
newline
bitfld.long 0x0 24. "CAP1DEN,Capture 1 DMA request enable" "0,1"
bitfld.long 0x0 23. "CAP0DEN,Capture 0 DMA request enable" "0,1"
bitfld.long 0x0 22. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x0 20. "REPDEN,Repetition DMA request enable" "0,1"
bitfld.long 0x0 19. "CMP3DEN,Compare 3 DMA request enable" "0,1"
bitfld.long 0x0 18. "CMP2DEN,Compare 2 DMA request enable" "0,1"
newline
bitfld.long 0x0 17. "CMP1DEN,Compare 1 DMA request enable" "0,1"
bitfld.long 0x0 16. "CMP0DEN,Compare 0 DMA request enable" "0,1"
bitfld.long 0x0 14. "DLYIIE,Delayed IDLE mode entry interrupt enable" "0,1"
bitfld.long 0x0 13. "RSTIE,Counter reset interrupt enable" "0,1"
bitfld.long 0x0 12. "CH1ONAIE,Channel 1 output inactive interrupt enable" "0,1"
bitfld.long 0x0 11. "CH1OAIE,Channel 1 output active interrupt enable" "0,1"
newline
bitfld.long 0x0 10. "CH0ONAIE,Channel 0 output inactive interrupt enable" "0,1"
bitfld.long 0x0 9. "CH0OAIE,Channel 0 output active interrupt enable" "0,1"
bitfld.long 0x0 8. "CAP1IE,Capture 1 interrupt enable" "0,1"
bitfld.long 0x0 7. "CAP0IE,Capture 0 interrupt enable" "0,1"
bitfld.long 0x0 6. "UPIE,Update interrupt enable" "0,1"
bitfld.long 0x0 4. "REPIE,Repetition interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "CMP3IE,Compare 3 interrupt enable" "0,1"
bitfld.long 0x0 2. "CMP2IE,Compare 2 interrupt enable" "0,1"
bitfld.long 0x0 1. "CMP1IE,Compare 1 interrupt enable" "0,1"
bitfld.long 0x0 0. "CMP0IE,Compare 0 interrupt enable" "0,1"
line.long 0x4 "ST1CNT,HRTIMER Slave_TIMER1 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,The current counter value"
line.long 0x8 "ST1CAR,HRTIMER Slave_TIMER1 counter auto reload register"
hexmask.long.word 0x8 0.--15. 1. "CARL,Counter auto reload value"
line.long 0xC "ST1CREP,HRTIMER Slave_TIMER1 counter repetition register"
hexmask.long.byte 0xC 0.--7. 1. "CREP,Counter repetition value"
line.long 0x10 "ST1CMP0V,HRTIMER Slave_TIMER1 compare 0 value register"
hexmask.long.word 0x10 0.--15. 1. "CMP0VAL,Compare 0 value"
line.long 0x14 "ST1CMP0CP,HRTIMER Slave_TIMER1 compare 0 composite register"
hexmask.long.byte 0x14 16.--23. 1. "CREP,Counter repetition value"
hexmask.long.word 0x14 0.--15. 1. "CMP0VAL,Compare 0 value"
line.long 0x18 "ST1CMP1V,HRTIMER Slave_TIMER1 compare 1 value register"
hexmask.long.word 0x18 0.--15. 1. "CMP1VAL,Compare 1 value"
line.long 0x1C "ST1CMP2V,HRTIMER Slave_TIMER1 compare 2 value register"
hexmask.long.word 0x1C 0.--15. 1. "CMP2VAL,Compare 2 value"
line.long 0x20 "ST1CMP3V,HRTIMER Slave_TIMER1 compare 3 value register"
hexmask.long.word 0x20 0.--15. 1. "CMP3VAL,Compare 3 value"
rgroup.long 0x30++0x7
line.long 0x0 "ST1CAP0V,HRTIMER Slave_TIMER1 capture 0 value register"
bitfld.long 0x0 16. "DIR,Slave_timer 0 capture 1 direction status" "0,1"
hexmask.long.word 0x0 0.--15. 1. "CAP0VAL,Capture 0 value"
line.long 0x4 "ST1CAP1V,HRTIMER Slave_TIMER1 capture 1 value register"
bitfld.long 0x4 16. "DIR,Slave_Timer 0 capture 1 direction status" "0,1"
hexmask.long.word 0x4 0.--15. 1. "CAP1VAL,Capture 1 value"
group.long 0x38++0x47
line.long 0x0 "ST1DTCTL,HRTIMER Slave_TIMER1 dead-time control register"
bitfld.long 0x0 31. "DTFSVPROT,Dead-time falling edge protection for value and sign" "0,1"
bitfld.long 0x0 30. "DTFSPROT,Dead-time falling edge protection for sign" "0,1"
bitfld.long 0x0 25. "DTFS,The sign of falling edge dead-time value" "0,1"
hexmask.long.word 0x0 16.--24. 1. "DTFCFG,Falling edge dead-time value"
bitfld.long 0x0 15. "DTRSVPROT,Dead-time rising edge protection for value and sign" "0,1"
bitfld.long 0x0 14. "DTRSPROT,Dead-time rising edge protection for sign" "0,1"
newline
hexmask.long.byte 0x0 10.--13. 1. "DTGCKDIV,Dead time clock division"
bitfld.long 0x0 9. "DTRS,The sign of rising edge dead-time value" "0,1"
hexmask.long.word 0x0 0.--8. 1. "DTRCFG,Rising edge dead-time value"
line.long 0x4 "ST1CH0SET,HRTIMER Slave_TIMER1 channel 0 set request register"
bitfld.long 0x4 31. "CH0SUP,Update event generates channel 0 set request" "0,1"
bitfld.long 0x4 30. "CH0SEXEV9,External event 9 generates channel 0 set request" "0,1"
bitfld.long 0x4 29. "CH0SEXEV8,External event 8 generates channel 0 set request" "0,1"
bitfld.long 0x4 28. "CH0SEXEV7,External event 7 generates channel 0 set request" "0,1"
bitfld.long 0x4 27. "CH0SEXEV6,External event 6 generates channel 0 set request" "0,1"
bitfld.long 0x4 26. "CH0SEXEV5,External event 5 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 25. "CH0SEXEV4,External event 4 generates channel 0 set request" "0,1"
bitfld.long 0x4 24. "CH0SEXEV3,External event 3 generates channel 0 set request" "0,1"
bitfld.long 0x4 23. "CH0SEXEV2,External event 2 generates channel 0 set request" "0,1"
bitfld.long 0x4 22. "CH0SEXEV1,External event 1 generates channel 0 set request" "0,1"
bitfld.long 0x4 21. "CH0SEXEV0,External event 0 generates channel 0 set request" "0,1"
bitfld.long 0x4 20. "CH0SSTEV8,interconnection event 8 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 19. "CH0SSTEV7,interconnection event 7 generates channel 0 set request" "0,1"
bitfld.long 0x4 18. "CH0SSTEV6,interconnection event 6 generates channel 0 set request" "0,1"
bitfld.long 0x4 17. "CH0SSTEV5,interconnection event 5 generates channel 0 set request" "0,1"
bitfld.long 0x4 16. "CH0SSTEV4,interconnection event 4 generates channel 0 set request" "0,1"
bitfld.long 0x4 15. "CH0SSTEV3,interconnection event 3 generates channel 0 set request" "0,1"
bitfld.long 0x4 14. "CH0SSTEV2,interconnection event 2 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 13. "CH0SSTEV1,interconnection event 1 generates channel 0 set request" "0,1"
bitfld.long 0x4 12. "CH0SSTEV0,interconnection event 0 generates channel 0 set request" "0,1"
bitfld.long 0x4 11. "CH0SMTCMP3,Master_TIMER compare 3 event generates channel 0 set request" "0,1"
bitfld.long 0x4 10. "CH0SMTCMP2,Master_TIMER compare 2 event generates channel 0 set request" "0,1"
bitfld.long 0x4 9. "CH0SMTCMP1,Master_TIMER compare 1 event generates channel 0 set request" "0,1"
bitfld.long 0x4 8. "CH0SMTCMP0,Master_TIMER compare 0 event generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 7. "CH0SMTPER,Master_TIMER period event generates channel 0 set request" "0,1"
bitfld.long 0x4 6. "CH0SCMP3,compare 3 event generates channel 0 set request" "0,1"
bitfld.long 0x4 5. "CH0SCMP2,compare 2 event generates channel 0 set request" "0,1"
bitfld.long 0x4 4. "CH0SCMP1,compare 1 event generates channel 0 set request" "0,1"
bitfld.long 0x4 3. "CH0SCMP0,compare 0 event generates channel 0 set request" "0,1"
bitfld.long 0x4 2. "CH0SPER,period event generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 1. "CH0SRST,reset event generates channel 0 set request" "0,1"
bitfld.long 0x4 0. "CH0SSEV,Software event generates channel 0 set request" "0,1"
line.long 0x8 "ST1CH0RST,HRTIMER Slave_TIMER1 channel 0 reset request register"
bitfld.long 0x8 31. "CH0RSUP,Update event generates channel 0 reset request" "0,1"
bitfld.long 0x8 30. "CH0RSEXEV9,External event 9 generates channel 0 reset request" "0,1"
bitfld.long 0x8 29. "CH0RSEXEV8,External event 8 generates channel 0 reset request" "0,1"
bitfld.long 0x8 28. "CH0RSEXEV7,External event 7 generates channel 0 reset request" "0,1"
bitfld.long 0x8 27. "CH0RSEXEV6,External event 6 generates channel 0 reset request" "0,1"
bitfld.long 0x8 26. "CH0RSEXEV5,External event 5 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 25. "CH0RSEXEV4,External event 4 generates channel 0 reset request" "0,1"
bitfld.long 0x8 24. "CH0RSEXEV3,External event 3 generates channel 0 reset request" "0,1"
bitfld.long 0x8 23. "CH0RSEXEV2,External event 2 generates channel 0 reset request" "0,1"
bitfld.long 0x8 22. "CH0RSEXEV1,External event 1 generates channel 0 reset request" "0,1"
bitfld.long 0x8 21. "CH0RSEXEV0,External event 0 generates channel 0 reset request" "0,1"
bitfld.long 0x8 20. "CH0RSSTEV8,interconnection event 8 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 19. "CH0RSSTEV7,interconnection event 7 generates channel 0 reset request" "0,1"
bitfld.long 0x8 18. "CH0RSSTEV6,interconnection event 6 generates channel 0 reset request" "0,1"
bitfld.long 0x8 17. "CH0RSSTEV5,interconnection event 5 generates channel 0 reset request" "0,1"
bitfld.long 0x8 16. "CH0RSSTEV4,interconnection event 4 generates channel 0 reset request" "0,1"
bitfld.long 0x8 15. "CH0RSSTEV3,interconnection event 3 generates channel 0 reset request" "0,1"
bitfld.long 0x8 14. "CH0RSSTEV2,interconnection event 2 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 13. "CH0RSSTEV1,interconnection event 1 generates channel 0 reset request" "0,1"
bitfld.long 0x8 12. "CH0RSSTEV0,interconnection event 0 generates channel 0 reset request" "0,1"
bitfld.long 0x8 11. "CH0RSMTCMP3,Master_TIMER compare 3 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 10. "CH0RSMTCMP2,Master_TIMER compare 2 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 9. "CH0RSMTCMP1,Master_TIMER compare 1 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 8. "CH0RSMTCMP0,Master_TIMER compare 0 event generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 7. "CH0RSMTPER,Master_TIMER period event generates channel 0 reset request" "0,1"
bitfld.long 0x8 6. "CH0RSCMP3,compare 3 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 5. "CH0RSCMP2,compare 2 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 4. "CH0RSCMP1,compare 1 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 3. "CH0RSCMP0,compare 0 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 2. "CH0RSPER,period event generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 1. "CH0RSRST,reset event generates channel 0 reset request" "0,1"
bitfld.long 0x8 0. "CH0RSSEV,Software event generates channel 0 reset request" "0,1"
line.long 0xC "ST1CH1SET,HRTIMER Slave_TIMER1 channel 1 set request register"
bitfld.long 0xC 31. "CH1SUP,Update event generates channel 1 set request" "0,1"
bitfld.long 0xC 30. "CH1SEXEV9,External event 9 generates channel 1 set request" "0,1"
bitfld.long 0xC 29. "CH1SEXEV8,External event 8 generates channel 1 set request" "0,1"
bitfld.long 0xC 28. "CH1SEXEV7,External event 7 generates channel 1 set request" "0,1"
bitfld.long 0xC 27. "CH1SEXEV6,External event 6 generates channel 1 set request" "0,1"
bitfld.long 0xC 26. "CH1SEXEV5,External event 5 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 25. "CH1SEXEV4,External event 4 generates channel 1 set request" "0,1"
bitfld.long 0xC 24. "CH1SEXEV3,External event 3 generates channel 1 set request" "0,1"
bitfld.long 0xC 23. "CH1SEXEV2,External event 2 generates channel 1 set request" "0,1"
bitfld.long 0xC 22. "CH1SEXEV1,External event 1 generates channel 1 set request" "0,1"
bitfld.long 0xC 21. "CH1SEXEV0,External event 0 generates channel 1 set request" "0,1"
bitfld.long 0xC 20. "CH1SSTEV8,interconnection event 8 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 19. "CH1SSTEV7,interconnection event 7 generates channel 1 set request" "0,1"
bitfld.long 0xC 18. "CH1SSTEV6,interconnection event 6 generates channel 1 set request" "0,1"
bitfld.long 0xC 17. "CH1SSTEV5,interconnection event 5 generates channel 1 set request" "0,1"
bitfld.long 0xC 16. "CH1SSTEV4,interconnection event 4 generates channel 1 set request" "0,1"
bitfld.long 0xC 15. "CH1SSTEV3,interconnection event 3 generates channel 1 set request" "0,1"
bitfld.long 0xC 14. "CH1SSTEV2,interconnection event 2 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 13. "CH1SSTEV1,interconnection event 1 generates channel 1 set request" "0,1"
bitfld.long 0xC 12. "CH1SSTEV0,interconnection event 0 generates channel 1 set request" "0,1"
bitfld.long 0xC 11. "CH1SMTCMP3,Master_TIMER compare 3 event generates channel 1 set request" "0,1"
bitfld.long 0xC 10. "CH1SMTCMP2,Master_TIMER compare 2 event generates channel 1 set request" "0,1"
bitfld.long 0xC 9. "CH1SMTCMP1,Master_TIMER compare 1 event generates channel 1 set request" "0,1"
bitfld.long 0xC 8. "CH1SMTCMP0,Master_TIMER compare 0 event generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 7. "CH1SMTPER,Master_TIMER period event generates channel 1 set request" "0,1"
bitfld.long 0xC 6. "CH1SCMP3,compare 3 event generates channel 1 set request" "0,1"
bitfld.long 0xC 5. "CH1SCMP2,compare 2 event generates channel 1 set request" "0,1"
bitfld.long 0xC 4. "CH1SCMP1,compare 1 event generates channel 1 set request" "0,1"
bitfld.long 0xC 3. "CH1SCMP0,compare 0 event generates channel 1 set request" "0,1"
bitfld.long 0xC 2. "CH1SPER,period event generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 1. "CH1SRST,reset event generates channel 1 set request" "0,1"
bitfld.long 0xC 0. "CH1SSEV,Software event generates channel 1 set request" "0,1"
line.long 0x10 "ST1CH1RST,HRTIMER Slave_TIMER1 channel 1 reset request register"
bitfld.long 0x10 31. "CH1RSUP,Update event generates channel 1 reset request" "0,1"
bitfld.long 0x10 30. "CH1RSEXEV9,External event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x10 29. "CH1RSEXEV8,External event 8 generates channel 1 reset request" "0,1"
bitfld.long 0x10 28. "CH1RSEXEV7,External event 7 generates channel 1 reset request" "0,1"
bitfld.long 0x10 27. "CH1RSEXEV6,External event 6 generates channel 1 reset request" "0,1"
bitfld.long 0x10 26. "CH1RSEXEV5,External event 5 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 25. "CH1RSEXEV4,External event 4 generates channel 1 reset request" "0,1"
bitfld.long 0x10 24. "CH1RSEXEV3,External event 3 generates channel 1 reset request" "0,1"
bitfld.long 0x10 23. "CH1RSEXEV2,External event 2 generates channel 1 reset request" "0,1"
bitfld.long 0x10 22. "CH1RSEXEV1,External event 1 generates channel 1 reset request" "0,1"
bitfld.long 0x10 21. "CH1RSEXEV0,External event 0 generates channel 1 reset request" "0,1"
bitfld.long 0x10 20. "CH1RSSTEV8,interconnection event 8 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 19. "CH1RSSTEV7,interconnection event 7 generates channel 1 reset request" "0,1"
bitfld.long 0x10 18. "CH1RSSTEV6,interconnection event 6 generates channel 1 reset request" "0,1"
bitfld.long 0x10 17. "CH1RSSTEV5,interconnection event 5 generates channel 1 reset request" "0,1"
bitfld.long 0x10 16. "CH1RSSTEV4,interconnection event 4 generates channel 1 reset request" "0,1"
bitfld.long 0x10 15. "CH1RSSTEV3,interconnection event 3 generates channel 1 reset request" "0,1"
bitfld.long 0x10 14. "CH1RSSTEV2,interconnection event 2 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 13. "CH1RSSTEV1,interconnection event 1 generates channel 1 reset request" "0,1"
bitfld.long 0x10 12. "CH1RSSTEV0,interconnection event 0 generates channel 1 reset request" "0,1"
bitfld.long 0x10 11. "CH1RSMTCMP3,Master_TIMER compare 3 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 10. "CH1RSMTCMP2,Master_TIMER compare 2 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 9. "CH1RSMTCMP1,Master_TIMER compare 1 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 8. "CH1RSMTCMP0,Master_TIMER compare 0 event generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 7. "CH1RSMTPER,Master_TIMER period event generates channel 1 reset request" "0,1"
bitfld.long 0x10 6. "CH1RSCMP3,compare 3 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 5. "CH1RSCMP2,compare 2 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 4. "CH1RSCMP1,compare 1 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 3. "CH1RSCMP0,compare 0 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 2. "CH1RSPER,period event generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 1. "CH1RSRST,reset event generates channel 1 reset request" "0,1"
bitfld.long 0x10 0. "CH1RSSEV,Software event generates channel 1 reset request" "0,1"
line.long 0x14 "ST1EXEVFCFG0,HRTIMER Slave_TIMER1 external event filter configuration register 0"
hexmask.long.byte 0x14 25.--29. 1. "EXEV4FM,External event 4 filter mode"
bitfld.long 0x14 24. "EXEV4MEEN,External event 4 memorized enable" "0,1"
hexmask.long.byte 0x14 19.--23. 1. "EXEV3FM,External event 3 filter mode"
bitfld.long 0x14 18. "EXEV3MEEN,External event 3 memorized enable" "0,1"
hexmask.long.byte 0x14 13.--17. 1. "EXEV2FM,External event 2 filter mode"
bitfld.long 0x14 12. "EXEV2MEEN,External event 2 memorized enable" "0,1"
newline
hexmask.long.byte 0x14 7.--11. 1. "EXEV1FM,External event 1 filter mode"
bitfld.long 0x14 6. "EXEV1MEEN,External event 1 memorized enable" "0,1"
hexmask.long.byte 0x14 1.--5. 1. "EXEV0FM,External event 0 filter mode"
bitfld.long 0x14 0. "EXEV0MEEN,External event 0 memory" "0,1"
line.long 0x18 "ST1EXEVFCFG1,HRTIMER Slave_TIMER1 external event filter configuration register 1"
hexmask.long.byte 0x18 25.--29. 1. "EXEV9FM,External event 9 filter mode"
bitfld.long 0x18 24. "EXEV9MEEN,External event 9 memorized enable" "0,1"
hexmask.long.byte 0x18 19.--23. 1. "EXEV8FM,External event 8 filter mode"
bitfld.long 0x18 18. "EXEV8MEEN,External event 8 memorized enable" "0,1"
hexmask.long.byte 0x18 13.--17. 1. "EXEV7FM,External event 7 filter mode"
bitfld.long 0x18 12. "EXEV7MEEN,External event 7 memorized enable" "0,1"
newline
hexmask.long.byte 0x18 7.--11. 1. "EXEV6FM,External event 6 filter mode"
bitfld.long 0x18 6. "EXEV6MEEN,External event 6 memorized enable" "0,1"
hexmask.long.byte 0x18 1.--5. 1. "EXEV5FM,External event 5 filter mode"
bitfld.long 0x18 0. "EXEV5MEEN,External event 0 memorized enable" "0,1"
line.long 0x1C "ST1CNTRST,HRTIMER Slave_TIMER1 counter reset register"
bitfld.long 0x1C 31. "ST5CMP1RST,Slave_TIMER5 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 30. "ST4CMP3RST,Slave_TIMER4 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 29. "ST4CMP1RST,Slave_TIMER4 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 28. "ST4CMP0RST,Slave_TIMER4 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 27. "ST3CMP3RST,Slave_TIMER3 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 26. "ST3CMP1RST,Slave_TIMER3 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x1C 25. "ST3CMP0RST,Slave_TIMER3 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 24. "ST2CMP3RST,Slave_TIMER2 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 23. "ST2CMP1RST,Slave_TIMER2 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 22. "ST2CMP0RST,Slave_TIMER2 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 21. "ST0CMP3RST,Slave_TIMER0 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 20. "ST0CMP1RST,Slave_TIMER0 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x1C 19. "ST0CMP0RST,Slave_TIMER0 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 18. "EXEV9RST,External event 9 resets counter" "0,1"
bitfld.long 0x1C 17. "EXEV8RST,External event 8 resets counter" "0,1"
bitfld.long 0x1C 16. "EXEV7RST,External event 7 resets counter" "0,1"
bitfld.long 0x1C 15. "EXEV6RST,External event 6 resets counter" "0,1"
bitfld.long 0x1C 14. "EXEV5RST,External event 5 resets counter" "0,1"
newline
bitfld.long 0x1C 13. "EXEV4RST,External event 4 resets counter" "0,1"
bitfld.long 0x1C 12. "EXEV3RST,External event 3 resets counter" "0,1"
bitfld.long 0x1C 11. "EXEV2RST,External event 2 resets counter" "0,1"
bitfld.long 0x1C 10. "EXEV1RST,External event 1 resets counter" "0,1"
bitfld.long 0x1C 9. "EXEV0RST,External event 0 resets counter" "0,1"
bitfld.long 0x1C 8. "MTCMP3RST,Master_TIMER compare 3 event resets counter" "0,1"
newline
bitfld.long 0x1C 7. "MTCMP2RST,Master_TIMER compare 2 event resets counter" "0,1"
bitfld.long 0x1C 6. "MTCMP1RST,Master_TIMER compare 1 event resets counter" "0,1"
bitfld.long 0x1C 5. "MTCMP0RST,Master_TIMER compare 0 event resets counter" "0,1"
bitfld.long 0x1C 4. "MTPERRST,Master_TIMER period event resets counter" "0,1"
bitfld.long 0x1C 3. "CMP3RST,Slave_TIMER1 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 2. "CMP1RST,Slave_TIMER1 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x1C 1. "UPRST,Slave_TIMER1 update event resets counter" "0,1"
bitfld.long 0x1C 0. "ST5CMP0RST,Slave_TIMER5 compare 0 event resets counter" "0,1"
line.long 0x20 "ST1CSCTL,HRTIMER Slave_TIMER1 carrier-signal control register"
hexmask.long.byte 0x20 7.--10. 1. "CSFSTPW,First carrier-signal pulse width"
bitfld.long 0x20 4.--6. "CSDTY,Carrier signal duty cycle" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x20 0.--3. 1. "CSPRD,Carrier signal period"
line.long 0x24 "ST1CAP0TRG,HRTIMER Slave_TIMER1 capture 0 trigger register"
bitfld.long 0x24 31. "CP0BST4CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x24 30. "CP0BST4CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x24 29. "CP0BST4NA,Capture 0 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 28. "CP0BST4A,Capture 0 triggered by ST4CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 27. "CP0BST3CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x24 26. "CP0BST3CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER3" "0,1"
newline
bitfld.long 0x24 25. "CP0BST3NA,Capture 0 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 24. "CP0BST3A,Capture 0 triggered by ST3CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 23. "CP0BST2CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x24 22. "CP0BST2CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x24 21. "CP0BST2NA,Capture 0 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 20. "CP0BST2A,Capture 0 triggered by ST2CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x24 15. "CP0BST0CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x24 14. "CP0BST0CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x24 13. "CP0BST0NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 12. "CP0BST0A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
bitfld.long 0x24 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
newline
bitfld.long 0x24 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x24 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
bitfld.long 0x24 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x24 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x24 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x24 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x24 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x24 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x24 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x24 0. "CP0BSW,Capture 0 triggered by software" "0,1"
line.long 0x28 "ST1CAP1TRG,HRTIMER Slave_TIMER1 capture 1 trigger register"
bitfld.long 0x28 31. "CP1BST4CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x28 30. "CP1BST4CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x28 29. "CP1BST4NA,Capture 1 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 28. "CP1BST4A,Capture 1 triggered by ST4CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 27. "CP1BST3CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x28 26. "CP1BST3CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER3" "0,1"
newline
bitfld.long 0x28 25. "CP1BST3NA,Capture 1 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 24. "CP1BST3A,Capture 1 triggered by ST3CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 23. "CP1BST2CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x28 22. "CP1BST2CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x28 21. "CP1BST2NA,Capture 1 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 15. "CP1BST0CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER0" "0,1"
newline
bitfld.long 0x28 14. "CP1BST0CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x28 13. "CP1BST0NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 12. "CP1BST0A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
bitfld.long 0x28 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
bitfld.long 0x28 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
newline
bitfld.long 0x28 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
bitfld.long 0x28 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x28 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x28 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x28 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
bitfld.long 0x28 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
newline
bitfld.long 0x28 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x28 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x28 0. "CP1BSW,Capture 1 triggered by software" "0,1"
line.long 0x2C "ST1CHOCTL,HRTIMER Slave_TIMER1 channel output control register"
bitfld.long 0x2C 23. "BMCH1DTI,Channel 1 dead-time insert in bunch mode" "0,1"
bitfld.long 0x2C 22. "CH1CSEN,Channel 1 carrier-signal mode enable" "0,1"
bitfld.long 0x2C 20.--21. "CH1FLTOS,Channel 1 Fault output state" "0,1,2,3"
bitfld.long 0x2C 19. "ISO1,channel 1 output idle state" "0,1"
bitfld.long 0x2C 18. "BMCH1IEN,Channel 1 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x2C 17. "CH1P,Channel 1 output polarity" "0,1"
newline
bitfld.long 0x2C 14. "BALIAR,Balanced Idle Automatic Resumption" "0,1"
bitfld.long 0x2C 10.--12. "DLYISCH,Delayed IDLE source and channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x2C 9. "DLYISMEN,Delayed IDLE state mode enable" "0,1"
bitfld.long 0x2C 8. "DTEN,Dead time enable" "0,1"
bitfld.long 0x2C 7. "BMCH0DTI,Channel 0 dead-time insert in bunch mode" "0,1"
bitfld.long 0x2C 6. "CH0CSEN,Channel 0 carrier-signal mode enable" "0,1"
newline
bitfld.long 0x2C 4.--5. "CH0FLTOS,Channel 0 Fault output state" "0,1,2,3"
bitfld.long 0x2C 3. "ISO0,Channel 0 output idle state" "0,1"
bitfld.long 0x2C 2. "BMCH0IEN,Channel 0 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x2C 1. "CH0P,Channel 0 output polarity" "0,1"
line.long 0x30 "ST1FLTCTL,HRTIMER Slave_TIMER1 fault control register"
bitfld.long 0x30 31. "FLTENPROT,Protect fault enable" "0,1"
bitfld.long 0x30 7. "FLT7EN,Fault 7 enable" "0,1"
bitfld.long 0x30 6. "FLT6EN,Fault 6 enable" "0,1"
bitfld.long 0x30 5. "FLT5EN,Fault 5 enable" "0,1"
bitfld.long 0x30 4. "FLT4EN,Fault 4 enable" "0,1"
bitfld.long 0x30 3. "FLT3EN,Fault 3 enable" "0,1"
newline
bitfld.long 0x30 2. "FLT2EN,Fault 2 enable" "0,1"
bitfld.long 0x30 1. "FLT1EN,Fault 1 enable" "0,1"
bitfld.long 0x30 0. "FLT0EN,Fault 0 enable" "0,1"
line.long 0x34 "ST1CTL1,HRTIMER Slave_TIMER1 control register 1"
bitfld.long 0x34 20. "TRGHALFM,Triggered-half mode" "0,1"
bitfld.long 0x34 17. "IMUPD2V,Immediately update compare 2 value PWM mode" "0,1"
bitfld.long 0x34 16. "IMUPD0V,Immediately update compare 0 value PWM mode" "0,1"
bitfld.long 0x34 14.--15. "FEROVM,Fault and event roll-over mode" "0,1,2,3"
bitfld.long 0x34 12.--13. "BMROVM,Bunch mode roll-over mode" "0,1,2,3"
bitfld.long 0x34 10.--11. "ADCROVM,ADC roll-over mode" "0,1,2,3"
newline
bitfld.long 0x34 8.--9. "OUTROVM,Output roll-over mode" "0,1,2,3"
bitfld.long 0x34 6.--7. "ROVM,Roll-over mode" "0,1,2,3"
bitfld.long 0x34 4. "CAM,Center-aligned counting mode" "0,1"
bitfld.long 0x34 2. "TRIG1M,This bit defines when TRIG1M is generated" "0,1"
bitfld.long 0x34 1. "TRIG0M,This bit defines when TRIG0M is generated" "0,1"
bitfld.long 0x34 0. "TRIGEN,Two trigger enable" "0,1"
line.long 0x38 "ST1EXEVFCFG2,HRTIMER Slave_TIMER1 external event filter configuration register 2"
hexmask.long.byte 0x38 26.--31. 1. "EXEVXCNT,External event X counter value"
hexmask.long.byte 0x38 8.--13. 1. "EXEVXCNTTHR,External event X counter threshold"
hexmask.long.byte 0x38 4.--7. 1. "EXEVXSEL,External event X selection This bit determines the source of external event X"
bitfld.long 0x38 2. "EXEVXRSTM,External event X reset mode" "0,1"
bitfld.long 0x38 1. "EXEVXCRST,External event X counter reset" "0,1"
bitfld.long 0x38 0. "EXEVXCEN,External event X counter enable" "0,1"
line.long 0x3C "ST1CAPTRGCOM,HRTIMER Slave_TIMER1 capture trigger combination register"
bitfld.long 0x3C 27. "CP1BST7CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 26. "CP1BST7CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 25. "CP1BST7NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 24. "CP1BST7A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 23. "CP1BST6CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER6" "0,1"
bitfld.long 0x3C 22. "CP1BST6CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER6" "0,1"
newline
bitfld.long 0x3C 21. "CP1BST6NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 20. "CP1BST6A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 19. "CP1BST5CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 18. "CP1BST5CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 17. "CP1BST5NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 16. "CP1BST5A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x3C 11. "CP0BST7CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 10. "CP0BST7CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 9. "CP0BST7NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 8. "CP0BST7A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 7. "CP0BST6CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER6" "0,1"
bitfld.long 0x3C 6. "CP0BST6CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER6" "0,1"
newline
bitfld.long 0x3C 5. "CP0BST6NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 4. "CP0BST6A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 3. "CP0BST5CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 2. "CP0BST5CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 1. "CP0BST5NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 0. "CP0BST5A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
line.long 0x40 "ST1CNTRSTA,HRTIMER Slave_TIMER1 counter reset and channel 0/1 set/reset request add register"
bitfld.long 0x40 29. "CH1RSSTCNTRST,Slave_TIMER1 counter reset generates channel 1 reset request" "0,1"
bitfld.long 0x40 28. "CH0RSSTCNTRST,Slave_TIMER1 counter reset generates channel 0 reset request" "0,1"
bitfld.long 0x40 27. "CH1RSSTEV10,Slave_TIMER1 interconnection event 10 generates channel 1 reset request" "0,1"
bitfld.long 0x40 26. "CH1RSSTEV9,Slave_TIMER1 interconnection event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x40 25. "CH0RSSTEV10,Slave_TIMER1 interconnection event 10 generates channel 0 reset request" "0,1"
bitfld.long 0x40 24. "CH0RSSTEV9,Slave_TIMER1 interconnection event 9 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x40 21. "CH1SSTCNTRST,Slave_TIMER1 counter reset generates channel 1 reset request" "0,1"
bitfld.long 0x40 20. "CH0SSTCNTRST,Slave_TIMER1 counter reset generates channel 0 reset request" "0,1"
bitfld.long 0x40 19. "CH1SSTEV10,Slave_TIMER1 interconnection event 10 generates channel 1 reset request" "0,1"
bitfld.long 0x40 18. "CH1SSTEV9,Slave_TIMER1 interconnection event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x40 17. "CH0SSTEV10,Slave_TIMER1 interconnection event 10 generates channel 0 set request" "0,1"
bitfld.long 0x40 16. "CH0SSTEV9,Slave_TIMER1 interconnection event 9 generates channel 1 set request" "0,1"
newline
bitfld.long 0x40 6. "ST7CMP3RST,Slave_TIMER7 compare 3 event resets counter" "0,1"
bitfld.long 0x40 5. "ST7CMP1RST,Slave_TIMER7 compare 1 event resets counter" "0,1"
bitfld.long 0x40 4. "ST7CMP0RST,Slave_TIMER7 compare 0 event resets counter" "0,1"
bitfld.long 0x40 3. "ST6CMP3RST,Slave_TIMER6 compare 3 event resets counter" "0,1"
bitfld.long 0x40 2. "ST6CMP1RST,Slave_TIMER6 compare 1 event resets counter" "0,1"
bitfld.long 0x40 1. "ST6CMP0RST,Slave_TIMER6 compare 0 event resets counter" "0,1"
newline
bitfld.long 0x40 0. "ST5CMP3RST,Slave_TIMER5 compare 3 event resets counter" "0,1"
line.long 0x44 "ST1ACTL,HRTIMER Slave_TIMER1 additional control register"
hexmask.long.byte 0x44 25.--31. 1. "DTFCFG,Falling edge dead-time value configure"
hexmask.long.byte 0x44 9.--15. 1. "DTRCFG,Rising edge dead-time value configure"
bitfld.long 0x44 1. "UPBST7,Update by Slave_TIMER7 update event" "0,1"
bitfld.long 0x44 0. "UPBST6,Update by Slave_TIMER6 update event" "0,1"
tree.end
tree "HRTIMER_SLAVE_TIMER2"
base ad:0x40015980
group.long 0x0++0x3
line.long 0x0 "ST2CTL0,HRTIMER Slave_TIMER2 control register 0"
hexmask.long.byte 0x0 28.--31. 1. "UPSEL,Update event selection"
bitfld.long 0x0 27. "SHWEN,Shadow registers enable" "0,1"
bitfld.long 0x0 25.--26. "DACTRGS,Trigger source to DAC" "0,1,2,3"
bitfld.long 0x0 24. "UPBMT,Update by Master_TIMER update event" "0,1"
bitfld.long 0x0 23. "UPBST4,Update by Slave_TIMER4 update event" "0,1"
bitfld.long 0x0 22. "UPBST3,Update by Slave_TIMER3 update event" "0,1"
newline
bitfld.long 0x0 21. "UPBST2,Update by Slave_TIMER2 update event" "0,1"
bitfld.long 0x0 20. "UPBST1,Update by Slave_TIMER1 update event" "0,1"
bitfld.long 0x0 19. "UPBST0,Update by Slave_TIMER0 update event" "0,1"
bitfld.long 0x0 18. "UPRST,Update event generated by reset event" "0,1"
bitfld.long 0x0 17. "UPREP,Update event generated by repetition event" "0,1"
bitfld.long 0x0 16. "UPBST5,Update by Slave_TIMER5 update event" "0,1"
newline
bitfld.long 0x0 14.--15. "DELCMP3M,Compare 3 delayed mode" "0,1,2,3"
bitfld.long 0x0 12.--13. "DELCMP1M,Compare 1 delayed mode" "0,1,2,3"
bitfld.long 0x0 11. "SYNISTRT,Synchronous input start timer" "0,1"
bitfld.long 0x0 10. "SYNIRST,Synchronous input reset timer" "0,1"
bitfld.long 0x0 9. "RSYNUPD,Re-synchronized update" "0,1"
bitfld.long 0x0 7.--8. "ALTM,Alternate mode" "0,1,2,3"
newline
bitfld.long 0x0 6. "BLNMEN,Balanced mode enable" "0,1"
bitfld.long 0x0 5. "HALFM,Half mode" "0,1"
bitfld.long 0x0 4. "CNTRSTM,Counter reset mode" "0,1"
bitfld.long 0x0 3. "CTNM,Continuous mode" "0,1"
bitfld.long 0x0 0.--2. "CNTCKDIV,Counter clock division" "0,1,2,3,4,5,6,7"
rgroup.long 0x4++0x3
line.long 0x0 "ST2INTF,HRTIMER Slave_TIMER2 interrupt flag register"
bitfld.long 0x0 31. "DIR,Direction" "0,1"
bitfld.long 0x0 21. "CH1F,Channel 1 output flag" "0,1"
bitfld.long 0x0 20. "CH0F,Channel 0 output flag" "0,1"
bitfld.long 0x0 19. "CH1SF,Channel 1 output state flag" "0,1"
bitfld.long 0x0 18. "CH0SF,Channel 0 output state flag" "0,1"
bitfld.long 0x0 17. "BLNIF,Balanced IDLE flag" "0,1"
newline
bitfld.long 0x0 16. "CBLNF,Current balanced flag" "0,1"
bitfld.long 0x0 14. "DLYIIF,Delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x0 13. "RSTIF,Counter reset interrupt flag" "0,1"
bitfld.long 0x0 12. "CH1ONAIF,Channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x0 11. "CH1OAIF,Channel 1 output active interrupt flag" "0,1"
bitfld.long 0x0 10. "CH0ONAIF,Channel 0 output inactive interrupt flag" "0,1"
newline
bitfld.long 0x0 9. "CH0OAIF,Channel 0 output active interrupt flag" "0,1"
bitfld.long 0x0 8. "CAP1IF,Capture 1 interrupt flag" "0,1"
bitfld.long 0x0 7. "CAP0IF,Capture 0 interrupt flag" "0,1"
bitfld.long 0x0 6. "UPIF,Update interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIF,Repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IF,Compare 3 interrupt flag" "0,1"
newline
bitfld.long 0x0 2. "CMP2IF,Compare 2 interrupt flag" "0,1"
bitfld.long 0x0 1. "CMP1IF,Compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IF,Compare 0 interrupt flag" "0,1"
wgroup.long 0x8++0x3
line.long 0x0 "ST2INTC,HRTIMER Slave_TIMER2 interrupt flag clear register"
bitfld.long 0x0 14. "DLYIIFC,Clear delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x0 13. "RSTIFC,Clear counter reset interrupt flag" "0,1"
bitfld.long 0x0 12. "CH1ONAIFC,Clear channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x0 11. "CH1OAIFC,Clear channel 1 output active interrupt flag" "0,1"
bitfld.long 0x0 10. "CH0ONAIFC,Clear channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x0 9. "CH0OAIFC,Clear channel 0 output active interrupt flag" "0,1"
newline
bitfld.long 0x0 8. "CAP1IFC,Clear capture 1 interrupt flag" "0,1"
bitfld.long 0x0 7. "CAP0IFC,Clear capture 0 interrupt flag" "0,1"
bitfld.long 0x0 6. "UPIFC,Clear update interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIFC,Clear repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IFC,Clear compare 3 interrupt flag" "0,1"
bitfld.long 0x0 2. "CMP2IFC,Clear compare 2 interrupt flag" "0,1"
newline
bitfld.long 0x0 1. "CMP1IFC,Clear compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IFC,Clear compare 0 interrupt flag" "0,1"
group.long 0xC++0x23
line.long 0x0 "ST2DMAINTEN,HRTIMER Slave_TIMER2 DMA and interrupt enable register"
bitfld.long 0x0 30. "DLYIDEN,Delayed IDLE mode entry DMA request enable" "0,1"
bitfld.long 0x0 29. "RSTDEN,Counter reset DMA request enable" "0,1"
bitfld.long 0x0 28. "CH1ONADEN,Channel 1 output inactive DMA request enable" "0,1"
bitfld.long 0x0 27. "CH1OADEN,Channel 1 output active DMA request enable" "0,1"
bitfld.long 0x0 26. "CH0ONADEN,Channel 0 output inactive DMA request enable" "0,1"
bitfld.long 0x0 25. "CH0OADEN,Channel 0 output active DMA request enable" "0,1"
newline
bitfld.long 0x0 24. "CAP1DEN,Capture 1 DMA request enable" "0,1"
bitfld.long 0x0 23. "CAP0DEN,Capture 0 DMA request enable" "0,1"
bitfld.long 0x0 22. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x0 20. "REPDEN,Repetition DMA request enable" "0,1"
bitfld.long 0x0 19. "CMP3DEN,Compare 3 DMA request enable" "0,1"
bitfld.long 0x0 18. "CMP2DEN,Compare 2 DMA request enable" "0,1"
newline
bitfld.long 0x0 17. "CMP1DEN,Compare 1 DMA request enable" "0,1"
bitfld.long 0x0 16. "CMP0DEN,Compare 0 DMA request enable" "0,1"
bitfld.long 0x0 14. "DLYIIE,Delayed IDLE mode entry interrupt enable" "0,1"
bitfld.long 0x0 13. "RSTIE,Counter reset interrupt enable" "0,1"
bitfld.long 0x0 12. "CH1ONAIE,Channel 1 output inactive interrupt enable" "0,1"
bitfld.long 0x0 11. "CH1OAIE,Channel 1 output active interrupt enable" "0,1"
newline
bitfld.long 0x0 10. "CH0ONAIE,Channel 0 output inactive interrupt enable" "0,1"
bitfld.long 0x0 9. "CH0OAIE,Channel 0 output active interrupt enable" "0,1"
bitfld.long 0x0 8. "CAP1IE,Capture 1 interrupt enable" "0,1"
bitfld.long 0x0 7. "CAP0IE,Capture 0 interrupt enable" "0,1"
bitfld.long 0x0 6. "UPIE,Update interrupt enable" "0,1"
bitfld.long 0x0 4. "REPIE,Repetition interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "CMP3IE,Compare 3 interrupt enable" "0,1"
bitfld.long 0x0 2. "CMP2IE,Compare 2 interrupt enable" "0,1"
bitfld.long 0x0 1. "CMP1IE,Compare 1 interrupt enable" "0,1"
bitfld.long 0x0 0. "CMP0IE,Compare 0 interrupt enable" "0,1"
line.long 0x4 "ST2CNT,HRTIMER Slave_TIMER2 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,The current counter value"
line.long 0x8 "ST2CAR,HRTIMER Slave_TIMER2 counter auto reload register"
hexmask.long.word 0x8 0.--15. 1. "CARL,Counter auto reload value"
line.long 0xC "ST2CREP,HRTIMER Slave_TIMER2 counter repetition register"
hexmask.long.byte 0xC 0.--7. 1. "CREP,Counter repetition value"
line.long 0x10 "ST2CMP0V,HRTIMER Slave_TIMER2 compare 0 value register"
hexmask.long.word 0x10 0.--15. 1. "CMP0VAL,Compare 0 value"
line.long 0x14 "ST2CMP0CP,HRTIMER Slave_TIMER2 compare 0 composite register"
hexmask.long.byte 0x14 16.--23. 1. "CREP,Counter repetition value"
hexmask.long.word 0x14 0.--15. 1. "CMP0VAL,Compare 0 value"
line.long 0x18 "ST2CMP1V,HRTIMER Slave_TIMER2 compare 1 value register"
hexmask.long.word 0x18 0.--15. 1. "CMP1VAL,Compare 1 value"
line.long 0x1C "ST2CMP2V,HRTIMER Slave_TIMER2 compare 2 value register"
hexmask.long.word 0x1C 0.--15. 1. "CMP2VAL,Compare 2 value"
line.long 0x20 "ST2CMP3V,HRTIMER Slave_TIMER2 compare 3 value register"
hexmask.long.word 0x20 0.--15. 1. "CMP3VAL,Compare 3 value"
rgroup.long 0x30++0x7
line.long 0x0 "ST2CAP0V,HRTIMER Slave_TIMER2 capture 0 value register"
bitfld.long 0x0 16. "DIR,Slave_timer 0 capture 1 direction status" "0,1"
hexmask.long.word 0x0 0.--15. 1. "CAP0VAL,Capture 0 value"
line.long 0x4 "ST2CAP1V,HRTIMER Slave_TIMER2 capture 1 value register"
bitfld.long 0x4 16. "DIR,Slave_Timer 0 capture 1 direction status" "0,1"
hexmask.long.word 0x4 0.--15. 1. "CAP1VAL,Capture 1 value"
group.long 0x38++0x47
line.long 0x0 "ST2DTCTL,HRTIMER Slave_TIMER2 dead-time control register"
bitfld.long 0x0 31. "DTFSVPROT,Dead-time falling edge protection for value and sign" "0,1"
bitfld.long 0x0 30. "DTFSPROT,Dead-time falling edge protection for sign" "0,1"
bitfld.long 0x0 25. "DTFS,The sign of falling edge dead-time value" "0,1"
hexmask.long.word 0x0 16.--24. 1. "DTFCFG,Falling edge dead-time value"
bitfld.long 0x0 15. "DTRSVPROT,Dead-time rising edge protection for value and sign" "0,1"
bitfld.long 0x0 14. "DTRSPROT,Dead-time rising edge protection for sign" "0,1"
newline
hexmask.long.byte 0x0 10.--13. 1. "DTGCKDIV,Dead time clock division"
bitfld.long 0x0 9. "DTRS,The sign of rising edge dead-time value" "0,1"
hexmask.long.word 0x0 0.--8. 1. "DTRCFG,Rising edge dead-time value"
line.long 0x4 "ST2CH0SET,HRTIMER Slave_TIMER2 channel 0 set request register"
bitfld.long 0x4 31. "CH0SUP,Update event generates channel 0 set request" "0,1"
bitfld.long 0x4 30. "CH0SEXEV9,External event 9 generates channel 0 set request" "0,1"
bitfld.long 0x4 29. "CH0SEXEV8,External event 8 generates channel 0 set request" "0,1"
bitfld.long 0x4 28. "CH0SEXEV7,External event 7 generates channel 0 set request" "0,1"
bitfld.long 0x4 27. "CH0SEXEV6,External event 6 generates channel 0 set request" "0,1"
bitfld.long 0x4 26. "CH0SEXEV5,External event 5 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 25. "CH0SEXEV4,External event 4 generates channel 0 set request" "0,1"
bitfld.long 0x4 24. "CH0SEXEV3,External event 3 generates channel 0 set request" "0,1"
bitfld.long 0x4 23. "CH0SEXEV2,External event 2 generates channel 0 set request" "0,1"
bitfld.long 0x4 22. "CH0SEXEV1,External event 1 generates channel 0 set request" "0,1"
bitfld.long 0x4 21. "CH0SEXEV0,External event 0 generates channel 0 set request" "0,1"
bitfld.long 0x4 20. "CH0SSTEV8,interconnection event 8 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 19. "CH0SSTEV7,interconnection event 7 generates channel 0 set request" "0,1"
bitfld.long 0x4 18. "CH0SSTEV6,interconnection event 6 generates channel 0 set request" "0,1"
bitfld.long 0x4 17. "CH0SSTEV5,interconnection event 5 generates channel 0 set request" "0,1"
bitfld.long 0x4 16. "CH0SSTEV4,interconnection event 4 generates channel 0 set request" "0,1"
bitfld.long 0x4 15. "CH0SSTEV3,interconnection event 3 generates channel 0 set request" "0,1"
bitfld.long 0x4 14. "CH0SSTEV2,interconnection event 2 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 13. "CH0SSTEV1,interconnection event 1 generates channel 0 set request" "0,1"
bitfld.long 0x4 12. "CH0SSTEV0,interconnection event 0 generates channel 0 set request" "0,1"
bitfld.long 0x4 11. "CH0SMTCMP3,Master_TIMER compare 3 event generates channel 0 set request" "0,1"
bitfld.long 0x4 10. "CH0SMTCMP2,Master_TIMER compare 2 event generates channel 0 set request" "0,1"
bitfld.long 0x4 9. "CH0SMTCMP1,Master_TIMER compare 1 event generates channel 0 set request" "0,1"
bitfld.long 0x4 8. "CH0SMTCMP0,Master_TIMER compare 0 event generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 7. "CH0SMTPER,Master_TIMER period event generates channel 0 set request" "0,1"
bitfld.long 0x4 6. "CH0SCMP3,compare 3 event generates channel 0 set request" "0,1"
bitfld.long 0x4 5. "CH0SCMP2,compare 2 event generates channel 0 set request" "0,1"
bitfld.long 0x4 4. "CH0SCMP1,compare 1 event generates channel 0 set request" "0,1"
bitfld.long 0x4 3. "CH0SCMP0,compare 0 event generates channel 0 set request" "0,1"
bitfld.long 0x4 2. "CH0SPER,period event generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 1. "CH0SRST,reset event generates channel 0 set request" "0,1"
bitfld.long 0x4 0. "CH0SSEV,Software event generates channel 0 set request" "0,1"
line.long 0x8 "ST2CH0RST,HRTIMER Slave_TIMER2 channel 0 reset request register"
bitfld.long 0x8 31. "CH0RSUP,Update event generates channel 0 reset request" "0,1"
bitfld.long 0x8 30. "CH0RSEXEV9,External event 9 generates channel 0 reset request" "0,1"
bitfld.long 0x8 29. "CH0RSEXEV8,External event 8 generates channel 0 reset request" "0,1"
bitfld.long 0x8 28. "CH0RSEXEV7,External event 7 generates channel 0 reset request" "0,1"
bitfld.long 0x8 27. "CH0RSEXEV6,External event 6 generates channel 0 reset request" "0,1"
bitfld.long 0x8 26. "CH0RSEXEV5,External event 5 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 25. "CH0RSEXEV4,External event 4 generates channel 0 reset request" "0,1"
bitfld.long 0x8 24. "CH0RSEXEV3,External event 3 generates channel 0 reset request" "0,1"
bitfld.long 0x8 23. "CH0RSEXEV2,External event 2 generates channel 0 reset request" "0,1"
bitfld.long 0x8 22. "CH0RSEXEV1,External event 1 generates channel 0 reset request" "0,1"
bitfld.long 0x8 21. "CH0RSEXEV0,External event 0 generates channel 0 reset request" "0,1"
bitfld.long 0x8 20. "CH0RSSTEV8,interconnection event 8 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 19. "CH0RSSTEV7,interconnection event 7 generates channel 0 reset request" "0,1"
bitfld.long 0x8 18. "CH0RSSTEV6,interconnection event 6 generates channel 0 reset request" "0,1"
bitfld.long 0x8 17. "CH0RSSTEV5,interconnection event 5 generates channel 0 reset request" "0,1"
bitfld.long 0x8 16. "CH0RSSTEV4,interconnection event 4 generates channel 0 reset request" "0,1"
bitfld.long 0x8 15. "CH0RSSTEV3,interconnection event 3 generates channel 0 reset request" "0,1"
bitfld.long 0x8 14. "CH0RSSTEV2,interconnection event 2 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 13. "CH0RSSTEV1,interconnection event 1 generates channel 0 reset request" "0,1"
bitfld.long 0x8 12. "CH0RSSTEV0,interconnection event 0 generates channel 0 reset request" "0,1"
bitfld.long 0x8 11. "CH0RSMTCMP3,Master_TIMER compare 3 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 10. "CH0RSMTCMP2,Master_TIMER compare 2 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 9. "CH0RSMTCMP1,Master_TIMER compare 1 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 8. "CH0RSMTCMP0,Master_TIMER compare 0 event generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 7. "CH0RSMTPER,Master_TIMER period event generates channel 0 reset request" "0,1"
bitfld.long 0x8 6. "CH0RSCMP3,compare 3 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 5. "CH0RSCMP2,compare 2 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 4. "CH0RSCMP1,compare 1 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 3. "CH0RSCMP0,compare 0 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 2. "CH0RSPER,period event generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 1. "CH0RSRST,reset event generates channel 0 reset request" "0,1"
bitfld.long 0x8 0. "CH0RSSEV,Software event generates channel 0 reset request" "0,1"
line.long 0xC "ST2CH1SET,HRTIMER Slave_TIMER2 channel 1 set request register"
bitfld.long 0xC 31. "CH1SUP,Update event generates channel 1 set request" "0,1"
bitfld.long 0xC 30. "CH1SEXEV9,External event 9 generates channel 1 set request" "0,1"
bitfld.long 0xC 29. "CH1SEXEV8,External event 8 generates channel 1 set request" "0,1"
bitfld.long 0xC 28. "CH1SEXEV7,External event 7 generates channel 1 set request" "0,1"
bitfld.long 0xC 27. "CH1SEXEV6,External event 6 generates channel 1 set request" "0,1"
bitfld.long 0xC 26. "CH1SEXEV5,External event 5 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 25. "CH1SEXEV4,External event 4 generates channel 1 set request" "0,1"
bitfld.long 0xC 24. "CH1SEXEV3,External event 3 generates channel 1 set request" "0,1"
bitfld.long 0xC 23. "CH1SEXEV2,External event 2 generates channel 1 set request" "0,1"
bitfld.long 0xC 22. "CH1SEXEV1,External event 1 generates channel 1 set request" "0,1"
bitfld.long 0xC 21. "CH1SEXEV0,External event 0 generates channel 1 set request" "0,1"
bitfld.long 0xC 20. "CH1SSTEV8,interconnection event 8 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 19. "CH1SSTEV7,interconnection event 7 generates channel 1 set request" "0,1"
bitfld.long 0xC 18. "CH1SSTEV6,interconnection event 6 generates channel 1 set request" "0,1"
bitfld.long 0xC 17. "CH1SSTEV5,interconnection event 5 generates channel 1 set request" "0,1"
bitfld.long 0xC 16. "CH1SSTEV4,interconnection event 4 generates channel 1 set request" "0,1"
bitfld.long 0xC 15. "CH1SSTEV3,interconnection event 3 generates channel 1 set request" "0,1"
bitfld.long 0xC 14. "CH1SSTEV2,interconnection event 2 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 13. "CH1SSTEV1,interconnection event 1 generates channel 1 set request" "0,1"
bitfld.long 0xC 12. "CH1SSTEV0,interconnection event 0 generates channel 1 set request" "0,1"
bitfld.long 0xC 11. "CH1SMTCMP3,Master_TIMER compare 3 event generates channel 1 set request" "0,1"
bitfld.long 0xC 10. "CH1SMTCMP2,Master_TIMER compare 2 event generates channel 1 set request" "0,1"
bitfld.long 0xC 9. "CH1SMTCMP1,Master_TIMER compare 1 event generates channel 1 set request" "0,1"
bitfld.long 0xC 8. "CH1SMTCMP0,Master_TIMER compare 0 event generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 7. "CH1SMTPER,Master_TIMER period event generates channel 1 set request" "0,1"
bitfld.long 0xC 6. "CH1SCMP3,compare 3 event generates channel 1 set request" "0,1"
bitfld.long 0xC 5. "CH1SCMP2,compare 2 event generates channel 1 set request" "0,1"
bitfld.long 0xC 4. "CH1SCMP1,compare 1 event generates channel 1 set request" "0,1"
bitfld.long 0xC 3. "CH1SCMP0,compare 0 event generates channel 1 set request" "0,1"
bitfld.long 0xC 2. "CH1SPER,period event generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 1. "CH1SRST,reset event generates channel 1 set request" "0,1"
bitfld.long 0xC 0. "CH1SSEV,Software event generates channel 1 set request" "0,1"
line.long 0x10 "ST2CH1RST,HRTIMER Slave_TIMER2 channel 1 reset request register"
bitfld.long 0x10 31. "CH1RSUP,Update event generates channel 1 reset request" "0,1"
bitfld.long 0x10 30. "CH1RSEXEV9,External event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x10 29. "CH1RSEXEV8,External event 8 generates channel 1 reset request" "0,1"
bitfld.long 0x10 28. "CH1RSEXEV7,External event 7 generates channel 1 reset request" "0,1"
bitfld.long 0x10 27. "CH1RSEXEV6,External event 6 generates channel 1 reset request" "0,1"
bitfld.long 0x10 26. "CH1RSEXEV5,External event 5 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 25. "CH1RSEXEV4,External event 4 generates channel 1 reset request" "0,1"
bitfld.long 0x10 24. "CH1RSEXEV3,External event 3 generates channel 1 reset request" "0,1"
bitfld.long 0x10 23. "CH1RSEXEV2,External event 2 generates channel 1 reset request" "0,1"
bitfld.long 0x10 22. "CH1RSEXEV1,External event 1 generates channel 1 reset request" "0,1"
bitfld.long 0x10 21. "CH1RSEXEV0,External event 0 generates channel 1 reset request" "0,1"
bitfld.long 0x10 20. "CH1RSSTEV8,interconnection event 8 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 19. "CH1RSSTEV7,interconnection event 7 generates channel 1 reset request" "0,1"
bitfld.long 0x10 18. "CH1RSSTEV6,interconnection event 6 generates channel 1 reset request" "0,1"
bitfld.long 0x10 17. "CH1RSSTEV5,interconnection event 5 generates channel 1 reset request" "0,1"
bitfld.long 0x10 16. "CH1RSSTEV4,interconnection event 4 generates channel 1 reset request" "0,1"
bitfld.long 0x10 15. "CH1RSSTEV3,interconnection event 3 generates channel 1 reset request" "0,1"
bitfld.long 0x10 14. "CH1RSSTEV2,interconnection event 2 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 13. "CH1RSSTEV1,interconnection event 1 generates channel 1 reset request" "0,1"
bitfld.long 0x10 12. "CH1RSSTEV0,interconnection event 0 generates channel 1 reset request" "0,1"
bitfld.long 0x10 11. "CH1RSMTCMP3,Master_TIMER compare 3 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 10. "CH1RSMTCMP2,Master_TIMER compare 2 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 9. "CH1RSMTCMP1,Master_TIMER compare 1 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 8. "CH1RSMTCMP0,Master_TIMER compare 0 event generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 7. "CH1RSMTPER,Master_TIMER period event generates channel 1 reset request" "0,1"
bitfld.long 0x10 6. "CH1RSCMP3,compare 3 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 5. "CH1RSCMP2,compare 2 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 4. "CH1RSCMP1,compare 1 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 3. "CH1RSCMP0,compare 0 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 2. "CH1RSPER,period event generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 1. "CH1RSRST,reset event generates channel 1 reset request" "0,1"
bitfld.long 0x10 0. "CH1RSSEV,Software event generates channel 1 reset request" "0,1"
line.long 0x14 "ST2EXEVFCFG0,HRTIMER Slave_TIMER2 external event filter configuration register 0"
hexmask.long.byte 0x14 25.--29. 1. "EXEV4FM,External event 4 filter mode"
bitfld.long 0x14 24. "EXEV4MEEN,External event 4 memorized enable" "0,1"
hexmask.long.byte 0x14 19.--23. 1. "EXEV3FM,External event 3 filter mode"
bitfld.long 0x14 18. "EXEV3MEEN,External event 3 memorized enable" "0,1"
hexmask.long.byte 0x14 13.--17. 1. "EXEV2FM,External event 2 filter mode"
bitfld.long 0x14 12. "EXEV2MEEN,External event 2 memorized enable" "0,1"
newline
hexmask.long.byte 0x14 7.--11. 1. "EXEV1FM,External event 1 filter mode"
bitfld.long 0x14 6. "EXEV1MEEN,External event 1 memorized enable" "0,1"
hexmask.long.byte 0x14 1.--5. 1. "EXEV0FM,External event 0 filter mode"
bitfld.long 0x14 0. "EXEV0MEEN,External event 0 memory" "0,1"
line.long 0x18 "ST2EXEVFCFG1,HRTIMER Slave_TIMER2 external event filter configuration register 1"
hexmask.long.byte 0x18 25.--29. 1. "EXEV9FM,External event 9 filter mode"
bitfld.long 0x18 24. "EXEV9MEEN,External event 9 memorized enable" "0,1"
hexmask.long.byte 0x18 19.--23. 1. "EXEV8FM,External event 8 filter mode"
bitfld.long 0x18 18. "EXEV8MEEN,External event 8 memorized enable" "0,1"
hexmask.long.byte 0x18 13.--17. 1. "EXEV7FM,External event 7 filter mode"
bitfld.long 0x18 12. "EXEV7MEEN,External event 7 memorized enable" "0,1"
newline
hexmask.long.byte 0x18 7.--11. 1. "EXEV6FM,External event 6 filter mode"
bitfld.long 0x18 6. "EXEV6MEEN,External event 6 memorized enable" "0,1"
hexmask.long.byte 0x18 1.--5. 1. "EXEV5FM,External event 5 filter mode"
bitfld.long 0x18 0. "EXEV5MEEN,External event 0 memorized enable" "0,1"
line.long 0x1C "ST2CNTRST,HRTIMER Slave_TIMER2 counter reset register"
bitfld.long 0x1C 31. "ST5CMP1RST,Slave_TIMER5 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 30. "ST4CMP3RST,Slave_TIMER4 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 29. "ST4CMP1RST,Slave_TIMER4 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 28. "ST4CMP0RST,Slave_TIMER4 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 27. "ST3CMP3RST,Slave_TIMER3 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 26. "ST3CMP1RST,Slave_TIMER3 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x1C 25. "ST3CMP0RST,Slave_TIMER3 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 24. "ST1CMP3RST,Slave_TIMER1 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 23. "ST1CMP1RST,Slave_TIMER1 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 22. "ST1CMP0RST,Slave_TIMER1 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 21. "ST0CMP3RST,Slave_TIMER0 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 20. "ST0CMP1RST,Slave_TIMER0 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x1C 19. "ST0CMP0RST,Slave_TIMER0 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 18. "EXEV9RST,External event 9 resets counter" "0,1"
bitfld.long 0x1C 17. "EXEV8RST,External event 8 resets counter" "0,1"
bitfld.long 0x1C 16. "EXEV7RST,External event 7 resets counter" "0,1"
bitfld.long 0x1C 15. "EXEV6RST,External event 6 resets counter" "0,1"
bitfld.long 0x1C 14. "EXEV5RST,External event 5 resets counter" "0,1"
newline
bitfld.long 0x1C 13. "EXEV4RST,External event 4 resets counter" "0,1"
bitfld.long 0x1C 12. "EXEV3RST,External event 3 resets counter" "0,1"
bitfld.long 0x1C 11. "EXEV2RST,External event 2 resets counter" "0,1"
bitfld.long 0x1C 10. "EXEV1RST,External event 1 resets counter" "0,1"
bitfld.long 0x1C 9. "EXEV0RST,External event 0 resets counter" "0,1"
bitfld.long 0x1C 8. "MTCMP3RST,Master_TIMER compare 3 event resets counter" "0,1"
newline
bitfld.long 0x1C 7. "MTCMP2RST,Master_TIMER compare 2 event resets counter" "0,1"
bitfld.long 0x1C 6. "MTCMP1RST,Master_TIMER compare 1 event resets counter" "0,1"
bitfld.long 0x1C 5. "MTCMP0RST,Master_TIMER compare 0 event resets counter" "0,1"
bitfld.long 0x1C 4. "MTPERRST,Master_TIMER period event resets counter" "0,1"
bitfld.long 0x1C 3. "CMP3RST,Slave_TIMER2 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 2. "CMP1RST,Slave_TIMER2 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x1C 1. "UPRST,Slave_TIMER2 update event resets counter" "0,1"
bitfld.long 0x1C 0. "ST5CMP0RST,Slave_TIMER5 compare 0 event resets counter" "0,1"
line.long 0x20 "ST2CSCTL,HRTIMER Slave_TIMER2 carrier-signal control register"
hexmask.long.byte 0x20 7.--10. 1. "CSFSTPW,First carrier-signal pulse width"
bitfld.long 0x20 4.--6. "CSDTY,Carrier signal duty cycle" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x20 0.--3. 1. "CSPRD,Carrier signal period"
line.long 0x24 "ST2CAP0TRG,HRTIMER Slave_TIMER2 capture 0 trigger register"
bitfld.long 0x24 31. "CP0BST4CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x24 30. "CP0BST4CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x24 29. "CP0BST4NA,Capture 0 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 28. "CP0BST4A,Capture 0 triggered by ST4CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 27. "CP0BST3CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x24 26. "CP0BST3CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER3" "0,1"
newline
bitfld.long 0x24 25. "CP0BST3NA,Capture 0 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 24. "CP0BST3A,Capture 0 triggered by ST3CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 19. "CP0BST1CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x24 18. "CP0BST1CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x24 17. "CP0BST1NA,Capture 0 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 16. "CP0BST1A,Capture 0 triggered by ST1CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x24 15. "CP0BST0CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x24 14. "CP0BST0CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x24 13. "CP0BST0NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 12. "CP0BST0A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
bitfld.long 0x24 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
newline
bitfld.long 0x24 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x24 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
bitfld.long 0x24 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x24 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x24 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x24 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x24 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x24 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x24 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x24 0. "CP0BSW,Capture 0 triggered by software" "0,1"
line.long 0x28 "ST2CAP1TRG,HRTIMER Slave_TIMER2 capture 1 trigger register"
bitfld.long 0x28 31. "CP1BST4CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x28 30. "CP1BST4CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x28 29. "CP1BST4NA,Capture 1 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 28. "CP1BST4A,Capture 1 triggered by ST4CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 27. "CP1BST3CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x28 26. "CP1BST3CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER3" "0,1"
newline
bitfld.long 0x28 25. "CP1BST3NA,Capture 1 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 24. "CP1BST3A,Capture 1 triggered by ST3CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 19. "CP1BST1CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x28 18. "CP1BST1CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x28 17. "CP1BST1NA,Capture 1 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 16. "CP1BST1A,Capture 1 triggered by ST1CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x28 15. "CP1BST0CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x28 14. "CP1BST0CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x28 13. "CP1BST0NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 12. "CP1BST0A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
bitfld.long 0x28 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
newline
bitfld.long 0x28 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
bitfld.long 0x28 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
bitfld.long 0x28 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x28 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x28 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x28 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
newline
bitfld.long 0x28 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
bitfld.long 0x28 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x28 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x28 0. "CP1BSW,Capture 1 triggered by software" "0,1"
line.long 0x2C "ST2CHOCTL,HRTIMER Slave_TIMER2 channel output control register"
bitfld.long 0x2C 23. "BMCH1DTI,Channel 1 dead-time insert in bunch mode" "0,1"
bitfld.long 0x2C 22. "CH1CSEN,Channel 1 carrier-signal mode enable" "0,1"
bitfld.long 0x2C 20.--21. "CH1FLTOS,Channel 1 Fault output state" "0,1,2,3"
bitfld.long 0x2C 19. "ISO1,channel 1 output idle state" "0,1"
bitfld.long 0x2C 18. "BMCH1IEN,Channel 1 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x2C 17. "CH1P,Channel 1 output polarity" "0,1"
newline
bitfld.long 0x2C 14. "BALIAR,Balanced Idle Automatic Resumption" "0,1"
bitfld.long 0x2C 10.--12. "DLYISCH,Delayed IDLE source and channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x2C 9. "DLYISMEN,Delayed IDLE state mode enable" "0,1"
bitfld.long 0x2C 8. "DTEN,Dead time enable" "0,1"
bitfld.long 0x2C 7. "BMCH0DTI,Channel 0 dead-time insert in bunch mode" "0,1"
bitfld.long 0x2C 6. "CH0CSEN,Channel 0 carrier-signal mode enable" "0,1"
newline
bitfld.long 0x2C 4.--5. "CH0FLTOS,Channel 0 Fault output state" "0,1,2,3"
bitfld.long 0x2C 3. "ISO0,Channel 0 output idle state" "0,1"
bitfld.long 0x2C 2. "BMCH0IEN,Channel 0 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x2C 1. "CH0P,Channel 0 output polarity" "0,1"
line.long 0x30 "ST2FLTCTL,HRTIMER Slave_TIMER2 fault control register"
bitfld.long 0x30 31. "FLTENPROT,Protect fault enable" "0,1"
bitfld.long 0x30 7. "FLT7EN,Fault 7 enable" "0,1"
bitfld.long 0x30 6. "FLT6EN,Fault 6 enable" "0,1"
bitfld.long 0x30 5. "FLT5EN,Fault 5 enable" "0,1"
bitfld.long 0x30 4. "FLT4EN,Fault 4 enable" "0,1"
bitfld.long 0x30 3. "FLT3EN,Fault 3 enable" "0,1"
newline
bitfld.long 0x30 2. "FLT2EN,Fault 2 enable" "0,1"
bitfld.long 0x30 1. "FLT1EN,Fault 1 enable" "0,1"
bitfld.long 0x30 0. "FLT0EN,Fault 0 enable" "0,1"
line.long 0x34 "ST2CTL1,HRTIMER Slave_TIMER2 control register 1"
bitfld.long 0x34 20. "TRGHALFM,Triggered-half mode" "0,1"
bitfld.long 0x34 17. "IMUPD2V,Immediately update compare 2 value PWM mode" "0,1"
bitfld.long 0x34 16. "IMUPD0V,Immediately update compare 0 value PWM mode" "0,1"
bitfld.long 0x34 14.--15. "FEROVM,Fault and event roll-over mode" "0,1,2,3"
bitfld.long 0x34 12.--13. "BMROVM,Bunch mode roll-over mode" "0,1,2,3"
bitfld.long 0x34 10.--11. "ADCROVM,ADC roll-over mode" "0,1,2,3"
newline
bitfld.long 0x34 8.--9. "OUTROVM,Output roll-over mode" "0,1,2,3"
bitfld.long 0x34 6.--7. "ROVM,Roll-over mode" "0,1,2,3"
bitfld.long 0x34 4. "CAM,Center-aligned counting mode" "0,1"
bitfld.long 0x34 2. "TRIG1M,This bit defines when TRIG1M is generated" "0,1"
bitfld.long 0x34 1. "TRIG0M,This bit defines when TRIG0M is generated" "0,1"
bitfld.long 0x34 0. "TRIGEN,Two trigger enable" "0,1"
line.long 0x38 "ST2EXEVFCFG2,HRTIMER Slave_TIMER2 external event filter configuration register 2"
hexmask.long.byte 0x38 26.--31. 1. "EXEVXCNT,External event X counter value"
hexmask.long.byte 0x38 8.--13. 1. "EXEVXCNTTHR,External event X counter threshold"
hexmask.long.byte 0x38 4.--7. 1. "EXEVXSEL,External event X selection This bit determines the source of external event X"
bitfld.long 0x38 2. "EXEVXRSTM,External event X reset mode" "0,1"
bitfld.long 0x38 1. "EXEVXCRST,External event X counter reset" "0,1"
bitfld.long 0x38 0. "EXEVXCEN,External event X counter enable" "0,1"
line.long 0x3C "ST2CAPTRGCOM,HRTIMER Slave_TIMER2 capture trigger combination register"
bitfld.long 0x3C 27. "CP1BST7CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 26. "CP1BST7CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 25. "CP1BST7NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 24. "CP1BST7A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 23. "CP1BST6CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER6" "0,1"
bitfld.long 0x3C 22. "CP1BST6CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER6" "0,1"
newline
bitfld.long 0x3C 21. "CP1BST6NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 20. "CP1BST6A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 19. "CP1BST5CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 18. "CP1BST5CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 17. "CP1BST5NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 16. "CP1BST5A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x3C 11. "CP0BST7CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 10. "CP0BST7CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 9. "CP0BST7NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 8. "CP0BST7A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 7. "CP0BST6CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER6" "0,1"
bitfld.long 0x3C 6. "CP0BST6CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER6" "0,1"
newline
bitfld.long 0x3C 5. "CP0BST6NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 4. "CP0BST6A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 3. "CP0BST5CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 2. "CP0BST5CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 1. "CP0BST5NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 0. "CP0BST5A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
line.long 0x40 "ST2CNTRSTA,HRTIMER Slave_TIMER2 counter reset and channel 0/1 set/reset request add register"
bitfld.long 0x40 29. "CH1RSSTCNTRST,Slave_TIMER2 counter reset generates channel 1 reset request" "0,1"
bitfld.long 0x40 28. "CH0RSSTCNTRST,Slave_TIMER2 counter reset generates channel 0 reset request" "0,1"
bitfld.long 0x40 27. "CH1RSSTEV10,Slave_TIMER2 interconnection event 10 generates channel 1 reset request" "0,1"
bitfld.long 0x40 26. "CH1RSSTEV9,Slave_TIMER2 interconnection event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x40 25. "CH0RSSTEV10,Slave_TIMER2 interconnection event 10 generates channel 0 reset request" "0,1"
bitfld.long 0x40 24. "CH0RSSTEV9,Slave_TIMER2 interconnection event 9 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x40 21. "CH1SSTCNTRST,Slave_TIMER2 counter reset generates channel 1 reset request" "0,1"
bitfld.long 0x40 20. "CH0SSTCNTRST,Slave_TIMER2 counter reset generates channel 0 reset request" "0,1"
bitfld.long 0x40 19. "CH1SSTEV10,Slave_TIMER2 interconnection event 10 generates channel 1 reset request" "0,1"
bitfld.long 0x40 18. "CH1SSTEV9,Slave_TIMER2 interconnection event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x40 17. "CH0SSTEV10,Slave_TIMER2 interconnection event 10 generates channel 0 set request" "0,1"
bitfld.long 0x40 16. "CH0SSTEV9,Slave_TIMER2 interconnection event 9 generates channel 1 set request" "0,1"
newline
bitfld.long 0x40 6. "ST7CMP3RST,Slave_TIMER7 compare 3 event resets counter" "0,1"
bitfld.long 0x40 5. "ST7CMP1RST,Slave_TIMER7 compare 1 event resets counter" "0,1"
bitfld.long 0x40 4. "ST7CMP0RST,Slave_TIMER7 compare 0 event resets counter" "0,1"
bitfld.long 0x40 3. "ST6CMP3RST,Slave_TIMER6 compare 3 event resets counter" "0,1"
bitfld.long 0x40 2. "ST6CMP1RST,Slave_TIMER6 compare 1 event resets counter" "0,1"
bitfld.long 0x40 1. "ST6CMP0RST,Slave_TIMER6 compare 0 event resets counter" "0,1"
newline
bitfld.long 0x40 0. "ST5CMP3RST,Slave_TIMER5 compare 3 event resets counter" "0,1"
line.long 0x44 "ST2ACTL,HRTIMER Slave_TIMER2 additional control register"
hexmask.long.byte 0x44 25.--31. 1. "DTFCFG,Falling edge dead-time value configure"
hexmask.long.byte 0x44 9.--15. 1. "DTRCFG,Rising edge dead-time value configure"
bitfld.long 0x44 1. "UPBST7,Update by Slave_TIMER7 update event" "0,1"
bitfld.long 0x44 0. "UPBST6,Update by Slave_TIMER6 update event" "0,1"
tree.end
tree "HRTIMER_SLAVE_TIMER3"
base ad:0x40015A00
group.long 0x0++0x3
line.long 0x0 "ST3CTL0,HRTIMER Slave_TIME3 control register 0"
hexmask.long.byte 0x0 28.--31. 1. "UPSEL,Update event selection"
bitfld.long 0x0 27. "SHWEN,Shadow registers enable" "0,1"
bitfld.long 0x0 25.--26. "DACTRGS,Trigger source to DAC" "0,1,2,3"
bitfld.long 0x0 24. "UPBMT,Update by Master_TIMER update event" "0,1"
bitfld.long 0x0 23. "UPBST4,Update by Slave_TIMER4 update event" "0,1"
bitfld.long 0x0 22. "UPBST3,Update by Slave_TIMER3 update event" "0,1"
newline
bitfld.long 0x0 21. "UPBST2,Update by Slave_TIMER2 update event" "0,1"
bitfld.long 0x0 20. "UPBST1,Update by Slave_TIMER1 update event" "0,1"
bitfld.long 0x0 19. "UPBST0,Update by Slave_TIMER0 update event" "0,1"
bitfld.long 0x0 18. "UPRST,Update event generated by reset event" "0,1"
bitfld.long 0x0 17. "UPREP,Update event generated by repetition event" "0,1"
bitfld.long 0x0 16. "UPBST5,Update by Slave_TIMER5 update event" "0,1"
newline
bitfld.long 0x0 14.--15. "DELCMP3M,Compare 3 delayed mode" "0,1,2,3"
bitfld.long 0x0 12.--13. "DELCMP1M,Compare 1 delayed mode" "0,1,2,3"
bitfld.long 0x0 11. "SYNISTRT,Synchronous input start timer" "0,1"
bitfld.long 0x0 10. "SYNIRST,Synchronous input reset timer" "0,1"
bitfld.long 0x0 9. "RSYNUPD,Re-synchronized update" "0,1"
bitfld.long 0x0 7.--8. "ALTM,Alternate mode" "0,1,2,3"
newline
bitfld.long 0x0 6. "BLNMEN,Balanced mode enable" "0,1"
bitfld.long 0x0 5. "HALFM,Half mode" "0,1"
bitfld.long 0x0 4. "CNTRSTM,Counter reset mode" "0,1"
bitfld.long 0x0 3. "CTNM,Continuous mode" "0,1"
bitfld.long 0x0 0.--2. "CNTCKDIV,Counter clock division" "0,1,2,3,4,5,6,7"
rgroup.long 0x4++0x3
line.long 0x0 "ST3INTF,HRTIMER Slave_TIME3 interrupt flag register"
bitfld.long 0x0 31. "DIR,Direction" "0,1"
bitfld.long 0x0 21. "CH1F,Channel 1 output flag" "0,1"
bitfld.long 0x0 20. "CH0F,Channel 0 output flag" "0,1"
bitfld.long 0x0 19. "CH1SF,Channel 1 output state flag" "0,1"
bitfld.long 0x0 18. "CH0SF,Channel 0 output state flag" "0,1"
bitfld.long 0x0 17. "BLNIF,Balanced IDLE flag" "0,1"
newline
bitfld.long 0x0 16. "CBLNF,Current balanced flag" "0,1"
bitfld.long 0x0 14. "DLYIIF,Delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x0 13. "RSTIF,Counter reset interrupt flag" "0,1"
bitfld.long 0x0 12. "CH1ONAIF,Channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x0 11. "CH1OAIF,Channel 1 output active interrupt flag" "0,1"
bitfld.long 0x0 10. "CH0ONAIF,Channel 0 output inactive interrupt flag" "0,1"
newline
bitfld.long 0x0 9. "CH0OAIF,Channel 0 output active interrupt flag" "0,1"
bitfld.long 0x0 8. "CAP1IF,Capture 1 interrupt flag" "0,1"
bitfld.long 0x0 7. "CAP0IF,Capture 0 interrupt flag" "0,1"
bitfld.long 0x0 6. "UPIF,Update interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIF,Repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IF,Compare 3 interrupt flag" "0,1"
newline
bitfld.long 0x0 2. "CMP2IF,Compare 2 interrupt flag" "0,1"
bitfld.long 0x0 1. "CMP1IF,Compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IF,Compare 0 interrupt flag" "0,1"
wgroup.long 0x8++0x3
line.long 0x0 "ST3INTC,HRTIMER Slave_TIME3 interrupt flag clear register"
bitfld.long 0x0 14. "DLYIIFC,Clear delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x0 13. "RSTIFC,Clear counter reset interrupt flag" "0,1"
bitfld.long 0x0 12. "CH1ONAIFC,Clear channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x0 11. "CH1OAIFC,Clear channel 1 output active interrupt flag" "0,1"
bitfld.long 0x0 10. "CH0ONAIFC,Clear channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x0 9. "CH0OAIFC,Clear channel 0 output active interrupt flag" "0,1"
newline
bitfld.long 0x0 8. "CAP1IFC,Clear capture 1 interrupt flag" "0,1"
bitfld.long 0x0 7. "CAP0IFC,Clear capture 0 interrupt flag" "0,1"
bitfld.long 0x0 6. "UPIFC,Clear update interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIFC,Clear repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IFC,Clear compare 3 interrupt flag" "0,1"
bitfld.long 0x0 2. "CMP2IFC,Clear compare 2 interrupt flag" "0,1"
newline
bitfld.long 0x0 1. "CMP1IFC,Clear compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IFC,Clear compare 0 interrupt flag" "0,1"
group.long 0xC++0x23
line.long 0x0 "ST3DMAINTEN,HRTIMER Slave_TIME3 DMA and interrupt enable register"
bitfld.long 0x0 30. "DLYIDEN,Delayed IDLE mode entry DMA request enable" "0,1"
bitfld.long 0x0 29. "RSTDEN,Counter reset DMA request enable" "0,1"
bitfld.long 0x0 28. "CH1ONADEN,Channel 1 output inactive DMA request enable" "0,1"
bitfld.long 0x0 27. "CH1OADEN,Channel 1 output active DMA request enable" "0,1"
bitfld.long 0x0 26. "CH0ONADEN,Channel 0 output inactive DMA request enable" "0,1"
bitfld.long 0x0 25. "CH0OADEN,Channel 0 output active DMA request enable" "0,1"
newline
bitfld.long 0x0 24. "CAP1DEN,Capture 1 DMA request enable" "0,1"
bitfld.long 0x0 23. "CAP0DEN,Capture 0 DMA request enable" "0,1"
bitfld.long 0x0 22. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x0 20. "REPDEN,Repetition DMA request enable" "0,1"
bitfld.long 0x0 19. "CMP3DEN,Compare 3 DMA request enable" "0,1"
bitfld.long 0x0 18. "CMP2DEN,Compare 2 DMA request enable" "0,1"
newline
bitfld.long 0x0 17. "CMP1DEN,Compare 1 DMA request enable" "0,1"
bitfld.long 0x0 16. "CMP0DEN,Compare 0 DMA request enable" "0,1"
bitfld.long 0x0 14. "DLYIIE,Delayed IDLE mode entry interrupt enable" "0,1"
bitfld.long 0x0 13. "RSTIE,Counter reset interrupt enable" "0,1"
bitfld.long 0x0 12. "CH1ONAIE,Channel 1 output inactive interrupt enable" "0,1"
bitfld.long 0x0 11. "CH1OAIE,Channel 1 output active interrupt enable" "0,1"
newline
bitfld.long 0x0 10. "CH0ONAIE,Channel 0 output inactive interrupt enable" "0,1"
bitfld.long 0x0 9. "CH0OAIE,Channel 0 output active interrupt enable" "0,1"
bitfld.long 0x0 8. "CAP1IE,Capture 1 interrupt enable" "0,1"
bitfld.long 0x0 7. "CAP0IE,Capture 0 interrupt enable" "0,1"
bitfld.long 0x0 6. "UPIE,Update interrupt enable" "0,1"
bitfld.long 0x0 4. "REPIE,Repetition interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "CMP3IE,Compare 3 interrupt enable" "0,1"
bitfld.long 0x0 2. "CMP2IE,Compare 2 interrupt enable" "0,1"
bitfld.long 0x0 1. "CMP1IE,Compare 1 interrupt enable" "0,1"
bitfld.long 0x0 0. "CMP0IE,Compare 0 interrupt enable" "0,1"
line.long 0x4 "ST3CNT,HRTIMER Slave_TIME3 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,The current counter value"
line.long 0x8 "ST3CAR,HRTIMER Slave_TIME3 counter auto reload register"
hexmask.long.word 0x8 0.--15. 1. "CARL,Counter auto reload value"
line.long 0xC "ST3CREP,HRTIMER Slave_TIME3 counter repetition register"
hexmask.long.byte 0xC 0.--7. 1. "CREP,Counter repetition value"
line.long 0x10 "ST3CMP0V,HRTIMER Slave_TIME3 compare 0 value register"
hexmask.long.word 0x10 0.--15. 1. "CMP0VAL,Compare 0 value"
line.long 0x14 "ST3CMP0CP,HRTIMER Slave_TIME3 compare 0 composite register"
hexmask.long.byte 0x14 16.--23. 1. "CREP,Counter repetition value"
hexmask.long.word 0x14 0.--15. 1. "CMP0VAL,Compare 0 value"
line.long 0x18 "ST3CMP1V,HRTIMER Slave_TIME3 compare 1 value register"
hexmask.long.word 0x18 0.--15. 1. "CMP1VAL,Compare 1 value"
line.long 0x1C "ST3CMP2V,HRTIMER Slave_TIME3 compare 2 value register"
hexmask.long.word 0x1C 0.--15. 1. "CMP2VAL,Compare 2 value"
line.long 0x20 "ST3CMP3V,HRTIMER Slave_TIME3 compare 3 value register"
hexmask.long.word 0x20 0.--15. 1. "CMP3VAL,Compare 3 value"
rgroup.long 0x30++0x7
line.long 0x0 "ST3CAP0V,HRTIMER Slave_TIME3 capture 0 value register"
bitfld.long 0x0 16. "DIR,Slave_timer 0 capture 1 direction status" "0,1"
hexmask.long.word 0x0 0.--15. 1. "CAP0VAL,Capture 0 value"
line.long 0x4 "ST3CAP1V,HRTIMER Slave_TIME3 capture 1 value register"
bitfld.long 0x4 16. "DIR,Slave_Timer 0 capture 1 direction status" "0,1"
hexmask.long.word 0x4 0.--15. 1. "CAP1VAL,Capture 1 value"
group.long 0x38++0x47
line.long 0x0 "ST3DTCTL,HRTIMER Slave_TIME3 dead-time control register"
bitfld.long 0x0 31. "DTFSVPROT,Dead-time falling edge protection for value and sign" "0,1"
bitfld.long 0x0 30. "DTFSPROT,Dead-time falling edge protection for sign" "0,1"
bitfld.long 0x0 25. "DTFS,The sign of falling edge dead-time value" "0,1"
hexmask.long.word 0x0 16.--24. 1. "DTFCFG,Falling edge dead-time value"
bitfld.long 0x0 15. "DTRSVPROT,Dead-time rising edge protection for value and sign" "0,1"
bitfld.long 0x0 14. "DTRSPROT,Dead-time rising edge protection for sign" "0,1"
newline
hexmask.long.byte 0x0 10.--13. 1. "DTGCKDIV,Dead time clock division"
bitfld.long 0x0 9. "DTRS,The sign of rising edge dead-time value" "0,1"
hexmask.long.word 0x0 0.--8. 1. "DTRCFG,Rising edge dead-time value"
line.long 0x4 "ST3CH0SET,HRTIMER Slave_TIME3 channel 0 set request register"
bitfld.long 0x4 31. "CH0SUP,Update event generates channel 0 set request" "0,1"
bitfld.long 0x4 30. "CH0SEXEV9,External event 9 generates channel 0 set request" "0,1"
bitfld.long 0x4 29. "CH0SEXEV8,External event 8 generates channel 0 set request" "0,1"
bitfld.long 0x4 28. "CH0SEXEV7,External event 7 generates channel 0 set request" "0,1"
bitfld.long 0x4 27. "CH0SEXEV6,External event 6 generates channel 0 set request" "0,1"
bitfld.long 0x4 26. "CH0SEXEV5,External event 5 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 25. "CH0SEXEV4,External event 4 generates channel 0 set request" "0,1"
bitfld.long 0x4 24. "CH0SEXEV3,External event 3 generates channel 0 set request" "0,1"
bitfld.long 0x4 23. "CH0SEXEV2,External event 2 generates channel 0 set request" "0,1"
bitfld.long 0x4 22. "CH0SEXEV1,External event 1 generates channel 0 set request" "0,1"
bitfld.long 0x4 21. "CH0SEXEV0,External event 0 generates channel 0 set request" "0,1"
bitfld.long 0x4 20. "CH0SSTEV8,interconnection event 8 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 19. "CH0SSTEV7,interconnection event 7 generates channel 0 set request" "0,1"
bitfld.long 0x4 18. "CH0SSTEV6,interconnection event 6 generates channel 0 set request" "0,1"
bitfld.long 0x4 17. "CH0SSTEV5,interconnection event 5 generates channel 0 set request" "0,1"
bitfld.long 0x4 16. "CH0SSTEV4,interconnection event 4 generates channel 0 set request" "0,1"
bitfld.long 0x4 15. "CH0SSTEV3,interconnection event 3 generates channel 0 set request" "0,1"
bitfld.long 0x4 14. "CH0SSTEV2,interconnection event 2 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 13. "CH0SSTEV1,interconnection event 1 generates channel 0 set request" "0,1"
bitfld.long 0x4 12. "CH0SSTEV0,interconnection event 0 generates channel 0 set request" "0,1"
bitfld.long 0x4 11. "CH0SMTCMP3,Master_TIMER compare 3 event generates channel 0 set request" "0,1"
bitfld.long 0x4 10. "CH0SMTCMP2,Master_TIMER compare 2 event generates channel 0 set request" "0,1"
bitfld.long 0x4 9. "CH0SMTCMP1,Master_TIMER compare 1 event generates channel 0 set request" "0,1"
bitfld.long 0x4 8. "CH0SMTCMP0,Master_TIMER compare 0 event generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 7. "CH0SMTPER,Master_TIMER period event generates channel 0 set request" "0,1"
bitfld.long 0x4 6. "CH0SCMP3,compare 3 event generates channel 0 set request" "0,1"
bitfld.long 0x4 5. "CH0SCMP2,compare 2 event generates channel 0 set request" "0,1"
bitfld.long 0x4 4. "CH0SCMP1,compare 1 event generates channel 0 set request" "0,1"
bitfld.long 0x4 3. "CH0SCMP0,compare 0 event generates channel 0 set request" "0,1"
bitfld.long 0x4 2. "CH0SPER,period event generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 1. "CH0SRST,reset event generates channel 0 set request" "0,1"
bitfld.long 0x4 0. "CH0SSEV,Software event generates channel 0 set request" "0,1"
line.long 0x8 "ST3CH0RST,HRTIMER Slave_TIME3 channel 0 reset request register"
bitfld.long 0x8 31. "CH0RSUP,Update event generates channel 0 reset request" "0,1"
bitfld.long 0x8 30. "CH0RSEXEV9,External event 9 generates channel 0 reset request" "0,1"
bitfld.long 0x8 29. "CH0RSEXEV8,External event 8 generates channel 0 reset request" "0,1"
bitfld.long 0x8 28. "CH0RSEXEV7,External event 7 generates channel 0 reset request" "0,1"
bitfld.long 0x8 27. "CH0RSEXEV6,External event 6 generates channel 0 reset request" "0,1"
bitfld.long 0x8 26. "CH0RSEXEV5,External event 5 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 25. "CH0RSEXEV4,External event 4 generates channel 0 reset request" "0,1"
bitfld.long 0x8 24. "CH0RSEXEV3,External event 3 generates channel 0 reset request" "0,1"
bitfld.long 0x8 23. "CH0RSEXEV2,External event 2 generates channel 0 reset request" "0,1"
bitfld.long 0x8 22. "CH0RSEXEV1,External event 1 generates channel 0 reset request" "0,1"
bitfld.long 0x8 21. "CH0RSEXEV0,External event 0 generates channel 0 reset request" "0,1"
bitfld.long 0x8 20. "CH0RSSTEV8,interconnection event 8 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 19. "CH0RSSTEV7,interconnection event 7 generates channel 0 reset request" "0,1"
bitfld.long 0x8 18. "CH0RSSTEV6,interconnection event 6 generates channel 0 reset request" "0,1"
bitfld.long 0x8 17. "CH0RSSTEV5,interconnection event 5 generates channel 0 reset request" "0,1"
bitfld.long 0x8 16. "CH0RSSTEV4,interconnection event 4 generates channel 0 reset request" "0,1"
bitfld.long 0x8 15. "CH0RSSTEV3,interconnection event 3 generates channel 0 reset request" "0,1"
bitfld.long 0x8 14. "CH0RSSTEV2,interconnection event 2 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 13. "CH0RSSTEV1,interconnection event 1 generates channel 0 reset request" "0,1"
bitfld.long 0x8 12. "CH0RSSTEV0,interconnection event 0 generates channel 0 reset request" "0,1"
bitfld.long 0x8 11. "CH0RSMTCMP3,Master_TIMER compare 3 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 10. "CH0RSMTCMP2,Master_TIMER compare 2 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 9. "CH0RSMTCMP1,Master_TIMER compare 1 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 8. "CH0RSMTCMP0,Master_TIMER compare 0 event generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 7. "CH0RSMTPER,Master_TIMER period event generates channel 0 reset request" "0,1"
bitfld.long 0x8 6. "CH0RSCMP3,compare 3 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 5. "CH0RSCMP2,compare 2 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 4. "CH0RSCMP1,compare 1 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 3. "CH0RSCMP0,compare 0 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 2. "CH0RSPER,period event generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 1. "CH0RSRST,reset event generates channel 0 reset request" "0,1"
bitfld.long 0x8 0. "CH0RSSEV,Software event generates channel 0 reset request" "0,1"
line.long 0xC "ST3CH1SET,HRTIMER Slave_TIME3 channel 1 set request register"
bitfld.long 0xC 31. "CH1SUP,Update event generates channel 1 set request" "0,1"
bitfld.long 0xC 30. "CH1SEXEV9,External event 9 generates channel 1 set request" "0,1"
bitfld.long 0xC 29. "CH1SEXEV8,External event 8 generates channel 1 set request" "0,1"
bitfld.long 0xC 28. "CH1SEXEV7,External event 7 generates channel 1 set request" "0,1"
bitfld.long 0xC 27. "CH1SEXEV6,External event 6 generates channel 1 set request" "0,1"
bitfld.long 0xC 26. "CH1SEXEV5,External event 5 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 25. "CH1SEXEV4,External event 4 generates channel 1 set request" "0,1"
bitfld.long 0xC 24. "CH1SEXEV3,External event 3 generates channel 1 set request" "0,1"
bitfld.long 0xC 23. "CH1SEXEV2,External event 2 generates channel 1 set request" "0,1"
bitfld.long 0xC 22. "CH1SEXEV1,External event 1 generates channel 1 set request" "0,1"
bitfld.long 0xC 21. "CH1SEXEV0,External event 0 generates channel 1 set request" "0,1"
bitfld.long 0xC 20. "CH1SSTEV8,interconnection event 8 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 19. "CH1SSTEV7,interconnection event 7 generates channel 1 set request" "0,1"
bitfld.long 0xC 18. "CH1SSTEV6,interconnection event 6 generates channel 1 set request" "0,1"
bitfld.long 0xC 17. "CH1SSTEV5,interconnection event 5 generates channel 1 set request" "0,1"
bitfld.long 0xC 16. "CH1SSTEV4,interconnection event 4 generates channel 1 set request" "0,1"
bitfld.long 0xC 15. "CH1SSTEV3,interconnection event 3 generates channel 1 set request" "0,1"
bitfld.long 0xC 14. "CH1SSTEV2,interconnection event 2 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 13. "CH1SSTEV1,interconnection event 1 generates channel 1 set request" "0,1"
bitfld.long 0xC 12. "CH1SSTEV0,interconnection event 0 generates channel 1 set request" "0,1"
bitfld.long 0xC 11. "CH1SMTCMP3,Master_TIMER compare 3 event generates channel 1 set request" "0,1"
bitfld.long 0xC 10. "CH1SMTCMP2,Master_TIMER compare 2 event generates channel 1 set request" "0,1"
bitfld.long 0xC 9. "CH1SMTCMP1,Master_TIMER compare 1 event generates channel 1 set request" "0,1"
bitfld.long 0xC 8. "CH1SMTCMP0,Master_TIMER compare 0 event generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 7. "CH1SMTPER,Master_TIMER period event generates channel 1 set request" "0,1"
bitfld.long 0xC 6. "CH1SCMP3,compare 3 event generates channel 1 set request" "0,1"
bitfld.long 0xC 5. "CH1SCMP2,compare 2 event generates channel 1 set request" "0,1"
bitfld.long 0xC 4. "CH1SCMP1,compare 1 event generates channel 1 set request" "0,1"
bitfld.long 0xC 3. "CH1SCMP0,compare 0 event generates channel 1 set request" "0,1"
bitfld.long 0xC 2. "CH1SPER,period event generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 1. "CH1SRST,reset event generates channel 1 set request" "0,1"
bitfld.long 0xC 0. "CH1SSEV,Software event generates channel 1 set request" "0,1"
line.long 0x10 "ST3CH1RST,HRTIMER Slave_TIME3 channel 1 reset request register"
bitfld.long 0x10 31. "CH1RSUP,Update event generates channel 1 reset request" "0,1"
bitfld.long 0x10 30. "CH1RSEXEV9,External event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x10 29. "CH1RSEXEV8,External event 8 generates channel 1 reset request" "0,1"
bitfld.long 0x10 28. "CH1RSEXEV7,External event 7 generates channel 1 reset request" "0,1"
bitfld.long 0x10 27. "CH1RSEXEV6,External event 6 generates channel 1 reset request" "0,1"
bitfld.long 0x10 26. "CH1RSEXEV5,External event 5 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 25. "CH1RSEXEV4,External event 4 generates channel 1 reset request" "0,1"
bitfld.long 0x10 24. "CH1RSEXEV3,External event 3 generates channel 1 reset request" "0,1"
bitfld.long 0x10 23. "CH1RSEXEV2,External event 2 generates channel 1 reset request" "0,1"
bitfld.long 0x10 22. "CH1RSEXEV1,External event 1 generates channel 1 reset request" "0,1"
bitfld.long 0x10 21. "CH1RSEXEV0,External event 0 generates channel 1 reset request" "0,1"
bitfld.long 0x10 20. "CH1RSSTEV8,interconnection event 8 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 19. "CH1RSSTEV7,interconnection event 7 generates channel 1 reset request" "0,1"
bitfld.long 0x10 18. "CH1RSSTEV6,interconnection event 6 generates channel 1 reset request" "0,1"
bitfld.long 0x10 17. "CH1RSSTEV5,interconnection event 5 generates channel 1 reset request" "0,1"
bitfld.long 0x10 16. "CH1RSSTEV4,interconnection event 4 generates channel 1 reset request" "0,1"
bitfld.long 0x10 15. "CH1RSSTEV3,interconnection event 3 generates channel 1 reset request" "0,1"
bitfld.long 0x10 14. "CH1RSSTEV2,interconnection event 2 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 13. "CH1RSSTEV1,interconnection event 1 generates channel 1 reset request" "0,1"
bitfld.long 0x10 12. "CH1RSSTEV0,interconnection event 0 generates channel 1 reset request" "0,1"
bitfld.long 0x10 11. "CH1RSMTCMP3,Master_TIMER compare 3 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 10. "CH1RSMTCMP2,Master_TIMER compare 2 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 9. "CH1RSMTCMP1,Master_TIMER compare 1 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 8. "CH1RSMTCMP0,Master_TIMER compare 0 event generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 7. "CH1RSMTPER,Master_TIMER period event generates channel 1 reset request" "0,1"
bitfld.long 0x10 6. "CH1RSCMP3,compare 3 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 5. "CH1RSCMP2,compare 2 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 4. "CH1RSCMP1,compare 1 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 3. "CH1RSCMP0,compare 0 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 2. "CH1RSPER,period event generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 1. "CH1RSRST,reset event generates channel 1 reset request" "0,1"
bitfld.long 0x10 0. "CH1RSSEV,Software event generates channel 1 reset request" "0,1"
line.long 0x14 "ST3EXEVFCFG0,HRTIMER Slave_TIME3 external event filter configuration register 0"
hexmask.long.byte 0x14 25.--29. 1. "EXEV4FM,External event 4 filter mode"
bitfld.long 0x14 24. "EXEV4MEEN,External event 4 memorized enable" "0,1"
hexmask.long.byte 0x14 19.--23. 1. "EXEV3FM,External event 3 filter mode"
bitfld.long 0x14 18. "EXEV3MEEN,External event 3 memorized enable" "0,1"
hexmask.long.byte 0x14 13.--17. 1. "EXEV2FM,External event 2 filter mode"
bitfld.long 0x14 12. "EXEV2MEEN,External event 2 memorized enable" "0,1"
newline
hexmask.long.byte 0x14 7.--11. 1. "EXEV1FM,External event 1 filter mode"
bitfld.long 0x14 6. "EXEV1MEEN,External event 1 memorized enable" "0,1"
hexmask.long.byte 0x14 1.--5. 1. "EXEV0FM,External event 0 filter mode"
bitfld.long 0x14 0. "EXEV0MEEN,External event 0 memory" "0,1"
line.long 0x18 "ST3EXEVFCFG1,HRTIMER Slave_TIME3 external event filter configuration register 1"
hexmask.long.byte 0x18 25.--29. 1. "EXEV9FM,External event 9 filter mode"
bitfld.long 0x18 24. "EXEV9MEEN,External event 9 memorized enable" "0,1"
hexmask.long.byte 0x18 19.--23. 1. "EXEV8FM,External event 8 filter mode"
bitfld.long 0x18 18. "EXEV8MEEN,External event 8 memorized enable" "0,1"
hexmask.long.byte 0x18 13.--17. 1. "EXEV7FM,External event 7 filter mode"
bitfld.long 0x18 12. "EXEV7MEEN,External event 7 memorized enable" "0,1"
newline
hexmask.long.byte 0x18 7.--11. 1. "EXEV6FM,External event 6 filter mode"
bitfld.long 0x18 6. "EXEV6MEEN,External event 6 memorized enable" "0,1"
hexmask.long.byte 0x18 1.--5. 1. "EXEV5FM,External event 5 filter mode"
bitfld.long 0x18 0. "EXEV5MEEN,External event 0 memorized enable" "0,1"
line.long 0x1C "ST3CNTRST,HRTIMER Slave_TIMER3 counter reset register"
bitfld.long 0x1C 31. "ST5CMP1RST,Slave_TIMER5 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 30. "ST4CMP3RST,Slave_TIMER4 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 29. "ST4CMP1RST,Slave_TIMER4 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 28. "ST4CMP0RST,Slave_TIMER4 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 27. "ST2CMP3RST,Slave_TIMER2 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 26. "ST2CMP1RST,Slave_TIMER2 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x1C 25. "ST2CMP0RST,Slave_TIMER2compare 0 event resets counter" "0,1"
bitfld.long 0x1C 24. "ST1CMP3RST,Slave_TIMER1 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 23. "ST1CMP1RST,Slave_TIMER1 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 22. "ST1CMP0RST,Slave_TIMER1 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 21. "ST0CMP3RST,Slave_TIMER0 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 20. "ST0CMP1RST,Slave_TIMER0 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x1C 19. "ST0CMP0RST,Slave_TIMER0 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 18. "EXEV9RST,External event 9 resets counter" "0,1"
bitfld.long 0x1C 17. "EXEV8RST,External event 8 resets counter" "0,1"
bitfld.long 0x1C 16. "EXEV7RST,External event 7 resets counter" "0,1"
bitfld.long 0x1C 15. "EXEV6RST,External event 6 resets counter" "0,1"
bitfld.long 0x1C 14. "EXEV5RST,External event 5 resets counter" "0,1"
newline
bitfld.long 0x1C 13. "EXEV4RST,External event 4 resets counter" "0,1"
bitfld.long 0x1C 12. "EXEV3RST,External event 3 resets counter" "0,1"
bitfld.long 0x1C 11. "EXEV2RST,External event 2 resets counter" "0,1"
bitfld.long 0x1C 10. "EXEV1RST,External event 1 resets counter" "0,1"
bitfld.long 0x1C 9. "EXEV0RST,External event 0 resets counter" "0,1"
bitfld.long 0x1C 8. "MTCMP3RST,Master_TIMER compare 3 event resets counter" "0,1"
newline
bitfld.long 0x1C 7. "MTCMP2RST,Master_TIMER compare 2 event resets counter" "0,1"
bitfld.long 0x1C 6. "MTCMP1RST,Master_TIMER compare 1 event resets counter" "0,1"
bitfld.long 0x1C 5. "MTCMP0RST,Master_TIMER compare 0 event resets counter" "0,1"
bitfld.long 0x1C 4. "MTPERRST,Master_TIMER period event resets counter" "0,1"
bitfld.long 0x1C 3. "CMP3RST,Slave_TIMER3 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 2. "CMP1RST,Slave_TIMER3 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x1C 1. "UPRST,Slave_TIMER3 update event resets counter" "0,1"
bitfld.long 0x1C 0. "ST5CMP0RST,Slave_TIMER5 compare 0 event resets counter" "0,1"
line.long 0x20 "ST3CSCTL,HRTIMER Slave_TIME3 carrier-signal control register"
hexmask.long.byte 0x20 7.--10. 1. "CSFSTPW,First carrier-signal pulse width"
bitfld.long 0x20 4.--6. "CSDTY,Carrier signal duty cycle" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x20 0.--3. 1. "CSPRD,Carrier signal period"
line.long 0x24 "ST3CAP0TRG,HRTIMER Slave_TIMER3 capture 0 trigger register"
bitfld.long 0x24 31. "CP0BST4CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x24 30. "CP0BST4CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x24 29. "CP0BST4NA,Capture 0 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 28. "CP0BST4A,Capture 0 triggered by ST4CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 23. "CP0BST2CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x24 22. "CP0BST2CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER2" "0,1"
newline
bitfld.long 0x24 21. "CP0BST2NA,Capture 0 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 20. "CP0BST2A,Capture 0 triggered by ST2CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 19. "CP0BST1CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x24 18. "CP0BST1CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x24 17. "CP0BST1NA,Capture 0 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 16. "CP0BST1A,Capture 0 triggered by ST1CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x24 15. "CP0BST0CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x24 14. "CP0BST0CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x24 13. "CP0BST0NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 12. "CP0BST0A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
bitfld.long 0x24 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
newline
bitfld.long 0x24 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x24 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
bitfld.long 0x24 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x24 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x24 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x24 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x24 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x24 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x24 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x24 0. "CP0BSW,Capture 0 triggered by software" "0,1"
line.long 0x28 "ST3CAP1TRG,HRTIMER Slave_TIMER3 capture 1 trigger register"
bitfld.long 0x28 31. "CP1BST4CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x28 30. "CP1BST4CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x28 29. "CP1BST4NA,Capture 1 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 28. "CP1BST4A,Capture 1 triggered by ST4CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 23. "CP1BST2CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x28 22. "CP1BST2CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER2" "0,1"
newline
bitfld.long 0x28 21. "CP1BST2NA,Capture 1 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 20. "CP1BST2A,Capture 1 triggered by ST2CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 19. "CP1BST1CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x28 18. "CP1BST1CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x28 17. "CP1BST1NA,Capture 1 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 16. "CP1BST1A,Capture 1 triggered by ST1CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x28 15. "CP1BST0CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x28 14. "CP1BST0CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x28 13. "CP1BST0NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 12. "CP1BST0A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
bitfld.long 0x28 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
newline
bitfld.long 0x28 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
bitfld.long 0x28 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
bitfld.long 0x28 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x28 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x28 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x28 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
newline
bitfld.long 0x28 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
bitfld.long 0x28 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x28 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x28 0. "CP1BSW,Capture 1 triggered by software" "0,1"
line.long 0x2C "ST3CHOCTL,HRTIMER Slave_TIME3 channel output control register"
bitfld.long 0x2C 23. "BMCH1DTI,Channel 1 dead-time insert in bunch mode" "0,1"
bitfld.long 0x2C 22. "CH1CSEN,Channel 1 carrier-signal mode enable" "0,1"
bitfld.long 0x2C 20.--21. "CH1FLTOS,Channel 1 Fault output state" "0,1,2,3"
bitfld.long 0x2C 19. "ISO1,channel 1 output idle state" "0,1"
bitfld.long 0x2C 18. "BMCH1IEN,Channel 1 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x2C 17. "CH1P,Channel 1 output polarity" "0,1"
newline
bitfld.long 0x2C 14. "BALIAR,Balanced Idle Automatic Resumption" "0,1"
bitfld.long 0x2C 10.--12. "DLYISCH,Delayed IDLE source and channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x2C 9. "DLYISMEN,Delayed IDLE state mode enable" "0,1"
bitfld.long 0x2C 8. "DTEN,Dead time enable" "0,1"
bitfld.long 0x2C 7. "BMCH0DTI,Channel 0 dead-time insert in bunch mode" "0,1"
bitfld.long 0x2C 6. "CH0CSEN,Channel 0 carrier-signal mode enable" "0,1"
newline
bitfld.long 0x2C 4.--5. "CH0FLTOS,Channel 0 Fault output state" "0,1,2,3"
bitfld.long 0x2C 3. "ISO0,Channel 0 output idle state" "0,1"
bitfld.long 0x2C 2. "BMCH0IEN,Channel 0 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x2C 1. "CH0P,Channel 0 output polarity" "0,1"
line.long 0x30 "ST3FLTCTL,HRTIMER Slave_TIME3 fault control register"
bitfld.long 0x30 31. "FLTENPROT,Protect fault enable" "0,1"
bitfld.long 0x30 7. "FLT7EN,Fault 7 enable" "0,1"
bitfld.long 0x30 6. "FLT6EN,Fault 6 enable" "0,1"
bitfld.long 0x30 5. "FLT5EN,Fault 5 enable" "0,1"
bitfld.long 0x30 4. "FLT4EN,Fault 4 enable" "0,1"
bitfld.long 0x30 3. "FLT3EN,Fault 3 enable" "0,1"
newline
bitfld.long 0x30 2. "FLT2EN,Fault 2 enable" "0,1"
bitfld.long 0x30 1. "FLT1EN,Fault 1 enable" "0,1"
bitfld.long 0x30 0. "FLT0EN,Fault 0 enable" "0,1"
line.long 0x34 "ST3CTL1,HRTIMER Slave_TIME3 control register 1"
bitfld.long 0x34 20. "TRGHALFM,Triggered-half mode" "0,1"
bitfld.long 0x34 17. "IMUPD2V,Immediately update compare 2 value PWM mode" "0,1"
bitfld.long 0x34 16. "IMUPD0V,Immediately update compare 0 value PWM mode" "0,1"
bitfld.long 0x34 14.--15. "FEROVM,Fault and event roll-over mode" "0,1,2,3"
bitfld.long 0x34 12.--13. "BMROVM,Bunch mode roll-over mode" "0,1,2,3"
bitfld.long 0x34 10.--11. "ADCROVM,ADC roll-over mode" "0,1,2,3"
newline
bitfld.long 0x34 8.--9. "OUTROVM,Output roll-over mode" "0,1,2,3"
bitfld.long 0x34 6.--7. "ROVM,Roll-over mode" "0,1,2,3"
bitfld.long 0x34 4. "CAM,Center-aligned counting mode" "0,1"
bitfld.long 0x34 2. "TRIG1M,This bit defines when TRIG1M is generated" "0,1"
bitfld.long 0x34 1. "TRIG0M,This bit defines when TRIG0M is generated" "0,1"
bitfld.long 0x34 0. "TRIGEN,Two trigger enable" "0,1"
line.long 0x38 "ST3EXEVFCFG2,HRTIMER Slave_TIME3 external event filter configuration register 2"
hexmask.long.byte 0x38 26.--31. 1. "EXEVXCNT,External event X counter value"
hexmask.long.byte 0x38 8.--13. 1. "EXEVXCNTTHR,External event X counter threshold"
hexmask.long.byte 0x38 4.--7. 1. "EXEVXSEL,External event X selection This bit determines the source of external event X"
bitfld.long 0x38 2. "EXEVXRSTM,External event X reset mode" "0,1"
bitfld.long 0x38 1. "EXEVXCRST,External event X counter reset" "0,1"
bitfld.long 0x38 0. "EXEVXCEN,External event X counter enable" "0,1"
line.long 0x3C "ST3CAPTRGCOM,HRTIMER Slave_TIMER3 capture trigger combination register"
bitfld.long 0x3C 27. "CP1BST7CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 26. "CP1BST7CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 25. "CP1BST7NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 24. "CP1BST7A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 23. "CP1BST6CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER6" "0,1"
bitfld.long 0x3C 22. "CP1BST6CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER6" "0,1"
newline
bitfld.long 0x3C 21. "CP1BST6NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 20. "CP1BST6A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 19. "CP1BST5CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 18. "CP1BST5CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 17. "CP1BST5NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 16. "CP1BST5A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x3C 11. "CP0BST7CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 10. "CP0BST7CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 9. "CP0BST7NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 8. "CP0BST7A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 7. "CP0BST6CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER6" "0,1"
bitfld.long 0x3C 6. "CP0BST6CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER6" "0,1"
newline
bitfld.long 0x3C 5. "CP0BST6NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 4. "CP0BST6A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 3. "CP0BST5CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 2. "CP0BST5CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 1. "CP0BST5NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 0. "CP0BST5A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
line.long 0x40 "ST3CNTRSTA,HRTIMER Slave_TIMER3 counter reset and channel 0/1 set/reset request add register"
bitfld.long 0x40 29. "CH1RSSTCNTRST,Slave_TIMER3 counter reset generates channel 1 reset request" "0,1"
bitfld.long 0x40 28. "CH0RSSTCNTRST,Slave_TIMER3 counter reset generates channel 0 reset request" "0,1"
bitfld.long 0x40 27. "CH1RSSTEV10,Slave_TIMER3 interconnection event 10 generates channel 1 reset request" "0,1"
bitfld.long 0x40 26. "CH1RSSTEV9,Slave_TIMER3 interconnection event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x40 25. "CH0RSSTEV10,Slave_TIMER3 interconnection event 10 generates channel 0 reset request" "0,1"
bitfld.long 0x40 24. "CH0RSSTEV9,Slave_TIMER3 interconnection event 9 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x40 21. "CH1SSTCNTRST,Slave_TIMER3 counter reset generates channel 1 reset request" "0,1"
bitfld.long 0x40 20. "CH0SSTCNTRST,Slave_TIMER3 counter reset generates channel 0 reset request" "0,1"
bitfld.long 0x40 19. "CH1SSTEV10,Slave_TIMER3 interconnection event 10 generates channel 1 reset request" "0,1"
bitfld.long 0x40 18. "CH1SSTEV9,Slave_TIMER3 interconnection event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x40 17. "CH0SSTEV10,Slave_TIMER3 interconnection event 10 generates channel 0 set request" "0,1"
bitfld.long 0x40 16. "CH0SSTEV9,Slave_TIMER3 interconnection event 9 generates channel 1 set request" "0,1"
newline
bitfld.long 0x40 6. "ST7CMP3RST,Slave_TIMER7 compare 3 event resets counter" "0,1"
bitfld.long 0x40 5. "ST7CMP1RST,Slave_TIMER7 compare 1 event resets counter" "0,1"
bitfld.long 0x40 4. "ST7CMP0RST,Slave_TIMER7 compare 0 event resets counter" "0,1"
bitfld.long 0x40 3. "ST6CMP3RST,Slave_TIMER6 compare 3 event resets counter" "0,1"
bitfld.long 0x40 2. "ST6CMP1RST,Slave_TIMER6 compare 1 event resets counter" "0,1"
bitfld.long 0x40 1. "ST6CMP0RST,Slave_TIMER6 compare 0 event resets counter" "0,1"
newline
bitfld.long 0x40 0. "ST5CMP3RST,Slave_TIMER5 compare 3 event resets counter" "0,1"
line.long 0x44 "ST3ACTL,HRTIMER Slave_TIME3 additional control register"
hexmask.long.byte 0x44 25.--31. 1. "DTFCFG,Falling edge dead-time value configure"
hexmask.long.byte 0x44 9.--15. 1. "DTRCFG,Rising edge dead-time value configure"
bitfld.long 0x44 1. "UPBST7,Update by Slave_TIMER7 update event" "0,1"
bitfld.long 0x44 0. "UPBST6,Update by Slave_TIMER6 update event" "0,1"
tree.end
tree "HRTIMER_SLAVE_TIMER4"
base ad:0x40015A80
group.long 0x0++0x3
line.long 0x0 "ST4CTL0,HRTIMER Slave_TIME4 control register 0"
hexmask.long.byte 0x0 28.--31. 1. "UPSEL,Update event selection"
bitfld.long 0x0 27. "SHWEN,Shadow registers enable" "0,1"
bitfld.long 0x0 25.--26. "DACTRGS,Trigger source to DAC" "0,1,2,3"
bitfld.long 0x0 24. "UPBMT,Update by Master_TIMER update event" "0,1"
bitfld.long 0x0 23. "UPBST4,Update by Slave_TIMER4 update event" "0,1"
bitfld.long 0x0 22. "UPBST3,Update by Slave_TIMER3 update event" "0,1"
newline
bitfld.long 0x0 21. "UPBST2,Update by Slave_TIMER2 update event" "0,1"
bitfld.long 0x0 20. "UPBST1,Update by Slave_TIMER1 update event" "0,1"
bitfld.long 0x0 19. "UPBST0,Update by Slave_TIMER0 update event" "0,1"
bitfld.long 0x0 18. "UPRST,Update event generated by reset event" "0,1"
bitfld.long 0x0 17. "UPREP,Update event generated by repetition event" "0,1"
bitfld.long 0x0 16. "UPBST5,Update by Slave_TIMER5 update event" "0,1"
newline
bitfld.long 0x0 14.--15. "DELCMP3M,Compare 3 delayed mode" "0,1,2,3"
bitfld.long 0x0 12.--13. "DELCMP1M,Compare 1 delayed mode" "0,1,2,3"
bitfld.long 0x0 11. "SYNISTRT,Synchronous input start timer" "0,1"
bitfld.long 0x0 10. "SYNIRST,Synchronous input reset timer" "0,1"
bitfld.long 0x0 9. "RSYNUPD,Re-synchronized update" "0,1"
bitfld.long 0x0 7.--8. "ALTM,Alternate mode" "0,1,2,3"
newline
bitfld.long 0x0 6. "BLNMEN,Balanced mode enable" "0,1"
bitfld.long 0x0 5. "HALFM,Half mode" "0,1"
bitfld.long 0x0 4. "CNTRSTM,Counter reset mode" "0,1"
bitfld.long 0x0 3. "CTNM,Continuous mode" "0,1"
bitfld.long 0x0 0.--2. "CNTCKDIV,Counter clock division" "0,1,2,3,4,5,6,7"
rgroup.long 0x4++0x3
line.long 0x0 "ST4INTF,HRTIMER Slave_TIME4 interrupt flag register"
bitfld.long 0x0 31. "DIR,Direction" "0,1"
bitfld.long 0x0 21. "CH1F,Channel 1 output flag" "0,1"
bitfld.long 0x0 20. "CH0F,Channel 0 output flag" "0,1"
bitfld.long 0x0 19. "CH1SF,Channel 1 output state flag" "0,1"
bitfld.long 0x0 18. "CH0SF,Channel 0 output state flag" "0,1"
bitfld.long 0x0 17. "BLNIF,Balanced IDLE flag" "0,1"
newline
bitfld.long 0x0 16. "CBLNF,Current balanced flag" "0,1"
bitfld.long 0x0 14. "DLYIIF,Delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x0 13. "RSTIF,Counter reset interrupt flag" "0,1"
bitfld.long 0x0 12. "CH1ONAIF,Channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x0 11. "CH1OAIF,Channel 1 output active interrupt flag" "0,1"
bitfld.long 0x0 10. "CH0ONAIF,Channel 0 output inactive interrupt flag" "0,1"
newline
bitfld.long 0x0 9. "CH0OAIF,Channel 0 output active interrupt flag" "0,1"
bitfld.long 0x0 8. "CAP1IF,Capture 1 interrupt flag" "0,1"
bitfld.long 0x0 7. "CAP0IF,Capture 0 interrupt flag" "0,1"
bitfld.long 0x0 6. "UPIF,Update interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIF,Repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IF,Compare 3 interrupt flag" "0,1"
newline
bitfld.long 0x0 2. "CMP2IF,Compare 2 interrupt flag" "0,1"
bitfld.long 0x0 1. "CMP1IF,Compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IF,Compare 0 interrupt flag" "0,1"
wgroup.long 0x8++0x3
line.long 0x0 "ST4INTC,HRTIMER Slave_TIME4 interrupt flag clear register"
bitfld.long 0x0 14. "DLYIIFC,Clear delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x0 13. "RSTIFC,Clear counter reset interrupt flag" "0,1"
bitfld.long 0x0 12. "CH1ONAIFC,Clear channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x0 11. "CH1OAIFC,Clear channel 1 output active interrupt flag" "0,1"
bitfld.long 0x0 10. "CH0ONAIFC,Clear channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x0 9. "CH0OAIFC,Clear channel 0 output active interrupt flag" "0,1"
newline
bitfld.long 0x0 8. "CAP1IFC,Clear capture 1 interrupt flag" "0,1"
bitfld.long 0x0 7. "CAP0IFC,Clear capture 0 interrupt flag" "0,1"
bitfld.long 0x0 6. "UPIFC,Clear update interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIFC,Clear repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IFC,Clear compare 3 interrupt flag" "0,1"
bitfld.long 0x0 2. "CMP2IFC,Clear compare 2 interrupt flag" "0,1"
newline
bitfld.long 0x0 1. "CMP1IFC,Clear compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IFC,Clear compare 0 interrupt flag" "0,1"
group.long 0xC++0x23
line.long 0x0 "ST4DMAINTEN,HRTIMER Slave_TIME4 DMA and interrupt enable register"
bitfld.long 0x0 30. "DLYIDEN,Delayed IDLE mode entry DMA request enable" "0,1"
bitfld.long 0x0 29. "RSTDEN,Counter reset DMA request enable" "0,1"
bitfld.long 0x0 28. "CH1ONADEN,Channel 1 output inactive DMA request enable" "0,1"
bitfld.long 0x0 27. "CH1OADEN,Channel 1 output active DMA request enable" "0,1"
bitfld.long 0x0 26. "CH0ONADEN,Channel 0 output inactive DMA request enable" "0,1"
bitfld.long 0x0 25. "CH0OADEN,Channel 0 output active DMA request enable" "0,1"
newline
bitfld.long 0x0 24. "CAP1DEN,Capture 1 DMA request enable" "0,1"
bitfld.long 0x0 23. "CAP0DEN,Capture 0 DMA request enable" "0,1"
bitfld.long 0x0 22. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x0 20. "REPDEN,Repetition DMA request enable" "0,1"
bitfld.long 0x0 19. "CMP3DEN,Compare 3 DMA request enable" "0,1"
bitfld.long 0x0 18. "CMP2DEN,Compare 2 DMA request enable" "0,1"
newline
bitfld.long 0x0 17. "CMP1DEN,Compare 1 DMA request enable" "0,1"
bitfld.long 0x0 16. "CMP0DEN,Compare 0 DMA request enable" "0,1"
bitfld.long 0x0 14. "DLYIIE,Delayed IDLE mode entry interrupt enable" "0,1"
bitfld.long 0x0 13. "RSTIE,Counter reset interrupt enable" "0,1"
bitfld.long 0x0 12. "CH1ONAIE,Channel 1 output inactive interrupt enable" "0,1"
bitfld.long 0x0 11. "CH1OAIE,Channel 1 output active interrupt enable" "0,1"
newline
bitfld.long 0x0 10. "CH0ONAIE,Channel 0 output inactive interrupt enable" "0,1"
bitfld.long 0x0 9. "CH0OAIE,Channel 0 output active interrupt enable" "0,1"
bitfld.long 0x0 8. "CAP1IE,Capture 1 interrupt enable" "0,1"
bitfld.long 0x0 7. "CAP0IE,Capture 0 interrupt enable" "0,1"
bitfld.long 0x0 6. "UPIE,Update interrupt enable" "0,1"
bitfld.long 0x0 4. "REPIE,Repetition interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "CMP3IE,Compare 3 interrupt enable" "0,1"
bitfld.long 0x0 2. "CMP2IE,Compare 2 interrupt enable" "0,1"
bitfld.long 0x0 1. "CMP1IE,Compare 1 interrupt enable" "0,1"
bitfld.long 0x0 0. "CMP0IE,Compare 0 interrupt enable" "0,1"
line.long 0x4 "ST4CNT,HRTIMER Slave_TIME4 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,The current counter value"
line.long 0x8 "ST4CAR,HRTIMER Slave_TIME4 counter auto reload register"
hexmask.long.word 0x8 0.--15. 1. "CARL,Counter auto reload value"
line.long 0xC "ST4CREP,HRTIMER Slave_TIME4 counter repetition register"
hexmask.long.byte 0xC 0.--7. 1. "CREP,Counter repetition value"
line.long 0x10 "ST4CMP0V,HRTIMER Slave_TIME4 compare 0 value register"
hexmask.long.word 0x10 0.--15. 1. "CMP0VAL,Compare 0 value"
line.long 0x14 "ST4CMP0CP,HRTIMER Slave_TIME4 compare 0 composite register"
hexmask.long.byte 0x14 16.--23. 1. "CREP,Counter repetition value"
hexmask.long.word 0x14 0.--15. 1. "CMP0VAL,Compare 0 value"
line.long 0x18 "ST4CMP1V,HRTIMER Slave_TIME4 compare 1 value register"
hexmask.long.word 0x18 0.--15. 1. "CMP1VAL,Compare 1 value"
line.long 0x1C "ST4CMP2V,HRTIMER Slave_TIME4 compare 2 value register"
hexmask.long.word 0x1C 0.--15. 1. "CMP2VAL,Compare 2 value"
line.long 0x20 "ST4CMP3V,HRTIMER Slave_TIME4 compare 3 value register"
hexmask.long.word 0x20 0.--15. 1. "CMP3VAL,Compare 3 value"
rgroup.long 0x30++0x7
line.long 0x0 "ST4CAP0V,HRTIMER Slave_TIME4 capture 0 value register"
bitfld.long 0x0 16. "DIR,Slave_timer 0 capture 1 direction status" "0,1"
hexmask.long.word 0x0 0.--15. 1. "CAP0VAL,Capture 0 value"
line.long 0x4 "ST4CAP1V,HRTIMER Slave_TIME4 capture 1 value register"
bitfld.long 0x4 16. "DIR,Slave_Timer 0 capture 1 direction status" "0,1"
hexmask.long.word 0x4 0.--15. 1. "CAP1VAL,Capture 1 value"
group.long 0x38++0x47
line.long 0x0 "ST4DTCTL,HRTIMER Slave_TIME4 dead-time control register"
bitfld.long 0x0 31. "DTFSVPROT,Dead-time falling edge protection for value and sign" "0,1"
bitfld.long 0x0 30. "DTFSPROT,Dead-time falling edge protection for sign" "0,1"
bitfld.long 0x0 25. "DTFS,The sign of falling edge dead-time value" "0,1"
hexmask.long.word 0x0 16.--24. 1. "DTFCFG,Falling edge dead-time value"
bitfld.long 0x0 15. "DTRSVPROT,Dead-time rising edge protection for value and sign" "0,1"
bitfld.long 0x0 14. "DTRSPROT,Dead-time rising edge protection for sign" "0,1"
newline
hexmask.long.byte 0x0 10.--13. 1. "DTGCKDIV,Dead time clock division"
bitfld.long 0x0 9. "DTRS,The sign of rising edge dead-time value" "0,1"
hexmask.long.word 0x0 0.--8. 1. "DTRCFG,Rising edge dead-time value"
line.long 0x4 "ST4CH0SET,HRTIMER Slave_TIME4 channel 0 set request register"
bitfld.long 0x4 31. "CH0SUP,Update event generates channel 0 set request" "0,1"
bitfld.long 0x4 30. "CH0SEXEV9,External event 9 generates channel 0 set request" "0,1"
bitfld.long 0x4 29. "CH0SEXEV8,External event 8 generates channel 0 set request" "0,1"
bitfld.long 0x4 28. "CH0SEXEV7,External event 7 generates channel 0 set request" "0,1"
bitfld.long 0x4 27. "CH0SEXEV6,External event 6 generates channel 0 set request" "0,1"
bitfld.long 0x4 26. "CH0SEXEV5,External event 5 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 25. "CH0SEXEV4,External event 4 generates channel 0 set request" "0,1"
bitfld.long 0x4 24. "CH0SEXEV3,External event 3 generates channel 0 set request" "0,1"
bitfld.long 0x4 23. "CH0SEXEV2,External event 2 generates channel 0 set request" "0,1"
bitfld.long 0x4 22. "CH0SEXEV1,External event 1 generates channel 0 set request" "0,1"
bitfld.long 0x4 21. "CH0SEXEV0,External event 0 generates channel 0 set request" "0,1"
bitfld.long 0x4 20. "CH0SSTEV8,interconnection event 8 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 19. "CH0SSTEV7,interconnection event 7 generates channel 0 set request" "0,1"
bitfld.long 0x4 18. "CH0SSTEV6,interconnection event 6 generates channel 0 set request" "0,1"
bitfld.long 0x4 17. "CH0SSTEV5,interconnection event 5 generates channel 0 set request" "0,1"
bitfld.long 0x4 16. "CH0SSTEV4,interconnection event 4 generates channel 0 set request" "0,1"
bitfld.long 0x4 15. "CH0SSTEV3,interconnection event 3 generates channel 0 set request" "0,1"
bitfld.long 0x4 14. "CH0SSTEV2,interconnection event 2 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 13. "CH0SSTEV1,interconnection event 1 generates channel 0 set request" "0,1"
bitfld.long 0x4 12. "CH0SSTEV0,interconnection event 0 generates channel 0 set request" "0,1"
bitfld.long 0x4 11. "CH0SMTCMP3,Master_TIMER compare 3 event generates channel 0 set request" "0,1"
bitfld.long 0x4 10. "CH0SMTCMP2,Master_TIMER compare 2 event generates channel 0 set request" "0,1"
bitfld.long 0x4 9. "CH0SMTCMP1,Master_TIMER compare 1 event generates channel 0 set request" "0,1"
bitfld.long 0x4 8. "CH0SMTCMP0,Master_TIMER compare 0 event generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 7. "CH0SMTPER,Master_TIMER period event generates channel 0 set request" "0,1"
bitfld.long 0x4 6. "CH0SCMP3,compare 3 event generates channel 0 set request" "0,1"
bitfld.long 0x4 5. "CH0SCMP2,compare 2 event generates channel 0 set request" "0,1"
bitfld.long 0x4 4. "CH0SCMP1,compare 1 event generates channel 0 set request" "0,1"
bitfld.long 0x4 3. "CH0SCMP0,compare 0 event generates channel 0 set request" "0,1"
bitfld.long 0x4 2. "CH0SPER,period event generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 1. "CH0SRST,reset event generates channel 0 set request" "0,1"
bitfld.long 0x4 0. "CH0SSEV,Software event generates channel 0 set request" "0,1"
line.long 0x8 "ST4CH0RST,HRTIMER Slave_TIME4 channel 0 reset request register"
bitfld.long 0x8 31. "CH0RSUP,Update event generates channel 0 reset request" "0,1"
bitfld.long 0x8 30. "CH0RSEXEV9,External event 9 generates channel 0 reset request" "0,1"
bitfld.long 0x8 29. "CH0RSEXEV8,External event 8 generates channel 0 reset request" "0,1"
bitfld.long 0x8 28. "CH0RSEXEV7,External event 7 generates channel 0 reset request" "0,1"
bitfld.long 0x8 27. "CH0RSEXEV6,External event 6 generates channel 0 reset request" "0,1"
bitfld.long 0x8 26. "CH0RSEXEV5,External event 5 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 25. "CH0RSEXEV4,External event 4 generates channel 0 reset request" "0,1"
bitfld.long 0x8 24. "CH0RSEXEV3,External event 3 generates channel 0 reset request" "0,1"
bitfld.long 0x8 23. "CH0RSEXEV2,External event 2 generates channel 0 reset request" "0,1"
bitfld.long 0x8 22. "CH0RSEXEV1,External event 1 generates channel 0 reset request" "0,1"
bitfld.long 0x8 21. "CH0RSEXEV0,External event 0 generates channel 0 reset request" "0,1"
bitfld.long 0x8 20. "CH0RSSTEV8,interconnection event 8 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 19. "CH0RSSTEV7,interconnection event 7 generates channel 0 reset request" "0,1"
bitfld.long 0x8 18. "CH0RSSTEV6,interconnection event 6 generates channel 0 reset request" "0,1"
bitfld.long 0x8 17. "CH0RSSTEV5,interconnection event 5 generates channel 0 reset request" "0,1"
bitfld.long 0x8 16. "CH0RSSTEV4,interconnection event 4 generates channel 0 reset request" "0,1"
bitfld.long 0x8 15. "CH0RSSTEV3,interconnection event 3 generates channel 0 reset request" "0,1"
bitfld.long 0x8 14. "CH0RSSTEV2,interconnection event 2 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 13. "CH0RSSTEV1,interconnection event 1 generates channel 0 reset request" "0,1"
bitfld.long 0x8 12. "CH0RSSTEV0,interconnection event 0 generates channel 0 reset request" "0,1"
bitfld.long 0x8 11. "CH0RSMTCMP3,Master_TIMER compare 3 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 10. "CH0RSMTCMP2,Master_TIMER compare 2 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 9. "CH0RSMTCMP1,Master_TIMER compare 1 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 8. "CH0RSMTCMP0,Master_TIMER compare 0 event generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 7. "CH0RSMTPER,Master_TIMER period event generates channel 0 reset request" "0,1"
bitfld.long 0x8 6. "CH0RSCMP3,compare 3 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 5. "CH0RSCMP2,compare 2 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 4. "CH0RSCMP1,compare 1 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 3. "CH0RSCMP0,compare 0 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 2. "CH0RSPER,period event generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 1. "CH0RSRST,reset event generates channel 0 reset request" "0,1"
bitfld.long 0x8 0. "CH0RSSEV,Software event generates channel 0 reset request" "0,1"
line.long 0xC "ST4CH1SET,HRTIMER Slave_TIME4 channel 1 set request register"
bitfld.long 0xC 31. "CH1SUP,Update event generates channel 1 set request" "0,1"
bitfld.long 0xC 30. "CH1SEXEV9,External event 9 generates channel 1 set request" "0,1"
bitfld.long 0xC 29. "CH1SEXEV8,External event 8 generates channel 1 set request" "0,1"
bitfld.long 0xC 28. "CH1SEXEV7,External event 7 generates channel 1 set request" "0,1"
bitfld.long 0xC 27. "CH1SEXEV6,External event 6 generates channel 1 set request" "0,1"
bitfld.long 0xC 26. "CH1SEXEV5,External event 5 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 25. "CH1SEXEV4,External event 4 generates channel 1 set request" "0,1"
bitfld.long 0xC 24. "CH1SEXEV3,External event 3 generates channel 1 set request" "0,1"
bitfld.long 0xC 23. "CH1SEXEV2,External event 2 generates channel 1 set request" "0,1"
bitfld.long 0xC 22. "CH1SEXEV1,External event 1 generates channel 1 set request" "0,1"
bitfld.long 0xC 21. "CH1SEXEV0,External event 0 generates channel 1 set request" "0,1"
bitfld.long 0xC 20. "CH1SSTEV8,interconnection event 8 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 19. "CH1SSTEV7,interconnection event 7 generates channel 1 set request" "0,1"
bitfld.long 0xC 18. "CH1SSTEV6,interconnection event 6 generates channel 1 set request" "0,1"
bitfld.long 0xC 17. "CH1SSTEV5,interconnection event 5 generates channel 1 set request" "0,1"
bitfld.long 0xC 16. "CH1SSTEV4,interconnection event 4 generates channel 1 set request" "0,1"
bitfld.long 0xC 15. "CH1SSTEV3,interconnection event 3 generates channel 1 set request" "0,1"
bitfld.long 0xC 14. "CH1SSTEV2,interconnection event 2 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 13. "CH1SSTEV1,interconnection event 1 generates channel 1 set request" "0,1"
bitfld.long 0xC 12. "CH1SSTEV0,interconnection event 0 generates channel 1 set request" "0,1"
bitfld.long 0xC 11. "CH1SMTCMP3,Master_TIMER compare 3 event generates channel 1 set request" "0,1"
bitfld.long 0xC 10. "CH1SMTCMP2,Master_TIMER compare 2 event generates channel 1 set request" "0,1"
bitfld.long 0xC 9. "CH1SMTCMP1,Master_TIMER compare 1 event generates channel 1 set request" "0,1"
bitfld.long 0xC 8. "CH1SMTCMP0,Master_TIMER compare 0 event generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 7. "CH1SMTPER,Master_TIMER period event generates channel 1 set request" "0,1"
bitfld.long 0xC 6. "CH1SCMP3,compare 3 event generates channel 1 set request" "0,1"
bitfld.long 0xC 5. "CH1SCMP2,compare 2 event generates channel 1 set request" "0,1"
bitfld.long 0xC 4. "CH1SCMP1,compare 1 event generates channel 1 set request" "0,1"
bitfld.long 0xC 3. "CH1SCMP0,compare 0 event generates channel 1 set request" "0,1"
bitfld.long 0xC 2. "CH1SPER,period event generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 1. "CH1SRST,reset event generates channel 1 set request" "0,1"
bitfld.long 0xC 0. "CH1SSEV,Software event generates channel 1 set request" "0,1"
line.long 0x10 "ST4CH1RST,HRTIMER Slave_TIME4 channel 1 reset request register"
bitfld.long 0x10 31. "CH1RSUP,Update event generates channel 1 reset request" "0,1"
bitfld.long 0x10 30. "CH1RSEXEV9,External event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x10 29. "CH1RSEXEV8,External event 8 generates channel 1 reset request" "0,1"
bitfld.long 0x10 28. "CH1RSEXEV7,External event 7 generates channel 1 reset request" "0,1"
bitfld.long 0x10 27. "CH1RSEXEV6,External event 6 generates channel 1 reset request" "0,1"
bitfld.long 0x10 26. "CH1RSEXEV5,External event 5 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 25. "CH1RSEXEV4,External event 4 generates channel 1 reset request" "0,1"
bitfld.long 0x10 24. "CH1RSEXEV3,External event 3 generates channel 1 reset request" "0,1"
bitfld.long 0x10 23. "CH1RSEXEV2,External event 2 generates channel 1 reset request" "0,1"
bitfld.long 0x10 22. "CH1RSEXEV1,External event 1 generates channel 1 reset request" "0,1"
bitfld.long 0x10 21. "CH1RSEXEV0,External event 0 generates channel 1 reset request" "0,1"
bitfld.long 0x10 20. "CH1RSSTEV8,interconnection event 8 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 19. "CH1RSSTEV7,interconnection event 7 generates channel 1 reset request" "0,1"
bitfld.long 0x10 18. "CH1RSSTEV6,interconnection event 6 generates channel 1 reset request" "0,1"
bitfld.long 0x10 17. "CH1RSSTEV5,interconnection event 5 generates channel 1 reset request" "0,1"
bitfld.long 0x10 16. "CH1RSSTEV4,interconnection event 4 generates channel 1 reset request" "0,1"
bitfld.long 0x10 15. "CH1RSSTEV3,interconnection event 3 generates channel 1 reset request" "0,1"
bitfld.long 0x10 14. "CH1RSSTEV2,interconnection event 2 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 13. "CH1RSSTEV1,interconnection event 1 generates channel 1 reset request" "0,1"
bitfld.long 0x10 12. "CH1RSSTEV0,interconnection event 0 generates channel 1 reset request" "0,1"
bitfld.long 0x10 11. "CH1RSMTCMP3,Master_TIMER compare 3 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 10. "CH1RSMTCMP2,Master_TIMER compare 2 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 9. "CH1RSMTCMP1,Master_TIMER compare 1 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 8. "CH1RSMTCMP0,Master_TIMER compare 0 event generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 7. "CH1RSMTPER,Master_TIMER period event generates channel 1 reset request" "0,1"
bitfld.long 0x10 6. "CH1RSCMP3,compare 3 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 5. "CH1RSCMP2,compare 2 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 4. "CH1RSCMP1,compare 1 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 3. "CH1RSCMP0,compare 0 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 2. "CH1RSPER,period event generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 1. "CH1RSRST,reset event generates channel 1 reset request" "0,1"
bitfld.long 0x10 0. "CH1RSSEV,Software event generates channel 1 reset request" "0,1"
line.long 0x14 "ST4EXEVFCFG0,HRTIMER Slave_TIME4 external event filter configuration register 0"
hexmask.long.byte 0x14 25.--29. 1. "EXEV4FM,External event 4 filter mode"
bitfld.long 0x14 24. "EXEV4MEEN,External event 4 memorized enable" "0,1"
hexmask.long.byte 0x14 19.--23. 1. "EXEV3FM,External event 3 filter mode"
bitfld.long 0x14 18. "EXEV3MEEN,External event 3 memorized enable" "0,1"
hexmask.long.byte 0x14 13.--17. 1. "EXEV2FM,External event 2 filter mode"
bitfld.long 0x14 12. "EXEV2MEEN,External event 2 memorized enable" "0,1"
newline
hexmask.long.byte 0x14 7.--11. 1. "EXEV1FM,External event 1 filter mode"
bitfld.long 0x14 6. "EXEV1MEEN,External event 1 memorized enable" "0,1"
hexmask.long.byte 0x14 1.--5. 1. "EXEV0FM,External event 0 filter mode"
bitfld.long 0x14 0. "EXEV0MEEN,External event 0 memory" "0,1"
line.long 0x18 "ST4EXEVFCFG1,HRTIMER Slave_TIME4 external event filter configuration register 1"
hexmask.long.byte 0x18 25.--29. 1. "EXEV9FM,External event 9 filter mode"
bitfld.long 0x18 24. "EXEV9MEEN,External event 9 memorized enable" "0,1"
hexmask.long.byte 0x18 19.--23. 1. "EXEV8FM,External event 8 filter mode"
bitfld.long 0x18 18. "EXEV8MEEN,External event 8 memorized enable" "0,1"
hexmask.long.byte 0x18 13.--17. 1. "EXEV7FM,External event 7 filter mode"
bitfld.long 0x18 12. "EXEV7MEEN,External event 7 memorized enable" "0,1"
newline
hexmask.long.byte 0x18 7.--11. 1. "EXEV6FM,External event 6 filter mode"
bitfld.long 0x18 6. "EXEV6MEEN,External event 6 memorized enable" "0,1"
hexmask.long.byte 0x18 1.--5. 1. "EXEV5FM,External event 5 filter mode"
bitfld.long 0x18 0. "EXEV5MEEN,External event 0 memorized enable" "0,1"
line.long 0x1C "ST4CNTRST,HRTIMER Slave_TIMER4 counter reset register"
bitfld.long 0x1C 31. "ST5CMP1RST,Slave_TIMER5 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 30. "ST3CMP3RST,Slave_TIMER3 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 29. "ST3CMP1RST,Slave_TIMER3 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 28. "ST3CMP0RST,Slave_TIMER3 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 27. "ST2CMP3RST,Slave_TIMER2 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 26. "ST2CMP1RST,Slave_TIMER2 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x1C 25. "ST2CMP0RST,Slave_TIMER2 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 24. "ST1CMP3RST,Slave_TIMER1 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 23. "ST1CMP1RST,Slave_TIMER1 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 22. "ST1CMP0RST,Slave_TIMER1 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 21. "ST0CMP3RST,Slave_TIMER0 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 20. "ST0CMP1RST,Slave_TIMER0 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x1C 19. "ST0CMP0RST,Slave_TIMER0 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 18. "EXEV9RST,External event 9 resets counter" "0,1"
bitfld.long 0x1C 17. "EXEV8RST,External event 8 resets counter" "0,1"
bitfld.long 0x1C 16. "EXEV7RST,External event 7 resets counter" "0,1"
bitfld.long 0x1C 15. "EXEV6RST,External event 6 resets counter" "0,1"
bitfld.long 0x1C 14. "EXEV5RST,External event 5 resets counter" "0,1"
newline
bitfld.long 0x1C 13. "EXEV4RST,External event 4 resets counter" "0,1"
bitfld.long 0x1C 12. "EXEV3RST,External event 3 resets counter" "0,1"
bitfld.long 0x1C 11. "EXEV2RST,External event 2 resets counter" "0,1"
bitfld.long 0x1C 10. "EXEV1RST,External event 1 resets counter" "0,1"
bitfld.long 0x1C 9. "EXEV0RST,External event 0 resets counter" "0,1"
bitfld.long 0x1C 8. "MTCMP3RST,Master_TIMER compare 3 event resets counter" "0,1"
newline
bitfld.long 0x1C 7. "MTCMP2RST,Master_TIMER compare 2 event resets counter" "0,1"
bitfld.long 0x1C 6. "MTCMP1RST,Master_TIMER compare 1 event resets counter" "0,1"
bitfld.long 0x1C 5. "MTCMP0RST,Master_TIMER compare 0 event resets counter" "0,1"
bitfld.long 0x1C 4. "MTPERRST,Master_TIMER period event resets counter" "0,1"
bitfld.long 0x1C 3. "CMP3RST,Slave_TIMER4 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 2. "CMP1RST,Slave_TIMER4 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x1C 1. "UPRST,Slave_TIMER4 update event resets counter" "0,1"
bitfld.long 0x1C 0. "ST5CMP0RST,Slave_TIMER5 compare 0 event resets counter" "0,1"
line.long 0x20 "ST4CSCTL,HRTIMER Slave_TIME4 carrier-signal control register"
hexmask.long.byte 0x20 7.--10. 1. "CSFSTPW,First carrier-signal pulse width"
bitfld.long 0x20 4.--6. "CSDTY,Carrier signal duty cycle" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x20 0.--3. 1. "CSPRD,Carrier signal period"
line.long 0x24 "ST4CAP0TRG,HRTIMER Slave_TIMER4 capture 0 trigger register"
bitfld.long 0x24 27. "CP0BST3CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x24 26. "CP0BST3CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x24 25. "CP0BST3NA,Capture 0 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 24. "CP0BST3A,Capture 0 triggered by ST3CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 23. "CP0BST2CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x24 22. "CP0BST2CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER2" "0,1"
newline
bitfld.long 0x24 21. "CP0BST2NA,Capture 0 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 20. "CP0BST2A,Capture 0 triggered by ST2CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 19. "CP0BST1CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x24 18. "CP0BST1CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x24 17. "CP0BST1NA,Capture 0 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 16. "CP0BST1A,Capture 0 triggered by ST1CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x24 15. "CP0BST0CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x24 14. "CP0BST0CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x24 13. "CP0BST0NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 12. "CP0BST0A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
bitfld.long 0x24 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
newline
bitfld.long 0x24 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x24 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
bitfld.long 0x24 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x24 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x24 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x24 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x24 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x24 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x24 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x24 0. "CP0BSW,Capture 0 triggered by software" "0,1"
line.long 0x28 "ST4CAP1TRG,HRTIMER Slave_TIMER4 capture 1 trigger register"
bitfld.long 0x28 27. "CP1BST3CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x28 26. "CP1BST3CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x28 25. "CP1BST3NA,Capture 1 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 24. "CP1BST3A,Capture 1 triggered by ST3CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 23. "CP1BST2CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x28 22. "CP1BST2CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER2" "0,1"
newline
bitfld.long 0x28 21. "CP1BST2NA,Capture 1 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 20. "CP1BST2A,Capture 1 triggered by ST2CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 19. "CP1BST1CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x28 18. "CP1BST1CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x28 17. "CP1BST1NA,Capture 1 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 16. "CP1BST1A,Capture 1 triggered by ST1CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x28 15. "CP1BST0CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x28 14. "CP1BST0CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x28 13. "CP1BST0NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 12. "CP1BST0A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
bitfld.long 0x28 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
newline
bitfld.long 0x28 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
bitfld.long 0x28 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
bitfld.long 0x28 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x28 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x28 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x28 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
newline
bitfld.long 0x28 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
bitfld.long 0x28 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x28 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x28 0. "CP1BSW,Capture 1 triggered by software" "0,1"
line.long 0x2C "ST4CHOCTL,HRTIMER Slave_TIME4 channel output control register"
bitfld.long 0x2C 23. "BMCH1DTI,Channel 1 dead-time insert in bunch mode" "0,1"
bitfld.long 0x2C 22. "CH1CSEN,Channel 1 carrier-signal mode enable" "0,1"
bitfld.long 0x2C 20.--21. "CH1FLTOS,Channel 1 Fault output state" "0,1,2,3"
bitfld.long 0x2C 19. "ISO1,channel 1 output idle state" "0,1"
bitfld.long 0x2C 18. "BMCH1IEN,Channel 1 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x2C 17. "CH1P,Channel 1 output polarity" "0,1"
newline
bitfld.long 0x2C 14. "BALIAR,Balanced Idle Automatic Resumption" "0,1"
bitfld.long 0x2C 10.--12. "DLYISCH,Delayed IDLE source and channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x2C 9. "DLYISMEN,Delayed IDLE state mode enable" "0,1"
bitfld.long 0x2C 8. "DTEN,Dead time enable" "0,1"
bitfld.long 0x2C 7. "BMCH0DTI,Channel 0 dead-time insert in bunch mode" "0,1"
bitfld.long 0x2C 6. "CH0CSEN,Channel 0 carrier-signal mode enable" "0,1"
newline
bitfld.long 0x2C 4.--5. "CH0FLTOS,Channel 0 Fault output state" "0,1,2,3"
bitfld.long 0x2C 3. "ISO0,Channel 0 output idle state" "0,1"
bitfld.long 0x2C 2. "BMCH0IEN,Channel 0 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x2C 1. "CH0P,Channel 0 output polarity" "0,1"
line.long 0x30 "ST4FLTCTL,HRTIMER Slave_TIME4 fault control register"
bitfld.long 0x30 31. "FLTENPROT,Protect fault enable" "0,1"
bitfld.long 0x30 7. "FLT7EN,Fault 7 enable" "0,1"
bitfld.long 0x30 6. "FLT6EN,Fault 6 enable" "0,1"
bitfld.long 0x30 5. "FLT5EN,Fault 5 enable" "0,1"
bitfld.long 0x30 4. "FLT4EN,Fault 4 enable" "0,1"
bitfld.long 0x30 3. "FLT3EN,Fault 3 enable" "0,1"
newline
bitfld.long 0x30 2. "FLT2EN,Fault 2 enable" "0,1"
bitfld.long 0x30 1. "FLT1EN,Fault 1 enable" "0,1"
bitfld.long 0x30 0. "FLT0EN,Fault 0 enable" "0,1"
line.long 0x34 "ST4CTL1,HRTIMER Slave_TIME4 control register 1"
bitfld.long 0x34 20. "TRGHALFM,Triggered-half mode" "0,1"
bitfld.long 0x34 17. "IMUPD2V,Immediately update compare 2 value PWM mode" "0,1"
bitfld.long 0x34 16. "IMUPD0V,Immediately update compare 0 value PWM mode" "0,1"
bitfld.long 0x34 14.--15. "FEROVM,Fault and event roll-over mode" "0,1,2,3"
bitfld.long 0x34 12.--13. "BMROVM,Bunch mode roll-over mode" "0,1,2,3"
bitfld.long 0x34 10.--11. "ADCROVM,ADC roll-over mode" "0,1,2,3"
newline
bitfld.long 0x34 8.--9. "OUTROVM,Output roll-over mode" "0,1,2,3"
bitfld.long 0x34 6.--7. "ROVM,Roll-over mode" "0,1,2,3"
bitfld.long 0x34 4. "CAM,Center-aligned counting mode" "0,1"
bitfld.long 0x34 2. "TRIG1M,This bit defines when TRIG1M is generated" "0,1"
bitfld.long 0x34 1. "TRIG0M,This bit defines when TRIG0M is generated" "0,1"
bitfld.long 0x34 0. "TRIGEN,Two trigger enable" "0,1"
line.long 0x38 "ST4EXEVFCFG2,HRTIMER Slave_TIME4 external event filter configuration register 2"
hexmask.long.byte 0x38 26.--31. 1. "EXEVXCNT,External event X counter value"
hexmask.long.byte 0x38 8.--13. 1. "EXEVXCNTTHR,External event X counter threshold"
hexmask.long.byte 0x38 4.--7. 1. "EXEVXSEL,External event X selection This bit determines the source of external event X"
bitfld.long 0x38 2. "EXEVXRSTM,External event X reset mode" "0,1"
bitfld.long 0x38 1. "EXEVXCRST,External event X counter reset" "0,1"
bitfld.long 0x38 0. "EXEVXCEN,External event X counter enable" "0,1"
line.long 0x3C "ST4CAPTRGCOM,HRTIMER Slave_TIMER4 capture trigger combination register"
bitfld.long 0x3C 27. "CP1BST7CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 26. "CP1BST7CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 25. "CP1BST7NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 24. "CP1BST7A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 23. "CP1BST6CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER6" "0,1"
bitfld.long 0x3C 22. "CP1BST6CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER6" "0,1"
newline
bitfld.long 0x3C 21. "CP1BST6NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 20. "CP1BST6A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 19. "CP1BST5CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 18. "CP1BST5CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 17. "CP1BST5NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 16. "CP1BST5A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x3C 11. "CP0BST7CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 10. "CP0BST7CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 9. "CP0BST7NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 8. "CP0BST7A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 7. "CP0BST6CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER6" "0,1"
bitfld.long 0x3C 6. "CP0BST6CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER6" "0,1"
newline
bitfld.long 0x3C 5. "CP0BST6NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 4. "CP0BST6A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 3. "CP0BST5CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 2. "CP0BST5CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 1. "CP0BST5NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 0. "CP0BST5A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
line.long 0x40 "ST4CNTRSTA,HRTIMER Slave_TIMER4 counter reset and channel 0/1 set/reset request add register"
bitfld.long 0x40 29. "CH1RSSTCNTRST,Slave_TIMER4 counter reset generates channel 1 reset request" "0,1"
bitfld.long 0x40 28. "CH0RSSTCNTRST,Slave_TIMER4 counter reset generates channel 0 reset request" "0,1"
bitfld.long 0x40 27. "CH1RSSTEV10,Slave_TIMER4 interconnection event 10 generates channel 1 reset request" "0,1"
bitfld.long 0x40 26. "CH1RSSTEV9,Slave_TIMER4 interconnection event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x40 25. "CH0RSSTEV10,Slave_TIMER4 interconnection event 10 generates channel 0 reset request" "0,1"
bitfld.long 0x40 24. "CH0RSSTEV9,Slave_TIMER4 interconnection event 9 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x40 21. "CH1SSTCNTRST,Slave_TIMER4 counter reset generates channel 1 reset request" "0,1"
bitfld.long 0x40 20. "CH0SSTCNTRST,Slave_TIMER4 counter reset generates channel 0 reset request" "0,1"
bitfld.long 0x40 19. "CH1SSTEV10,Slave_TIMER4 interconnection event 10 generates channel 1 reset request" "0,1"
bitfld.long 0x40 18. "CH1SSTEV9,Slave_TIMER4 interconnection event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x40 17. "CH0SSTEV10,Slave_TIMER4 interconnection event 10 generates channel 0 set request" "0,1"
bitfld.long 0x40 16. "CH0SSTEV9,Slave_TIMER4 interconnection event 9 generates channel 1 set request" "0,1"
newline
bitfld.long 0x40 6. "ST7CMP3RST,Slave_TIMER7 compare 3 event resets counter" "0,1"
bitfld.long 0x40 5. "ST7CMP1RST,Slave_TIMER7 compare 1 event resets counter" "0,1"
bitfld.long 0x40 4. "ST7CMP0RST,Slave_TIMER7 compare 0 event resets counter" "0,1"
bitfld.long 0x40 3. "ST6CMP3RST,Slave_TIMER6 compare 3 event resets counter" "0,1"
bitfld.long 0x40 2. "ST6CMP1RST,Slave_TIMER6 compare 1 event resets counter" "0,1"
bitfld.long 0x40 1. "ST6CMP0RST,Slave_TIMER6 compare 0 event resets counter" "0,1"
newline
bitfld.long 0x40 0. "ST5CMP3RST,Slave_TIMER5 compare 3 event resets counter" "0,1"
line.long 0x44 "ST4ACTL,HRTIMER Slave_TIME4 additional control register"
hexmask.long.byte 0x44 25.--31. 1. "DTFCFG,Falling edge dead-time value configure"
hexmask.long.byte 0x44 9.--15. 1. "DTRCFG,Rising edge dead-time value configure"
bitfld.long 0x44 1. "UPBST7,Update by Slave_TIMER7 update event" "0,1"
bitfld.long 0x44 0. "UPBST6,Update by Slave_TIMER6 update event" "0,1"
tree.end
tree "HRTIMER_SLAVE_TIMER5"
base ad:0x40015B00
group.long 0x0++0x3
line.long 0x0 "ST5CTL0,HRTIMER Slave_TIME5 control register 0"
hexmask.long.byte 0x0 28.--31. 1. "UPSEL,Update event selection"
bitfld.long 0x0 27. "SHWEN,Shadow registers enable" "0,1"
bitfld.long 0x0 25.--26. "DACTRGS,Trigger source to DAC" "0,1,2,3"
bitfld.long 0x0 24. "UPBMT,Update by Master_TIMER update event" "0,1"
bitfld.long 0x0 23. "UPBST4,Update by Slave_TIMER4 update event" "0,1"
bitfld.long 0x0 22. "UPBST3,Update by Slave_TIMER3 update event" "0,1"
bitfld.long 0x0 21. "UPBST2,Update by Slave_TIMER2 update event" "0,1"
newline
bitfld.long 0x0 20. "UPBST1,Update by Slave_TIMER1 update event" "0,1"
bitfld.long 0x0 19. "UPBST0,Update by Slave_TIMER0 update event" "0,1"
bitfld.long 0x0 18. "UPRST,Update event generated by reset event" "0,1"
bitfld.long 0x0 17. "UPREP,Update event generated by repetition event" "0,1"
bitfld.long 0x0 16. "UPBST5,Update by Slave_TIMER5 update event" "0,1"
bitfld.long 0x0 14.--15. "DELCMP3M,Compare 3 delayed mode" "0,1,2,3"
bitfld.long 0x0 12.--13. "DELCMP1M,Compare 1 delayed mode" "0,1,2,3"
newline
bitfld.long 0x0 11. "SYNISTRT,Synchronous input start timer" "0,1"
bitfld.long 0x0 10. "SYNIRST,Synchronous input reset timer" "0,1"
bitfld.long 0x0 9. "RSYNUPD,Re-synchronized update" "0,1"
bitfld.long 0x0 7.--8. "ALTM,Alternate mode" "0,1,2,3"
bitfld.long 0x0 6. "BLNMEN,Balanced mode enable" "0,1"
bitfld.long 0x0 5. "HALFM,Half mode" "0,1"
bitfld.long 0x0 4. "CNTRSTM,Counter reset mode" "0,1"
newline
bitfld.long 0x0 3. "CTNM,Continuous mode" "0,1"
bitfld.long 0x0 0.--2. "CNTCKDIV,Counter clock division" "0,1,2,3,4,5,6,7"
rgroup.long 0x4++0x3
line.long 0x0 "ST5INTF,HRTIMER Slave_TIME5 interrupt flag register"
bitfld.long 0x0 31. "DIR,Direction" "0,1"
bitfld.long 0x0 21. "CH1F,Channel 1 output flag" "0,1"
bitfld.long 0x0 20. "CH0F,Channel 0 output flag" "0,1"
bitfld.long 0x0 19. "CH1SF,Channel 1 output state flag" "0,1"
bitfld.long 0x0 18. "CH0SF,Channel 0 output state flag" "0,1"
bitfld.long 0x0 17. "BLNIF,Balanced IDLE flag" "0,1"
bitfld.long 0x0 16. "CBLNF,Current balanced flag" "0,1"
newline
bitfld.long 0x0 14. "DLYIIF,Delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x0 13. "RSTIF,Counter reset interrupt flag" "0,1"
bitfld.long 0x0 12. "CH1ONAIF,Channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x0 11. "CH1OAIF,Channel 1 output active interrupt flag" "0,1"
bitfld.long 0x0 10. "CH0ONAIF,Channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x0 9. "CH0OAIF,Channel 0 output active interrupt flag" "0,1"
bitfld.long 0x0 8. "CAP1IF,Capture 1 interrupt flag" "0,1"
newline
bitfld.long 0x0 7. "CAP0IF,Capture 0 interrupt flag" "0,1"
bitfld.long 0x0 6. "UPIF,Update interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIF,Repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IF,Compare 3 interrupt flag" "0,1"
bitfld.long 0x0 2. "CMP2IF,Compare 2 interrupt flag" "0,1"
bitfld.long 0x0 1. "CMP1IF,Compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IF,Compare 0 interrupt flag" "0,1"
wgroup.long 0x8++0x3
line.long 0x0 "ST5INTC,HRTIMER Slave_TIME5 interrupt flag clear register"
bitfld.long 0x0 14. "DLYIIFC,Clear delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x0 13. "RSTIFC,Clear counter reset interrupt flag" "0,1"
bitfld.long 0x0 12. "CH1ONAIFC,Clear channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x0 11. "CH1OAIFC,Clear channel 1 output active interrupt flag" "0,1"
bitfld.long 0x0 10. "CH0ONAIFC,Clear channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x0 9. "CH0OAIFC,Clear channel 0 output active interrupt flag" "0,1"
bitfld.long 0x0 8. "CAP1IFC,Clear capture 1 interrupt flag" "0,1"
newline
bitfld.long 0x0 7. "CAP0IFC,Clear capture 0 interrupt flag" "0,1"
bitfld.long 0x0 6. "UPIFC,Clear update interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIFC,Clear repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IFC,Clear compare 3 interrupt flag" "0,1"
bitfld.long 0x0 2. "CMP2IFC,Clear compare 2 interrupt flag" "0,1"
bitfld.long 0x0 1. "CMP1IFC,Clear compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IFC,Clear compare 0 interrupt flag" "0,1"
group.long 0xC++0x23
line.long 0x0 "ST5DMAINTEN,HRTIMER Slave_TIME5 DMA and interrupt enable register"
bitfld.long 0x0 30. "DLYIDEN,Delayed IDLE mode entry DMA request enable" "0,1"
bitfld.long 0x0 29. "RSTDEN,Counter reset DMA request enable" "0,1"
bitfld.long 0x0 28. "CH1ONADEN,Channel 1 output inactive DMA request enable" "0,1"
bitfld.long 0x0 27. "CH1OADEN,Channel 1 output active DMA request enable" "0,1"
bitfld.long 0x0 26. "CH0ONADEN,Channel 0 output inactive DMA request enable" "0,1"
bitfld.long 0x0 25. "CH0OADEN,Channel 0 output active DMA request enable" "0,1"
bitfld.long 0x0 24. "CAP1DEN,Capture 1 DMA request enable" "0,1"
newline
bitfld.long 0x0 23. "CAP0DEN,Capture 0 DMA request enable" "0,1"
bitfld.long 0x0 22. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x0 20. "REPDEN,Repetition DMA request enable" "0,1"
bitfld.long 0x0 19. "CMP3DEN,Compare 3 DMA request enable" "0,1"
bitfld.long 0x0 18. "CMP2DEN,Compare 2 DMA request enable" "0,1"
bitfld.long 0x0 17. "CMP1DEN,Compare 1 DMA request enable" "0,1"
bitfld.long 0x0 16. "CMP0DEN,Compare 0 DMA request enable" "0,1"
newline
bitfld.long 0x0 14. "DLYIIE,Delayed IDLE mode entry interrupt enable" "0,1"
bitfld.long 0x0 13. "RSTIE,Counter reset interrupt enable" "0,1"
bitfld.long 0x0 12. "CH1ONAIE,Channel 1 output inactive interrupt enable" "0,1"
bitfld.long 0x0 11. "CH1OAIE,Channel 1 output active interrupt enable" "0,1"
bitfld.long 0x0 10. "CH0ONAIE,Channel 0 output inactive interrupt enable" "0,1"
bitfld.long 0x0 9. "CH0OAIE,Channel 0 output active interrupt enable" "0,1"
bitfld.long 0x0 8. "CAP1IE,Capture 1 interrupt enable" "0,1"
newline
bitfld.long 0x0 7. "CAP0IE,Capture 0 interrupt enable" "0,1"
bitfld.long 0x0 6. "UPIE,Update interrupt enable" "0,1"
bitfld.long 0x0 4. "REPIE,Repetition interrupt enable" "0,1"
bitfld.long 0x0 3. "CMP3IE,Compare 3 interrupt enable" "0,1"
bitfld.long 0x0 2. "CMP2IE,Compare 2 interrupt enable" "0,1"
bitfld.long 0x0 1. "CMP1IE,Compare 1 interrupt enable" "0,1"
bitfld.long 0x0 0. "CMP0IE,Compare 0 interrupt enable" "0,1"
line.long 0x4 "ST5CNT,HRTIMER Slave_TIME5 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,The current counter value"
line.long 0x8 "ST5CAR,HRTIMER Slave_TIME5 counter auto reload register"
hexmask.long.word 0x8 0.--15. 1. "CARL,Counter auto reload value"
line.long 0xC "ST5CREP,HRTIMER Slave_TIME5 counter repetition register"
hexmask.long.byte 0xC 0.--7. 1. "CREP,Counter repetition value"
line.long 0x10 "ST5CMP0V,HRTIMER Slave_TIME5 compare 0 value register"
hexmask.long.word 0x10 0.--15. 1. "CMP0VAL,Compare 0 value"
line.long 0x14 "ST5CMP0CP,HRTIMER Slave_TIME5 compare 0 composite register"
hexmask.long.byte 0x14 16.--23. 1. "CREP,Counter repetition value"
hexmask.long.word 0x14 0.--15. 1. "CMP0VAL,Compare 0 value"
line.long 0x18 "ST5CMP1V,HRTIMER Slave_TIME5 compare 1 value register"
hexmask.long.word 0x18 0.--15. 1. "CMP1VAL,Compare 1 value"
line.long 0x1C "ST5CMP2V,HRTIMER Slave_TIME5 compare 2 value register"
hexmask.long.word 0x1C 0.--15. 1. "CMP2VAL,Compare 2 value"
line.long 0x20 "ST5CMP3V,HRTIMER Slave_TIME5 compare 3 value register"
hexmask.long.word 0x20 0.--15. 1. "CMP3VAL,Compare 3 value"
rgroup.long 0x30++0x7
line.long 0x0 "ST5CAP0V,HRTIMER Slave_TIME5 capture 0 value register"
bitfld.long 0x0 16. "DIR,Slave_timer 0 capture 1 direction status" "0,1"
hexmask.long.word 0x0 0.--15. 1. "CAP0VAL,Capture 0 value"
line.long 0x4 "ST5CAP1V,HRTIMER Slave_TIME5 capture 1 value register"
bitfld.long 0x4 16. "DIR,Slave_Timer 0 capture 1 direction status" "0,1"
hexmask.long.word 0x4 0.--15. 1. "CAP1VAL,Capture 1 value"
group.long 0x38++0x47
line.long 0x0 "ST5DTCTL,HRTIMER Slave_TIME5 dead-time control register"
bitfld.long 0x0 31. "DTFSVPROT,Dead-time falling edge protection for value and sign" "0,1"
bitfld.long 0x0 30. "DTFSPROT,Dead-time falling edge protection for sign" "0,1"
bitfld.long 0x0 25. "DTFS,The sign of falling edge dead-time value" "0,1"
hexmask.long.word 0x0 16.--24. 1. "DTFCFG,Falling edge dead-time value"
bitfld.long 0x0 15. "DTRSVPROT,Dead-time rising edge protection for value and sign" "0,1"
bitfld.long 0x0 14. "DTRSPROT,Dead-time rising edge protection for sign" "0,1"
hexmask.long.byte 0x0 10.--13. 1. "DTGCKDIV,Dead time clock division"
newline
bitfld.long 0x0 9. "DTRS,The sign of rising edge dead-time value" "0,1"
hexmask.long.word 0x0 0.--8. 1. "DTRCFG,Rising edge dead-time value"
line.long 0x4 "ST5CH0SET,HRTIMER Slave_TIME5 channel 0 set request register"
bitfld.long 0x4 31. "CH0SUP,Update event generates channel 0 set request" "0,1"
bitfld.long 0x4 30. "CH0SEXEV9,External event 9 generates channel 0 set request" "0,1"
bitfld.long 0x4 29. "CH0SEXEV8,External event 8 generates channel 0 set request" "0,1"
bitfld.long 0x4 28. "CH0SEXEV7,External event 7 generates channel 0 set request" "0,1"
bitfld.long 0x4 27. "CH0SEXEV6,External event 6 generates channel 0 set request" "0,1"
bitfld.long 0x4 26. "CH0SEXEV5,External event 5 generates channel 0 set request" "0,1"
bitfld.long 0x4 25. "CH0SEXEV4,External event 4 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 24. "CH0SEXEV3,External event 3 generates channel 0 set request" "0,1"
bitfld.long 0x4 23. "CH0SEXEV2,External event 2 generates channel 0 set request" "0,1"
bitfld.long 0x4 22. "CH0SEXEV1,External event 1 generates channel 0 set request" "0,1"
bitfld.long 0x4 21. "CH0SEXEV0,External event 0 generates channel 0 set request" "0,1"
bitfld.long 0x4 20. "CH0SSTEV8,interconnection event 8 generates channel 0 set request" "0,1"
bitfld.long 0x4 19. "CH0SSTEV7,interconnection event 7 generates channel 0 set request" "0,1"
bitfld.long 0x4 18. "CH0SSTEV6,interconnection event 6 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 17. "CH0SSTEV5,interconnection event 5 generates channel 0 set request" "0,1"
bitfld.long 0x4 16. "CH0SSTEV4,interconnection event 4 generates channel 0 set request" "0,1"
bitfld.long 0x4 15. "CH0SSTEV3,interconnection event 3 generates channel 0 set request" "0,1"
bitfld.long 0x4 14. "CH0SSTEV2,interconnection event 2 generates channel 0 set request" "0,1"
bitfld.long 0x4 13. "CH0SSTEV1,interconnection event 1 generates channel 0 set request" "0,1"
bitfld.long 0x4 12. "CH0SSTEV0,interconnection event 0 generates channel 0 set request" "0,1"
bitfld.long 0x4 11. "CH0SMTCMP3,Master_TIMER compare 3 event generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 10. "CH0SMTCMP2,Master_TIMER compare 2 event generates channel 0 set request" "0,1"
bitfld.long 0x4 9. "CH0SMTCMP1,Master_TIMER compare 1 event generates channel 0 set request" "0,1"
bitfld.long 0x4 8. "CH0SMTCMP0,Master_TIMER compare 0 event generates channel 0 set request" "0,1"
bitfld.long 0x4 7. "CH0SMTPER,Master_TIMER period event generates channel 0 set request" "0,1"
bitfld.long 0x4 6. "CH0SCMP3,compare 3 event generates channel 0 set request" "0,1"
bitfld.long 0x4 5. "CH0SCMP2,compare 2 event generates channel 0 set request" "0,1"
bitfld.long 0x4 4. "CH0SCMP1,compare 1 event generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 3. "CH0SCMP0,compare 0 event generates channel 0 set request" "0,1"
bitfld.long 0x4 2. "CH0SPER,period event generates channel 0 set request" "0,1"
bitfld.long 0x4 1. "CH0SRST,reset event generates channel 0 set request" "0,1"
bitfld.long 0x4 0. "CH0SSEV,Software event generates channel 0 set request" "0,1"
line.long 0x8 "ST5CH0RST,HRTIMER Slave_TIME5 channel 0 reset request register"
bitfld.long 0x8 31. "CH0RSUP,Update event generates channel 0 reset request" "0,1"
bitfld.long 0x8 30. "CH0RSEXEV9,External event 9 generates channel 0 reset request" "0,1"
bitfld.long 0x8 29. "CH0RSEXEV8,External event 8 generates channel 0 reset request" "0,1"
bitfld.long 0x8 28. "CH0RSEXEV7,External event 7 generates channel 0 reset request" "0,1"
bitfld.long 0x8 27. "CH0RSEXEV6,External event 6 generates channel 0 reset request" "0,1"
bitfld.long 0x8 26. "CH0RSEXEV5,External event 5 generates channel 0 reset request" "0,1"
bitfld.long 0x8 25. "CH0RSEXEV4,External event 4 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 24. "CH0RSEXEV3,External event 3 generates channel 0 reset request" "0,1"
bitfld.long 0x8 23. "CH0RSEXEV2,External event 2 generates channel 0 reset request" "0,1"
bitfld.long 0x8 22. "CH0RSEXEV1,External event 1 generates channel 0 reset request" "0,1"
bitfld.long 0x8 21. "CH0RSEXEV0,External event 0 generates channel 0 reset request" "0,1"
bitfld.long 0x8 20. "CH0RSSTEV8,interconnection event 8 generates channel 0 reset request" "0,1"
bitfld.long 0x8 19. "CH0RSSTEV7,interconnection event 7 generates channel 0 reset request" "0,1"
bitfld.long 0x8 18. "CH0RSSTEV6,interconnection event 6 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 17. "CH0RSSTEV5,interconnection event 5 generates channel 0 reset request" "0,1"
bitfld.long 0x8 16. "CH0RSSTEV4,interconnection event 4 generates channel 0 reset request" "0,1"
bitfld.long 0x8 15. "CH0RSSTEV3,interconnection event 3 generates channel 0 reset request" "0,1"
bitfld.long 0x8 14. "CH0RSSTEV2,interconnection event 2 generates channel 0 reset request" "0,1"
bitfld.long 0x8 13. "CH0RSSTEV1,interconnection event 1 generates channel 0 reset request" "0,1"
bitfld.long 0x8 12. "CH0RSSTEV0,interconnection event 0 generates channel 0 reset request" "0,1"
bitfld.long 0x8 11. "CH0RSMTCMP3,Master_TIMER compare 3 event generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 10. "CH0RSMTCMP2,Master_TIMER compare 2 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 9. "CH0RSMTCMP1,Master_TIMER compare 1 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 8. "CH0RSMTCMP0,Master_TIMER compare 0 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 7. "CH0RSMTPER,Master_TIMER period event generates channel 0 reset request" "0,1"
bitfld.long 0x8 6. "CH0RSCMP3,compare 3 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 5. "CH0RSCMP2,compare 2 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 4. "CH0RSCMP1,compare 1 event generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 3. "CH0RSCMP0,compare 0 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 2. "CH0RSPER,period event generates channel 0 reset request" "0,1"
bitfld.long 0x8 1. "CH0RSRST,reset event generates channel 0 reset request" "0,1"
bitfld.long 0x8 0. "CH0RSSEV,Software event generates channel 0 reset request" "0,1"
line.long 0xC "ST5CH1SET,HRTIMER Slave_TIME5 channel 1 set request register"
bitfld.long 0xC 31. "CH1SUP,Update event generates channel 1 set request" "0,1"
bitfld.long 0xC 30. "CH1SEXEV9,External event 9 generates channel 1 set request" "0,1"
bitfld.long 0xC 29. "CH1SEXEV8,External event 8 generates channel 1 set request" "0,1"
bitfld.long 0xC 28. "CH1SEXEV7,External event 7 generates channel 1 set request" "0,1"
bitfld.long 0xC 27. "CH1SEXEV6,External event 6 generates channel 1 set request" "0,1"
bitfld.long 0xC 26. "CH1SEXEV5,External event 5 generates channel 1 set request" "0,1"
bitfld.long 0xC 25. "CH1SEXEV4,External event 4 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 24. "CH1SEXEV3,External event 3 generates channel 1 set request" "0,1"
bitfld.long 0xC 23. "CH1SEXEV2,External event 2 generates channel 1 set request" "0,1"
bitfld.long 0xC 22. "CH1SEXEV1,External event 1 generates channel 1 set request" "0,1"
bitfld.long 0xC 21. "CH1SEXEV0,External event 0 generates channel 1 set request" "0,1"
bitfld.long 0xC 20. "CH1SSTEV8,interconnection event 8 generates channel 1 set request" "0,1"
bitfld.long 0xC 19. "CH1SSTEV7,interconnection event 7 generates channel 1 set request" "0,1"
bitfld.long 0xC 18. "CH1SSTEV6,interconnection event 6 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 17. "CH1SSTEV5,interconnection event 5 generates channel 1 set request" "0,1"
bitfld.long 0xC 16. "CH1SSTEV4,interconnection event 4 generates channel 1 set request" "0,1"
bitfld.long 0xC 15. "CH1SSTEV3,interconnection event 3 generates channel 1 set request" "0,1"
bitfld.long 0xC 14. "CH1SSTEV2,interconnection event 2 generates channel 1 set request" "0,1"
bitfld.long 0xC 13. "CH1SSTEV1,interconnection event 1 generates channel 1 set request" "0,1"
bitfld.long 0xC 12. "CH1SSTEV0,interconnection event 0 generates channel 1 set request" "0,1"
bitfld.long 0xC 11. "CH1SMTCMP3,Master_TIMER compare 3 event generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 10. "CH1SMTCMP2,Master_TIMER compare 2 event generates channel 1 set request" "0,1"
bitfld.long 0xC 9. "CH1SMTCMP1,Master_TIMER compare 1 event generates channel 1 set request" "0,1"
bitfld.long 0xC 8. "CH1SMTCMP0,Master_TIMER compare 0 event generates channel 1 set request" "0,1"
bitfld.long 0xC 7. "CH1SMTPER,Master_TIMER period event generates channel 1 set request" "0,1"
bitfld.long 0xC 6. "CH1SCMP3,compare 3 event generates channel 1 set request" "0,1"
bitfld.long 0xC 5. "CH1SCMP2,compare 2 event generates channel 1 set request" "0,1"
bitfld.long 0xC 4. "CH1SCMP1,compare 1 event generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 3. "CH1SCMP0,compare 0 event generates channel 1 set request" "0,1"
bitfld.long 0xC 2. "CH1SPER,period event generates channel 1 set request" "0,1"
bitfld.long 0xC 1. "CH1SRST,reset event generates channel 1 set request" "0,1"
bitfld.long 0xC 0. "CH1SSEV,Software event generates channel 1 set request" "0,1"
line.long 0x10 "ST5CH1RST,HRTIMER Slave_TIME5 channel 1 reset request register"
bitfld.long 0x10 31. "CH1RSUP,Update event generates channel 1 reset request" "0,1"
bitfld.long 0x10 30. "CH1RSEXEV9,External event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x10 29. "CH1RSEXEV8,External event 8 generates channel 1 reset request" "0,1"
bitfld.long 0x10 28. "CH1RSEXEV7,External event 7 generates channel 1 reset request" "0,1"
bitfld.long 0x10 27. "CH1RSEXEV6,External event 6 generates channel 1 reset request" "0,1"
bitfld.long 0x10 26. "CH1RSEXEV5,External event 5 generates channel 1 reset request" "0,1"
bitfld.long 0x10 25. "CH1RSEXEV4,External event 4 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 24. "CH1RSEXEV3,External event 3 generates channel 1 reset request" "0,1"
bitfld.long 0x10 23. "CH1RSEXEV2,External event 2 generates channel 1 reset request" "0,1"
bitfld.long 0x10 22. "CH1RSEXEV1,External event 1 generates channel 1 reset request" "0,1"
bitfld.long 0x10 21. "CH1RSEXEV0,External event 0 generates channel 1 reset request" "0,1"
bitfld.long 0x10 20. "CH1RSSTEV8,interconnection event 8 generates channel 1 reset request" "0,1"
bitfld.long 0x10 19. "CH1RSSTEV7,interconnection event 7 generates channel 1 reset request" "0,1"
bitfld.long 0x10 18. "CH1RSSTEV6,interconnection event 6 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 17. "CH1RSSTEV5,interconnection event 5 generates channel 1 reset request" "0,1"
bitfld.long 0x10 16. "CH1RSSTEV4,interconnection event 4 generates channel 1 reset request" "0,1"
bitfld.long 0x10 15. "CH1RSSTEV3,interconnection event 3 generates channel 1 reset request" "0,1"
bitfld.long 0x10 14. "CH1RSSTEV2,interconnection event 2 generates channel 1 reset request" "0,1"
bitfld.long 0x10 13. "CH1RSSTEV1,interconnection event 1 generates channel 1 reset request" "0,1"
bitfld.long 0x10 12. "CH1RSSTEV0,interconnection event 0 generates channel 1 reset request" "0,1"
bitfld.long 0x10 11. "CH1RSMTCMP3,Master_TIMER compare 3 event generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 10. "CH1RSMTCMP2,Master_TIMER compare 2 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 9. "CH1RSMTCMP1,Master_TIMER compare 1 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 8. "CH1RSMTCMP0,Master_TIMER compare 0 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 7. "CH1RSMTPER,Master_TIMER period event generates channel 1 reset request" "0,1"
bitfld.long 0x10 6. "CH1RSCMP3,compare 3 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 5. "CH1RSCMP2,compare 2 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 4. "CH1RSCMP1,compare 1 event generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 3. "CH1RSCMP0,compare 0 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 2. "CH1RSPER,period event generates channel 1 reset request" "0,1"
bitfld.long 0x10 1. "CH1RSRST,reset event generates channel 1 reset request" "0,1"
bitfld.long 0x10 0. "CH1RSSEV,Software event generates channel 1 reset request" "0,1"
line.long 0x14 "ST5EXEVFCFG0,HRTIMER Slave_TIME5 external event filter configuration register 0"
hexmask.long.byte 0x14 25.--29. 1. "EXEV4FM,External event 4 filter mode"
bitfld.long 0x14 24. "EXEV4MEEN,External event 4 memorized enable" "0,1"
hexmask.long.byte 0x14 19.--23. 1. "EXEV3FM,External event 3 filter mode"
bitfld.long 0x14 18. "EXEV3MEEN,External event 3 memorized enable" "0,1"
hexmask.long.byte 0x14 13.--17. 1. "EXEV2FM,External event 2 filter mode"
bitfld.long 0x14 12. "EXEV2MEEN,External event 2 memorized enable" "0,1"
hexmask.long.byte 0x14 7.--11. 1. "EXEV1FM,External event 1 filter mode"
newline
bitfld.long 0x14 6. "EXEV1MEEN,External event 1 memorized enable" "0,1"
hexmask.long.byte 0x14 1.--5. 1. "EXEV0FM,External event 0 filter mode"
bitfld.long 0x14 0. "EXEV0MEEN,External event 0 memory" "0,1"
line.long 0x18 "ST5EXEVFCFG1,HRTIMER Slave_TIME5 external event filter configuration register 1"
hexmask.long.byte 0x18 25.--29. 1. "EXEV9FM,External event 9 filter mode"
bitfld.long 0x18 24. "EXEV9MEEN,External event 9 memorized enable" "0,1"
hexmask.long.byte 0x18 19.--23. 1. "EXEV8FM,External event 8 filter mode"
bitfld.long 0x18 18. "EXEV8MEEN,External event 8 memorized enable" "0,1"
hexmask.long.byte 0x18 13.--17. 1. "EXEV7FM,External event 7 filter mode"
bitfld.long 0x18 12. "EXEV7MEEN,External event 7 memorized enable" "0,1"
hexmask.long.byte 0x18 7.--11. 1. "EXEV6FM,External event 6 filter mode"
newline
bitfld.long 0x18 6. "EXEV6MEEN,External event 6 memorized enable" "0,1"
hexmask.long.byte 0x18 1.--5. 1. "EXEV5FM,External event 5 filter mode"
bitfld.long 0x18 0. "EXEV5MEEN,External event 0 memorized enable" "0,1"
line.long 0x1C "ST5CNTRST,HRTIMER Slave_TIMER5 counter reset register"
bitfld.long 0x1C 31. "ST4CMP1RST,Slave_TIMER4 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 30. "ST3CMP3RST,Slave_TIMER3 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 29. "ST3CMP1RST,Slave_TIMER3 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 28. "ST3CMP0RST,Slave_TIMER3 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 27. "ST2CMP3RST,Slave_TIMER2 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 26. "ST2CMP1RST,Slave_TIMER2 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 25. "ST2CMP0RST,Slave_TIMER2 compare 0 event resets counter" "0,1"
newline
bitfld.long 0x1C 24. "ST1CMP3RST,Slave_TIMER1 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 23. "ST1CMP1RST,Slave_TIMER1 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 22. "ST1CMP0RST,Slave_TIMER1 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 21. "ST0CMP3RST,Slave_TIMER0 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 20. "ST0CMP1RST,Slave_TIMER0 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 19. "ST0CMP0RST,Slave_TIMER0 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 18. "EXEV9RST,External event 9 resets counter" "0,1"
newline
bitfld.long 0x1C 17. "EXEV8RST,External event 8 resets counter" "0,1"
bitfld.long 0x1C 16. "EXEV7RST,External event 7 resets counter" "0,1"
bitfld.long 0x1C 15. "EXEV6RST,External event 6 resets counter" "0,1"
bitfld.long 0x1C 14. "EXEV5RST,External event 5 resets counter" "0,1"
bitfld.long 0x1C 13. "EXEV4RST,External event 4 resets counter" "0,1"
bitfld.long 0x1C 12. "EXEV3RST,External event 3 resets counter" "0,1"
bitfld.long 0x1C 11. "EXEV2RST,External event 2 resets counter" "0,1"
newline
bitfld.long 0x1C 10. "EXEV1RST,External event 1 resets counter" "0,1"
bitfld.long 0x1C 9. "EXEV0RST,External event 0 resets counter" "0,1"
bitfld.long 0x1C 8. "MTCMP3RST,Master_TIMER compare 3 event resets counter" "0,1"
bitfld.long 0x1C 7. "MTCMP2RST,Master_TIMER compare 2 event resets counter" "0,1"
bitfld.long 0x1C 6. "MTCMP1RST,Master_TIMER compare 1 event resets counter" "0,1"
bitfld.long 0x1C 5. "MTCMP0RST,Master_TIMER compare 0 event resets counter" "0,1"
bitfld.long 0x1C 4. "MTPERRST,Master_TIMER period event resets counter" "0,1"
newline
bitfld.long 0x1C 3. "CMP3RST,Slave_TIMER5 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 2. "CMP1RST,Slave_TIMER5 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 1. "UPRST,Slave_TIMER5 update event resets counter" "0,1"
bitfld.long 0x1C 0. "ST4CMP0RST,Slave_TIMER4 compare 0 event resets counter" "0,1"
line.long 0x20 "ST5CSCTL,HRTIMER Slave_TIME5 carrier-signal control register"
hexmask.long.byte 0x20 7.--10. 1. "CSFSTPW,First carrier-signal pulse width"
bitfld.long 0x20 4.--6. "CSDTY,Carrier signal duty cycle" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x20 0.--3. 1. "CSPRD,Carrier signal period"
line.long 0x24 "ST5CAP0TRG,HRTIMER Slave_TIMER5 capture 0 trigger register"
bitfld.long 0x24 31. "CP0BST4CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x24 30. "CP0BST4CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x24 29. "CP0BST4NA,Capture 0 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 28. "CP0BST4A,Capture 0 triggered by ST4CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 27. "CP0BST3CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x24 26. "CP0BST3CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x24 25. "CP0BST3NA,Capture 0 triggered by ST3CH0_O output active to inactive transition" "0,1"
newline
bitfld.long 0x24 24. "CP0BST3A,Capture 0 triggered by ST3CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 23. "CP0BST2CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x24 22. "CP0BST2CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x24 21. "CP0BST2NA,Capture 0 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 20. "CP0BST2A,Capture 0 triggered by ST2CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 19. "CP0BST1CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x24 18. "CP0BST1CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER1" "0,1"
newline
bitfld.long 0x24 17. "CP0BST1NA,Capture 0 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 16. "CP0BST1A,Capture 0 triggered by ST1CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 15. "CP0BST0CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x24 14. "CP0BST0CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x24 13. "CP0BST0NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 12. "CP0BST0A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
newline
bitfld.long 0x24 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
bitfld.long 0x24 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x24 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
bitfld.long 0x24 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x24 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x24 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x24 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x24 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x24 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x24 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x24 0. "CP0BSW,Capture 0 triggered by software" "0,1"
line.long 0x28 "ST5CAP1TRG,HRTIMER Slave_TIMER5 capture 1 trigger register"
bitfld.long 0x28 31. "CP1BST4CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x28 30. "CP1BST4CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x28 29. "CP1BST4NA,Capture 1 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 28. "CP1BST4A,Capture 1 triggered by ST4CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 27. "CP1BST3CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x28 26. "CP1BST3CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x28 25. "CP1BST3NA,Capture 1 triggered by ST3CH0_O output active to inactive transition" "0,1"
newline
bitfld.long 0x28 24. "CP1BST3A,Capture 1 triggered by ST3CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 23. "CP1BST2CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x28 22. "CP1BST2CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x28 21. "CP1BST2NA,Capture 1 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 20. "CP1BST2A,Capture 1 triggered by ST2CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 19. "CP1BST1CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x28 18. "CP1BST1CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER1" "0,1"
newline
bitfld.long 0x28 17. "CP1BST1NA,Capture 1 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 16. "CP1BST1A,Capture 1 triggered by ST1CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 15. "CP1BST0CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x28 14. "CP1BST0CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x28 13. "CP1BST0NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 12. "CP1BST0A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
newline
bitfld.long 0x28 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
bitfld.long 0x28 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
bitfld.long 0x28 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
bitfld.long 0x28 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x28 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x28 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x28 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
newline
bitfld.long 0x28 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
bitfld.long 0x28 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x28 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x28 0. "CP1BSW,Capture 1 triggered by software" "0,1"
line.long 0x2C "ST5CHOCTL,HRTIMER Slave_TIME5 channel output control register"
bitfld.long 0x2C 23. "BMCH1DTI,Channel 1 dead-time insert in bunch mode" "0,1"
bitfld.long 0x2C 22. "CH1CSEN,Channel 1 carrier-signal mode enable" "0,1"
bitfld.long 0x2C 20.--21. "CH1FLTOS,Channel 1 Fault output state" "0,1,2,3"
bitfld.long 0x2C 19. "ISO1,channel 1 output idle state" "0,1"
bitfld.long 0x2C 18. "BMCH1IEN,Channel 1 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x2C 17. "CH1P,Channel 1 output polarity" "0,1"
bitfld.long 0x2C 14. "BALIAR,Balanced Idle Automatic Resumption" "0,1"
newline
bitfld.long 0x2C 10.--12. "DLYISCH,Delayed IDLE source and channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x2C 9. "DLYISMEN,Delayed IDLE state mode enable" "0,1"
bitfld.long 0x2C 8. "DTEN,Dead time enable" "0,1"
bitfld.long 0x2C 7. "BMCH0DTI,Channel 0 dead-time insert in bunch mode" "0,1"
bitfld.long 0x2C 6. "CH0CSEN,Channel 0 carrier-signal mode enable" "0,1"
bitfld.long 0x2C 4.--5. "CH0FLTOS,Channel 0 Fault output state" "0,1,2,3"
bitfld.long 0x2C 3. "ISO0,Channel 0 output idle state" "0,1"
newline
bitfld.long 0x2C 2. "BMCH0IEN,Channel 0 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x2C 1. "CH0P,Channel 0 output polarity" "0,1"
line.long 0x30 "ST5FLTCTL,HRTIMER Slave_TIME5 fault control register"
bitfld.long 0x30 31. "FLTENPROT,Protect fault enable" "0,1"
bitfld.long 0x30 7. "FLT7EN,Fault 7 enable" "0,1"
bitfld.long 0x30 6. "FLT6EN,Fault 6 enable" "0,1"
bitfld.long 0x30 5. "FLT5EN,Fault 5 enable" "0,1"
bitfld.long 0x30 4. "FLT4EN,Fault 4 enable" "0,1"
bitfld.long 0x30 3. "FLT3EN,Fault 3 enable" "0,1"
bitfld.long 0x30 2. "FLT2EN,Fault 2 enable" "0,1"
newline
bitfld.long 0x30 1. "FLT1EN,Fault 1 enable" "0,1"
bitfld.long 0x30 0. "FLT0EN,Fault 0 enable" "0,1"
line.long 0x34 "ST5CTL1,HRTIMER Slave_TIME5 control register 1"
bitfld.long 0x34 20. "TRGHALFM,Triggered-half mode" "0,1"
bitfld.long 0x34 17. "IMUPD2V,Immediately update compare 2 value PWM mode" "0,1"
bitfld.long 0x34 16. "IMUPD0V,Immediately update compare 0 value PWM mode" "0,1"
bitfld.long 0x34 14.--15. "FEROVM,Fault and event roll-over mode" "0,1,2,3"
bitfld.long 0x34 12.--13. "BMROVM,Bunch mode roll-over mode" "0,1,2,3"
bitfld.long 0x34 10.--11. "ADCROVM,ADC roll-over mode" "0,1,2,3"
bitfld.long 0x34 8.--9. "OUTROVM,Output roll-over mode" "0,1,2,3"
newline
bitfld.long 0x34 6.--7. "ROVM,Roll-over mode" "0,1,2,3"
bitfld.long 0x34 4. "CAM,Center-aligned counting mode" "0,1"
bitfld.long 0x34 2. "TRIG1M,This bit defines when TRIG1M is generated" "0,1"
bitfld.long 0x34 1. "TRIG0M,This bit defines when TRIG0M is generated" "0,1"
bitfld.long 0x34 0. "TRIGEN,Two trigger enable" "0,1"
line.long 0x38 "ST5EXEVFCFG2,HRTIMER Slave_TIME5 external event filter configuration register 2"
hexmask.long.byte 0x38 26.--31. 1. "EXEVXCNT,External event X counter value"
hexmask.long.byte 0x38 8.--13. 1. "EXEVXCNTTHR,External event X counter threshold"
hexmask.long.byte 0x38 4.--7. 1. "EXEVXSEL,External event X selection This bit determines the source of external event X"
bitfld.long 0x38 2. "EXEVXRSTM,External event X reset mode" "0,1"
bitfld.long 0x38 1. "EXEVXCRST,External event X counter reset" "0,1"
bitfld.long 0x38 0. "EXEVXCEN,External event X counter enable" "0,1"
line.long 0x3C "ST5CAPTRGCOM,HRTIMER Slave_TIMER5 capture trigger combination register"
bitfld.long 0x3C 27. "CP1BST7CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 26. "CP1BST7CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 25. "CP1BST7NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 24. "CP1BST7A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 23. "CP1BST6CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER6" "0,1"
bitfld.long 0x3C 22. "CP1BST6CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER6" "0,1"
bitfld.long 0x3C 21. "CP1BST6NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
newline
bitfld.long 0x3C 20. "CP1BST6A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 11. "CP0BST7CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 10. "CP0BST7CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 9. "CP0BST7NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 8. "CP0BST7A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 7. "CP0BST6CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER6" "0,1"
bitfld.long 0x3C 6. "CP0BST6CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER6" "0,1"
newline
bitfld.long 0x3C 5. "CP0BST6NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 4. "CP0BST6A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
line.long 0x40 "ST5CNTRSTA,HRTIMER Slave_TIMER5 counter reset and channel 0/1 set/reset request add register"
bitfld.long 0x40 29. "CH1CNTRST,Counter reset for channel 1 output reset" "0,1"
bitfld.long 0x40 28. "CH0CNTRST,Counter reset for channel 0 output reset" "0,1"
bitfld.long 0x40 27. "CH1RSSTEV10,Slave_TIMER5 interconnection event 10 generates channel 1" "0,1"
bitfld.long 0x40 26. "CH1RSSTEV9,Slave_TIMER5 interconnection event 9 generates channel 1" "0,1"
bitfld.long 0x40 25. "CH0RSSTEV10,Slave_TIMER5 interconnection event 10 generates channel 0" "0,1"
bitfld.long 0x40 24. "CH0RSSTEV9,Slave_TIMER5 interconnection event 9 generates channel 0" "0,1"
bitfld.long 0x40 21. "CH1CNTSET,Counter reset for channel 1 output set" "0,1"
newline
bitfld.long 0x40 20. "CH0CNTSET,Counter reset for channel 0 output set" "0,1"
bitfld.long 0x40 19. "CH1SSTEV10,Slave_TIMER5 interconnection event 10 generates channel 1 set request" "0,1"
bitfld.long 0x40 18. "CH1SSTEV9,Slave_TIMER5 interconnection event 9 generates channel 1 set request" "0,1"
bitfld.long 0x40 17. "CH0SSTEV10,Slave_TIMER5 interconnection event 10 generates channel 0 set request" "0,1"
bitfld.long 0x40 16. "CH0SSTEV9,Slave_TIMER5 interconnection event 9 generates channel 1 set request" "0,1"
bitfld.long 0x40 6. "ST7CMP3RST,Slave_TIMER7 compare 3 event resets counter" "0,1"
bitfld.long 0x40 5. "ST7CMP1RST,Slave_TIMER7 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x40 4. "ST7CMP0RST,Slave_TIMER7 compare 0 event resets counter" "0,1"
bitfld.long 0x40 3. "ST6CMP3RST,Slave_TIMER6 compare 3 event resets counter" "0,1"
bitfld.long 0x40 2. "ST6CMP1RST,Slave_TIMER6 compare 1 event resets counter" "0,1"
bitfld.long 0x40 1. "ST6CMP0RST,Slave_TIMER6 compare 0 event resets counter" "0,1"
bitfld.long 0x40 0. "ST4CMP3RST,Slave_TIMER4 compare 3 event resets counter" "0,1"
line.long 0x44 "ST5ACTL,HRTIMER Slave_TIME5 additional control register"
hexmask.long.byte 0x44 25.--31. 1. "DTFCFG,Falling edge dead-time value configure"
hexmask.long.byte 0x44 9.--15. 1. "DTRCFG,Rising edge dead-time value configure"
bitfld.long 0x44 1. "UPBST7,Update by Slave_TIMER7 update event" "0,1"
bitfld.long 0x44 0. "UPBST6,Update by Slave_TIMER6 update event" "0,1"
tree.end
tree "HRTIMER_SLAVE_TIMER6"
base ad:0x40016000
group.long 0x0++0x3
line.long 0x0 "ST6CTL0,HRTIMER Slave_TIME6 control register 0"
hexmask.long.byte 0x0 28.--31. 1. "UPSEL,Update event selection"
bitfld.long 0x0 27. "SHWEN,Shadow registers enable" "0,1"
bitfld.long 0x0 25.--26. "DACTRGS,Trigger source to DAC" "0,1,2,3"
bitfld.long 0x0 24. "UPBMT,Update by Master_TIMER update event" "0,1"
bitfld.long 0x0 23. "UPBST4,Update by Slave_TIMER4 update event" "0,1"
bitfld.long 0x0 22. "UPBST3,Update by Slave_TIMER3 update event" "0,1"
bitfld.long 0x0 21. "UPBST2,Update by Slave_TIMER2 update event" "0,1"
newline
bitfld.long 0x0 20. "UPBST1,Update by Slave_TIMER1 update event" "0,1"
bitfld.long 0x0 19. "UPBST0,Update by Slave_TIMER0 update event" "0,1"
bitfld.long 0x0 18. "UPRST,Update event generated by reset event" "0,1"
bitfld.long 0x0 17. "UPREP,Update event generated by repetition event" "0,1"
bitfld.long 0x0 16. "UPBST5,Update by Slave_TIMER5 update event" "0,1"
bitfld.long 0x0 14.--15. "DELCMP3M,Compare 3 delayed mode" "0,1,2,3"
bitfld.long 0x0 12.--13. "DELCMP1M,Compare 1 delayed mode" "0,1,2,3"
newline
bitfld.long 0x0 11. "SYNISTRT,Synchronous input start timer" "0,1"
bitfld.long 0x0 10. "SYNIRST,Synchronous input reset timer" "0,1"
bitfld.long 0x0 9. "RSYNUPD,Re-synchronized update" "0,1"
bitfld.long 0x0 7.--8. "ALTM,Alternate mode" "0,1,2,3"
bitfld.long 0x0 6. "BLNMEN,Balanced mode enable" "0,1"
bitfld.long 0x0 5. "HALFM,Half mode" "0,1"
bitfld.long 0x0 4. "CNTRSTM,Counter reset mode" "0,1"
newline
bitfld.long 0x0 3. "CTNM,Continuous mode" "0,1"
bitfld.long 0x0 0.--2. "CNTCKDIV,Counter clock division" "0,1,2,3,4,5,6,7"
rgroup.long 0x4++0x3
line.long 0x0 "ST6INTF,HRTIMER Slave_TIME6 interrupt flag register"
bitfld.long 0x0 31. "DIR,Direction" "0,1"
bitfld.long 0x0 21. "CH1F,Channel 1 output flag" "0,1"
bitfld.long 0x0 20. "CH0F,Channel 0 output flag" "0,1"
bitfld.long 0x0 19. "CH1SF,Channel 1 output state flag" "0,1"
bitfld.long 0x0 18. "CH0SF,Channel 0 output state flag" "0,1"
bitfld.long 0x0 17. "BLNIF,Balanced IDLE flag" "0,1"
bitfld.long 0x0 16. "CBLNF,Current balanced flag" "0,1"
newline
bitfld.long 0x0 14. "DLYIIF,Delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x0 13. "RSTIF,Counter reset interrupt flag" "0,1"
bitfld.long 0x0 12. "CH1ONAIF,Channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x0 11. "CH1OAIF,Channel 1 output active interrupt flag" "0,1"
bitfld.long 0x0 10. "CH0ONAIF,Channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x0 9. "CH0OAIF,Channel 0 output active interrupt flag" "0,1"
bitfld.long 0x0 8. "CAP1IF,Capture 1 interrupt flag" "0,1"
newline
bitfld.long 0x0 7. "CAP0IF,Capture 0 interrupt flag" "0,1"
bitfld.long 0x0 6. "UPIF,Update interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIF,Repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IF,Compare 3 interrupt flag" "0,1"
bitfld.long 0x0 2. "CMP2IF,Compare 2 interrupt flag" "0,1"
bitfld.long 0x0 1. "CMP1IF,Compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IF,Compare 0 interrupt flag" "0,1"
wgroup.long 0x8++0x3
line.long 0x0 "ST6INTC,HRTIMER Slave_TIME6 interrupt flag clear register"
bitfld.long 0x0 14. "DLYIIFC,Clear delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x0 13. "RSTIFC,Clear counter reset interrupt flag" "0,1"
bitfld.long 0x0 12. "CH1ONAIFC,Clear channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x0 11. "CH1OAIFC,Clear channel 1 output active interrupt flag" "0,1"
bitfld.long 0x0 10. "CH0ONAIFC,Clear channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x0 9. "CH0OAIFC,Clear channel 0 output active interrupt flag" "0,1"
bitfld.long 0x0 8. "CAP1IFC,Clear capture 1 interrupt flag" "0,1"
newline
bitfld.long 0x0 7. "CAP0IFC,Clear capture 0 interrupt flag" "0,1"
bitfld.long 0x0 6. "UPIFC,Clear update interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIFC,Clear repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IFC,Clear compare 3 interrupt flag" "0,1"
bitfld.long 0x0 2. "CMP2IFC,Clear compare 2 interrupt flag" "0,1"
bitfld.long 0x0 1. "CMP1IFC,Clear compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IFC,Clear compare 0 interrupt flag" "0,1"
group.long 0xC++0x23
line.long 0x0 "ST6DMAINTEN,HRTIMER Slave_TIME6 DMA and interrupt enable register"
bitfld.long 0x0 30. "DLYIDEN,Delayed IDLE mode entry DMA request enable" "0,1"
bitfld.long 0x0 29. "RSTDEN,Counter reset DMA request enable" "0,1"
bitfld.long 0x0 28. "CH1ONADEN,Channel 1 output inactive DMA request enable" "0,1"
bitfld.long 0x0 27. "CH1OADEN,Channel 1 output active DMA request enable" "0,1"
bitfld.long 0x0 26. "CH0ONADEN,Channel 0 output inactive DMA request enable" "0,1"
bitfld.long 0x0 25. "CH0OADEN,Channel 0 output active DMA request enable" "0,1"
bitfld.long 0x0 24. "CAP1DEN,Capture 1 DMA request enable" "0,1"
newline
bitfld.long 0x0 23. "CAP0DEN,Capture 0 DMA request enable" "0,1"
bitfld.long 0x0 22. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x0 20. "REPDEN,Repetition DMA request enable" "0,1"
bitfld.long 0x0 19. "CMP3DEN,Compare 3 DMA request enable" "0,1"
bitfld.long 0x0 18. "CMP2DEN,Compare 2 DMA request enable" "0,1"
bitfld.long 0x0 17. "CMP1DEN,Compare 1 DMA request enable" "0,1"
bitfld.long 0x0 16. "CMP0DEN,Compare 0 DMA request enable" "0,1"
newline
bitfld.long 0x0 14. "DLYIIE,Delayed IDLE mode entry interrupt enable" "0,1"
bitfld.long 0x0 13. "RSTIE,Counter reset interrupt enable" "0,1"
bitfld.long 0x0 12. "CH1ONAIE,Channel 1 output inactive interrupt enable" "0,1"
bitfld.long 0x0 11. "CH1OAIE,Channel 1 output active interrupt enable" "0,1"
bitfld.long 0x0 10. "CH0ONAIE,Channel 0 output inactive interrupt enable" "0,1"
bitfld.long 0x0 9. "CH0OAIE,Channel 0 output active interrupt enable" "0,1"
bitfld.long 0x0 8. "CAP1IE,Capture 1 interrupt enable" "0,1"
newline
bitfld.long 0x0 7. "CAP0IE,Capture 0 interrupt enable" "0,1"
bitfld.long 0x0 6. "UPIE,Update interrupt enable" "0,1"
bitfld.long 0x0 4. "REPIE,Repetition interrupt enable" "0,1"
bitfld.long 0x0 3. "CMP3IE,Compare 3 interrupt enable" "0,1"
bitfld.long 0x0 2. "CMP2IE,Compare 2 interrupt enable" "0,1"
bitfld.long 0x0 1. "CMP1IE,Compare 1 interrupt enable" "0,1"
bitfld.long 0x0 0. "CMP0IE,Compare 0 interrupt enable" "0,1"
line.long 0x4 "ST6CNT,HRTIMER Slave_TIME6 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,The current counter value"
line.long 0x8 "ST6CAR,HRTIMER Slave_TIME6 counter auto reload register"
hexmask.long.word 0x8 0.--15. 1. "CARL,Counter auto reload value"
line.long 0xC "ST6CREP,HRTIMER Slave_TIME6 counter repetition register"
hexmask.long.byte 0xC 0.--7. 1. "CREP,Counter repetition value"
line.long 0x10 "ST6CMP0V,HRTIMER Slave_TIME6 compare 0 value register"
hexmask.long.word 0x10 0.--15. 1. "CMP0VAL,Compare 0 value"
line.long 0x14 "ST6CMP0CP,HRTIMER Slave_TIME6 compare 0 composite register"
hexmask.long.byte 0x14 16.--23. 1. "CREP,Counter repetition value"
hexmask.long.word 0x14 0.--15. 1. "CMP0VAL,Compare 0 value"
line.long 0x18 "ST6CMP1V,HRTIMER Slave_TIME6 compare 1 value register"
hexmask.long.word 0x18 0.--15. 1. "CMP1VAL,Compare 1 value"
line.long 0x1C "ST6CMP2V,HRTIMER Slave_TIME6 compare 2 value register"
hexmask.long.word 0x1C 0.--15. 1. "CMP2VAL,Compare 2 value"
line.long 0x20 "ST6CMP3V,HRTIMER Slave_TIME6 compare 3 value register"
hexmask.long.word 0x20 0.--15. 1. "CMP3VAL,Compare 3 value"
rgroup.long 0x30++0x7
line.long 0x0 "ST6CAP0V,HRTIMER Slave_TIME6 capture 0 value register"
bitfld.long 0x0 16. "DIR,Slave_timer 0 capture 1 direction status" "0,1"
hexmask.long.word 0x0 0.--15. 1. "CAP0VAL,Capture 0 value"
line.long 0x4 "ST6CAP1V,HRTIMER Slave_TIME6 capture 1 value register"
bitfld.long 0x4 16. "DIR,Slave_Timer 0 capture 1 direction status" "0,1"
hexmask.long.word 0x4 0.--15. 1. "CAP1VAL,Capture 1 value"
group.long 0x38++0x47
line.long 0x0 "ST6DTCTL,HRTIMER Slave_TIME6 dead-time control register"
bitfld.long 0x0 31. "DTFSVPROT,Dead-time falling edge protection for value and sign" "0,1"
bitfld.long 0x0 30. "DTFSPROT,Dead-time falling edge protection for sign" "0,1"
bitfld.long 0x0 25. "DTFS,The sign of falling edge dead-time value" "0,1"
hexmask.long.word 0x0 16.--24. 1. "DTFCFG,Falling edge dead-time value"
bitfld.long 0x0 15. "DTRSVPROT,Dead-time rising edge protection for value and sign" "0,1"
bitfld.long 0x0 14. "DTRSPROT,Dead-time rising edge protection for sign" "0,1"
hexmask.long.byte 0x0 10.--13. 1. "DTGCKDIV,Dead time clock division"
newline
bitfld.long 0x0 9. "DTRS,The sign of rising edge dead-time value" "0,1"
hexmask.long.word 0x0 0.--8. 1. "DTRCFG,Rising edge dead-time value"
line.long 0x4 "ST6CH0SET,HRTIMER Slave_TIME6 channel 0 set request register"
bitfld.long 0x4 31. "CH0SUP,Update event generates channel 0 set request" "0,1"
bitfld.long 0x4 30. "CH0SEXEV9,External event 9 generates channel 0 set request" "0,1"
bitfld.long 0x4 29. "CH0SEXEV8,External event 8 generates channel 0 set request" "0,1"
bitfld.long 0x4 28. "CH0SEXEV7,External event 7 generates channel 0 set request" "0,1"
bitfld.long 0x4 27. "CH0SEXEV6,External event 6 generates channel 0 set request" "0,1"
bitfld.long 0x4 26. "CH0SEXEV5,External event 5 generates channel 0 set request" "0,1"
bitfld.long 0x4 25. "CH0SEXEV4,External event 4 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 24. "CH0SEXEV3,External event 3 generates channel 0 set request" "0,1"
bitfld.long 0x4 23. "CH0SEXEV2,External event 2 generates channel 0 set request" "0,1"
bitfld.long 0x4 22. "CH0SEXEV1,External event 1 generates channel 0 set request" "0,1"
bitfld.long 0x4 21. "CH0SEXEV0,External event 0 generates channel 0 set request" "0,1"
bitfld.long 0x4 20. "CH0SSTEV8,interconnection event 8 generates channel 0 set request" "0,1"
bitfld.long 0x4 19. "CH0SSTEV7,interconnection event 7 generates channel 0 set request" "0,1"
bitfld.long 0x4 18. "CH0SSTEV6,interconnection event 6 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 17. "CH0SSTEV5,interconnection event 5 generates channel 0 set request" "0,1"
bitfld.long 0x4 16. "CH0SSTEV4,interconnection event 4 generates channel 0 set request" "0,1"
bitfld.long 0x4 15. "CH0SSTEV3,interconnection event 3 generates channel 0 set request" "0,1"
bitfld.long 0x4 14. "CH0SSTEV2,interconnection event 2 generates channel 0 set request" "0,1"
bitfld.long 0x4 13. "CH0SSTEV1,interconnection event 1 generates channel 0 set request" "0,1"
bitfld.long 0x4 12. "CH0SSTEV0,interconnection event 0 generates channel 0 set request" "0,1"
bitfld.long 0x4 11. "CH0SMTCMP3,Master_TIMER compare 3 event generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 10. "CH0SMTCMP2,Master_TIMER compare 2 event generates channel 0 set request" "0,1"
bitfld.long 0x4 9. "CH0SMTCMP1,Master_TIMER compare 1 event generates channel 0 set request" "0,1"
bitfld.long 0x4 8. "CH0SMTCMP0,Master_TIMER compare 0 event generates channel 0 set request" "0,1"
bitfld.long 0x4 7. "CH0SMTPER,Master_TIMER period event generates channel 0 set request" "0,1"
bitfld.long 0x4 6. "CH0SCMP3,compare 3 event generates channel 0 set request" "0,1"
bitfld.long 0x4 5. "CH0SCMP2,compare 2 event generates channel 0 set request" "0,1"
bitfld.long 0x4 4. "CH0SCMP1,compare 1 event generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 3. "CH0SCMP0,compare 0 event generates channel 0 set request" "0,1"
bitfld.long 0x4 2. "CH0SPER,period event generates channel 0 set request" "0,1"
bitfld.long 0x4 1. "CH0SRST,reset event generates channel 0 set request" "0,1"
bitfld.long 0x4 0. "CH0SSEV,Software event generates channel 0 set request" "0,1"
line.long 0x8 "ST6CH0RST,HRTIMER Slave_TIME6 channel 0 reset request register"
bitfld.long 0x8 31. "CH0RSUP,Update event generates channel 0 reset request" "0,1"
bitfld.long 0x8 30. "CH0RSEXEV9,External event 9 generates channel 0 reset request" "0,1"
bitfld.long 0x8 29. "CH0RSEXEV8,External event 8 generates channel 0 reset request" "0,1"
bitfld.long 0x8 28. "CH0RSEXEV7,External event 7 generates channel 0 reset request" "0,1"
bitfld.long 0x8 27. "CH0RSEXEV6,External event 6 generates channel 0 reset request" "0,1"
bitfld.long 0x8 26. "CH0RSEXEV5,External event 5 generates channel 0 reset request" "0,1"
bitfld.long 0x8 25. "CH0RSEXEV4,External event 4 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 24. "CH0RSEXEV3,External event 3 generates channel 0 reset request" "0,1"
bitfld.long 0x8 23. "CH0RSEXEV2,External event 2 generates channel 0 reset request" "0,1"
bitfld.long 0x8 22. "CH0RSEXEV1,External event 1 generates channel 0 reset request" "0,1"
bitfld.long 0x8 21. "CH0RSEXEV0,External event 0 generates channel 0 reset request" "0,1"
bitfld.long 0x8 20. "CH0RSSTEV8,interconnection event 8 generates channel 0 reset request" "0,1"
bitfld.long 0x8 19. "CH0RSSTEV7,interconnection event 7 generates channel 0 reset request" "0,1"
bitfld.long 0x8 18. "CH0RSSTEV6,interconnection event 6 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 17. "CH0RSSTEV5,interconnection event 5 generates channel 0 reset request" "0,1"
bitfld.long 0x8 16. "CH0RSSTEV4,interconnection event 4 generates channel 0 reset request" "0,1"
bitfld.long 0x8 15. "CH0RSSTEV3,interconnection event 3 generates channel 0 reset request" "0,1"
bitfld.long 0x8 14. "CH0RSSTEV2,interconnection event 2 generates channel 0 reset request" "0,1"
bitfld.long 0x8 13. "CH0RSSTEV1,interconnection event 1 generates channel 0 reset request" "0,1"
bitfld.long 0x8 12. "CH0RSSTEV0,interconnection event 0 generates channel 0 reset request" "0,1"
bitfld.long 0x8 11. "CH0RSMTCMP3,Master_TIMER compare 3 event generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 10. "CH0RSMTCMP2,Master_TIMER compare 2 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 9. "CH0RSMTCMP1,Master_TIMER compare 1 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 8. "CH0RSMTCMP0,Master_TIMER compare 0 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 7. "CH0RSMTPER,Master_TIMER period event generates channel 0 reset request" "0,1"
bitfld.long 0x8 6. "CH0RSCMP3,compare 3 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 5. "CH0RSCMP2,compare 2 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 4. "CH0RSCMP1,compare 1 event generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 3. "CH0RSCMP0,compare 0 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 2. "CH0RSPER,period event generates channel 0 reset request" "0,1"
bitfld.long 0x8 1. "CH0RSRST,reset event generates channel 0 reset request" "0,1"
bitfld.long 0x8 0. "CH0RSSEV,Software event generates channel 0 reset request" "0,1"
line.long 0xC "ST6CH1SET,HRTIMER Slave_TIME6 channel 1 set request register"
bitfld.long 0xC 31. "CH1SUP,Update event generates channel 1 set request" "0,1"
bitfld.long 0xC 30. "CH1SEXEV9,External event 9 generates channel 1 set request" "0,1"
bitfld.long 0xC 29. "CH1SEXEV8,External event 8 generates channel 1 set request" "0,1"
bitfld.long 0xC 28. "CH1SEXEV7,External event 7 generates channel 1 set request" "0,1"
bitfld.long 0xC 27. "CH1SEXEV6,External event 6 generates channel 1 set request" "0,1"
bitfld.long 0xC 26. "CH1SEXEV5,External event 5 generates channel 1 set request" "0,1"
bitfld.long 0xC 25. "CH1SEXEV4,External event 4 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 24. "CH1SEXEV3,External event 3 generates channel 1 set request" "0,1"
bitfld.long 0xC 23. "CH1SEXEV2,External event 2 generates channel 1 set request" "0,1"
bitfld.long 0xC 22. "CH1SEXEV1,External event 1 generates channel 1 set request" "0,1"
bitfld.long 0xC 21. "CH1SEXEV0,External event 0 generates channel 1 set request" "0,1"
bitfld.long 0xC 20. "CH1SSTEV8,interconnection event 8 generates channel 1 set request" "0,1"
bitfld.long 0xC 19. "CH1SSTEV7,interconnection event 7 generates channel 1 set request" "0,1"
bitfld.long 0xC 18. "CH1SSTEV6,interconnection event 6 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 17. "CH1SSTEV5,interconnection event 5 generates channel 1 set request" "0,1"
bitfld.long 0xC 16. "CH1SSTEV4,interconnection event 4 generates channel 1 set request" "0,1"
bitfld.long 0xC 15. "CH1SSTEV3,interconnection event 3 generates channel 1 set request" "0,1"
bitfld.long 0xC 14. "CH1SSTEV2,interconnection event 2 generates channel 1 set request" "0,1"
bitfld.long 0xC 13. "CH1SSTEV1,interconnection event 1 generates channel 1 set request" "0,1"
bitfld.long 0xC 12. "CH1SSTEV0,interconnection event 0 generates channel 1 set request" "0,1"
bitfld.long 0xC 11. "CH1SMTCMP3,Master_TIMER compare 3 event generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 10. "CH1SMTCMP2,Master_TIMER compare 2 event generates channel 1 set request" "0,1"
bitfld.long 0xC 9. "CH1SMTCMP1,Master_TIMER compare 1 event generates channel 1 set request" "0,1"
bitfld.long 0xC 8. "CH1SMTCMP0,Master_TIMER compare 0 event generates channel 1 set request" "0,1"
bitfld.long 0xC 7. "CH1SMTPER,Master_TIMER period event generates channel 1 set request" "0,1"
bitfld.long 0xC 6. "CH1SCMP3,compare 3 event generates channel 1 set request" "0,1"
bitfld.long 0xC 5. "CH1SCMP2,compare 2 event generates channel 1 set request" "0,1"
bitfld.long 0xC 4. "CH1SCMP1,compare 1 event generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 3. "CH1SCMP0,compare 0 event generates channel 1 set request" "0,1"
bitfld.long 0xC 2. "CH1SPER,period event generates channel 1 set request" "0,1"
bitfld.long 0xC 1. "CH1SRST,reset event generates channel 1 set request" "0,1"
bitfld.long 0xC 0. "CH1SSEV,Software event generates channel 1 set request" "0,1"
line.long 0x10 "ST6CH1RST,HRTIMER Slave_TIME6 channel 1 reset request register"
bitfld.long 0x10 31. "CH1RSUP,Update event generates channel 1 reset request" "0,1"
bitfld.long 0x10 30. "CH1RSEXEV9,External event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x10 29. "CH1RSEXEV8,External event 8 generates channel 1 reset request" "0,1"
bitfld.long 0x10 28. "CH1RSEXEV7,External event 7 generates channel 1 reset request" "0,1"
bitfld.long 0x10 27. "CH1RSEXEV6,External event 6 generates channel 1 reset request" "0,1"
bitfld.long 0x10 26. "CH1RSEXEV5,External event 5 generates channel 1 reset request" "0,1"
bitfld.long 0x10 25. "CH1RSEXEV4,External event 4 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 24. "CH1RSEXEV3,External event 3 generates channel 1 reset request" "0,1"
bitfld.long 0x10 23. "CH1RSEXEV2,External event 2 generates channel 1 reset request" "0,1"
bitfld.long 0x10 22. "CH1RSEXEV1,External event 1 generates channel 1 reset request" "0,1"
bitfld.long 0x10 21. "CH1RSEXEV0,External event 0 generates channel 1 reset request" "0,1"
bitfld.long 0x10 20. "CH1RSSTEV8,interconnection event 8 generates channel 1 reset request" "0,1"
bitfld.long 0x10 19. "CH1RSSTEV7,interconnection event 7 generates channel 1 reset request" "0,1"
bitfld.long 0x10 18. "CH1RSSTEV6,interconnection event 6 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 17. "CH1RSSTEV5,interconnection event 5 generates channel 1 reset request" "0,1"
bitfld.long 0x10 16. "CH1RSSTEV4,interconnection event 4 generates channel 1 reset request" "0,1"
bitfld.long 0x10 15. "CH1RSSTEV3,interconnection event 3 generates channel 1 reset request" "0,1"
bitfld.long 0x10 14. "CH1RSSTEV2,interconnection event 2 generates channel 1 reset request" "0,1"
bitfld.long 0x10 13. "CH1RSSTEV1,interconnection event 1 generates channel 1 reset request" "0,1"
bitfld.long 0x10 12. "CH1RSSTEV0,interconnection event 0 generates channel 1 reset request" "0,1"
bitfld.long 0x10 11. "CH1RSMTCMP3,Master_TIMER compare 3 event generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 10. "CH1RSMTCMP2,Master_TIMER compare 2 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 9. "CH1RSMTCMP1,Master_TIMER compare 1 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 8. "CH1RSMTCMP0,Master_TIMER compare 0 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 7. "CH1RSMTPER,Master_TIMER period event generates channel 1 reset request" "0,1"
bitfld.long 0x10 6. "CH1RSCMP3,compare 3 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 5. "CH1RSCMP2,compare 2 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 4. "CH1RSCMP1,compare 1 event generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 3. "CH1RSCMP0,compare 0 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 2. "CH1RSPER,period event generates channel 1 reset request" "0,1"
bitfld.long 0x10 1. "CH1RSRST,reset event generates channel 1 reset request" "0,1"
bitfld.long 0x10 0. "CH1RSSEV,Software event generates channel 1 reset request" "0,1"
line.long 0x14 "ST6EXEVFCFG0,HRTIMER Slave_TIME6 external event filter configuration register 0"
hexmask.long.byte 0x14 25.--29. 1. "EXEV4FM,External event 4 filter mode"
bitfld.long 0x14 24. "EXEV4MEEN,External event 4 memorized enable" "0,1"
hexmask.long.byte 0x14 19.--23. 1. "EXEV3FM,External event 3 filter mode"
bitfld.long 0x14 18. "EXEV3MEEN,External event 3 memorized enable" "0,1"
hexmask.long.byte 0x14 13.--17. 1. "EXEV2FM,External event 2 filter mode"
bitfld.long 0x14 12. "EXEV2MEEN,External event 2 memorized enable" "0,1"
hexmask.long.byte 0x14 7.--11. 1. "EXEV1FM,External event 1 filter mode"
newline
bitfld.long 0x14 6. "EXEV1MEEN,External event 1 memorized enable" "0,1"
hexmask.long.byte 0x14 1.--5. 1. "EXEV0FM,External event 0 filter mode"
bitfld.long 0x14 0. "EXEV0MEEN,External event 0 memory" "0,1"
line.long 0x18 "ST6EXEVFCFG1,HRTIMER Slave_TIME6 external event filter configuration register 1"
hexmask.long.byte 0x18 25.--29. 1. "EXEV9FM,External event 9 filter mode"
bitfld.long 0x18 24. "EXEV9MEEN,External event 9 memorized enable" "0,1"
hexmask.long.byte 0x18 19.--23. 1. "EXEV8FM,External event 8 filter mode"
bitfld.long 0x18 18. "EXEV8MEEN,External event 8 memorized enable" "0,1"
hexmask.long.byte 0x18 13.--17. 1. "EXEV7FM,External event 7 filter mode"
bitfld.long 0x18 12. "EXEV7MEEN,External event 7 memorized enable" "0,1"
hexmask.long.byte 0x18 7.--11. 1. "EXEV6FM,External event 6 filter mode"
newline
bitfld.long 0x18 6. "EXEV6MEEN,External event 6 memorized enable" "0,1"
hexmask.long.byte 0x18 1.--5. 1. "EXEV5FM,External event 5 filter mode"
bitfld.long 0x18 0. "EXEV5MEEN,External event 0 memorized enable" "0,1"
line.long 0x1C "ST6CNTRST,HRTIMER Slave_TIMER6 counter reset register"
bitfld.long 0x1C 31. "ST4CMP1RST,Slave_TIMER4 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 30. "ST3CMP3RST,Slave_TIMER3 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 29. "ST3CMP1RST,Slave_TIMER3 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 28. "ST3CMP0RST,Slave_TIMER3 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 27. "ST2CMP3RST,Slave_TIMER2 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 26. "ST2CMP1RST,Slave_TIMER2 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 25. "ST2CMP0RST,Slave_TIMER2 compare 0 event resets counter" "0,1"
newline
bitfld.long 0x1C 24. "ST1CMP3RST,Slave_TIMER1 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 23. "ST1CMP1RST,Slave_TIMER1 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 22. "ST1CMP0RST,Slave_TIMER1 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 21. "ST0CMP3RST,Slave_TIMER0 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 20. "ST0CMP1RST,Slave_TIMER0 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 19. "ST0CMP0RST,Slave_TIMER0 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 18. "EXEV9RST,External event 9 resets counter" "0,1"
newline
bitfld.long 0x1C 17. "EXEV8RST,External event 8 resets counter" "0,1"
bitfld.long 0x1C 16. "EXEV7RST,External event 7 resets counter" "0,1"
bitfld.long 0x1C 15. "EXEV6RST,External event 6 resets counter" "0,1"
bitfld.long 0x1C 14. "EXEV5RST,External event 5 resets counter" "0,1"
bitfld.long 0x1C 13. "EXEV4RST,External event 4 resets counter" "0,1"
bitfld.long 0x1C 12. "EXEV3RST,External event 3 resets counter" "0,1"
bitfld.long 0x1C 11. "EXEV2RST,External event 2 resets counter" "0,1"
newline
bitfld.long 0x1C 10. "EXEV1RST,External event 1 resets counter" "0,1"
bitfld.long 0x1C 9. "EXEV0RST,External event 0 resets counter" "0,1"
bitfld.long 0x1C 8. "MTCMP3RST,Master_TIMER compare 3 event resets counter" "0,1"
bitfld.long 0x1C 7. "MTCMP2RST,Master_TIMER compare 2 event resets counter" "0,1"
bitfld.long 0x1C 6. "MTCMP1RST,Master_TIMER compare 1 event resets counter" "0,1"
bitfld.long 0x1C 5. "MTCMP0RST,Master_TIMER compare 0 event resets counter" "0,1"
bitfld.long 0x1C 4. "MTPERRST,Master_TIMER period event resets counter" "0,1"
newline
bitfld.long 0x1C 3. "CMP3RST,Slave_TIMER6 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 2. "CMP1RST,Slave_TIMER6 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 1. "UPRST,Slave_TIMER6 update event resets counter" "0,1"
bitfld.long 0x1C 0. "ST4CMP0RST,Slave_TIMER4 compare 0 event resets counter" "0,1"
line.long 0x20 "ST6CSCTL,HRTIMER Slave_TIME6 carrier-signal control register"
hexmask.long.byte 0x20 7.--10. 1. "CSFSTPW,First carrier-signal pulse width"
bitfld.long 0x20 4.--6. "CSDTY,Carrier signal duty cycle" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x20 0.--3. 1. "CSPRD,Carrier signal period"
line.long 0x24 "ST6CAP0TRG,HRTIMER Slave_TIMER6 capture 0 trigger register"
bitfld.long 0x24 31. "CP0BST4CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x24 30. "CP0BST4CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x24 29. "CP0BST4NA,Capture 0 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 28. "CP0BST4A,Capture 0 triggered by ST4CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 27. "CP0BST3CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x24 26. "CP0BST3CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x24 25. "CP0BST3NA,Capture 0 triggered by ST3CH0_O output active to inactive transition" "0,1"
newline
bitfld.long 0x24 24. "CP0BST3A,Capture 0 triggered by ST3CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 23. "CP0BST2CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x24 22. "CP0BST2CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x24 21. "CP0BST2NA,Capture 0 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 20. "CP0BST2A,Capture 0 triggered by ST2CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 19. "CP0BST1CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x24 18. "CP0BST1CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER1" "0,1"
newline
bitfld.long 0x24 17. "CP0BST1NA,Capture 0 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 16. "CP0BST1A,Capture 0 triggered by ST1CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 15. "CP0BST0CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x24 14. "CP0BST0CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x24 13. "CP0BST0NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 12. "CP0BST0A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
newline
bitfld.long 0x24 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
bitfld.long 0x24 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x24 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
bitfld.long 0x24 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x24 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x24 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x24 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x24 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x24 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x24 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x24 0. "CP0BSW,Capture 0 triggered by software" "0,1"
line.long 0x28 "ST6CAP1TRG,HRTIMER Slave_TIMER6 capture 1 trigger register"
bitfld.long 0x28 31. "CP1BST4CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x28 30. "CP1BST4CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x28 29. "CP1BST4NA,Capture 1 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 28. "CP1BST4A,Capture 1 triggered by ST4CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 27. "CP1BST3CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x28 26. "CP1BST3CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x28 25. "CP1BST3NA,Capture 1 triggered by ST3CH0_O output active to inactive transition" "0,1"
newline
bitfld.long 0x28 24. "CP1BST3A,Capture 1 triggered by ST3CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 23. "CP1BST2CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x28 22. "CP1BST2CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x28 21. "CP1BST2NA,Capture 1 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 20. "CP1BST2A,Capture 1 triggered by ST2CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 19. "CP1BST1CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x28 18. "CP1BST1CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER1" "0,1"
newline
bitfld.long 0x28 17. "CP1BST1NA,Capture 1 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 16. "CP1BST1A,Capture 1 triggered by ST1CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 15. "CP1BST0CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x28 14. "CP1BST0CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x28 13. "CP1BST0NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 12. "CP1BST0A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
newline
bitfld.long 0x28 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
bitfld.long 0x28 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
bitfld.long 0x28 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
bitfld.long 0x28 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x28 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x28 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x28 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
newline
bitfld.long 0x28 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
bitfld.long 0x28 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x28 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x28 0. "CP1BSW,Capture 1 triggered by software" "0,1"
line.long 0x2C "ST6CHOCTL,HRTIMER Slave_TIME6 channel output control register"
bitfld.long 0x2C 23. "BMCH1DTI,Channel 1 dead-time insert in bunch mode" "0,1"
bitfld.long 0x2C 22. "CH1CSEN,Channel 1 carrier-signal mode enable" "0,1"
bitfld.long 0x2C 20.--21. "CH1FLTOS,Channel 1 Fault output state" "0,1,2,3"
bitfld.long 0x2C 19. "ISO1,channel 1 output idle state" "0,1"
bitfld.long 0x2C 18. "BMCH1IEN,Channel 1 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x2C 17. "CH1P,Channel 1 output polarity" "0,1"
bitfld.long 0x2C 14. "BALIAR,Balanced Idle Automatic Resumption" "0,1"
newline
bitfld.long 0x2C 10.--12. "DLYISCH,Delayed IDLE source and channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x2C 9. "DLYISMEN,Delayed IDLE state mode enable" "0,1"
bitfld.long 0x2C 8. "DTEN,Dead time enable" "0,1"
bitfld.long 0x2C 7. "BMCH0DTI,Channel 0 dead-time insert in bunch mode" "0,1"
bitfld.long 0x2C 6. "CH0CSEN,Channel 0 carrier-signal mode enable" "0,1"
bitfld.long 0x2C 4.--5. "CH0FLTOS,Channel 0 Fault output state" "0,1,2,3"
bitfld.long 0x2C 3. "ISO0,Channel 0 output idle state" "0,1"
newline
bitfld.long 0x2C 2. "BMCH0IEN,Channel 0 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x2C 1. "CH0P,Channel 0 output polarity" "0,1"
line.long 0x30 "ST6FLTCTL,HRTIMER Slave_TIME6 fault control register"
bitfld.long 0x30 31. "FLTENPROT,Protect fault enable" "0,1"
bitfld.long 0x30 7. "FLT7EN,Fault 7 enable" "0,1"
bitfld.long 0x30 6. "FLT6EN,Fault 6 enable" "0,1"
bitfld.long 0x30 5. "FLT5EN,Fault 5 enable" "0,1"
bitfld.long 0x30 4. "FLT4EN,Fault 4 enable" "0,1"
bitfld.long 0x30 3. "FLT3EN,Fault 3 enable" "0,1"
bitfld.long 0x30 2. "FLT2EN,Fault 2 enable" "0,1"
newline
bitfld.long 0x30 1. "FLT1EN,Fault 1 enable" "0,1"
bitfld.long 0x30 0. "FLT0EN,Fault 0 enable" "0,1"
line.long 0x34 "ST6CTL1,HRTIMER Slave_TIME6 control register 1"
bitfld.long 0x34 20. "TRGHALFM,Triggered-half mode" "0,1"
bitfld.long 0x34 17. "IMUPD2V,Immediately update compare 2 value PWM mode" "0,1"
bitfld.long 0x34 16. "IMUPD0V,Immediately update compare 0 value PWM mode" "0,1"
bitfld.long 0x34 14.--15. "FEROVM,Fault and event roll-over mode" "0,1,2,3"
bitfld.long 0x34 12.--13. "BMROVM,Bunch mode roll-over mode" "0,1,2,3"
bitfld.long 0x34 10.--11. "ADCROVM,ADC roll-over mode" "0,1,2,3"
bitfld.long 0x34 8.--9. "OUTROVM,Output roll-over mode" "0,1,2,3"
newline
bitfld.long 0x34 6.--7. "ROVM,Roll-over mode" "0,1,2,3"
bitfld.long 0x34 4. "CAM,Center-aligned counting mode" "0,1"
bitfld.long 0x34 2. "TRIG1M,This bit defines when TRIG1M is generated" "0,1"
bitfld.long 0x34 1. "TRIG0M,This bit defines when TRIG0M is generated" "0,1"
bitfld.long 0x34 0. "TRIGEN,Two trigger enable" "0,1"
line.long 0x38 "ST6EXEVFCFG2,HRTIMER Slave_TIME6 external event filter configuration register 2"
hexmask.long.byte 0x38 26.--31. 1. "EXEVXCNT,External event X counter value"
hexmask.long.byte 0x38 8.--13. 1. "EXEVXCNTTHR,External event X counter threshold"
hexmask.long.byte 0x38 4.--7. 1. "EXEVXSEL,External event X selection This bit determines the source of external event X"
bitfld.long 0x38 2. "EXEVXRSTM,External event X reset mode" "0,1"
bitfld.long 0x38 1. "EXEVXCRST,External event X counter reset" "0,1"
bitfld.long 0x38 0. "EXEVXCEN,External event X counter enable" "0,1"
line.long 0x3C "ST6CAPTRGCOM,HRTIMER Slave_TIMER6 capture trigger combination register"
bitfld.long 0x3C 27. "CP1BST7CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 26. "CP1BST7CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 25. "CP1BST7NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 24. "CP1BST7A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 19. "CP1BST5CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 18. "CP1BST5CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 17. "CP1BST5NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
newline
bitfld.long 0x3C 16. "CP1BST5A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 11. "CP0BST7CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 10. "CP0BST7CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER7" "0,1"
bitfld.long 0x3C 9. "CP0BST7NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 8. "CP0BST7A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 3. "CP0BST5CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 2. "CP0BST5CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER5" "0,1"
newline
bitfld.long 0x3C 1. "CP0BST5NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 0. "CP0BST5A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
line.long 0x40 "ST6CNTRSTA,HRTIMER Slave_TIMER6 counter reset and channel 0/1 set/reset request add register"
bitfld.long 0x40 29. "CH1CNTRST,Counter reset for channel 1 output reset" "0,1"
bitfld.long 0x40 28. "CH0CNTRST,Counter reset for channel 0 output reset" "0,1"
bitfld.long 0x40 27. "CH1RSSTEV10,Slave_TIMER5 interconnection event 10 generates channel 1" "0,1"
bitfld.long 0x40 26. "CH1RSSTEV9,Slave_TIMER5 interconnection event 9 generates channel 1" "0,1"
bitfld.long 0x40 25. "CH0RSSTEV10,Slave_TIMER5 interconnection event 10 generates channel 0" "0,1"
bitfld.long 0x40 24. "CH0RSSTEV9,Slave_TIMER5 interconnection event 9 generates channel 0" "0,1"
bitfld.long 0x40 21. "CH1CNTSET,Counter reset for channel 1 output set" "0,1"
newline
bitfld.long 0x40 20. "CH0CNTSET,Counter reset for channel 0 output set" "0,1"
bitfld.long 0x40 19. "CH1SSTEV10,Slave_TIMER5 interconnection event 10 generates channel 1 set request" "0,1"
bitfld.long 0x40 18. "CH1SSTEV9,Slave_TIMER5 interconnection event 9 generates channel 1 set request" "0,1"
bitfld.long 0x40 17. "CH0SSTEV10,Slave_TIMER5 interconnection event 10 generates channel 0 set request" "0,1"
bitfld.long 0x40 16. "CH0SSTEV9,Slave_TIMER5 interconnection event 9 generates channel 1 set request" "0,1"
bitfld.long 0x40 6. "ST7CMP3RST,Slave_TIMER7 compare 3 event resets counter" "0,1"
bitfld.long 0x40 5. "ST7CMP1RST,Slave_TIMER7 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x40 4. "ST7CMP0RST,Slave_TIMER7 compare 0 event resets counter" "0,1"
bitfld.long 0x40 3. "ST5CMP3RST,Slave_TIMER5 compare 3 event resets counter" "0,1"
bitfld.long 0x40 2. "ST5CMP1RST,Slave_TIMER5 compare 1 event resets counter" "0,1"
bitfld.long 0x40 1. "ST5CMP0RST,Slave_TIMER5 compare 0 event resets counter" "0,1"
bitfld.long 0x40 0. "ST4CMP3RST,Slave_TIMER4 compare 3 event resets counter" "0,1"
line.long 0x44 "ST6ACTL,HRTIMER Slave_TIME6 additional control register"
hexmask.long.byte 0x44 25.--31. 1. "DTFCFG,Falling edge dead-time value configure"
hexmask.long.byte 0x44 9.--15. 1. "DTRCFG,Rising edge dead-time value configure"
bitfld.long 0x44 1. "UPBST7,Update by Slave_TIMER7 update event" "0,1"
bitfld.long 0x44 0. "UPBST6,Update by Slave_TIMER6 update event" "0,1"
tree.end
tree "HRTIMER_SLAVE_TIMER7"
base ad:0x40016080
group.long 0x0++0x3
line.long 0x0 "ST7CTL0,HRTIMER Slave_TIME7 control register 0"
hexmask.long.byte 0x0 28.--31. 1. "UPSEL,Update event selection"
bitfld.long 0x0 27. "SHWEN,Shadow registers enable" "0,1"
bitfld.long 0x0 25.--26. "DACTRGS,Trigger source to DAC" "0,1,2,3"
bitfld.long 0x0 24. "UPBMT,Update by Master_TIMER update event" "0,1"
bitfld.long 0x0 23. "UPBST4,Update by Slave_TIMER4 update event" "0,1"
bitfld.long 0x0 22. "UPBST3,Update by Slave_TIMER3 update event" "0,1"
bitfld.long 0x0 21. "UPBST2,Update by Slave_TIMER2 update event" "0,1"
newline
bitfld.long 0x0 20. "UPBST1,Update by Slave_TIMER1 update event" "0,1"
bitfld.long 0x0 19. "UPBST0,Update by Slave_TIMER0 update event" "0,1"
bitfld.long 0x0 18. "UPRST,Update event generated by reset event" "0,1"
bitfld.long 0x0 17. "UPREP,Update event generated by repetition event" "0,1"
bitfld.long 0x0 16. "UPBST5,Update by Slave_TIMER5 update event" "0,1"
bitfld.long 0x0 14.--15. "DELCMP3M,Compare 3 delayed mode" "0,1,2,3"
bitfld.long 0x0 12.--13. "DELCMP1M,Compare 1 delayed mode" "0,1,2,3"
newline
bitfld.long 0x0 11. "SYNISTRT,Synchronous input start timer" "0,1"
bitfld.long 0x0 10. "SYNIRST,Synchronous input reset timer" "0,1"
bitfld.long 0x0 9. "RSYNUPD,Re-synchronized update" "0,1"
bitfld.long 0x0 7.--8. "ALTM,Alternate mode" "0,1,2,3"
bitfld.long 0x0 6. "BLNMEN,Balanced mode enable" "0,1"
bitfld.long 0x0 5. "HALFM,Half mode" "0,1"
bitfld.long 0x0 4. "CNTRSTM,Counter reset mode" "0,1"
newline
bitfld.long 0x0 3. "CTNM,Continuous mode" "0,1"
bitfld.long 0x0 0.--2. "CNTCKDIV,Counter clock division" "0,1,2,3,4,5,6,7"
rgroup.long 0x4++0x3
line.long 0x0 "ST7INTF,HRTIMER Slave_TIME7 interrupt flag register"
bitfld.long 0x0 31. "DIR,Direction" "0,1"
bitfld.long 0x0 21. "CH1F,Channel 1 output flag" "0,1"
bitfld.long 0x0 20. "CH0F,Channel 0 output flag" "0,1"
bitfld.long 0x0 19. "CH1SF,Channel 1 output state flag" "0,1"
bitfld.long 0x0 18. "CH0SF,Channel 0 output state flag" "0,1"
bitfld.long 0x0 17. "BLNIF,Balanced IDLE flag" "0,1"
bitfld.long 0x0 16. "CBLNF,Current balanced flag" "0,1"
newline
bitfld.long 0x0 14. "DLYIIF,Delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x0 13. "RSTIF,Counter reset interrupt flag" "0,1"
bitfld.long 0x0 12. "CH1ONAIF,Channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x0 11. "CH1OAIF,Channel 1 output active interrupt flag" "0,1"
bitfld.long 0x0 10. "CH0ONAIF,Channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x0 9. "CH0OAIF,Channel 0 output active interrupt flag" "0,1"
bitfld.long 0x0 8. "CAP1IF,Capture 1 interrupt flag" "0,1"
newline
bitfld.long 0x0 7. "CAP0IF,Capture 0 interrupt flag" "0,1"
bitfld.long 0x0 6. "UPIF,Update interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIF,Repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IF,Compare 3 interrupt flag" "0,1"
bitfld.long 0x0 2. "CMP2IF,Compare 2 interrupt flag" "0,1"
bitfld.long 0x0 1. "CMP1IF,Compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IF,Compare 0 interrupt flag" "0,1"
wgroup.long 0x8++0x3
line.long 0x0 "ST7INTC,HRTIMER Slave_TIME7 interrupt flag clear register"
bitfld.long 0x0 14. "DLYIIFC,Clear delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x0 13. "RSTIFC,Clear counter reset interrupt flag" "0,1"
bitfld.long 0x0 12. "CH1ONAIFC,Clear channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x0 11. "CH1OAIFC,Clear channel 1 output active interrupt flag" "0,1"
bitfld.long 0x0 10. "CH0ONAIFC,Clear channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x0 9. "CH0OAIFC,Clear channel 0 output active interrupt flag" "0,1"
bitfld.long 0x0 8. "CAP1IFC,Clear capture 1 interrupt flag" "0,1"
newline
bitfld.long 0x0 7. "CAP0IFC,Clear capture 0 interrupt flag" "0,1"
bitfld.long 0x0 6. "UPIFC,Clear update interrupt flag" "0,1"
bitfld.long 0x0 4. "REPIFC,Clear repetition interrupt flag" "0,1"
bitfld.long 0x0 3. "CMP3IFC,Clear compare 3 interrupt flag" "0,1"
bitfld.long 0x0 2. "CMP2IFC,Clear compare 2 interrupt flag" "0,1"
bitfld.long 0x0 1. "CMP1IFC,Clear compare 1 interrupt flag" "0,1"
bitfld.long 0x0 0. "CMP0IFC,Clear compare 0 interrupt flag" "0,1"
group.long 0xC++0x23
line.long 0x0 "ST7DMAINTEN,HRTIMER Slave_TIME7 DMA and interrupt enable register"
bitfld.long 0x0 30. "DLYIDEN,Delayed IDLE mode entry DMA request enable" "0,1"
bitfld.long 0x0 29. "RSTDEN,Counter reset DMA request enable" "0,1"
bitfld.long 0x0 28. "CH1ONADEN,Channel 1 output inactive DMA request enable" "0,1"
bitfld.long 0x0 27. "CH1OADEN,Channel 1 output active DMA request enable" "0,1"
bitfld.long 0x0 26. "CH0ONADEN,Channel 0 output inactive DMA request enable" "0,1"
bitfld.long 0x0 25. "CH0OADEN,Channel 0 output active DMA request enable" "0,1"
bitfld.long 0x0 24. "CAP1DEN,Capture 1 DMA request enable" "0,1"
newline
bitfld.long 0x0 23. "CAP0DEN,Capture 0 DMA request enable" "0,1"
bitfld.long 0x0 22. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x0 20. "REPDEN,Repetition DMA request enable" "0,1"
bitfld.long 0x0 19. "CMP3DEN,Compare 3 DMA request enable" "0,1"
bitfld.long 0x0 18. "CMP2DEN,Compare 2 DMA request enable" "0,1"
bitfld.long 0x0 17. "CMP1DEN,Compare 1 DMA request enable" "0,1"
bitfld.long 0x0 16. "CMP0DEN,Compare 0 DMA request enable" "0,1"
newline
bitfld.long 0x0 14. "DLYIIE,Delayed IDLE mode entry interrupt enable" "0,1"
bitfld.long 0x0 13. "RSTIE,Counter reset interrupt enable" "0,1"
bitfld.long 0x0 12. "CH1ONAIE,Channel 1 output inactive interrupt enable" "0,1"
bitfld.long 0x0 11. "CH1OAIE,Channel 1 output active interrupt enable" "0,1"
bitfld.long 0x0 10. "CH0ONAIE,Channel 0 output inactive interrupt enable" "0,1"
bitfld.long 0x0 9. "CH0OAIE,Channel 0 output active interrupt enable" "0,1"
bitfld.long 0x0 8. "CAP1IE,Capture 1 interrupt enable" "0,1"
newline
bitfld.long 0x0 7. "CAP0IE,Capture 0 interrupt enable" "0,1"
bitfld.long 0x0 6. "UPIE,Update interrupt enable" "0,1"
bitfld.long 0x0 4. "REPIE,Repetition interrupt enable" "0,1"
bitfld.long 0x0 3. "CMP3IE,Compare 3 interrupt enable" "0,1"
bitfld.long 0x0 2. "CMP2IE,Compare 2 interrupt enable" "0,1"
bitfld.long 0x0 1. "CMP1IE,Compare 1 interrupt enable" "0,1"
bitfld.long 0x0 0. "CMP0IE,Compare 0 interrupt enable" "0,1"
line.long 0x4 "ST7CNT,HRTIMER Slave_TIME7 counter register"
hexmask.long.word 0x4 0.--15. 1. "CNT,The current counter value"
line.long 0x8 "ST7CAR,HRTIMER Slave_TIME7 counter auto reload register"
hexmask.long.word 0x8 0.--15. 1. "CARL,Counter auto reload value"
line.long 0xC "ST7CREP,HRTIMER Slave_TIME7 counter repetition register"
hexmask.long.byte 0xC 0.--7. 1. "CREP,Counter repetition value"
line.long 0x10 "ST7CMP0V,HRTIMER Slave_TIME7 compare 0 value register"
hexmask.long.word 0x10 0.--15. 1. "CMP0VAL,Compare 0 value"
line.long 0x14 "ST7CMP0CP,HRTIMER Slave_TIME7 compare 0 composite register"
hexmask.long.byte 0x14 16.--23. 1. "CREP,Counter repetition value"
hexmask.long.word 0x14 0.--15. 1. "CMP0VAL,Compare 0 value"
line.long 0x18 "ST7CMP1V,HRTIMER Slave_TIME7 compare 1 value register"
hexmask.long.word 0x18 0.--15. 1. "CMP1VAL,Compare 1 value"
line.long 0x1C "ST7CMP2V,HRTIMER Slave_TIME7 compare 2 value register"
hexmask.long.word 0x1C 0.--15. 1. "CMP2VAL,Compare 2 value"
line.long 0x20 "ST7CMP3V,HRTIMER Slave_TIME7 compare 3 value register"
hexmask.long.word 0x20 0.--15. 1. "CMP3VAL,Compare 3 value"
rgroup.long 0x30++0x7
line.long 0x0 "ST7CAP0V,HRTIMER Slave_TIME7 capture 0 value register"
bitfld.long 0x0 16. "DIR,Slave_timer 0 capture 1 direction status" "0,1"
hexmask.long.word 0x0 0.--15. 1. "CAP0VAL,Capture 0 value"
line.long 0x4 "ST7CAP1V,HRTIMER Slave_TIME7 capture 1 value register"
bitfld.long 0x4 16. "DIR,Slave_Timer 0 capture 1 direction status" "0,1"
hexmask.long.word 0x4 0.--15. 1. "CAP1VAL,Capture 1 value"
group.long 0x38++0x47
line.long 0x0 "ST7DTCTL,HRTIMER Slave_TIME7 dead-time control register"
bitfld.long 0x0 31. "DTFSVPROT,Dead-time falling edge protection for value and sign" "0,1"
bitfld.long 0x0 30. "DTFSPROT,Dead-time falling edge protection for sign" "0,1"
bitfld.long 0x0 25. "DTFS,The sign of falling edge dead-time value" "0,1"
hexmask.long.word 0x0 16.--24. 1. "DTFCFG,Falling edge dead-time value"
bitfld.long 0x0 15. "DTRSVPROT,Dead-time rising edge protection for value and sign" "0,1"
bitfld.long 0x0 14. "DTRSPROT,Dead-time rising edge protection for sign" "0,1"
hexmask.long.byte 0x0 10.--13. 1. "DTGCKDIV,Dead time clock division"
newline
bitfld.long 0x0 9. "DTRS,The sign of rising edge dead-time value" "0,1"
hexmask.long.word 0x0 0.--8. 1. "DTRCFG,Rising edge dead-time value"
line.long 0x4 "ST7CH0SET,HRTIMER Slave_TIME7 channel 0 set request register"
bitfld.long 0x4 31. "CH0SUP,Update event generates channel 0 set request" "0,1"
bitfld.long 0x4 30. "CH0SEXEV9,External event 9 generates channel 0 set request" "0,1"
bitfld.long 0x4 29. "CH0SEXEV8,External event 8 generates channel 0 set request" "0,1"
bitfld.long 0x4 28. "CH0SEXEV7,External event 7 generates channel 0 set request" "0,1"
bitfld.long 0x4 27. "CH0SEXEV6,External event 6 generates channel 0 set request" "0,1"
bitfld.long 0x4 26. "CH0SEXEV5,External event 5 generates channel 0 set request" "0,1"
bitfld.long 0x4 25. "CH0SEXEV4,External event 4 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 24. "CH0SEXEV3,External event 3 generates channel 0 set request" "0,1"
bitfld.long 0x4 23. "CH0SEXEV2,External event 2 generates channel 0 set request" "0,1"
bitfld.long 0x4 22. "CH0SEXEV1,External event 1 generates channel 0 set request" "0,1"
bitfld.long 0x4 21. "CH0SEXEV0,External event 0 generates channel 0 set request" "0,1"
bitfld.long 0x4 20. "CH0SSTEV8,interconnection event 8 generates channel 0 set request" "0,1"
bitfld.long 0x4 19. "CH0SSTEV7,interconnection event 7 generates channel 0 set request" "0,1"
bitfld.long 0x4 18. "CH0SSTEV6,interconnection event 6 generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 17. "CH0SSTEV5,interconnection event 5 generates channel 0 set request" "0,1"
bitfld.long 0x4 16. "CH0SSTEV4,interconnection event 4 generates channel 0 set request" "0,1"
bitfld.long 0x4 15. "CH0SSTEV3,interconnection event 3 generates channel 0 set request" "0,1"
bitfld.long 0x4 14. "CH0SSTEV2,interconnection event 2 generates channel 0 set request" "0,1"
bitfld.long 0x4 13. "CH0SSTEV1,interconnection event 1 generates channel 0 set request" "0,1"
bitfld.long 0x4 12. "CH0SSTEV0,interconnection event 0 generates channel 0 set request" "0,1"
bitfld.long 0x4 11. "CH0SMTCMP3,Master_TIMER compare 3 event generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 10. "CH0SMTCMP2,Master_TIMER compare 2 event generates channel 0 set request" "0,1"
bitfld.long 0x4 9. "CH0SMTCMP1,Master_TIMER compare 1 event generates channel 0 set request" "0,1"
bitfld.long 0x4 8. "CH0SMTCMP0,Master_TIMER compare 0 event generates channel 0 set request" "0,1"
bitfld.long 0x4 7. "CH0SMTPER,Master_TIMER period event generates channel 0 set request" "0,1"
bitfld.long 0x4 6. "CH0SCMP3,compare 3 event generates channel 0 set request" "0,1"
bitfld.long 0x4 5. "CH0SCMP2,compare 2 event generates channel 0 set request" "0,1"
bitfld.long 0x4 4. "CH0SCMP1,compare 1 event generates channel 0 set request" "0,1"
newline
bitfld.long 0x4 3. "CH0SCMP0,compare 0 event generates channel 0 set request" "0,1"
bitfld.long 0x4 2. "CH0SPER,period event generates channel 0 set request" "0,1"
bitfld.long 0x4 1. "CH0SRST,reset event generates channel 0 set request" "0,1"
bitfld.long 0x4 0. "CH0SSEV,Software event generates channel 0 set request" "0,1"
line.long 0x8 "ST7CH0RST,HRTIMER Slave_TIME7 channel 0 reset request register"
bitfld.long 0x8 31. "CH0RSUP,Update event generates channel 0 reset request" "0,1"
bitfld.long 0x8 30. "CH0RSEXEV9,External event 9 generates channel 0 reset request" "0,1"
bitfld.long 0x8 29. "CH0RSEXEV8,External event 8 generates channel 0 reset request" "0,1"
bitfld.long 0x8 28. "CH0RSEXEV7,External event 7 generates channel 0 reset request" "0,1"
bitfld.long 0x8 27. "CH0RSEXEV6,External event 6 generates channel 0 reset request" "0,1"
bitfld.long 0x8 26. "CH0RSEXEV5,External event 5 generates channel 0 reset request" "0,1"
bitfld.long 0x8 25. "CH0RSEXEV4,External event 4 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 24. "CH0RSEXEV3,External event 3 generates channel 0 reset request" "0,1"
bitfld.long 0x8 23. "CH0RSEXEV2,External event 2 generates channel 0 reset request" "0,1"
bitfld.long 0x8 22. "CH0RSEXEV1,External event 1 generates channel 0 reset request" "0,1"
bitfld.long 0x8 21. "CH0RSEXEV0,External event 0 generates channel 0 reset request" "0,1"
bitfld.long 0x8 20. "CH0RSSTEV8,interconnection event 8 generates channel 0 reset request" "0,1"
bitfld.long 0x8 19. "CH0RSSTEV7,interconnection event 7 generates channel 0 reset request" "0,1"
bitfld.long 0x8 18. "CH0RSSTEV6,interconnection event 6 generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 17. "CH0RSSTEV5,interconnection event 5 generates channel 0 reset request" "0,1"
bitfld.long 0x8 16. "CH0RSSTEV4,interconnection event 4 generates channel 0 reset request" "0,1"
bitfld.long 0x8 15. "CH0RSSTEV3,interconnection event 3 generates channel 0 reset request" "0,1"
bitfld.long 0x8 14. "CH0RSSTEV2,interconnection event 2 generates channel 0 reset request" "0,1"
bitfld.long 0x8 13. "CH0RSSTEV1,interconnection event 1 generates channel 0 reset request" "0,1"
bitfld.long 0x8 12. "CH0RSSTEV0,interconnection event 0 generates channel 0 reset request" "0,1"
bitfld.long 0x8 11. "CH0RSMTCMP3,Master_TIMER compare 3 event generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 10. "CH0RSMTCMP2,Master_TIMER compare 2 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 9. "CH0RSMTCMP1,Master_TIMER compare 1 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 8. "CH0RSMTCMP0,Master_TIMER compare 0 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 7. "CH0RSMTPER,Master_TIMER period event generates channel 0 reset request" "0,1"
bitfld.long 0x8 6. "CH0RSCMP3,compare 3 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 5. "CH0RSCMP2,compare 2 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 4. "CH0RSCMP1,compare 1 event generates channel 0 reset request" "0,1"
newline
bitfld.long 0x8 3. "CH0RSCMP0,compare 0 event generates channel 0 reset request" "0,1"
bitfld.long 0x8 2. "CH0RSPER,period event generates channel 0 reset request" "0,1"
bitfld.long 0x8 1. "CH0RSRST,reset event generates channel 0 reset request" "0,1"
bitfld.long 0x8 0. "CH0RSSEV,Software event generates channel 0 reset request" "0,1"
line.long 0xC "ST7CH1SET,HRTIMER Slave_TIME7 channel 1 set request register"
bitfld.long 0xC 31. "CH1SUP,Update event generates channel 1 set request" "0,1"
bitfld.long 0xC 30. "CH1SEXEV9,External event 9 generates channel 1 set request" "0,1"
bitfld.long 0xC 29. "CH1SEXEV8,External event 8 generates channel 1 set request" "0,1"
bitfld.long 0xC 28. "CH1SEXEV7,External event 7 generates channel 1 set request" "0,1"
bitfld.long 0xC 27. "CH1SEXEV6,External event 6 generates channel 1 set request" "0,1"
bitfld.long 0xC 26. "CH1SEXEV5,External event 5 generates channel 1 set request" "0,1"
bitfld.long 0xC 25. "CH1SEXEV4,External event 4 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 24. "CH1SEXEV3,External event 3 generates channel 1 set request" "0,1"
bitfld.long 0xC 23. "CH1SEXEV2,External event 2 generates channel 1 set request" "0,1"
bitfld.long 0xC 22. "CH1SEXEV1,External event 1 generates channel 1 set request" "0,1"
bitfld.long 0xC 21. "CH1SEXEV0,External event 0 generates channel 1 set request" "0,1"
bitfld.long 0xC 20. "CH1SSTEV8,interconnection event 8 generates channel 1 set request" "0,1"
bitfld.long 0xC 19. "CH1SSTEV7,interconnection event 7 generates channel 1 set request" "0,1"
bitfld.long 0xC 18. "CH1SSTEV6,interconnection event 6 generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 17. "CH1SSTEV5,interconnection event 5 generates channel 1 set request" "0,1"
bitfld.long 0xC 16. "CH1SSTEV4,interconnection event 4 generates channel 1 set request" "0,1"
bitfld.long 0xC 15. "CH1SSTEV3,interconnection event 3 generates channel 1 set request" "0,1"
bitfld.long 0xC 14. "CH1SSTEV2,interconnection event 2 generates channel 1 set request" "0,1"
bitfld.long 0xC 13. "CH1SSTEV1,interconnection event 1 generates channel 1 set request" "0,1"
bitfld.long 0xC 12. "CH1SSTEV0,interconnection event 0 generates channel 1 set request" "0,1"
bitfld.long 0xC 11. "CH1SMTCMP3,Master_TIMER compare 3 event generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 10. "CH1SMTCMP2,Master_TIMER compare 2 event generates channel 1 set request" "0,1"
bitfld.long 0xC 9. "CH1SMTCMP1,Master_TIMER compare 1 event generates channel 1 set request" "0,1"
bitfld.long 0xC 8. "CH1SMTCMP0,Master_TIMER compare 0 event generates channel 1 set request" "0,1"
bitfld.long 0xC 7. "CH1SMTPER,Master_TIMER period event generates channel 1 set request" "0,1"
bitfld.long 0xC 6. "CH1SCMP3,compare 3 event generates channel 1 set request" "0,1"
bitfld.long 0xC 5. "CH1SCMP2,compare 2 event generates channel 1 set request" "0,1"
bitfld.long 0xC 4. "CH1SCMP1,compare 1 event generates channel 1 set request" "0,1"
newline
bitfld.long 0xC 3. "CH1SCMP0,compare 0 event generates channel 1 set request" "0,1"
bitfld.long 0xC 2. "CH1SPER,period event generates channel 1 set request" "0,1"
bitfld.long 0xC 1. "CH1SRST,reset event generates channel 1 set request" "0,1"
bitfld.long 0xC 0. "CH1SSEV,Software event generates channel 1 set request" "0,1"
line.long 0x10 "ST7CH1RST,HRTIMER Slave_TIME7 channel 1 reset request register"
bitfld.long 0x10 31. "CH1RSUP,Update event generates channel 1 reset request" "0,1"
bitfld.long 0x10 30. "CH1RSEXEV9,External event 9 generates channel 1 reset request" "0,1"
bitfld.long 0x10 29. "CH1RSEXEV8,External event 8 generates channel 1 reset request" "0,1"
bitfld.long 0x10 28. "CH1RSEXEV7,External event 7 generates channel 1 reset request" "0,1"
bitfld.long 0x10 27. "CH1RSEXEV6,External event 6 generates channel 1 reset request" "0,1"
bitfld.long 0x10 26. "CH1RSEXEV5,External event 5 generates channel 1 reset request" "0,1"
bitfld.long 0x10 25. "CH1RSEXEV4,External event 4 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 24. "CH1RSEXEV3,External event 3 generates channel 1 reset request" "0,1"
bitfld.long 0x10 23. "CH1RSEXEV2,External event 2 generates channel 1 reset request" "0,1"
bitfld.long 0x10 22. "CH1RSEXEV1,External event 1 generates channel 1 reset request" "0,1"
bitfld.long 0x10 21. "CH1RSEXEV0,External event 0 generates channel 1 reset request" "0,1"
bitfld.long 0x10 20. "CH1RSSTEV8,interconnection event 8 generates channel 1 reset request" "0,1"
bitfld.long 0x10 19. "CH1RSSTEV7,interconnection event 7 generates channel 1 reset request" "0,1"
bitfld.long 0x10 18. "CH1RSSTEV6,interconnection event 6 generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 17. "CH1RSSTEV5,interconnection event 5 generates channel 1 reset request" "0,1"
bitfld.long 0x10 16. "CH1RSSTEV4,interconnection event 4 generates channel 1 reset request" "0,1"
bitfld.long 0x10 15. "CH1RSSTEV3,interconnection event 3 generates channel 1 reset request" "0,1"
bitfld.long 0x10 14. "CH1RSSTEV2,interconnection event 2 generates channel 1 reset request" "0,1"
bitfld.long 0x10 13. "CH1RSSTEV1,interconnection event 1 generates channel 1 reset request" "0,1"
bitfld.long 0x10 12. "CH1RSSTEV0,interconnection event 0 generates channel 1 reset request" "0,1"
bitfld.long 0x10 11. "CH1RSMTCMP3,Master_TIMER compare 3 event generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 10. "CH1RSMTCMP2,Master_TIMER compare 2 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 9. "CH1RSMTCMP1,Master_TIMER compare 1 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 8. "CH1RSMTCMP0,Master_TIMER compare 0 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 7. "CH1RSMTPER,Master_TIMER period event generates channel 1 reset request" "0,1"
bitfld.long 0x10 6. "CH1RSCMP3,compare 3 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 5. "CH1RSCMP2,compare 2 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 4. "CH1RSCMP1,compare 1 event generates channel 1 reset request" "0,1"
newline
bitfld.long 0x10 3. "CH1RSCMP0,compare 0 event generates channel 1 reset request" "0,1"
bitfld.long 0x10 2. "CH1RSPER,period event generates channel 1 reset request" "0,1"
bitfld.long 0x10 1. "CH1RSRST,reset event generates channel 1 reset request" "0,1"
bitfld.long 0x10 0. "CH1RSSEV,Software event generates channel 1 reset request" "0,1"
line.long 0x14 "ST7EXEVFCFG0,HRTIMER Slave_TIME7 external event filter configuration register 0"
hexmask.long.byte 0x14 25.--29. 1. "EXEV4FM,External event 4 filter mode"
bitfld.long 0x14 24. "EXEV4MEEN,External event 4 memorized enable" "0,1"
hexmask.long.byte 0x14 19.--23. 1. "EXEV3FM,External event 3 filter mode"
bitfld.long 0x14 18. "EXEV3MEEN,External event 3 memorized enable" "0,1"
hexmask.long.byte 0x14 13.--17. 1. "EXEV2FM,External event 2 filter mode"
bitfld.long 0x14 12. "EXEV2MEEN,External event 2 memorized enable" "0,1"
hexmask.long.byte 0x14 7.--11. 1. "EXEV1FM,External event 1 filter mode"
newline
bitfld.long 0x14 6. "EXEV1MEEN,External event 1 memorized enable" "0,1"
hexmask.long.byte 0x14 1.--5. 1. "EXEV0FM,External event 0 filter mode"
bitfld.long 0x14 0. "EXEV0MEEN,External event 0 memory" "0,1"
line.long 0x18 "ST7EXEVFCFG1,HRTIMER Slave_TIME7 external event filter configuration register 1"
hexmask.long.byte 0x18 25.--29. 1. "EXEV9FM,External event 9 filter mode"
bitfld.long 0x18 24. "EXEV9MEEN,External event 9 memorized enable" "0,1"
hexmask.long.byte 0x18 19.--23. 1. "EXEV8FM,External event 8 filter mode"
bitfld.long 0x18 18. "EXEV8MEEN,External event 8 memorized enable" "0,1"
hexmask.long.byte 0x18 13.--17. 1. "EXEV7FM,External event 7 filter mode"
bitfld.long 0x18 12. "EXEV7MEEN,External event 7 memorized enable" "0,1"
hexmask.long.byte 0x18 7.--11. 1. "EXEV6FM,External event 6 filter mode"
newline
bitfld.long 0x18 6. "EXEV6MEEN,External event 6 memorized enable" "0,1"
hexmask.long.byte 0x18 1.--5. 1. "EXEV5FM,External event 5 filter mode"
bitfld.long 0x18 0. "EXEV5MEEN,External event 0 memorized enable" "0,1"
line.long 0x1C "ST7CNTRST,HRTIMER Slave_TIMER7 counter reset register"
bitfld.long 0x1C 31. "ST4CMP1RST,Slave_TIMER4 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 30. "ST3CMP3RST,Slave_TIMER3 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 29. "ST3CMP1RST,Slave_TIMER3 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 28. "ST3CMP0RST,Slave_TIMER3 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 27. "ST2CMP3RST,Slave_TIMER2 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 26. "ST2CMP1RST,Slave_TIMER2 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 25. "ST2CMP0RST,Slave_TIMER2 compare 0 event resets counter" "0,1"
newline
bitfld.long 0x1C 24. "ST1CMP3RST,Slave_TIMER1 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 23. "ST1CMP1RST,Slave_TIMER1 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 22. "ST1CMP0RST,Slave_TIMER1 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 21. "ST0CMP3RST,Slave_TIMER0 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 20. "ST0CMP1RST,Slave_TIMER0 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 19. "ST0CMP0RST,Slave_TIMER0 compare 0 event resets counter" "0,1"
bitfld.long 0x1C 18. "EXEV9RST,External event 9 resets counter" "0,1"
newline
bitfld.long 0x1C 17. "EXEV8RST,External event 8 resets counter" "0,1"
bitfld.long 0x1C 16. "EXEV7RST,External event 7 resets counter" "0,1"
bitfld.long 0x1C 15. "EXEV6RST,External event 6 resets counter" "0,1"
bitfld.long 0x1C 14. "EXEV5RST,External event 5 resets counter" "0,1"
bitfld.long 0x1C 13. "EXEV4RST,External event 4 resets counter" "0,1"
bitfld.long 0x1C 12. "EXEV3RST,External event 3 resets counter" "0,1"
bitfld.long 0x1C 11. "EXEV2RST,External event 2 resets counter" "0,1"
newline
bitfld.long 0x1C 10. "EXEV1RST,External event 1 resets counter" "0,1"
bitfld.long 0x1C 9. "EXEV0RST,External event 0 resets counter" "0,1"
bitfld.long 0x1C 8. "MTCMP3RST,Master_TIMER compare 3 event resets counter" "0,1"
bitfld.long 0x1C 7. "MTCMP2RST,Master_TIMER compare 2 event resets counter" "0,1"
bitfld.long 0x1C 6. "MTCMP1RST,Master_TIMER compare 1 event resets counter" "0,1"
bitfld.long 0x1C 5. "MTCMP0RST,Master_TIMER compare 0 event resets counter" "0,1"
bitfld.long 0x1C 4. "MTPERRST,Master_TIMER period event resets counter" "0,1"
newline
bitfld.long 0x1C 3. "CMP3RST,Slave_TIMER7 compare 3 event resets counter" "0,1"
bitfld.long 0x1C 2. "CMP1RST,Slave_TIMER7 compare 1 event resets counter" "0,1"
bitfld.long 0x1C 1. "UPRST,Slave_TIMER7 update event resets counter" "0,1"
bitfld.long 0x1C 0. "ST4CMP0RST,Slave_TIMER4 compare 0 event resets counter" "0,1"
line.long 0x20 "ST7CSCTL,HRTIMER Slave_TIME7 carrier-signal control register"
hexmask.long.byte 0x20 7.--10. 1. "CSFSTPW,First carrier-signal pulse width"
bitfld.long 0x20 4.--6. "CSDTY,Carrier signal duty cycle" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x20 0.--3. 1. "CSPRD,Carrier signal period"
line.long 0x24 "ST7CAP0TRG,HRTIMER Slave_TIMER7 capture 0 trigger register"
bitfld.long 0x24 31. "CP0BST4CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x24 30. "CP0BST4CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x24 29. "CP0BST4NA,Capture 0 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 28. "CP0BST4A,Capture 0 triggered by ST4CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 27. "CP0BST3CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x24 26. "CP0BST3CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x24 25. "CP0BST3NA,Capture 0 triggered by ST3CH0_O output active to inactive transition" "0,1"
newline
bitfld.long 0x24 24. "CP0BST3A,Capture 0 triggered by ST3CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 23. "CP0BST2CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x24 22. "CP0BST2CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x24 21. "CP0BST2NA,Capture 0 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 20. "CP0BST2A,Capture 0 triggered by ST2CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 19. "CP0BST1CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x24 18. "CP0BST1CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER1" "0,1"
newline
bitfld.long 0x24 17. "CP0BST1NA,Capture 0 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 16. "CP0BST1A,Capture 0 triggered by ST1CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 15. "CP0BST0CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x24 14. "CP0BST0CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x24 13. "CP0BST0NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x24 12. "CP0BST0A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x24 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
newline
bitfld.long 0x24 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
bitfld.long 0x24 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x24 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
bitfld.long 0x24 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x24 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x24 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x24 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x24 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x24 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x24 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x24 0. "CP0BSW,Capture 0 triggered by software" "0,1"
line.long 0x28 "ST7CAP1TRG,HRTIMER Slave_TIMER7 capture 1 trigger register"
bitfld.long 0x28 31. "CP1BST4CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x28 30. "CP1BST4CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x28 29. "CP1BST4NA,Capture 1 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 28. "CP1BST4A,Capture 1 triggered by ST4CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 27. "CP1BST3CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x28 26. "CP1BST3CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x28 25. "CP1BST3NA,Capture 1 triggered by ST3CH0_O output active to inactive transition" "0,1"
newline
bitfld.long 0x28 24. "CP1BST3A,Capture 1 triggered by ST3CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 23. "CP1BST2CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x28 22. "CP1BST2CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x28 21. "CP1BST2NA,Capture 1 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 20. "CP1BST2A,Capture 1 triggered by ST2CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 19. "CP1BST1CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x28 18. "CP1BST1CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER1" "0,1"
newline
bitfld.long 0x28 17. "CP1BST1NA,Capture 1 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 16. "CP1BST1A,Capture 1 triggered by ST1CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 15. "CP1BST0CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x28 14. "CP1BST0CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x28 13. "CP1BST0NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x28 12. "CP1BST0A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x28 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
newline
bitfld.long 0x28 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
bitfld.long 0x28 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
bitfld.long 0x28 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
bitfld.long 0x28 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x28 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x28 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x28 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
newline
bitfld.long 0x28 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
bitfld.long 0x28 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x28 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x28 0. "CP1BSW,Capture 1 triggered by software" "0,1"
line.long 0x2C "ST7CHOCTL,HRTIMER Slave_TIME7 channel output control register"
bitfld.long 0x2C 23. "BMCH1DTI,Channel 1 dead-time insert in bunch mode" "0,1"
bitfld.long 0x2C 22. "CH1CSEN,Channel 1 carrier-signal mode enable" "0,1"
bitfld.long 0x2C 20.--21. "CH1FLTOS,Channel 1 Fault output state" "0,1,2,3"
bitfld.long 0x2C 19. "ISO1,channel 1 output idle state" "0,1"
bitfld.long 0x2C 18. "BMCH1IEN,Channel 1 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x2C 17. "CH1P,Channel 1 output polarity" "0,1"
bitfld.long 0x2C 14. "BALIAR,Balanced Idle Automatic Resumption" "0,1"
newline
bitfld.long 0x2C 10.--12. "DLYISCH,Delayed IDLE source and channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x2C 9. "DLYISMEN,Delayed IDLE state mode enable" "0,1"
bitfld.long 0x2C 8. "DTEN,Dead time enable" "0,1"
bitfld.long 0x2C 7. "BMCH0DTI,Channel 0 dead-time insert in bunch mode" "0,1"
bitfld.long 0x2C 6. "CH0CSEN,Channel 0 carrier-signal mode enable" "0,1"
bitfld.long 0x2C 4.--5. "CH0FLTOS,Channel 0 Fault output state" "0,1,2,3"
bitfld.long 0x2C 3. "ISO0,Channel 0 output idle state" "0,1"
newline
bitfld.long 0x2C 2. "BMCH0IEN,Channel 0 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x2C 1. "CH0P,Channel 0 output polarity" "0,1"
line.long 0x30 "ST7FLTCTL,HRTIMER Slave_TIME7 fault control register"
bitfld.long 0x30 31. "FLTENPROT,Protect fault enable" "0,1"
bitfld.long 0x30 7. "FLT7EN,Fault 7 enable" "0,1"
bitfld.long 0x30 6. "FLT6EN,Fault 6 enable" "0,1"
bitfld.long 0x30 5. "FLT5EN,Fault 5 enable" "0,1"
bitfld.long 0x30 4. "FLT4EN,Fault 4 enable" "0,1"
bitfld.long 0x30 3. "FLT3EN,Fault 3 enable" "0,1"
bitfld.long 0x30 2. "FLT2EN,Fault 2 enable" "0,1"
newline
bitfld.long 0x30 1. "FLT1EN,Fault 1 enable" "0,1"
bitfld.long 0x30 0. "FLT0EN,Fault 0 enable" "0,1"
line.long 0x34 "ST7CTL1,HRTIMER Slave_TIME7 control register 1"
bitfld.long 0x34 20. "TRGHALFM,Triggered-half mode" "0,1"
bitfld.long 0x34 17. "IMUPD2V,Immediately update compare 2 value PWM mode" "0,1"
bitfld.long 0x34 16. "IMUPD0V,Immediately update compare 0 value PWM mode" "0,1"
bitfld.long 0x34 14.--15. "FEROVM,Fault and event roll-over mode" "0,1,2,3"
bitfld.long 0x34 12.--13. "BMROVM,Bunch mode roll-over mode" "0,1,2,3"
bitfld.long 0x34 10.--11. "ADCROVM,ADC roll-over mode" "0,1,2,3"
bitfld.long 0x34 8.--9. "OUTROVM,Output roll-over mode" "0,1,2,3"
newline
bitfld.long 0x34 6.--7. "ROVM,Roll-over mode" "0,1,2,3"
bitfld.long 0x34 4. "CAM,Center-aligned counting mode" "0,1"
bitfld.long 0x34 2. "TRIG1M,This bit defines when TRIG1M is generated" "0,1"
bitfld.long 0x34 1. "TRIG0M,This bit defines when TRIG0M is generated" "0,1"
bitfld.long 0x34 0. "TRIGEN,Two trigger enable" "0,1"
line.long 0x38 "ST7EXEVFCFG2,HRTIMER Slave_TIME7 external event filter configuration register 2"
hexmask.long.byte 0x38 26.--31. 1. "EXEVXCNT,External event X counter value"
hexmask.long.byte 0x38 8.--13. 1. "EXEVXCNTTHR,External event X counter threshold"
hexmask.long.byte 0x38 4.--7. 1. "EXEVXSEL,External event X selection This bit determines the source of external event X"
bitfld.long 0x38 2. "EXEVXRSTM,External event X reset mode" "0,1"
bitfld.long 0x38 1. "EXEVXCRST,External event X counter reset" "0,1"
bitfld.long 0x38 0. "EXEVXCEN,External event X counter enable" "0,1"
line.long 0x3C "ST7CAPTRGCOM,HRTIMER Slave_TIMER7 capture trigger combination register"
bitfld.long 0x3C 23. "CP1BST6CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER6" "0,1"
bitfld.long 0x3C 22. "CP1BST6CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER6" "0,1"
bitfld.long 0x3C 21. "CP1BST6NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 20. "CP1BST6A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 19. "CP1BST5CMP1,Capture 1 triggered by compare 1 event of Slave_TIME5" "0,1"
bitfld.long 0x3C 18. "CP1BST5CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 17. "CP1BST5NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
newline
bitfld.long 0x3C 16. "CP1BST5A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 7. "CP0BST6CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER6" "0,1"
bitfld.long 0x3C 6. "CP0BST6CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER6" "0,1"
bitfld.long 0x3C 5. "CP0BST6NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 4. "CP0BST6A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
bitfld.long 0x3C 3. "CP0BST5CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER5" "0,1"
bitfld.long 0x3C 2. "CP0BST5CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER5" "0,1"
newline
bitfld.long 0x3C 1. "CP0BST5NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x3C 0. "CP0BST5A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
line.long 0x40 "ST7CNTRSTA,HRTIMER Slave_TIMER7 counter reset and channel 0/1 set/reset request add register"
bitfld.long 0x40 29. "CH1CNTRST,Counter reset for channel 1 output reset" "0,1"
bitfld.long 0x40 28. "CH0CNTRST,Counter reset for channel 0 output reset" "0,1"
bitfld.long 0x40 27. "CH1RSSTEV10,Slave_TIMER5 interconnection event 10 generates channel 1" "0,1"
bitfld.long 0x40 26. "CH1RSSTEV9,Slave_TIMER5 interconnection event 9 generates channel 1" "0,1"
bitfld.long 0x40 25. "CH0RSSTEV10,Slave_TIMER5 interconnection event 10 generates channel 0" "0,1"
bitfld.long 0x40 24. "CH0RSSTEV9,Slave_TIMER5 interconnection event 9 generates channel 0" "0,1"
bitfld.long 0x40 21. "CH1CNTSET,Counter reset for channel 1 output set" "0,1"
newline
bitfld.long 0x40 20. "CH0CNTSET,Counter reset for channel 0 output set" "0,1"
bitfld.long 0x40 19. "CH1SSTEV10,Slave_TIMER5 interconnection event 10 generates channel 1 set request" "0,1"
bitfld.long 0x40 18. "CH1SSTEV9,Slave_TIMER5 interconnection event 9 generates channel 1 set request" "0,1"
bitfld.long 0x40 17. "CH0SSTEV10,Slave_TIMER5 interconnection event 10 generates channel 0 set request" "0,1"
bitfld.long 0x40 16. "CH0SSTEV9,Slave_TIMER5 interconnection event 9 generates channel 1 set request" "0,1"
bitfld.long 0x40 6. "ST6CMP3RST,Slave_TIMER6 compare 3 event resets counter" "0,1"
bitfld.long 0x40 5. "ST6CMP1RST,Slave_TIMER6 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x40 4. "ST6CMP0RST,Slave_TIMER6 compare 0 event resets counter" "0,1"
bitfld.long 0x40 3. "ST5CMP3RST,Slave_TIMER5 compare 3 event resets counter" "0,1"
bitfld.long 0x40 2. "ST5CMP1RST,Slave_TIMER5 compare 1 event resets counter" "0,1"
bitfld.long 0x40 1. "ST5CMP0RST,Slave_TIMER5 compare 0 event resets counter" "0,1"
bitfld.long 0x40 0. "ST4CMP3RST,Slave_TIMER4 compare 3 event resets counter" "0,1"
line.long 0x44 "ST7ACTL,HRTIMER Slave_TIME7 additional control register"
hexmask.long.byte 0x44 25.--31. 1. "DTFCFG,Falling edge dead-time value configure"
hexmask.long.byte 0x44 9.--15. 1. "DTRCFG,Rising edge dead-time value configure"
bitfld.long 0x44 1. "UPBST7,Update by Slave_TIMER7 update event" "0,1"
bitfld.long 0x44 0. "UPBST6,Update by Slave_TIMER6 update event" "0,1"
tree.end
tree.end
tree "I2C (Inter-Integrated Circuit Interface)"
base ad:0x0
tree "I2C0"
base ad:0x40005400
group.long 0x0++0x17
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 23. "PECEN,PEC Calculation Switch" "0,1"
bitfld.long 0x0 22. "SMBALTEN,SMBus Alert enable" "0,1"
bitfld.long 0x0 21. "SMBDAEN,SMBus device default address enable" "0,1"
bitfld.long 0x0 20. "SMBHAEN,SMBus Host address enable" "0,1"
bitfld.long 0x0 19. "GCEN,Whether or not to response to a General Call" "0,1"
bitfld.long 0x0 18. "WUEN,Wakeup from Deep-sleep mode enable" "0,1"
bitfld.long 0x0 17. "SS,Whether to stretch SCL low when data is not ready in slave mode" "0,1"
bitfld.long 0x0 16. "SBCTL,Slave byte control" "0,1"
newline
bitfld.long 0x0 15. "DENR,DMA enable for reception" "0,1"
bitfld.long 0x0 14. "DENT,DMA enable for transmission" "0,1"
bitfld.long 0x0 12. "ANOFF,Analog noise filter disable" "0,1"
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
bitfld.long 0x0 7. "ERRIE,Error interrupt enable" "0,1"
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0,1"
bitfld.long 0x0 5. "STPDETIE,Stop detection interrupt enable" "0,1"
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "ADDMIE,Address match interrupt enable in slave mode" "0,1"
bitfld.long 0x0 2. "RBNEIE,Receive interrupt enable" "0,1"
bitfld.long 0x0 1. "TIE,Receive interrupt enable" "0,1"
bitfld.long 0x0 0. "I2CEN,I2C peripheral enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 26. "PECTRANS,PEC Transfer" "0,1"
bitfld.long 0x4 25. "AUTOEND,Automatic end mode in master mode" "0,1"
bitfld.long 0x4 24. "RELOAD,Reload mode" "0,1"
hexmask.long.byte 0x4 16.--23. 1. "BYTENUM,Number of bytes to be transferred"
bitfld.long 0x4 15. "NACKEN,Generate NACK in slave mode" "0,1"
bitfld.long 0x4 14. "STOP,Generate a STOP condition on I2C bus" "0,1"
bitfld.long 0x4 13. "START,Generate a START condition on I2C bus" "0,1"
bitfld.long 0x4 12. "HEAD10R,10-bit address header executes read direction only in master receive mode" "0,1"
newline
bitfld.long 0x4 11. "ADD10EN,10-bit addressing mode enable in master mode" "0,1"
bitfld.long 0x4 10. "TRDIR,Transfer direction in master mode" "0,1"
hexmask.long.word 0x4 0.--9. 1. "SADDRESS,Slave address to be sent"
line.long 0x8 "SADDR0,Slave address register 0"
bitfld.long 0x8 15. "ADDRESSEN,I2C address enable" "0,1"
bitfld.long 0x8 10. "ADDFORMAT,Address mode for the I2C slave" "0,1"
bitfld.long 0x8 8.--9. "ADDRESS_8_9,7-bit address or bits 7:1 of a 10-bit address" "0,1,2,3"
hexmask.long.byte 0x8 1.--7. 1. "ADDRESS_1_7,Highest two bits of a 10-bit address"
bitfld.long 0x8 0. "ADDRESS_0,Bit 0 of a 10-bit address" "0,1"
line.long 0xC "SADDR1,Slave address register 1"
bitfld.long 0xC 15. "ADDRESS2EN,Second I2C address enable" "0,1"
bitfld.long 0xC 8.--10. "ADDMSK2,ADDRESS2[7:1] mask" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 1.--7. 1. "ADDRESS2,Second I2C address for the slave"
line.long 0x10 "TIMING,Timing register"
hexmask.long.byte 0x10 28.--31. 1. "PSC,Timing prescaler"
hexmask.long.byte 0x10 20.--23. 1. "SCLDELY,Data setup time"
hexmask.long.byte 0x10 16.--19. 1. "SDADELY,Data hold time"
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period"
line.long 0x14 "TIMEOUT,timeout register"
bitfld.long 0x14 31. "EXTOEN,Extended clock timeout detection enable" "0,1"
hexmask.long.word 0x14 16.--27. 1. "BUSTOB,Bus timeout B"
bitfld.long 0x14 15. "TOEN,Clock timeout detection enable" "0,1"
bitfld.long 0x14 12. "TOIDLE,Idle clock timeout detection" "0,1"
hexmask.long.word 0x14 0.--11. 1. "BUSTOA,Bus timeout A"
rgroup.long 0x18++0x3
line.long 0x0 "STAT,Transfer status register"
hexmask.long.byte 0x0 17.--23. 1. "READDR,Received match address in slave mode"
bitfld.long 0x0 16. "TR,Whether the I2C is a transmitter or a receiver in slave mode" "0,1"
bitfld.long 0x0 15. "I2CBSY,Busy flag" "0,1"
bitfld.long 0x0 13. "SMBALT,SMBus Alert" "0,1"
bitfld.long 0x0 12. "TIMEOUT,TIMEOUT flag" "0,1"
bitfld.long 0x0 11. "PECERR,PEC error" "0,1"
bitfld.long 0x0 10. "OUERR,Overrun/Underrun error in slave mode" "0,1"
bitfld.long 0x0 9. "LOSTARB,Arbitration Lost" "0,1"
newline
bitfld.long 0x0 8. "BERR,Bus error" "0,1"
bitfld.long 0x0 7. "TCR,Transfer complete reload" "0,1"
bitfld.long 0x0 6. "TC,Transfer complete in master mode" "0,1"
bitfld.long 0x0 5. "STPDET,STOP condition is detected on the bus" "0,1"
bitfld.long 0x0 4. "NACK,Not Acknowledge flag" "0,1"
bitfld.long 0x0 3. "ADDSEND,Address received matches in slave mode" "0,1"
bitfld.long 0x0 2. "RBNE,I2C_RDATA is not empty during receiving" "0,1"
bitfld.long 0x0 1. "TI,Transmit interrupt" "0,1"
newline
bitfld.long 0x0 0. "TBE,I2C_TDATA is empty during transmitting" "0,1"
wgroup.long 0x1C++0x3
line.long 0x0 "STATC,Status clear register"
bitfld.long 0x0 13. "SMBALTC,SMBus Alert flag clear" "0,1"
bitfld.long 0x0 12. "TIMEOUTC,TIMEOUT flag clear" "0,1"
bitfld.long 0x0 11. "PECERRC,PEC error flag clear" "0,1"
bitfld.long 0x0 10. "OUERRC,Overrun/Underrun flag clear" "0,1"
bitfld.long 0x0 9. "LOSTARBC,Arbitration Lost flag clear" "0,1"
bitfld.long 0x0 8. "BERRC,Bus error flag clear" "0,1"
bitfld.long 0x0 5. "STPDETC,STPDET flag clear" "0,1"
bitfld.long 0x0 4. "NACKC,Not Acknowledge flag clear" "0,1"
newline
bitfld.long 0x0 3. "ADDSENDC,ADDSEND flag clear" "0,1"
rgroup.long 0x20++0x7
line.long 0x0 "PEC,Packet Error Check register"
hexmask.long.byte 0x0 0.--7. 1. "PECV,Packet Error Checking Value"
line.long 0x4 "RDATA,receive data register"
hexmask.long.byte 0x4 0.--7. 1. "RDATA,Receive data value"
group.long 0x28++0x3
line.long 0x0 "TDATA,Transmit data register"
hexmask.long.byte 0x0 0.--7. 1. "TDATA,Transmit data value"
group.long 0x90++0x3
line.long 0x0 "CTL2,Control register 2"
hexmask.long.byte 0x0 9.--15. 1. "ADDM,Defines which bits of ADDRESS are compared with an incoming address byte"
tree.end
tree "I2C1"
base ad:0x40005800
group.long 0x0++0x17
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 23. "PECEN,PEC Calculation Switch" "0,1"
bitfld.long 0x0 22. "SMBALTEN,SMBus Alert enable" "0,1"
bitfld.long 0x0 21. "SMBDAEN,SMBus device default address enable" "0,1"
bitfld.long 0x0 20. "SMBHAEN,SMBus Host address enable" "0,1"
bitfld.long 0x0 19. "GCEN,Whether or not to response to a General Call" "0,1"
bitfld.long 0x0 18. "WUEN,Wakeup from Deep-sleep mode enable" "0,1"
bitfld.long 0x0 17. "SS,Whether to stretch SCL low when data is not ready in slave mode" "0,1"
bitfld.long 0x0 16. "SBCTL,Slave byte control" "0,1"
newline
bitfld.long 0x0 15. "DENR,DMA enable for reception" "0,1"
bitfld.long 0x0 14. "DENT,DMA enable for transmission" "0,1"
bitfld.long 0x0 12. "ANOFF,Analog noise filter disable" "0,1"
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
bitfld.long 0x0 7. "ERRIE,Error interrupt enable" "0,1"
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0,1"
bitfld.long 0x0 5. "STPDETIE,Stop detection interrupt enable" "0,1"
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "ADDMIE,Address match interrupt enable in slave mode" "0,1"
bitfld.long 0x0 2. "RBNEIE,Receive interrupt enable" "0,1"
bitfld.long 0x0 1. "TIE,Receive interrupt enable" "0,1"
bitfld.long 0x0 0. "I2CEN,I2C peripheral enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 26. "PECTRANS,PEC Transfer" "0,1"
bitfld.long 0x4 25. "AUTOEND,Automatic end mode in master mode" "0,1"
bitfld.long 0x4 24. "RELOAD,Reload mode" "0,1"
hexmask.long.byte 0x4 16.--23. 1. "BYTENUM,Number of bytes to be transferred"
bitfld.long 0x4 15. "NACKEN,Generate NACK in slave mode" "0,1"
bitfld.long 0x4 14. "STOP,Generate a STOP condition on I2C bus" "0,1"
bitfld.long 0x4 13. "START,Generate a START condition on I2C bus" "0,1"
bitfld.long 0x4 12. "HEAD10R,10-bit address header executes read direction only in master receive mode" "0,1"
newline
bitfld.long 0x4 11. "ADD10EN,10-bit addressing mode enable in master mode" "0,1"
bitfld.long 0x4 10. "TRDIR,Transfer direction in master mode" "0,1"
hexmask.long.word 0x4 0.--9. 1. "SADDRESS,Slave address to be sent"
line.long 0x8 "SADDR0,Slave address register 0"
bitfld.long 0x8 15. "ADDRESSEN,I2C address enable" "0,1"
bitfld.long 0x8 10. "ADDFORMAT,Address mode for the I2C slave" "0,1"
bitfld.long 0x8 8.--9. "ADDRESS_8_9,7-bit address or bits 7:1 of a 10-bit address" "0,1,2,3"
hexmask.long.byte 0x8 1.--7. 1. "ADDRESS_1_7,Highest two bits of a 10-bit address"
bitfld.long 0x8 0. "ADDRESS_0,Bit 0 of a 10-bit address" "0,1"
line.long 0xC "SADDR1,Slave address register 1"
bitfld.long 0xC 15. "ADDRESS2EN,Second I2C address enable" "0,1"
bitfld.long 0xC 8.--10. "ADDMSK2,ADDRESS2[7:1] mask" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 1.--7. 1. "ADDRESS2,Second I2C address for the slave"
line.long 0x10 "TIMING,Timing register"
hexmask.long.byte 0x10 28.--31. 1. "PSC,Timing prescaler"
hexmask.long.byte 0x10 20.--23. 1. "SCLDELY,Data setup time"
hexmask.long.byte 0x10 16.--19. 1. "SDADELY,Data hold time"
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period"
line.long 0x14 "TIMEOUT,timeout register"
bitfld.long 0x14 31. "EXTOEN,Extended clock timeout detection enable" "0,1"
hexmask.long.word 0x14 16.--27. 1. "BUSTOB,Bus timeout B"
bitfld.long 0x14 15. "TOEN,Clock timeout detection enable" "0,1"
bitfld.long 0x14 12. "TOIDLE,Idle clock timeout detection" "0,1"
hexmask.long.word 0x14 0.--11. 1. "BUSTOA,Bus timeout A"
rgroup.long 0x18++0x3
line.long 0x0 "STAT,Transfer status register"
hexmask.long.byte 0x0 17.--23. 1. "READDR,Received match address in slave mode"
bitfld.long 0x0 16. "TR,Whether the I2C is a transmitter or a receiver in slave mode" "0,1"
bitfld.long 0x0 15. "I2CBSY,Busy flag" "0,1"
bitfld.long 0x0 13. "SMBALT,SMBus Alert" "0,1"
bitfld.long 0x0 12. "TIMEOUT,TIMEOUT flag" "0,1"
bitfld.long 0x0 11. "PECERR,PEC error" "0,1"
bitfld.long 0x0 10. "OUERR,Overrun/Underrun error in slave mode" "0,1"
bitfld.long 0x0 9. "LOSTARB,Arbitration Lost" "0,1"
newline
bitfld.long 0x0 8. "BERR,Bus error" "0,1"
bitfld.long 0x0 7. "TCR,Transfer complete reload" "0,1"
bitfld.long 0x0 6. "TC,Transfer complete in master mode" "0,1"
bitfld.long 0x0 5. "STPDET,STOP condition is detected on the bus" "0,1"
bitfld.long 0x0 4. "NACK,Not Acknowledge flag" "0,1"
bitfld.long 0x0 3. "ADDSEND,Address received matches in slave mode" "0,1"
bitfld.long 0x0 2. "RBNE,I2C_RDATA is not empty during receiving" "0,1"
bitfld.long 0x0 1. "TI,Transmit interrupt" "0,1"
newline
bitfld.long 0x0 0. "TBE,I2C_TDATA is empty during transmitting" "0,1"
wgroup.long 0x1C++0x3
line.long 0x0 "STATC,Status clear register"
bitfld.long 0x0 13. "SMBALTC,SMBus Alert flag clear" "0,1"
bitfld.long 0x0 12. "TIMEOUTC,TIMEOUT flag clear" "0,1"
bitfld.long 0x0 11. "PECERRC,PEC error flag clear" "0,1"
bitfld.long 0x0 10. "OUERRC,Overrun/Underrun flag clear" "0,1"
bitfld.long 0x0 9. "LOSTARBC,Arbitration Lost flag clear" "0,1"
bitfld.long 0x0 8. "BERRC,Bus error flag clear" "0,1"
bitfld.long 0x0 5. "STPDETC,STPDET flag clear" "0,1"
bitfld.long 0x0 4. "NACKC,Not Acknowledge flag clear" "0,1"
newline
bitfld.long 0x0 3. "ADDSENDC,ADDSEND flag clear" "0,1"
rgroup.long 0x20++0x7
line.long 0x0 "PEC,Packet Error Check register"
hexmask.long.byte 0x0 0.--7. 1. "PECV,Packet Error Checking Value"
line.long 0x4 "RDATA,receive data register"
hexmask.long.byte 0x4 0.--7. 1. "RDATA,Receive data value"
group.long 0x28++0x3
line.long 0x0 "TDATA,Transmit data register"
hexmask.long.byte 0x0 0.--7. 1. "TDATA,Transmit data value"
group.long 0x90++0x3
line.long 0x0 "CTL2,Control register 2"
hexmask.long.byte 0x0 9.--15. 1. "ADDM,Defines which bits of ADDRESS are compared with an incoming address byte"
tree.end
tree "I2C2"
base ad:0x4000C000
group.long 0x0++0x17
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 23. "PECEN,PEC Calculation Switch" "0,1"
bitfld.long 0x0 22. "SMBALTEN,SMBus Alert enable" "0,1"
bitfld.long 0x0 21. "SMBDAEN,SMBus device default address enable" "0,1"
bitfld.long 0x0 20. "SMBHAEN,SMBus Host address enable" "0,1"
bitfld.long 0x0 19. "GCEN,Whether or not to response to a General Call" "0,1"
bitfld.long 0x0 18. "WUEN,Wakeup from Deep-sleep mode enable" "0,1"
bitfld.long 0x0 17. "SS,Whether to stretch SCL low when data is not ready in slave mode" "0,1"
bitfld.long 0x0 16. "SBCTL,Slave byte control" "0,1"
newline
bitfld.long 0x0 15. "DENR,DMA enable for reception" "0,1"
bitfld.long 0x0 14. "DENT,DMA enable for transmission" "0,1"
bitfld.long 0x0 12. "ANOFF,Analog noise filter disable" "0,1"
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
bitfld.long 0x0 7. "ERRIE,Error interrupt enable" "0,1"
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0,1"
bitfld.long 0x0 5. "STPDETIE,Stop detection interrupt enable" "0,1"
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "ADDMIE,Address match interrupt enable in slave mode" "0,1"
bitfld.long 0x0 2. "RBNEIE,Receive interrupt enable" "0,1"
bitfld.long 0x0 1. "TIE,Receive interrupt enable" "0,1"
bitfld.long 0x0 0. "I2CEN,I2C peripheral enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 26. "PECTRANS,PEC Transfer" "0,1"
bitfld.long 0x4 25. "AUTOEND,Automatic end mode in master mode" "0,1"
bitfld.long 0x4 24. "RELOAD,Reload mode" "0,1"
hexmask.long.byte 0x4 16.--23. 1. "BYTENUM,Number of bytes to be transferred"
bitfld.long 0x4 15. "NACKEN,Generate NACK in slave mode" "0,1"
bitfld.long 0x4 14. "STOP,Generate a STOP condition on I2C bus" "0,1"
bitfld.long 0x4 13. "START,Generate a START condition on I2C bus" "0,1"
bitfld.long 0x4 12. "HEAD10R,10-bit address header executes read direction only in master receive mode" "0,1"
newline
bitfld.long 0x4 11. "ADD10EN,10-bit addressing mode enable in master mode" "0,1"
bitfld.long 0x4 10. "TRDIR,Transfer direction in master mode" "0,1"
hexmask.long.word 0x4 0.--9. 1. "SADDRESS,Slave address to be sent"
line.long 0x8 "SADDR0,Slave address register 0"
bitfld.long 0x8 15. "ADDRESSEN,I2C address enable" "0,1"
bitfld.long 0x8 10. "ADDFORMAT,Address mode for the I2C slave" "0,1"
bitfld.long 0x8 8.--9. "ADDRESS_8_9,7-bit address or bits 7:1 of a 10-bit address" "0,1,2,3"
hexmask.long.byte 0x8 1.--7. 1. "ADDRESS_1_7,Highest two bits of a 10-bit address"
bitfld.long 0x8 0. "ADDRESS_0,Bit 0 of a 10-bit address" "0,1"
line.long 0xC "SADDR1,Slave address register 1"
bitfld.long 0xC 15. "ADDRESS2EN,Second I2C address enable" "0,1"
bitfld.long 0xC 8.--10. "ADDMSK2,ADDRESS2[7:1] mask" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 1.--7. 1. "ADDRESS2,Second I2C address for the slave"
line.long 0x10 "TIMING,Timing register"
hexmask.long.byte 0x10 28.--31. 1. "PSC,Timing prescaler"
hexmask.long.byte 0x10 20.--23. 1. "SCLDELY,Data setup time"
hexmask.long.byte 0x10 16.--19. 1. "SDADELY,Data hold time"
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period"
line.long 0x14 "TIMEOUT,timeout register"
bitfld.long 0x14 31. "EXTOEN,Extended clock timeout detection enable" "0,1"
hexmask.long.word 0x14 16.--27. 1. "BUSTOB,Bus timeout B"
bitfld.long 0x14 15. "TOEN,Clock timeout detection enable" "0,1"
bitfld.long 0x14 12. "TOIDLE,Idle clock timeout detection" "0,1"
hexmask.long.word 0x14 0.--11. 1. "BUSTOA,Bus timeout A"
rgroup.long 0x18++0x3
line.long 0x0 "STAT,Transfer status register"
hexmask.long.byte 0x0 17.--23. 1. "READDR,Received match address in slave mode"
bitfld.long 0x0 16. "TR,Whether the I2C is a transmitter or a receiver in slave mode" "0,1"
bitfld.long 0x0 15. "I2CBSY,Busy flag" "0,1"
bitfld.long 0x0 13. "SMBALT,SMBus Alert" "0,1"
bitfld.long 0x0 12. "TIMEOUT,TIMEOUT flag" "0,1"
bitfld.long 0x0 11. "PECERR,PEC error" "0,1"
bitfld.long 0x0 10. "OUERR,Overrun/Underrun error in slave mode" "0,1"
bitfld.long 0x0 9. "LOSTARB,Arbitration Lost" "0,1"
newline
bitfld.long 0x0 8. "BERR,Bus error" "0,1"
bitfld.long 0x0 7. "TCR,Transfer complete reload" "0,1"
bitfld.long 0x0 6. "TC,Transfer complete in master mode" "0,1"
bitfld.long 0x0 5. "STPDET,STOP condition is detected on the bus" "0,1"
bitfld.long 0x0 4. "NACK,Not Acknowledge flag" "0,1"
bitfld.long 0x0 3. "ADDSEND,Address received matches in slave mode" "0,1"
bitfld.long 0x0 2. "RBNE,I2C_RDATA is not empty during receiving" "0,1"
bitfld.long 0x0 1. "TI,Transmit interrupt" "0,1"
newline
bitfld.long 0x0 0. "TBE,I2C_TDATA is empty during transmitting" "0,1"
wgroup.long 0x1C++0x3
line.long 0x0 "STATC,Status clear register"
bitfld.long 0x0 13. "SMBALTC,SMBus Alert flag clear" "0,1"
bitfld.long 0x0 12. "TIMEOUTC,TIMEOUT flag clear" "0,1"
bitfld.long 0x0 11. "PECERRC,PEC error flag clear" "0,1"
bitfld.long 0x0 10. "OUERRC,Overrun/Underrun flag clear" "0,1"
bitfld.long 0x0 9. "LOSTARBC,Arbitration Lost flag clear" "0,1"
bitfld.long 0x0 8. "BERRC,Bus error flag clear" "0,1"
bitfld.long 0x0 5. "STPDETC,STPDET flag clear" "0,1"
bitfld.long 0x0 4. "NACKC,Not Acknowledge flag clear" "0,1"
newline
bitfld.long 0x0 3. "ADDSENDC,ADDSEND flag clear" "0,1"
rgroup.long 0x20++0x7
line.long 0x0 "PEC,Packet Error Check register"
hexmask.long.byte 0x0 0.--7. 1. "PECV,Packet Error Checking Value"
line.long 0x4 "RDATA,receive data register"
hexmask.long.byte 0x4 0.--7. 1. "RDATA,Receive data value"
group.long 0x28++0x3
line.long 0x0 "TDATA,Transmit data register"
hexmask.long.byte 0x0 0.--7. 1. "TDATA,Transmit data value"
group.long 0x90++0x3
line.long 0x0 "CTL2,Control register 2"
hexmask.long.byte 0x0 9.--15. 1. "ADDM,Defines which bits of ADDRESS are compared with an incoming address byte"
tree.end
tree "I2C3"
base ad:0x40005C00
group.long 0x0++0x17
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 23. "PECEN,PEC Calculation Switch" "0,1"
bitfld.long 0x0 22. "SMBALTEN,SMBus Alert enable" "0,1"
bitfld.long 0x0 21. "SMBDAEN,SMBus device default address enable" "0,1"
bitfld.long 0x0 20. "SMBHAEN,SMBus Host address enable" "0,1"
bitfld.long 0x0 19. "GCEN,Whether or not to response to a General Call" "0,1"
bitfld.long 0x0 18. "WUEN,Wakeup from Deep-sleep mode enable" "0,1"
bitfld.long 0x0 17. "SS,Whether to stretch SCL low when data is not ready in slave mode" "0,1"
bitfld.long 0x0 16. "SBCTL,Slave byte control" "0,1"
newline
bitfld.long 0x0 15. "DENR,DMA enable for reception" "0,1"
bitfld.long 0x0 14. "DENT,DMA enable for transmission" "0,1"
bitfld.long 0x0 12. "ANOFF,Analog noise filter disable" "0,1"
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
bitfld.long 0x0 7. "ERRIE,Error interrupt enable" "0,1"
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0,1"
bitfld.long 0x0 5. "STPDETIE,Stop detection interrupt enable" "0,1"
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "ADDMIE,Address match interrupt enable in slave mode" "0,1"
bitfld.long 0x0 2. "RBNEIE,Receive interrupt enable" "0,1"
bitfld.long 0x0 1. "TIE,Receive interrupt enable" "0,1"
bitfld.long 0x0 0. "I2CEN,I2C peripheral enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 26. "PECTRANS,PEC Transfer" "0,1"
bitfld.long 0x4 25. "AUTOEND,Automatic end mode in master mode" "0,1"
bitfld.long 0x4 24. "RELOAD,Reload mode" "0,1"
hexmask.long.byte 0x4 16.--23. 1. "BYTENUM,Number of bytes to be transferred"
bitfld.long 0x4 15. "NACKEN,Generate NACK in slave mode" "0,1"
bitfld.long 0x4 14. "STOP,Generate a STOP condition on I2C bus" "0,1"
bitfld.long 0x4 13. "START,Generate a START condition on I2C bus" "0,1"
bitfld.long 0x4 12. "HEAD10R,10-bit address header executes read direction only in master receive mode" "0,1"
newline
bitfld.long 0x4 11. "ADD10EN,10-bit addressing mode enable in master mode" "0,1"
bitfld.long 0x4 10. "TRDIR,Transfer direction in master mode" "0,1"
hexmask.long.word 0x4 0.--9. 1. "SADDRESS,Slave address to be sent"
line.long 0x8 "SADDR0,Slave address register 0"
bitfld.long 0x8 15. "ADDRESSEN,I2C address enable" "0,1"
bitfld.long 0x8 10. "ADDFORMAT,Address mode for the I2C slave" "0,1"
bitfld.long 0x8 8.--9. "ADDRESS_8_9,7-bit address or bits 7:1 of a 10-bit address" "0,1,2,3"
hexmask.long.byte 0x8 1.--7. 1. "ADDRESS_1_7,Highest two bits of a 10-bit address"
bitfld.long 0x8 0. "ADDRESS_0,Bit 0 of a 10-bit address" "0,1"
line.long 0xC "SADDR1,Slave address register 1"
bitfld.long 0xC 15. "ADDRESS2EN,Second I2C address enable" "0,1"
bitfld.long 0xC 8.--10. "ADDMSK2,ADDRESS2[7:1] mask" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 1.--7. 1. "ADDRESS2,Second I2C address for the slave"
line.long 0x10 "TIMING,Timing register"
hexmask.long.byte 0x10 28.--31. 1. "PSC,Timing prescaler"
hexmask.long.byte 0x10 20.--23. 1. "SCLDELY,Data setup time"
hexmask.long.byte 0x10 16.--19. 1. "SDADELY,Data hold time"
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period"
line.long 0x14 "TIMEOUT,timeout register"
bitfld.long 0x14 31. "EXTOEN,Extended clock timeout detection enable" "0,1"
hexmask.long.word 0x14 16.--27. 1. "BUSTOB,Bus timeout B"
bitfld.long 0x14 15. "TOEN,Clock timeout detection enable" "0,1"
bitfld.long 0x14 12. "TOIDLE,Idle clock timeout detection" "0,1"
hexmask.long.word 0x14 0.--11. 1. "BUSTOA,Bus timeout A"
rgroup.long 0x18++0x3
line.long 0x0 "STAT,Transfer status register"
hexmask.long.byte 0x0 17.--23. 1. "READDR,Received match address in slave mode"
bitfld.long 0x0 16. "TR,Whether the I2C is a transmitter or a receiver in slave mode" "0,1"
bitfld.long 0x0 15. "I2CBSY,Busy flag" "0,1"
bitfld.long 0x0 13. "SMBALT,SMBus Alert" "0,1"
bitfld.long 0x0 12. "TIMEOUT,TIMEOUT flag" "0,1"
bitfld.long 0x0 11. "PECERR,PEC error" "0,1"
bitfld.long 0x0 10. "OUERR,Overrun/Underrun error in slave mode" "0,1"
bitfld.long 0x0 9. "LOSTARB,Arbitration Lost" "0,1"
newline
bitfld.long 0x0 8. "BERR,Bus error" "0,1"
bitfld.long 0x0 7. "TCR,Transfer complete reload" "0,1"
bitfld.long 0x0 6. "TC,Transfer complete in master mode" "0,1"
bitfld.long 0x0 5. "STPDET,STOP condition is detected on the bus" "0,1"
bitfld.long 0x0 4. "NACK,Not Acknowledge flag" "0,1"
bitfld.long 0x0 3. "ADDSEND,Address received matches in slave mode" "0,1"
bitfld.long 0x0 2. "RBNE,I2C_RDATA is not empty during receiving" "0,1"
bitfld.long 0x0 1. "TI,Transmit interrupt" "0,1"
newline
bitfld.long 0x0 0. "TBE,I2C_TDATA is empty during transmitting" "0,1"
wgroup.long 0x1C++0x3
line.long 0x0 "STATC,Status clear register"
bitfld.long 0x0 13. "SMBALTC,SMBus Alert flag clear" "0,1"
bitfld.long 0x0 12. "TIMEOUTC,TIMEOUT flag clear" "0,1"
bitfld.long 0x0 11. "PECERRC,PEC error flag clear" "0,1"
bitfld.long 0x0 10. "OUERRC,Overrun/Underrun flag clear" "0,1"
bitfld.long 0x0 9. "LOSTARBC,Arbitration Lost flag clear" "0,1"
bitfld.long 0x0 8. "BERRC,Bus error flag clear" "0,1"
bitfld.long 0x0 5. "STPDETC,STPDET flag clear" "0,1"
bitfld.long 0x0 4. "NACKC,Not Acknowledge flag clear" "0,1"
newline
bitfld.long 0x0 3. "ADDSENDC,ADDSEND flag clear" "0,1"
rgroup.long 0x20++0x7
line.long 0x0 "PEC,Packet Error Check register"
hexmask.long.byte 0x0 0.--7. 1. "PECV,Packet Error Checking Value"
line.long 0x4 "RDATA,receive data register"
hexmask.long.byte 0x4 0.--7. 1. "RDATA,Receive data value"
group.long 0x28++0x3
line.long 0x0 "TDATA,Transmit data register"
hexmask.long.byte 0x0 0.--7. 1. "TDATA,Transmit data value"
group.long 0x90++0x3
line.long 0x0 "CTL2,Control register 2"
hexmask.long.byte 0x0 9.--15. 1. "ADDM,Defines which bits of ADDRESS are compared with an incoming address byte"
tree.end
tree.end
tree "LPTIMER (Low Power Timer)"
base ad:0x40009400
rgroup.long 0x0++0x3
line.long 0x0 "INTF,Interrupt flag register"
bitfld.long 0x0 31. "IN1EIF,LPTIMER_IN1 error interrupt flag" "0,1"
bitfld.long 0x0 30. "IN0EIF,LPTIMER_IN0 error interrupt flag" "0,1"
bitfld.long 0x0 29. "INRFOEIF,The falling and rising edges of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt flag" "0,1"
bitfld.long 0x0 28. "INHLOEIF,The high level of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt flag" "0,1"
bitfld.long 0x0 27. "INHLCOIF,LPTIMER_INx(x=0 1) high level counter overflow interrupt flag" "0,1"
bitfld.long 0x0 26. "HLCMVUPIF,Input high level counter max value register update interrupt flag" "0,1"
bitfld.long 0x0 6. "DOWNIF,LPTIMER counter direction change up to down interrupt flag" "0,1"
bitfld.long 0x0 5. "UPIF,LPTIMER counter direction change down to up interrupt flag" "0,1"
bitfld.long 0x0 4. "CARUPIF,Counter auto reload register update interrupt flag" "0,1"
newline
bitfld.long 0x0 3. "CMPVUPIF,Compare value register update interrupt flag" "0,1"
bitfld.long 0x0 2. "ETEDEVIF,External trigger edge event interrupt flag" "0,1"
bitfld.long 0x0 1. "CARMIF,Counter auto reload register match interrupt flag" "0,1"
bitfld.long 0x0 0. "CMPVMIF,Compare value register match interrupt flag" "0,1"
wgroup.long 0x4++0x3
line.long 0x0 "INTC,Interrupt flag clear register"
bitfld.long 0x0 31. "IN1EIC,LPTIMER_IN1 error interrupt flag clear bit" "0,1"
bitfld.long 0x0 30. "IN0EIC,LPTIMER_IN0 error interrupt flag clear bit" "0,1"
bitfld.long 0x0 29. "INRFOEIC,The falling and rising edges of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt flag clear bit" "0,1"
bitfld.long 0x0 28. "INHLOEIC,The high level of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt flag clear bit" "0,1"
bitfld.long 0x0 27. "INHLCOIC,LPTIMER_INx(x=0 1) high level counter overflow interrupt flag clear bit" "0,1"
bitfld.long 0x0 26. "HLCMVUPIC,Input high level counter max value register update interrupt flag clear bit" "0,1"
bitfld.long 0x0 6. "DOWNIC,LPTIMER counter direction change up to down interrupt flag clear bit" "0,1"
bitfld.long 0x0 5. "UPIC,LPTIMER counter direction change down to up interrupt flag clear bit" "0,1"
bitfld.long 0x0 4. "CARUPIC,Counter auto reload register update interrupt flag clear bit" "0,1"
newline
bitfld.long 0x0 3. "CMPVUPIC,Compare value register update interrupt flag clear bit" "0,1"
bitfld.long 0x0 2. "ETEDEVIC,External trigger edge event interrupt flag clear bit" "0,1"
bitfld.long 0x0 1. "CARMIC,Counter auto reload register match interrupt flag clear bit" "0,1"
bitfld.long 0x0 0. "CMPVMIC,Compare value register match interrupt flag clear bit" "0,1"
group.long 0x8++0x13
line.long 0x0 "INTEN,Interrupt enable register"
bitfld.long 0x0 31. "IN1EIE,LPTIMER_IN1 error interrupt enable bit" "0,1"
bitfld.long 0x0 30. "IN0EIE,LPTIMER_IN0 error interrupt enable bit" "0,1"
bitfld.long 0x0 29. "INRFOEIE,The falling and rising edges of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt enable bit" "0,1"
bitfld.long 0x0 28. "INHLOEIE,The high level of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt enable bit" "0,1"
bitfld.long 0x0 27. "INHLCOIE,LPTIMER_INx(x=0 1) high level counter overflow interrupt enable bit" "0,1"
bitfld.long 0x0 26. "HLCMVUPIE,Input high level counter max value register update interrupt enable bit" "0,1"
bitfld.long 0x0 6. "DOWNIE,LPTIMER counter direction change up to down interrupt enable bit" "0,1"
bitfld.long 0x0 5. "UPIE,LPTIMER counter direction change down to up interrupt enable bit" "0,1"
bitfld.long 0x0 4. "CARUPIE,Counter auto reload register update interrupt enable bit" "0,1"
newline
bitfld.long 0x0 3. "CMPVUPIE,Compare value register update interrupt enable bit" "0,1"
bitfld.long 0x0 2. "ETEDEVIE,External trigger edge event interrupt enable bit" "0,1"
bitfld.long 0x0 1. "CARMIE,Counter auto reload register match interrupt enable bit" "0,1"
bitfld.long 0x0 0. "CMPVMIE,Compare value register match interrupt enable bit" "0,1"
line.long 0x4 "CTL0,Control register 0"
bitfld.long 0x4 29. "ETSEL_3,External trigger select" "0,1"
bitfld.long 0x4 25. "DECMSEL,Decoder mode select" "0,1"
bitfld.long 0x4 24. "DECMEN,Decoder mode enabled" "0,1"
bitfld.long 0x4 23. "CNTMEN,Counter mode select" "0,1"
bitfld.long 0x4 22. "SHWEN,LPTIMER_CAR and LPTIMER_CMPV shadow registers enable" "0,1"
bitfld.long 0x4 21. "OPSEL,Output polarity select" "0,1"
bitfld.long 0x4 20. "OMSEL,Output Mode select" "0,1"
bitfld.long 0x4 19. "TIMEOUT,Timeout mode enable" "0,1"
bitfld.long 0x4 17.--18. "ETMEN,External Trigger mode enable" "0,1,2,3"
newline
bitfld.long 0x4 13.--15. "ETSEL,External trigger select" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 9.--11. "PSC,Clock prescaler selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 6.--7. "TFLT,Trigger filter" "0,1,2,3"
bitfld.long 0x4 3.--4. "ECKFLT,External clock filter" "0,1,2,3"
bitfld.long 0x4 1.--2. "CKPSEL,Clock polarity select" "0,1,2,3"
bitfld.long 0x4 0. "CKSSEL,Clock source select" "0,1"
line.long 0x8 "CTL1,Control register 1"
bitfld.long 0x8 31. "INHLCEN,LPTIMER external input high level counter enable" "0,1"
rbitfld.long 0x8 30. "LPTENF,LPTIMER enabled from LPTIMER core flag" "0,1"
bitfld.long 0x8 4. "RDRSTEN,Read cause LPTIMER_CNT asynchronously reset enable" "0,1"
bitfld.long 0x8 3. "CNTRST,Counter (LPTIMER_CNT) synchronously reset" "0,1"
bitfld.long 0x8 2. "CTNMST,LPTIMER start for continuous counting mode" "0,1"
bitfld.long 0x8 1. "SMST,LPTIMER start for single counting mode" "0,1"
bitfld.long 0x8 0. "LPTEN,LPTIMER enable" "0,1"
line.long 0xC "CMPV,Compare value register"
hexmask.long.word 0xC 0.--15. 1. "CMPVAL,Compare value"
line.long 0x10 "CAR,Counter auto reload register"
hexmask.long.word 0x10 0.--15. 1. "CARL,Counter auto reload value"
rgroup.long 0x1C++0x3
line.long 0x0 "CNT,Counter register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
group.long 0x20++0x7
line.long 0x0 "EIRMP,External input remap register"
bitfld.long 0x0 4.--5. "IN1_RMP1_2,LPTIMER input1 remap extension" "0,1,2,3"
bitfld.long 0x0 2.--3. "IN0_RMP1_2,LPTIMER input0 remap extension" "0,1,2,3"
bitfld.long 0x0 1. "IN1_RMP,External input1 remap" "0,1"
bitfld.long 0x0 0. "IN0_RMP,External input0 remap" "0,1"
line.long 0x4 "INHLCMV,Input high level counter max value register"
hexmask.long 0x4 0.--25. 1. "INHLCMVAL,Input high level counter max value"
tree.end
tree "PMU (Power Management Unit)"
base ad:0x40007000
group.long 0x0++0xF
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 27.--28. "VUVDVC,V1.1v under voltage detector voltage level configure bits" "0,1,2,3"
bitfld.long 0x0 25.--26. "VOVDVC,V1.1v over voltage detector voltage level configure bits" "0,1,2,3"
bitfld.long 0x0 24. "VUVDEN,V1.1v Under Voltage Detector Enable" "0,1"
bitfld.long 0x0 23. "VOVDEN,V1.1v Over Voltage Detector Enable" "0,1"
bitfld.long 0x0 21.--22. "VAVDVC,VDDA analog voltage detector voltage level configure bits" "0,1,2,3"
bitfld.long 0x0 20. "VAVDEN,VDDA analog voltage detector voltage enable bit" "0,1"
bitfld.long 0x0 16.--17. "DSLPVS,Deep-sleep mode voltage scaling selection" "0,1,2,3"
hexmask.long.byte 0x0 11.--15. 1. "LDOVS,LDO output voltage select"
bitfld.long 0x0 8. "BKPWEN,Backup Domain Write Enable" "0,1"
bitfld.long 0x0 5.--7. "LVDT,Low Voltage Detector Threshold" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "LVDEN,Low Voltage Detector Enable" "0,1"
bitfld.long 0x0 3. "STBRST,Standby Flag Reset" "0,1"
bitfld.long 0x0 2. "WURST,Wakeup Flag Reset" "0,1"
bitfld.long 0x0 1. "STBMOD,Standby Mode" "0,1"
bitfld.long 0x0 0. "LDOLP,LDO Low Power Mode" "0,1"
line.long 0x4 "CS,Control and status register 0"
bitfld.long 0x4 12. "WUPEN4,WKUP Pin4(PC5) Enable" "0,1"
bitfld.long 0x4 11. "WUPEN3,WKUP Pin3 (PA2) Enable" "0,1"
bitfld.long 0x4 10. "WUPEN2,WKUP Pin2 (PE6) Enable" "0,1"
bitfld.long 0x4 9. "WUPEN1,WKUP Pin1 (PC13) Enable" "0,1"
bitfld.long 0x4 8. "WUPEN0,WKUP Pin0 (PA0) Enable (EWUP)" "0,1"
rbitfld.long 0x4 7. "VUVDF1,V1" "0,1"
rbitfld.long 0x4 6. "VOVDF1,V1" "0,1"
rbitfld.long 0x4 5. "VUVDF0,V1" "0,1"
rbitfld.long 0x4 4. "VOVDF0,V1" "0,1"
rbitfld.long 0x4 3. "VAVDF,VDDA analog voltage detector voltage output on VDDA flag bit" "0,1"
newline
rbitfld.long 0x4 2. "LVDF,Low Voltage Detector Status Flag" "0,1"
rbitfld.long 0x4 1. "STBF,Standby Flag" "0,1"
rbitfld.long 0x4 0. "WUF,Wakeup Flag" "0,1"
line.long 0x8 "CTL1,Control register 1"
rbitfld.long 0x8 23. "TEMPHF,Temperature level monitoring versus high threshold" "0,1"
rbitfld.long 0x8 22. "TEMPLF,Temperature level monitoring versus low threshold" "0,1"
rbitfld.long 0x8 21. "VBATHF,VBAT level monitoring versus high threshold" "0,1"
rbitfld.long 0x8 20. "VBATLF,VBAT level monitoring versus low threshold" "0,1"
rbitfld.long 0x8 16. "BKPVSRF,Bandgap Voltage Reference ready BRRDY" "0,1"
bitfld.long 0x8 4. "VBTMEN,VBAT and temperature monitoring enable" "0,1"
bitfld.long 0x8 0. "BKPVSEN,Bandgap Voltage Reference(BGR) enable" "0,1"
line.long 0xC "CTL2,Control register 2"
bitfld.long 0xC 9. "VCRSEL,VBAT battery charging resistor selection" "0,1"
bitfld.long 0xC 8. "VCEN,VBAT battery charging enable" "0,1"
group.long 0x18++0x3
line.long 0x0 "CTL3,Control register 3"
hexmask.long.byte 0x0 8.--15. 1. "VUVDO_DNF,VUVD analog output digital noise filter"
hexmask.long.byte 0x0 0.--7. 1. "VOVDO_DNF,VOVD analog output digital noise filter"
tree.end
tree "QSPI (Quad-SPI Interface)"
base ad:0xA0001000
group.long 0x0++0xB
line.long 0x0 "CTL,Control register"
hexmask.long.byte 0x0 24.--31. 1. "PSC,The clock prescaler of AHB clock for generating SCK"
bitfld.long 0x0 23. "RPMM,Read polling match mode" "0,1"
bitfld.long 0x0 22. "RPMS,Read polling mode stop" "0,1"
bitfld.long 0x0 20. "TMOUTIE,Timeout interrupt enable" "0,1"
bitfld.long 0x0 19. "RPMFIE,Read polling mode match interrupt enable" "0,1"
bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable" "0,1"
bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable" "0,1"
bitfld.long 0x0 16. "TERRIE,Transfer error interrupt enable" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "OCKDV,output clock delay value"
hexmask.long.byte 0x0 8.--11. 1. "FTL,FIFO threshold level"
bitfld.long 0x0 5. "OCKDEN,Output clock delay enable when write data to flash" "0,1"
bitfld.long 0x0 4. "SSAMPLE,Sample delay" "0,1"
bitfld.long 0x0 3. "TMOUTEN,Timeout counter enable" "0,1"
bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1"
bitfld.long 0x0 1. "ABORT,Abort request" "0,1"
bitfld.long 0x0 0. "QSPIEN,QSPI enable bit" "0,1"
line.long 0x4 "DCFG,Device configuration register"
bitfld.long 0x4 30. "CSNCKM,Select whether the CSN falls and rises one or two SCK clock cycles before the first SCK effective rising edge and after the last SCK effective rising edge" "0,1"
hexmask.long.byte 0x4 16.--20. 1. "FMSZ,Flash memory size"
bitfld.long 0x4 8.--10. "CSHC,Chip select high cycle" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 5. "DLYSCEN,Delay scan enable" "0,1"
bitfld.long 0x4 4. "RCKSEL,Receive clock select" "0,1"
bitfld.long 0x4 1.--3. "RXSFT,Shift receive step if rececive data delay more than 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0. "CKMOD,This bit indicates the SCK level when QSPI is free" "0,1"
line.long 0x8 "STAT,Status register"
hexmask.long.byte 0x8 8.--12. 1. "FL,FIFO level"
rbitfld.long 0x8 5. "BUSY,Busy flag" "0,1"
rbitfld.long 0x8 4. "TMOUT,Timeout flag" "0,1"
rbitfld.long 0x8 3. "RPMF,Read polling match flag" "0,1"
rbitfld.long 0x8 2. "FT,FIFO threshold flag" "0,1"
rbitfld.long 0x8 1. "TC,Transfer complete flag" "0,1"
rbitfld.long 0x8 0. "TERR,Transfer error flag" "0,1"
wgroup.long 0xC++0x3
line.long 0x0 "STATC,Status clear register"
bitfld.long 0x0 4. "TMOUTC,Clear timeout flag" "0,1"
bitfld.long 0x0 3. "RPMFC,Clear read polling mode match flag" "0,1"
bitfld.long 0x0 1. "TCC,Clear transfer complete flag" "0,1"
bitfld.long 0x0 0. "TERRC,Clear transfer error flag" "0,1"
group.long 0x10++0x23
line.long 0x0 "DTLEN,Data length register"
hexmask.long 0x0 0.--31. 1. "DTLEN,Data length"
line.long 0x4 "TCFG,Transfer configuration register"
bitfld.long 0x4 31. "DDREN,Double data rate mode enable" "0,1"
bitfld.long 0x4 30. "DDRHEN,DDR output hold enable" "0,1"
bitfld.long 0x4 28. "SIOO,Send instruction only once mode" "0,1"
bitfld.long 0x4 26.--27. "FMOD,Functional mode" "0,1,2,3"
bitfld.long 0x4 24.--25. "DATAMOD,Data mode" "0,1,2,3"
hexmask.long.byte 0x4 18.--22. 1. "DUMYC,Number of dummy cycles"
bitfld.long 0x4 16.--17. "ALTESZ,Alternate bytes size" "0,1,2,3"
bitfld.long 0x4 14.--15. "ALTEMOD,Alternate bytes mode" "0,1,2,3"
newline
bitfld.long 0x4 12.--13. "ADDRSZ,Address size" "0,1,2,3"
bitfld.long 0x4 10.--11. "ADDRMOD,Address mode" "0,1,2,3"
bitfld.long 0x4 8.--9. "IMOD,Instruction mode" "0,1,2,3"
hexmask.long.byte 0x4 0.--7. 1. "INSTRUCTION,Instruction"
line.long 0x8 "ADDR,Address register"
hexmask.long 0x8 0.--31. 1. "ADDR,Address to be send to the external Flash memory"
line.long 0xC "ALTE,Alternate bytes register"
hexmask.long 0xC 0.--31. 1. "ALTE,Alternate bytes"
line.long 0x10 "DATA,Data register"
hexmask.long 0x10 0.--31. 1. "DATA,Interactive data between QSPI and flash memory"
line.long 0x14 "STATMK,Status mask register"
hexmask.long 0x14 0.--31. 1. "MASK,Status mask in read polling mode"
line.long 0x18 "STATMATCH,Status match register"
hexmask.long 0x18 0.--31. 1. "MATCH,Status match in read polling mode"
line.long 0x1C "INTERVAL,Interval register"
hexmask.long.word 0x1C 0.--15. 1. "INTERVAL,Interval cycle"
line.long 0x20 "TMOUT,Timeout register"
hexmask.long.word 0x20 0.--15. 1. "TMOUTCYC,Timeout cycle"
wgroup.long 0x34++0x3
line.long 0x0 "FLUSH,FIFO flush register"
bitfld.long 0x0 0. "FLUSH,Used to flush all qspi interal fifo" "0,1"
tree.end
tree "RCU (Reset and Clock Unit)"
base ad:0x40021000
group.long 0x0++0x1B
line.long 0x0 "CTL,Control register"
rbitfld.long 0x0 25. "PLLSTB,PLL clock stabilization flag" "0,1"
bitfld.long 0x0 24. "PLLEN,PLL enable" "0,1"
bitfld.long 0x0 20. "HXTALSTBRST,HXTAL stabilization reset" "0,1"
bitfld.long 0x0 19. "CKMEN,HXTAL clock monitor enable" "0,1"
bitfld.long 0x0 18. "HXTALBPS,High speed crystal oscillator (HXTAL) clock bypass mode enable" "0,1"
rbitfld.long 0x0 17. "HXTALSTB,High speed crystal oscillator (HXTAL) clock stabilization flag" "0,1"
bitfld.long 0x0 16. "HXTALEN,High speed crystal oscillator (HXTAL) Enable" "0,1"
newline
hexmask.long.byte 0x0 8.--15. 1. "IRC8MCALIB,Internal 8MHz RC Oscillator calibration value register"
hexmask.long.byte 0x0 3.--7. 1. "IRC8MADJ,Internal 8MHz RC Oscillator clock trim adjust value"
rbitfld.long 0x0 1. "IRC8MSTB,IRC8M internal 8MHz RC oscillator stabilization flag" "0,1"
bitfld.long 0x0 0. "IRC8MEN,Internal 8MHz RC oscillator enable" "0,1"
line.long 0x4 "PLL,PLL register"
hexmask.long.byte 0x4 27.--31. 1. "PLLR,The PLLR output frequency division factor from PLL VCO clock"
hexmask.long.byte 0x4 23.--26. 1. "PLLQ,The PLLQ output frequency division factor from PLL VCO clock"
bitfld.long 0x4 22. "PLLSEL,PLL clock source selection" "0,1"
bitfld.long 0x4 21. "PLLREN,PLLR divider output enable" "0,1"
bitfld.long 0x4 20. "PLLQEN,PLLQ divider output enable" "0,1"
bitfld.long 0x4 19. "PLLPEN,PLLP divider output enable" "0,1"
bitfld.long 0x4 16.--17. "PLLP,The PLLP output frequency division factor from PLL VCO clock" "0,1,2,3"
newline
hexmask.long.byte 0x4 6.--13. 1. "PLLN,The PLL VCO clock multiplication factor"
hexmask.long.byte 0x4 0.--3. 1. "PLLPSC,The PLL VCO source clock prescaler"
line.long 0x8 "CFG0,Clock configuration register 0"
bitfld.long 0x8 27.--29. "APB3PSC,APB3 prescaler selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 24.--26. "CKOUTDIV,The CK_OUT divider which the CK_OUT frequency can be reduced" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 21.--23. "CKOUTSEL,CK_OUT clock source selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 13.--15. "APB2PSC,APB2 prescaler selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 10.--12. "APB1PSC,APB1 prescaler selection" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 4.--7. 1. "AHBPSC,AHB prescaler selection"
rbitfld.long 0x8 2.--3. "SCSS,System clock switch status" "0,1,2,3"
newline
bitfld.long 0x8 0.--1. "SCS,System clock switch" "0,1,2,3"
line.long 0xC "INT,Clock interrupt register"
bitfld.long 0xC 28. "LCKMIC,LXTAL clock monitor interrupt clear" "0,1"
rbitfld.long 0xC 27. "LCKMIF,LXTAL clock monitor interrupt flag" "0,1"
bitfld.long 0xC 23. "CKMIC,HXTAL clock stuck interrupt clear" "0,1"
bitfld.long 0xC 20. "PLLSTBIC,PLL stabilization interrupt clear" "0,1"
bitfld.long 0xC 19. "HXTALSTBIC,HXTAL stabilization interrupt clear" "0,1"
bitfld.long 0xC 18. "IRC8MSTBIC,IRC8M stabilization interrupt clear" "0,1"
bitfld.long 0xC 17. "LXTALSTBIC,LXTAL stabilization interrupt clear" "0,1"
newline
bitfld.long 0xC 16. "IRC32KSTBIC,IRC32K stabilization interrupt clear" "0,1"
bitfld.long 0xC 12. "PLLSTBIE,PLL stabilization interrupt enable" "0,1"
bitfld.long 0xC 11. "HXTALSTBIE,HXTAL stabilization interrupt enable" "0,1"
bitfld.long 0xC 10. "IRC8MSTBIE,IRC8M stabilization interrupt enable" "0,1"
bitfld.long 0xC 9. "LXTALSTBIE,LXTAL stabilization interrupt enable" "0,1"
bitfld.long 0xC 8. "IRC32KSTBIE,IRC32K stabilization interrupt enable" "0,1"
rbitfld.long 0xC 7. "CKMIF,HXTAL clock stuck interrupt flag" "0,1"
newline
rbitfld.long 0xC 4. "PLLSTBIF,PLL stabilization interrupt flag" "0,1"
rbitfld.long 0xC 3. "HXTALSTBIF,HXTAL stabilization interrupt flag" "0,1"
rbitfld.long 0xC 2. "IRC8MSTBIF,IRC8M stabilization interrupt flag" "0,1"
rbitfld.long 0xC 1. "LXTALSTBIF,LXTAL stabilization interrupt flag" "0,1"
rbitfld.long 0xC 0. "IRC32KSTBIF,IRC32K stabilization interrupt flag" "0,1"
line.long 0x10 "AHB1RST,AHB1 reset register"
bitfld.long 0x10 31. "FFTRST,FFT reset" "0,1"
bitfld.long 0x10 23. "DMAMUXRST,DMAMUX reset" "0,1"
bitfld.long 0x10 22. "DMA1RST,DMA1 reset" "0,1"
bitfld.long 0x10 21. "DMA0RST,DMA0 reset" "0,1"
bitfld.long 0x10 15. "CLARST,CLA reset" "0,1"
bitfld.long 0x10 12. "CRCRST,CRC reset" "0,1"
line.long 0x14 "AHB2RST,AHB2 reset register"
bitfld.long 0x14 23. "PGRST,GPIO port G reset" "0,1"
bitfld.long 0x14 22. "PFRST,GPIO portF reset" "0,1"
bitfld.long 0x14 21. "PERST,GPIO port E reset" "0,1"
bitfld.long 0x14 20. "PDRST,GPIO port D reset" "0,1"
bitfld.long 0x14 19. "PCRST,GPIO port C reset" "0,1"
bitfld.long 0x14 18. "PBRST,GPIO port B reset" "0,1"
bitfld.long 0x14 17. "PARST,GPIO port A reset" "0,1"
newline
bitfld.long 0x14 7. "TMURST,TMU reset" "0,1"
bitfld.long 0x14 6. "TRNGRST,TRNG reset" "0,1"
bitfld.long 0x14 3. "CAURST,CAU reset" "0,1"
bitfld.long 0x14 1. "FACRST,FAC reset" "0,1"
line.long 0x18 "AHB3RST,AHB3 reset register"
bitfld.long 0x18 1. "QSPIRST,QSPI reset" "0,1"
bitfld.long 0x18 0. "EXMCRST,EXMC reset" "0,1"
group.long 0x20++0xB
line.long 0x0 "APB1RST,APB1 reset register"
bitfld.long 0x0 28. "PMURST,Power control reset" "0,1"
bitfld.long 0x0 24. "I2C3RST,I2C3 reset" "0,1"
bitfld.long 0x0 23. "I2C2RST,I2C2 reset" "0,1"
bitfld.long 0x0 22. "I2C1RST,I2C1 reset" "0,1"
bitfld.long 0x0 21. "I2C0RST,I2C0 reset" "0,1"
bitfld.long 0x0 20. "UART4RST,UART4 reset" "0,1"
bitfld.long 0x0 19. "UART3RST,UART3 reset" "0,1"
newline
bitfld.long 0x0 18. "USART2RST,USART2 reset" "0,1"
bitfld.long 0x0 17. "USART1RST,USART1 reset" "0,1"
bitfld.long 0x0 15. "SPI2RST,SPI2 reset" "0,1"
bitfld.long 0x0 14. "SPI1RST,SPI1 reset" "0,1"
bitfld.long 0x0 11. "WWDGTRST,WWDGT reset" "0,1"
bitfld.long 0x0 9. "LPTIMERRST,LPTIMER reset" "0,1"
bitfld.long 0x0 5. "TIMER6RST,TIMER6 reset" "0,1"
newline
bitfld.long 0x0 4. "TIMER5RST,TIMER5 reset" "0,1"
bitfld.long 0x0 3. "TIMER4RST,TIMER4 reset" "0,1"
bitfld.long 0x0 2. "TIMER3RST,TIMER3 reset" "0,1"
bitfld.long 0x0 1. "TIMER2RST,TIMER2 reset" "0,1"
bitfld.long 0x0 0. "TIMER1RST,TIMER1 reset" "0,1"
line.long 0x4 "APB2RST,APB2 reset register"
bitfld.long 0x4 31. "TRIGSELRST,TRIGSELreset" "0,1"
bitfld.long 0x4 29. "HRTIMERRST,HRTIMER reset" "0,1"
bitfld.long 0x4 19. "HPDFRST,HPDF reset" "0,1"
bitfld.long 0x4 18. "TIMER16RST,TIMER16 reset" "0,1"
bitfld.long 0x4 17. "TIMER15RST,TIMER15 reset" "0,1"
bitfld.long 0x4 16. "TIMER14RST,TIMER14 reset" "0,1"
bitfld.long 0x4 15. "TIMER19RST,TIMER19 reset" "0,1"
newline
bitfld.long 0x4 14. "SYSCFGRST,SYSCFG reset" "0,1"
bitfld.long 0x4 12. "SPI0RST,SPI0 reset" "0,1"
bitfld.long 0x4 10. "CAN2RST,CAN2 reset" "0,1"
bitfld.long 0x4 9. "CAN1RST,CAN1 reset" "0,1"
bitfld.long 0x4 8. "CAN0RST,CAN0 reset" "0,1"
bitfld.long 0x4 4. "USART0RST,USART0 reset" "0,1"
bitfld.long 0x4 3. "CMPRST,CMP reset" "0,1"
newline
bitfld.long 0x4 2. "VREFRST,VREF reset" "0,1"
bitfld.long 0x4 1. "TIMER7RST,TIMER7 reset" "0,1"
bitfld.long 0x4 0. "TIMER0RST,TIMER0 reset" "0,1"
line.long 0x8 "APB3RST,APB3 reset register"
bitfld.long 0x8 20. "DAC3RST,DAC3 reset" "0,1"
bitfld.long 0x8 19. "DAC2RST,DAC2 reset" "0,1"
bitfld.long 0x8 18. "DAC1RST,DAC1 reset" "0,1"
bitfld.long 0x8 17. "DAC0RST,DAC0 reset" "0,1"
bitfld.long 0x8 16. "DACHOLDRST,DAC hold clock reset" "0,1"
bitfld.long 0x8 11. "ADC3RST,ADC3 reset" "0,1"
bitfld.long 0x8 10. "ADC2RST,ADC2 reset" "0,1"
newline
bitfld.long 0x8 9. "ADC1RST,ADC1 reset" "0,1"
bitfld.long 0x8 8. "ADC0RST,ADC0 reset" "0,1"
group.long 0x30++0xB
line.long 0x0 "AHB1EN,AHB1 enable register"
bitfld.long 0x0 31. "FFTEN,FFT clock enable" "0,1"
bitfld.long 0x0 23. "DMAMUXEN,DMAMUX clock enable" "0,1"
bitfld.long 0x0 22. "DMA1EN,DMA1 clock enable" "0,1"
bitfld.long 0x0 21. "DMA0EN,DMA0 clock enable" "0,1"
bitfld.long 0x0 15. "CLAEN,CLA clock enable" "0,1"
bitfld.long 0x0 12. "CRCEN,CRC clock enable" "0,1"
line.long 0x4 "AHB2EN,AHB2 enable register"
bitfld.long 0x4 23. "PGEN,GPIO port G clock enable" "0,1"
bitfld.long 0x4 22. "PFEN,GPIO port F clock enable" "0,1"
bitfld.long 0x4 21. "PEEN,GPIO port E clock enable" "0,1"
bitfld.long 0x4 20. "PDEN,GPIO port D clock enable" "0,1"
bitfld.long 0x4 19. "PCEN,GPIO port C clock enable" "0,1"
bitfld.long 0x4 18. "PBEN,GPIO port B clock enable" "0,1"
bitfld.long 0x4 17. "PAEN,GPIO port A clock enable" "0,1"
newline
bitfld.long 0x4 7. "TMUEN,TMU clock enable" "0,1"
bitfld.long 0x4 6. "TRNGEN,TRNG clock enable" "0,1"
bitfld.long 0x4 3. "CAUEN,CRY clock enable" "0,1"
bitfld.long 0x4 1. "FACEN,FAC clock enable" "0,1"
line.long 0x8 "AHB3EN,AHB3 enable register"
bitfld.long 0x8 1. "QSPIEN,QSPI clock enable" "0,1"
bitfld.long 0x8 0. "EXMCEN,EXMC clock enable" "0,1"
group.long 0x40++0xB
line.long 0x0 "APB1EN,APB1 enable register"
bitfld.long 0x0 28. "PMUEN,PMU clock enable" "0,1"
bitfld.long 0x0 24. "I2C3EN,I2C3 clock enable" "0,1"
bitfld.long 0x0 23. "I2C2EN,I2C2 clock enable" "0,1"
bitfld.long 0x0 22. "I2C1EN,I2C1 clock enable" "0,1"
bitfld.long 0x0 21. "I2C0EN,I2C0 clock enable" "0,1"
bitfld.long 0x0 20. "UART4EN,UART4 clock enable" "0,1"
bitfld.long 0x0 19. "UART3EN,UART3 clock enable" "0,1"
newline
bitfld.long 0x0 18. "USART2EN,USART2 clock enable" "0,1"
bitfld.long 0x0 17. "USART1EN,USART1 clock enable" "0,1"
bitfld.long 0x0 15. "SPI2EN,SPI2 clock enable" "0,1"
bitfld.long 0x0 14. "SPI1EN,SPI1 clock enable" "0,1"
bitfld.long 0x0 11. "WWDGTEN,WWDGT clock enable" "0,1"
bitfld.long 0x0 9. "LPTIMEREN,LPTIMER clock enable" "0,1"
bitfld.long 0x0 5. "TIMER6EN,TIMER6 clock enable" "0,1"
newline
bitfld.long 0x0 4. "TIMER5EN,TIMER5 clock enable" "0,1"
bitfld.long 0x0 3. "TIMER4EN,TIMER4 clock enable" "0,1"
bitfld.long 0x0 2. "TIMER3EN,TIMER3 clock enable" "0,1"
bitfld.long 0x0 1. "TIMER2EN,TIMER2 clock enable" "0,1"
bitfld.long 0x0 0. "TIMER1EN,TIMER1 clock enable" "0,1"
line.long 0x4 "APB2EN,APB2 enable register"
bitfld.long 0x4 31. "TRIGSELEN,TRIGSEL clock enable" "0,1"
bitfld.long 0x4 29. "HRTIMEREN,HRTIMER clock enable" "0,1"
bitfld.long 0x4 19. "HPDFEN,HPDF clock enable" "0,1"
bitfld.long 0x4 18. "TIMER16EN,TIMER16 clock enable" "0,1"
bitfld.long 0x4 17. "TIMER15EN,TIMER15 clock enable" "0,1"
bitfld.long 0x4 16. "TIMER14EN,TIMER14 clock enable" "0,1"
bitfld.long 0x4 15. "TIMER19EN,TIMER19 clock enable" "0,1"
newline
bitfld.long 0x4 14. "SYSCFGEN,SYSCFG clock enable" "0,1"
bitfld.long 0x4 12. "SPI0EN,SPI0 clock enable" "0,1"
bitfld.long 0x4 10. "CAN2EN,CAN2 clock enable" "0,1"
bitfld.long 0x4 9. "CAN1EN,CAN1 clock enable" "0,1"
bitfld.long 0x4 8. "CAN0EN,CAN0 clock enable" "0,1"
bitfld.long 0x4 4. "USART0EN,USART0 clock enable" "0,1"
bitfld.long 0x4 3. "CMPEN,CMP clock enable" "0,1"
newline
bitfld.long 0x4 2. "VREFEN,VREF clock enable" "0,1"
bitfld.long 0x4 1. "TIMER7EN,TIMER7 clock enable" "0,1"
bitfld.long 0x4 0. "TIMER0EN,TIMER0 clock enable" "0,1"
line.long 0x8 "APB3EN,APB3 enable register"
bitfld.long 0x8 20. "DAC3EN,DAC3 clock enable" "0,1"
bitfld.long 0x8 19. "DAC2EN,DAC2 clock enable" "0,1"
bitfld.long 0x8 18. "DAC1EN,DAC1 clock enable" "0,1"
bitfld.long 0x8 17. "DAC0EN,DAC0 clock enable" "0,1"
bitfld.long 0x8 16. "DACHOLDEN,DAC hold clock clock enable" "0,1"
bitfld.long 0x8 11. "ADC3EN,ADC3 clock enable" "0,1"
bitfld.long 0x8 10. "ADC2EN,ADC2 clock enable" "0,1"
newline
bitfld.long 0x8 9. "ADC1EN,ADC1 clock enable" "0,1"
bitfld.long 0x8 8. "ADC0EN,ADC0 clock enable" "0,1"
group.long 0x50++0xB
line.long 0x0 "AHB1SPDPEN,AHB1 sleep and deep-sleep mode enable register"
bitfld.long 0x0 31. "FFTSPDPEN,FFT clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 23. "DMAMUXSPDPEN,DMAMUX clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 22. "DMA1SPDPEN,DMA1 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 21. "DMA0SPDPEN,DMA0 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 19. "TCMSRAMSPDPEN,TCMSRAM enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 17. "SRAM1SPDPEN,SRAM1 enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 16. "SRAM0SPDPEN,SRAM0 enable when sleep and deep sleep mode" "0,1"
newline
bitfld.long 0x0 15. "CLASPDPEN,CLA clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 12. "CRCSPDPEN,CRC clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 8. "FMCSPDPEN,FMC clock enable when sleep and deep sleep mode" "0,1"
line.long 0x4 "AHB2SPDPEN,AHB2 sleep and deep-sleep mode enable register"
bitfld.long 0x4 23. "PGSPDPEN,GPIO port G clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 22. "PFSPDPEN,GPIO port F clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 21. "PESPDPEN,GPIO port E clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 20. "PDSPDPEN,GPIO port D clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 19. "PCSPDPEN,GPIO port C clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 18. "PBSPDPEN,GPIO port B clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 17. "PASPDPEN,GPIO port A clock enable when sleep and deep sleep mode" "0,1"
newline
bitfld.long 0x4 7. "TMUSPDPEN,TMU clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 6. "TRNGSPDPEN,TRNG clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 3. "CAUSPDPEN,CAU clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 1. "FACSPDPEN,FAC clock enable when sleep and deep sleep mode" "0,1"
line.long 0x8 "AHB3SPDPEN,AHB3 sleep and deep-sleep mode enable register"
bitfld.long 0x8 1. "QSPISPDPEN,QSPI clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x8 0. "EXMCSPDPEN,EXMC clock enable when sleep and deep sleep mode" "0,1"
group.long 0x60++0xB
line.long 0x0 "APB1SPDPEN,APB1 sleep and deep-sleep mode enable register"
bitfld.long 0x0 28. "PMUSPDPEN,PMU clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 24. "I2C3SPDPEN,I2C3 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 23. "I2C2SPDPEN,I2C2 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 22. "I2C1SPDPEN,I2C1 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 21. "I2C0SPDPEN,I2C0 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 20. "UART4SPDPEN,UART4 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 19. "UART3SPDPEN,UART3 clock enable when sleep and deep sleep mode" "0,1"
newline
bitfld.long 0x0 18. "USART2SPDPEN,USART2 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 17. "USART1SPDPEN,USART1 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 15. "SPI2SPDPEN,SPI2 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 14. "SPI1SPDPEN,SPI1 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 11. "WWDGTSPDPEN,WWDGT clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 9. "LPTIMERSPDPEN,LPTIMER clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 5. "TIMER6SPDPEN,TIMER6 clock enable when sleep and deep sleep mode" "0,1"
newline
bitfld.long 0x0 4. "TIMER5SPDPEN,TIMER5 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 3. "TIMER4SPDPEN,TIMER4 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 2. "TIMER3SPDPEN,TIMER3 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 1. "TIMER2SPDPEN,TIMER2 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x0 0. "TIMER1SPDPEN,TIMER1 clock enable when sleep and deep sleep mode" "0,1"
line.long 0x4 "APB2SPDPEN,APB2 sleep and deep-sleep mode enable register"
bitfld.long 0x4 31. "TRIGSELSPDPEN,TRIGSEL clock enable when sleep mode" "0,1"
bitfld.long 0x4 29. "HRTIMERSPDPEN,HRTIMER clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 19. "HPDFSPDPEN,HPDF clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 18. "TIMER16SPDPEN,TIMER16 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 17. "TIMER15SPDPEN,TIMER15 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 16. "TIMER14SPDPEN,TIMER14 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 15. "TIMER19SPDPEN,TIMER19 clock enable when sleep and deep sleep mode" "0,1"
newline
bitfld.long 0x4 14. "SYSCFGSPDPEN,SYSCFG clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 12. "SPI0SPDPEN,SPI0 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 10. "CAN2SPDPEN,CAN2 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 9. "CAN1SPDPEN,CAN1 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 8. "CAN0SPDPEN,CAN0 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 4. "USART0SPDPEN,USART0 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 3. "CMPSPDPEN,CMP clock enable when sleep and deep sleep mode" "0,1"
newline
bitfld.long 0x4 2. "VREFSPDPEN,VREF clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 1. "TIMER7SPDPEN,TIMER7 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x4 0. "TIMER0SPDPEN,TIMER0 clock enable when sleep and deep sleep mode" "0,1"
line.long 0x8 "APB3SPDPEN,APB3 sleep and deep-sleep mode enable register"
bitfld.long 0x8 20. "DAC3SPDPEN,DAC3 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x8 19. "DAC2SPDPEN,DAC2 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x8 18. "DAC1SPDPEN,DAC1 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x8 17. "DAC0SPDPEN,DAC0 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x8 16. "DACHOLDSPDPEN,DAC hold clock clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x8 11. "ADC3SPDPEN,ADC3 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x8 10. "ADC2SPDPEN,ADC2 clock enable when sleep and deep sleep mode" "0,1"
newline
bitfld.long 0x8 9. "ADC1SPDPEN,ADC1 clock enable when sleep and deep sleep mode" "0,1"
bitfld.long 0x8 8. "ADC0SPDPEN,ADC0 clock enable when sleep and deep sleep mode" "0,1"
group.long 0x70++0x7
line.long 0x0 "BDCTL,Backup domain control register"
bitfld.long 0x0 25. "LSCKOUTSEL,Low speed clock output selection" "0,1"
bitfld.long 0x0 24. "LSCKOUTEN,Low speed clock output enalbe" "0,1"
bitfld.long 0x0 16. "BKPRST,Backup domain reset" "0,1"
bitfld.long 0x0 15. "RTCEN,RTC clock enable" "0,1"
bitfld.long 0x0 8.--9. "RTCSRC,RTC clock entry selection" "0,1,2,3"
bitfld.long 0x0 7. "LXTALSTBRST,LXTAL stabilization reset" "0,1"
bitfld.long 0x0 6. "LCKMD,LXTALclock failure detection" "0,1"
newline
bitfld.long 0x0 5. "LCKMEN,LXTAL clock monitor enable" "0,1"
bitfld.long 0x0 3.--4. "LXTALDRI,LXTAL drive capability" "0,1,2,3"
bitfld.long 0x0 2. "LXTALBPS,LXTAL bypass mode enable" "0,1"
rbitfld.long 0x0 1. "LXTALSTB,Low speed crystal oscillator stabilization flag" "0,1"
bitfld.long 0x0 0. "LXTALEN,LXTAL enable" "0,1"
line.long 0x4 "RSTSCK,Reset source/clock register"
rbitfld.long 0x4 31. "LPRSTF,Low-power reset flag" "0,1"
rbitfld.long 0x4 30. "WWDGTRSTF,Window watchdog timer reset flag" "0,1"
rbitfld.long 0x4 29. "FWDGTRSTF,Free watchdog timer reset flag" "0,1"
rbitfld.long 0x4 28. "SWRSTF,Software reset flag" "0,1"
rbitfld.long 0x4 27. "PORRSTF,Power reset flag" "0,1"
rbitfld.long 0x4 26. "EPRSTF,External PIN reset flag" "0,1"
rbitfld.long 0x4 25. "BORRSTF,BOR reset flag" "0,1"
newline
bitfld.long 0x4 24. "RSTFC,Reset flag clear" "0,1"
rbitfld.long 0x4 23. "OBLRST,Option byte loader reset flag" "0,1"
rbitfld.long 0x4 1. "IRC32KSTB,IRC32K stabilization flag" "0,1"
bitfld.long 0x4 0. "IRC32KEN,IRC32K enable" "0,1"
group.long 0x8C++0x7
line.long 0x0 "CFG1,Clock configuration register 1"
bitfld.long 0x0 31. "HPDFSEL,HPDF clock source selection" "0,1"
bitfld.long 0x0 29.--30. "HPDFAUDIOSEL,HPDF AUDIO clock source selection" "0,1,2,3"
bitfld.long 0x0 20.--21. "USART2SEL,USART2 clock source selection" "0,1,2,3"
bitfld.long 0x0 18.--19. "USART1SEL,USART1 clock source selection" "0,1,2,3"
bitfld.long 0x0 12.--13. "CAN2SEL,CAN2 clock source selection" "0,1,2,3"
bitfld.long 0x0 10.--11. "CAN1SEL,CAN1 clock selection" "0,1,2,3"
bitfld.long 0x0 8.--9. "CAN0SEL,CAN0 clock source selection" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "USART0SEL,USART0 clock source selection" "0,1,2,3"
line.long 0x4 "CFG2,Clock configuration register 2"
bitfld.long 0x4 28.--29. "ADC3SEL,ADC3 clock source selection" "0,1,2,3"
bitfld.long 0x4 26.--27. "ADC0_1_2SEL,ADC0 / 1 / 2 clock source selection" "0,1,2,3"
bitfld.long 0x4 19. "HRTIMERSEL,HRTIMER clock source selection" "0,1"
bitfld.long 0x4 16.--17. "QSPISEL,QSPI clock source selection" "0,1,2,3"
hexmask.long.byte 0x4 12.--15. 1. "TRNGPSC,TRNG prescaler selection"
bitfld.long 0x4 9.--10. "LPTIMERSEL,LPTIMER clock source selection" "0,1,2,3"
bitfld.long 0x4 6.--7. "I2C3SEL,I2C3 clock source selection" "0,1,2,3"
newline
bitfld.long 0x4 4.--5. "I2C2SEL,I2C2 clock source selection" "0,1,2,3"
bitfld.long 0x4 2.--3. "I2C1SEL,I2C1 clock source selection" "0,1,2,3"
bitfld.long 0x4 0.--1. "I2C0SEL,I2C0 clock source selection" "0,1,2,3"
tree.end
tree "RTC (Real-Time Clock)"
base ad:0x40002800
group.long 0x0++0x17
line.long 0x0 "TIME,time register"
bitfld.long 0x0 22. "PM,AM/PM mark" "0,1"
bitfld.long 0x0 20.--21. "HRT,Hour tens in BCD code" "0,1,2,3"
hexmask.long.byte 0x0 16.--19. 1. "HRU,Hour units in BCD format"
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD code" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD code"
bitfld.long 0x0 4.--6. "SCT,Second tens in BCD code" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--3. 1. "SCU,Second units in BCD code"
line.long 0x4 "DATE,date register"
hexmask.long.byte 0x4 20.--23. 1. "YRT,Year tens in BCD code"
hexmask.long.byte 0x4 16.--19. 1. "YRU,Year units in BCD code"
bitfld.long 0x4 13.--15. "DOW,Days of the week" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 12. "MONT,Month tens in BCD code" "0,1"
hexmask.long.byte 0x4 8.--11. 1. "MONU,Month units in BCD code"
bitfld.long 0x4 4.--5. "DAYT,Date tens in BCD code" "0,1,2,3"
hexmask.long.byte 0x4 0.--3. 1. "DAYU,Date units in BCD code"
line.long 0x8 "CTL,control register"
bitfld.long 0x8 25. "TAMPCLK,edge tamper needs RTC Clok" "0,1"
bitfld.long 0x8 24. "ITSEN,Internal timestamp event enable" "0,1"
bitfld.long 0x8 23. "COEN,Calibration output enable" "0,1"
bitfld.long 0x8 21.--22. "OS,Output selection" "0,1,2,3"
bitfld.long 0x8 20. "OPOL,Output polarity" "0,1"
bitfld.long 0x8 19. "COS,Calibration output selection" "0,1"
bitfld.long 0x8 18. "DSM,Backup" "0,1"
newline
bitfld.long 0x8 17. "S1H,Subtract 1 hour (winter time change)" "0,1"
bitfld.long 0x8 16. "A1H,Add 1 hour (summer time change)" "0,1"
bitfld.long 0x8 15. "TSIE,Time-stamp interrupt enable" "0,1"
bitfld.long 0x8 14. "WTIE,Auto-wakeup timer interrupt enable" "0,1"
bitfld.long 0x8 13. "ALRM1IE,Alarm1 interrupt enable" "0,1"
bitfld.long 0x8 12. "ALRM0IE,Alarm0 interrupt enable" "0,1"
bitfld.long 0x8 11. "TSEN,timestamp enable" "0,1"
newline
bitfld.long 0x8 10. "WTEN,Auto-wakeup timer function enable" "0,1"
bitfld.long 0x8 9. "ALRM1EN,Alarm1 enable" "0,1"
bitfld.long 0x8 8. "ALRM0EN,Alarm0 enable" "0,1"
bitfld.long 0x8 6. "CS,Hour format" "0,1"
bitfld.long 0x8 5. "BPSHAD,Bypass the shadow registers" "0,1"
bitfld.long 0x8 4. "REFEN,RTC_REFIN reference clock detection enable (50 or 60 Hz)" "0,1"
bitfld.long 0x8 3. "TSEG,Time-stamp event active edge" "0,1"
newline
bitfld.long 0x8 0.--2. "WTCS,Auto-wakeup timer clock selection" "0,1,2,3,4,5,6,7"
line.long 0xC "STAT,initialization and status register"
rbitfld.long 0xC 17. "ITSF,Internal timestamp flag" "0,1"
rbitfld.long 0xC 16. "SCPF,Smooth calibration pending flag" "0,1"
bitfld.long 0xC 15. "TP2F,RTC_TAMP2 detection flag" "0,1"
bitfld.long 0xC 14. "TP1F,RTC_TAMP1 detection flag" "0,1"
bitfld.long 0xC 13. "TP0F,RTC_TAMP0 detection flag" "0,1"
bitfld.long 0xC 12. "TSOVRF,Time-stamp overflow flag" "0,1"
bitfld.long 0xC 11. "TSF,Time-stamp flag" "0,1"
newline
bitfld.long 0xC 10. "WTF,Wakeup timer flag" "0,1"
bitfld.long 0xC 9. "ALRM1F,Alarm1 flag" "0,1"
bitfld.long 0xC 8. "ALRM0F,Alarm0 flag" "0,1"
bitfld.long 0xC 7. "INITM,Initialization mode" "0,1"
rbitfld.long 0xC 6. "INITF,Initialization flag" "0,1"
bitfld.long 0xC 5. "RSYNF,Registers synchronization flag" "0,1"
rbitfld.long 0xC 4. "YCM,Initialization status flag" "0,1"
newline
rbitfld.long 0xC 3. "SOPF,Shift operation pending" "0,1"
rbitfld.long 0xC 2. "WTWF,Wakeup timer write enable flag" "0,1"
rbitfld.long 0xC 1. "ALRM1WF,Alarm1 write flag" "0,1"
rbitfld.long 0xC 0. "ALRM0WF,Alarm0 write flag" "0,1"
line.long 0x10 "PSC,prescaler register"
hexmask.long.byte 0x10 16.--22. 1. "FACTOR_A,Asynchronous prescaler factor"
hexmask.long.word 0x10 0.--14. 1. "FACTOR_S,Synchronous prescaler factor"
line.long 0x14 "WUT,Wakeup timer register"
hexmask.long.word 0x14 0.--15. 1. "WTRV,Auto-wakeup timer reloads value"
group.long 0x1C++0x7
line.long 0x0 "ALRM0TD,Alarm 0 time and date register"
bitfld.long 0x0 31. "MSKD,Alarm date mask" "0,1"
bitfld.long 0x0 30. "DOWS,Week day selection" "0,1"
bitfld.long 0x0 28.--29. "DAYT,Date tens in BCD format" "0,1,2,3"
hexmask.long.byte 0x0 24.--27. 1. "DAYU,Date units or day in BCD format"
bitfld.long 0x0 23. "MSKH,Alarm hours mask" "0,1"
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
bitfld.long 0x0 20.--21. "HRT,Hour tens in BCD format" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--19. 1. "HRU,Hour units in BCD format"
bitfld.long 0x0 15. "MSKM,Alarm minutes mask" "0,1"
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
bitfld.long 0x0 7. "MSKS,Alarm seconds mask" "0,1"
bitfld.long 0x0 4.--6. "SCT,Second tens in BCD format" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--3. 1. "SCU,Second units in BCD format"
line.long 0x4 "ALRM1TD,Alarm 1 time and date register"
bitfld.long 0x4 31. "MSKD,Alarm date mask" "0,1"
bitfld.long 0x4 30. "DOWS,Week day selection" "0,1"
bitfld.long 0x4 28.--29. "DAYT,Date tens in BCD format" "0,1,2,3"
hexmask.long.byte 0x4 24.--27. 1. "DAYU,Date units or day in BCD format"
bitfld.long 0x4 23. "MSKH,Alarm hours mask" "0,1"
bitfld.long 0x4 22. "PM,AM/PM notation" "0,1"
bitfld.long 0x4 20.--21. "HRT,Hour tens in BCD format" "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--19. 1. "HRU,Hour units in BCD format"
bitfld.long 0x4 15. "MSKM,Alarm minutes mask" "0,1"
bitfld.long 0x4 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 8.--11. 1. "MNU,Minute units in BCD format"
bitfld.long 0x4 7. "MSKS,Alarm seconds mask" "0,1"
bitfld.long 0x4 4.--6. "SCT,Second tens in BCD format" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 0.--3. 1. "SCU,Second units in BCD format"
wgroup.long 0x24++0x3
line.long 0x0 "WPK,write protection register"
hexmask.long.byte 0x0 0.--7. 1. "WPK,Write protection key"
rgroup.long 0x28++0x3
line.long 0x0 "SS,sub second register"
hexmask.long.word 0x0 0.--15. 1. "SSC,Sub second value"
wgroup.long 0x2C++0x3
line.long 0x0 "SHIFTCTL,shift control register"
bitfld.long 0x0 31. "A1S,One second add" "0,1"
hexmask.long.word 0x0 0.--14. 1. "SFS,Subtract a fraction of a second"
rgroup.long 0x30++0xB
line.long 0x0 "TTS,timestamp time register"
bitfld.long 0x0 22. "PM,AM/PM mark" "0,1"
bitfld.long 0x0 20.--21. "HRT,Hour tens in BCD code" "0,1,2,3"
hexmask.long.byte 0x0 16.--19. 1. "HRU,Hour units in BCD code"
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD code" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD code"
bitfld.long 0x0 4.--6. "SCT,Second tens in BCD code" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--3. 1. "SCU,Second units in BCD code"
line.long 0x4 "DTS,Date of time stamp register"
bitfld.long 0x4 13.--15. "DOW,Week day units" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 12. "MONT,Month tens in BCD code" "0,1"
hexmask.long.byte 0x4 8.--11. 1. "MONU,Month units in BCD code"
bitfld.long 0x4 4.--5. "DAYT,Date tens in BCD code" "0,1,2,3"
hexmask.long.byte 0x4 0.--3. 1. "DAYU,Date units in BCD code"
line.long 0x8 "SSTS,time-stamp sub second register"
hexmask.long.word 0x8 0.--15. 1. "SSC,Sub second value"
group.long 0x3C++0x93
line.long 0x0 "HRFC,High resolution frequency compensation register"
bitfld.long 0x0 15. "FREQI,Increase RTC frequency by 488.5PPM" "0,1"
bitfld.long 0x0 14. "CWND8,Frequency compensation window 8 second selected" "0,1"
bitfld.long 0x0 13. "CWND16,Frequency compensation window 16 second selected" "0,1"
hexmask.long.word 0x0 0.--8. 1. "CMSK,Calibration mask number"
line.long 0x4 "TAMP,tamper and alternate function configuration register"
bitfld.long 0x4 29. "TP2IE,Tamper 2 interrupt enable" "0,1"
bitfld.long 0x4 28. "TP1IE,Tamper 1 interrupt enable" "0,1"
bitfld.long 0x4 27. "TP0IE,Tamper 0 interrupt enable" "0,1"
bitfld.long 0x4 25. "TP2MASK,Tamper 2 mask flag" "0,1"
bitfld.long 0x4 24. "TP1MASK,Tamper 1 mask flag" "0,1"
bitfld.long 0x4 23. "TP0MASK,Tamper 0 mask flag" "0,1"
bitfld.long 0x4 21. "TP2_NOERASE,Tamper 2 no erase" "0,1"
newline
bitfld.long 0x4 20. "TP1_NOERASE,Tamper 1 no erase" "0,1"
bitfld.long 0x4 19. "TP0_NOERASE,Tamper 0 no erase" "0,1"
bitfld.long 0x4 16. "TP2_DISPIN,Tamper2 selection" "0,1"
bitfld.long 0x4 15. "DISPU,RTC_TAMPx pull-up disable" "0,1"
bitfld.long 0x4 13.--14. "PRCH,Pre-charge duration time of RTC_TAMPx" "0,1,2,3"
bitfld.long 0x4 11.--12. "FLT,RTC_TAMPx filter count setting" "0,1,2,3"
bitfld.long 0x4 8.--10. "FREQ,Sampling frequency of tamper event detection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 7. "TPTS,Make tamper function used for timestamp function" "0,1"
bitfld.long 0x4 6. "TP2EG,Tamper 2 event trigger edge" "0,1"
bitfld.long 0x4 5. "TP2EN,Tamper 2 detection enable" "0,1"
bitfld.long 0x4 4. "TP1EG,Tamper 1 event trigger edge" "0,1"
bitfld.long 0x4 3. "TP1EN,Tamper 1 detection enable" "0,1"
bitfld.long 0x4 2. "TPIE,Tamper detection interrupt enable" "0,1"
bitfld.long 0x4 1. "TP0EG,Tamper 0 event trigger edge" "0,1"
newline
bitfld.long 0x4 0. "TP0EN,Tamper 0 detection enable" "0,1"
line.long 0x8 "ALRM0SS,alarm 0 sub second register"
hexmask.long.byte 0x8 24.--27. 1. "MSKSSC,Mask control bit of SSC"
hexmask.long.word 0x8 0.--14. 1. "SSC,Alarm sub second value"
line.long 0xC "ALRM1SS,alarm 1 sub second register"
hexmask.long.byte 0xC 24.--27. 1. "MSKSSC,Mask control bit of SSC"
hexmask.long.word 0xC 0.--14. 1. "SSC,Alarm sub second value"
line.long 0x10 "CFG,Configuration register"
bitfld.long 0x10 1. "OUT2EN,RTC_OUT pin select" "0,1"
bitfld.long 0x10 0. "ALRMOUTTYPE,RTC_ALARM Output Type" "0,1"
line.long 0x14 "BKP0,backup register"
hexmask.long 0x14 0.--31. 1. "DATA,BKP data"
line.long 0x18 "BKP1,backup register"
hexmask.long 0x18 0.--31. 1. "DATA,BKP data"
line.long 0x1C "BKP2,backup register"
hexmask.long 0x1C 0.--31. 1. "DATA,BKP data"
line.long 0x20 "BKP3,backup register"
hexmask.long 0x20 0.--31. 1. "DATA,BKP data"
line.long 0x24 "BKP4,backup register"
hexmask.long 0x24 0.--31. 1. "DATA,BKP data"
line.long 0x28 "BKP5,backup register"
hexmask.long 0x28 0.--31. 1. "DATA,BKP data"
line.long 0x2C "BKP6,backup register"
hexmask.long 0x2C 0.--31. 1. "DATA,BKP data"
line.long 0x30 "BKP7,backup register"
hexmask.long 0x30 0.--31. 1. "DATA,BKP data"
line.long 0x34 "BKP8,backup register"
hexmask.long 0x34 0.--31. 1. "DATA,BKP data"
line.long 0x38 "BKP9,backup register"
hexmask.long 0x38 0.--31. 1. "DATA,BKP data"
line.long 0x3C "BKP10,Backup registe 10"
hexmask.long 0x3C 0.--31. 1. "DATA,Data"
line.long 0x40 "BKP11,Backup registe 11"
hexmask.long 0x40 0.--31. 1. "DATA,Data"
line.long 0x44 "BKP12,Backup registe 12"
hexmask.long 0x44 0.--31. 1. "DATA,Data"
line.long 0x48 "BKP13,Backup registe 13"
hexmask.long 0x48 0.--31. 1. "DATA,Data"
line.long 0x4C "BKP14,Backup registe 14"
hexmask.long 0x4C 0.--31. 1. "DATA,Data"
line.long 0x50 "BKP15,Backup registe 15"
hexmask.long 0x50 0.--31. 1. "DATA,Data"
line.long 0x54 "BKP16,Backup registe 16"
hexmask.long 0x54 0.--31. 1. "DATA,Data"
line.long 0x58 "BKP17,Backup registe 17"
hexmask.long 0x58 0.--31. 1. "DATA,Data"
line.long 0x5C "BKP18,Backup registe 18"
hexmask.long 0x5C 0.--31. 1. "DATA,Data"
line.long 0x60 "BKP19,Backup registe 19"
hexmask.long 0x60 0.--31. 1. "DATA,Data"
line.long 0x64 "BKP20,Backup registe 20"
hexmask.long 0x64 0.--31. 1. "DATA,Data"
line.long 0x68 "BKP21,Backup registe 21"
hexmask.long 0x68 0.--31. 1. "DATA,Data"
line.long 0x6C "BKP22,Backup registe 22"
hexmask.long 0x6C 0.--31. 1. "DATA,Data"
line.long 0x70 "BKP23,Backup registe 23"
hexmask.long 0x70 0.--31. 1. "DATA,Data"
line.long 0x74 "BKP24,Backup registe 24"
hexmask.long 0x74 0.--31. 1. "DATA,Data"
line.long 0x78 "BKP25,Backup registe 25"
hexmask.long 0x78 0.--31. 1. "DATA,Data"
line.long 0x7C "BKP26,Backup registe 26"
hexmask.long 0x7C 0.--31. 1. "DATA,Data"
line.long 0x80 "BKP27,Backup registe 27"
hexmask.long 0x80 0.--31. 1. "DATA,Data"
line.long 0x84 "BKP28,Backup registe 28"
hexmask.long 0x84 0.--31. 1. "DATA,Data"
line.long 0x88 "BKP29,Backup registe 29"
hexmask.long 0x88 0.--31. 1. "DATA,Data"
line.long 0x8C "BKP30,Backup registe 30"
hexmask.long 0x8C 0.--31. 1. "DATA,Data"
line.long 0x90 "BKP31,Backup registe 31"
hexmask.long 0x90 0.--31. 1. "DATA,Data"
tree.end
tree "SPI (Serial Peripheral Interface)"
base ad:0x0
tree "SPI0"
base ad:0x40013000
group.long 0x0++0x13
line.long 0x0 "CTL0,control register 0"
bitfld.long 0x0 15. "BDEN,Bidirectional enable" "0,1"
bitfld.long 0x0 14. "BDOEN,Bidirectional Transmit output enable" "0,1"
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0,1"
bitfld.long 0x0 12. "CRCNT,CRC transfer next" "0,1"
bitfld.long 0x0 11. "CRCL,CRC length" "0,1"
bitfld.long 0x0 10. "RO,Receive only" "0,1"
bitfld.long 0x0 9. "SWNSSEN,NSS Software Mode Selection" "0,1"
bitfld.long 0x0 8. "SWNSS,NSS Pin Selection In NSS Software Mode" "0,1"
bitfld.long 0x0 7. "LF,LSB First Mode" "0,1"
bitfld.long 0x0 6. "SPIEN,SPI enable" "0,1"
newline
bitfld.long 0x0 3.--5. "PSC,Master Clock Prescaler Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 2. "MSTMOD,Master Mode Enable" "0,1"
bitfld.long 0x0 1. "CKPL,Clock Polarity Selection" "0,1"
bitfld.long 0x0 0. "CKPH,Clock Phase Selection" "0,1"
line.long 0x4 "CTL1,control register 1"
bitfld.long 0x4 14. "TXDMA_ODD,Odd bytes in TX DMA channel" "0,1"
bitfld.long 0x4 13. "RXDMA_ODD,Odd bytes in RX DMA channel" "0,1"
bitfld.long 0x4 12. "BYTEN,Byte access enable" "0,1"
hexmask.long.byte 0x4 8.--11. 1. "DZ,Date size"
bitfld.long 0x4 7. "TBEIE,Transmit Buffer Empty Interrupt Enable" "0,1"
bitfld.long 0x4 6. "RBNEIE,Receive Buffer Not Empty Interrupt Enable" "0,1"
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
bitfld.long 0x4 4. "TMOD,SPI TI Mode Enable" "0,1"
bitfld.long 0x4 3. "NSSP,SPI NSS Pulse Mode Enable" "0,1"
bitfld.long 0x4 2. "NSSDRV,NSS output enable" "0,1"
newline
bitfld.long 0x4 1. "DMATEN,Tx buffer DMA enable" "0,1"
bitfld.long 0x4 0. "DMAREN,Rx buffer DMA enable" "0,1"
line.long 0x8 "STAT,status register"
rbitfld.long 0x8 11.--12. "TXLVL,Tx FIFO level" "0,1,2,3"
rbitfld.long 0x8 9.--10. "RXLVL,Rx FIFO level" "0,1,2,3"
bitfld.long 0x8 8. "FERR,Format Error" "0,1"
rbitfld.long 0x8 7. "TRANS,Transmitting ongoing Bit" "0,1"
rbitfld.long 0x8 6. "RXORERR,Reception Overrun Error Bit" "0,1"
rbitfld.long 0x8 5. "CONFERR,SPI Configuration error" "0,1"
bitfld.long 0x8 4. "CRCERR,SPI CRC Error Bit" "0,1"
rbitfld.long 0x8 1. "TBE,Transmit Buffer Empty" "0,1"
rbitfld.long 0x8 0. "RBNE,Receive Buffer Not Empty" "0,1"
line.long 0xC "DATA,data register"
hexmask.long.word 0xC 0.--15. 1. "DATA,Data register"
line.long 0x10 "CPCPOLY,CRC polynomial register"
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
rgroup.long 0x14++0x7
line.long 0x0 "RCRC,RX CRC register"
hexmask.long.word 0x0 0.--15. 1. "RCRC,RX RCR register"
line.long 0x4 "TCRC,TX CRC register"
hexmask.long.word 0x4 0.--15. 1. "TCRC,Tx CRC register"
group.long 0x80++0x3
line.long 0x0 "QCTL,SPI quad wird control register"
bitfld.long 0x0 2. "IO23_DRV,Drive IO2 and IO3 enable" "0,1"
bitfld.long 0x0 1. "QRD,Quad wire read select" "0,1"
bitfld.long 0x0 0. "QMOD,Quad wire mode enable" "0,1"
tree.end
tree "SPI1"
base ad:0x40003800
group.long 0x0++0x13
line.long 0x0 "CTL0,control register 0"
bitfld.long 0x0 15. "BDEN,Bidirectional enable" "0,1"
bitfld.long 0x0 14. "BDOEN,Bidirectional Transmit output enable" "0,1"
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0,1"
bitfld.long 0x0 12. "CRCNT,CRC transfer next" "0,1"
bitfld.long 0x0 11. "CRCL,CRC length" "0,1"
bitfld.long 0x0 10. "RO,Receive only" "0,1"
bitfld.long 0x0 9. "SWNSSEN,NSS Software Mode Selection" "0,1"
bitfld.long 0x0 8. "SWNSS,NSS Pin Selection In NSS Software Mode" "0,1"
bitfld.long 0x0 7. "LF,LSB First Mode" "0,1"
bitfld.long 0x0 6. "SPIEN,SPI enable" "0,1"
newline
bitfld.long 0x0 3.--5. "PSC,Master Clock Prescaler Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 2. "MSTMOD,Master Mode Enable" "0,1"
bitfld.long 0x0 1. "CKPL,Clock Polarity Selection" "0,1"
bitfld.long 0x0 0. "CKPH,Clock Phase Selection" "0,1"
line.long 0x4 "CTL1,control register 1"
bitfld.long 0x4 14. "TXDMA_ODD,Odd bytes in TX DMA channel" "0,1"
bitfld.long 0x4 13. "RXDMA_ODD,Odd bytes in RX DMA channel" "0,1"
bitfld.long 0x4 12. "BYTEN,Byte access enable" "0,1"
hexmask.long.byte 0x4 8.--11. 1. "DZ,Date size"
bitfld.long 0x4 7. "TBEIE,Transmit Buffer Empty Interrupt Enable" "0,1"
bitfld.long 0x4 6. "RBNEIE,Receive Buffer Not Empty Interrupt Enable" "0,1"
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
bitfld.long 0x4 4. "TMOD,SPI TI Mode Enable" "0,1"
bitfld.long 0x4 3. "NSSP,SPI NSS Pulse Mode Enable" "0,1"
bitfld.long 0x4 2. "NSSDRV,NSS output enable" "0,1"
newline
bitfld.long 0x4 1. "DMATEN,Tx buffer DMA enable" "0,1"
bitfld.long 0x4 0. "DMAREN,Rx buffer DMA enable" "0,1"
line.long 0x8 "STAT,status register"
rbitfld.long 0x8 11.--12. "TXLVL,Tx FIFO level" "0,1,2,3"
rbitfld.long 0x8 9.--10. "RXLVL,Rx FIFO level" "0,1,2,3"
bitfld.long 0x8 8. "FERR,Format Error" "0,1"
rbitfld.long 0x8 7. "TRANS,Transmitting ongoing Bit" "0,1"
rbitfld.long 0x8 6. "RXORERR,Reception Overrun Error Bit" "0,1"
rbitfld.long 0x8 5. "CONFERR,SPI Configuration error" "0,1"
bitfld.long 0x8 4. "CRCERR,SPI CRC Error Bit" "0,1"
rbitfld.long 0x8 1. "TBE,Transmit Buffer Empty" "0,1"
rbitfld.long 0x8 0. "RBNE,Receive Buffer Not Empty" "0,1"
line.long 0xC "DATA,data register"
hexmask.long.word 0xC 0.--15. 1. "DATA,Data register"
line.long 0x10 "CPCPOLY,CRC polynomial register"
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
rgroup.long 0x14++0x7
line.long 0x0 "RCRC,RX CRC register"
hexmask.long.word 0x0 0.--15. 1. "RCRC,RX RCR register"
line.long 0x4 "TCRC,TX CRC register"
hexmask.long.word 0x4 0.--15. 1. "TCRC,Tx CRC register"
tree.end
tree "SPI2"
base ad:0x40003C00
group.long 0x0++0x13
line.long 0x0 "CTL0,control register 0"
bitfld.long 0x0 15. "BDEN,Bidirectional enable" "0,1"
bitfld.long 0x0 14. "BDOEN,Bidirectional Transmit output enable" "0,1"
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0,1"
bitfld.long 0x0 12. "CRCNT,CRC transfer next" "0,1"
bitfld.long 0x0 11. "CRCL,CRC length" "0,1"
bitfld.long 0x0 10. "RO,Receive only" "0,1"
bitfld.long 0x0 9. "SWNSSEN,NSS Software Mode Selection" "0,1"
bitfld.long 0x0 8. "SWNSS,NSS Pin Selection In NSS Software Mode" "0,1"
bitfld.long 0x0 7. "LF,LSB First Mode" "0,1"
bitfld.long 0x0 6. "SPIEN,SPI enable" "0,1"
newline
bitfld.long 0x0 3.--5. "PSC,Master Clock Prescaler Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 2. "MSTMOD,Master Mode Enable" "0,1"
bitfld.long 0x0 1. "CKPL,Clock Polarity Selection" "0,1"
bitfld.long 0x0 0. "CKPH,Clock Phase Selection" "0,1"
line.long 0x4 "CTL1,control register 1"
bitfld.long 0x4 14. "TXDMA_ODD,Odd bytes in TX DMA channel" "0,1"
bitfld.long 0x4 13. "RXDMA_ODD,Odd bytes in RX DMA channel" "0,1"
bitfld.long 0x4 12. "BYTEN,Byte access enable" "0,1"
hexmask.long.byte 0x4 8.--11. 1. "DZ,Date size"
bitfld.long 0x4 7. "TBEIE,Transmit Buffer Empty Interrupt Enable" "0,1"
bitfld.long 0x4 6. "RBNEIE,Receive Buffer Not Empty Interrupt Enable" "0,1"
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
bitfld.long 0x4 4. "TMOD,SPI TI Mode Enable" "0,1"
bitfld.long 0x4 3. "NSSP,SPI NSS Pulse Mode Enable" "0,1"
bitfld.long 0x4 2. "NSSDRV,NSS output enable" "0,1"
newline
bitfld.long 0x4 1. "DMATEN,Tx buffer DMA enable" "0,1"
bitfld.long 0x4 0. "DMAREN,Rx buffer DMA enable" "0,1"
line.long 0x8 "STAT,status register"
rbitfld.long 0x8 11.--12. "TXLVL,Tx FIFO level" "0,1,2,3"
rbitfld.long 0x8 9.--10. "RXLVL,Rx FIFO level" "0,1,2,3"
bitfld.long 0x8 8. "FERR,Format Error" "0,1"
rbitfld.long 0x8 7. "TRANS,Transmitting ongoing Bit" "0,1"
rbitfld.long 0x8 6. "RXORERR,Reception Overrun Error Bit" "0,1"
rbitfld.long 0x8 5. "CONFERR,SPI Configuration error" "0,1"
bitfld.long 0x8 4. "CRCERR,SPI CRC Error Bit" "0,1"
rbitfld.long 0x8 1. "TBE,Transmit Buffer Empty" "0,1"
rbitfld.long 0x8 0. "RBNE,Receive Buffer Not Empty" "0,1"
line.long 0xC "DATA,data register"
hexmask.long.word 0xC 0.--15. 1. "DATA,Data register"
line.long 0x10 "CPCPOLY,CRC polynomial register"
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
rgroup.long 0x14++0x7
line.long 0x0 "RCRC,RX CRC register"
hexmask.long.word 0x0 0.--15. 1. "RCRC,RX RCR register"
line.long 0x4 "TCRC,TX CRC register"
hexmask.long.word 0x4 0.--15. 1. "TCRC,Tx CRC register"
tree.end
tree.end
tree "SYSCFG (System Configuration Registers)"
base ad:0x40010000
group.long 0x0++0x2B
line.long 0x0 "CFG0,System configuration register 0"
bitfld.long 0x0 8. "FMC_SWP,FMC memory mapping swap" "0,1"
bitfld.long 0x0 0.--2. "BOOT_MODE,Boot mode" "0,1,2,3,4,5,6,7"
line.long 0x4 "CFG1,System configuration register 1"
bitfld.long 0x4 31. "IXIE,FPU inexact interrupt enable bit" "0,1"
bitfld.long 0x4 30. "IDIE,FPU input denormal interrupt enable bit" "0,1"
bitfld.long 0x4 29. "OVFIE,FPU overflow interrupt enable bit" "0,1"
bitfld.long 0x4 28. "UFIE,FPU underflow interrupt enable bit" "0,1"
bitfld.long 0x4 27. "DZIE,FPU divide by 0 interrupt enable bit" "0,1"
newline
bitfld.long 0x4 26. "IOPIE,FPU invalid operation interrupt enable bit" "0,1"
bitfld.long 0x4 23. "I2C3FMPEN,I2C3 Fm+ mode enable" "0,1"
bitfld.long 0x4 22. "I2C2FMPEN,I2C2 Fm+ mode enable" "0,1"
bitfld.long 0x4 21. "I2C1FMPEN,I2C1 Fm+ mode enable" "0,1"
bitfld.long 0x4 20. "I2C0FMPEN,I2C0 Fm+ mode enable" "0,1"
newline
bitfld.long 0x4 19. "PB9FMPEN,I2C Fm+ mode on PB9 pin enable" "0,1"
bitfld.long 0x4 18. "PB8FMPEN,I2C Fm+ mode on PB8 pin enable" "0,1"
bitfld.long 0x4 17. "PB7FMPEN,I2C Fm+ mode on PB7 pin enable" "0,1"
bitfld.long 0x4 16. "PB6FMPEN,I2C Fm+ mode on PB6 pin enable" "0,1"
line.long 0x8 "EXTISS0,EXTI sources selection register 0"
hexmask.long.byte 0x8 12.--15. 1. "EXTI3_SS,EXTI 3 sources selection"
hexmask.long.byte 0x8 8.--11. 1. "EXTI2_SS,EXTI 2 sources selection"
hexmask.long.byte 0x8 4.--7. 1. "EXTI1_SS,EXTI 1 sources selection"
hexmask.long.byte 0x8 0.--3. 1. "EXTI0_SS,EXTI 0 sources selection"
line.long 0xC "EXTISS1,EXTI sources selection register 1"
hexmask.long.byte 0xC 12.--15. 1. "EXTI7_SS,EXTI 7 sources selection"
hexmask.long.byte 0xC 8.--11. 1. "EXTI6_SS,EXTI 6 sources selection"
hexmask.long.byte 0xC 4.--7. 1. "EXTI5_SS,EXTI 5 sources selection"
hexmask.long.byte 0xC 0.--3. 1. "EXTI4_SS,EXTI 4 sources selection"
line.long 0x10 "EXTISS2,EXTI sources selection register 2"
hexmask.long.byte 0x10 12.--15. 1. "EXTI11_SS,EXTI 11 sources selection"
hexmask.long.byte 0x10 8.--11. 1. "EXTI10_SS,EXTI 10 sources selection"
hexmask.long.byte 0x10 4.--7. 1. "EXTI9_SS,EXTI 9 sources selection"
hexmask.long.byte 0x10 0.--3. 1. "EXTI8_SS,EXTI 8 sources selection"
line.long 0x14 "EXTISS3,EXTI sources selection register 3"
hexmask.long.byte 0x14 12.--15. 1. "EXTI15_SS,EXTI 15 sources selection"
hexmask.long.byte 0x14 8.--11. 1. "EXTI14_SS,EXTI 14 sources selection"
hexmask.long.byte 0x14 4.--7. 1. "EXTI13_SS,EXTI 13 sources selection"
hexmask.long.byte 0x14 0.--3. 1. "EXTI12_SS,EXTI 12 sources selection"
line.long 0x18 "CFG2,System configuration register 2"
bitfld.long 0x18 25. "TRGSEL_RSTMD,Trigsel reset mode" "0,1"
bitfld.long 0x18 24. "PIN_RSTMD,Pin reset mode" "0,1"
bitfld.long 0x18 5. "TCMSRAM_ECC_LOCK,TCMSRAM ECC lock enable bit" "0,1"
bitfld.long 0x18 4. "SRAM1_ECC_LOCK,SRAM1 ECC lock enable bit" "0,1"
bitfld.long 0x18 3. "FLASH_ECC_LOCK,Flash ECC lockup enable bit" "0,1"
newline
bitfld.long 0x18 2. "LVD_LOCK,LVD lcokup enable bit" "0,1"
bitfld.long 0x18 1. "SRAM0_ECC_LOCK,SRAM0 ECC lockup enable bit" "0,1"
bitfld.long 0x18 0. "LOCKUP_LOCK,Cortex-M33 lockup (Hardfault) output enable bit" "0,1"
line.long 0x1C "STAT,System status register"
bitfld.long 0x1C 8. "TCMSRAMECCSEIF,TCMSRAM single bit correction interrupt flag" "0,1"
bitfld.long 0x1C 7. "TCMSRAMECCMEIF,TCMSRAM multi-bits (two bits) non-correction interrupt flag" "0,1"
bitfld.long 0x1C 6. "SRAM1ECCSEIF,SRAM1 single bit correction interrupt flag" "0,1"
bitfld.long 0x1C 5. "SRAM1ECCMEIF,SRAM1 multi-bits (two bits) non-correction interrupt flag" "0,1"
rbitfld.long 0x1C 4. "NMIPINIF,Interrupt flag from NMI pin" "0,1"
newline
bitfld.long 0x1C 3. "CKMNMIIF,HXTAL clock moniotor NMI interrupt flag" "0,1"
bitfld.long 0x1C 2. "FLASHECCIF,Flash ECC NMI interrupt flag" "0,1"
bitfld.long 0x1C 1. "SRAM0ECCSEIF,SRAM0 single bit correction interrupt flag" "0,1"
bitfld.long 0x1C 0. "SRAM0ECCMEIF,SRAM0 multi-bits (two bits) non-correction interrupt flag" "0,1"
line.long 0x20 "CFG3,System configuration register 3"
hexmask.long.word 0x20 17.--31. 1. "SRAM0ECCEADDR,Record the faulting system address (SRAM0ECCEADDR = SRAM0 address[16:0] >> 2) where the last SRAM0 ECC event on SRAM occurred"
hexmask.long.byte 0x20 10.--15. 1. "SRAM0ECCSERRBITS,Which one bit has SRAM0 ECC single-bit correctable error"
bitfld.long 0x20 4. "NMIPINIE,NMI pin interrupt enable" "0,1"
bitfld.long 0x20 3. "CKMNMIIE,HXTAL clock moniotor NMI interrupt enable" "0,1"
bitfld.long 0x20 2. "FLASHECCIE,Flash ECC NMI interrupt flag" "0,1"
newline
bitfld.long 0x20 1. "SRAM0ECCSEIE,SRAM0 single bit correction error interrupt enable" "0,1"
bitfld.long 0x20 0. "SRAM0ECCMEIE,SRAM0 multi-bits (two bits) non-correction error NMI interrupt enable" "0,1"
line.long 0x24 "CFG4,System configuration register 4"
hexmask.long.word 0x24 20.--31. 1. "SRAM1ECCEADDR,Record the faulting system address (SRAM1ECCEADDR = SRAM1 address[13:0] >> 2) where the last SRAM1 ECC event on SRAM occurred"
hexmask.long.byte 0x24 10.--15. 1. "SRAM1ECCSERRBITS,Which one bit has SRAM1 ECC single-bit correctable error"
bitfld.long 0x24 1. "SRAM1ECCSEIE,SRAM1 single bit correction error event flag" "0,1"
bitfld.long 0x24 0. "SRAM1ECCMEIE,SRAM1 multi-bits (two bits) non-correction error event flag" "0,1"
line.long 0x28 "CFG5,System configuration register 5"
hexmask.long.word 0x28 19.--31. 1. "TCMSRAMECCEADDR,Record the faulting system address (TCMSRAMECCEADDR = TCM SRAM address[14:0] >> 2) where the last TCMSRAM ECC event on SRAM occurred"
hexmask.long.byte 0x28 10.--15. 1. "TCMSRAMECCSERRBITS,Which one bit has TCMSRAM ECC single-bit correctable error"
bitfld.long 0x28 1. "TCMSRAMECCSEIE,TCMSRAM single bit correction error event flag" "0,1"
bitfld.long 0x28 0. "TCMSRAMECCMEIE,TCMSRAM multi-bits (two bits) non-correction error event flag" "0,1"
group.long 0x30++0x3
line.long 0x0 "TCMSRAMCS,SYSCFG TCMSRAM control and status register"
rbitfld.long 0x0 1. "TCMSRAMBSY,TCMSRAM busy flag by erase operation" "0,1"
bitfld.long 0x0 0. "TCMSRAMERS,TCMSRAM erase" "0,1"
wgroup.long 0x34++0x3
line.long 0x0 "TCMSRAMKEY,SYSCFG TCMSRAM key register"
hexmask.long.byte 0x0 0.--7. 1. "WP_KEY,TCMSRAM write protection key"
group.long 0x38++0x7
line.long 0x0 "TCMSRAMWP,SYSCFG TCMSRAM write protection register"
bitfld.long 0x0 31. "P31WPEN,TCMSRAM page 31 write protection enable bit" "0,1"
bitfld.long 0x0 30. "P30WPEN,TCMSRAM page 30 write protection enable bit" "0,1"
bitfld.long 0x0 29. "P29WPEN,TCMSRAM page 29 write protection enable bit" "0,1"
bitfld.long 0x0 28. "P28WPEN,TCMSRAM page 28 write protection enable bit" "0,1"
bitfld.long 0x0 27. "P27WPEN,TCMSRAM page 27 write protection enable bit" "0,1"
newline
bitfld.long 0x0 26. "P26WPEN,TCMSRAM page 26 write protection enable bit" "0,1"
bitfld.long 0x0 25. "P25WPEN,TCMSRAM page 25 write protection enable bit" "0,1"
bitfld.long 0x0 24. "P24WPEN,TCMSRAM page 24 write protection enable bit" "0,1"
bitfld.long 0x0 23. "P23WPEN,TCMSRAM page 23 write protection enable bit" "0,1"
bitfld.long 0x0 22. "P22WPEN,TCMSRAM page 22 write protection enable bit" "0,1"
newline
bitfld.long 0x0 21. "P21WPEN,TCMSRAM page 21 write protection enable bit" "0,1"
bitfld.long 0x0 20. "P20WPEN,TCMSRAM page 20 write protection enable bit" "0,1"
bitfld.long 0x0 19. "P19WPEN,TCMSRAM page 19 write protection enable bit" "0,1"
bitfld.long 0x0 18. "P18WPEN,TCMSRAM page 18 write protection enable bit" "0,1"
bitfld.long 0x0 17. "P17WPEN,TCMSRAM page 17 write protection enable bit" "0,1"
newline
bitfld.long 0x0 16. "P16WPEN,TCMSRAM page 16 write protection enable bit" "0,1"
bitfld.long 0x0 15. "P15WPEN,TCMSRAM page 15 write protection enable bit" "0,1"
bitfld.long 0x0 14. "P14WPEN,TCMSRAM page 14 write protection enable bit" "0,1"
bitfld.long 0x0 13. "P13WPEN,TCMSRAM page 13 write protection enable bit" "0,1"
bitfld.long 0x0 12. "P12WPEN,TCMSRAM page 12 write protection enable bit" "0,1"
newline
bitfld.long 0x0 11. "P11WPEN,TCMSRAM page 11 write protection enable bit" "0,1"
bitfld.long 0x0 10. "P10WPEN,TCMSRAM page 10 write protection enable bit" "0,1"
bitfld.long 0x0 9. "P9WPEN,TCMSRAM page 9 write protection enable bit" "0,1"
bitfld.long 0x0 8. "P8WPEN,TCMSRAM page 8 write protection enable bit" "0,1"
bitfld.long 0x0 7. "P7WPEN,TCMSRAM page 7 write protection enable bit" "0,1"
newline
bitfld.long 0x0 6. "P6WPEN,TCMSRAM page 6 write protection enable bit" "0,1"
bitfld.long 0x0 5. "P5WPEN,TCMSRAM page 5 write protection enable bit" "0,1"
bitfld.long 0x0 4. "P4WPEN,TCMSRAM page 4 write protection enable bit" "0,1"
bitfld.long 0x0 3. "P3WPEN,TCMSRAM page 3 write protection enable bit" "0,1"
bitfld.long 0x0 2. "P2WPEN,TCMSRAM page 2 write protection enable bit" "0,1"
newline
bitfld.long 0x0 1. "P1WPEN,TCMSRAM page 1 write protection enable bit" "0,1"
bitfld.long 0x0 0. "P0WPEN,TCMSRAM page 0 write protection enable bit" "0,1"
line.long 0x4 "CPSCTL,I/O Compensation cell control/status register"
rbitfld.long 0x4 8. "CPS_RDY,Compensation cell ready flag" "0,1"
bitfld.long 0x4 0. "CPS_EN,I/O compensation cell enable" "0,1"
group.long 0x44++0x13
line.long 0x0 "TIMERCISEL0,Timer input selection register 0"
hexmask.long.byte 0x0 28.--31. 1. "TIMER0_CI3_SEL,Selects TIMER0_CI3 input"
hexmask.long.byte 0x0 24.--27. 1. "TIMER0_CI2_SEL,Selects TIMER0_CI2 input"
hexmask.long.byte 0x0 20.--23. 1. "TIMER0_CI1_SEL,Selects TIMER0_CI1 input"
hexmask.long.byte 0x0 16.--19. 1. "TIMER0_CI0_SEL,Selects TIMER0_CI0 input"
hexmask.long.byte 0x0 12.--15. 1. "TIMER7_CI3_SEL,Selects TIMER7_CI3 input"
newline
hexmask.long.byte 0x0 8.--11. 1. "TIMER7_CI2_SEL,Selects TIMER7_CI2 input"
hexmask.long.byte 0x0 4.--7. 1. "TIMER7_CI1_SEL,Selects TIMER7_CI1 input"
hexmask.long.byte 0x0 0.--3. 1. "TIMER7_CI0_SEL,Selects TIMER7_CI0 input"
line.long 0x4 "TIMERCISEL1,Timer input selection register 1"
hexmask.long.byte 0x4 12.--15. 1. "TIMER19_CI3_SEL,Selects TIMER19_CI3 input"
hexmask.long.byte 0x4 8.--11. 1. "TIMER19_CI2_SEL,Selects TIMER19_CI2 input"
hexmask.long.byte 0x4 4.--7. 1. "TIMER19_CI1_SEL,Selects TIMER19_CI1 input"
hexmask.long.byte 0x4 0.--3. 1. "TIMER19_CI0_SEL,Selects TIMER19_CI0 input"
line.long 0x8 "TIMERCISEL2,Timer input selection register 2"
hexmask.long.byte 0x8 28.--31. 1. "TIMER1_CI3_SEL,TIMER1_CI3 input selection"
hexmask.long.byte 0x8 24.--27. 1. "TIMER1_CI2_SEL,TIMER1_CI2 input selection"
hexmask.long.byte 0x8 20.--23. 1. "TIMER1_CI1_SEL,TIMER1_CI1 input selection"
hexmask.long.byte 0x8 16.--19. 1. "TIMER1_CI0_SEL,TIMER1_CI0 input selection"
hexmask.long.byte 0x8 12.--15. 1. "TIMER2_CI3_SEL,TIMER2_CI3 input selection"
newline
hexmask.long.byte 0x8 8.--11. 1. "TIMER2_CI2_SEL,TIMER2_CI2 input selection"
hexmask.long.byte 0x8 4.--7. 1. "TIMER2_CI1_SEL,TIMER2_CI1 input selection"
hexmask.long.byte 0x8 0.--3. 1. "TIMER2_CI0_SEL,TIMER2_CI0 input selection"
line.long 0xC "TIMERCISEL3,Timer input selection register 3"
hexmask.long.byte 0xC 28.--31. 1. "TIMER3_CI3_SEL,TIMER3_CI3 input selection"
hexmask.long.byte 0xC 24.--27. 1. "TIMER3_CI2_SEL,TIMER3_CI2 input selection"
hexmask.long.byte 0xC 20.--23. 1. "TIMER3_CI1_SEL,TIMER3_CI1 input selection"
hexmask.long.byte 0xC 16.--19. 1. "TIMER3_CI0_SEL,TIMER3_CI0 input selection"
hexmask.long.byte 0xC 12.--15. 1. "TIMER4_CI3_SEL,TIMER4_CI3 input selection"
newline
hexmask.long.byte 0xC 8.--11. 1. "TIMER4_CI2_SEL,TIMER4_CI2 input selection"
hexmask.long.byte 0xC 4.--7. 1. "TIMER4_CI1_SEL,TIMER4_CI1 input selection"
hexmask.long.byte 0xC 0.--3. 1. "TIMER4_CI0_SEL,TIMER4_CI0 input selection"
line.long 0x10 "TIMERCISEL4,Timer input selection register 4"
hexmask.long.byte 0x10 12.--15. 1. "TIMER16_CI0_SEL,Selects TIMER16_CI0 input"
hexmask.long.byte 0x10 8.--11. 1. "TIMER15_CI0_SEL,Selects TIMER15_CI0 input"
hexmask.long.byte 0x10 4.--7. 1. "TIMER14_CI1_SEL,Selects TIMER14_CI1 input"
hexmask.long.byte 0x10 0.--3. 1. "TIMER14_CI0_SEL,Selects TIMER14_CI0 input"
group.long 0x100++0x3
line.long 0x0 "TIMER0CFG0,TIMER0 configuration register 0"
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
hexmask.long.byte 0x0 10.--14. 1. "TSCFG2,Quadrature decoder mode 2 configuration"
hexmask.long.byte 0x0 5.--9. 1. "TSCFG1,Quadrature decoder mode 1 configuration"
newline
hexmask.long.byte 0x0 0.--4. 1. "TSCFG0,Quadrature decoder mode 0 configuration"
group.long 0x10C++0x3
line.long 0x0 "TIMER1CFG0,TIMER1 configuration register 0"
group.long 0x118++0x3
line.long 0x0 "TIMER2CFG0,TIMER2 configuration register 0"
group.long 0x124++0x3
line.long 0x0 "TIMER3CFG0,TIMER3 configuration register 0"
group.long 0x130++0x3
line.long 0x0 "TIMER4CFG0,TIMER4 configuration register 0"
group.long 0x13C++0x3
line.long 0x0 "TIMER7CFG0,TIMER7 configuration register 0"
group.long 0x154++0x3
line.long 0x0 "TIMER19CFG0,TIMER19 configuration register 0"
group.long 0x104++0x3
line.long 0x0 "TIMER0CFG1,TIMER1 configuration register 1"
hexmask.long.byte 0x0 26.--30. 1. "TSCFG11,Decoder mode 2 configuration"
hexmask.long.byte 0x0 21.--25. 1. "TSCFG10,Decoder mode 1 configuration"
hexmask.long.byte 0x0 16.--20. 1. "TSCFG9,Decoder mode 0 configuration"
hexmask.long.byte 0x0 10.--14. 1. "TSCFG8,Pause + restart mode configuration"
hexmask.long.byte 0x0 5.--9. 1. "TSCFG7,Restart + event mode configuration"
newline
hexmask.long.byte 0x0 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
group.long 0x110++0x3
line.long 0x0 "TIMER1CFG1,TIMER1 configuration register 1"
group.long 0x11C++0x3
line.long 0x0 "TIMER2CFG1,TIMER2 configuration register 1"
group.long 0x128++0x3
line.long 0x0 "TIMER3CFG1,TIMER3 configuration register 1"
group.long 0x134++0x3
line.long 0x0 "TIMER4CFG1,TIMER4 configuration register 1"
group.long 0x140++0x3
line.long 0x0 "TIMER7CFG1,TIMER7 configuration register 1"
group.long 0x158++0x3
line.long 0x0 "TIMER19CFG1,TIMER19 configuration register 1"
group.long 0x108++0x3
line.long 0x0 "TIMER0CFG2,TIMERx configuration register 2"
hexmask.long.byte 0x0 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
hexmask.long.byte 0x0 10.--14. 1. "TSCFG14,Quadrature decoder mode 4 configuration"
hexmask.long.byte 0x0 5.--9. 1. "TSCFG13,Quadrature decoder mode 3 configuration"
hexmask.long.byte 0x0 0.--4. 1. "TSCFG12,Decoder mode 3 configuration"
group.long 0x114++0x3
line.long 0x0 "TIMER1CFG2,TIMER1 configuration register 2"
group.long 0x120++0x3
line.long 0x0 "TIMER2CFG2,TIMER2 configuration register 2"
group.long 0x12C++0x3
line.long 0x0 "TIMER3CFG2,TIMER3 configuration register 2"
group.long 0x138++0x3
line.long 0x0 "TIMER4CFG2,TIMER4 configuration register 2"
group.long 0x144++0x3
line.long 0x0 "TIMER7CFG2,TIMER7 configuration register 2"
group.long 0x15C++0x3
line.long 0x0 "TIMER19CFG2,TIMER19 configuration register 2"
group.long 0x148++0xB
line.long 0x0 "TIMER14CFG0,TIMERx configuration register 0"
hexmask.long.byte 0x0 26.--30. 1. "TSCFG5,Event mode configuration"
hexmask.long.byte 0x0 21.--25. 1. "TSCFG4,Pause mode configuration"
hexmask.long.byte 0x0 16.--20. 1. "TSCFG3,Restart mode configuration"
line.long 0x4 "TIMER14CFG1,TIMERx configuration register 1"
hexmask.long.byte 0x4 5.--9. 1. "TSCFG7,Restart + event mode configuration"
hexmask.long.byte 0x4 0.--4. 1. "TSCFG6,External clock mode 0 configuration"
line.long 0x8 "TIMER14CFG2,TIMERx configuration register 2"
hexmask.long.byte 0x8 16.--20. 1. "TSCFG15,Internal trigger input source configuration"
tree.end
tree "TIMER (Timer)"
base ad:0x0
tree "TIMER0 (Advanced Timer)"
base ad:0x40012C00
group.long 0x0++0x13
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 12. "ADMEN,Adjustment mode enable" "0,1"
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
bitfld.long 0x0 4. "DIR,Direction" "0,1"
newline
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x0 2. "UPS,Update source" "0,1"
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 30.--31. "CCUC1_2,Commutation control shadow register update control" "0,1,2,3"
bitfld.long 0x4 25. "MMC0_3,Master mode control 0" "0,1"
bitfld.long 0x4 20.--22. "MMC1,Master mode control 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 15. "ISO3N,Idle state of multi mode channel 3 complementary output" "0,1"
bitfld.long 0x4 14. "ISO3,Idle state of channel 3 output" "0,1"
bitfld.long 0x4 13. "ISO2N,Idle state of multi mode channel 2 complementary output" "0,1"
newline
bitfld.long 0x4 12. "ISO2,Idle state of channel 2 output" "0,1"
bitfld.long 0x4 11. "ISO1N,Idle state of multi mode channel 1 complementary output" "0,1"
bitfld.long 0x4 10. "ISO1,Idle state of channel 1 output" "0,1"
bitfld.long 0x4 9. "ISO0N,Idle state of multi mode channel 0 complementary output" "0,1"
bitfld.long 0x4 8. "ISO0,Idle state of channel 0 output" "0,1"
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
newline
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
bitfld.long 0x4 2. "CCUC,Commutation control shadow register update control" "0,1"
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
line.long 0x8 "SMCFG,Slave mode configuration register"
bitfld.long 0x8 26. "PRMRPSEL,Pause + restart mode reset polarity selection" "0,1"
bitfld.long 0x8 25. "DECMODS,Decoder mode update source" "0,1"
bitfld.long 0x8 24. "DECMODEN,Decoder mode modified on-the-fly enable" "0,1"
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
bitfld.long 0x8 14. "SMC1,Part of slave mode controller is used to enable external clock mode 1" "0,1"
bitfld.long 0x8 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
newline
hexmask.long.byte 0x8 8.--11. 1. "ETFC,External trigger filter control"
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
bitfld.long 0x8 3. "OCRC,OxCPRE / MOxCPRE clear source selection" "0,1"
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
bitfld.long 0xC 31. "CH3COMADDIE,Channel 3 additional compare interrupt enable" "0,1"
bitfld.long 0xC 30. "CH2COMADDIE,Channel 2 additional compare interrupt enable" "0,1"
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
bitfld.long 0xC 27. "MCH3DEN,Multi mode channel 3 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 26. "MCH2DEN,Multi mode channel 2 capture / compare DMA request enable" "0,1"
newline
bitfld.long 0xC 25. "MCH1DEN,Multi mode channel 1 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 24. "MCH0DEN,Multi mode channel 0 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 23. "MCH3IE,Multi mode channel 3 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 22. "MCH2IE,Multi mode channel 2 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 21. "MCH1IE,Multi mode channel 1 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 20. "MCH0IE,Multi mode channel 0 capture / compare interrupt enable" "0,1"
newline
bitfld.long 0xC 19. "INDERRIE,Index error interrupt enable" "0,1"
bitfld.long 0xC 18. "DIRTRANIE,Direction transform interrupt enable" "0,1"
bitfld.long 0xC 17. "DECDISIE,Quadrature decoder signal disconnection interrupt enable" "0,1"
bitfld.long 0xC 16. "DECJIE,Quadrature decoder signal jump (the two signals jump at the same time) interrupt enable" "0,1"
bitfld.long 0xC 15. "INDIE,Index interrupt enable" "0,1"
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
newline
bitfld.long 0xC 13. "CMTDEN,Commutation DMA request enable" "0,1"
bitfld.long 0xC 12. "CH3DEN,Channel 3 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 11. "CH2DEN,Channel 2 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
newline
bitfld.long 0xC 7. "BRKIE,Break interrupt enable" "0,1"
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
bitfld.long 0xC 5. "CMTIE,Commutation interrupt enable" "0,1"
bitfld.long 0xC 4. "CH3IE,Channel 3 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 3. "CH2IE,Channel 2 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 2. "CH1IE,Channel 1 capture / compare interrupt enable" "0,1"
newline
bitfld.long 0xC 1. "CH0IE,Channel 0 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
line.long 0x10 "INTF,Interrupt flag register"
bitfld.long 0x10 31. "CH3COMADDIF,Channel 3 additional compare interrupt flag" "0,1"
bitfld.long 0x10 30. "CH2COMADDIF,Channel 2 additional compare interrupt flag" "0,1"
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
bitfld.long 0x10 27. "MCH3OF,Multi mode channel 3 over capture flag" "0,1"
bitfld.long 0x10 26. "MCH2OF,Multi mode channel 2 over capture flag" "0,1"
newline
bitfld.long 0x10 25. "MCH1OF,Multi mode channel 1 over capture flag" "0,1"
bitfld.long 0x10 24. "MCH0OF,Multi mode channel 0 over capture flag" "0,1"
bitfld.long 0x10 23. "MCH3IF,Multi mode channel 3 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 22. "MCH2IF,Multi mode channel 2 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 21. "MCH1IF,Multi mode channel 1 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 20. "MCH0IF,Multi mode channel 0 capture / compare interrupt flag" "0,1"
newline
bitfld.long 0x10 19. "INDERRIF,Index error interrupt flag" "0,1"
bitfld.long 0x10 18. "DIRTRANIF,Direction transform interrupt flag" "0,1"
bitfld.long 0x10 17. "DECDISIF,Quadrature decoder signal disconnection interrupt flag" "0,1"
bitfld.long 0x10 16. "DECJIF,Quadrature decoder signal jump (the two signals jump at the same time) interrupt flag" "0,1"
bitfld.long 0x10 15. "INDIF,Index interrupt flag" "0,1"
bitfld.long 0x10 13. "SYSBIF,System source break interrupt flag" "0,1"
newline
bitfld.long 0x10 12. "CH3OF,Channel 3 over capture flag" "0,1"
bitfld.long 0x10 11. "CH2OF,Channel 2 over capture flag" "0,1"
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
bitfld.long 0x10 8. "BRK1IF,BREAK1 interrupt flag" "0,1"
bitfld.long 0x10 7. "BRK0IF,BREAK0 interrupt flag" "0,1"
newline
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
bitfld.long 0x10 5. "CMTIF,Channel commutation interrupt flag" "0,1"
bitfld.long 0x10 4. "CH3IF,Channel 3 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 3. "CH2IF,Channel 2 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 2. "CH1IF,Channel 1 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 1. "CH0IF,Channel 0 capture / compare interrupt flag" "0,1"
newline
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x3
line.long 0x0 "SWEVG,Software event generation register"
bitfld.long 0x0 31. "CH3COMADDG,Channel 3 additional compare event generation" "0,1"
bitfld.long 0x0 30. "CH2COMADDG,Channel 2 additional compare event generation" "0,1"
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
bitfld.long 0x0 23. "MCH3G,Multi mode channel 3 capture or compare event generation" "0,1"
bitfld.long 0x0 22. "MCH2G,Multi mode channel 2 capture or compare event generation" "0,1"
newline
bitfld.long 0x0 21. "MCH1G,Multi mode channel 1 capture or compare event generation" "0,1"
bitfld.long 0x0 20. "MCH0G,Multi mode channel 0 capture or compare event generation" "0,1"
bitfld.long 0x0 8. "BRK1G,BREAK1 event generation" "0,1"
bitfld.long 0x0 7. "BRK0G,BREAK0 event generation" "0,1"
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
bitfld.long 0x0 5. "CMTG,Channel commutation event generation" "0,1"
newline
bitfld.long 0x0 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
bitfld.long 0x0 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
group.long 0x18++0x3
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
bitfld.long 0x0 27. "CH1ADDUPS,Channel 1 additional update source" "0,1"
bitfld.long 0x0 26. "CH0ADDUPS,Channel 0 additional update source" "0,1"
newline
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
bitfld.long 0x0 10. "CH1COMFEN,Channel 1 output compare fast enable" "0,1"
newline
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
bitfld.long 0x0 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x7
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input mode)"
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
bitfld.long 0x0 27. "CH1ADDUPS,Channel 1 additional update source" "0,1"
bitfld.long 0x0 26. "CH0ADDUPS,Channel 0 additional update source" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
line.long 0x4 "CHCTL1_Output,Channel control register 1 (output mode)"
bitfld.long 0x4 31. "CH3MS_2,2th bit of CH3MS" "0,1"
bitfld.long 0x4 30. "CH2MS_2,2th bit of CH2MS" "0,1"
bitfld.long 0x4 29. "CH3COMADDSEN,Channel 3 additional compare output shadow enable" "0,1"
bitfld.long 0x4 28. "CH2COMADDSEN,Channel 2 additional compare output shadow enable" "0,1"
bitfld.long 0x4 27. "CH3ADDUPS,Channel 3 additional update source" "0,1"
bitfld.long 0x4 26. "CH2ADDUPS,Channel 2 additional update source" "0,1"
newline
bitfld.long 0x4 24. "CH3COMCTL_3,BIT 3 of channel 3 compare output control" "0,1"
bitfld.long 0x4 16. "CH2COMCTL_3,BIT 3 of channel 2 compare output control" "0,1"
bitfld.long 0x4 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
bitfld.long 0x4 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
bitfld.long 0x4 10. "CH3COMFEN,Channel 3 output compare fast enable" "0,1"
newline
bitfld.long 0x4 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
bitfld.long 0x4 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
bitfld.long 0x4 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
bitfld.long 0x4 2. "CH2COMFEN,Channel 2 output compare fast enable" "0,1"
bitfld.long 0x4 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
group.long 0x1C++0x2F
line.long 0x0 "CHCTL1_Input,Channel control register 1 (input mode)"
bitfld.long 0x0 31. "CH3MS_2,2th bit of CH3MS" "0,1"
bitfld.long 0x0 30. "CH2MS_2,2th bit of CH2MS" "0,1"
bitfld.long 0x0 27. "CH3ADDUPS,Channel 3 additional update source" "0,1"
bitfld.long 0x0 26. "CH2ADDUPS,Channel 2 additional update source" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "CH3CAPFLT,Channel 3 input capture filter control"
bitfld.long 0x0 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "CH2CAPFLT,Channel 2 input capture filter control"
bitfld.long 0x0 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
line.long 0x4 "CHCTL2,Channel control register 2"
bitfld.long 0x4 15. "MCH3P,Multi mode channel 3 capture / compare polarity" "0,1"
bitfld.long 0x4 14. "MCH3EN,Multi mode channel 3 capture / compare enable" "0,1"
bitfld.long 0x4 13. "CH3P,Channel 3 capture / compare polarity" "0,1"
bitfld.long 0x4 12. "CH3EN,Channel 3 capture / compare enable" "0,1"
bitfld.long 0x4 11. "MCH2P,Multi mode channel 2 output polarity" "0,1"
bitfld.long 0x4 10. "MCH2EN,Multi mode channel 2 output enable" "0,1"
newline
bitfld.long 0x4 9. "CH2P,Channel 2 capture / compare polarity" "0,1"
bitfld.long 0x4 8. "CH2EN,Channel 2 capture / compare enable" "0,1"
bitfld.long 0x4 7. "MCH1P,Multi mode channel 1 output polarity" "0,1"
bitfld.long 0x4 6. "MCH1EN,Multi mode channel 1 output enable" "0,1"
bitfld.long 0x4 5. "CH1P,Channel 1 capture / compare polarity" "0,1"
bitfld.long 0x4 4. "CH1EN,Channel 1 capture / compare enable" "0,1"
newline
bitfld.long 0x4 3. "MCH0P,Multi mode channel 0 output polarity" "0,1"
bitfld.long 0x4 2. "MCH0EN,Multi mode channel 0 capture / compare enable" "0,1"
bitfld.long 0x4 1. "CH0P,Channel 0 capture / compare polarity" "0,1"
bitfld.long 0x4 0. "CH0EN,Channel 0 capture / compare enable" "0,1"
line.long 0x8 "CNT,Counter register"
rbitfld.long 0x8 31. "UPIFBU,UPIF bit backup" "0,1"
hexmask.long.word 0x8 0.--15. 1. "CNT,This bit-field indicates the current counter value"
line.long 0xC "PSC,Prescaler register"
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value of the counter clock"
line.long 0x10 "CAR,Counter auto reload register"
hexmask.long.byte 0x10 28.--31. 1. "CARL16_19,Counter auto reload value(bit 16 to 19)"
hexmask.long.word 0x10 0.--15. 1. "CARL,Counter auto reload value (bit 0 to 15)"
line.long 0x14 "CREP0,Counter repetition register 0"
hexmask.long.byte 0x14 0.--7. 1. "CREP0,Counter repetition value 0"
line.long 0x18 "CH0CV,Channel 0 capture/compare value register"
hexmask.long.byte 0x18 28.--31. 1. "CH0VAL16_19,Capture / compare value of channel0 (bit 16 to 19)"
hexmask.long.word 0x18 0.--15. 1. "CH0VAL,Capture / compare value of channel 0"
line.long 0x1C "CH1CV,Channel 1 capture/compare value register"
hexmask.long.byte 0x1C 28.--31. 1. "CH1VAL16_19,Capture / compare value of channel1 (bit 16 to 19)"
hexmask.long.word 0x1C 0.--15. 1. "CH1VAL,Capture / compare value of channel 1 (bit 0 to 15)"
line.long 0x20 "CH2CV,Channel 2 capture/compare value register"
hexmask.long.byte 0x20 28.--31. 1. "CH2VAL16_19,Capture / compare value of channel 2 (bit 16 to 19)"
hexmask.long.word 0x20 0.--15. 1. "CH2VAL,Capture or compare value of channel 2"
line.long 0x24 "CH3CV,Channel 3 capture/compare value register"
hexmask.long.byte 0x24 28.--31. 1. "CH3VAL16_19,Capture / compare value of channel 3 (bit 16 to 19)"
hexmask.long.word 0x24 0.--15. 1. "CH3VAL,Capture / compare value of channel 3 (bit 0 to 15)"
line.long 0x28 "CCHP0,Complementary channel protection register 0"
bitfld.long 0x28 29. "BRK1LK,BREAK1 input locked" "0,1"
bitfld.long 0x28 28. "BRK0LK,BREAK0 input locked" "0,1"
bitfld.long 0x28 27. "BRK1REL,BREAK1 input released" "0,1"
bitfld.long 0x28 26. "BRK0REL,BREAK0 input released" "0,1"
bitfld.long 0x28 25. "BRK1P,BREAK1 input signal polarity" "0,1"
bitfld.long 0x28 24. "BRK1EN,BREAK1 input signal enable" "0,1"
newline
hexmask.long.byte 0x28 20.--23. 1. "BRK1F,BREAK1 input signal filter"
hexmask.long.byte 0x28 16.--19. 1. "BRK0F,BREAK0 input signal filter"
bitfld.long 0x28 15. "POEN,Primary output enable" "0,1"
bitfld.long 0x28 14. "OAEN,Output automatic enable" "0,1"
bitfld.long 0x28 13. "BRK0P,BREAK0 input signal polarity" "0,1"
bitfld.long 0x28 12. "BRK0EN,BREAK0 input signal enable" "0,1"
newline
bitfld.long 0x28 11. "ROS,Run mode off-state enable" "0,1"
bitfld.long 0x28 10. "IOS,Idle mode off-state enable" "0,1"
bitfld.long 0x28 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
hexmask.long.byte 0x28 0.--7. 1. "DTCFG,Dead time configuration"
line.long 0x2C "MCHCTL0_Output,Multi mode channel control register 0 (output mode)"
bitfld.long 0x2C 31. "MCH1MS_2,Multi mode channel 1 I/O mode selection" "0,1"
bitfld.long 0x2C 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
bitfld.long 0x2C 24. "MCH1COMCT_3,Multi mode channel 1 compare output control" "0,1"
bitfld.long 0x2C 16. "MCH0COMCTL_3,Multi mode channel 0 compare output control" "0,1"
bitfld.long 0x2C 15. "MCH1COMCEN,Multi mode channel 1 output compare clear enable" "0,1"
bitfld.long 0x2C 12.--14. "MCH1COMCTL,Multi mode channel 1 compare output control" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2C 11. "MCH1COMSEN,Multi mode channel 1 output compare shadow enable" "0,1"
bitfld.long 0x2C 10. "MCH1COMFEN,Multi mode channel 1 output compare fast enable" "0,1"
bitfld.long 0x2C 8.--9. "MCH1MS,Multi mode channel 1 I/O mode selection" "0,1,2,3"
bitfld.long 0x2C 7. "MCH0COMCEN,Multi mode channel 0 output compare clear enable" "0,1"
bitfld.long 0x2C 4.--6. "MCH0COMCTL,Multi mode channel 0 output compare control" "0,1,2,3,4,5,6,7"
bitfld.long 0x2C 3. "MCH0COMSEN,Multi mode channel 0 output compare shadow enable" "0,1"
newline
bitfld.long 0x2C 2. "MCH0COMFEN,Multi mode channel 0 output compare fast enable" "0,1"
bitfld.long 0x2C 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
group.long 0x48++0x7
line.long 0x0 "MCHCTL0_Input,Multi mode channel control register 0 (input mode)"
bitfld.long 0x0 31. "MCH1MS_2,Multi mode channel 1 I/O mode selection" "0,1"
bitfld.long 0x0 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "MCH1CAPFLT,Multi mode channel 1 input capture filter control"
bitfld.long 0x0 10.--11. "MCH1CAPPSC,Multi mode channel 1 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 8.--9. "MCH1MS,Multi mode channel 1 I/O mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "MCH0CAPFLT,Multi mode channel 0 input capture filter control"
newline
bitfld.long 0x0 2.--3. "MCH0CAPPSC,Multi mode channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
line.long 0x4 "MCHCTL1_Output,Multi mode channel control register 1 (output mode)"
bitfld.long 0x4 31. "MCH3MS_2,2th bit of MCH3MS" "0,1"
bitfld.long 0x4 30. "MCH2MS_2,2th bit of MCH2MS" "0,1"
bitfld.long 0x4 24. "MCH3COMCT_3,Multi mode channel 3 compare output control" "0,1"
bitfld.long 0x4 16. "MCH2COMCTL_3,Multi mode channel 2 compare output control" "0,1"
bitfld.long 0x4 15. "MCH3COMCEN,Multi mode channel 3 output compare clear enable" "0,1"
bitfld.long 0x4 12.--14. "MCH3COMCTL,Multi mode channel 3 compare output control" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 11. "MCH3COMSEN,Multi mode channel 3 output compare shadow enable" "0,1"
bitfld.long 0x4 10. "MCH3COMFEN,Multi mode channel 3 output compare fast enable" "0,1"
bitfld.long 0x4 8.--9. "MCH3MS,Multi mode channel 3 I/O mode selection" "0,1,2,3"
bitfld.long 0x4 7. "MCH2COMCEN,Multi mode channel 2 output compare clear enable" "0,1"
bitfld.long 0x4 4.--6. "MCH2COMCTL,Multi mode channel 2 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "MCH2COMSEN,Multi mode channel 2 output compare shadow enable" "0,1"
newline
bitfld.long 0x4 2. "MCH2COMFEN,Multi mode channel 2 output compare fast enable" "0,1"
bitfld.long 0x4 0.--1. "MCH2MS,Multi mode channel 2 I/O mode selection" "0,1,2,3"
group.long 0x4C++0x2B
line.long 0x0 "MCHCTL1_Input,Multi mode channel control register 1(input mode)"
bitfld.long 0x0 31. "MCH3MS_2,2th bit of MCH3MS" "0,1"
bitfld.long 0x0 30. "MCH2MS_2,2th bit of MCH2MS" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "MCH3CAPFLT,Multi mode channel 3 input capture filter control"
bitfld.long 0x0 10.--11. "MCH3CAPPSC,Multi mode channel 3 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 8.--9. "MCH3MS,Multi mode channel 3 I/O mode selection." "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "MCH2CAPFLT,Multi mode channel 2 input capture filter control"
newline
bitfld.long 0x0 2.--3. "MCH2CAPPSC,Multi mode channel 2 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "MCH2MS,Multi mode channel 2 I/O mode selection" "0,1,2,3"
line.long 0x4 "MCHCTL2,Multi mode channel control register 2"
bitfld.long 0x4 6.--7. "MCH3FP,Multi mode channel 3 capture / compare free polarity" "0,1,2,3"
bitfld.long 0x4 4.--5. "MCH2FP,Multi mode channel 2 capture / compare free polarity" "0,1,2,3"
bitfld.long 0x4 2.--3. "MCH1FP,Multi mode channel 1 capture / compare free polarity" "0,1,2,3"
bitfld.long 0x4 0.--1. "MCH0FP,Multi mode channel 0 capture / compare free polarity" "0,1,2,3"
line.long 0x8 "MCH0CV,Multi mode channel 0 capture/compare value register"
hexmask.long.word 0x8 0.--15. 1. "MCH0VAL,Capture / compare value of multi mode channel 0"
line.long 0xC "MCH1CV,Multi mode channel 1 capture/compare value register"
hexmask.long.word 0xC 0.--15. 1. "MCH1VAL,Capture / compare value of multi mode channel 1"
line.long 0x10 "MCH2CV,Multi mode channel 2 capture/compare value register"
hexmask.long.word 0x10 0.--15. 1. "MCH2VAL,Capture / compare value of multi mode channel 2"
line.long 0x14 "MCH3CV,Multi mode channel 3 capture / compare value register"
hexmask.long.word 0x14 0.--15. 1. "MCH3VAL,Capture / compare value of channel 3"
line.long 0x18 "CH0COMV_ADD,Channel 0 additional compare value register"
hexmask.long.word 0x18 0.--15. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
line.long 0x1C "CH1COMV_ADD,Channel 1 additional compare value register"
hexmask.long.word 0x1C 0.--15. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
line.long 0x20 "CH2COMV_ADD,Channel 2 additional compare value register"
hexmask.long.word 0x20 0.--15. 1. "CH2COMVAL_ADD,Additional compare value of channel 2"
line.long 0x24 "CH3COMV_ADD,Channel 3 additional compare value register"
hexmask.long.word 0x24 0.--15. 1. "CH3COMVAL_ADD,Additional compare value of channel 3"
line.long 0x28 "CTL2,Control register 2"
bitfld.long 0x28 31. "CH3CPWMEN,Channel 3 composite PWM mode enable" "0,1"
bitfld.long 0x28 30. "CH2CPWMEN,Channel 2 composite PWM mode enable" "0,1"
bitfld.long 0x28 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
bitfld.long 0x28 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
bitfld.long 0x28 26.--27. "MCH3MSEL,Multi mode channel 3 mode select" "0,1,2,3"
bitfld.long 0x28 24.--25. "MCH2MSEL,Multi mode channel 2 mode select" "0,1,2,3"
newline
bitfld.long 0x28 22.--23. "MCH1MSEL,Multi mode channel 1 mode select" "0,1,2,3"
bitfld.long 0x28 20.--21. "MCH0MSEL,Multi mode channel 0 mode select" "0,1,2,3"
bitfld.long 0x28 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
bitfld.long 0x28 18. "DECJDEN,Quadrature decoder signal jump (the two signals jump at the same time) detection enable" "0,1"
bitfld.long 0x28 14.--15. "CH3OMPSEL,Channel 3 output match pulse select" "0,1,2,3"
bitfld.long 0x28 12.--13. "CH2OMPSEL,Channel 2 output match pulse select" "0,1,2,3"
newline
bitfld.long 0x28 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
bitfld.long 0x28 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
bitfld.long 0x28 7. "BRKENCH3,Break control enable for channel 3" "0,1"
bitfld.long 0x28 6. "BRKENCH2,Break control enable for channel 2" "0,1"
bitfld.long 0x28 5. "BRKENCH1,Break control enable for channel 1" "0,1"
bitfld.long 0x28 4. "BRKENCH0,Break control enable for channel 0" "0,1"
newline
bitfld.long 0x28 3. "DTIENCH3,Dead time inserted enable for channel 3" "0,1"
bitfld.long 0x28 2. "DTIENCH2,Dead time inserted enable for channel 2" "0,1"
bitfld.long 0x28 1. "DTIENCH1,Dead time inserted enable for channel 1" "0,1"
bitfld.long 0x28 0. "DTIENCH0,Dead time inserted enable for channel 0" "0,1"
group.long 0x7C++0x2F
line.long 0x0 "FCCHP0,Free complementary channel protection register 0"
bitfld.long 0x0 31. "FCCHP0EN,Free complementary channel protection register 0 enable" "0,1"
hexmask.long.byte 0x0 16.--23. 1. "DTFCFG,Dead time falling edge configure"
bitfld.long 0x0 11. "ROS,Run mode off-state configure" "0,1"
bitfld.long 0x0 10. "IOS,Idle mode off-state configure" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configure"
line.long 0x4 "FCCHP1,Free complementary channel protection register 1"
bitfld.long 0x4 31. "FCCHP1EN,Free complementary channel protection register 1 enable" "0,1"
hexmask.long.byte 0x4 16.--23. 1. "DTFCFG,Dead time falling edge configure"
bitfld.long 0x4 11. "ROS,Run mode off-state configure" "0,1"
bitfld.long 0x4 10. "IOS,Idle mode off-state configure" "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DTCFG,Dead time configure"
line.long 0x8 "FCCHP2,Free complementary channel protection register 2"
bitfld.long 0x8 31. "FCCHP2EN,Free complementary channel protection register 2 enable" "0,1"
hexmask.long.byte 0x8 16.--23. 1. "DTFCFG,Dead time falling edge configure"
bitfld.long 0x8 11. "ROS,Run mode off-state configure" "0,1"
bitfld.long 0x8 10. "IOS,Idle mode off-state configure" "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DTCFG,Dead time configure"
line.long 0xC "FCCHP3,Free complementary channel protection register 3"
bitfld.long 0xC 31. "FCCHP3EN,Free complementary channel protection register 0 enable" "0,1"
hexmask.long.byte 0xC 16.--23. 1. "DTFCFG,Dead time falling edge configure"
bitfld.long 0xC 11. "ROS,Run mode off-state configure" "0,1"
bitfld.long 0xC 10. "IOS,Idle mode off-state configure" "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DTCFG,Dead time configure"
line.long 0x10 "AFCTL0,Alternate function control register 0"
bitfld.long 0x10 28. "BRK0CMP3P,BREAK0 CMP3 input polarity" "0,1"
bitfld.long 0x10 27. "BRK0CMP2P,BREAK0 CMP2 input polarity" "0,1"
bitfld.long 0x10 26. "BRK0CMP1P,BREAK0 CMP1 input polarity" "0,1"
bitfld.long 0x10 25. "BRK0CMP0P,BREAK0 CMP0 input polarity" "0,1"
bitfld.long 0x10 18. "BRK0IN2P,BREAK0 BRKIN2 alternate function input polarity" "0,1"
bitfld.long 0x10 17. "BRK0IN1P,BREAK0 BRKIN1 alternate function input polarity" "0,1"
newline
bitfld.long 0x10 16. "BRK0IN0P,BREAK0 BRKIN0 alternate function input polarity" "0,1"
bitfld.long 0x10 15. "BRK0CMP6EN,BREAK0 CMP6 enable" "0,1"
bitfld.long 0x10 14. "BRK0CMP5EN,BREAK0 CMP5 enable" "0,1"
bitfld.long 0x10 13. "BRK0CMP4EN,BREAK0 CMP4 enable" "0,1"
bitfld.long 0x10 12. "BRK0CMP3EN,BREAK0 CMP3 enable" "0,1"
bitfld.long 0x10 11. "BRK0CMP2EN,BREAK0 CMP2 enable" "0,1"
newline
bitfld.long 0x10 10. "BRK0CMP1EN,BREAK0 CMP1 enable" "0,1"
bitfld.long 0x10 9. "BRK0CMP0EN,BREAK0 CMP0 enable" "0,1"
bitfld.long 0x10 8. "BRK0HPDFEN,BREAK0 HPDF input enable" "0,1"
bitfld.long 0x10 7. "BRK0CMP7EN,BREAK0 CMP7 enable" "0,1"
bitfld.long 0x10 2. "BRK0IN2EN,BREAK0 BRKIN2 alternate function input enable" "0,1"
bitfld.long 0x10 1. "BRK0IN1EN,BREAK0 BRKIN1 alternate function input enable" "0,1"
newline
bitfld.long 0x10 0. "BRK0IN0EN,BREAK0 BRKIN0 alternate function input enable" "0,1"
line.long 0x14 "AFCTL1,Alternate function control register 1"
bitfld.long 0x14 28. "BRK1CMP3P,BREAK1 CMP3 input polarity" "0,1"
bitfld.long 0x14 27. "BRK1CMP2P,BREAK1 CMP2 input polarity" "0,1"
bitfld.long 0x14 26. "BRK1CMP1P,BREAK1 CMP1 input polarity" "0,1"
bitfld.long 0x14 25. "BRK1CMP0P,BREAK1 CMP0 input polarity" "0,1"
bitfld.long 0x14 19.--21. "OCRINSEL,OCPRE_CLR inputs selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 18. "BRK1IN2P,BREAK1 BRKIN2 alternate function input polarity" "0,1"
newline
bitfld.long 0x14 17. "BRK1IN1P,BREAK1 BRKIN1 alternate function input polarity" "0,1"
bitfld.long 0x14 16. "BRK1IN0P,BREAK1 BRKIN0 alternate function input polarity" "0,1"
bitfld.long 0x14 15. "BRK1CMP6EN,BREAK1 CMP6 enable" "0,1"
bitfld.long 0x14 14. "BRK1CMP5EN,BREAK1 CMP5 enable" "0,1"
bitfld.long 0x14 13. "BRK1CMP4EN,BREAK1 CMP4 enable" "0,1"
bitfld.long 0x14 12. "BRK1CMP3EN,BREAK1 CMP3 enable" "0,1"
newline
bitfld.long 0x14 11. "BRK1CMP2EN,BREAK1 CMP2 enable" "0,1"
bitfld.long 0x14 10. "BRK1CMP1EN,BREAK1 CMP1 enable" "0,1"
bitfld.long 0x14 9. "BRK1CMP0EN,BREAK1 CMP0 enable" "0,1"
bitfld.long 0x14 8. "BRK1HPDFEN,BREAK1 HPDF input enable" "0,1"
bitfld.long 0x14 7. "BRK1CMP7EN,BREAK1 CMP7 enable" "0,1"
bitfld.long 0x14 2. "BRK1IN2EN,BREAK1 BRKIN2 alternate function input enable" "0,1"
newline
bitfld.long 0x14 1. "BRK1IN1EN,BREAK1 BRKIN1 alternate function input enable" "0,1"
bitfld.long 0x14 0. "BRK1IN0EN,BREAK1 BRKIN0 alternate function input enable" "0,1"
line.long 0x18 "WDGPER,Watchdog counter period register"
hexmask.long 0x18 0.--31. 1. "WDGPER,Watchdog counter period value"
line.long 0x1C "CREP1,Counter repetition register 1"
hexmask.long 0x1C 0.--31. 1. "CREP1,Counter repetition value 1"
line.long 0x20 "CCHP1,Complementary channel protection register 1"
bitfld.long 0x20 17. "DTMODEN,Dead time modified on-the-fly enable" "0,1"
bitfld.long 0x20 16. "DTDIFEN,Dead time configure different enable" "0,1"
hexmask.long.byte 0x20 0.--7. 1. "DTFCFG,Dead time falling edge configure"
line.long 0x24 "DECCTL,Decoder control register"
bitfld.long 0x24 24.--26. "OPPSC,Output pulse prescaler" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x24 16.--23. 1. "OPWID,Output pulse width"
bitfld.long 0x24 6.--7. "INDP,Index positioning" "0,1,2,3"
bitfld.long 0x24 5. "FINDRST,First index signal reset the counter" "0,1"
bitfld.long 0x24 1.--2. "INDRSTDIR,Index signal reset counter direction" "0,1,2,3"
bitfld.long 0x24 0. "INDRSTEN,Index signal reset enable" "0,1"
line.long 0x28 "CINITCTL,Counter initial control register"
bitfld.long 0x28 2. "SWSYNCG,Soft synchronization event generation" "0,1"
bitfld.long 0x28 1. "CINITDIR,Counter initial count direction" "0,1"
bitfld.long 0x28 0. "CINITVEN,Counter initial value register enable" "0,1"
line.long 0x2C "CINITV,Counter initial value register"
hexmask.long.word 0x2C 0.--15. 1. "CINITVAL,Counter initial value"
group.long 0xE0++0x7
line.long 0x0 "DMACFG,DMA configuration register"
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
line.long 0x4 "DMATB,DMA transfer buffer register"
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
group.long 0xFC++0x3
line.long 0x0 "CFG,Configuration register"
bitfld.long 0x0 3. "CCUSEL,Commutation control shadow register update select" "0,1"
bitfld.long 0x0 2. "CREPSEL,The counter repetition register select" "0,1"
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection bit" "0,1"
bitfld.long 0x0 0. "OUTSEL,The output value selection bit" "0,1"
tree.end
tree "TIMER1 (General-L0 Timer)"
base ad:0x40000000
group.long 0x0++0x13
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 12. "ADMEN,Adjustment mode enable" "0,1"
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
bitfld.long 0x0 4. "DIR,Direction" "0,1"
newline
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x0 2. "UPS,Update source" "0,1"
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 25. "MMC0_3,Master mode control 0 (bit 3)" "0,1"
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
line.long 0x8 "SMCFG,Slave mode configuration register"
bitfld.long 0x8 26. "PRMRPSEL,Pause + restart mode reset polarity selection" "0,1"
bitfld.long 0x8 25. "DECMODS,Decoder mode update source" "0,1"
bitfld.long 0x8 24. "DECMODEN,Decoder mode modified on-the-fly enable" "0,1"
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
bitfld.long 0x8 14. "SMC1,Part of slave mode controller is used to enable external clock mode 1" "0,1"
bitfld.long 0x8 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
newline
hexmask.long.byte 0x8 8.--11. 1. "ETFC,External trigger filter control"
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
bitfld.long 0x8 3. "OCRC,OxCPRE clear source selection" "0,1"
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
bitfld.long 0xC 31. "CH3COMADDIE,Channel 3 additional compare interrupt enable" "0,1"
bitfld.long 0xC 30. "CH2COMADDIE,Channel 2 additional compare interrupt enable" "0,1"
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
bitfld.long 0xC 19. "INDERRIE,Index error interrupt enable" "0,1"
bitfld.long 0xC 18. "DIRTRANIE,Direction transform interrupt enable" "0,1"
newline
bitfld.long 0xC 17. "DECDISIE,Quadrature decoder signal disconnection interrupt enable" "0,1"
bitfld.long 0xC 16. "DECJIE,Quadrature decoder signal jump (the two signals jump at the same time) interrupt enable" "0,1"
bitfld.long 0xC 15. "INDIE,Index interrupt enable" "0,1"
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
bitfld.long 0xC 12. "CH3DEN,Channel 3 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 11. "CH2DEN,Channel 2 capture / compare DMA request enable" "0,1"
newline
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
bitfld.long 0xC 4. "CH3IE,Channel 3 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 3. "CH2IE,Channel 2 capture / compare interrupt enable" "0,1"
newline
bitfld.long 0xC 2. "CH1IE,Channel 1 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 1. "CH0IE,Channel 0 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
line.long 0x10 "INTF,Interrupt flag register"
bitfld.long 0x10 31. "CH3COMADDIF,Channel 3 additional compare interrupt flag" "0,1"
bitfld.long 0x10 30. "CH2COMADDIF,Channel 2 additional compare interrupt flag" "0,1"
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
bitfld.long 0x10 19. "INDERRIF,Index error interrupt flag" "0,1"
bitfld.long 0x10 18. "DIRTRANIF,Direction transform interrupt flag" "0,1"
newline
bitfld.long 0x10 17. "DECDISIF,Quadrature decoder signal disconnection interrupt flag" "0,1"
bitfld.long 0x10 16. "DECJIF,Quadrature decoder signal jump (the two signals jump at the same time) interrupt flag" "0,1"
bitfld.long 0x10 15. "INDIF,Index interrupt flag" "0,1"
bitfld.long 0x10 12. "CH3OF,Channel 3 over capture flag" "0,1"
bitfld.long 0x10 11. "CH2OF,Channel 2 over capture flag" "0,1"
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
newline
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
bitfld.long 0x10 4. "CH3IF,Channel 3 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 3. "CH2IF,Channel 2 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 2. "CH1IF,Channel 1 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 1. "CH0IF,Channel 0 capture / compare interrupt flag" "0,1"
newline
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x3
line.long 0x0 "SWEVG,Software event generation register"
bitfld.long 0x0 31. "CH3COMADDG,Channel 3 additional compare event generation" "0,1"
bitfld.long 0x0 30. "CH2COMADDG,Channel 2 additional compare event generation" "0,1"
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
bitfld.long 0x0 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
newline
bitfld.long 0x0 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
group.long 0x18++0x3
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
bitfld.long 0x0 27. "CH1ADDUPS,Channel 1 additional update source" "0,1"
bitfld.long 0x0 26. "CH0ADDUPS,Channel 0 additional update source" "0,1"
newline
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
bitfld.long 0x0 10. "CH1COMFEN,Channel 1 output compare fast enable" "0,1"
newline
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
bitfld.long 0x0 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x7
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input mode)"
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
bitfld.long 0x0 27. "CH1ADDUPS,Channel 1 additional update source" "0,1"
bitfld.long 0x0 26. "CH0ADDUPS,Channel 0 additional update source" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
line.long 0x4 "CHCTL1_Output,Channel control register 1 (output mode)"
bitfld.long 0x4 31. "CH3MS_2,2th bit of CH3MS" "0,1"
bitfld.long 0x4 30. "CH2MS_2,2th bit of CH2MS" "0,1"
bitfld.long 0x4 29. "CH3COMADDSEN,Channel 3 additional compare output shadow enable" "0,1"
bitfld.long 0x4 28. "CH2COMADDSEN,Channel 2 additional compare output shadow enable" "0,1"
bitfld.long 0x4 27. "CH3ADDUPS,Channel 3 additional update source" "0,1"
bitfld.long 0x4 26. "CH2ADDUPS,Channel 2 additional update source" "0,1"
newline
bitfld.long 0x4 24. "CH3COMCTL_3,BIT 3 of channel 3 compare output control" "0,1"
bitfld.long 0x4 23. "CH2COMCTL_3,BIT 3 of channel 2 compare output control" "0,1"
bitfld.long 0x4 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
bitfld.long 0x4 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
bitfld.long 0x4 10. "CH3COMFEN,Channel 3 output compare fast enable" "0,1"
newline
bitfld.long 0x4 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
bitfld.long 0x4 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
bitfld.long 0x4 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
bitfld.long 0x4 2. "CH2COMFEN,Channel 2 output compare fast enable" "0,1"
bitfld.long 0x4 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
group.long 0x1C++0x13
line.long 0x0 "CHCTL1_Input,Channel control register 1 (input mode)"
bitfld.long 0x0 31. "CH3MS_2,2th bit of CH3MS" "0,1"
bitfld.long 0x0 30. "CH2MS_2,2th bit of CH2MS" "0,1"
bitfld.long 0x0 27. "CH3ADDUPS,Channel 3 additional update source" "0,1"
bitfld.long 0x0 26. "CH2ADDUPS,Channel 2 additional update source" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "CH3CAPFLT,Channel 3 input capture filter control"
bitfld.long 0x0 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "CH2CAPFLT,Channel 2 input capture filter control"
bitfld.long 0x0 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
line.long 0x4 "CHCTL2,Channel control register 2"
bitfld.long 0x4 15. "CH3NP,Channel 3 complementary capture / compare polarity" "0,1"
bitfld.long 0x4 13. "CH3P,Channel 3 capture / compare function polarity" "0,1"
bitfld.long 0x4 12. "CH3EN,Channel 3 capture / compare function enable" "0,1"
bitfld.long 0x4 11. "CH2NP,Channel 2 complementary capture / compare polarity" "0,1"
bitfld.long 0x4 9. "CH2P,Channel 2 capture / compare function polarity" "0,1"
bitfld.long 0x4 8. "CH2EN,Channel 2 capture / compare function enable" "0,1"
newline
bitfld.long 0x4 7. "CH1NP,Channel 1 complementary capture / compare polarity" "0,1"
bitfld.long 0x4 5. "CH1P,Channel 1 capture / compare function polarity" "0,1"
bitfld.long 0x4 4. "CH1EN,Channel 1 capture / compare function enable" "0,1"
bitfld.long 0x4 3. "CH0NP,Channel 0 complementary output polarity" "0,1"
bitfld.long 0x4 1. "CH0P,Channel 0 capture / compare function polarity" "0,1"
bitfld.long 0x4 0. "CH0EN,Channel 0 capture / compare function enable" "0,1"
line.long 0x8 "CNT,Counter register"
bitfld.long 0x8 31. "UPIFBU,UPIF bit backup" "0,1"
hexmask.long 0x8 0.--30. 1. "CNT,This bit-field indicates the current counter value"
line.long 0xC "PSC,Prescaler register"
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value of the counter clock"
line.long 0x10 "CAR,Counter auto reload register"
hexmask.long 0x10 0.--31. 1. "CARL,Counter auto reload value"
group.long 0x34++0xF
line.long 0x0 "CH0CV,Channel 0 capture/compare value register"
hexmask.long 0x0 0.--31. 1. "CH0VAL,Capture / compare value of channel 0"
line.long 0x4 "CH1CV,Channel 1 capture/compare value register"
hexmask.long 0x4 0.--31. 1. "CH1VAL,Capture / compare value of channel 1"
line.long 0x8 "CH2CV,Channel 2 capture/compare value register"
hexmask.long 0x8 0.--31. 1. "CH2VAL,Capture / compare value of channel 2"
line.long 0xC "CH3CV,Channel 3 capture/compare value register"
hexmask.long 0xC 0.--31. 1. "CH3VAL,Capture / compare value of channel 3"
group.long 0x64++0x13
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
hexmask.long 0x0 0.--31. 1. "CH0COMVAL_ADD,Additional compare value of channel 0 (bit 16 to 31)"
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
hexmask.long 0x4 0.--31. 1. "CH1COMVAL_ADD,Additional compare value of channel 1 (bit 16 to 31)"
line.long 0x8 "CH2COMV_ADD,Channel 2 additional compare value register"
hexmask.long 0x8 0.--31. 1. "CH2COMVAL_ADD,Additional compare value of channel 2 (bit 16 to 31)"
line.long 0xC "CH3COMV_ADD,Channel 3 additional compare value register"
hexmask.long 0xC 0.--31. 1. "CH3COMVAL_ADD,Additional compare value of channel 3 (bit 16 to 31)"
line.long 0x10 "CTL2,Control register 2"
bitfld.long 0x10 31. "CH3CPWMEN,Channel 3 composite PWM mode enable" "0,1"
bitfld.long 0x10 30. "CH2CPWMEN,Channel 2 composite PWM mode enable" "0,1"
bitfld.long 0x10 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
bitfld.long 0x10 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
bitfld.long 0x10 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
bitfld.long 0x10 18. "DECJDEN,Quadrature decoder signal jump (the two signals jump at the same time) detection enable" "0,1"
newline
bitfld.long 0x10 14.--15. "CH3OMPSEL,Channel 3 output match pulse select" "0,1,2,3"
bitfld.long 0x10 12.--13. "CH2OMPSEL,Channel 2 output match pulse select" "0,1,2,3"
bitfld.long 0x10 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
bitfld.long 0x10 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
group.long 0x90++0x7
line.long 0x0 "AFCTL1,TIMER alternate function control register 1"
bitfld.long 0x0 19.--21. "OCRINSEL,OCPRE_CLR inputs selection" "0,1,2,3,4,5,6,7"
line.long 0x4 "WDGPER,Watchdog counter period register"
hexmask.long 0x4 0.--31. 1. "WDGPER,Watchdog counter period value"
group.long 0xA0++0x3
line.long 0x0 "TIMER_DECCTL,Decoder control register"
bitfld.long 0x0 24.--26. "OPPSC,Output pulse prescaler" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 16.--23. 1. "OPWID,Output pulse width"
bitfld.long 0x0 6.--7. "INDP,Index positioning" "0,1,2,3"
bitfld.long 0x0 5. "FINDRST,First index signal reset the counter" "0,1"
bitfld.long 0x0 1.--2. "INDRSTDIR,Index signal reset counter direction" "0,1,2,3"
bitfld.long 0x0 0. "INDRSTEN,Index signal reset enable" "0,1"
group.long 0xE0++0x7
line.long 0x0 "TIMERx_DMACFG,DMA configuration register"
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
line.long 0x4 "DMATB,DMA transfer buffer register"
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
group.long 0xFC++0x3
line.long 0x0 "CFG,Configuration register"
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection bit" "0,1"
tree.end
tree "TIMER2 (General-L0 Timer)"
base ad:0x40000400
group.long 0x0++0x13
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 12. "ADMEN,Adjustment mode enable" "0,1"
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
bitfld.long 0x0 4. "DIR,Direction" "0,1"
newline
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x0 2. "UPS,Update source" "0,1"
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 25. "MMC0_3,Master mode control 0 (bit 3)" "0,1"
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
line.long 0x8 "SMCFG,Slave mode configuration register"
bitfld.long 0x8 26. "PRMRPSEL,Pause + restart mode reset polarity selection" "0,1"
bitfld.long 0x8 25. "DECMODS,Decoder mode update source" "0,1"
bitfld.long 0x8 24. "DECMODEN,Decoder mode modified on-the-fly enable" "0,1"
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
bitfld.long 0x8 14. "SMC1,Part of slave mode controller is used to enable external clock mode 1" "0,1"
bitfld.long 0x8 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
newline
hexmask.long.byte 0x8 8.--11. 1. "ETFC,External trigger filter control"
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
bitfld.long 0x8 3. "OCRC,OxCPRE clear source selection" "0,1"
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
bitfld.long 0xC 31. "CH3COMADDIE,Channel 3 additional compare interrupt enable" "0,1"
bitfld.long 0xC 30. "CH2COMADDIE,Channel 2 additional compare interrupt enable" "0,1"
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
bitfld.long 0xC 19. "INDERRIE,Index error interrupt enable" "0,1"
bitfld.long 0xC 18. "DIRTRANIE,Direction transform interrupt enable" "0,1"
newline
bitfld.long 0xC 17. "DECDISIE,Quadrature decoder signal disconnection interrupt enable" "0,1"
bitfld.long 0xC 16. "DECJIE,Quadrature decoder signal jump (the two signals jump at the same time) interrupt enable" "0,1"
bitfld.long 0xC 15. "INDIE,Index interrupt enable" "0,1"
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
bitfld.long 0xC 12. "CH3DEN,Channel 3 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 11. "CH2DEN,Channel 2 capture / compare DMA request enable" "0,1"
newline
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
bitfld.long 0xC 4. "CH3IE,Channel 3 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 3. "CH2IE,Channel 2 capture / compare interrupt enable" "0,1"
newline
bitfld.long 0xC 2. "CH1IE,Channel 1 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 1. "CH0IE,Channel 0 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
line.long 0x10 "INTF,Interrupt flag register"
bitfld.long 0x10 31. "CH3COMADDIF,Channel 3 additional compare interrupt flag" "0,1"
bitfld.long 0x10 30. "CH2COMADDIF,Channel 2 additional compare interrupt flag" "0,1"
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
bitfld.long 0x10 19. "INDERRIF,Index error interrupt flag" "0,1"
bitfld.long 0x10 18. "DIRTRANIF,Direction transform interrupt flag" "0,1"
newline
bitfld.long 0x10 17. "DECDISIF,Quadrature decoder signal disconnection interrupt flag" "0,1"
bitfld.long 0x10 16. "DECJIF,Quadrature decoder signal jump (the two signals jump at the same time) interrupt flag" "0,1"
bitfld.long 0x10 15. "INDIF,Index interrupt flag" "0,1"
bitfld.long 0x10 12. "CH3OF,Channel 3 over capture flag" "0,1"
bitfld.long 0x10 11. "CH2OF,Channel 2 over capture flag" "0,1"
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
newline
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
bitfld.long 0x10 4. "CH3IF,Channel 3 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 3. "CH2IF,Channel 2 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 2. "CH1IF,Channel 1 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 1. "CH0IF,Channel 0 capture / compare interrupt flag" "0,1"
newline
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x3
line.long 0x0 "SWEVG,Software event generation register"
bitfld.long 0x0 31. "CH3COMADDG,Channel 3 additional compare event generation" "0,1"
bitfld.long 0x0 30. "CH2COMADDG,Channel 2 additional compare event generation" "0,1"
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
bitfld.long 0x0 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
newline
bitfld.long 0x0 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
group.long 0x18++0x3
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
bitfld.long 0x0 27. "CH1ADDUPS,Channel 1 additional update source" "0,1"
bitfld.long 0x0 26. "CH0ADDUPS,Channel 0 additional update source" "0,1"
newline
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
bitfld.long 0x0 10. "CH1COMFEN,Channel 1 output compare fast enable" "0,1"
newline
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
bitfld.long 0x0 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x7
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input mode)"
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
bitfld.long 0x0 27. "CH1ADDUPS,Channel 1 additional update source" "0,1"
bitfld.long 0x0 26. "CH0ADDUPS,Channel 0 additional update source" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
line.long 0x4 "CHCTL1_Output,Channel control register 1 (output mode)"
bitfld.long 0x4 31. "CH3MS_2,2th bit of CH3MS" "0,1"
bitfld.long 0x4 30. "CH2MS_2,2th bit of CH2MS" "0,1"
bitfld.long 0x4 29. "CH3COMADDSEN,Channel 3 additional compare output shadow enable" "0,1"
bitfld.long 0x4 28. "CH2COMADDSEN,Channel 2 additional compare output shadow enable" "0,1"
bitfld.long 0x4 27. "CH3ADDUPS,Channel 3 additional update source" "0,1"
bitfld.long 0x4 26. "CH2ADDUPS,Channel 2 additional update source" "0,1"
newline
bitfld.long 0x4 24. "CH3COMCTL_3,BIT 3 of channel 3 compare output control" "0,1"
bitfld.long 0x4 23. "CH2COMCTL_3,BIT 3 of channel 2 compare output control" "0,1"
bitfld.long 0x4 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
bitfld.long 0x4 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
bitfld.long 0x4 10. "CH3COMFEN,Channel 3 output compare fast enable" "0,1"
newline
bitfld.long 0x4 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
bitfld.long 0x4 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
bitfld.long 0x4 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
bitfld.long 0x4 2. "CH2COMFEN,Channel 2 output compare fast enable" "0,1"
bitfld.long 0x4 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
group.long 0x1C++0x13
line.long 0x0 "CHCTL1_Input,Channel control register 1 (input mode)"
bitfld.long 0x0 31. "CH3MS_2,2th bit of CH3MS" "0,1"
bitfld.long 0x0 30. "CH2MS_2,2th bit of CH2MS" "0,1"
bitfld.long 0x0 27. "CH3ADDUPS,Channel 3 additional update source" "0,1"
bitfld.long 0x0 26. "CH2ADDUPS,Channel 2 additional update source" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "CH3CAPFLT,Channel 3 input capture filter control"
bitfld.long 0x0 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "CH2CAPFLT,Channel 2 input capture filter control"
bitfld.long 0x0 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
line.long 0x4 "CHCTL2,Channel control register 2"
bitfld.long 0x4 15. "CH3NP,Channel 3 complementary capture / compare polarity" "0,1"
bitfld.long 0x4 13. "CH3P,Channel 3 capture / compare function polarity" "0,1"
bitfld.long 0x4 12. "CH3EN,Channel 3 capture / compare function enable" "0,1"
bitfld.long 0x4 11. "CH2NP,Channel 2 complementary capture / compare polarity" "0,1"
bitfld.long 0x4 9. "CH2P,Channel 2 capture / compare function polarity" "0,1"
bitfld.long 0x4 8. "CH2EN,Channel 2 capture / compare function enable" "0,1"
newline
bitfld.long 0x4 7. "CH1NP,Channel 1 complementary capture / compare polarity" "0,1"
bitfld.long 0x4 5. "CH1P,Channel 1 capture / compare function polarity" "0,1"
bitfld.long 0x4 4. "CH1EN,Channel 1 capture / compare function enable" "0,1"
bitfld.long 0x4 3. "CH0NP,Channel 0 complementary output polarity" "0,1"
bitfld.long 0x4 1. "CH0P,Channel 0 capture / compare function polarity" "0,1"
bitfld.long 0x4 0. "CH0EN,Channel 0 capture / compare function enable" "0,1"
line.long 0x8 "CNT,Counter register"
rbitfld.long 0x8 31. "UPIFBU,UPIF bit backup" "0,1"
hexmask.long.word 0x8 0.--15. 1. "CNT,This bit-field indicates the current counter value"
line.long 0xC "PSC,Prescaler register"
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value of the counter clock"
line.long 0x10 "CAR,Counter auto reload register"
hexmask.long.byte 0x10 28.--31. 1. "CARL16_19,Counter auto reload value (bit 16 to 19)"
hexmask.long.word 0x10 0.--15. 1. "CARL,Counter auto reload value (bit 0 to 15)"
group.long 0x34++0xF
line.long 0x0 "CH0CV,Channel 0 capture/compare value register"
hexmask.long.byte 0x0 28.--31. 1. "CH0VAL16_19,Capture / compare value of channel 0 (bit 16 to 19)"
hexmask.long.word 0x0 0.--15. 1. "CH0VAL,Capture / compare value of channel 0 (bit 0 to 15)"
line.long 0x4 "CH1CV,Channel 1 capture/compare value register"
hexmask.long.byte 0x4 28.--31. 1. "CH1VAL16_19,Capture / compare value of channel 1 (bit 16 to 19)"
hexmask.long.word 0x4 0.--15. 1. "CH1VAL,Capture / compare value of channel 1 (bit 0 to 15)"
line.long 0x8 "CH2CV,Channel 2 capture/compare value register"
hexmask.long.byte 0x8 28.--31. 1. "CH2VAL16_19,Capture / compare value of channel 2 (bit 16 to 19)"
hexmask.long.word 0x8 0.--15. 1. "CH2VAL,Capture / compare value of channel 2 (bit 0 to 15)"
line.long 0xC "CH3CV,Channel 3 capture/compare value register"
hexmask.long.byte 0xC 28.--31. 1. "CH3VAL16_19,Capture / compare value of channel 3 (bit 16 to 19)"
hexmask.long.word 0xC 0.--15. 1. "CH3VAL,Capture / compare value of channel 3 (bit 0 to 15)"
group.long 0x64++0x13
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
hexmask.long 0x0 0.--31. 1. "CH0COMVAL_ADD,Additional compare value of channel 0 (bit 16 to 31)"
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
hexmask.long 0x4 0.--31. 1. "CH1COMVAL_ADD,Additional compare value of channel 1 (bit 16 to 31)"
line.long 0x8 "CH2COMV_ADD,Channel 2 additional compare value register"
hexmask.long 0x8 0.--31. 1. "CH2COMVAL_ADD,Additional compare value of channel 2 (bit 16 to 31)"
line.long 0xC "CH3COMV_ADD,Channel 3 additional compare value register"
hexmask.long 0xC 0.--31. 1. "CH3COMVAL_ADD,Additional compare value of channel 3 (bit 16 to 31)"
line.long 0x10 "CTL2,Control register 2"
bitfld.long 0x10 31. "CH3CPWMEN,Channel 3 composite PWM mode enable" "0,1"
bitfld.long 0x10 30. "CH2CPWMEN,Channel 2 composite PWM mode enable" "0,1"
bitfld.long 0x10 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
bitfld.long 0x10 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
bitfld.long 0x10 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
bitfld.long 0x10 18. "DECJDEN,Quadrature decoder signal jump (the two signals jump at the same time) detection enable" "0,1"
newline
bitfld.long 0x10 14.--15. "CH3OMPSEL,Channel 3 output match pulse select" "0,1,2,3"
bitfld.long 0x10 12.--13. "CH2OMPSEL,Channel 2 output match pulse select" "0,1,2,3"
bitfld.long 0x10 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
bitfld.long 0x10 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
group.long 0x90++0x7
line.long 0x0 "AFCTL1,TIMER alternate function control register 1"
bitfld.long 0x0 19.--21. "OCRINSEL,OCPRE_CLR inputs selection" "0,1,2,3,4,5,6,7"
line.long 0x4 "WDGPER,Watchdog counter period register"
hexmask.long 0x4 0.--31. 1. "WDGPER,Watchdog counter period value"
group.long 0xA0++0x3
line.long 0x0 "TIMERx_DECCTL,Decoder control register"
bitfld.long 0x0 24.--26. "OPPSC,Output pulse prescaler" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 16.--23. 1. "OPWID,Output pulse width"
bitfld.long 0x0 6.--7. "INDP,Index positioning" "0,1,2,3"
bitfld.long 0x0 5. "FINDRST,First index signal reset the counter" "0,1"
bitfld.long 0x0 1.--2. "INDRSTDIR,Index signal reset counter direction" "0,1,2,3"
bitfld.long 0x0 0. "INDRSTEN,Index signal reset enable" "0,1"
group.long 0xE0++0x7
line.long 0x0 "TIMERx_DMACFG,DMA configuration register"
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
line.long 0x4 "DMATB,DMA transfer buffer register"
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
group.long 0xFC++0x3
line.long 0x0 "CFG,Configuration register"
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection bit" "0,1"
tree.end
tree "TIMER3 (General-L0 Timer)"
base ad:0x40000800
group.long 0x0++0x13
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 12. "ADMEN,Adjustment mode enable" "0,1"
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
bitfld.long 0x0 4. "DIR,Direction" "0,1"
newline
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x0 2. "UPS,Update source" "0,1"
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 25. "MMC0_3,Master mode control 0 (bit 3)" "0,1"
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
line.long 0x8 "SMCFG,Slave mode configuration register"
bitfld.long 0x8 26. "PRMRPSEL,Pause + restart mode reset polarity selection" "0,1"
bitfld.long 0x8 25. "DECMODS,Decoder mode update source" "0,1"
bitfld.long 0x8 24. "DECMODEN,Decoder mode modified on-the-fly enable" "0,1"
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
bitfld.long 0x8 14. "SMC1,Part of slave mode controller is used to enable external clock mode 1" "0,1"
bitfld.long 0x8 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
newline
hexmask.long.byte 0x8 8.--11. 1. "ETFC,External trigger filter control"
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
bitfld.long 0x8 3. "OCRC,OxCPRE clear source selection" "0,1"
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
bitfld.long 0xC 31. "CH3COMADDIE,Channel 3 additional compare interrupt enable" "0,1"
bitfld.long 0xC 30. "CH2COMADDIE,Channel 2 additional compare interrupt enable" "0,1"
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
bitfld.long 0xC 19. "INDERRIE,Index error interrupt enable" "0,1"
bitfld.long 0xC 18. "DIRTRANIE,Direction transform interrupt enable" "0,1"
newline
bitfld.long 0xC 17. "DECDISIE,Quadrature decoder signal disconnection interrupt enable" "0,1"
bitfld.long 0xC 16. "DECJIE,Quadrature decoder signal jump (the two signals jump at the same time) interrupt enable" "0,1"
bitfld.long 0xC 15. "INDIE,Index interrupt enable" "0,1"
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
bitfld.long 0xC 12. "CH3DEN,Channel 3 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 11. "CH2DEN,Channel 2 capture / compare DMA request enable" "0,1"
newline
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
bitfld.long 0xC 4. "CH3IE,Channel 3 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 3. "CH2IE,Channel 2 capture / compare interrupt enable" "0,1"
newline
bitfld.long 0xC 2. "CH1IE,Channel 1 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 1. "CH0IE,Channel 0 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
line.long 0x10 "INTF,Interrupt flag register"
bitfld.long 0x10 31. "CH3COMADDIF,Channel 3 additional compare interrupt flag" "0,1"
bitfld.long 0x10 30. "CH2COMADDIF,Channel 2 additional compare interrupt flag" "0,1"
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
bitfld.long 0x10 19. "INDERRIF,Index error interrupt flag" "0,1"
bitfld.long 0x10 18. "DIRTRANIF,Direction transform interrupt flag" "0,1"
newline
bitfld.long 0x10 17. "DECDISIF,Quadrature decoder signal disconnection interrupt flag" "0,1"
bitfld.long 0x10 16. "DECJIF,Quadrature decoder signal jump (the two signals jump at the same time) interrupt flag" "0,1"
bitfld.long 0x10 15. "INDIF,Index interrupt flag" "0,1"
bitfld.long 0x10 12. "CH3OF,Channel 3 over capture flag" "0,1"
bitfld.long 0x10 11. "CH2OF,Channel 2 over capture flag" "0,1"
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
newline
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
bitfld.long 0x10 4. "CH3IF,Channel 3 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 3. "CH2IF,Channel 2 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 2. "CH1IF,Channel 1 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 1. "CH0IF,Channel 0 capture / compare interrupt flag" "0,1"
newline
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x3
line.long 0x0 "SWEVG,Software event generation register"
bitfld.long 0x0 31. "CH3COMADDG,Channel 3 additional compare event generation" "0,1"
bitfld.long 0x0 30. "CH2COMADDG,Channel 2 additional compare event generation" "0,1"
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
bitfld.long 0x0 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
newline
bitfld.long 0x0 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
group.long 0x18++0x3
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
bitfld.long 0x0 27. "CH1ADDUPS,Channel 1 additional update source" "0,1"
bitfld.long 0x0 26. "CH0ADDUPS,Channel 0 additional update source" "0,1"
newline
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
bitfld.long 0x0 10. "CH1COMFEN,Channel 1 output compare fast enable" "0,1"
newline
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
bitfld.long 0x0 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x7
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input mode)"
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
bitfld.long 0x0 27. "CH1ADDUPS,Channel 1 additional update source" "0,1"
bitfld.long 0x0 26. "CH0ADDUPS,Channel 0 additional update source" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
line.long 0x4 "CHCTL1_Output,Channel control register 1 (output mode)"
bitfld.long 0x4 31. "CH3MS_2,2th bit of CH3MS" "0,1"
bitfld.long 0x4 30. "CH2MS_2,2th bit of CH2MS" "0,1"
bitfld.long 0x4 29. "CH3COMADDSEN,Channel 3 additional compare output shadow enable" "0,1"
bitfld.long 0x4 28. "CH2COMADDSEN,Channel 2 additional compare output shadow enable" "0,1"
bitfld.long 0x4 27. "CH3ADDUPS,Channel 3 additional update source" "0,1"
bitfld.long 0x4 26. "CH2ADDUPS,Channel 2 additional update source" "0,1"
newline
bitfld.long 0x4 24. "CH3COMCTL_3,BIT 3 of channel 3 compare output control" "0,1"
bitfld.long 0x4 23. "CH2COMCTL_3,BIT 3 of channel 2 compare output control" "0,1"
bitfld.long 0x4 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
bitfld.long 0x4 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
bitfld.long 0x4 10. "CH3COMFEN,Channel 3 output compare fast enable" "0,1"
newline
bitfld.long 0x4 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
bitfld.long 0x4 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
bitfld.long 0x4 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
bitfld.long 0x4 2. "CH2COMFEN,Channel 2 output compare fast enable" "0,1"
bitfld.long 0x4 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
group.long 0x1C++0x13
line.long 0x0 "CHCTL1_Input,Channel control register 1 (input mode)"
bitfld.long 0x0 31. "CH3MS_2,2th bit of CH3MS" "0,1"
bitfld.long 0x0 30. "CH2MS_2,2th bit of CH2MS" "0,1"
bitfld.long 0x0 27. "CH3ADDUPS,Channel 3 additional update source" "0,1"
bitfld.long 0x0 26. "CH2ADDUPS,Channel 2 additional update source" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "CH3CAPFLT,Channel 3 input capture filter control"
bitfld.long 0x0 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "CH2CAPFLT,Channel 2 input capture filter control"
bitfld.long 0x0 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
line.long 0x4 "CHCTL2,Channel control register 2"
bitfld.long 0x4 15. "CH3NP,Channel 3 complementary capture / compare polarity" "0,1"
bitfld.long 0x4 13. "CH3P,Channel 3 capture / compare function polarity" "0,1"
bitfld.long 0x4 12. "CH3EN,Channel 3 capture / compare function enable" "0,1"
bitfld.long 0x4 11. "CH2NP,Channel 2 complementary capture / compare polarity" "0,1"
bitfld.long 0x4 9. "CH2P,Channel 2 capture / compare function polarity" "0,1"
bitfld.long 0x4 8. "CH2EN,Channel 2 capture / compare function enable" "0,1"
newline
bitfld.long 0x4 7. "CH1NP,Channel 1 complementary capture / compare polarity" "0,1"
bitfld.long 0x4 5. "CH1P,Channel 1 capture / compare function polarity" "0,1"
bitfld.long 0x4 4. "CH1EN,Channel 1 capture / compare function enable" "0,1"
bitfld.long 0x4 3. "CH0NP,Channel 0 complementary output polarity" "0,1"
bitfld.long 0x4 1. "CH0P,Channel 0 capture / compare function polarity" "0,1"
bitfld.long 0x4 0. "CH0EN,Channel 0 capture / compare function enable" "0,1"
line.long 0x8 "CNT,Counter register"
rbitfld.long 0x8 31. "UPIFBU,UPIF bit backup" "0,1"
hexmask.long.word 0x8 0.--15. 1. "CNT,This bit-field indicates the current counter value"
line.long 0xC "PSC,Prescaler register"
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value of the counter clock"
line.long 0x10 "CAR,Counter auto reload register"
hexmask.long.byte 0x10 28.--31. 1. "CARL16_19,Counter auto reload value (bit 16 to 19)"
hexmask.long.word 0x10 0.--15. 1. "CARL,Counter auto reload value (bit 0 to 15)"
group.long 0x34++0xF
line.long 0x0 "CH0CV,Channel 0 capture/compare value register"
hexmask.long.byte 0x0 28.--31. 1. "CH0VAL16_19,Capture / compare value of channel 0 (bit 16 to 19)"
hexmask.long.word 0x0 0.--15. 1. "CH0VAL,Capture / compare value of channel 0 (bit 0 to 15)"
line.long 0x4 "CH1CV,Channel 1 capture/compare value register"
hexmask.long.byte 0x4 28.--31. 1. "CH1VAL16_19,Capture / compare value of channel 1 (bit 16 to 19)"
hexmask.long.word 0x4 0.--15. 1. "CH1VAL,Capture / compare value of channel 1 (bit 0 to 15)"
line.long 0x8 "CH2CV,Channel 2 capture/compare value register"
hexmask.long.byte 0x8 28.--31. 1. "CH2VAL16_19,Capture / compare value of channel 2 (bit 16 to 19)"
hexmask.long.word 0x8 0.--15. 1. "CH2VAL,Capture / compare value of channel 2 (bit 0 to 15)"
line.long 0xC "CH3CV,Channel 3 capture/compare value register"
hexmask.long.byte 0xC 28.--31. 1. "CH3VAL16_19,Capture / compare value of channel 3 (bit 16 to 19)"
hexmask.long.word 0xC 0.--15. 1. "CH3VAL,Capture / compare value of channel 3 (bit 0 to 15)"
group.long 0x64++0x13
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
hexmask.long 0x0 0.--31. 1. "CH0COMVAL_ADD,Additional compare value of channel 0 (bit 16 to 31)"
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
hexmask.long 0x4 0.--31. 1. "CH1COMVAL_ADD,Additional compare value of channel 1 (bit 16 to 31)"
line.long 0x8 "CH2COMV_ADD,Channel 2 additional compare value register"
hexmask.long 0x8 0.--31. 1. "CH2COMVAL_ADD,Additional compare value of channel 2 (bit 16 to 31)"
line.long 0xC "CH3COMV_ADD,Channel 3 additional compare value register"
hexmask.long 0xC 0.--31. 1. "CH3COMVAL_ADD,Additional compare value of channel 3 (bit 16 to 31)"
line.long 0x10 "CTL2,Control register 2"
bitfld.long 0x10 31. "CH3CPWMEN,Channel 3 composite PWM mode enable" "0,1"
bitfld.long 0x10 30. "CH2CPWMEN,Channel 2 composite PWM mode enable" "0,1"
bitfld.long 0x10 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
bitfld.long 0x10 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
bitfld.long 0x10 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
bitfld.long 0x10 18. "DECJDEN,Quadrature decoder signal jump (the two signals jump at the same time) detection enable" "0,1"
newline
bitfld.long 0x10 14.--15. "CH3OMPSEL,Channel 3 output match pulse select" "0,1,2,3"
bitfld.long 0x10 12.--13. "CH2OMPSEL,Channel 2 output match pulse select" "0,1,2,3"
bitfld.long 0x10 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
bitfld.long 0x10 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
group.long 0x90++0x7
line.long 0x0 "AFCTL1,TIMER alternate function control register 1"
bitfld.long 0x0 19.--21. "OCRINSEL,OCPRE_CLR inputs selection" "0,1,2,3,4,5,6,7"
line.long 0x4 "WDGPER,Watchdog counter period register"
hexmask.long 0x4 0.--31. 1. "WDGPER,Watchdog counter period value"
group.long 0xA0++0x3
line.long 0x0 "TIMERx_DECCTL,Decoder control register"
bitfld.long 0x0 24.--26. "OPPSC,Output pulse prescaler" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 16.--23. 1. "OPWID,Output pulse width"
bitfld.long 0x0 6.--7. "INDP,Index positioning" "0,1,2,3"
bitfld.long 0x0 5. "FINDRST,First index signal reset the counter" "0,1"
bitfld.long 0x0 1.--2. "INDRSTDIR,Index signal reset counter direction" "0,1,2,3"
bitfld.long 0x0 0. "INDRSTEN,Index signal reset enable" "0,1"
group.long 0xE0++0x7
line.long 0x0 "TIMERx_DMACFG,DMA configuration register"
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
line.long 0x4 "DMATB,DMA transfer buffer register"
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
group.long 0xFC++0x3
line.long 0x0 "CFG,Configuration register"
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection bit" "0,1"
tree.end
tree "TIMER4 (General-L0 Timer)"
base ad:0x40000C00
group.long 0x0++0x13
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 12. "ADMEN,Adjustment mode enable" "0,1"
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
bitfld.long 0x0 4. "DIR,Direction" "0,1"
newline
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x0 2. "UPS,Update source" "0,1"
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 25. "MMC0_3,Master mode control 0 (bit 3)" "0,1"
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
line.long 0x8 "SMCFG,Slave mode configuration register"
bitfld.long 0x8 26. "PRMRPSEL,Pause + restart mode reset polarity selection" "0,1"
bitfld.long 0x8 25. "DECMODS,Decoder mode update source" "0,1"
bitfld.long 0x8 24. "DECMODEN,Decoder mode modified on-the-fly enable" "0,1"
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
bitfld.long 0x8 14. "SMC1,Part of slave mode controller is used to enable external clock mode 1" "0,1"
bitfld.long 0x8 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
newline
hexmask.long.byte 0x8 8.--11. 1. "ETFC,External trigger filter control"
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
bitfld.long 0x8 3. "OCRC,OxCPRE clear source selection" "0,1"
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
bitfld.long 0xC 31. "CH3COMADDIE,Channel 3 additional compare interrupt enable" "0,1"
bitfld.long 0xC 30. "CH2COMADDIE,Channel 2 additional compare interrupt enable" "0,1"
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
bitfld.long 0xC 19. "INDERRIE,Index error interrupt enable" "0,1"
bitfld.long 0xC 18. "DIRTRANIE,Direction transform interrupt enable" "0,1"
newline
bitfld.long 0xC 17. "DECDISIE,Quadrature decoder signal disconnection interrupt enable" "0,1"
bitfld.long 0xC 16. "DECJIE,Quadrature decoder signal jump (the two signals jump at the same time) interrupt enable" "0,1"
bitfld.long 0xC 15. "INDIE,Index interrupt enable" "0,1"
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
bitfld.long 0xC 12. "CH3DEN,Channel 3 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 11. "CH2DEN,Channel 2 capture / compare DMA request enable" "0,1"
newline
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
bitfld.long 0xC 4. "CH3IE,Channel 3 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 3. "CH2IE,Channel 2 capture / compare interrupt enable" "0,1"
newline
bitfld.long 0xC 2. "CH1IE,Channel 1 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 1. "CH0IE,Channel 0 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
line.long 0x10 "INTF,Interrupt flag register"
bitfld.long 0x10 31. "CH3COMADDIF,Channel 3 additional compare interrupt flag" "0,1"
bitfld.long 0x10 30. "CH2COMADDIF,Channel 2 additional compare interrupt flag" "0,1"
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
bitfld.long 0x10 19. "INDERRIF,Index error interrupt flag" "0,1"
bitfld.long 0x10 18. "DIRTRANIF,Direction transform interrupt flag" "0,1"
newline
bitfld.long 0x10 17. "DECDISIF,Quadrature decoder signal disconnection interrupt flag" "0,1"
bitfld.long 0x10 16. "DECJIF,Quadrature decoder signal jump (the two signals jump at the same time) interrupt flag" "0,1"
bitfld.long 0x10 15. "INDIF,Index interrupt flag" "0,1"
bitfld.long 0x10 12. "CH3OF,Channel 3 over capture flag" "0,1"
bitfld.long 0x10 11. "CH2OF,Channel 2 over capture flag" "0,1"
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
newline
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
bitfld.long 0x10 4. "CH3IF,Channel 3 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 3. "CH2IF,Channel 2 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 2. "CH1IF,Channel 1 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 1. "CH0IF,Channel 0 capture / compare interrupt flag" "0,1"
newline
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x3
line.long 0x0 "SWEVG,Software event generation register"
bitfld.long 0x0 31. "CH3COMADDG,Channel 3 additional compare event generation" "0,1"
bitfld.long 0x0 30. "CH2COMADDG,Channel 2 additional compare event generation" "0,1"
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
bitfld.long 0x0 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
newline
bitfld.long 0x0 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
group.long 0x18++0x3
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
bitfld.long 0x0 27. "CH1ADDUPS,Channel 1 additional update source" "0,1"
bitfld.long 0x0 26. "CH0ADDUPS,Channel 0 additional update source" "0,1"
newline
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
bitfld.long 0x0 10. "CH1COMFEN,Channel 1 output compare fast enable" "0,1"
newline
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
bitfld.long 0x0 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x7
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input mode)"
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
bitfld.long 0x0 27. "CH1ADDUPS,Channel 1 additional update source" "0,1"
bitfld.long 0x0 26. "CH0ADDUPS,Channel 0 additional update source" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
line.long 0x4 "CHCTL1_Output,Channel control register 1 (output mode)"
bitfld.long 0x4 31. "CH3MS_2,2th bit of CH3MS" "0,1"
bitfld.long 0x4 30. "CH2MS_2,2th bit of CH2MS" "0,1"
bitfld.long 0x4 29. "CH3COMADDSEN,Channel 3 additional compare output shadow enable" "0,1"
bitfld.long 0x4 28. "CH2COMADDSEN,Channel 2 additional compare output shadow enable" "0,1"
bitfld.long 0x4 27. "CH3ADDUPS,Channel 3 additional update source" "0,1"
bitfld.long 0x4 26. "CH2ADDUPS,Channel 2 additional update source" "0,1"
newline
bitfld.long 0x4 24. "CH3COMCTL_3,BIT 3 of channel 3 compare output control" "0,1"
bitfld.long 0x4 23. "CH2COMCTL_3,BIT 3 of channel 2 compare output control" "0,1"
bitfld.long 0x4 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
bitfld.long 0x4 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
bitfld.long 0x4 10. "CH3COMFEN,Channel 3 output compare fast enable" "0,1"
newline
bitfld.long 0x4 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
bitfld.long 0x4 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
bitfld.long 0x4 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
bitfld.long 0x4 2. "CH2COMFEN,Channel 2 output compare fast enable" "0,1"
bitfld.long 0x4 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
group.long 0x1C++0x13
line.long 0x0 "CHCTL1_Input,Channel control register 1 (input mode)"
bitfld.long 0x0 31. "CH3MS_2,2th bit of CH3MS" "0,1"
bitfld.long 0x0 30. "CH2MS_2,2th bit of CH2MS" "0,1"
bitfld.long 0x0 27. "CH3ADDUPS,Channel 3 additional update source" "0,1"
bitfld.long 0x0 26. "CH2ADDUPS,Channel 2 additional update source" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "CH3CAPFLT,Channel 3 input capture filter control"
bitfld.long 0x0 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "CH2CAPFLT,Channel 2 input capture filter control"
bitfld.long 0x0 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
line.long 0x4 "CHCTL2,Channel control register 2"
bitfld.long 0x4 15. "CH3NP,Channel 3 complementary capture / compare polarity" "0,1"
bitfld.long 0x4 13. "CH3P,Channel 3 capture / compare function polarity" "0,1"
bitfld.long 0x4 12. "CH3EN,Channel 3 capture / compare function enable" "0,1"
bitfld.long 0x4 11. "CH2NP,Channel 2 complementary capture / compare polarity" "0,1"
bitfld.long 0x4 9. "CH2P,Channel 2 capture / compare function polarity" "0,1"
bitfld.long 0x4 8. "CH2EN,Channel 2 capture / compare function enable" "0,1"
newline
bitfld.long 0x4 7. "CH1NP,Channel 1 complementary capture / compare polarity" "0,1"
bitfld.long 0x4 5. "CH1P,Channel 1 capture / compare function polarity" "0,1"
bitfld.long 0x4 4. "CH1EN,Channel 1 capture / compare function enable" "0,1"
bitfld.long 0x4 3. "CH0NP,Channel 0 complementary output polarity" "0,1"
bitfld.long 0x4 1. "CH0P,Channel 0 capture / compare function polarity" "0,1"
bitfld.long 0x4 0. "CH0EN,Channel 0 capture / compare function enable" "0,1"
line.long 0x8 "CNT,Counter register"
bitfld.long 0x8 31. "UPIFBU,UPIF bit backup" "0,1"
hexmask.long 0x8 0.--30. 1. "CNT,This bit-field indicates the current counter value"
line.long 0xC "PSC,Prescaler register"
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value of the counter clock"
line.long 0x10 "CAR,Counter auto reload register"
hexmask.long 0x10 0.--31. 1. "CARL,Counter auto reload value"
group.long 0x34++0xF
line.long 0x0 "CH0CV,Channel 0 capture/compare value register"
hexmask.long 0x0 0.--31. 1. "CH0VAL,Capture / compare value of channel 0"
line.long 0x4 "CH1CV,Channel 1 capture/compare value register"
hexmask.long 0x4 0.--31. 1. "CH1VAL,Capture / compare value of channel 1"
line.long 0x8 "CH2CV,Channel 2 capture/compare value register"
hexmask.long 0x8 0.--31. 1. "CH2VAL,Capture / compare value of channel 2"
line.long 0xC "CH3CV,Channel 3 capture/compare value register"
hexmask.long 0xC 0.--31. 1. "CH3VAL,Capture / compare value of channel 3"
group.long 0x64++0x13
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
hexmask.long 0x0 0.--31. 1. "CH0COMVAL_ADD,Additional compare value of channel 0 (bit 16 to 31)"
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
hexmask.long 0x4 0.--31. 1. "CH1COMVAL_ADD,Additional compare value of channel 1 (bit 16 to 31)"
line.long 0x8 "CH2COMV_ADD,Channel 2 additional compare value register"
hexmask.long 0x8 0.--31. 1. "CH2COMVAL_ADD,Additional compare value of channel 2 (bit 16 to 31)"
line.long 0xC "CH3COMV_ADD,Channel 3 additional compare value register"
hexmask.long 0xC 0.--31. 1. "CH3COMVAL_ADD,Additional compare value of channel 3 (bit 16 to 31)"
line.long 0x10 "CTL2,Control register 2"
bitfld.long 0x10 31. "CH3CPWMEN,Channel 3 composite PWM mode enable" "0,1"
bitfld.long 0x10 30. "CH2CPWMEN,Channel 2 composite PWM mode enable" "0,1"
bitfld.long 0x10 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
bitfld.long 0x10 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
bitfld.long 0x10 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
bitfld.long 0x10 18. "DECJDEN,Quadrature decoder signal jump (the two signals jump at the same time) detection enable" "0,1"
newline
bitfld.long 0x10 14.--15. "CH3OMPSEL,Channel 3 output match pulse select" "0,1,2,3"
bitfld.long 0x10 12.--13. "CH2OMPSEL,Channel 2 output match pulse select" "0,1,2,3"
bitfld.long 0x10 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
bitfld.long 0x10 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
group.long 0x90++0x7
line.long 0x0 "AFCTL1,TIMER alternate function control register 1"
bitfld.long 0x0 19.--21. "OCRINSEL,OCPRE_CLR inputs selection" "0,1,2,3,4,5,6,7"
line.long 0x4 "WDGPER,Watchdog counter period register"
hexmask.long 0x4 0.--31. 1. "WDGPER,Watchdog counter period value"
group.long 0xA0++0x3
line.long 0x0 "TIMER_DECCTL,Decoder control register"
bitfld.long 0x0 24.--26. "OPPSC,Output pulse prescaler" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 16.--23. 1. "OPWID,Output pulse width"
bitfld.long 0x0 6.--7. "INDP,Index positioning" "0,1,2,3"
bitfld.long 0x0 5. "FINDRST,First index signal reset the counter" "0,1"
bitfld.long 0x0 1.--2. "INDRSTDIR,Index signal reset counter direction" "0,1,2,3"
bitfld.long 0x0 0. "INDRSTEN,Index signal reset enable" "0,1"
group.long 0xE0++0x7
line.long 0x0 "TIMERx_DMACFG,DMA configuration register"
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
line.long 0x4 "DMATB,DMA transfer buffer register"
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
group.long 0xFC++0x3
line.long 0x0 "CFG,Configuration register"
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection bit" "0,1"
tree.end
tree "TIMER5 (Basic Timer)"
base ad:0x40001000
group.long 0x0++0x7
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 12. "ADMEN,Adjustment mode enable" "0,1"
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x0 2. "UPS,Update source" "0,1"
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
group.long 0xC++0x7
line.long 0x0 "DMAINTEN,Interrupt enable register"
bitfld.long 0x0 8. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x0 0. "UPIE,Update interrupt enable" "0,1"
line.long 0x4 "INTF,Interrupt flag register"
bitfld.long 0x4 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x3
line.long 0x0 "SWEVG,Software event generation register"
bitfld.long 0x0 0. "UPG,Update generation" "0,1"
group.long 0x24++0xB
line.long 0x0 "CNT,Counter register"
rbitfld.long 0x0 31. "UPIFBU,UPIF bit backup" "0,1"
hexmask.long.word 0x0 0.--15. 1. "CNT,This bit-field indicates the current counter value"
line.long 0x4 "PSC,Prescaler register"
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value of the counter clock"
line.long 0x8 "CARL,Counter auto reload register"
hexmask.long.byte 0x8 28.--31. 1. "CARL_16_19,Counter auto reload value(bit 16 to 19)"
hexmask.long.word 0x8 0.--15. 1. "CARL,Counter auto reload value"
tree.end
tree "TIMER6 (Basic Timer)"
base ad:0x40001400
group.long 0x0++0x7
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 12. "ADMEN,Adjustment mode enable" "0,1"
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x0 2. "UPS,Update source" "0,1"
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
group.long 0xC++0x7
line.long 0x0 "DMAINTEN,Interrupt enable register"
bitfld.long 0x0 8. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x0 0. "UPIE,Update interrupt enable" "0,1"
line.long 0x4 "INTF,Interrupt flag register"
bitfld.long 0x4 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x3
line.long 0x0 "SWEVG,Software event generation register"
bitfld.long 0x0 0. "UPG,Update generation" "0,1"
group.long 0x24++0xB
line.long 0x0 "CNT,Counter register"
rbitfld.long 0x0 31. "UPIFBU,UPIF bit backup" "0,1"
hexmask.long.word 0x0 0.--15. 1. "CNT,This bit-field indicates the current counter value"
line.long 0x4 "PSC,Prescaler register"
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value of the counter clock"
line.long 0x8 "CARL,Counter auto reload register"
hexmask.long.byte 0x8 28.--31. 1. "CARL_16_19,Counter auto reload value(bit 16 to 19)"
hexmask.long.word 0x8 0.--15. 1. "CARL,Counter auto reload value"
tree.end
tree "TIMER7 (Advanced Timer)"
base ad:0x40013400
group.long 0x0++0x13
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 12. "ADMEN,Adjustment mode enable" "0,1"
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
bitfld.long 0x0 4. "DIR,Direction" "0,1"
newline
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x0 2. "UPS,Update source" "0,1"
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 30.--31. "CCUC1_2,Commutation control shadow register update control" "0,1,2,3"
bitfld.long 0x4 25. "MMC0_3,Master mode control 0" "0,1"
bitfld.long 0x4 20.--22. "MMC1,Master mode control 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 15. "ISO3N,Idle state of multi mode channel 3 complementary output" "0,1"
bitfld.long 0x4 14. "ISO3,Idle state of channel 3 output" "0,1"
bitfld.long 0x4 13. "ISO2N,Idle state of multi mode channel 2 complementary output" "0,1"
newline
bitfld.long 0x4 12. "ISO2,Idle state of channel 2 output" "0,1"
bitfld.long 0x4 11. "ISO1N,Idle state of multi mode channel 1 complementary output" "0,1"
bitfld.long 0x4 10. "ISO1,Idle state of channel 1 output" "0,1"
bitfld.long 0x4 9. "ISO0N,Idle state of multi mode channel 0 complementary output" "0,1"
bitfld.long 0x4 8. "ISO0,Idle state of channel 0 output" "0,1"
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
newline
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
bitfld.long 0x4 2. "CCUC,Commutation control shadow register update control" "0,1"
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
line.long 0x8 "SMCFG,Slave mode configuration register"
bitfld.long 0x8 26. "PRMRPSEL,Pause + restart mode reset polarity selection" "0,1"
bitfld.long 0x8 25. "DECMODS,Decoder mode update source" "0,1"
bitfld.long 0x8 24. "DECMODEN,Decoder mode modified on-the-fly enable" "0,1"
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
bitfld.long 0x8 14. "SMC1,Part of slave mode controller is used to enable external clock mode 1" "0,1"
bitfld.long 0x8 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
newline
hexmask.long.byte 0x8 8.--11. 1. "ETFC,External trigger filter control"
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
bitfld.long 0x8 3. "OCRC,OxCPRE / MOxCPRE clear source selection" "0,1"
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
bitfld.long 0xC 31. "CH3COMADDIE,Channel 3 additional compare interrupt enable" "0,1"
bitfld.long 0xC 30. "CH2COMADDIE,Channel 2 additional compare interrupt enable" "0,1"
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
bitfld.long 0xC 27. "MCH3DEN,Multi mode channel 3 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 26. "MCH2DEN,Multi mode channel 2 capture / compare DMA request enable" "0,1"
newline
bitfld.long 0xC 25. "MCH1DEN,Multi mode channel 1 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 24. "MCH0DEN,Multi mode channel 0 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 23. "MCH3IE,Multi mode channel 3 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 22. "MCH2IE,Multi mode channel 2 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 21. "MCH1IE,Multi mode channel 1 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 20. "MCH0IE,Multi mode channel 0 capture / compare interrupt enable" "0,1"
newline
bitfld.long 0xC 19. "INDERRIE,Index error interrupt enable" "0,1"
bitfld.long 0xC 18. "DIRTRANIE,Direction transform interrupt enable" "0,1"
bitfld.long 0xC 17. "DECDISIE,Quadrature decoder signal disconnection interrupt enable" "0,1"
bitfld.long 0xC 16. "DECJIE,Quadrature decoder signal jump (the two signals jump at the same time) interrupt enable" "0,1"
bitfld.long 0xC 15. "INDIE,Index interrupt enable" "0,1"
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
newline
bitfld.long 0xC 13. "CMTDEN,Commutation DMA request enable" "0,1"
bitfld.long 0xC 12. "CH3DEN,Channel 3 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 11. "CH2DEN,Channel 2 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
newline
bitfld.long 0xC 7. "BRKIE,Break interrupt enable" "0,1"
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
bitfld.long 0xC 5. "CMTIE,Commutation interrupt enable" "0,1"
bitfld.long 0xC 4. "CH3IE,Channel 3 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 3. "CH2IE,Channel 2 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 2. "CH1IE,Channel 1 capture / compare interrupt enable" "0,1"
newline
bitfld.long 0xC 1. "CH0IE,Channel 0 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
line.long 0x10 "INTF,Interrupt flag register"
bitfld.long 0x10 31. "CH3COMADDIF,Channel 3 additional compare interrupt flag" "0,1"
bitfld.long 0x10 30. "CH2COMADDIF,Channel 2 additional compare interrupt flag" "0,1"
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
bitfld.long 0x10 27. "MCH3OF,Multi mode channel 3 over capture flag" "0,1"
bitfld.long 0x10 26. "MCH2OF,Multi mode channel 2 over capture flag" "0,1"
newline
bitfld.long 0x10 25. "MCH1OF,Multi mode channel 1 over capture flag" "0,1"
bitfld.long 0x10 24. "MCH0OF,Multi mode channel 0 over capture flag" "0,1"
bitfld.long 0x10 23. "MCH3IF,Multi mode channel 3 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 22. "MCH2IF,Multi mode channel 2 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 21. "MCH1IF,Multi mode channel 1 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 20. "MCH0IF,Multi mode channel 0 capture / compare interrupt flag" "0,1"
newline
bitfld.long 0x10 19. "INDERRIF,Index error interrupt flag" "0,1"
bitfld.long 0x10 18. "DIRTRANIF,Direction transform interrupt flag" "0,1"
bitfld.long 0x10 17. "DECDISIF,Quadrature decoder signal disconnection interrupt flag" "0,1"
bitfld.long 0x10 16. "DECJIF,Quadrature decoder signal jump (the two signals jump at the same time) interrupt flag" "0,1"
bitfld.long 0x10 15. "INDIF,Index interrupt flag" "0,1"
bitfld.long 0x10 13. "SYSBIF,System source break interrupt flag" "0,1"
newline
bitfld.long 0x10 12. "CH3OF,Channel 3 over capture flag" "0,1"
bitfld.long 0x10 11. "CH2OF,Channel 2 over capture flag" "0,1"
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
bitfld.long 0x10 8. "BRK1IF,BREAK1 interrupt flag" "0,1"
bitfld.long 0x10 7. "BRK0IF,BREAK0 interrupt flag" "0,1"
newline
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
bitfld.long 0x10 5. "CMTIF,Channel commutation interrupt flag" "0,1"
bitfld.long 0x10 4. "CH3IF,Channel 3 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 3. "CH2IF,Channel 2 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 2. "CH1IF,Channel 1 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 1. "CH0IF,Channel 0 capture / compare interrupt flag" "0,1"
newline
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x3
line.long 0x0 "SWEVG,Software event generation register"
bitfld.long 0x0 31. "CH3COMADDG,Channel 3 additional compare event generation" "0,1"
bitfld.long 0x0 30. "CH2COMADDG,Channel 2 additional compare event generation" "0,1"
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
bitfld.long 0x0 23. "MCH3G,Multi mode channel 3 capture or compare event generation" "0,1"
bitfld.long 0x0 22. "MCH2G,Multi mode channel 2 capture or compare event generation" "0,1"
newline
bitfld.long 0x0 21. "MCH1G,Multi mode channel 1 capture or compare event generation" "0,1"
bitfld.long 0x0 20. "MCH0G,Multi mode channel 0 capture or compare event generation" "0,1"
bitfld.long 0x0 8. "BRK1G,BREAK1 event generation" "0,1"
bitfld.long 0x0 7. "BRK0G,BREAK0 event generation" "0,1"
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
bitfld.long 0x0 5. "CMTG,Channel commutation event generation" "0,1"
newline
bitfld.long 0x0 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
bitfld.long 0x0 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
group.long 0x18++0x3
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
bitfld.long 0x0 27. "CH1ADDUPS,Channel 1 additional update source" "0,1"
bitfld.long 0x0 26. "CH0ADDUPS,Channel 0 additional update source" "0,1"
newline
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
bitfld.long 0x0 10. "CH1COMFEN,Channel 1 output compare fast enable" "0,1"
newline
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
bitfld.long 0x0 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x7
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input mode)"
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
bitfld.long 0x0 27. "CH1ADDUPS,Channel 1 additional update source" "0,1"
bitfld.long 0x0 26. "CH0ADDUPS,Channel 0 additional update source" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
line.long 0x4 "CHCTL1_Output,Channel control register 1 (output mode)"
bitfld.long 0x4 31. "CH3MS_2,2th bit of CH3MS" "0,1"
bitfld.long 0x4 30. "CH2MS_2,2th bit of CH2MS" "0,1"
bitfld.long 0x4 29. "CH3COMADDSEN,Channel 3 additional compare output shadow enable" "0,1"
bitfld.long 0x4 28. "CH2COMADDSEN,Channel 2 additional compare output shadow enable" "0,1"
bitfld.long 0x4 27. "CH3ADDUPS,Channel 3 additional update source" "0,1"
bitfld.long 0x4 26. "CH2ADDUPS,Channel 2 additional update source" "0,1"
newline
bitfld.long 0x4 24. "CH3COMCTL_3,BIT 3 of channel 3 compare output control" "0,1"
bitfld.long 0x4 16. "CH2COMCTL_3,BIT 3 of channel 2 compare output control" "0,1"
bitfld.long 0x4 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
bitfld.long 0x4 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
bitfld.long 0x4 10. "CH3COMFEN,Channel 3 output compare fast enable" "0,1"
newline
bitfld.long 0x4 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
bitfld.long 0x4 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
bitfld.long 0x4 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
bitfld.long 0x4 2. "CH2COMFEN,Channel 2 output compare fast enable" "0,1"
bitfld.long 0x4 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
group.long 0x1C++0x2F
line.long 0x0 "CHCTL1_Input,Channel control register 1 (input mode)"
bitfld.long 0x0 31. "CH3MS_2,2th bit of CH3MS" "0,1"
bitfld.long 0x0 30. "CH2MS_2,2th bit of CH2MS" "0,1"
bitfld.long 0x0 27. "CH3ADDUPS,Channel 3 additional update source" "0,1"
bitfld.long 0x0 26. "CH2ADDUPS,Channel 2 additional update source" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "CH3CAPFLT,Channel 3 input capture filter control"
bitfld.long 0x0 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "CH2CAPFLT,Channel 2 input capture filter control"
bitfld.long 0x0 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
line.long 0x4 "CHCTL2,Channel control register 2"
bitfld.long 0x4 15. "MCH3P,Multi mode channel 3 capture / compare polarity" "0,1"
bitfld.long 0x4 14. "MCH3EN,Multi mode channel 3 capture / compare enable" "0,1"
bitfld.long 0x4 13. "CH3P,Channel 3 capture / compare polarity" "0,1"
bitfld.long 0x4 12. "CH3EN,Channel 3 capture / compare enable" "0,1"
bitfld.long 0x4 11. "MCH2P,Multi mode channel 2 output polarity" "0,1"
bitfld.long 0x4 10. "MCH2EN,Multi mode channel 2 output enable" "0,1"
newline
bitfld.long 0x4 9. "CH2P,Channel 2 capture / compare polarity" "0,1"
bitfld.long 0x4 8. "CH2EN,Channel 2 capture / compare enable" "0,1"
bitfld.long 0x4 7. "MCH1P,Multi mode channel 1 output polarity" "0,1"
bitfld.long 0x4 6. "MCH1EN,Multi mode channel 1 output enable" "0,1"
bitfld.long 0x4 5. "CH1P,Channel 1 capture / compare polarity" "0,1"
bitfld.long 0x4 4. "CH1EN,Channel 1 capture / compare enable" "0,1"
newline
bitfld.long 0x4 3. "MCH0P,Multi mode channel 0 output polarity" "0,1"
bitfld.long 0x4 2. "MCH0EN,Multi mode channel 0 capture / compare enable" "0,1"
bitfld.long 0x4 1. "CH0P,Channel 0 capture / compare polarity" "0,1"
bitfld.long 0x4 0. "CH0EN,Channel 0 capture / compare enable" "0,1"
line.long 0x8 "CNT,Counter register"
rbitfld.long 0x8 31. "UPIFBU,UPIF bit backup" "0,1"
hexmask.long.word 0x8 0.--15. 1. "CNT,This bit-field indicates the current counter value"
line.long 0xC "PSC,Prescaler register"
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value of the counter clock"
line.long 0x10 "CAR,Counter auto reload register"
hexmask.long.byte 0x10 28.--31. 1. "CARL16_19,Counter auto reload value(bit 16 to 19)"
hexmask.long.word 0x10 0.--15. 1. "CARL,Counter auto reload value (bit 0 to 15)"
line.long 0x14 "CREP0,Counter repetition register 0"
hexmask.long.byte 0x14 0.--7. 1. "CREP0,Counter repetition value 0"
line.long 0x18 "CH0CV,Channel 0 capture/compare value register"
hexmask.long.byte 0x18 28.--31. 1. "CH0VAL16_19,Capture / compare value of channel0 (bit 16 to 19)"
hexmask.long.word 0x18 0.--15. 1. "CH0VAL,Capture / compare value of channel 0"
line.long 0x1C "CH1CV,Channel 1 capture/compare value register"
hexmask.long.byte 0x1C 28.--31. 1. "CH1VAL16_19,Capture / compare value of channel1 (bit 16 to 19)"
hexmask.long.word 0x1C 0.--15. 1. "CH1VAL,Capture / compare value of channel 1 (bit 0 to 15)"
line.long 0x20 "CH2CV,Channel 2 capture/compare value register"
hexmask.long.byte 0x20 28.--31. 1. "CH2VAL16_19,Capture / compare value of channel 2 (bit 16 to 19)"
hexmask.long.word 0x20 0.--15. 1. "CH2VAL,Capture or compare value of channel 2"
line.long 0x24 "CH3CV,Channel 3 capture/compare value register"
hexmask.long.byte 0x24 28.--31. 1. "CH3VAL16_19,Capture / compare value of channel 3 (bit 16 to 19)"
hexmask.long.word 0x24 0.--15. 1. "CH3VAL,Capture / compare value of channel 3 (bit 0 to 15)"
line.long 0x28 "CCHP0,Complementary channel protection register 0"
bitfld.long 0x28 29. "BRK1LK,BREAK1 input locked" "0,1"
bitfld.long 0x28 28. "BRK0LK,BREAK0 input locked" "0,1"
bitfld.long 0x28 27. "BRK1REL,BREAK1 input released" "0,1"
bitfld.long 0x28 26. "BRK0REL,BREAK0 input released" "0,1"
bitfld.long 0x28 25. "BRK1P,BREAK1 input signal polarity" "0,1"
bitfld.long 0x28 24. "BRK1EN,BREAK1 input signal enable" "0,1"
newline
hexmask.long.byte 0x28 20.--23. 1. "BRK1F,BREAK1 input signal filter"
hexmask.long.byte 0x28 16.--19. 1. "BRK0F,BREAK0 input signal filter"
bitfld.long 0x28 15. "POEN,Primary output enable" "0,1"
bitfld.long 0x28 14. "OAEN,Output automatic enable" "0,1"
bitfld.long 0x28 13. "BRK0P,BREAK0 input signal polarity" "0,1"
bitfld.long 0x28 12. "BRK0EN,BREAK0 input signal enable" "0,1"
newline
bitfld.long 0x28 11. "ROS,Run mode off-state enable" "0,1"
bitfld.long 0x28 10. "IOS,Idle mode off-state enable" "0,1"
bitfld.long 0x28 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
hexmask.long.byte 0x28 0.--7. 1. "DTCFG,Dead time configuration"
line.long 0x2C "MCHCTL0_Output,Multi mode channel control register 0 (output mode)"
bitfld.long 0x2C 31. "MCH1MS_2,Multi mode channel 1 I/O mode selection" "0,1"
bitfld.long 0x2C 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
bitfld.long 0x2C 24. "MCH1COMCT_3,Multi mode channel 1 compare output control" "0,1"
bitfld.long 0x2C 16. "MCH0COMCTL_3,Multi mode channel 0 compare output control" "0,1"
bitfld.long 0x2C 15. "MCH1COMCEN,Multi mode channel 1 output compare clear enable" "0,1"
bitfld.long 0x2C 12.--14. "MCH1COMCTL,Multi mode channel 1 compare output control" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2C 11. "MCH1COMSEN,Multi mode channel 1 output compare shadow enable" "0,1"
bitfld.long 0x2C 10. "MCH1COMFEN,Multi mode channel 1 output compare fast enable" "0,1"
bitfld.long 0x2C 8.--9. "MCH1MS,Multi mode channel 1 I/O mode selection" "0,1,2,3"
bitfld.long 0x2C 7. "MCH0COMCEN,Multi mode channel 0 output compare clear enable" "0,1"
bitfld.long 0x2C 4.--6. "MCH0COMCTL,Multi mode channel 0 output compare control" "0,1,2,3,4,5,6,7"
bitfld.long 0x2C 3. "MCH0COMSEN,Multi mode channel 0 output compare shadow enable" "0,1"
newline
bitfld.long 0x2C 2. "MCH0COMFEN,Multi mode channel 0 output compare fast enable" "0,1"
bitfld.long 0x2C 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
group.long 0x48++0x7
line.long 0x0 "MCHCTL0_Input,Multi mode channel control register 0 (input mode)"
bitfld.long 0x0 31. "MCH1MS_2,Multi mode channel 1 I/O mode selection" "0,1"
bitfld.long 0x0 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "MCH1CAPFLT,Multi mode channel 1 input capture filter control"
bitfld.long 0x0 10.--11. "MCH1CAPPSC,Multi mode channel 1 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 8.--9. "MCH1MS,Multi mode channel 1 I/O mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "MCH0CAPFLT,Multi mode channel 0 input capture filter control"
newline
bitfld.long 0x0 2.--3. "MCH0CAPPSC,Multi mode channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
line.long 0x4 "MCHCTL1_Output,Multi mode channel control register 1 (output mode)"
bitfld.long 0x4 31. "MCH3MS_2,2th bit of MCH3MS" "0,1"
bitfld.long 0x4 30. "MCH2MS_2,2th bit of MCH2MS" "0,1"
bitfld.long 0x4 24. "MCH3COMCT_3,Multi mode channel 3 compare output control" "0,1"
bitfld.long 0x4 16. "MCH2COMCTL_3,Multi mode channel 2 compare output control" "0,1"
bitfld.long 0x4 15. "MCH3COMCEN,Multi mode channel 3 output compare clear enable" "0,1"
bitfld.long 0x4 12.--14. "MCH3COMCTL,Multi mode channel 3 compare output control" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 11. "MCH3COMSEN,Multi mode channel 3 output compare shadow enable" "0,1"
bitfld.long 0x4 10. "MCH3COMFEN,Multi mode channel 3 output compare fast enable" "0,1"
bitfld.long 0x4 8.--9. "MCH3MS,Multi mode channel 3 I/O mode selection" "0,1,2,3"
bitfld.long 0x4 7. "MCH2COMCEN,Multi mode channel 2 output compare clear enable" "0,1"
bitfld.long 0x4 4.--6. "MCH2COMCTL,Multi mode channel 2 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "MCH2COMSEN,Multi mode channel 2 output compare shadow enable" "0,1"
newline
bitfld.long 0x4 2. "MCH2COMFEN,Multi mode channel 2 output compare fast enable" "0,1"
bitfld.long 0x4 0.--1. "MCH2MS,Multi mode channel 2 I/O mode selection" "0,1,2,3"
group.long 0x4C++0x2B
line.long 0x0 "MCHCTL1_Input,Multi mode channel control register 1(input mode)"
bitfld.long 0x0 31. "MCH3MS_2,2th bit of MCH3MS" "0,1"
bitfld.long 0x0 30. "MCH2MS_2,2th bit of MCH2MS" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "MCH3CAPFLT,Multi mode channel 3 input capture filter control"
bitfld.long 0x0 10.--11. "MCH3CAPPSC,Multi mode channel 3 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 8.--9. "MCH3MS,Multi mode channel 3 I/O mode selection." "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "MCH2CAPFLT,Multi mode channel 2 input capture filter control"
newline
bitfld.long 0x0 2.--3. "MCH2CAPPSC,Multi mode channel 2 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "MCH2MS,Multi mode channel 2 I/O mode selection" "0,1,2,3"
line.long 0x4 "MCHCTL2,Multi mode channel control register 2"
bitfld.long 0x4 6.--7. "MCH3FP,Multi mode channel 3 capture / compare free polarity" "0,1,2,3"
bitfld.long 0x4 4.--5. "MCH2FP,Multi mode channel 2 capture / compare free polarity" "0,1,2,3"
bitfld.long 0x4 2.--3. "MCH1FP,Multi mode channel 1 capture / compare free polarity" "0,1,2,3"
bitfld.long 0x4 0.--1. "MCH0FP,Multi mode channel 0 capture / compare free polarity" "0,1,2,3"
line.long 0x8 "MCH0CV,Multi mode channel 0 capture/compare value register"
hexmask.long.word 0x8 0.--15. 1. "MCH0VAL,Capture / compare value of multi mode channel 0"
line.long 0xC "MCH1CV,Multi mode channel 1 capture/compare value register"
hexmask.long.word 0xC 0.--15. 1. "MCH1VAL,Capture / compare value of multi mode channel 1"
line.long 0x10 "MCH2CV,Multi mode channel 2 capture/compare value register"
hexmask.long.word 0x10 0.--15. 1. "MCH2VAL,Capture / compare value of multi mode channel 2"
line.long 0x14 "MCH3CV,Multi mode channel 3 capture / compare value register"
hexmask.long.word 0x14 0.--15. 1. "MCH3VAL,Capture / compare value of channel 3"
line.long 0x18 "CH0COMV_ADD,Channel 0 additional compare value register"
hexmask.long.word 0x18 0.--15. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
line.long 0x1C "CH1COMV_ADD,Channel 1 additional compare value register"
hexmask.long.word 0x1C 0.--15. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
line.long 0x20 "CH2COMV_ADD,Channel 2 additional compare value register"
hexmask.long.word 0x20 0.--15. 1. "CH2COMVAL_ADD,Additional compare value of channel 2"
line.long 0x24 "CH3COMV_ADD,Channel 3 additional compare value register"
hexmask.long.word 0x24 0.--15. 1. "CH3COMVAL_ADD,Additional compare value of channel 3"
line.long 0x28 "CTL2,Control register 2"
bitfld.long 0x28 31. "CH3CPWMEN,Channel 3 composite PWM mode enable" "0,1"
bitfld.long 0x28 30. "CH2CPWMEN,Channel 2 composite PWM mode enable" "0,1"
bitfld.long 0x28 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
bitfld.long 0x28 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
bitfld.long 0x28 26.--27. "MCH3MSEL,Multi mode channel 3 mode select" "0,1,2,3"
bitfld.long 0x28 24.--25. "MCH2MSEL,Multi mode channel 2 mode select" "0,1,2,3"
newline
bitfld.long 0x28 22.--23. "MCH1MSEL,Multi mode channel 1 mode select" "0,1,2,3"
bitfld.long 0x28 20.--21. "MCH0MSEL,Multi mode channel 0 mode select" "0,1,2,3"
bitfld.long 0x28 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
bitfld.long 0x28 18. "DECJDEN,Quadrature decoder signal jump (the two signals jump at the same time) detection enable" "0,1"
bitfld.long 0x28 14.--15. "CH3OMPSEL,Channel 3 output match pulse select" "0,1,2,3"
bitfld.long 0x28 12.--13. "CH2OMPSEL,Channel 2 output match pulse select" "0,1,2,3"
newline
bitfld.long 0x28 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
bitfld.long 0x28 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
bitfld.long 0x28 7. "BRKENCH3,Break control enable for channel 3" "0,1"
bitfld.long 0x28 6. "BRKENCH2,Break control enable for channel 2" "0,1"
bitfld.long 0x28 5. "BRKENCH1,Break control enable for channel 1" "0,1"
bitfld.long 0x28 4. "BRKENCH0,Break control enable for channel 0" "0,1"
newline
bitfld.long 0x28 3. "DTIENCH3,Dead time inserted enable for channel 3" "0,1"
bitfld.long 0x28 2. "DTIENCH2,Dead time inserted enable for channel 2" "0,1"
bitfld.long 0x28 1. "DTIENCH1,Dead time inserted enable for channel 1" "0,1"
bitfld.long 0x28 0. "DTIENCH0,Dead time inserted enable for channel 0" "0,1"
group.long 0x7C++0x2F
line.long 0x0 "FCCHP0,Free complementary channel protection register 0"
bitfld.long 0x0 31. "FCCHP0EN,Free complementary channel protection register 0 enable" "0,1"
hexmask.long.byte 0x0 16.--23. 1. "DTFCFG,Dead time falling edge configure"
bitfld.long 0x0 11. "ROS,Run mode off-state configure" "0,1"
bitfld.long 0x0 10. "IOS,Idle mode off-state configure" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configure"
line.long 0x4 "FCCHP1,Free complementary channel protection register 1"
bitfld.long 0x4 31. "FCCHP1EN,Free complementary channel protection register 1 enable" "0,1"
hexmask.long.byte 0x4 16.--23. 1. "DTFCFG,Dead time falling edge configure"
bitfld.long 0x4 11. "ROS,Run mode off-state configure" "0,1"
bitfld.long 0x4 10. "IOS,Idle mode off-state configure" "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DTCFG,Dead time configure"
line.long 0x8 "FCCHP2,Free complementary channel protection register 2"
bitfld.long 0x8 31. "FCCHP2EN,Free complementary channel protection register 2 enable" "0,1"
hexmask.long.byte 0x8 16.--23. 1. "DTFCFG,Dead time falling edge configure"
bitfld.long 0x8 11. "ROS,Run mode off-state configure" "0,1"
bitfld.long 0x8 10. "IOS,Idle mode off-state configure" "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DTCFG,Dead time configure"
line.long 0xC "FCCHP3,Free complementary channel protection register 3"
bitfld.long 0xC 31. "FCCHP3EN,Free complementary channel protection register 0 enable" "0,1"
hexmask.long.byte 0xC 16.--23. 1. "DTFCFG,Dead time falling edge configure"
bitfld.long 0xC 11. "ROS,Run mode off-state configure" "0,1"
bitfld.long 0xC 10. "IOS,Idle mode off-state configure" "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DTCFG,Dead time configure"
line.long 0x10 "AFCTL0,Alternate function control register 0"
bitfld.long 0x10 28. "BRK0CMP3P,BREAK0 CMP3 input polarity" "0,1"
bitfld.long 0x10 27. "BRK0CMP2P,BREAK0 CMP2 input polarity" "0,1"
bitfld.long 0x10 26. "BRK0CMP1P,BREAK0 CMP1 input polarity" "0,1"
bitfld.long 0x10 25. "BRK0CMP0P,BREAK0 CMP0 input polarity" "0,1"
bitfld.long 0x10 18. "BRK0IN2P,BREAK0 BRKIN2 alternate function input polarity" "0,1"
bitfld.long 0x10 17. "BRK0IN1P,BREAK0 BRKIN1 alternate function input polarity" "0,1"
newline
bitfld.long 0x10 16. "BRK0IN0P,BREAK0 BRKIN0 alternate function input polarity" "0,1"
bitfld.long 0x10 15. "BRK0CMP6EN,BREAK0 CMP6 enable" "0,1"
bitfld.long 0x10 14. "BRK0CMP5EN,BREAK0 CMP5 enable" "0,1"
bitfld.long 0x10 13. "BRK0CMP4EN,BREAK0 CMP4 enable" "0,1"
bitfld.long 0x10 12. "BRK0CMP3EN,BREAK0 CMP3 enable" "0,1"
bitfld.long 0x10 11. "BRK0CMP2EN,BREAK0 CMP2 enable" "0,1"
newline
bitfld.long 0x10 10. "BRK0CMP1EN,BREAK0 CMP1 enable" "0,1"
bitfld.long 0x10 9. "BRK0CMP0EN,BREAK0 CMP0 enable" "0,1"
bitfld.long 0x10 8. "BRK0HPDFEN,BREAK0 HPDF input enable" "0,1"
bitfld.long 0x10 7. "BRK0CMP7EN,BREAK0 CMP7 enable" "0,1"
bitfld.long 0x10 2. "BRK0IN2EN,BREAK0 BRKIN2 alternate function input enable" "0,1"
bitfld.long 0x10 1. "BRK0IN1EN,BREAK0 BRKIN1 alternate function input enable" "0,1"
newline
bitfld.long 0x10 0. "BRK0IN0EN,BREAK0 BRKIN0 alternate function input enable" "0,1"
line.long 0x14 "AFCTL1,Alternate function control register 1"
bitfld.long 0x14 28. "BRK1CMP3P,BREAK1 CMP3 input polarity" "0,1"
bitfld.long 0x14 27. "BRK1CMP2P,BREAK1 CMP2 input polarity" "0,1"
bitfld.long 0x14 26. "BRK1CMP1P,BREAK1 CMP1 input polarity" "0,1"
bitfld.long 0x14 25. "BRK1CMP0P,BREAK1 CMP0 input polarity" "0,1"
bitfld.long 0x14 19.--21. "OCRINSEL,OCPRE_CLR inputs selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 18. "BRK1IN2P,BREAK1 BRKIN2 alternate function input polarity" "0,1"
newline
bitfld.long 0x14 17. "BRK1IN1P,BREAK1 BRKIN1 alternate function input polarity" "0,1"
bitfld.long 0x14 16. "BRK1IN0P,BREAK1 BRKIN0 alternate function input polarity" "0,1"
bitfld.long 0x14 15. "BRK1CMP6EN,BREAK1 CMP6 enable" "0,1"
bitfld.long 0x14 14. "BRK1CMP5EN,BREAK1 CMP5 enable" "0,1"
bitfld.long 0x14 13. "BRK1CMP4EN,BREAK1 CMP4 enable" "0,1"
bitfld.long 0x14 12. "BRK1CMP3EN,BREAK1 CMP3 enable" "0,1"
newline
bitfld.long 0x14 11. "BRK1CMP2EN,BREAK1 CMP2 enable" "0,1"
bitfld.long 0x14 10. "BRK1CMP1EN,BREAK1 CMP1 enable" "0,1"
bitfld.long 0x14 9. "BRK1CMP0EN,BREAK1 CMP0 enable" "0,1"
bitfld.long 0x14 8. "BRK1HPDFEN,BREAK1 HPDF input enable" "0,1"
bitfld.long 0x14 7. "BRK1CMP7EN,BREAK1 CMP7 enable" "0,1"
bitfld.long 0x14 2. "BRK1IN2EN,BREAK1 BRKIN2 alternate function input enable" "0,1"
newline
bitfld.long 0x14 1. "BRK1IN1EN,BREAK1 BRKIN1 alternate function input enable" "0,1"
bitfld.long 0x14 0. "BRK1IN0EN,BREAK1 BRKIN0 alternate function input enable" "0,1"
line.long 0x18 "WDGPER,Watchdog counter period register"
hexmask.long 0x18 0.--31. 1. "WDGPER,Watchdog counter period value"
line.long 0x1C "CREP1,Counter repetition register 1"
hexmask.long 0x1C 0.--31. 1. "CREP1,Counter repetition value 1"
line.long 0x20 "CCHP1,Complementary channel protection register 1"
bitfld.long 0x20 17. "DTMODEN,Dead time modified on-the-fly enable" "0,1"
bitfld.long 0x20 16. "DTDIFEN,Dead time configure different enable" "0,1"
hexmask.long.byte 0x20 0.--7. 1. "DTFCFG,Dead time falling edge configure"
line.long 0x24 "DECCTL,Decoder control register"
bitfld.long 0x24 24.--26. "OPPSC,Output pulse prescaler" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x24 16.--23. 1. "OPWID,Output pulse width"
bitfld.long 0x24 6.--7. "INDP,Index positioning" "0,1,2,3"
bitfld.long 0x24 5. "FINDRST,First index signal reset the counter" "0,1"
bitfld.long 0x24 1.--2. "INDRSTDIR,Index signal reset counter direction" "0,1,2,3"
bitfld.long 0x24 0. "INDRSTEN,Index signal reset enable" "0,1"
line.long 0x28 "CINITCTL,Counter initial control register"
bitfld.long 0x28 2. "SWSYNCG,Soft synchronization event generation" "0,1"
bitfld.long 0x28 1. "CINITDIR,Counter initial count direction" "0,1"
bitfld.long 0x28 0. "CINITVEN,Counter initial value register enable" "0,1"
line.long 0x2C "CINITV,Counter initial value register"
hexmask.long.word 0x2C 0.--15. 1. "CINITVAL,Counter initial value"
group.long 0xE0++0x7
line.long 0x0 "DMACFG,DMA configuration register"
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
line.long 0x4 "DMATB,DMA transfer buffer register"
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
group.long 0xFC++0x3
line.long 0x0 "CFG,Configuration register"
bitfld.long 0x0 3. "CCUSEL,Commutation control shadow register update select" "0,1"
bitfld.long 0x0 2. "CREPSEL,The counter repetition register select" "0,1"
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection bit" "0,1"
bitfld.long 0x0 0. "OUTSEL,The output value selection bit" "0,1"
tree.end
tree "TIMER14 (General-L3 Timer)"
base ad:0x40014000
group.long 0x0++0x13
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 12. "ADMEN,Adjustment mode enable" "0,1"
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x0 2. "UPS,Update source" "0,1"
newline
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 30.--31. "CCUC,Commutation control shadow register update control" "0,1,2,3"
bitfld.long 0x4 10. "ISO1,Idle state of channel 1 output" "0,1"
bitfld.long 0x4 9. "ISO0N,Idle state of multi mode channel 0 complementary output" "0,1"
bitfld.long 0x4 8. "ISO0,Idle state of channel 0 output" "0,1"
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
newline
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
line.long 0x8 "SMCFG,Slave mode configuration register"
bitfld.long 0x8 26. "PRMRPSEL,Pause + restart mode reset polarity selection" "0,1"
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
bitfld.long 0xC 24. "MCH0DEN,Multi mode channel 0 capture/compare DMA request enable" "0,1"
bitfld.long 0xC 20. "MCH0IE,Multi mode channel 0 capture/compare interrupt enable" "0,1"
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
bitfld.long 0xC 13. "CMTDEN,Commutation DMA request enable" "0,1"
newline
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0xC 7. "BRKIE,Break interrupt enable" "0,1"
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
bitfld.long 0xC 5. "CMTIE,Commutation interrupt enable" "0,1"
newline
bitfld.long 0xC 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
bitfld.long 0xC 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
line.long 0x10 "INTF,Interrupt flag register"
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
bitfld.long 0x10 24. "MCH0OF,Multi mode channel 0 over capture flag" "0,1"
bitfld.long 0x10 20. "MCH0IF,Multi mode channel 0 capture/compare interrupt flag" "0,1"
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
newline
bitfld.long 0x10 7. "BRK0IF,BREAK0 interrupt flag" "0,1"
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
bitfld.long 0x10 5. "CMTIF,Channel commutation interrupt flag" "0,1"
bitfld.long 0x10 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
bitfld.long 0x10 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x3
line.long 0x0 "SWEVG,Software event generation register"
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
bitfld.long 0x0 20. "MCH0G,Multi mode channel 0 capture or compare event generation" "0,1"
bitfld.long 0x0 7. "BRK0G,BREAK0 event generation" "0,1"
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
bitfld.long 0x0 5. "CMTG,Channel commutation event generation" "0,1"
newline
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
group.long 0x18++0x3
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
bitfld.long 0x0 27. "CH1ADDUPS,Channel 1 additional update source" "0,1"
bitfld.long 0x0 26. "CH0ADDUPS,Channel 0 additional update source" "0,1"
newline
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 0 compare output control" "0,1"
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
bitfld.long 0x0 10. "CH1COMFEN,Channel 1 output compare fast enable" "0,1"
newline
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
bitfld.long 0x0 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x3
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input mode)"
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
bitfld.long 0x0 27. "CH1ADDUPS,Channel 1 additional update source" "0,1"
bitfld.long 0x0 26. "CH0ADDUPS,Channel 0 additional update source" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
group.long 0x20++0x1B
line.long 0x0 "CHCTL2,Channel control register 2"
bitfld.long 0x0 7. "MCH1P,Multi mode channel 1 output polarity" "0,1"
bitfld.long 0x0 5. "CH1P,Channel 1 capture/compare polarity" "0,1"
bitfld.long 0x0 4. "CH1EN,Channel 1 capture/compare enable" "0,1"
bitfld.long 0x0 3. "MCH0P,Multi mode channel 0 output polarity" "0,1"
bitfld.long 0x0 2. "MCH0EN,Multi mode channel 0 capture/compare enable" "0,1"
bitfld.long 0x0 1. "CH0P,Channel 0 capture/compare polarity" "0,1"
newline
bitfld.long 0x0 0. "CH0EN,Channel 0 capture/compare enable" "0,1"
line.long 0x4 "CNT,Counter register"
rbitfld.long 0x4 31. "UPIFBU,UPIF bit backup" "0,1"
hexmask.long.word 0x4 0.--15. 1. "CNT,This bit-field indicates the current counter value"
line.long 0x8 "PSC,Prescaler register"
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value of the counter clock"
line.long 0xC "CAR,Counter auto reload register"
hexmask.long.byte 0xC 28.--31. 1. "CARL16_19,Counter auto reload value (bit 16 to 19)"
hexmask.long.word 0xC 0.--15. 1. "CARL,Counter auto reload value"
line.long 0x10 "CREP0,Counter repetition register"
hexmask.long.byte 0x10 0.--7. 1. "CREP0,Counter repetition value 0"
line.long 0x14 "CH0CV,Channel 0 capture/compare value register"
hexmask.long.byte 0x14 28.--31. 1. "CH0VAL16_19,Capture/compare value of channel 0 (bit 16 to 19)"
hexmask.long.word 0x14 0.--15. 1. "CH0VAL,Capture/compare value of channel 0 (bit 0 to 15)"
line.long 0x18 "CH1CV,Channel 1 capture/compare value register"
hexmask.long.byte 0x18 28.--31. 1. "CH1VAL16_19,Capture/compare value of channel 1 (bit 16 to 19)"
hexmask.long.word 0x18 0.--15. 1. "CH1VAL,Capture/compare value of channel 1 (bit 0 to 15)"
group.long 0x44++0x7
line.long 0x0 "CCHP0,Complementary channel protection register 0"
bitfld.long 0x0 28. "BRK0LK,BREAK0 input locked" "0,1"
bitfld.long 0x0 26. "BRK0REL,BREAK0 input released" "0,1"
hexmask.long.byte 0x0 16.--19. 1. "BRK0F,BREAK0 input signal filter"
bitfld.long 0x0 15. "POEN,Primary output enable" "0,1"
bitfld.long 0x0 14. "OAEN,Output automatic enable" "0,1"
bitfld.long 0x0 13. "BRK0P,BREAK0 input signal polarity" "0,1"
newline
bitfld.long 0x0 12. "BRK0EN,BREAK0 input signal enable" "0,1"
bitfld.long 0x0 11. "ROS,Run mode off-state enable" "0,1"
bitfld.long 0x0 10. "IOS,Idle mode off-state enable" "0,1"
bitfld.long 0x0 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configuration"
line.long 0x4 "MCHCTL0_Output,Multi mode channel control register 0 (output mode)"
bitfld.long 0x4 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
bitfld.long 0x4 16. "MCH0COMCTL_3,Multi mode channel 0 compare output control(bit 3)" "0,1"
bitfld.long 0x4 7. "MCH0COMCEN,Multi mode channel 0 output compare clear enable" "0,1"
bitfld.long 0x4 4.--6. "MCH0COMCTL,Multi mode channel 0 output compare control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "MCH0COMSEN,Multi mode channel 0 output compare shadow enable" "0,1"
bitfld.long 0x4 2. "MCH0COMFEN,Multi mode channel 0 output compare fast enable" "0,1"
newline
bitfld.long 0x4 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
group.long 0x48++0x3
line.long 0x0 "MCHCTL0_Input,Multi mode channel control register 0 (input mode)"
bitfld.long 0x0 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "MCH0CAPFLT,Multi mode channel 0 input capture filter control"
bitfld.long 0x0 2.--3. "MCH0CAPPSC,Multi mode channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
group.long 0x50++0x7
line.long 0x0 "MCHCTL2,Multi mode channel control register 2"
bitfld.long 0x0 0.--1. "MCH0FP,Multi mode channel 0 capture/compare free polarity" "0,1,2,3"
line.long 0x4 "MCH0CV,Multi mode channel 0 capture/compare value register"
hexmask.long.word 0x4 0.--15. 1. "MCH0VAL,Capture/compare value of multi mode channel 0"
group.long 0x64++0x7
line.long 0x0 "CH0COMV_ADD,Channel 0 additional compare value register"
hexmask.long.word 0x0 0.--15. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
line.long 0x4 "CH1COMV_ADD,Channel 1 additional compare value register"
hexmask.long.word 0x4 0.--15. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
group.long 0x74++0x3
line.long 0x0 "CTL2,Control register 2"
bitfld.long 0x0 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
bitfld.long 0x0 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
bitfld.long 0x0 20.--21. "MCH0MSEL,Multi mode channel 0 mode select" "0,1,2,3"
bitfld.long 0x0 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
bitfld.long 0x0 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
group.long 0x8C++0x7
line.long 0x0 "AFCTL0,alternate function control register 0"
bitfld.long 0x0 28. "BRK0CMP3P,BREAK0 CMP3 input polarity" "0,1"
bitfld.long 0x0 27. "BRK0CMP2P,BREAK0 CMP2 input polarity" "0,1"
bitfld.long 0x0 26. "BRK0CMP1P,BREAK0 CMP1 input polarity" "0,1"
bitfld.long 0x0 25. "BRK0CMP0P,BREAK0 CMP0 input polarity" "0,1"
bitfld.long 0x0 16. "BRK0IN0P,BREAK0 BRKIN0 alternate function input polarity" "0,1"
bitfld.long 0x0 15. "BRK0CMP6EN,BREAK0 CMP6 enable" "0,1"
newline
bitfld.long 0x0 14. "BRK0CMP5EN,BREAK0 CMP5 enable" "0,1"
bitfld.long 0x0 13. "BRK0CMP4EN,BREAK0 CMP4 enable" "0,1"
bitfld.long 0x0 12. "BRK0CMP3EN,BREAK0 CMP3 enable" "0,1"
bitfld.long 0x0 11. "BRK0CMP2EN,BREAK0 CMP2 enable" "0,1"
bitfld.long 0x0 10. "BRK0CMP1EN,BREAK0 CMP1 enable" "0,1"
bitfld.long 0x0 9. "BRK0CMP0EN,BREAK0 CMP0 enable" "0,1"
newline
bitfld.long 0x0 8. "BRK0HPDFEN,BREAK0 HPDF input (HPDF_BREAK[0]) enable" "0,1"
bitfld.long 0x0 7. "BRK0CMP7EN,BREAK0 CMP7 enable" "0,1"
bitfld.long 0x0 0. "BRK0IN0EN,BREAK0 BRKIN0 alternate function input enable" "0,1"
line.long 0x4 "AFCTL1,alternate function control register 1"
bitfld.long 0x4 19.--21. "OCRINSEL,OCPRE_CLR inputs selection" "0,1,2,3,4,5,6,7"
group.long 0x98++0x7
line.long 0x0 "CREP1,Counter repetition register 1"
hexmask.long 0x0 0.--31. 1. "CREP1,Counter repetition value 1"
line.long 0x4 "CCHP1,Complementary channel protection register 1"
bitfld.long 0x4 17. "DTMODEN,Dead time modified on-the-fly enable" "0,1"
bitfld.long 0x4 16. "DTDIFEN,Dead time configure different enable" "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DTFCFG,Dead time falling edge configure"
group.long 0xE0++0x7
line.long 0x0 "DMACFG,DMA configuration register"
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
line.long 0x4 "DMATB,DMA transfer buffer register"
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
group.long 0xFC++0x3
line.long 0x0 "CFG,Configuration register"
bitfld.long 0x0 3. "CCUSEL,Commutation control shadow register update select" "0,1"
bitfld.long 0x0 2. "CREPSEL,The counter repetition register select" "0,1"
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection bit" "0,1"
bitfld.long 0x0 0. "OUTSEL,The output value selection bit" "0,1"
tree.end
tree "TIMER15 (General-L4 Timer)"
base ad:0x40014400
group.long 0x0++0x7
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 12. "ADMEN,Adjustment mode enable" "0,1"
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x0 2. "UPS,Update source" "0,1"
newline
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 30.--31. "CCUC,Commutation control shadow register update control" "0,1,2,3"
bitfld.long 0x4 9. "ISO0N,Idle state of multi mode channel 0 complementary output" "0,1"
bitfld.long 0x4 8. "ISO0,Idle state of channel 0 output" "0,1"
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
group.long 0xC++0x7
line.long 0x0 "DMAINTEN,DMA and interrupt enable register"
bitfld.long 0x0 24. "MCH0DEN,Multi mode channel 0 capture/compare DMA request enable" "0,1"
bitfld.long 0x0 20. "MCH0IE,Multi mode channel 0 capture/compare interrupt enable" "0,1"
bitfld.long 0x0 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
bitfld.long 0x0 8. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x0 7. "BRKIE,Break interrupt enable" "0,1"
bitfld.long 0x0 5. "CMTIE,Commutation interrupt enable" "0,1"
newline
bitfld.long 0x0 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
bitfld.long 0x0 0. "UPIE,Update interrupt enable" "0,1"
line.long 0x4 "INTF,Interrupt flag register"
bitfld.long 0x4 24. "MCH0OF,Multi mode channel 0 over capture flag" "0,1"
bitfld.long 0x4 20. "MCH0IF,Multi mode channel 0 capture/compare interrupt flag" "0,1"
bitfld.long 0x4 9. "CH0OF,Channel 0 over capture flag" "0,1"
bitfld.long 0x4 7. "BRK0IF,BREAK0 interrupt flag" "0,1"
bitfld.long 0x4 5. "CMTIF,Channel commutation interrupt flag" "0,1"
bitfld.long 0x4 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
newline
bitfld.long 0x4 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x3
line.long 0x0 "SWEVG,Software event generation register"
bitfld.long 0x0 20. "MCH0G,Multi mode channel 0 capture or compare event generation" "0,1"
bitfld.long 0x0 7. "BRK0G,BREAK0 event generation" "0,1"
bitfld.long 0x0 5. "CMTG,Channel commutation event generation" "0,1"
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
group.long 0x18++0x3
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x0 30. "CH0MS_2,bit2 of Channel 0 I/O mode selection" "0,1"
bitfld.long 0x0 16. "CH2COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
bitfld.long 0x0 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
newline
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x3
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input mode)"
bitfld.long 0x0 30. "CH0MS_2,bit 2 of Channel 0 I/O mode selection" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
group.long 0x20++0x17
line.long 0x0 "CHCTL2,Channel control register 2"
bitfld.long 0x0 3. "MCH0P,Multi mode channel 0 output polarity" "0,1"
bitfld.long 0x0 2. "MCH0EN,Multi mode channel 0 capture/compare enable" "0,1"
bitfld.long 0x0 1. "CH0P,Channel 0 capture/compare polarity" "0,1"
bitfld.long 0x0 0. "CH0EN,Channel 0 capture/compare enable" "0,1"
line.long 0x4 "CNT,>Counter register"
rbitfld.long 0x4 31. "UPIFBU,UPIF bit backup" "0,1"
hexmask.long.word 0x4 0.--15. 1. "CNT,This bit-field indicates the current counter value"
line.long 0x8 "PSC,Prescaler register"
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value of the counter clock"
line.long 0xC "CAR,Counter auto reload register"
hexmask.long.byte 0xC 28.--31. 1. "CARL_16_19,Counter auto reload value(bit 16 to 19)"
hexmask.long.word 0xC 0.--15. 1. "CARL,Counter auto reload value (bit 0 to 15)"
line.long 0x10 "CREP0,Counter repetition register 0"
hexmask.long.byte 0x10 0.--7. 1. "CREP0,Counter repetition value 0"
line.long 0x14 "CH0CV,Channel 0 capture/compare value register"
hexmask.long.byte 0x14 28.--31. 1. "CH0VAL_16_19,Capture / compare value of channel0(bit 16 to 19)"
hexmask.long.word 0x14 0.--15. 1. "CH0VAL,Capture/compare value of channel 0 (bit 0 to 15)"
group.long 0x44++0x7
line.long 0x0 "CCHP0,Complementary channel protection register 0"
bitfld.long 0x0 28. "BRK0LK,BREAK0 input locked" "0,1"
bitfld.long 0x0 26. "BRK0REL,BREAK0 input released" "0,1"
hexmask.long.byte 0x0 16.--19. 1. "BRK0F,BREAK0 input signal filter"
bitfld.long 0x0 15. "POEN,Primary output enable" "0,1"
bitfld.long 0x0 14. "OAEN,Output automatic enable" "0,1"
bitfld.long 0x0 13. "BRK0P,BREAK0 input signal polarity" "0,1"
newline
bitfld.long 0x0 12. "BRK0EN,BREAK0 input signal enable" "0,1"
bitfld.long 0x0 11. "ROS,Run mode off-state enable" "0,1"
bitfld.long 0x0 10. "IOS,Idle mode off-state enable" "0,1"
bitfld.long 0x0 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configuration"
line.long 0x4 "MCHCTL0_Output,Multi mode channel control register 0 (output mode)"
bitfld.long 0x4 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
bitfld.long 0x4 16. "MCH0COMCTL_3,Multi mode channel 0 compare output control." "0,1"
bitfld.long 0x4 7. "MCH0COMCEN,Multi mode channel 0 output compare clear enable" "0,1"
bitfld.long 0x4 4.--6. "MCH0COMCTL,Multi mode channel 0 output compare control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "MCH0COMSEN,Multi mode channel 0 output compare shadow enable" "0,1"
bitfld.long 0x4 2. "MCH0COMFEN,Multi mode channel 0 output compare fast enable" "0,1"
newline
bitfld.long 0x4 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
group.long 0x48++0x3
line.long 0x0 "MCHCTL0_Input,Multi mode channel control register 0 (input mode)"
bitfld.long 0x0 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection(bit2)" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "MCH0CAPFLT,Multi mode channel 0 input capture filter control"
bitfld.long 0x0 2.--3. "MCH0CAPPSC,Multi mode channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
group.long 0x50++0x7
line.long 0x0 "MCHCTL2,Multi mode channel control register 2"
bitfld.long 0x0 0.--1. "MCH0FP,Multi mode channel 0 capture/compare free polarity" "0,1,2,3"
line.long 0x4 "MCH0CV,Multi mode channel 0 capture/compare value register"
hexmask.long.word 0x4 0.--15. 1. "MCH0VAL,Capture/compare value of multi mode channel 0"
group.long 0x74++0x3
line.long 0x0 "CTL2,Control register 2"
bitfld.long 0x0 20.--21. "MCH0MSEL,Multi mode channel 0 mode select" "0,1,2,3"
group.long 0x8C++0x7
line.long 0x0 "AFCTL0,alternate function control register 0"
bitfld.long 0x0 28. "BRK0CMP3P,BREAK0 CMP3 input polarity" "0,1"
bitfld.long 0x0 27. "BRK0CMP2P,BREAK0 CMP2 input polarity" "0,1"
bitfld.long 0x0 26. "BRK0CMP1P,BREAK0 CMP1 input polarity" "0,1"
bitfld.long 0x0 25. "BRK0CMP0P,BREAK0 CMP0 input polarity" "0,1"
bitfld.long 0x0 16. "BRK0IN0P,BREAK0 BRKIN0 alternate function input polarity" "0,1"
bitfld.long 0x0 15. "BRK0CMP6EN,BREAK0 CMP6 enable" "0,1"
newline
bitfld.long 0x0 14. "BRK0CMP5EN,BREAK0 CMP5 enable" "0,1"
bitfld.long 0x0 13. "BRK0CMP4EN,BREAK0 CMP4 enable" "0,1"
bitfld.long 0x0 12. "BRK0CMP3EN,BREAK0 CMP3 enable" "0,1"
bitfld.long 0x0 11. "BRK0CMP2EN,BREAK0 CMP2 enable" "0,1"
bitfld.long 0x0 10. "BRK0CMP1EN,BREAK0 CMP1 enable" "0,1"
bitfld.long 0x0 9. "BRK0CMP0EN,BREAK0 CMP0 enable" "0,1"
newline
bitfld.long 0x0 8. "BRK0HPDFEN,BREAK0 HPDF input" "0,1"
bitfld.long 0x0 7. "BRK0CMP7EN,BREAK0 CMP7 enable" "0,1"
bitfld.long 0x0 0. "BRK0IN0EN,BREAK0 BRKIN0 alternate function input enable" "0,1"
line.long 0x4 "AFCTL1,alternate function control register 1"
bitfld.long 0x4 19.--21. "OCRINSEL,OCPRE_CLR inputs selection" "0,1,2,3,4,5,6,7"
group.long 0x98++0x7
line.long 0x0 "CREP1,Counter repetition register 1"
hexmask.long 0x0 0.--31. 1. "CREP1,Counter repetition value 1"
line.long 0x4 "CCHP1,Complementary channel protection register 1"
bitfld.long 0x4 17. "DTMODEN,Dead time modified on-the-fly enable" "0,1"
bitfld.long 0x4 16. "DTDIFEN,Dead time configure different enable" "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DTFCFG,Dead time falling edge configure"
group.long 0xE0++0x7
line.long 0x0 "DMACFG,DMA configuration register"
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
line.long 0x4 "DMATB,DMA transfer buffer register"
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
group.long 0xFC++0x3
line.long 0x0 "CFG,Configuration register"
bitfld.long 0x0 3. "CCUSEL,Commutation control shadow register update select" "0,1"
bitfld.long 0x0 2. "CREPSEL,The counter repetition register select" "0,1"
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection bit" "0,1"
bitfld.long 0x0 0. "OUTSEL,The output value selection bit" "0,1"
tree.end
tree "TIMER16 (General-L4 Timer)"
base ad:0x40014800
group.long 0x0++0x7
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 12. "ADMEN,Adjustment mode enable" "0,1"
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x0 2. "UPS,Update source" "0,1"
newline
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 30.--31. "CCUC,Commutation control shadow register update control" "0,1,2,3"
bitfld.long 0x4 9. "ISO0N,Idle state of multi mode channel 0 complementary output" "0,1"
bitfld.long 0x4 8. "ISO0,Idle state of channel 0 output" "0,1"
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
bitfld.long 0x4 2. "CCUC_0,Commutation control shadow register update control" "0,1"
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
group.long 0xC++0x7
line.long 0x0 "DMAINTEN,DMA and interrupt enable register"
bitfld.long 0x0 24. "MCH0DEN,Multi mode channel 0 capture/compare DMA request enable" "0,1"
bitfld.long 0x0 20. "MCH0IE,Multi mode channel 0 capture/compare interrupt enable" "0,1"
bitfld.long 0x0 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
bitfld.long 0x0 8. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x0 7. "BRKIE,Break interrupt enable" "0,1"
bitfld.long 0x0 5. "CMTIE,Commutation interrupt enable" "0,1"
newline
bitfld.long 0x0 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
bitfld.long 0x0 0. "UPIE,Update interrupt enable" "0,1"
line.long 0x4 "INTF,Interrupt flag register"
bitfld.long 0x4 24. "MCH0OF,Multi mode channel 0 over capture flag" "0,1"
bitfld.long 0x4 20. "MCH0IF,Multi mode channel 0 capture/compare interrupt flag" "0,1"
bitfld.long 0x4 9. "CH0OF,Channel 0 over capture flag" "0,1"
bitfld.long 0x4 7. "BRK0IF,BREAK0 interrupt flag" "0,1"
bitfld.long 0x4 5. "CMTIF,Channel commutation interrupt flag" "0,1"
bitfld.long 0x4 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
newline
bitfld.long 0x4 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x3
line.long 0x0 "SWEVG,Software event generation register"
bitfld.long 0x0 20. "MCH0G,Multi mode channel 0 capture or compare event generation" "0,1"
bitfld.long 0x0 7. "BRK0G,BREAK0 event generation" "0,1"
bitfld.long 0x0 5. "CMTG,Channel commutation event generation" "0,1"
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
group.long 0x18++0x3
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x0 30. "CH0MS_2,bit2 of Channel 0 I/O mode selection" "0,1"
bitfld.long 0x0 16. "CH2COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
bitfld.long 0x0 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
newline
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x3
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input mode)"
bitfld.long 0x0 30. "CH0MS_2,bit 2 of Channel 0 I/O mode selection" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
group.long 0x20++0x17
line.long 0x0 "CHCTL2,Channel control register 2"
bitfld.long 0x0 3. "MCH0P,Multi mode channel 0 output polarity" "0,1"
bitfld.long 0x0 2. "MCH0EN,Multi mode channel 0 capture/compare enable" "0,1"
bitfld.long 0x0 1. "CH0P,Channel 0 capture/compare polarity" "0,1"
bitfld.long 0x0 0. "CH0EN,Channel 0 capture/compare enable" "0,1"
line.long 0x4 "CNT,>Counter register"
rbitfld.long 0x4 31. "UPIFBU,UPIF bit backup" "0,1"
hexmask.long.word 0x4 0.--15. 1. "CNT,This bit-field indicates the current counter value"
line.long 0x8 "PSC,Prescaler register"
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value of the counter clock"
line.long 0xC "CAR,Counter auto reload register"
hexmask.long.byte 0xC 28.--31. 1. "CARL_16_19,Counter auto reload value(bit 16 to 19)"
hexmask.long.word 0xC 0.--15. 1. "CARL,Counter auto reload value (bit 0 to 15)"
line.long 0x10 "CREP0,Counter repetition register 0"
hexmask.long.byte 0x10 0.--7. 1. "CREP0,Counter repetition value 0"
line.long 0x14 "CH0CV,Channel 0 capture/compare value register"
hexmask.long.byte 0x14 28.--31. 1. "CH0VAL_16_19,Capture / compare value of channel0(bit 16 to 19)"
hexmask.long.word 0x14 0.--15. 1. "CH0VAL,Capture/compare value of channel 0 (bit 0 to 15)"
group.long 0x44++0x7
line.long 0x0 "CCHP0,Complementary channel protection register 0"
bitfld.long 0x0 28. "BRK0LK,BREAK0 input locked" "0,1"
bitfld.long 0x0 26. "BRK0REL,BREAK0 input released" "0,1"
hexmask.long.byte 0x0 16.--19. 1. "BRK0F,BREAK0 input signal filter"
bitfld.long 0x0 15. "POEN,Primary output enable" "0,1"
bitfld.long 0x0 14. "OAEN,Output automatic enable" "0,1"
bitfld.long 0x0 13. "BRK0P,BREAK0 input signal polarity" "0,1"
newline
bitfld.long 0x0 12. "BRK0EN,BREAK0 input signal enable" "0,1"
bitfld.long 0x0 11. "ROS,Run mode off-state enable" "0,1"
bitfld.long 0x0 10. "IOS,Idle mode off-state enable" "0,1"
bitfld.long 0x0 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configuration"
line.long 0x4 "MCHCTL0_Output,Multi mode channel control register 0 (output mode)"
bitfld.long 0x4 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
bitfld.long 0x4 16. "MCH0COMCTL_3,Multi mode channel 0 compare output control." "0,1"
bitfld.long 0x4 7. "MCH0COMCEN,Multi mode channel 0 output compare clear enable" "0,1"
bitfld.long 0x4 4.--6. "MCH0COMCTL,Multi mode channel 0 output compare control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "MCH0COMSEN,Multi mode channel 0 output compare shadow enable" "0,1"
bitfld.long 0x4 2. "MCH0COMFEN,Multi mode channel 0 output compare fast enable" "0,1"
newline
bitfld.long 0x4 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
group.long 0x48++0x3
line.long 0x0 "MCHCTL0_Input,Multi mode channel control register 0 (input mode)"
bitfld.long 0x0 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection(bit2)" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "MCH0CAPFLT,Multi mode channel 0 input capture filter control"
bitfld.long 0x0 2.--3. "MCH0CAPPSC,Multi mode channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
group.long 0x50++0x7
line.long 0x0 "MCHCTL2,Multi mode channel control register 2"
bitfld.long 0x0 0.--1. "MCH0FP,Multi mode channel 0 capture/compare free polarity" "0,1,2,3"
line.long 0x4 "MCH0CV,Multi mode channel 0 capture/compare value register"
hexmask.long.word 0x4 0.--15. 1. "MCH0VAL,Capture/compare value of multi mode channel 0"
group.long 0x74++0x3
line.long 0x0 "CTL2,Control register 2"
bitfld.long 0x0 20.--21. "MCH0MSEL,Multi mode channel 0 mode select" "0,1,2,3"
group.long 0x8C++0x7
line.long 0x0 "AFCTL0,alternate function control register 0"
bitfld.long 0x0 28. "BRK0CMP3P,BREAK0 CMP3 input polarity" "0,1"
bitfld.long 0x0 27. "BRK0CMP2P,BREAK0 CMP2 input polarity" "0,1"
bitfld.long 0x0 26. "BRK0CMP1P,BREAK0 CMP1 input polarity" "0,1"
bitfld.long 0x0 25. "BRK0CMP0P,BREAK0 CMP0 input polarity" "0,1"
bitfld.long 0x0 16. "BRK0IN0P,BREAK0 BRKIN0 alternate function input polarity" "0,1"
bitfld.long 0x0 15. "BRK0CMP6EN,BREAK0 CMP6 enable" "0,1"
newline
bitfld.long 0x0 14. "BRK0CMP5EN,BREAK0 CMP5 enable" "0,1"
bitfld.long 0x0 13. "BRK0CMP4EN,BREAK0 CMP4 enable" "0,1"
bitfld.long 0x0 12. "BRK0CMP3EN,BREAK0 CMP3 enable" "0,1"
bitfld.long 0x0 11. "BRK0CMP2EN,BREAK0 CMP2 enable" "0,1"
bitfld.long 0x0 10. "BRK0CMP1EN,BREAK0 CMP1 enable" "0,1"
bitfld.long 0x0 9. "BRK0CMP0EN,BREAK0 CMP0 enable" "0,1"
newline
bitfld.long 0x0 8. "BRK0HPDFEN,BREAK0 HPDF input" "0,1"
bitfld.long 0x0 7. "BRK0CMP7EN,BREAK0 CMP7 enable" "0,1"
bitfld.long 0x0 0. "BRK0IN0EN,BREAK0 BRKIN0 alternate function input enable" "0,1"
line.long 0x4 "AFCTL1,alternate function control register 1"
bitfld.long 0x4 19.--21. "OCRINSEL,OCPRE_CLR inputs selection" "0,1,2,3,4,5,6,7"
group.long 0x98++0x7
line.long 0x0 "CREP1,Counter repetition register 1"
hexmask.long 0x0 0.--31. 1. "CREP1,Counter repetition value 1"
line.long 0x4 "CCHP1,Complementary channel protection register 1"
bitfld.long 0x4 17. "DTMODEN,Dead time modified on-the-fly enable" "0,1"
bitfld.long 0x4 16. "DTDIFEN,Dead time configure different enable" "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DTFCFG,Dead time falling edge configure"
group.long 0xE0++0x7
line.long 0x0 "DMACFG,DMA configuration register"
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
line.long 0x4 "DMATB,DMA transfer buffer register"
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
group.long 0xFC++0x3
line.long 0x0 "CFG,Configuration register"
bitfld.long 0x0 3. "CCUSEL,Commutation control shadow register update select" "0,1"
bitfld.long 0x0 2. "CREPSEL,The counter repetition register select" "0,1"
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection bit" "0,1"
bitfld.long 0x0 0. "OUTSEL,The output value selection bit" "0,1"
tree.end
tree "TIMER19 (Advanced Timer)"
base ad:0x40015000
group.long 0x0++0x13
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 12. "ADMEN,Adjustment mode enable" "0,1"
bitfld.long 0x0 11. "UPIFBUEN,UPIF bit backup enable" "0,1"
bitfld.long 0x0 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x0 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x0 5.--6. "CAM,Counter align mode selection" "0,1,2,3"
bitfld.long 0x0 4. "DIR,Direction" "0,1"
newline
bitfld.long 0x0 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x0 2. "UPS,Update source" "0,1"
bitfld.long 0x0 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
bitfld.long 0x4 30.--31. "CCUC1_2,Commutation control shadow register update control" "0,1,2,3"
bitfld.long 0x4 25. "MMC0_3,Master mode control 0" "0,1"
bitfld.long 0x4 20.--22. "MMC1,Master mode control 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 15. "ISO3N,Idle state of multi mode channel 3 complementary output" "0,1"
bitfld.long 0x4 14. "ISO3,Idle state of channel 3 output" "0,1"
bitfld.long 0x4 13. "ISO2N,Idle state of multi mode channel 2 complementary output" "0,1"
newline
bitfld.long 0x4 12. "ISO2,Idle state of channel 2 output" "0,1"
bitfld.long 0x4 11. "ISO1N,Idle state of multi mode channel 1 complementary output" "0,1"
bitfld.long 0x4 10. "ISO1,Idle state of channel 1 output" "0,1"
bitfld.long 0x4 9. "ISO0N,Idle state of multi mode channel 0 complementary output" "0,1"
bitfld.long 0x4 8. "ISO0,Idle state of channel 0 output" "0,1"
bitfld.long 0x4 7. "TI0S,Channel 0 trigger input selection" "0,1"
newline
bitfld.long 0x4 4.--6. "MMC0,Master mode control 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "DMAS,DMA request source selection" "0,1"
bitfld.long 0x4 2. "CCUC,Commutation control shadow register update control" "0,1"
bitfld.long 0x4 0. "CCSE,Commutation control shadow enable" "0,1"
line.long 0x8 "SMCFG,Slave mode configuration register"
bitfld.long 0x8 26. "PRMRPSEL,Pause + restart mode reset polarity selection" "0,1"
bitfld.long 0x8 25. "DECMODS,Decoder mode update source" "0,1"
bitfld.long 0x8 24. "DECMODEN,Decoder mode modified on-the-fly enable" "0,1"
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
bitfld.long 0x8 14. "SMC1,Part of slave mode controller is used to enable external clock mode 1" "0,1"
bitfld.long 0x8 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
newline
hexmask.long.byte 0x8 8.--11. 1. "ETFC,External trigger filter control"
bitfld.long 0x8 7. "MSM,Master-slave mode" "0,1"
bitfld.long 0x8 3. "OCRC,OxCPRE / MOxCPRE clear source selection" "0,1"
line.long 0xC "DMAINTEN,DMA and interrupt enable register"
bitfld.long 0xC 31. "CH3COMADDIE,Channel 3 additional compare interrupt enable" "0,1"
bitfld.long 0xC 30. "CH2COMADDIE,Channel 2 additional compare interrupt enable" "0,1"
bitfld.long 0xC 29. "CH1COMADDIE,Channel 1 additional compare interrupt enable" "0,1"
bitfld.long 0xC 28. "CH0COMADDIE,Channel 0 additional compare interrupt enable" "0,1"
bitfld.long 0xC 27. "MCH3DEN,Multi mode channel 3 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 26. "MCH2DEN,Multi mode channel 2 capture / compare DMA request enable" "0,1"
newline
bitfld.long 0xC 25. "MCH1DEN,Multi mode channel 1 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 24. "MCH0DEN,Multi mode channel 0 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 23. "MCH3IE,Multi mode channel 3 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 22. "MCH2IE,Multi mode channel 2 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 21. "MCH1IE,Multi mode channel 1 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 20. "MCH0IE,Multi mode channel 0 capture / compare interrupt enable" "0,1"
newline
bitfld.long 0xC 19. "INDERRIE,Index error interrupt enable" "0,1"
bitfld.long 0xC 18. "DIRTRANIE,Direction transform interrupt enable" "0,1"
bitfld.long 0xC 17. "DECDISIE,Quadrature decoder signal disconnection interrupt enable" "0,1"
bitfld.long 0xC 16. "DECJIE,Quadrature decoder signal jump (the two signals jump at the same time) interrupt enable" "0,1"
bitfld.long 0xC 15. "INDIE,Index interrupt enable" "0,1"
bitfld.long 0xC 14. "TRGDEN,Trigger DMA request enable" "0,1"
newline
bitfld.long 0xC 13. "CMTDEN,Commutation DMA request enable" "0,1"
bitfld.long 0xC 12. "CH3DEN,Channel 3 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 11. "CH2DEN,Channel 2 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 10. "CH1DEN,Channel 1 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 9. "CH0DEN,Channel 0 capture / compare DMA request enable" "0,1"
bitfld.long 0xC 8. "UPDEN,Update DMA request enable" "0,1"
newline
bitfld.long 0xC 7. "BRKIE,Break interrupt enable" "0,1"
bitfld.long 0xC 6. "TRGIE,Trigger interrupt enable" "0,1"
bitfld.long 0xC 5. "CMTIE,Commutation interrupt enable" "0,1"
bitfld.long 0xC 4. "CH3IE,Channel 3 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 3. "CH2IE,Channel 2 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 2. "CH1IE,Channel 1 capture / compare interrupt enable" "0,1"
newline
bitfld.long 0xC 1. "CH0IE,Channel 0 capture / compare interrupt enable" "0,1"
bitfld.long 0xC 0. "UPIE,Update interrupt enable" "0,1"
line.long 0x10 "INTF,Interrupt flag register"
bitfld.long 0x10 31. "CH3COMADDIF,Channel 3 additional compare interrupt flag" "0,1"
bitfld.long 0x10 30. "CH2COMADDIF,Channel 2 additional compare interrupt flag" "0,1"
bitfld.long 0x10 29. "CH1COMADDIF,Channel 1 additional compare interrupt flag" "0,1"
bitfld.long 0x10 28. "CH0COMADDIF,Channel 0 additional compare interrupt flag" "0,1"
bitfld.long 0x10 27. "MCH3OF,Multi mode channel 3 over capture flag" "0,1"
bitfld.long 0x10 26. "MCH2OF,Multi mode channel 2 over capture flag" "0,1"
newline
bitfld.long 0x10 25. "MCH1OF,Multi mode channel 1 over capture flag" "0,1"
bitfld.long 0x10 24. "MCH0OF,Multi mode channel 0 over capture flag" "0,1"
bitfld.long 0x10 23. "MCH3IF,Multi mode channel 3 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 22. "MCH2IF,Multi mode channel 2 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 21. "MCH1IF,Multi mode channel 1 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 20. "MCH0IF,Multi mode channel 0 capture / compare interrupt flag" "0,1"
newline
bitfld.long 0x10 19. "INDERRIF,Index error interrupt flag" "0,1"
bitfld.long 0x10 18. "DIRTRANIF,Direction transform interrupt flag" "0,1"
bitfld.long 0x10 17. "DECDISIF,Quadrature decoder signal disconnection interrupt flag" "0,1"
bitfld.long 0x10 16. "DECJIF,Quadrature decoder signal jump (the two signals jump at the same time) interrupt flag" "0,1"
bitfld.long 0x10 15. "INDIF,Index interrupt flag" "0,1"
bitfld.long 0x10 13. "SYSBIF,System source break interrupt flag" "0,1"
newline
bitfld.long 0x10 12. "CH3OF,Channel 3 over capture flag" "0,1"
bitfld.long 0x10 11. "CH2OF,Channel 2 over capture flag" "0,1"
bitfld.long 0x10 10. "CH1OF,Channel 1 over capture flag" "0,1"
bitfld.long 0x10 9. "CH0OF,Channel 0 over capture flag" "0,1"
bitfld.long 0x10 8. "BRK1IF,BREAK1 interrupt flag" "0,1"
bitfld.long 0x10 7. "BRK0IF,BREAK0 interrupt flag" "0,1"
newline
bitfld.long 0x10 6. "TRGIF,Trigger interrupt flag" "0,1"
bitfld.long 0x10 5. "CMTIF,Channel commutation interrupt flag" "0,1"
bitfld.long 0x10 4. "CH3IF,Channel 3 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 3. "CH2IF,Channel 2 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 2. "CH1IF,Channel 1 capture / compare interrupt flag" "0,1"
bitfld.long 0x10 1. "CH0IF,Channel 0 capture / compare interrupt flag" "0,1"
newline
bitfld.long 0x10 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x3
line.long 0x0 "SWEVG,Software event generation register"
bitfld.long 0x0 31. "CH3COMADDG,Channel 3 additional compare event generation" "0,1"
bitfld.long 0x0 30. "CH2COMADDG,Channel 2 additional compare event generation" "0,1"
bitfld.long 0x0 29. "CH1COMADDG,Channel 1 additional compare event generation" "0,1"
bitfld.long 0x0 28. "CH0COMADDG,Channel 0 additional compare event generation" "0,1"
bitfld.long 0x0 23. "MCH3G,Multi mode channel 3 capture or compare event generation" "0,1"
bitfld.long 0x0 22. "MCH2G,Multi mode channel 2 capture or compare event generation" "0,1"
newline
bitfld.long 0x0 21. "MCH1G,Multi mode channel 1 capture or compare event generation" "0,1"
bitfld.long 0x0 20. "MCH0G,Multi mode channel 0 capture or compare event generation" "0,1"
bitfld.long 0x0 8. "BRK1G,BREAK1 event generation" "0,1"
bitfld.long 0x0 7. "BRK0G,BREAK0 event generation" "0,1"
bitfld.long 0x0 6. "TRGG,Trigger event generation" "0,1"
bitfld.long 0x0 5. "CMTG,Channel commutation event generation" "0,1"
newline
bitfld.long 0x0 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
bitfld.long 0x0 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
bitfld.long 0x0 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
bitfld.long 0x0 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x0 0. "UPG,Update event generation" "0,1"
group.long 0x18++0x3
line.long 0x0 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
bitfld.long 0x0 29. "CH1COMADDSEN,Channel 1 additional compare output shadow enable" "0,1"
bitfld.long 0x0 28. "CH0COMADDSEN,Channel 0 additional compare output shadow enable" "0,1"
bitfld.long 0x0 27. "CH1ADDUPS,Channel 1 additional update source" "0,1"
bitfld.long 0x0 26. "CH0ADDUPS,Channel 0 additional update source" "0,1"
newline
bitfld.long 0x0 24. "CH1COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
bitfld.long 0x0 16. "CH0COMCTL_3,Bit 3 of channel 1 compare output control" "0,1"
bitfld.long 0x0 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
bitfld.long 0x0 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
bitfld.long 0x0 10. "CH1COMFEN,Channel 1 output compare fast enable" "0,1"
newline
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x0 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
bitfld.long 0x0 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
bitfld.long 0x0 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x7
line.long 0x0 "CHCTL0_Input,Channel control register 0 (input mode)"
bitfld.long 0x0 31. "CH1MS_2,2th bit of CH1MS" "0,1"
bitfld.long 0x0 30. "CH0MS_2,2th bit of CH0MS" "0,1"
bitfld.long 0x0 27. "CH1ADDUPS,Channel 1 additional update source" "0,1"
bitfld.long 0x0 26. "CH0ADDUPS,Channel 0 additional update source" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "CH1CAPFLT,Channel 1 input capture filter control"
bitfld.long 0x0 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "CH0CAPFLT,Channel 0 input capture filter control"
bitfld.long 0x0 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
line.long 0x4 "CHCTL1_Output,Channel control register 1 (output mode)"
bitfld.long 0x4 31. "CH3MS_2,2th bit of CH3MS" "0,1"
bitfld.long 0x4 30. "CH2MS_2,2th bit of CH2MS" "0,1"
bitfld.long 0x4 29. "CH3COMADDSEN,Channel 3 additional compare output shadow enable" "0,1"
bitfld.long 0x4 28. "CH2COMADDSEN,Channel 2 additional compare output shadow enable" "0,1"
bitfld.long 0x4 27. "CH3ADDUPS,Channel 3 additional update source" "0,1"
bitfld.long 0x4 26. "CH2ADDUPS,Channel 2 additional update source" "0,1"
newline
bitfld.long 0x4 24. "CH3COMCTL_3,BIT 3 of channel 3 compare output control" "0,1"
bitfld.long 0x4 16. "CH2COMCTL_3,BIT 3 of channel 2 compare output control" "0,1"
bitfld.long 0x4 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
bitfld.long 0x4 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
bitfld.long 0x4 10. "CH3COMFEN,Channel 3 output compare fast enable" "0,1"
newline
bitfld.long 0x4 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
bitfld.long 0x4 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
bitfld.long 0x4 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
bitfld.long 0x4 2. "CH2COMFEN,Channel 2 output compare fast enable" "0,1"
bitfld.long 0x4 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
group.long 0x1C++0x2F
line.long 0x0 "CHCTL1_Input,Channel control register 1 (input mode)"
bitfld.long 0x0 31. "CH3MS_2,2th bit of CH3MS" "0,1"
bitfld.long 0x0 30. "CH2MS_2,2th bit of CH2MS" "0,1"
bitfld.long 0x0 27. "CH3ADDUPS,Channel 3 additional update source" "0,1"
bitfld.long 0x0 26. "CH2ADDUPS,Channel 2 additional update source" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "CH3CAPFLT,Channel 3 input capture filter control"
bitfld.long 0x0 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "CH2CAPFLT,Channel 2 input capture filter control"
bitfld.long 0x0 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
line.long 0x4 "CHCTL2,Channel control register 2"
bitfld.long 0x4 15. "MCH3P,Multi mode channel 3 capture / compare polarity" "0,1"
bitfld.long 0x4 14. "MCH3EN,Multi mode channel 3 capture / compare enable" "0,1"
bitfld.long 0x4 13. "CH3P,Channel 3 capture / compare polarity" "0,1"
bitfld.long 0x4 12. "CH3EN,Channel 3 capture / compare enable" "0,1"
bitfld.long 0x4 11. "MCH2P,Multi mode channel 2 output polarity" "0,1"
bitfld.long 0x4 10. "MCH2EN,Multi mode channel 2 output enable" "0,1"
newline
bitfld.long 0x4 9. "CH2P,Channel 2 capture / compare polarity" "0,1"
bitfld.long 0x4 8. "CH2EN,Channel 2 capture / compare enable" "0,1"
bitfld.long 0x4 7. "MCH1P,Multi mode channel 1 output polarity" "0,1"
bitfld.long 0x4 6. "MCH1EN,Multi mode channel 1 output enable" "0,1"
bitfld.long 0x4 5. "CH1P,Channel 1 capture / compare polarity" "0,1"
bitfld.long 0x4 4. "CH1EN,Channel 1 capture / compare enable" "0,1"
newline
bitfld.long 0x4 3. "MCH0P,Multi mode channel 0 output polarity" "0,1"
bitfld.long 0x4 2. "MCH0EN,Multi mode channel 0 capture / compare enable" "0,1"
bitfld.long 0x4 1. "CH0P,Channel 0 capture / compare polarity" "0,1"
bitfld.long 0x4 0. "CH0EN,Channel 0 capture / compare enable" "0,1"
line.long 0x8 "CNT,Counter register"
rbitfld.long 0x8 31. "UPIFBU,UPIF bit backup" "0,1"
hexmask.long.word 0x8 0.--15. 1. "CNT,This bit-field indicates the current counter value"
line.long 0xC "PSC,Prescaler register"
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value of the counter clock"
line.long 0x10 "CAR,Counter auto reload register"
hexmask.long.byte 0x10 28.--31. 1. "CARL16_19,Counter auto reload value(bit 16 to 19)"
hexmask.long.word 0x10 0.--15. 1. "CARL,Counter auto reload value (bit 0 to 15)"
line.long 0x14 "CREP0,Counter repetition register 0"
hexmask.long.byte 0x14 0.--7. 1. "CREP0,Counter repetition value 0"
line.long 0x18 "CH0CV,Channel 0 capture/compare value register"
hexmask.long.byte 0x18 28.--31. 1. "CH0VAL16_19,Capture / compare value of channel0 (bit 16 to 19)"
hexmask.long.word 0x18 0.--15. 1. "CH0VAL,Capture / compare value of channel 0"
line.long 0x1C "CH1CV,Channel 1 capture/compare value register"
hexmask.long.byte 0x1C 28.--31. 1. "CH1VAL16_19,Capture / compare value of channel1 (bit 16 to 19)"
hexmask.long.word 0x1C 0.--15. 1. "CH1VAL,Capture / compare value of channel 1 (bit 0 to 15)"
line.long 0x20 "CH2CV,Channel 2 capture/compare value register"
hexmask.long.byte 0x20 28.--31. 1. "CH2VAL16_19,Capture / compare value of channel 2 (bit 16 to 19)"
hexmask.long.word 0x20 0.--15. 1. "CH2VAL,Capture or compare value of channel 2"
line.long 0x24 "CH3CV,Channel 3 capture/compare value register"
hexmask.long.byte 0x24 28.--31. 1. "CH3VAL16_19,Capture / compare value of channel 3 (bit 16 to 19)"
hexmask.long.word 0x24 0.--15. 1. "CH3VAL,Capture / compare value of channel 3 (bit 0 to 15)"
line.long 0x28 "CCHP0,Complementary channel protection register 0"
bitfld.long 0x28 29. "BRK1LK,BREAK1 input locked" "0,1"
bitfld.long 0x28 28. "BRK0LK,BREAK0 input locked" "0,1"
bitfld.long 0x28 27. "BRK1REL,BREAK1 input released" "0,1"
bitfld.long 0x28 26. "BRK0REL,BREAK0 input released" "0,1"
bitfld.long 0x28 25. "BRK1P,BREAK1 input signal polarity" "0,1"
bitfld.long 0x28 24. "BRK1EN,BREAK1 input signal enable" "0,1"
newline
hexmask.long.byte 0x28 20.--23. 1. "BRK1F,BREAK1 input signal filter"
hexmask.long.byte 0x28 16.--19. 1. "BRK0F,BREAK0 input signal filter"
bitfld.long 0x28 15. "POEN,Primary output enable" "0,1"
bitfld.long 0x28 14. "OAEN,Output automatic enable" "0,1"
bitfld.long 0x28 13. "BRK0P,BREAK0 input signal polarity" "0,1"
bitfld.long 0x28 12. "BRK0EN,BREAK0 input signal enable" "0,1"
newline
bitfld.long 0x28 11. "ROS,Run mode off-state enable" "0,1"
bitfld.long 0x28 10. "IOS,Idle mode off-state enable" "0,1"
bitfld.long 0x28 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
hexmask.long.byte 0x28 0.--7. 1. "DTCFG,Dead time configuration"
line.long 0x2C "MCHCTL0_Output,Multi mode channel control register 0 (output mode)"
bitfld.long 0x2C 31. "MCH1MS_2,Multi mode channel 1 I/O mode selection" "0,1"
bitfld.long 0x2C 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
bitfld.long 0x2C 24. "MCH1COMCT_3,Multi mode channel 1 compare output control" "0,1"
bitfld.long 0x2C 16. "MCH0COMCTL_3,Multi mode channel 0 compare output control" "0,1"
bitfld.long 0x2C 15. "MCH1COMCEN,Multi mode channel 1 output compare clear enable" "0,1"
bitfld.long 0x2C 12.--14. "MCH1COMCTL,Multi mode channel 1 compare output control" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2C 11. "MCH1COMSEN,Multi mode channel 1 output compare shadow enable" "0,1"
bitfld.long 0x2C 10. "MCH1COMFEN,Multi mode channel 1 output compare fast enable" "0,1"
bitfld.long 0x2C 8.--9. "MCH1MS,Multi mode channel 1 I/O mode selection" "0,1,2,3"
bitfld.long 0x2C 7. "MCH0COMCEN,Multi mode channel 0 output compare clear enable" "0,1"
bitfld.long 0x2C 4.--6. "MCH0COMCTL,Multi mode channel 0 output compare control" "0,1,2,3,4,5,6,7"
bitfld.long 0x2C 3. "MCH0COMSEN,Multi mode channel 0 output compare shadow enable" "0,1"
newline
bitfld.long 0x2C 2. "MCH0COMFEN,Multi mode channel 0 output compare fast enable" "0,1"
bitfld.long 0x2C 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
group.long 0x48++0x7
line.long 0x0 "MCHCTL0_Input,Multi mode channel control register 0 (input mode)"
bitfld.long 0x0 31. "MCH1MS_2,Multi mode channel 1 I/O mode selection" "0,1"
bitfld.long 0x0 30. "MCH0MS_2,Multi mode channel 0 I/O mode selection" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "MCH1CAPFLT,Multi mode channel 1 input capture filter control"
bitfld.long 0x0 10.--11. "MCH1CAPPSC,Multi mode channel 1 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 8.--9. "MCH1MS,Multi mode channel 1 I/O mode selection" "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "MCH0CAPFLT,Multi mode channel 0 input capture filter control"
newline
bitfld.long 0x0 2.--3. "MCH0CAPPSC,Multi mode channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "MCH0MS,Multi mode channel 0 I/O mode selection" "0,1,2,3"
line.long 0x4 "MCHCTL1_Output,Multi mode channel control register 1 (output mode)"
bitfld.long 0x4 31. "MCH3MS_2,2th bit of MCH3MS" "0,1"
bitfld.long 0x4 30. "MCH2MS_2,2th bit of MCH2MS" "0,1"
bitfld.long 0x4 24. "MCH3COMCT_3,Multi mode channel 3 compare output control" "0,1"
bitfld.long 0x4 16. "MCH2COMCTL_3,Multi mode channel 2 compare output control" "0,1"
bitfld.long 0x4 15. "MCH3COMCEN,Multi mode channel 3 output compare clear enable" "0,1"
bitfld.long 0x4 12.--14. "MCH3COMCTL,Multi mode channel 3 compare output control" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 11. "MCH3COMSEN,Multi mode channel 3 output compare shadow enable" "0,1"
bitfld.long 0x4 10. "MCH3COMFEN,Multi mode channel 3 output compare fast enable" "0,1"
bitfld.long 0x4 8.--9. "MCH3MS,Multi mode channel 3 I/O mode selection" "0,1,2,3"
bitfld.long 0x4 7. "MCH2COMCEN,Multi mode channel 2 output compare clear enable" "0,1"
bitfld.long 0x4 4.--6. "MCH2COMCTL,Multi mode channel 2 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "MCH2COMSEN,Multi mode channel 2 output compare shadow enable" "0,1"
newline
bitfld.long 0x4 2. "MCH2COMFEN,Multi mode channel 2 output compare fast enable" "0,1"
bitfld.long 0x4 0.--1. "MCH2MS,Multi mode channel 2 I/O mode selection" "0,1,2,3"
group.long 0x4C++0x2B
line.long 0x0 "MCHCTL1_Input,Multi mode channel control register 1(input mode)"
bitfld.long 0x0 31. "MCH3MS_2,2th bit of MCH3MS" "0,1"
bitfld.long 0x0 30. "MCH2MS_2,2th bit of MCH2MS" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "MCH3CAPFLT,Multi mode channel 3 input capture filter control"
bitfld.long 0x0 10.--11. "MCH3CAPPSC,Multi mode channel 3 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 8.--9. "MCH3MS,Multi mode channel 3 I/O mode selection." "0,1,2,3"
hexmask.long.byte 0x0 4.--7. 1. "MCH2CAPFLT,Multi mode channel 2 input capture filter control"
newline
bitfld.long 0x0 2.--3. "MCH2CAPPSC,Multi mode channel 2 input capture prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "MCH2MS,Multi mode channel 2 I/O mode selection" "0,1,2,3"
line.long 0x4 "MCHCTL2,Multi mode channel control register 2"
bitfld.long 0x4 6.--7. "MCH3FP,Multi mode channel 3 capture / compare free polarity" "0,1,2,3"
bitfld.long 0x4 4.--5. "MCH2FP,Multi mode channel 2 capture / compare free polarity" "0,1,2,3"
bitfld.long 0x4 2.--3. "MCH1FP,Multi mode channel 1 capture / compare free polarity" "0,1,2,3"
bitfld.long 0x4 0.--1. "MCH0FP,Multi mode channel 0 capture / compare free polarity" "0,1,2,3"
line.long 0x8 "MCH0CV,Multi mode channel 0 capture/compare value register"
hexmask.long.word 0x8 0.--15. 1. "MCH0VAL,Capture / compare value of multi mode channel 0"
line.long 0xC "MCH1CV,Multi mode channel 1 capture/compare value register"
hexmask.long.word 0xC 0.--15. 1. "MCH1VAL,Capture / compare value of multi mode channel 1"
line.long 0x10 "MCH2CV,Multi mode channel 2 capture/compare value register"
hexmask.long.word 0x10 0.--15. 1. "MCH2VAL,Capture / compare value of multi mode channel 2"
line.long 0x14 "MCH3CV,Multi mode channel 3 capture / compare value register"
hexmask.long.word 0x14 0.--15. 1. "MCH3VAL,Capture / compare value of channel 3"
line.long 0x18 "CH0COMV_ADD,Channel 0 additional compare value register"
hexmask.long.word 0x18 0.--15. 1. "CH0COMVAL_ADD,Additional compare value of channel 0"
line.long 0x1C "CH1COMV_ADD,Channel 1 additional compare value register"
hexmask.long.word 0x1C 0.--15. 1. "CH1COMVAL_ADD,Additional compare value of channel 1"
line.long 0x20 "CH2COMV_ADD,Channel 2 additional compare value register"
hexmask.long.word 0x20 0.--15. 1. "CH2COMVAL_ADD,Additional compare value of channel 2"
line.long 0x24 "CH3COMV_ADD,Channel 3 additional compare value register"
hexmask.long.word 0x24 0.--15. 1. "CH3COMVAL_ADD,Additional compare value of channel 3"
line.long 0x28 "CTL2,Control register 2"
bitfld.long 0x28 31. "CH3CPWMEN,Channel 3 composite PWM mode enable" "0,1"
bitfld.long 0x28 30. "CH2CPWMEN,Channel 2 composite PWM mode enable" "0,1"
bitfld.long 0x28 29. "CH1CPWMEN,Channel 1 composite PWM mode enable" "0,1"
bitfld.long 0x28 28. "CH0CPWMEN,Channel 0 composite PWM mode enable" "0,1"
bitfld.long 0x28 26.--27. "MCH3MSEL,Multi mode channel 3 mode select" "0,1,2,3"
bitfld.long 0x28 24.--25. "MCH2MSEL,Multi mode channel 2 mode select" "0,1,2,3"
newline
bitfld.long 0x28 22.--23. "MCH1MSEL,Multi mode channel 1 mode select" "0,1,2,3"
bitfld.long 0x28 20.--21. "MCH0MSEL,Multi mode channel 0 mode select" "0,1,2,3"
bitfld.long 0x28 19. "DECDISDEN,Quadrature decoder signal disconnection detection enable" "0,1"
bitfld.long 0x28 18. "DECJDEN,Quadrature decoder signal jump (the two signals jump at the same time) detection enable" "0,1"
bitfld.long 0x28 14.--15. "CH3OMPSEL,Channel 3 output match pulse select" "0,1,2,3"
bitfld.long 0x28 12.--13. "CH2OMPSEL,Channel 2 output match pulse select" "0,1,2,3"
newline
bitfld.long 0x28 10.--11. "CH1OMPSEL,Channel 1 output match pulse select" "0,1,2,3"
bitfld.long 0x28 8.--9. "CH0OMPSEL,Channel 0 output match pulse select" "0,1,2,3"
bitfld.long 0x28 7. "BRKENCH3,Break control enable for channel 3" "0,1"
bitfld.long 0x28 6. "BRKENCH2,Break control enable for channel 2" "0,1"
bitfld.long 0x28 5. "BRKENCH1,Break control enable for channel 1" "0,1"
bitfld.long 0x28 4. "BRKENCH0,Break control enable for channel 0" "0,1"
newline
bitfld.long 0x28 3. "DTIENCH3,Dead time inserted enable for channel 3" "0,1"
bitfld.long 0x28 2. "DTIENCH2,Dead time inserted enable for channel 2" "0,1"
bitfld.long 0x28 1. "DTIENCH1,Dead time inserted enable for channel 1" "0,1"
bitfld.long 0x28 0. "DTIENCH0,Dead time inserted enable for channel 0" "0,1"
group.long 0x7C++0x2F
line.long 0x0 "FCCHP0,Free complementary channel protection register 0"
bitfld.long 0x0 31. "FCCHP0EN,Free complementary channel protection register 0 enable" "0,1"
hexmask.long.byte 0x0 16.--23. 1. "DTFCFG,Dead time falling edge configure"
bitfld.long 0x0 11. "ROS,Run mode off-state configure" "0,1"
bitfld.long 0x0 10. "IOS,Idle mode off-state configure" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DTCFG,Dead time configure"
line.long 0x4 "FCCHP1,Free complementary channel protection register 1"
bitfld.long 0x4 31. "FCCHP1EN,Free complementary channel protection register 1 enable" "0,1"
hexmask.long.byte 0x4 16.--23. 1. "DTFCFG,Dead time falling edge configure"
bitfld.long 0x4 11. "ROS,Run mode off-state configure" "0,1"
bitfld.long 0x4 10. "IOS,Idle mode off-state configure" "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DTCFG,Dead time configure"
line.long 0x8 "FCCHP2,Free complementary channel protection register 2"
bitfld.long 0x8 31. "FCCHP2EN,Free complementary channel protection register 2 enable" "0,1"
hexmask.long.byte 0x8 16.--23. 1. "DTFCFG,Dead time falling edge configure"
bitfld.long 0x8 11. "ROS,Run mode off-state configure" "0,1"
bitfld.long 0x8 10. "IOS,Idle mode off-state configure" "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DTCFG,Dead time configure"
line.long 0xC "FCCHP3,Free complementary channel protection register 3"
bitfld.long 0xC 31. "FCCHP3EN,Free complementary channel protection register 0 enable" "0,1"
hexmask.long.byte 0xC 16.--23. 1. "DTFCFG,Dead time falling edge configure"
bitfld.long 0xC 11. "ROS,Run mode off-state configure" "0,1"
bitfld.long 0xC 10. "IOS,Idle mode off-state configure" "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DTCFG,Dead time configure"
line.long 0x10 "AFCTL0,Alternate function control register 0"
bitfld.long 0x10 28. "BRK0CMP3P,BREAK0 CMP3 input polarity" "0,1"
bitfld.long 0x10 27. "BRK0CMP2P,BREAK0 CMP2 input polarity" "0,1"
bitfld.long 0x10 26. "BRK0CMP1P,BREAK0 CMP1 input polarity" "0,1"
bitfld.long 0x10 25. "BRK0CMP0P,BREAK0 CMP0 input polarity" "0,1"
bitfld.long 0x10 18. "BRK0IN2P,BREAK0 BRKIN2 alternate function input polarity" "0,1"
bitfld.long 0x10 17. "BRK0IN1P,BREAK0 BRKIN1 alternate function input polarity" "0,1"
newline
bitfld.long 0x10 16. "BRK0IN0P,BREAK0 BRKIN0 alternate function input polarity" "0,1"
bitfld.long 0x10 15. "BRK0CMP6EN,BREAK0 CMP6 enable" "0,1"
bitfld.long 0x10 14. "BRK0CMP5EN,BREAK0 CMP5 enable" "0,1"
bitfld.long 0x10 13. "BRK0CMP4EN,BREAK0 CMP4 enable" "0,1"
bitfld.long 0x10 12. "BRK0CMP3EN,BREAK0 CMP3 enable" "0,1"
bitfld.long 0x10 11. "BRK0CMP2EN,BREAK0 CMP2 enable" "0,1"
newline
bitfld.long 0x10 10. "BRK0CMP1EN,BREAK0 CMP1 enable" "0,1"
bitfld.long 0x10 9. "BRK0CMP0EN,BREAK0 CMP0 enable" "0,1"
bitfld.long 0x10 8. "BRK0HPDFEN,BREAK0 HPDF input enable" "0,1"
bitfld.long 0x10 7. "BRK0CMP7EN,BREAK0 CMP7 enable" "0,1"
bitfld.long 0x10 2. "BRK0IN2EN,BREAK0 BRKIN2 alternate function input enable" "0,1"
bitfld.long 0x10 1. "BRK0IN1EN,BREAK0 BRKIN1 alternate function input enable" "0,1"
newline
bitfld.long 0x10 0. "BRK0IN0EN,BREAK0 BRKIN0 alternate function input enable" "0,1"
line.long 0x14 "AFCTL1,Alternate function control register 1"
bitfld.long 0x14 28. "BRK1CMP3P,BREAK1 CMP3 input polarity" "0,1"
bitfld.long 0x14 27. "BRK1CMP2P,BREAK1 CMP2 input polarity" "0,1"
bitfld.long 0x14 26. "BRK1CMP1P,BREAK1 CMP1 input polarity" "0,1"
bitfld.long 0x14 25. "BRK1CMP0P,BREAK1 CMP0 input polarity" "0,1"
bitfld.long 0x14 19.--21. "OCRINSEL,OCPRE_CLR inputs selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 18. "BRK1IN2P,BREAK1 BRKIN2 alternate function input polarity" "0,1"
newline
bitfld.long 0x14 17. "BRK1IN1P,BREAK1 BRKIN1 alternate function input polarity" "0,1"
bitfld.long 0x14 16. "BRK1IN0P,BREAK1 BRKIN0 alternate function input polarity" "0,1"
bitfld.long 0x14 15. "BRK1CMP6EN,BREAK1 CMP6 enable" "0,1"
bitfld.long 0x14 14. "BRK1CMP5EN,BREAK1 CMP5 enable" "0,1"
bitfld.long 0x14 13. "BRK1CMP4EN,BREAK1 CMP4 enable" "0,1"
bitfld.long 0x14 12. "BRK1CMP3EN,BREAK1 CMP3 enable" "0,1"
newline
bitfld.long 0x14 11. "BRK1CMP2EN,BREAK1 CMP2 enable" "0,1"
bitfld.long 0x14 10. "BRK1CMP1EN,BREAK1 CMP1 enable" "0,1"
bitfld.long 0x14 9. "BRK1CMP0EN,BREAK1 CMP0 enable" "0,1"
bitfld.long 0x14 8. "BRK1HPDFEN,BREAK1 HPDF input enable" "0,1"
bitfld.long 0x14 7. "BRK1CMP7EN,BREAK1 CMP7 enable" "0,1"
bitfld.long 0x14 2. "BRK1IN2EN,BREAK1 BRKIN2 alternate function input enable" "0,1"
newline
bitfld.long 0x14 1. "BRK1IN1EN,BREAK1 BRKIN1 alternate function input enable" "0,1"
bitfld.long 0x14 0. "BRK1IN0EN,BREAK1 BRKIN0 alternate function input enable" "0,1"
line.long 0x18 "WDGPER,Watchdog counter period register"
hexmask.long 0x18 0.--31. 1. "WDGPER,Watchdog counter period value"
line.long 0x1C "CREP1,Counter repetition register 1"
hexmask.long 0x1C 0.--31. 1. "CREP1,Counter repetition value 1"
line.long 0x20 "CCHP1,Complementary channel protection register 1"
bitfld.long 0x20 17. "DTMODEN,Dead time modified on-the-fly enable" "0,1"
bitfld.long 0x20 16. "DTDIFEN,Dead time configure different enable" "0,1"
hexmask.long.byte 0x20 0.--7. 1. "DTFCFG,Dead time falling edge configure"
line.long 0x24 "DECCTL,Decoder control register"
bitfld.long 0x24 24.--26. "OPPSC,Output pulse prescaler" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x24 16.--23. 1. "OPWID,Output pulse width"
bitfld.long 0x24 6.--7. "INDP,Index positioning" "0,1,2,3"
bitfld.long 0x24 5. "FINDRST,First index signal reset the counter" "0,1"
bitfld.long 0x24 1.--2. "INDRSTDIR,Index signal reset counter direction" "0,1,2,3"
bitfld.long 0x24 0. "INDRSTEN,Index signal reset enable" "0,1"
line.long 0x28 "CINITCTL,Counter initial control register"
bitfld.long 0x28 2. "SWSYNCG,Soft synchronization event generation" "0,1"
bitfld.long 0x28 1. "CINITDIR,Counter initial count direction" "0,1"
bitfld.long 0x28 0. "CINITVEN,Counter initial value register enable" "0,1"
line.long 0x2C "CINITV,Counter initial value register"
hexmask.long.word 0x2C 0.--15. 1. "CINITVAL,Counter initial value"
group.long 0xE0++0x7
line.long 0x0 "DMACFG,DMA configuration register"
hexmask.long.byte 0x0 8.--13. 1. "DMATC,DMA transfer count"
hexmask.long.byte 0x0 0.--5. 1. "DMATA,DMA transfer access start address"
line.long 0x4 "DMATB,DMA transfer buffer register"
hexmask.long 0x4 0.--31. 1. "DMATB,DMA transfer buffer"
group.long 0xFC++0x3
line.long 0x0 "CFG,Configuration register"
bitfld.long 0x0 3. "CCUSEL,Commutation control shadow register update select" "0,1"
bitfld.long 0x0 2. "CREPSEL,The counter repetition register select" "0,1"
bitfld.long 0x0 1. "CHVSEL,Write CHxVAL register selection bit" "0,1"
bitfld.long 0x0 0. "OUTSEL,The output value selection bit" "0,1"
tree.end
tree.end
tree "TMU (Trigonometric Math Unit)"
base ad:0x48024400
group.long 0x0++0x3
line.long 0x0 "CS,Control and status register"
rbitfld.long 0x0 31. "ENDF,End of TMU operation flag" "0,1"
bitfld.long 0x0 30. "OVRF,The flag of overflow" "0,1"
bitfld.long 0x0 29. "OVRIE,Overflow interrupt enable" "0,1"
bitfld.long 0x0 22. "IWIDTH,Width of input data" "0,1"
bitfld.long 0x0 21. "OWIDTH,Width of output data" "0,1"
bitfld.long 0x0 20. "INUM,The number of times that the TMU_IDATA needs to be written" "0,1"
bitfld.long 0x0 19. "ONUM,The number of times that the TMU_ODATA needs to be read" "0,1"
bitfld.long 0x0 18. "WDEN,Enable DMA request to write TMU_IDATA" "0,1"
bitfld.long 0x0 17. "RDEN,Enable DMA request to read TMU_ODATA" "0,1"
bitfld.long 0x0 16. "RIE,Enable interrupt request to read TMU_ODATA" "0,1"
bitfld.long 0x0 15. "IFLTEN,Input floating point format enable" "0,1"
bitfld.long 0x0 14. "OFLTEN,Output floating point format enable" "0,1"
newline
bitfld.long 0x0 8.--10. "FACTOR,Scaling factor" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 4.--7. 1. "ITRTNUM,Number of iterations"
hexmask.long.byte 0x0 0.--3. 1. "MODE,Mode of TMU operation"
wgroup.long 0x4++0x3
line.long 0x0 "IDATA,Input data register"
hexmask.long 0x0 0.--31. 1. "IDATA,The input data"
rgroup.long 0x8++0x3
line.long 0x0 "ODATA,Output data register"
hexmask.long 0x0 0.--31. 1. "ODATA,The output data"
tree.end
tree "TRIGSEL (Trigger Selection Controller)"
base ad:0x40018400
group.long 0x0++0x1F
line.long 0x0 "EXTOUT_0,Trigger selection for EXTOUT register 0"
bitfld.long 0x0 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x0 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x0 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x4 "EXTOUT_1,Trigger selection for EXTOUT register 1"
bitfld.long 0x4 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x4 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x4 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x8 "EXTOUT_2,Trigger selection for EXTOUT register 2"
bitfld.long 0x8 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x8 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x8 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0xC "EXTOUT_3,Trigger selection for EXTOUT register 3"
bitfld.long 0xC 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0xC 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0xC 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x10 "ADC0,Trigger selection for ADC0 register"
bitfld.long 0x10 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x10 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x10 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x14 "ADC1,Trigger selection for ADC1 register"
bitfld.long 0x14 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x14 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x14 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x18 "ADC2,Trigger selection for ADC2 register"
bitfld.long 0x18 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x18 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x18 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x1C "ADC3,Trigger selection for ADC3 register"
bitfld.long 0x1C 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x1C 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x1C 0.--7. 1. "INSEL0,Trigger input source selection for output0"
group.long 0x2C++0x97
line.long 0x0 "TIMER0BRKIN,Trigger selection for TIMER0_BRKIN register"
bitfld.long 0x0 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x0 16.--23. 1. "INSEL2,Trigger input source selection for output2"
hexmask.long.byte 0x0 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x0 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x4 "TIMER7BRKIN,Trigger selection for TIMER7_BRKIN register"
bitfld.long 0x4 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x4 16.--23. 1. "INSEL2,Trigger input source selection for output2"
hexmask.long.byte 0x4 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x4 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x8 "TIMER14BRKIN,Trigger selection for TIMER14_BRKIN register"
bitfld.long 0x8 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x8 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0xC "TIMER15BRKIN,Trigger selection for TIMER15_BRKIN register"
bitfld.long 0xC 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0xC 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x10 "TIMER16BRKIN,Trigger selection for TIMER16_BRKIN register"
bitfld.long 0x10 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x14 "TIMER19BRKIN,Trigger selection for TIMER19_BRKIN register"
bitfld.long 0x14 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x18 "CAN0,Trigger selection for CAN0 register"
bitfld.long 0x18 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x18 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x1C "CAN1,Trigger selection for CAN1 register"
bitfld.long 0x1C 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x1C 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x20 "CAN2,Trigger selection for CAN2 register"
bitfld.long 0x20 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x20 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x24 "TIMER0ETI,Trigger selection for TIMER0_ETI register"
bitfld.long 0x24 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x24 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x28 "TIMER1ETI,Trigger selection for TIMER1_ETI register"
bitfld.long 0x28 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x28 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x2C "TIMER2ETI,Trigger selection for TIMER2_ETI register"
bitfld.long 0x2C 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x2C 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x30 "TIMER3ETI,Trigger selection for TIMER3_ETI register"
bitfld.long 0x30 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x30 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x34 "TIMER4ETI,Trigger selection for TIMER4_ETI register"
bitfld.long 0x34 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x34 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x38 "TIMER7ETI,Trigger selection for TIMER7_ETI register"
bitfld.long 0x38 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x38 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x3C "TIMER19ETI,Trigger selection for TIMER19_ETI register"
bitfld.long 0x3C 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x3C 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x40 "HPDF,Trigger selection for HPDF_ITRG register"
bitfld.long 0x40 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x40 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x44 "TIMER0ITI14,Trigger selection for TIMER0_ITI14 register"
bitfld.long 0x44 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x44 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x48 "TIMER1ITI14,Trigger selection for TIMER1_ITI14 register"
bitfld.long 0x48 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x48 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x4C "TIMER2ITI14,Trigger selection for TIMER2_ITI14 register"
bitfld.long 0x4C 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x4C 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x50 "TIMER3ITI14,Trigger selection for TIMER3_ITI14 register"
bitfld.long 0x50 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x50 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x54 "TIMER4ITI14,Trigger selection for TIMER4_ITI14 register"
bitfld.long 0x54 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x54 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x58 "TIMER7ITI14,Trigger selection for TIMER7_ITI14 register"
bitfld.long 0x58 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x58 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x5C "TIMER14ITI14,Trigger selection for TIMER14_ITI14 register"
bitfld.long 0x5C 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x5C 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x60 "TIMER19ITI14,Trigger selection for TIMER19_ITI14 register"
bitfld.long 0x60 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x60 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x64 "DAC0,Trigger selection for DAC0 register"
bitfld.long 0x64 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x64 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x64 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x68 "DAC1,Trigger selection for DAC1 register"
bitfld.long 0x68 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x68 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x68 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x6C "DAC2,Trigger selection for DAC2 register"
bitfld.long 0x6C 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x6C 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x6C 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x70 "DAC3,Trigger selection for DAC3 register"
bitfld.long 0x70 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x70 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x70 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x74 "EXTDAC0,Trigger selection for DAC0 extended register"
bitfld.long 0x74 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x74 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x74 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x78 "EXTDAC1,Trigger selection for DAC1 extended register"
bitfld.long 0x78 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x78 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x78 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x7C "EXTDAC2,Trigger selection for DAC2 extended register"
bitfld.long 0x7C 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x7C 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x7C 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x80 "EXTDAC3,Trigger selection for DAC3 extended register"
bitfld.long 0x80 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x80 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x80 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x84 "CLA_0,Trigger selection for CLA register 0"
bitfld.long 0x84 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x84 16.--23. 1. "INSEL2,Trigger input source selection for output2"
hexmask.long.byte 0x84 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x84 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x88 "CLA_1,Trigger selection for CLA register 1"
bitfld.long 0x88 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x88 16.--23. 1. "INSEL2,Trigger input source selection for output2"
hexmask.long.byte 0x88 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x88 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x8C "CLA_2,Trigger selection for CLA register 2"
bitfld.long 0x8C 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x8C 16.--23. 1. "INSEL2,Trigger input source selection for output2"
hexmask.long.byte 0x8C 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x8C 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x90 "CLA_3,Trigger selection for CLA register 3"
bitfld.long 0x90 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x90 8.--15. 1. "INSEL1,Trigger input source selection for output1"
hexmask.long.byte 0x90 0.--7. 1. "INSEL0,Trigger input source selection for output0"
line.long 0x94 "CLA_4,Trigger selection for CLA register 4"
bitfld.long 0x94 31. "LK,TRIGSEL register lock" "0,1"
hexmask.long.byte 0x94 0.--7. 1. "INSEL0,Trigger input source selection for output0"
tree.end
tree "TRNG (True Random Number Generator)"
base ad:0x48021800
group.long 0x0++0x7
line.long 0x0 "CTL,Control register"
bitfld.long 0x0 31. "CTLLK,TRNG_CTL register lock bit" "0,1"
bitfld.long 0x0 30. "CONDRST,Reset conditioning logic" "0,1"
bitfld.long 0x0 24.--25. "NR,Analog trng power mode" "0,1,2,3"
hexmask.long.byte 0x0 16.--19. 1. "CLKDIV,TRNG clock divider"
bitfld.long 0x0 15. "INMOD,Select random seed number input to conditioning module" "0,1"
bitfld.long 0x0 14. "OUTMOD,Select random data width output of conditioning module" "0,1"
bitfld.long 0x0 12.--13. "ALGO,conditioning module hash algorithm selection" "0,1,2,3"
bitfld.long 0x0 10. "CONDEN,The enable bit of conditioning component" "0,1"
bitfld.long 0x0 9. "PPEN,The enable bit of post processing function" "0,1"
bitfld.long 0x0 8. "INIT,Initialize hash algorithm when conditioning enabled" "0,1"
bitfld.long 0x0 7. "RTEN,Replace test enable bit" "0,1"
newline
bitfld.long 0x0 6. "SEEDSEL,seed mode selection" "0,1"
bitfld.long 0x0 5. "CED,Clock error detection" "0,1"
bitfld.long 0x0 4. "MODSEL,LFSR or NIST mode selection" "0,1"
bitfld.long 0x0 3. "IE,The enable bit of the TRNG interrupt" "0,1"
bitfld.long 0x0 2. "TRNGEN,The enabled bit of the TRNG" "0,1"
line.long 0x4 "STAT,Status register"
bitfld.long 0x4 6. "SEIF,Seed error interrupt flag" "0,1"
bitfld.long 0x4 5. "CEIF,Clock error interrupt flag" "0,1"
rbitfld.long 0x4 3. "ERRSTA,NIST mode error flag this bit could be reset by CONDRST" "0,1"
rbitfld.long 0x4 2. "SECS,Seed error current status" "0,1"
rbitfld.long 0x4 1. "CECS,Clock error current status" "0,1"
rbitfld.long 0x4 0. "DRDY,Random data ready status bit" "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "DATA,Data register"
hexmask.long 0x0 0.--31. 1. "TRNDATA,32-bit random data"
group.long 0x10++0x3
line.long 0x0 "HTCFG,Health tests configure register"
hexmask.long.word 0x0 16.--25. 1. "APTTH,Adaptive proportion test threshold"
hexmask.long.byte 0x0 0.--6. 1. "RCTTH,Repetition count test threshold"
tree.end
tree "UART (Universal Asynchronous Receiver/Transmitter)"
base ad:0x0
tree "UART3"
base ad:0x40004C00
group.long 0x0++0xF
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 31. "AMIE1,ADDR1 match interrupt enable" "0,1"
bitfld.long 0x0 28. "WL1,Word length 1" "0,1"
hexmask.long.byte 0x0 21.--25. 1. "DEA,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DED,Driver Enable de-assertion time"
bitfld.long 0x0 15. "OVSMOD,Oversample mode" "0,1"
bitfld.long 0x0 14. "AMIE0,ADDR0 match interrupt enable" "0,1"
bitfld.long 0x0 13. "MEN,Mute mode enable" "0,1"
bitfld.long 0x0 12. "WL0,Word length" "0,1"
newline
bitfld.long 0x0 11. "WM,Wakeup method in mute mode" "0,1"
bitfld.long 0x0 10. "PCEN,Parity control enable" "0,1"
bitfld.long 0x0 9. "PM,Parity mode" "0,1"
bitfld.long 0x0 8. "PERRIE,Parity error interrupt enable" "0,1"
bitfld.long 0x0 7. "TBEIE_TFNFIE,Interrupt enable" "0,1"
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
bitfld.long 0x0 5. "RBNEIE_RFNEIE,Interrupt enable" "0,1"
bitfld.long 0x0 4. "IDLEIE,IDLE line detected interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "TEN,Transmitter enable" "0,1"
bitfld.long 0x0 2. "REN,Receiver enable" "0,1"
bitfld.long 0x0 1. "UESM,USART enable in Deep-sleep mode" "0,1"
bitfld.long 0x0 0. "UEN,USART enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
hexmask.long.byte 0x4 24.--31. 1. "ADDR0,Address 0 of the USART terminal"
bitfld.long 0x4 19. "MSBF,Most significant bit first" "0,1"
bitfld.long 0x4 18. "DINV,Data bit level inversion" "0,1"
bitfld.long 0x4 17. "TINV,TX pin level inversion" "0,1"
bitfld.long 0x4 16. "RINV,RX pin level inversion" "0,1"
bitfld.long 0x4 15. "STRP,Swap TX/RX pins" "0,1"
bitfld.long 0x4 10. "CPL,Clock polarity" "0,1"
bitfld.long 0x4 9. "CPH,Clock phase" "0,1"
newline
bitfld.long 0x4 8. "CLEN,CK length" "0,1"
bitfld.long 0x4 4. "ADDM0,Address detection mode 0" "0,1"
bitfld.long 0x4 0. "AMEN0,Match Address Mode Enable 0" "0,1"
line.long 0x8 "CTL2,Control register 2"
hexmask.long.byte 0x8 24.--31. 1. "ADDR1,Address 1 of the USART terminal"
bitfld.long 0x8 23. "ADDM1,Address detection mode 1" "0,1"
bitfld.long 0x8 16. "AMEN1,Match Address Mode Enable 1" "0,1"
bitfld.long 0x8 15. "DEP,Driver enable polarity mode" "0,1"
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
bitfld.long 0x8 13. "DDRE,Disable DMA on reception error" "0,1"
bitfld.long 0x8 12. "OVRD,Overrun disable" "0,1"
bitfld.long 0x8 11. "OSB,One sample bit method" "0,1"
newline
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
bitfld.long 0x8 9. "CTSEN,CTS enable" "0,1"
bitfld.long 0x8 8. "RTSEN,RTS enable" "0,1"
bitfld.long 0x8 7. "DENT,DMA enable for transmission" "0,1"
bitfld.long 0x8 6. "DENR,DMA enable for reception" "0,1"
bitfld.long 0x8 3. "HDEN,Half-duplex enable" "0,1"
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0,1"
bitfld.long 0x8 0. "ERRIE,Error interrupt enable" "0,1"
line.long 0xC "BAUD,Baud rate generator register"
hexmask.long.word 0xC 4.--15. 1. "BRR_INT,Integer of baud-rate divider"
hexmask.long.byte 0xC 0.--3. 1. "BRR_DIV,Fraction of baud-rate divider"
wgroup.long 0x18++0x3
line.long 0x0 "CMD,Command register"
bitfld.long 0x0 4. "TXFCMD,Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFCMD,Receive data flush command" "0,1"
bitfld.long 0x0 2. "MMCMD,Mute mode command" "0,1"
bitfld.long 0x0 1. "SBKCMD,Send break command" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "STAT,Status register"
bitfld.long 0x0 22. "REA,Receive enable acknowledge flag" "0,1"
bitfld.long 0x0 21. "TEA,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 19. "RWU,Receiver wakeup from mute mode" "0,1"
bitfld.long 0x0 18. "SBF,Send break flag" "0,1"
bitfld.long 0x0 17. "AMF0,ADDR0 match flag" "0,1"
bitfld.long 0x0 16. "BSY,Busy flag" "0,1"
bitfld.long 0x0 13. "AMF1,ADDR1 match flag" "0,1"
bitfld.long 0x0 10. "CTS,CTS level" "0,1"
newline
bitfld.long 0x0 9. "CTSF,CTS change flag" "0,1"
bitfld.long 0x0 7. "TBE_TFNF,When FIFO is disabled:" "0,1"
bitfld.long 0x0 6. "TC,Transmission completed" "0,1"
bitfld.long 0x0 5. "RBNE_RFNE,Interrupt enable" "0,1"
bitfld.long 0x0 4. "IDLEF,IDLE line detected flag" "0,1"
bitfld.long 0x0 3. "ORERR,Overrun error" "0,1"
bitfld.long 0x0 2. "NERR,Noise error flag" "0,1"
bitfld.long 0x0 1. "FERR,Frame error flag" "0,1"
newline
bitfld.long 0x0 0. "PERR,Parity error flag" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "INTC,Interrupt status clear register"
bitfld.long 0x0 20. "WUC,Wakeup from Deep-sleep mode clear" "0,1"
bitfld.long 0x0 17. "AMC0,ADDR0 match clear" "0,1"
bitfld.long 0x0 16. "AMC1,ADDR1 match clear" "0,1"
bitfld.long 0x0 9. "CTSC,CTS change clear" "0,1"
bitfld.long 0x0 6. "TCC,Transmission complete clear" "0,1"
bitfld.long 0x0 4. "IDLEC,Idle line detected clear" "0,1"
bitfld.long 0x0 3. "OREC,Overrun error clear" "0,1"
bitfld.long 0x0 2. "NEC,Noise detected clear" "0,1"
newline
bitfld.long 0x0 1. "FEC,Frame error flag clear" "0,1"
bitfld.long 0x0 0. "PEC,Parity error clear" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "RDATA,Receive data register"
hexmask.long.word 0x0 0.--9. 1. "RDATA,Receive Data value"
group.long 0x28++0x3
line.long 0x0 "TDATA,Transmit data register"
hexmask.long.word 0x0 0.--9. 1. "TDATA,Transmit Data value"
group.long 0xC0++0x3
line.long 0x0 "CHC,USART coherence control register"
bitfld.long 0x0 8. "EPERR,Early parity error flag" "0,1"
bitfld.long 0x0 0. "HCM,Hardware flow control coherence mode" "0,1"
group.long 0xD0++0x3
line.long 0x0 "RFCS,USART receive FIFO control and status register"
bitfld.long 0x0 31. "TFEIE,Transmit FIFO empty interrupt enable" "0,1"
bitfld.long 0x0 29. "TFTIE,Transmit FIFO threshold interrupt enable" "0,1"
bitfld.long 0x0 27. "RFTIE,Receive FIFO threshold interrupt enable" "0,1"
bitfld.long 0x0 26. "TFEC,Transmit FIFO empty flag clear" "0,1"
rbitfld.long 0x0 25. "TFTIF,Transmit FIFO threshold interrupt flag" "0,1"
rbitfld.long 0x0 24. "TFEIF,Transmit FIFO empty interrupt flag" "0,1"
rbitfld.long 0x0 22. "RFTIF,Receive FIFO threshold interrupt flag" "0,1"
bitfld.long 0x0 19.--21. "TFTCFG,Transmit FIFO threshold configuration" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16.--18. "RFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "RFFIF,Receive FIFO full interrupt flag" "0,1"
rbitfld.long 0x0 12.--14. "RFCNT,Receive FIFO counter number" "0,1,2,3,4,5,6,7"
rbitfld.long 0x0 11. "RFF,Receive FIFO full flag" "0,1"
bitfld.long 0x0 10. "RFE,Receive FIFO empty flag" "0,1"
bitfld.long 0x0 9. "RFFIE,Receive FIFO full interrupt enable" "0,1"
bitfld.long 0x0 8. "FEN,FIFO enable" "0,1"
rbitfld.long 0x0 7. "TFF,Transmit FIFO full flag" "0,1"
newline
rbitfld.long 0x0 6. "TFE,Transmit FIFO empty flag" "0,1"
bitfld.long 0x0 5. "TFT,Transmit FIFO threshold flag" "0,1"
rbitfld.long 0x0 4. "RFT,Receive FIFO threshold flag" "0,1"
rbitfld.long 0x0 1.--2. "RFCNT_3_4,Bits 3_4 of receive FIFO counter number" "0,1,2,3"
bitfld.long 0x0 0. "ELNACK,Early NACK when smartcard mode is selected" "0,1"
tree.end
tree "UART4"
base ad:0x40005000
group.long 0x0++0xF
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 31. "AMIE1,ADDR1 match interrupt enable" "0,1"
bitfld.long 0x0 28. "WL1,Word length 1" "0,1"
hexmask.long.byte 0x0 21.--25. 1. "DEA,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DED,Driver Enable de-assertion time"
bitfld.long 0x0 15. "OVSMOD,Oversample mode" "0,1"
bitfld.long 0x0 14. "AMIE0,ADDR0 match interrupt enable" "0,1"
bitfld.long 0x0 13. "MEN,Mute mode enable" "0,1"
bitfld.long 0x0 12. "WL0,Word length" "0,1"
newline
bitfld.long 0x0 11. "WM,Wakeup method in mute mode" "0,1"
bitfld.long 0x0 10. "PCEN,Parity control enable" "0,1"
bitfld.long 0x0 9. "PM,Parity mode" "0,1"
bitfld.long 0x0 8. "PERRIE,Parity error interrupt enable" "0,1"
bitfld.long 0x0 7. "TBEIE_TFNFIE,Interrupt enable" "0,1"
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
bitfld.long 0x0 5. "RBNEIE_RFNEIE,Interrupt enable" "0,1"
bitfld.long 0x0 4. "IDLEIE,IDLE line detected interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "TEN,Transmitter enable" "0,1"
bitfld.long 0x0 2. "REN,Receiver enable" "0,1"
bitfld.long 0x0 1. "UESM,USART enable in Deep-sleep mode" "0,1"
bitfld.long 0x0 0. "UEN,USART enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
hexmask.long.byte 0x4 24.--31. 1. "ADDR0,Address 0 of the USART terminal"
bitfld.long 0x4 19. "MSBF,Most significant bit first" "0,1"
bitfld.long 0x4 18. "DINV,Data bit level inversion" "0,1"
bitfld.long 0x4 17. "TINV,TX pin level inversion" "0,1"
bitfld.long 0x4 16. "RINV,RX pin level inversion" "0,1"
bitfld.long 0x4 15. "STRP,Swap TX/RX pins" "0,1"
bitfld.long 0x4 10. "CPL,Clock polarity" "0,1"
bitfld.long 0x4 9. "CPH,Clock phase" "0,1"
newline
bitfld.long 0x4 8. "CLEN,CK length" "0,1"
bitfld.long 0x4 4. "ADDM0,Address detection mode 0" "0,1"
bitfld.long 0x4 0. "AMEN0,Match Address Mode Enable 0" "0,1"
line.long 0x8 "CTL2,Control register 2"
hexmask.long.byte 0x8 24.--31. 1. "ADDR1,Address 1 of the USART terminal"
bitfld.long 0x8 23. "ADDM1,Address detection mode 1" "0,1"
bitfld.long 0x8 16. "AMEN1,Match Address Mode Enable 1" "0,1"
bitfld.long 0x8 15. "DEP,Driver enable polarity mode" "0,1"
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
bitfld.long 0x8 13. "DDRE,Disable DMA on reception error" "0,1"
bitfld.long 0x8 12. "OVRD,Overrun disable" "0,1"
bitfld.long 0x8 11. "OSB,One sample bit method" "0,1"
newline
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
bitfld.long 0x8 9. "CTSEN,CTS enable" "0,1"
bitfld.long 0x8 8. "RTSEN,RTS enable" "0,1"
bitfld.long 0x8 7. "DENT,DMA enable for transmission" "0,1"
bitfld.long 0x8 6. "DENR,DMA enable for reception" "0,1"
bitfld.long 0x8 3. "HDEN,Half-duplex enable" "0,1"
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0,1"
bitfld.long 0x8 0. "ERRIE,Error interrupt enable" "0,1"
line.long 0xC "BAUD,Baud rate generator register"
hexmask.long.word 0xC 4.--15. 1. "BRR_INT,Integer of baud-rate divider"
hexmask.long.byte 0xC 0.--3. 1. "BRR_DIV,Fraction of baud-rate divider"
wgroup.long 0x18++0x3
line.long 0x0 "CMD,Command register"
bitfld.long 0x0 4. "TXFCMD,Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFCMD,Receive data flush command" "0,1"
bitfld.long 0x0 2. "MMCMD,Mute mode command" "0,1"
bitfld.long 0x0 1. "SBKCMD,Send break command" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "STAT,Status register"
bitfld.long 0x0 22. "REA,Receive enable acknowledge flag" "0,1"
bitfld.long 0x0 21. "TEA,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 19. "RWU,Receiver wakeup from mute mode" "0,1"
bitfld.long 0x0 18. "SBF,Send break flag" "0,1"
bitfld.long 0x0 17. "AMF0,ADDR0 match flag" "0,1"
bitfld.long 0x0 16. "BSY,Busy flag" "0,1"
bitfld.long 0x0 13. "AMF1,ADDR1 match flag" "0,1"
bitfld.long 0x0 10. "CTS,CTS level" "0,1"
newline
bitfld.long 0x0 9. "CTSF,CTS change flag" "0,1"
bitfld.long 0x0 7. "TBE_TFNF,When FIFO is disabled:" "0,1"
bitfld.long 0x0 6. "TC,Transmission completed" "0,1"
bitfld.long 0x0 5. "RBNE_RFNE,Interrupt enable" "0,1"
bitfld.long 0x0 4. "IDLEF,IDLE line detected flag" "0,1"
bitfld.long 0x0 3. "ORERR,Overrun error" "0,1"
bitfld.long 0x0 2. "NERR,Noise error flag" "0,1"
bitfld.long 0x0 1. "FERR,Frame error flag" "0,1"
newline
bitfld.long 0x0 0. "PERR,Parity error flag" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "INTC,Interrupt status clear register"
bitfld.long 0x0 20. "WUC,Wakeup from Deep-sleep mode clear" "0,1"
bitfld.long 0x0 17. "AMC0,ADDR0 match clear" "0,1"
bitfld.long 0x0 16. "AMC1,ADDR1 match clear" "0,1"
bitfld.long 0x0 9. "CTSC,CTS change clear" "0,1"
bitfld.long 0x0 6. "TCC,Transmission complete clear" "0,1"
bitfld.long 0x0 4. "IDLEC,Idle line detected clear" "0,1"
bitfld.long 0x0 3. "OREC,Overrun error clear" "0,1"
bitfld.long 0x0 2. "NEC,Noise detected clear" "0,1"
newline
bitfld.long 0x0 1. "FEC,Frame error flag clear" "0,1"
bitfld.long 0x0 0. "PEC,Parity error clear" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "RDATA,Receive data register"
hexmask.long.word 0x0 0.--9. 1. "RDATA,Receive Data value"
group.long 0x28++0x3
line.long 0x0 "TDATA,Transmit data register"
hexmask.long.word 0x0 0.--9. 1. "TDATA,Transmit Data value"
group.long 0xC0++0x3
line.long 0x0 "CHC,USART coherence control register"
bitfld.long 0x0 8. "EPERR,Early parity error flag" "0,1"
bitfld.long 0x0 0. "HCM,Hardware flow control coherence mode" "0,1"
group.long 0xD0++0x3
line.long 0x0 "RFCS,USART receive FIFO control and status register"
bitfld.long 0x0 31. "TFEIE,Transmit FIFO empty interrupt enable" "0,1"
bitfld.long 0x0 29. "TFTIE,Transmit FIFO threshold interrupt enable" "0,1"
bitfld.long 0x0 27. "RFTIE,Receive FIFO threshold interrupt enable" "0,1"
bitfld.long 0x0 26. "TFEC,Transmit FIFO empty flag clear" "0,1"
rbitfld.long 0x0 25. "TFTIF,Transmit FIFO threshold interrupt flag" "0,1"
rbitfld.long 0x0 24. "TFEIF,Transmit FIFO empty interrupt flag" "0,1"
rbitfld.long 0x0 22. "RFTIF,Receive FIFO threshold interrupt flag" "0,1"
bitfld.long 0x0 19.--21. "TFTCFG,Transmit FIFO threshold configuration" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16.--18. "RFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "RFFIF,Receive FIFO full interrupt flag" "0,1"
rbitfld.long 0x0 12.--14. "RFCNT,Receive FIFO counter number" "0,1,2,3,4,5,6,7"
rbitfld.long 0x0 11. "RFF,Receive FIFO full flag" "0,1"
bitfld.long 0x0 10. "RFE,Receive FIFO empty flag" "0,1"
bitfld.long 0x0 9. "RFFIE,Receive FIFO full interrupt enable" "0,1"
bitfld.long 0x0 8. "FEN,FIFO enable" "0,1"
rbitfld.long 0x0 7. "TFF,Transmit FIFO full flag" "0,1"
newline
rbitfld.long 0x0 6. "TFE,Transmit FIFO empty flag" "0,1"
bitfld.long 0x0 5. "TFT,Transmit FIFO threshold flag" "0,1"
rbitfld.long 0x0 4. "RFT,Receive FIFO threshold flag" "0,1"
rbitfld.long 0x0 1.--2. "RFCNT_3_4,Bits 3_4 of receive FIFO counter number" "0,1,2,3"
bitfld.long 0x0 0. "ELNACK,Early NACK when smartcard mode is selected" "0,1"
tree.end
tree.end
tree "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"
base ad:0x0
tree "USART0"
base ad:0x40013800
group.long 0x0++0x17
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 31. "AMIE1,ADDR1 match interrupt enable" "0,1"
bitfld.long 0x0 28. "WL1,Word length 1" "0,1"
bitfld.long 0x0 27. "EBIE,End of Block interrupt enable" "0,1"
bitfld.long 0x0 26. "RTIE,Receiver timeout interrupt enable" "0,1"
hexmask.long.byte 0x0 21.--25. 1. "DEA,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DED,Driver Enable de-assertion time"
bitfld.long 0x0 15. "OVSMOD,Oversample mode" "0,1"
bitfld.long 0x0 14. "AMIE0,ADDR0 match interrupt enable" "0,1"
newline
bitfld.long 0x0 13. "MEN,Mute mode enable" "0,1"
bitfld.long 0x0 12. "WL0,Word length" "0,1"
bitfld.long 0x0 11. "WM,Wakeup method in mute mode" "0,1"
bitfld.long 0x0 10. "PCEN,Parity control enable" "0,1"
bitfld.long 0x0 9. "PM,Parity mode" "0,1"
bitfld.long 0x0 8. "PERRIE,Parity error interrupt enable" "0,1"
bitfld.long 0x0 7. "TBEIE_TFNFIE,Interrupt enable" "0,1"
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
newline
bitfld.long 0x0 5. "RBNEIE_RFNEIE,Interrupt enable" "0,1"
bitfld.long 0x0 4. "IDLEIE,IDLE line detected interrupt enable" "0,1"
bitfld.long 0x0 3. "TEN,Transmitter enable" "0,1"
bitfld.long 0x0 2. "REN,Receiver enable" "0,1"
bitfld.long 0x0 1. "UESM,USART enable in Deep-sleep mode" "0,1"
bitfld.long 0x0 0. "UEN,USART enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
hexmask.long.byte 0x4 24.--31. 1. "ADDR0,Address 0 of the USART terminal"
bitfld.long 0x4 23. "RTEN,Receiver timeout enable" "0,1"
bitfld.long 0x4 19. "MSBF,Most significant bit first" "0,1"
bitfld.long 0x4 18. "DINV,Data bit level inversion" "0,1"
bitfld.long 0x4 17. "TINV,TX pin level inversion" "0,1"
bitfld.long 0x4 16. "RINV,RX pin level inversion" "0,1"
bitfld.long 0x4 15. "STRP,Swap TX/RX pins" "0,1"
bitfld.long 0x4 14. "LMEN,LIN mode enable" "0,1"
newline
bitfld.long 0x4 12.--13. "STB,STOP bits length" "0,1,2,3"
bitfld.long 0x4 11. "CKEN,CK pin enable" "0,1"
bitfld.long 0x4 10. "CPL,Clock polarity" "0,1"
bitfld.long 0x4 9. "CPH,Clock phase" "0,1"
bitfld.long 0x4 8. "CLEN,CK length" "0,1"
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
bitfld.long 0x4 5. "LBLEN,LIN break frame length" "0,1"
bitfld.long 0x4 4. "ADDM0,Address detection mode 0" "0,1"
newline
bitfld.long 0x4 0. "AMEN0,Match Address Mode Enable 0" "0,1"
line.long 0x8 "CTL2,Control register 2"
hexmask.long.byte 0x8 24.--31. 1. "ADDR1,Address 1 of the USART terminal"
bitfld.long 0x8 23. "ADDM1,Address detection mode 1" "0,1"
bitfld.long 0x8 22. "WUIE,Wakeup from Deep-sleep mode interrupt enable" "0,1"
bitfld.long 0x8 20.--21. "WUM,Wakeup mode from Deep-sleep mode" "0,1,2,3"
bitfld.long 0x8 17.--19. "SCRTNUM,Smartcard auto-retry number" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 16. "AMEN1,Match Address Mode Enable 1" "0,1"
bitfld.long 0x8 15. "DEP,Driver enable polarity mode" "0,1"
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
newline
bitfld.long 0x8 13. "DDRE,Disable DMA on reception error" "0,1"
bitfld.long 0x8 12. "OVRD,Overrun disable" "0,1"
bitfld.long 0x8 11. "OSB,One sample bit method" "0,1"
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
bitfld.long 0x8 9. "CTSEN,CTS enable" "0,1"
bitfld.long 0x8 8. "RTSEN,RTS enable" "0,1"
bitfld.long 0x8 7. "DENT,DMA enable for transmission" "0,1"
bitfld.long 0x8 6. "DENR,DMA enable for reception" "0,1"
newline
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
bitfld.long 0x8 4. "NKEN,NACK enable in Smartcard mode" "0,1"
bitfld.long 0x8 3. "HDEN,Half-duplex enable" "0,1"
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0,1"
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0,1"
bitfld.long 0x8 0. "ERRIE,Error interrupt enable" "0,1"
line.long 0xC "BAUD,Baud rate generator register"
hexmask.long.word 0xC 4.--15. 1. "BRR_INT,Integer of baud-rate divider"
hexmask.long.byte 0xC 0.--3. 1. "BRR_DIV,Fraction of baud-rate divider"
line.long 0x10 "GP,Prescaler and guard time configuration register"
hexmask.long.byte 0x10 8.--15. 1. "GUAT,Guard time value in smartcard mode"
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value for dividing the system clock"
line.long 0x14 "RT,Receiver timeout register"
hexmask.long.byte 0x14 24.--31. 1. "BL,Block Length"
hexmask.long.tbyte 0x14 0.--23. 1. "RT,Receiver timeout threshold"
wgroup.long 0x18++0x3
line.long 0x0 "CMD,Command register"
bitfld.long 0x0 4. "TXFCMD,Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFCMD,Receive data flush command" "0,1"
bitfld.long 0x0 2. "MMCMD,Mute mode command" "0,1"
bitfld.long 0x0 1. "SBKCMD,Send break command" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "STAT,Status register"
bitfld.long 0x0 22. "REA,Receive enable acknowledge flag" "0,1"
bitfld.long 0x0 21. "TEA,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 20. "WUF,Wakeup from Deep-sleep mode flag" "0,1"
bitfld.long 0x0 19. "RWU,Receiver wakeup from mute mode" "0,1"
bitfld.long 0x0 18. "SBF,Send break flag" "0,1"
bitfld.long 0x0 17. "AMF0,ADDR0 match flag" "0,1"
bitfld.long 0x0 16. "BSY,Busy flag" "0,1"
bitfld.long 0x0 13. "AMF1,ADDR1 match flag" "0,1"
newline
bitfld.long 0x0 12. "EBF,End of block flag" "0,1"
bitfld.long 0x0 11. "RTF,Receiver timeout flag" "0,1"
bitfld.long 0x0 10. "CTS,CTS level" "0,1"
bitfld.long 0x0 9. "CTSF,CTS change flag" "0,1"
bitfld.long 0x0 8. "LBDF,LIN break detected flag" "0,1"
bitfld.long 0x0 7. "TBE_TFNF,When FIFO is disabled:" "0,1"
bitfld.long 0x0 6. "TC,Transmission completed" "0,1"
bitfld.long 0x0 5. "RBNE_RFNE,Interrupt enable" "0,1"
newline
bitfld.long 0x0 4. "IDLEF,IDLE line detected flag" "0,1"
bitfld.long 0x0 3. "ORERR,Overrun error" "0,1"
bitfld.long 0x0 2. "NERR,Noise error flag" "0,1"
bitfld.long 0x0 1. "FERR,Frame error flag" "0,1"
bitfld.long 0x0 0. "PERR,Parity error flag" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "INTC,Interrupt status clear register"
bitfld.long 0x0 20. "WUC,Wakeup from Deep-sleep mode clear" "0,1"
bitfld.long 0x0 17. "AMC0,ADDR0 match clear" "0,1"
bitfld.long 0x0 16. "AMC1,ADDR1 match clear" "0,1"
bitfld.long 0x0 12. "EBC,End of block clear" "0,1"
bitfld.long 0x0 11. "RTC,Receiver timeout clear" "0,1"
bitfld.long 0x0 9. "CTSC,CTS change clear" "0,1"
bitfld.long 0x0 8. "LBDC,LIN break detected clear" "0,1"
bitfld.long 0x0 6. "TCC,Transmission complete clear" "0,1"
newline
bitfld.long 0x0 4. "IDLEC,Idle line detected clear" "0,1"
bitfld.long 0x0 3. "OREC,Overrun error clear" "0,1"
bitfld.long 0x0 2. "NEC,Noise detected clear" "0,1"
bitfld.long 0x0 1. "FEC,Frame error flag clear" "0,1"
bitfld.long 0x0 0. "PEC,Parity error clear" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "RDATA,Receive data register"
hexmask.long.word 0x0 0.--9. 1. "RDATA,Receive Data value"
group.long 0x28++0x3
line.long 0x0 "TDATA,Transmit data register"
hexmask.long.word 0x0 0.--9. 1. "TDATA,Transmit Data value"
group.long 0xC0++0x3
line.long 0x0 "CHC,USART coherence control register"
bitfld.long 0x0 8. "EPERR,Early parity error flag" "0,1"
bitfld.long 0x0 0. "HCM,Hardware flow control coherence mode" "0,1"
group.long 0xD0++0x3
line.long 0x0 "RFCS,USART receive FIFO control and status register"
bitfld.long 0x0 31. "TFEIE,Transmit FIFO empty interrupt enable" "0,1"
bitfld.long 0x0 29. "TFTIE,Transmit FIFO threshold interrupt enable" "0,1"
bitfld.long 0x0 27. "RFTIE,Receive FIFO threshold interrupt enable" "0,1"
bitfld.long 0x0 26. "TFEC,Transmit FIFO empty flag clear" "0,1"
rbitfld.long 0x0 25. "TFTIF,Transmit FIFO threshold interrupt flag" "0,1"
rbitfld.long 0x0 24. "TFEIF,Transmit FIFO empty interrupt flag" "0,1"
rbitfld.long 0x0 22. "RFTIF,Receive FIFO threshold interrupt flag" "0,1"
bitfld.long 0x0 19.--21. "TFTCFG,Transmit FIFO threshold configuration" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16.--18. "RFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "RFFIF,Receive FIFO full interrupt flag" "0,1"
rbitfld.long 0x0 12.--14. "RFCNT,Receive FIFO counter number" "0,1,2,3,4,5,6,7"
rbitfld.long 0x0 11. "RFF,Receive FIFO full flag" "0,1"
rbitfld.long 0x0 10. "RFE,Receive FIFO empty flag" "0,1"
bitfld.long 0x0 9. "RFFIE,Receive FIFO full interrupt enable" "0,1"
bitfld.long 0x0 8. "FEN,FIFO enable" "0,1"
rbitfld.long 0x0 7. "TFF,Transmit FIFO full flag" "0,1"
newline
rbitfld.long 0x0 6. "TFE,Transmit FIFO empty flag" "0,1"
rbitfld.long 0x0 5. "TFT,Transmit FIFO threshold flag" "0,1"
rbitfld.long 0x0 4. "RFT,Receive FIFO threshold flag" "0,1"
rbitfld.long 0x0 1.--2. "RFCNT_3_4,Bit 3_4 of receive FIFO counter number" "0,1,2,3"
bitfld.long 0x0 0. "ELNACK,Early NACK when smartcard mode is selected" "0,1"
tree.end
tree "USART1"
base ad:0x40004400
group.long 0x0++0x17
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 31. "AMIE1,ADDR1 match interrupt enable" "0,1"
bitfld.long 0x0 28. "WL1,Word length 1" "0,1"
bitfld.long 0x0 27. "EBIE,End of Block interrupt enable" "0,1"
bitfld.long 0x0 26. "RTIE,Receiver timeout interrupt enable" "0,1"
hexmask.long.byte 0x0 21.--25. 1. "DEA,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DED,Driver Enable de-assertion time"
bitfld.long 0x0 15. "OVSMOD,Oversample mode" "0,1"
bitfld.long 0x0 14. "AMIE0,ADDR0 match interrupt enable" "0,1"
newline
bitfld.long 0x0 13. "MEN,Mute mode enable" "0,1"
bitfld.long 0x0 12. "WL0,Word length" "0,1"
bitfld.long 0x0 11. "WM,Wakeup method in mute mode" "0,1"
bitfld.long 0x0 10. "PCEN,Parity control enable" "0,1"
bitfld.long 0x0 9. "PM,Parity mode" "0,1"
bitfld.long 0x0 8. "PERRIE,Parity error interrupt enable" "0,1"
bitfld.long 0x0 7. "TBEIE_TFNFIE,Interrupt enable" "0,1"
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
newline
bitfld.long 0x0 5. "RBNEIE_RFNEIE,Interrupt enable" "0,1"
bitfld.long 0x0 4. "IDLEIE,IDLE line detected interrupt enable" "0,1"
bitfld.long 0x0 3. "TEN,Transmitter enable" "0,1"
bitfld.long 0x0 2. "REN,Receiver enable" "0,1"
bitfld.long 0x0 1. "UESM,USART enable in Deep-sleep mode" "0,1"
bitfld.long 0x0 0. "UEN,USART enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
hexmask.long.byte 0x4 24.--31. 1. "ADDR0,Address 0 of the USART terminal"
bitfld.long 0x4 23. "RTEN,Receiver timeout enable" "0,1"
bitfld.long 0x4 19. "MSBF,Most significant bit first" "0,1"
bitfld.long 0x4 18. "DINV,Data bit level inversion" "0,1"
bitfld.long 0x4 17. "TINV,TX pin level inversion" "0,1"
bitfld.long 0x4 16. "RINV,RX pin level inversion" "0,1"
bitfld.long 0x4 15. "STRP,Swap TX/RX pins" "0,1"
bitfld.long 0x4 14. "LMEN,LIN mode enable" "0,1"
newline
bitfld.long 0x4 12.--13. "STB,STOP bits length" "0,1,2,3"
bitfld.long 0x4 11. "CKEN,CK pin enable" "0,1"
bitfld.long 0x4 10. "CPL,Clock polarity" "0,1"
bitfld.long 0x4 9. "CPH,Clock phase" "0,1"
bitfld.long 0x4 8. "CLEN,CK length" "0,1"
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
bitfld.long 0x4 5. "LBLEN,LIN break frame length" "0,1"
bitfld.long 0x4 4. "ADDM0,Address detection mode 0" "0,1"
newline
bitfld.long 0x4 0. "AMEN0,Match Address Mode Enable 0" "0,1"
line.long 0x8 "CTL2,Control register 2"
hexmask.long.byte 0x8 24.--31. 1. "ADDR1,Address 1 of the USART terminal"
bitfld.long 0x8 23. "ADDM1,Address detection mode 1" "0,1"
bitfld.long 0x8 22. "WUIE,Wakeup from Deep-sleep mode interrupt enable" "0,1"
bitfld.long 0x8 20.--21. "WUM,Wakeup mode from Deep-sleep mode" "0,1,2,3"
bitfld.long 0x8 17.--19. "SCRTNUM,Smartcard auto-retry number" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 16. "AMEN1,Match Address Mode Enable 1" "0,1"
bitfld.long 0x8 15. "DEP,Driver enable polarity mode" "0,1"
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
newline
bitfld.long 0x8 13. "DDRE,Disable DMA on reception error" "0,1"
bitfld.long 0x8 12. "OVRD,Overrun disable" "0,1"
bitfld.long 0x8 11. "OSB,One sample bit method" "0,1"
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
bitfld.long 0x8 9. "CTSEN,CTS enable" "0,1"
bitfld.long 0x8 8. "RTSEN,RTS enable" "0,1"
bitfld.long 0x8 7. "DENT,DMA enable for transmission" "0,1"
bitfld.long 0x8 6. "DENR,DMA enable for reception" "0,1"
newline
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
bitfld.long 0x8 4. "NKEN,NACK enable in Smartcard mode" "0,1"
bitfld.long 0x8 3. "HDEN,Half-duplex enable" "0,1"
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0,1"
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0,1"
bitfld.long 0x8 0. "ERRIE,Error interrupt enable" "0,1"
line.long 0xC "BAUD,Baud rate generator register"
hexmask.long.word 0xC 4.--15. 1. "BRR_INT,Integer of baud-rate divider"
hexmask.long.byte 0xC 0.--3. 1. "BRR_DIV,Fraction of baud-rate divider"
line.long 0x10 "GP,Prescaler and guard time configuration register"
hexmask.long.byte 0x10 8.--15. 1. "GUAT,Guard time value in smartcard mode"
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value for dividing the system clock"
line.long 0x14 "RT,Receiver timeout register"
hexmask.long.byte 0x14 24.--31. 1. "BL,Block Length"
hexmask.long.tbyte 0x14 0.--23. 1. "RT,Receiver timeout threshold"
wgroup.long 0x18++0x3
line.long 0x0 "CMD,Command register"
bitfld.long 0x0 4. "TXFCMD,Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFCMD,Receive data flush command" "0,1"
bitfld.long 0x0 2. "MMCMD,Mute mode command" "0,1"
bitfld.long 0x0 1. "SBKCMD,Send break command" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "STAT,Status register"
bitfld.long 0x0 22. "REA,Receive enable acknowledge flag" "0,1"
bitfld.long 0x0 21. "TEA,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 20. "WUF,Wakeup from Deep-sleep mode flag" "0,1"
bitfld.long 0x0 19. "RWU,Receiver wakeup from mute mode" "0,1"
bitfld.long 0x0 18. "SBF,Send break flag" "0,1"
bitfld.long 0x0 17. "AMF0,ADDR0 match flag" "0,1"
bitfld.long 0x0 16. "BSY,Busy flag" "0,1"
bitfld.long 0x0 13. "AMF1,ADDR1 match flag" "0,1"
newline
bitfld.long 0x0 12. "EBF,End of block flag" "0,1"
bitfld.long 0x0 11. "RTF,Receiver timeout flag" "0,1"
bitfld.long 0x0 10. "CTS,CTS level" "0,1"
bitfld.long 0x0 9. "CTSF,CTS change flag" "0,1"
bitfld.long 0x0 8. "LBDF,LIN break detected flag" "0,1"
bitfld.long 0x0 7. "TBE_TFNF,When FIFO is disabled:" "0,1"
bitfld.long 0x0 6. "TC,Transmission completed" "0,1"
bitfld.long 0x0 5. "RBNE_RFNE,Interrupt enable" "0,1"
newline
bitfld.long 0x0 4. "IDLEF,IDLE line detected flag" "0,1"
bitfld.long 0x0 3. "ORERR,Overrun error" "0,1"
bitfld.long 0x0 2. "NERR,Noise error flag" "0,1"
bitfld.long 0x0 1. "FERR,Frame error flag" "0,1"
bitfld.long 0x0 0. "PERR,Parity error flag" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "INTC,Interrupt status clear register"
bitfld.long 0x0 20. "WUC,Wakeup from Deep-sleep mode clear" "0,1"
bitfld.long 0x0 17. "AMC0,ADDR0 match clear" "0,1"
bitfld.long 0x0 16. "AMC1,ADDR1 match clear" "0,1"
bitfld.long 0x0 12. "EBC,End of block clear" "0,1"
bitfld.long 0x0 11. "RTC,Receiver timeout clear" "0,1"
bitfld.long 0x0 9. "CTSC,CTS change clear" "0,1"
bitfld.long 0x0 8. "LBDC,LIN break detected clear" "0,1"
bitfld.long 0x0 6. "TCC,Transmission complete clear" "0,1"
newline
bitfld.long 0x0 4. "IDLEC,Idle line detected clear" "0,1"
bitfld.long 0x0 3. "OREC,Overrun error clear" "0,1"
bitfld.long 0x0 2. "NEC,Noise detected clear" "0,1"
bitfld.long 0x0 1. "FEC,Frame error flag clear" "0,1"
bitfld.long 0x0 0. "PEC,Parity error clear" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "RDATA,Receive data register"
hexmask.long.word 0x0 0.--9. 1. "RDATA,Receive Data value"
group.long 0x28++0x3
line.long 0x0 "TDATA,Transmit data register"
hexmask.long.word 0x0 0.--9. 1. "TDATA,Transmit Data value"
group.long 0xC0++0x3
line.long 0x0 "CHC,USART coherence control register"
bitfld.long 0x0 8. "EPERR,Early parity error flag" "0,1"
bitfld.long 0x0 0. "HCM,Hardware flow control coherence mode" "0,1"
group.long 0xD0++0x3
line.long 0x0 "RFCS,USART receive FIFO control and status register"
bitfld.long 0x0 31. "TFEIE,Transmit FIFO empty interrupt enable" "0,1"
bitfld.long 0x0 29. "TFTIE,Transmit FIFO threshold interrupt enable" "0,1"
bitfld.long 0x0 27. "RFTIE,Receive FIFO threshold interrupt enable" "0,1"
bitfld.long 0x0 26. "TFEC,Transmit FIFO empty flag clear" "0,1"
rbitfld.long 0x0 25. "TFTIF,Transmit FIFO threshold interrupt flag" "0,1"
rbitfld.long 0x0 24. "TFEIF,Transmit FIFO empty interrupt flag" "0,1"
rbitfld.long 0x0 22. "RFTIF,Receive FIFO threshold interrupt flag" "0,1"
bitfld.long 0x0 19.--21. "TFTCFG,Transmit FIFO threshold configuration" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16.--18. "RFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "RFFIF,Receive FIFO full interrupt flag" "0,1"
rbitfld.long 0x0 12.--14. "RFCNT,Receive FIFO counter number" "0,1,2,3,4,5,6,7"
rbitfld.long 0x0 11. "RFF,Receive FIFO full flag" "0,1"
rbitfld.long 0x0 10. "RFE,Receive FIFO empty flag" "0,1"
bitfld.long 0x0 9. "RFFIE,Receive FIFO full interrupt enable" "0,1"
bitfld.long 0x0 8. "FEN,FIFO enable" "0,1"
rbitfld.long 0x0 7. "TFF,Transmit FIFO full flag" "0,1"
newline
rbitfld.long 0x0 6. "TFE,Transmit FIFO empty flag" "0,1"
rbitfld.long 0x0 5. "TFT,Transmit FIFO threshold flag" "0,1"
rbitfld.long 0x0 4. "RFT,Receive FIFO threshold flag" "0,1"
rbitfld.long 0x0 1.--2. "RFCNT_3_4,Bit 3_4 of receive FIFO counter number" "0,1,2,3"
bitfld.long 0x0 0. "ELNACK,Early NACK when smartcard mode is selected" "0,1"
tree.end
tree "USART2"
base ad:0x40004800
group.long 0x0++0x17
line.long 0x0 "CTL0,Control register 0"
bitfld.long 0x0 31. "AMIE1,ADDR1 match interrupt enable" "0,1"
bitfld.long 0x0 28. "WL1,Word length 1" "0,1"
bitfld.long 0x0 27. "EBIE,End of Block interrupt enable" "0,1"
bitfld.long 0x0 26. "RTIE,Receiver timeout interrupt enable" "0,1"
hexmask.long.byte 0x0 21.--25. 1. "DEA,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DED,Driver Enable de-assertion time"
bitfld.long 0x0 15. "OVSMOD,Oversample mode" "0,1"
bitfld.long 0x0 14. "AMIE0,ADDR0 match interrupt enable" "0,1"
newline
bitfld.long 0x0 13. "MEN,Mute mode enable" "0,1"
bitfld.long 0x0 12. "WL0,Word length" "0,1"
bitfld.long 0x0 11. "WM,Wakeup method in mute mode" "0,1"
bitfld.long 0x0 10. "PCEN,Parity control enable" "0,1"
bitfld.long 0x0 9. "PM,Parity mode" "0,1"
bitfld.long 0x0 8. "PERRIE,Parity error interrupt enable" "0,1"
bitfld.long 0x0 7. "TBEIE_TFNFIE,Interrupt enable" "0,1"
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
newline
bitfld.long 0x0 5. "RBNEIE_RFNEIE,Interrupt enable" "0,1"
bitfld.long 0x0 4. "IDLEIE,IDLE line detected interrupt enable" "0,1"
bitfld.long 0x0 3. "TEN,Transmitter enable" "0,1"
bitfld.long 0x0 2. "REN,Receiver enable" "0,1"
bitfld.long 0x0 1. "UESM,USART enable in Deep-sleep mode" "0,1"
bitfld.long 0x0 0. "UEN,USART enable" "0,1"
line.long 0x4 "CTL1,Control register 1"
hexmask.long.byte 0x4 24.--31. 1. "ADDR0,Address 0 of the USART terminal"
bitfld.long 0x4 23. "RTEN,Receiver timeout enable" "0,1"
bitfld.long 0x4 19. "MSBF,Most significant bit first" "0,1"
bitfld.long 0x4 18. "DINV,Data bit level inversion" "0,1"
bitfld.long 0x4 17. "TINV,TX pin level inversion" "0,1"
bitfld.long 0x4 16. "RINV,RX pin level inversion" "0,1"
bitfld.long 0x4 15. "STRP,Swap TX/RX pins" "0,1"
bitfld.long 0x4 14. "LMEN,LIN mode enable" "0,1"
newline
bitfld.long 0x4 12.--13. "STB,STOP bits length" "0,1,2,3"
bitfld.long 0x4 11. "CKEN,CK pin enable" "0,1"
bitfld.long 0x4 10. "CPL,Clock polarity" "0,1"
bitfld.long 0x4 9. "CPH,Clock phase" "0,1"
bitfld.long 0x4 8. "CLEN,CK length" "0,1"
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
bitfld.long 0x4 5. "LBLEN,LIN break frame length" "0,1"
bitfld.long 0x4 4. "ADDM0,Address detection mode 0" "0,1"
newline
bitfld.long 0x4 0. "AMEN0,Match Address Mode Enable 0" "0,1"
line.long 0x8 "CTL2,Control register 2"
hexmask.long.byte 0x8 24.--31. 1. "ADDR1,Address 1 of the USART terminal"
bitfld.long 0x8 23. "ADDM1,Address detection mode 1" "0,1"
bitfld.long 0x8 22. "WUIE,Wakeup from Deep-sleep mode interrupt enable" "0,1"
bitfld.long 0x8 20.--21. "WUM,Wakeup mode from Deep-sleep mode" "0,1,2,3"
bitfld.long 0x8 17.--19. "SCRTNUM,Smartcard auto-retry number" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 16. "AMEN1,Match Address Mode Enable 1" "0,1"
bitfld.long 0x8 15. "DEP,Driver enable polarity mode" "0,1"
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
newline
bitfld.long 0x8 13. "DDRE,Disable DMA on reception error" "0,1"
bitfld.long 0x8 12. "OVRD,Overrun disable" "0,1"
bitfld.long 0x8 11. "OSB,One sample bit method" "0,1"
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
bitfld.long 0x8 9. "CTSEN,CTS enable" "0,1"
bitfld.long 0x8 8. "RTSEN,RTS enable" "0,1"
bitfld.long 0x8 7. "DENT,DMA enable for transmission" "0,1"
bitfld.long 0x8 6. "DENR,DMA enable for reception" "0,1"
newline
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
bitfld.long 0x8 4. "NKEN,NACK enable in Smartcard mode" "0,1"
bitfld.long 0x8 3. "HDEN,Half-duplex enable" "0,1"
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0,1"
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0,1"
bitfld.long 0x8 0. "ERRIE,Error interrupt enable" "0,1"
line.long 0xC "BAUD,Baud rate generator register"
hexmask.long.word 0xC 4.--15. 1. "BRR_INT,Integer of baud-rate divider"
hexmask.long.byte 0xC 0.--3. 1. "BRR_DIV,Fraction of baud-rate divider"
line.long 0x10 "GP,Prescaler and guard time configuration register"
hexmask.long.byte 0x10 8.--15. 1. "GUAT,Guard time value in smartcard mode"
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value for dividing the system clock"
line.long 0x14 "RT,Receiver timeout register"
hexmask.long.byte 0x14 24.--31. 1. "BL,Block Length"
hexmask.long.tbyte 0x14 0.--23. 1. "RT,Receiver timeout threshold"
wgroup.long 0x18++0x3
line.long 0x0 "CMD,Command register"
bitfld.long 0x0 4. "TXFCMD,Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFCMD,Receive data flush command" "0,1"
bitfld.long 0x0 2. "MMCMD,Mute mode command" "0,1"
bitfld.long 0x0 1. "SBKCMD,Send break command" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "STAT,Status register"
bitfld.long 0x0 22. "REA,Receive enable acknowledge flag" "0,1"
bitfld.long 0x0 21. "TEA,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 20. "WUF,Wakeup from Deep-sleep mode flag" "0,1"
bitfld.long 0x0 19. "RWU,Receiver wakeup from mute mode" "0,1"
bitfld.long 0x0 18. "SBF,Send break flag" "0,1"
bitfld.long 0x0 17. "AMF0,ADDR0 match flag" "0,1"
bitfld.long 0x0 16. "BSY,Busy flag" "0,1"
bitfld.long 0x0 13. "AMF1,ADDR1 match flag" "0,1"
newline
bitfld.long 0x0 12. "EBF,End of block flag" "0,1"
bitfld.long 0x0 11. "RTF,Receiver timeout flag" "0,1"
bitfld.long 0x0 10. "CTS,CTS level" "0,1"
bitfld.long 0x0 9. "CTSF,CTS change flag" "0,1"
bitfld.long 0x0 8. "LBDF,LIN break detected flag" "0,1"
bitfld.long 0x0 7. "TBE_TFNF,When FIFO is disabled:" "0,1"
bitfld.long 0x0 6. "TC,Transmission completed" "0,1"
bitfld.long 0x0 5. "RBNE_RFNE,Interrupt enable" "0,1"
newline
bitfld.long 0x0 4. "IDLEF,IDLE line detected flag" "0,1"
bitfld.long 0x0 3. "ORERR,Overrun error" "0,1"
bitfld.long 0x0 2. "NERR,Noise error flag" "0,1"
bitfld.long 0x0 1. "FERR,Frame error flag" "0,1"
bitfld.long 0x0 0. "PERR,Parity error flag" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "INTC,Interrupt status clear register"
bitfld.long 0x0 20. "WUC,Wakeup from Deep-sleep mode clear" "0,1"
bitfld.long 0x0 17. "AMC0,ADDR0 match clear" "0,1"
bitfld.long 0x0 16. "AMC1,ADDR1 match clear" "0,1"
bitfld.long 0x0 12. "EBC,End of block clear" "0,1"
bitfld.long 0x0 11. "RTC,Receiver timeout clear" "0,1"
bitfld.long 0x0 9. "CTSC,CTS change clear" "0,1"
bitfld.long 0x0 8. "LBDC,LIN break detected clear" "0,1"
bitfld.long 0x0 6. "TCC,Transmission complete clear" "0,1"
newline
bitfld.long 0x0 4. "IDLEC,Idle line detected clear" "0,1"
bitfld.long 0x0 3. "OREC,Overrun error clear" "0,1"
bitfld.long 0x0 2. "NEC,Noise detected clear" "0,1"
bitfld.long 0x0 1. "FEC,Frame error flag clear" "0,1"
bitfld.long 0x0 0. "PEC,Parity error clear" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "RDATA,Receive data register"
hexmask.long.word 0x0 0.--9. 1. "RDATA,Receive Data value"
group.long 0x28++0x3
line.long 0x0 "TDATA,Transmit data register"
hexmask.long.word 0x0 0.--9. 1. "TDATA,Transmit Data value"
group.long 0xC0++0x3
line.long 0x0 "CHC,USART coherence control register"
bitfld.long 0x0 8. "EPERR,Early parity error flag" "0,1"
bitfld.long 0x0 0. "HCM,Hardware flow control coherence mode" "0,1"
group.long 0xD0++0x3
line.long 0x0 "RFCS,USART receive FIFO control and status register"
bitfld.long 0x0 31. "TFEIE,Transmit FIFO empty interrupt enable" "0,1"
bitfld.long 0x0 29. "TFTIE,Transmit FIFO threshold interrupt enable" "0,1"
bitfld.long 0x0 27. "RFTIE,Receive FIFO threshold interrupt enable" "0,1"
bitfld.long 0x0 26. "TFEC,Transmit FIFO empty flag clear" "0,1"
rbitfld.long 0x0 25. "TFTIF,Transmit FIFO threshold interrupt flag" "0,1"
rbitfld.long 0x0 24. "TFEIF,Transmit FIFO empty interrupt flag" "0,1"
rbitfld.long 0x0 22. "RFTIF,Receive FIFO threshold interrupt flag" "0,1"
bitfld.long 0x0 19.--21. "TFTCFG,Transmit FIFO threshold configuration" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16.--18. "RFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "RFFIF,Receive FIFO full interrupt flag" "0,1"
rbitfld.long 0x0 12.--14. "RFCNT,Receive FIFO counter number" "0,1,2,3,4,5,6,7"
rbitfld.long 0x0 11. "RFF,Receive FIFO full flag" "0,1"
rbitfld.long 0x0 10. "RFE,Receive FIFO empty flag" "0,1"
bitfld.long 0x0 9. "RFFIE,Receive FIFO full interrupt enable" "0,1"
bitfld.long 0x0 8. "FEN,FIFO enable" "0,1"
rbitfld.long 0x0 7. "TFF,Transmit FIFO full flag" "0,1"
newline
rbitfld.long 0x0 6. "TFE,Transmit FIFO empty flag" "0,1"
rbitfld.long 0x0 5. "TFT,Transmit FIFO threshold flag" "0,1"
rbitfld.long 0x0 4. "RFT,Receive FIFO threshold flag" "0,1"
rbitfld.long 0x0 1.--2. "RFCNT_3_4,Bit 3_4 of receive FIFO counter number" "0,1,2,3"
bitfld.long 0x0 0. "ELNACK,Early NACK when smartcard mode is selected" "0,1"
tree.end
tree.end
tree "VREF (Voltage Reference Unit)"
base ad:0x40017800
group.long 0x0++0x7
line.long 0x0 "CS,Control and status register"
bitfld.long 0x0 4.--5. "VREFS,Voltage reference select" "0,1,2,3"
rbitfld.long 0x0 3. "VREFRDY,VREF ready" "0,1"
bitfld.long 0x0 1. "HIPM,High impedance mode" "0,1"
bitfld.long 0x0 0. "VREFEN,VREF enable" "0,1"
line.long 0x4 "CALIB,Calibration register"
hexmask.long.byte 0x4 0.--5. 1. "VREFCAL,VREF calibration"
tree.end
tree "WWDGT (Window Watchdog Timer)"
base ad:0x40002C00
group.long 0x0++0xB
line.long 0x0 "CTL,Control register"
bitfld.long 0x0 7. "WDGTEN,Activation bit" "0,1"
hexmask.long.byte 0x0 0.--6. 1. "CNT,7-bit counter"
line.long 0x4 "CFG,Configuration register"
bitfld.long 0x4 9. "EWIE,Early wakeup interrupt" "0,1"
bitfld.long 0x4 7.--8. "PSC,Prescaler" "0,1,2,3"
hexmask.long.byte 0x4 0.--6. 1. "WIN,7-bit window value"
line.long 0x8 "STAT,Status register"
bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag" "0,1"
tree.end
newline
AUTOINDENT.OFF
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