46347 lines
3.1 MiB
46347 lines
3.1 MiB
; --------------------------------------------------------------------------------
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; @Title: PSoC6 On-Chip Peripherals
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; @Props: Released
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; @Author: KRZ
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; @Changelog: 2025-03-12 KRZ
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; @Manufacturer: INFINEON - Infineon Technologies AG
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; @Doc: Generated (TRACE32, build: 178045.), based on:
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; psoc6_01.svd, psoc6_02.svd, psoc6_03.svd, psoc6_04.svd (CAT1A_DFP 1.6.0)
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; @Core: Cortex-M4F, Cortex-M0+
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; @Chip: CY8C61*, CY8C62*, CY8C63*, CYB064*, CYS064*
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; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
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; or an affiliate of Cypress Semiconductor Corporation.
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;
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; SPDX-License-Identifier: Apache-2.0
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;
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; Licensed under the Apache License, Version 2.0 (the "License");
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; you may not use this file except in compliance with the License.
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; You may obtain a copy of the License at\n
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;
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; http://www.apache.org/licenses/LICENSE-2.0
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;
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; Unless required by applicable law or agreed to in writing, software
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; distributed under the License is distributed on an "AS IS" BASIS,
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; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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; See the License for the specific language governing permissions and
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; limitations under the License.
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; --------------------------------------------------------------------------------
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; $Id: perpsoc6.per 19220 2025-03-13 10:33:01Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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sif (CORENAME()=="CORTEXM4F")
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,ARMv7-M"
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newline
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC24=Cortex-M4"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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|
textline " "
|
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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|
textline " "
|
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
|
|
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
sif (CORENAME()=="CORTEXM0+")
|
|
tree.close "Core Registers (Cortex-M0+)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0x8
|
|
if (CORENAME()=="CORTEXM1")
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
else
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
endif
|
|
if (CORENAME()=="CORTEXM1")
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
|
|
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
|
|
else
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
|
|
endif
|
|
if (CORENAME()=="CORTEXM1")
|
|
rgroup.long 0xd00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
|
|
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
|
|
textline " "
|
|
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC21=Cortex-M1"
|
|
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
|
|
elif (CORENAME()=="CORTEXM0+")
|
|
rgroup.long 0xd00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
|
|
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
|
|
textline " "
|
|
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC60=Cortex-M0+"
|
|
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
|
|
else
|
|
rgroup.long 0xd00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
|
|
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
|
|
textline " "
|
|
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC20=Cortex-M0"
|
|
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
|
|
endif
|
|
group.long 0xd04++0x03
|
|
line.long 0x00 "ICSR,Interrupt Control State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
|
|
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
|
|
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
|
|
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
group.long 0xd08++0x03
|
|
line.long 0x00 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
|
|
else
|
|
textline " "
|
|
endif
|
|
group.long 0xd0c++0x03
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
|
|
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
|
|
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
|
|
group.long 0xd10++0x03
|
|
line.long 0x00 "SCR,System Control Register"
|
|
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
rgroup.long 0xd14++0x03
|
|
line.long 0x00 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
|
|
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
|
|
group.long 0xd1c++0x0b
|
|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
|
|
line.long 0x04 "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
|
|
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
|
|
line.long 0x08 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
else
|
|
textline " "
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
tree "BACKUP (SRSS Backup Domain)"
|
|
base ad:0x40270000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "EN_CHARGE_KEY,When set to 3C the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A.."
|
|
bitfld.long 0x0 19. "VBACKUP_MEAS,Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup so it is within the supply range of the ADC." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "VDDBAK_CTL,Controls the behavior of the switch that generates vddbak from vbackup or vddd." "0: automatically select vddd if its brownout..,?,?,3: force vddbak and vmax to select vbackup"
|
|
bitfld.long 0x0 16. "WCO_BYPASS,Configures the WCO for different board-level connections to the WCO pins. For example this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases the two related GPIO pins (WCO input and.." "0: Watch crystal,1: Clock signal"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "PRESCALER,N/A" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CLK_SEL,Clock select for BAK clock" "0: Watch-crystal oscillator input.,1: This allows to use the LFCLK selection as an..,?,?"
|
|
newline
|
|
bitfld.long 0x0 3. "WCO_EN,Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared the WCO will be internally kept on until the write completes." "0,1"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "RTC_RW,RTC Read Write register"
|
|
bitfld.long 0x0 1. "WRITE,Write bit" "0,1"
|
|
bitfld.long 0x0 0. "READ,Read bit" "0,1"
|
|
line.long 0x4 "CAL_CTL,Oscillator calibration for absolute frequency"
|
|
bitfld.long 0x4 31. "CAL_OUT,Output enable for 512Hz signal for calibration and allow CALIB_VAL to be written. Note that calibration does not affect the 512Hz output signal." "0,1"
|
|
bitfld.long 0x4 6. "CALIB_SIGN,Calibration sign:" "0: Negative sign: remove pulses,1: Positive sign: add pulses"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "CALIB_VAL,Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/(60*60*32 768))."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 2. "WCO_OK,Indicates that output has transitioned." "0,1"
|
|
bitfld.long 0x0 0. "RTC_BUSY,pending RTC write" "0,1"
|
|
group.long 0x14++0x23
|
|
line.long 0x0 "RTC_TIME,Calendar Seconds. Minutes. Hours. Day of Week"
|
|
bitfld.long 0x0 24.--26. "RTC_DAY,Calendar Day of the week in BCD 1-7" "?,1: Monday is recommended,?,?,?,?,?,?"
|
|
bitfld.long 0x0 22. "CTRL_12HR,Select 12/24HR mode: 1=12HR 0=24HR" "0: 24HR,1: 12HR"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "RTC_HOUR,Calendar hours in BCD value depending on 12/24HR mode"
|
|
hexmask.long.byte 0x0 8.--14. 1. "RTC_MIN,Calendar minutes in BCD 0-59"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "RTC_SEC,Calendar seconds in BCD 0-59"
|
|
line.long 0x4 "RTC_DATE,Calendar Day of Month. Month. Year"
|
|
hexmask.long.byte 0x4 16.--23. 1. "RTC_YEAR,Calendar year in BCD 0-99"
|
|
hexmask.long.byte 0x4 8.--12. 1. "RTC_MON,Calendar Month in BCD 1-12"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "RTC_DATE,Calendar Day of the Month in BCD 1-31"
|
|
line.long 0x8 "ALM1_TIME,Alarm 1 Seconds. Minute. Hours. Day of Week"
|
|
bitfld.long 0x8 31. "ALM_DAY_EN,Alarm Day of the Week enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
bitfld.long 0x8 24.--26. "ALM_DAY,Alarm Day of the week in BCD 1-7" "?,1: Monday is recommended,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x8 23. "ALM_HOUR_EN,Alarm hour enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
hexmask.long.byte 0x8 16.--21. 1. "ALM_HOUR,Alarm hours in BCD value depending on 12/24HR mode"
|
|
newline
|
|
bitfld.long 0x8 15. "ALM_MIN_EN,Alarm minutes enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
hexmask.long.byte 0x8 8.--14. 1. "ALM_MIN,Alarm minutes in BCD 0-59"
|
|
newline
|
|
bitfld.long 0x8 7. "ALM_SEC_EN,Alarm second enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
hexmask.long.byte 0x8 0.--6. 1. "ALM_SEC,Alarm seconds in BCD 0-59"
|
|
line.long 0xC "ALM1_DATE,Alarm 1 Day of Month. Month"
|
|
bitfld.long 0xC 31. "ALM_EN,Master enable for alarm 1." "0: Alarm 1 is disabled,1: Alarm 1 is enabled"
|
|
bitfld.long 0xC 15. "ALM_MON_EN,Alarm Month enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--12. 1. "ALM_MON,Alarm Month in BCD 1-12"
|
|
bitfld.long 0xC 7. "ALM_DATE_EN,Alarm Day of the Month enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "ALM_DATE,Alarm Day of the Month in BCD 1-31"
|
|
line.long 0x10 "ALM2_TIME,Alarm 2 Seconds. Minute. Hours. Day of Week"
|
|
bitfld.long 0x10 31. "ALM_DAY_EN,Alarm Day of the Week enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
bitfld.long 0x10 24.--26. "ALM_DAY,Alarm Day of the week in BCD 1-7" "?,1: Monday is recommended,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x10 23. "ALM_HOUR_EN,Alarm hour enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
hexmask.long.byte 0x10 16.--21. 1. "ALM_HOUR,Alarm hours in BCD value depending on 12/24HR mode"
|
|
newline
|
|
bitfld.long 0x10 15. "ALM_MIN_EN,Alarm minutes enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
hexmask.long.byte 0x10 8.--14. 1. "ALM_MIN,Alarm minutes in BCD 0-59"
|
|
newline
|
|
bitfld.long 0x10 7. "ALM_SEC_EN,Alarm second enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
hexmask.long.byte 0x10 0.--6. 1. "ALM_SEC,Alarm seconds in BCD 0-59"
|
|
line.long 0x14 "ALM2_DATE,Alarm 2 Day of Month. Month"
|
|
bitfld.long 0x14 31. "ALM_EN,Master enable for alarm 2." "0: Alarm 2 is disabled,1: Alarm 2 is enabled"
|
|
bitfld.long 0x14 15. "ALM_MON_EN,Alarm Month enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--12. 1. "ALM_MON,Alarm Month in BCD 1-12"
|
|
bitfld.long 0x14 7. "ALM_DATE_EN,Alarm Day of the Month enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--5. 1. "ALM_DATE,Alarm Day of the Month in BCD 1-31"
|
|
line.long 0x18 "INTR,Interrupt request register"
|
|
bitfld.long 0x18 2. "CENTURY,Century overflow interrupt" "0,1"
|
|
bitfld.long 0x18 1. "ALARM2,Alarm 2 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "ALARM1,Alarm 1 Interrupt" "0,1"
|
|
line.long 0x1C "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x1C 2. "CENTURY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x1C 1. "ALARM2,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ALARM1,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x20 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x20 2. "CENTURY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x20 1. "ALARM2,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "ALARM1,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0x38++0xB
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 2. "CENTURY,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 1. "ALARM2,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ALARM1,Logical and of corresponding request and mask bits." "0,1"
|
|
line.long 0x4 "OSCCNT,32kHz oscillator counter"
|
|
hexmask.long.byte 0x4 0.--7. 1. "CNT32KHZ,32kHz oscillator count (msb=128Hz) calibration can cause bit 6 to skip. Reset when RTC_TIME.RTC_SEC fields is written."
|
|
line.long 0x8 "TICKS,128Hz tick counter"
|
|
hexmask.long.byte 0x8 0.--5. 1. "CNT128HZ,128Hz counter (msb=2Hz)"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "PMIC_CTL,PMIC control register"
|
|
bitfld.long 0x0 31. "PMIC_EN,Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0 the system functions normally until vddd is no longer present.." "0,1"
|
|
bitfld.long 0x0 30. "PMIC_ALWAYSEN,Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware." "0: Normal operation,1: PMIC_EN and PMIC_OUTEN are ignored and the.."
|
|
newline
|
|
bitfld.long 0x0 29. "PMIC_EN_OUTEN,Output enable for the output driver in the PMIC_EN pad." "0: Output pad is tristate for PMIC_EN pin,1: Output pad is enabled for PMIC_EN pin"
|
|
bitfld.long 0x0 16. "POLARITY,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "UNLOCK,This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the.."
|
|
line.long 0x4 "RESET,Backup reset register"
|
|
bitfld.long 0x4 31. "RESET,Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register firmware should confirm it reads as 0 before attempting to write other backup registers." "0,1"
|
|
group.long 0xFF00++0x3
|
|
line.long 0x0 "TRIM,Trim Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TRIM,WCO trim"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1000)++0x3
|
|
line.long 0x0 "BREG[$1],Backup register region"
|
|
hexmask.long 0x0 0.--31. 1. "BREG,Backup memory that contains application-specific data. Memory is retained on vbackup supply."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1000)++0x3
|
|
line.long 0x0 "BREG[$1],Backup register region"
|
|
hexmask.long 0x0 0.--31. 1. "BREG,Backup memory that contains application-specific data. Memory is retained on vbackup supply."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1000)++0x3
|
|
line.long 0x0 "BREG[$1],Backup register region"
|
|
hexmask.long 0x0 0.--31. 1. "BREG,Backup memory that contains application-specific data. Memory is retained on vbackup supply."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1000)++0x3
|
|
line.long 0x0 "BREG[$1],Backup register region"
|
|
hexmask.long 0x0 0.--31. 1. "BREG,Backup memory that contains application-specific data. Memory is retained on vbackup supply."
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("CY8C6??6*")||cpuis("CYB06??6*")||cpuis("CYS06??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??7*")||cpuis("CYS06??7*"))
|
|
tree "BLE (Bluetooth Low Energy Subsystem)"
|
|
base ad:0x403C0000
|
|
tree "BLELL (Bluetooth Low Energy Link Layer)"
|
|
base ad:0x403C1000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "COMMAND_REGISTER,Instruction Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "COMMAND,N/A"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "EVENT_INTR,Event(Interrupt) status and Clear register"
|
|
rbitfld.long 0x0 7. "RSSI_RX_DONE_INTR,RSSI RX done interrupt." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 6. "ENC_INTR,Encryption module interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DSM_INTR,Read: Deep sleep mode exit interrupt. This bit is set when link layer hardware exits from deep sleep mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SM_INTR,Read: Sleep-mode-exit interrupt. This bit is set when link layer hardware exits from sleep mode." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "CONN_INTR,Connection interrupt. If bit is set to 1 it indicates an event occurred in the connection operation. This interrupt is aggregation of interrupts for all the connections. The source of the event for the specific connection needs to be read.." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 2. "INIT_INTR,Initiator interrupt. If bit is set to 1 it indicates an event occurred in the initiating procedure. The source of the event needs to be read from the INIT_INTR register." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "SCAN_INTR,Scanner interrupt. If bit is set to 1 it indicates an event occurred in the scanning procedure. The source of the event needs to be read from the SCAN_INTR register." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 0. "ADV_INTR,Advertiser interrupt. If bit is set to 1 it indicates an event occurred in the advertising procedure. The source of the event needs to be read from the ADV_INTR register." "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "EVENT_ENABLE,Event indications enable."
|
|
bitfld.long 0x0 7. "RSSI_RX_DONE_INT_EN,RSSI Rx interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ENC_INT_EN,Encryption module interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DSM_INT_EN,Deep Sleep-mode-exit interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SM_INT_EN,Sleep-mode-exit interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CONN_INT_EN,Connection interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "INIT_INT_EN,Initiator interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SCN_INT_EN,Scanner interrupt enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ADV_INT_EN,Advertiser interrupt enable." "0,1"
|
|
group.long 0x18++0xB
|
|
line.long 0x0 "ADV_PARAMS,Advertising parameters register."
|
|
rbitfld.long 0x0 15. "RCV_TX_ADDR,Transmit address field of the received packet extracted from the receive packet. This field is used by firmware to report peer_addr_type parameter in the connection complete event." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "ADV_RPT_PEER_NRPA_ADDR_IN_PRIV,Advertiser behavior when a peer Non Resolvable Private Address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. This is applicable when whitelist is disabled." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ADV_RCV_IA_IN_PRIV,Advertiser behavior when a peer Identity address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TX_ADDR_PRIV,Device own address type subtype when Address type is random. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "INITA_RPA_CHECK,This bit field is used to specify the Advertiser behavior on receiving the same INITA in the connect_req as in the ADV_DIRECT_IND packet it sent. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ADV_LOW_DUTY_CYCLE,This bit field is used to specify to the Controller the Low Duty Cycle connectable directed advertising variant being used." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RX_SEC_ADDR,Peer secondary addresses type. This is the Direct_Address_type field programmed only if ADV_DIRECT_IND type is sent. This address type corresponds to the PEER_SERC_ADDR register. Valid only if PRIV_1_2_ADV is set." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RX_ADDR,Peer addresses type. This is the Direct_Address_type field programmed only if ADV_DIRECT_IND type is sent." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5.--7. "ADV_CHANNEL_MAP,Advertising channel map indicates the advertising channels used for advertising. By setting the bit corresponding channel is enabled for use. Atleast one channel bit should be set." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "ADV_FILT_POLICY,Advertising filter policy. The set of devices that the advertising procedure uses for device filtering is called the White List." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "ADV_TYPE,The Advertising type is used to determine the packet type that is used for advertising when advertising is enabled." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0. "TX_ADDR,Device own address type." "0,1"
|
|
line.long 0x4 "ADV_INTERVAL_TIMEOUT,Advertising interval register."
|
|
hexmask.long.word 0x4 0.--14. 1. "ADV_INTERVAL,Range: 0x0020 to 0x4000 (For ADV_IND)"
|
|
line.long 0x8 "ADV_INTR,Advertising interrupt status and Clear register"
|
|
bitfld.long 0x8 12. "SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR,If this bit is set it indicates that an Identity address is received from an initiator and matches an entry in the resolving list but peer IRK is set and hence a corresponding RPA is expected from the initiator" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "INIT_ADDR_MATCH_PRIV_MISMATCH_INTR,If this bit is set it indicates that an Identity address is received from a Scanner and matches an entry in the resolving list but peer IRK is set and hence a corresponding RPA is expected from the Scanner" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SCAN_REQ_RX_PEER_RPA_UNMCH_INTR,If this bit is set it indicates scan request packet received but the peer device Resolvable Private Address is not resolved/ ID or NRPA are not matched yet." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SLV_CONN_PEER_RPA_UNMCH_INTR,If this bit is set it indicates that connection is created as slave but the peer device Resolvable Private Address is not resolved/ ID or NRPA are not matched yet. If the address is not resolved prior to connection.." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "ADV_ON,Advertiser procedure is ON in hardware. Indicates that advertiser procedure is ON in hardware." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "ADV_TIMEOUT,If this bit is set it indicates that the directed advertising event has timed out after 1.28 seconds. Applicable in adv_direct_ind advertising." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "SLV_CONNECTED,If this bit is set it indicates that connection is created as slave." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "CONN_REQ_RX_INTR,If this bit is set it indicates connect request packet is received." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "SCAN_REQ_RX_INTR,If this bit is set it indicates scan request packet received." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "SCAN_RSP_TX_INTR,If this bit is set it indicates scan response packet transmitted in response to previous scan request packet received." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADV_TX_INTR,If this bit is set it indicates ADV packet is transmitted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "ADV_CLOSE_INTR,If this bit is set it indicates current advertising event is closed." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ADV_STRT_INTR,If this bit is set it indicates a new advertising event started after interval expiry." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "ADV_NEXT_INSTANT,Advertising next instant."
|
|
hexmask.long.word 0x0 0.--15. 1. "ADV_NEXT_INSTANT,Shows the next start of advertising event with reference to the internal reference clock."
|
|
group.long 0x28++0xB
|
|
line.long 0x0 "SCAN_INTERVAL,Scan Interval Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SCAN_INTERVAL,Scan interval register. Interval between two consecutive scanning events. Firmware sets the scanning interval value to this register before issuing start scan command."
|
|
line.long 0x4 "SCAN_WINDOW,Scan window Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "SCAN_WINDOW,Duration of scan in a scanning event which should be less than or equal to scan interval value. Firmware sets the scan window value to this register before issuing start scan command."
|
|
line.long 0x8 "SCAN_PARAM,Scanning parameters register"
|
|
bitfld.long 0x8 9. "SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV,Scanner behavior when a peer Non Resolvable Private Address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. This is applicable when whitelist is disabled." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "SCAN_RCV_IA_IN_PRIV,Scanner behavior when a peer Identity address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "SCAN_RSP_ADVA_CHECK,This bit field is used to specify the Scanner behavior with respect to ADVA while receiving a SCAN_RSP packet. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "DUP_FILT_CHK_ADV_DIR,This bit field is used to specify the Scanner duplicate filter behavior for ADV_DIRECT_IND packet when duplicate DUP_FILT_EN is set. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DUP_FILT_EN,Filter duplicate packets." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3.--4. "SCAN_FILT_POLICY,The scanner filter policy determines how the scanner processes advertising packets." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 1.--2. "SCAN_TYPE,0x00 - passive scanning.(default)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 0. "TX_ADDR,Device's own address type." "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "SCAN_INTR,Scan interrupt status and Clear register"
|
|
bitfld.long 0x0 10. "SELF_ADDR_MATCH_PRIV_MISMATCH_INTR,If this bit is set it indicates that the self Identity address is received from an initiator and matches but self IRK is set and hence a corresponding RPA is expected from the initiator" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PEER_ADDR_MATCH_PRIV_MISMATCH_INTR,If this bit is set it indicates that an Identity address is received from an initiator and matches an entry in the resolving list but peer IRK is set and hence a corresponding RPA is expected from the initiator" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 8. "SCAN_ON,Scan procedure status." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SCANA_TX_ADDR_NOT_SET_INTR,If this bit is set it indicates that a valid ScanA RPA to be transmitted in SCAN_REQ packet in response to an ADV packet is not present in the resolving list" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ADV_RX_SELF_RPA_UNMCH_INTR,If this bit is set it indicates ADV_DIRECT packet received but the self device Resolvable Private Address is not resolved yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ADV_RX_PEER_RPA_UNMCH_INTR,If this bit is set it indicates ADV packet received but the peer device Address is not match yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SCAN_RSP_RX_INTR,If this bit is set it indicates SCAN_RSP packet is received. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADV_RX_INTR,If this bit is set it indicates ADV packet received. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SCAN_TX_INTR,If this bit is set it indicates scan request packet is transmitted." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SCAN_CLOSE_INTR,If this bit is set it indicates scan window is closed." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SCAN_STRT_INTR,If this bit is set it indicates scan window is opened." "0,1"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "SCAN_NEXT_INSTANT,Advertising next instant."
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT_SCAN_INSTANT,Shows the instant with respect to internal reference clock of resolution 625 us at which next scanning event begins."
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "INIT_INTERVAL,Initiator Interval Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INIT_SCAN_INTERVAL,Initiator interval register. Firmware sets the initiator's scanning interval value to this regis-ter before issuing create connection command. Interval between two consecutive scanning events."
|
|
line.long 0x4 "INIT_WINDOW,Initiator window Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "INIT_SCAN_WINDOW,Duration of scan in a scanning event which should be less than or equal to scan interval value. Firmware sets the scan window value to this register before issuing create connection command."
|
|
line.long 0x8 "INIT_PARAM,Initiator parameters register"
|
|
bitfld.long 0x8 4. "INIT_RCV_IA_IN_PRIV,Init behavior when a peer Identity address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "INIT_FILT_POLICY,The Initiator_Filter_Policy is used to determine whether the White List is used or not." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "RX_ADDR__RX_TX_ADDR,Peer address type." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TX_ADDR,Device' own address type." "0,1"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "INIT_INTR,Scan interrupt status and Clear register"
|
|
bitfld.long 0x0 9. "INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR,If this bit is set it indicates that" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR,If this bit is set it indicates that an Identity address is received from an initiator and matches an entry in the resolving list but peer IRK is set and hence a corresponding RPA is expected from the initiator" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "INITA_TX_ADDR_NOT_SET_INTR,If this bit is set it indicates that a valid INITA RPA to be transmitted in CONN_REQ packet in response to an ADV packet is not present in the resolving list" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ADV_RX_PEER_ADDR_UNMCH_INTR,If this bit is set it indicates ADV packet received but the peer device Address is not matched yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ADV_RX_SELF_ADDR_UNMCH_INTR,If this bit is set it indicates ADV_DIRECT packet received but the self device Resolvable Private Address is not resolved yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MASTER_CONN_CREATED,If this bit is set it indicates connection is created as master." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "INIT_TX_START_INTR,If this bit is set it indicates initiator packet (CONREQ) transmission has started." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INIT_CLOSE_WINDOW_INR,If this bit is set it indicates initiator scan window has finished." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "INIT_INTERVAL_EXPIRE_INTR,If this bit is set it indicates initiator scan window has started." "0,1"
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "INIT_NEXT_INSTANT,Initiator next instant."
|
|
hexmask.long.word 0x0 0.--15. 1. "INIT_NEXT_INSTANT,Shows the instant with respect to internal reference clock of resolution 625 us at which next initiator scanning event begins."
|
|
group.long 0x58++0xB
|
|
line.long 0x0 "DEVICE_RAND_ADDR_L,Lower 16 bit random address of the device."
|
|
hexmask.long.word 0x0 0.--15. 1. "DEVICE_RAND_ADDR_L,Lower 16 bit of 48-bit random address of the device."
|
|
line.long 0x4 "DEVICE_RAND_ADDR_M,Middle 16 bit random address of the device."
|
|
hexmask.long.word 0x4 0.--15. 1. "DEVICE_RAND_ADDR_M,Middle 16 bit of 48-bit random address of the device."
|
|
line.long 0x8 "DEVICE_RAND_ADDR_H,Higher 16 bit random address of the device."
|
|
hexmask.long.word 0x8 0.--15. 1. "DEVICE_RAND_ADDR_H,Higher 16 bit of 48-bit random address of the device."
|
|
group.long 0x68++0xB
|
|
line.long 0x0 "PEER_ADDR_L,Lower 16 bit address of the peer device."
|
|
hexmask.long.word 0x0 0.--15. 1. "PEER_ADDR_L,Lower 16 bit of 48-bit address of the peer device."
|
|
line.long 0x4 "PEER_ADDR_M,Middle 16 bit address of the peer device."
|
|
hexmask.long.word 0x4 0.--15. 1. "PEER_ADDR_M,Middle 16 bit of 48-bit address of the peer device."
|
|
line.long 0x8 "PEER_ADDR_H,Higher 16 bit address of the peer device."
|
|
hexmask.long.word 0x8 0.--15. 1. "PEER_ADDR_H,Higher 16 bit of 48-bit address of the peer device."
|
|
group.long 0x78++0x1B
|
|
line.long 0x0 "WL_ADDR_TYPE,whitelist address type"
|
|
hexmask.long.word 0x0 0.--15. 1. "WL_ADDR_TYPE,8 address type bits corresponding to the device address stored."
|
|
line.long 0x4 "WL_ENABLE,whitelist valid entry bit"
|
|
hexmask.long.word 0x4 0.--15. 1. "WL_ENABLE,Stores the valid entry bit corresponding to each of the eight device address stored in the whitelist."
|
|
line.long 0x8 "TRANSMIT_WINDOW_OFFSET,Transmit window offset"
|
|
hexmask.long.word 0x8 0.--15. 1. "TX_WINDOW_OFFSET,This is used to determine the first anchor point for the master transmission from the time of connection creation."
|
|
line.long 0xC "TRANSMIT_WINDOW_SIZE,Transmit window size"
|
|
hexmask.long.byte 0xC 0.--7. 1. "TX_WINDOW_SIZE,window_size along with the window_offset is used to calculate the first connection point anchor point for the master."
|
|
line.long 0x10 "DATA_CHANNELS_L0,Data channel map 0 (lower word)"
|
|
hexmask.long.word 0x10 0.--15. 1. "DATA_CHANNELS_L0,This register field indicates which of the data channels are in use. This stores the information for the lower 16 (15:0) data channel indices."
|
|
line.long 0x14 "DATA_CHANNELS_M0,Data channel map 0 (middle word)"
|
|
hexmask.long.word 0x14 0.--15. 1. "DATA_CHANNELS_M0,This register field indicates which of the data channels are in use. This stores the information for the middle 16 (32:16) data channel indices."
|
|
line.long 0x18 "DATA_CHANNELS_H0,Data channel map 0 (upper word)"
|
|
hexmask.long.byte 0x18 0.--4. 1. "DATA_CHANNELS_H0,This register field indicates which of the data channels are in use. This stores the information for the upper 5 (36:32) data channel indices."
|
|
group.long 0x98++0xB
|
|
line.long 0x0 "DATA_CHANNELS_L1,Data channel map 1 (lower word)"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA_CHANNELS_L1,This register field indicates which of the data channels are in use. This stores the information for the lower 16 (15:0) data channel indices."
|
|
line.long 0x4 "DATA_CHANNELS_M1,Data channel map 1 (middle word)"
|
|
hexmask.long.word 0x4 0.--15. 1. "DATA_CHANNELS_M1,This register field indicates which of the data channels are in use. This stores the information for the middle 16 (32:16) data channel indices."
|
|
line.long 0x8 "DATA_CHANNELS_H1,Data channel map 1 (upper word)"
|
|
hexmask.long.byte 0x8 0.--4. 1. "DATA_CHANNELS_H1,This register field indicates which of the data channels are in use. This stores the information for the upper 5 data channel indices."
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "CONN_INTR,Connection interrupt status and Clear register"
|
|
bitfld.long 0x0 15. "PING_NEARLY_EXPIRD_INTR,If this is set it indicates that ping timer has nearly expired." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PING_TIMER_EXPIRD_INTR,If this is set it indicates that ping timer has expired." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 11.--13. "RX_PDU_STATUS,Status of PDU received. This information is valid along with receive interrupt." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 8.--10. "DISCON_STATUS,Reason for disconnect - indicates the reason the link is disconnected by hardware." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 7. "CON_UPDT_DONE,This bit is set when the last connection event with previous connec-tion parameters is reached. The bit is set immediately after the re-ceive operation at the anchor point of the last connection event." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CE_RX,If this bit is set it indicates that a packet is received in the connection event." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CE_TX_ACK,If this bit is set it indicates that the connection event transmission acknowledgement is received for the previous non-empty packet transmitted." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CLOSE_CE,If this bit is set it indicates that the connection event closed interrupt has happened." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "START_CE,If this bit is set it indicates that the connection event started interrupt has happened." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MAP_UPDT_DONE,If this bit is set it indicates that the channel map update is completed at the instant specified by the firmware." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CONN_ESTB,If this bit is set it indicates that the connection has been established. The bit is also set when a connection update procedure is complet-ed at the start of the first anchor point with the updated parameters." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CONN_CLOSED,If this bit is set it indicates that the link is disconnected." "0,1"
|
|
rgroup.long 0xAC++0x3
|
|
line.long 0x0 "CONN_STATUS,Connection channel status"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RECEIVE_PACKET_COUNT,This field stores the count for the number of receive packets in the receive FIFO that are still not ready by firmware."
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "CONN_INDEX,Connection Index register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CONN_INDEX,This field is used to index the multiple connections existing. Range is 0 to maximum number of connections supported."
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "WAKEUP_CONFIG,Wakeup configuration"
|
|
hexmask.long.byte 0x0 10.--15. 1. "DSM_OFFSET_TO_WAKEUP_INSTANT,Number of 'slots' before the wake up instant before which the hardware needs to exit from deep sleep mode. The slot is of 0.625ms period. This is a onetime configuration field which is used every time hardware does an.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "OSC_STARTUP_DELAY,Oscillator stabilization/startup delay. This is in X.Y for-mat where X is in terms of number of BT slots (625 us) and Y is in terms of number of clock periods of 16KHz clock input required for RF oscillator to stabilize the clock.."
|
|
group.long 0xC0++0x7
|
|
line.long 0x0 "WAKEUP_CONTROL,Wakeup control"
|
|
hexmask.long.word 0x0 0.--15. 1. "WAKEUP_INSTANT,Instant with reference to the internal 16-bit clock reference at which the hardware must wakeup from deep sleep mode. This is calculated by firmware based on the next closest instant where a controller operation is required (like.."
|
|
line.long 0x4 "CLOCK_CONFIG,Clock control"
|
|
bitfld.long 0x4 15. "DEEP_SLEEP_MODE_EN,Enable deep sleep mode. 1 - enable 0 - disable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "SLEEP_MODE_EN,Enable sleep mode. 1 - enable 0 - disable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "DEEP_SLEEP_AUTO_WKUP_DISABLE,Disable Auto Wakeup in DEEP_SLEEP mode." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "SM_INTR_EN,Enable SM exit interrupt. 1 - enable 0 - disable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SM_AUTO_WKUP_EN,Enable sleep mode auto wakeup enable. 1- enable 0 - disable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "LPO_SEL_EXTERNAL,Select external sleep clock. 1 - External clock 0 - inter-nal generated clock." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "LPO_CLK_FREQ_SEL,Clock frequency select. 0 - 32KHz 1 - 32.768KHz." "0,1"
|
|
newline
|
|
rbitfld.long 0x4 7. "LLH_IDLE,Indicates if hardware is doing any transmit/receive operation. This information is used by firmware to decide to program the hardware into deep sleep mode." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "PHY_CLK_GATE_EN,Digital PHY clock enable. 1- enable 0-disable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "SYSCLK_GATE_EN,Sysclk gate enable. 1- enable 0 - disable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CORECLK_GATE_EN,Core clock gate enable. 1 - enable 0 - disable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CONN_CLK_GATE_EN,Connection block clock gate enable. 1 - enable 0 - disable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "INIT_CLK_GATE_EN,Initiator block clock gate enable. 1 - enable 0 - disable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "SCAN_CLK_GATE_EN,Scan block clock gate enable. 1 - enable 0 - disable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "ADV_CLK_GATE_EN,Advertiser block clock gate enable. 1 - enable 0 - disable." "0,1"
|
|
rgroup.long 0xC8++0x3
|
|
line.long 0x0 "TIM_COUNTER_L,Reference Clock"
|
|
hexmask.long.word 0x0 0.--15. 1. "TIM_REF_CLOCK,16-bit internal reference clock. The clock is a free run-ning clock incremented by a 0.625ms periodic pulse. It is used as a reference clock to derive all the timing required as per protocol."
|
|
group.long 0xCC++0x3
|
|
line.long 0x0 "WAKEUP_CONFIG_EXTD,Wakeup configuration extended"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DSM_LF_OFFSET,Number of 'LF slots' before the wake up instant before which the hardware needs to exit from deep sleep mode. The LF slot is of 62.5us period. This is a onetime configuration field which is used every time hardware does an auto-wakeup.."
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "POC_REG__TIM_CONTROL,BLE Time Control"
|
|
hexmask.long.byte 0x0 8.--11. 1. "START_SLOT_OFFSET,LLH clock configuration. The start of slot signal is offset by this value. If value is 0 the start of slot signal is generated at the 625us. The offset value is in terms of us."
|
|
newline
|
|
hexmask.long.byte 0x0 3.--7. 1. "BB_CLK_FREQ_MINUS_1,LLH clock configuration. The clock frequency of the clock input to this design is configured in this register. This is used to derive a 1MHz clock."
|
|
group.long 0xE0++0x3
|
|
line.long 0x0 "ADV_TX_DATA_FIFO,Advertising data transmit FIFO. Access ADVCH_TX_FIFO."
|
|
hexmask.long.word 0x0 0.--15. 1. "ADV_TX_DATA,IO mapped FIFO of depth 16 (2 byte wide) to store ADV data of maximum length 31 bytes for transmitting. Firmware writes consecutive words by writing to the same address location."
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "ADV_SCN_RSP_TX_FIFO,Advertising scan response data transmit FIFO. Access ADVCH_TX_FIFO."
|
|
hexmask.long.word 0x0 0.--15. 1. "SCAN_RSP_DATA,IO mapped FIFO of depth 16 (2 byte wide) to store scan response data of maximum length 31 bytes for transmitting. Firmware writes consecutive words by writing to the same location."
|
|
rgroup.long 0xF8++0x3
|
|
line.long 0x0 "INIT_SCN_ADV_RX_FIFO,advertising scan response data receive data FIFO. Access ADVRX_FIFO."
|
|
hexmask.long.word 0x0 0.--15. 1. "ADV_SCAN_RSP_RX_DATA,IO mapped FIFO of depth 64 to store ADV and SCAN_RSP header and payload received by the scanner. The RSSI value at the time of reception of this packet is also stored. Firmware reads from the same address to read out consecutive.."
|
|
group.long 0x100++0x1F
|
|
line.long 0x0 "CONN_INTERVAL,Connection Interval"
|
|
hexmask.long.word 0x0 0.--15. 1. "CONNECTION_INTERVAL,The value configured in this register determines the spacing be-tween the connection events."
|
|
line.long 0x4 "SUP_TIMEOUT,Supervision timeout"
|
|
hexmask.long.word 0x4 0.--15. 1. "SUPERVISION_TIMEOUT,This field defines the maximum time between two received Data packet PDUs before the connection is considered lost."
|
|
line.long 0x8 "SLAVE_LATENCY,Slave Latency"
|
|
hexmask.long.word 0x8 0.--15. 1. "SLAVE_LATENCY,The value configured in this field defines the number of consecutive connection events that the slave device is not required to listen for master."
|
|
line.long 0xC "CE_LENGTH,Connection event length"
|
|
hexmask.long.word 0xC 0.--15. 1. "CONNECTION_EVENT_LENGTH,This field defines the length of Connection event. This value is derived from the CE length HCI parameters received from the host. This determines the number of master transmit slots in a connection event subject to either of.."
|
|
line.long 0x10 "PDU_ACCESS_ADDR_L_REGISTER,Access address (lower)"
|
|
hexmask.long.word 0x10 0.--15. 1. "PDU_ACCESS_ADDRESS_LOWER_BITS,This field defines the lower 16 bits of the access address for each Link layer connection between any two devices."
|
|
line.long 0x14 "PDU_ACCESS_ADDR_H_REGISTER,Access address (upper)"
|
|
hexmask.long.word 0x14 0.--15. 1. "PDU_ACCESS_ADDRESS_HIGHER_BITS,This field defines the higher 16 bits of the access address for each Link layer connection between any two devices."
|
|
line.long 0x18 "CONN_CE_INSTANT,Connection event instant"
|
|
hexmask.long.word 0x18 0.--15. 1. "CE_INSTANT,This is the value of the free running Connection Event counter when the new parameters of 'connection update' and/or 'Channel map update' will be effective."
|
|
line.long 0x1C "CE_CNFG_STS_REGISTER,connection configuration & status register"
|
|
hexmask.long.byte 0x1C 12.--15. 1. "CURRENT_PDU_INDEX,The index of the transmit packet buffer that is currently in transmission/waiting for transmission."
|
|
newline
|
|
rbitfld.long 0x1C 10. "CONN_ACTIVE,This bit is '1' whenever the connection is active." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 8. "PAUSE_DATA,Pause data." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 7. "MAP_INDEX__CURR_INDEX,Written by firmware to select the map index to be used by hardware for this connection." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 6. "MD,MD bit set to '1' indicates device has more data to be sent." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 5. "SPARE,This bit is unused" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "DATA_LIST_HEAD_UP,Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--3. 1. "DATA_LIST_INDEX_LAST_ACK_INDEX,Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded."
|
|
rgroup.long 0x120++0x7
|
|
line.long 0x0 "NEXT_CE_INSTANT,Next connection event instant"
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT_CE_INSTANT,16-bit internal reference clock value at which the next connection event will occur on a connection. The connection index register must be programmed with index of the connection before reading the register."
|
|
line.long 0x4 "CONN_CE_COUNTER,connection event counter"
|
|
hexmask.long.word 0x4 0.--15. 1. "CONNECTION_EVENT_COUNTER,This is the free running counter connEventCounter as defined by Bluetooth spec."
|
|
group.long 0x128++0x13
|
|
line.long 0x0 "DATA_LIST_SENT_UPDATE__STATUS,data list sent update and status"
|
|
bitfld.long 0x0 7. "SET_CLEAR,Write: Used to set the SENT bit in hardware for the selected packet buffer." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "LIST_INDEX__TX_SENT_3_0,Write:Indicates the buffer index for which the SENT bit is being updated by firmware."
|
|
line.long 0x4 "DATA_LIST_ACK_UPDATE__STATUS,data list ack update and status"
|
|
bitfld.long 0x4 7. "SET_CLEAR,Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "LIST_INDEX__TX_ACK_3_0,Write: Indicates the buffer index for which the ACK bit is being updated by firmware."
|
|
line.long 0x8 "CE_CNFG_STS_REGISTER_EXT,connection configuration & status register"
|
|
hexmask.long.byte 0x8 8.--13. 1. "LAST_UNMAPPED_CHANNEL,Last unmapped channel for next scheduled connection index"
|
|
newline
|
|
bitfld.long 0x8 3. "NESN,Next Sequence number for next scheduled connection index" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SN,Sequence number for next scheduled connection index" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "RX_2M,receiving on 2M" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TX_2M,transmittion on 2M" "0,1"
|
|
line.long 0xC "CONN_EXT_INTR,Connection extended interrupt status and Clear register"
|
|
bitfld.long 0xC 2. "GEN_TIMER_INTR,If this bit is set it indicates that the generic timer (PDU response timer reconfigured in MMMS mode) has expired" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "EARLY_INTR,For master this bit is set on start_ce" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "DATARATE_UPDATE,If this bit is set it indicates that the data rate is updated" "0,1"
|
|
line.long 0x10 "CONN_EXT_INTR_MASK,Connection Extended Interrupt mask"
|
|
bitfld.long 0x10 2. "GEN_TIMER_INTR,Generic timer (PDU response timer reconfigured in MMMS mode) expiry interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "EARLY_INTR,If this bit is set connection early interrupt is enabled." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "DATARATE_UPDATE,If this bit is set connection data rate update interrupt is enabled." "0,1"
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x140)++0x3
|
|
line.long 0x0 "DATA_MEM_DESCRIPTOR[$1],Data buffer descriptor 0 to 4"
|
|
hexmask.long.byte 0x0 2.--9. 1. "DATA_LENGTH,This field indicates the length of the data packet. Bits [9:7] are valid only if DLE is set."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "LLID,N/A" "0,1,2,3"
|
|
repeat.end
|
|
group.long 0x160++0x7
|
|
line.long 0x0 "WINDOW_WIDEN_INTVL,Window widen for interval"
|
|
hexmask.long.word 0x0 0.--11. 1. "WINDOW_WIDEN_INTVL,This value defines the increased listening time for the slave."
|
|
line.long 0x4 "WINDOW_WIDEN_WINOFF,Window widen for offset"
|
|
hexmask.long.word 0x4 0.--11. 1. "WINDOW_WIDEN_WINOFF,This field stores the additional number of microseconds the slave must extend its listening window to listen for a master packet. This value is calculated based on the window offset value. This is used at connection setup directly."
|
|
group.long 0x170++0x3
|
|
line.long 0x0 "LE_RF_TEST_MODE,Direct Test Mode control"
|
|
bitfld.long 0x0 15. "DTM_DATA_2MBPS,0: DTM run at 1M bps data rate" "0: DTM run at 1M bps data rate,1: DTM run at 2M bps data rate"
|
|
newline
|
|
bitfld.long 0x0 13. "DTM_CONT_TXEN,0: DTM run at normal DTMTX burst mode" "0: DTM run at normal DTMTX burst mode,1: DTM run at continuous TX DTM mode"
|
|
newline
|
|
bitfld.long 0x0 7.--9. "PKT_PAYLOAD,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6. "DTM_STATUS__DTM_CONT_RXEN,This bit is overloaded." "0: DTM run at normal DTMRX burst mode,1: DTM run at continuous RX DTM mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TEST_FREQUENCY,N = (F - 2402) / 2"
|
|
rgroup.long 0x174++0x3
|
|
line.long 0x0 "DTM_RX_PKT_COUNT,Direct Test Mode receive packet count"
|
|
hexmask.long.word 0x0 0.--15. 1. "RX_PACKET_COUNT,Number of packets received in receive test mode."
|
|
group.long 0x178++0x3
|
|
line.long 0x0 "LE_RF_TEST_MODE_EXT,Direct Test Mode control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTM_PACKET_LENGTH,DTM TX packet length."
|
|
rgroup.long 0x188++0x3
|
|
line.long 0x0 "TXRX_HOP,Channel Address register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "HOP_CH_RX,Receive channel index. Channel index on which previous packet is received."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "HOP_CH_TX,Transmit channel index. Channel index on which previous packet is transmitted."
|
|
group.long 0x190++0x3
|
|
line.long 0x0 "TX_RX_ON_DELAY,Transmit/Receive data delay"
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXON_DELAY,Transmit delay - Delay from start of transmit to transmission of first bit on air. It is used to control the T_IFS. The delay is in resolution of 1 microsecond."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXON_DELAY,Receive delay - Delay from start of receive to expected first bit of receive packet at the controller. Used to control the turn on time of radio to optimize on power. The delay is in resolution of 1 microsecond."
|
|
group.long 0x1A8++0x23
|
|
line.long 0x0 "ADV_ACCADDR_L,ADV packet access code low word"
|
|
hexmask.long.word 0x0 0.--15. 1. "ADV_ACCADDR_L,Lower 16 bit of ADV packet access code"
|
|
line.long 0x4 "ADV_ACCADDR_H,ADV packet access code high word"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADV_ACCADDR_H,higher 16 bit of ADV packet access code"
|
|
line.long 0x8 "ADV_CH_TX_POWER_LVL_LS,Advertising channel transmit power setting"
|
|
hexmask.long.word 0x8 0.--15. 1. "ADV_TRANSMIT_POWER_LVL_LS,When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 1 this field represents the Advertising channel transmit power setting Least Significant 16 bits."
|
|
line.long 0xC "ADV_CH_TX_POWER_LVL_MS,Advertising channel transmit power setting extension"
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bitfld.long 0xC 0.--1. "ADV_TRANSMIT_POWER_LVL_MS,Advertising channel transmit power setting Most Significant 2 bits." "0,1,2,3"
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line.long 0x10 "CONN_CH_TX_POWER_LVL_LS,Connection channel transmit power setting"
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hexmask.long.word 0x10 0.--15. 1. "CONNCH_TRANSMIT_POWER_LVL_LS,When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 1 this field represents the Connection channel transmit power setting Least Significant 16 bits."
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line.long 0x14 "CONN_CH_TX_POWER_LVL_MS,Connection channel transmit power setting extension"
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bitfld.long 0x14 0.--1. "CONNCH_TRANSMIT_POWER_LVL_MS,Connection channel transmit power setting Most Significant 2 bits." "0,1,2,3"
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|
line.long 0x18 "DEV_PUB_ADDR_L,Device public address lower register"
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|
hexmask.long.word 0x18 0.--15. 1. "DEV_PUB_ADDR_L,Lower 16 bit of 48-bit public address of the device."
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|
line.long 0x1C "DEV_PUB_ADDR_M,Device public address middle register"
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hexmask.long.word 0x1C 0.--15. 1. "DEV_PUB_ADDR_M,Middle 16 bit of 48-bit public address of the device."
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|
line.long 0x20 "DEV_PUB_ADDR_H,Device public address higher register"
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hexmask.long.word 0x20 0.--15. 1. "DEV_PUB_ADDR_H,Higher 16 bit of 48-bit public address of the device."
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|
group.long 0x1D0++0x13
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line.long 0x0 "OFFSET_TO_FIRST_INSTANT,Offset to first instant"
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|
hexmask.long.word 0x0 0.--15. 1. "OFFSET_TO_FIRST_EVENT,The offset w.r.t the internal reference clock at which instant the first event occurs."
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|
line.long 0x4 "ADV_CONFIG,Advertiser configuration register"
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hexmask.long.byte 0x4 11.--15. 1. "ADV_PKT_INTERVAL,Time between the beginning of two consecutive advertising PDU's."
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bitfld.long 0x4 10. "ADV_CONN_PEER_RPA_UNMCH_EN,Enable connect request packet received with peer device address unmatched interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set." "0,1"
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bitfld.long 0x4 9. "ADV_SCN_PEER_RPA_UNMCH_EN,Enable scan request packet received with peer device address unmatched interrupt. This bit is valid only if PRIV_1_2 PRIV_1_2 and PRIV_1_2_ADV are set." "0,1"
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bitfld.long 0x4 8. "ADV_RAND_DISABLE,Disable randomization of adv interval. When disabled interval is same as programmed in adv_interval register." "0,1"
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bitfld.long 0x4 7. "ADV_TIMEOUT_EN,Enable adv_timeout interrupt. Applicable in adv_direct_ind advertising." "0,1"
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bitfld.long 0x4 6. "SLV_CONNECTED_EN,Enable slave connected interrupt." "0,1"
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bitfld.long 0x4 5. "ADV_CONN_REQ_RX_EN,Enable connect request packet received interrupt." "0,1"
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bitfld.long 0x4 4. "ADV_SCN_REQ_RX_EN,Enable scan request packet received interrupt." "0,1"
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bitfld.long 0x4 3. "SCN_RSP_TX_EN,Enable scan response packet transmitted interrupt." "0,1"
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bitfld.long 0x4 2. "ADV_TX_EN,Enable adv packet transmitted interrupt." "0,1"
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bitfld.long 0x4 1. "ADV_CLS_EN,Enable advertising event stop interrupt." "0,1"
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bitfld.long 0x4 0. "ADV_STRT_EN,Enable advertising event start interrupt." "0,1"
|
|
line.long 0x8 "SCAN_CONFIG,Scan configuration register"
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bitfld.long 0x8 13.--15. "SCAN_CHANNEL_MAP,Advertising channels that are enabled for scanning operation." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 11. "BACKOFF_ENABLE,Enable random backoff feature in scanner." "0,1"
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bitfld.long 0x8 8. "RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN,This bit controls the SCAN engine behavior when an self address match occurs but a privacy mismatch occurs" "0,1"
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bitfld.long 0x8 7. "SCANA_TX_ADDR_NOT_SET_INTR_EN,Enable SCANA RPA TX not set interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set." "0,1"
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bitfld.long 0x8 6. "SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN,Enable ADV self address unmatched interrupt. This bit is valid only if PRIV_1_2 PRIV_1_2 and PRIV_1_2_SCAN are set." "0,1"
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bitfld.long 0x8 5. "SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN,Enable ADV peer address unmatched interrupt. This bit is valid only if PRIV_1_2 PRIV_1_2 and PRIV_1_2_SCAN are set." "0,1"
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bitfld.long 0x8 4. "SCN_RSP_RX_EN,Enable scan_rsp packet received interrupt ." "0,1"
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bitfld.long 0x8 3. "ADV_RX_EN,Enable adv packet received interrupt ." "0,1"
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bitfld.long 0x8 2. "SCN_TX_EN,Enable scan request packet transmitted interrupt." "0,1"
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bitfld.long 0x8 1. "SCN_CLOSE_EN,Enable scan event close interrupt." "0,1"
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bitfld.long 0x8 0. "SCN_STRT_EN,Enable scan event start interrupt." "0,1"
|
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line.long 0xC "INIT_CONFIG,Initiator configuration register"
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bitfld.long 0xC 13.--15. "INIT_CHANNEL_MAP,Advertising channels that are enabled for initiator scanning operation." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 7. "INITA_TX_ADDR_NOT_SET_INTR_EN,Enable INITA RPA TX not set interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set." "0,1"
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bitfld.long 0xC 6. "INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN,Enable ADV peer address RPA unresolved interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set." "0,1"
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bitfld.long 0xC 5. "INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN,Enable ADV self address RPA unresolved interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set." "0,1"
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bitfld.long 0xC 4. "CONN_CREATED,Enable master connection created interrupt" "0,1"
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bitfld.long 0xC 2. "CONN_REQ_TX_EN,Enables connection request packet transmission start interrupt." "0,1"
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|
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|
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bitfld.long 0xC 1. "INIT_CLOSE_EN,Enable Initiator event close interrupt." "0,1"
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bitfld.long 0xC 0. "INIT_STRT_EN,Enable Initiator event start interrupt." "0,1"
|
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line.long 0x10 "CONN_CONFIG,Connection configuration register"
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bitfld.long 0x10 15. "CONN_REQ_1SLOT_EARLY,This bit is used to enable extension of the Conn Request to arbiter to 1 slot early. When enabled the request length is 2 slots." "0,1"
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bitfld.long 0x10 14. "MASK_SUTO_AT_UPDT,This bit is used to enable/disable masking of internal hardware supervision timeout trigger when switching from old connection parameters to new parameters." "0,1"
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bitfld.long 0x10 13. "EXTEND_CU_TX_WIN,This bit is used to enable/disable extending the additional rx window on slave side during connection update in event of packet miss at the update instant." "0,1"
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bitfld.long 0x10 12. "SLV_MD_CONFIG,This bit is set to configure the MD bit control when IUT is in slave role." "0,1"
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bitfld.long 0x10 11. "DSM_SLOT_VARIANCE,This bit configures the DSM slot counting mode." "0,1"
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bitfld.long 0x10 8. "MD_BIT_CLEAR,This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or 'hardware and soft-ware logic combined'." "0,1"
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hexmask.long.byte 0x10 4.--7. 1. "RX_INTR_THRESHOLD,This register field allows setting a threshold for the packet received interrupt to the firmware."
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hexmask.long.byte 0x10 0.--3. 1. "RX_PKT_LIMIT,Defines a limit for the number of Rx packets that can be re-ceived by the LLH. Default maximum value is 0xF.Minimum value shall be '1' or no packet will be stored in the Rx FIFO."
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group.long 0x1E8++0x13
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line.long 0x0 "CONN_PARAM1,Connection parameter 1"
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|
hexmask.long.byte 0x0 8.--15. 1. "CRC_INIT_L,This field defines the lower byte (7:0) of the CRC initialization vector."
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hexmask.long.byte 0x0 3.--7. 1. "HOP_INCREMENT_PARAM,Hop increment for connection channel."
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bitfld.long 0x0 0.--2. "SCA_PARAM,Sleep Clock Accuracy" "0,1,2,3,4,5,6,7"
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|
line.long 0x4 "CONN_PARAM2,Connection parameter 2"
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hexmask.long.word 0x4 0.--15. 1. "CRC_INIT_H,This field defines the upper two bytes (23:8) of the CRC initialization vector."
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line.long 0x8 "CONN_INTR_MASK,Connection Interrupt mask"
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bitfld.long 0x8 15. "PING_NEARLY_EXPIRD_INTR,If this bit is set ping timer nearly expired interrupt is enabled" "0,1"
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bitfld.long 0x8 14. "PING_TIMER_EXPIRD_INTR,If this bit is set ping timer expired interrupt is enabled." "0,1"
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bitfld.long 0x8 13. "CE_CLOSE_NULL_RX_INT_EN,If this but us set the RX interrupt is triggerred for an end of connection event with a null packet" "0,1"
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bitfld.long 0x8 9. "RX_BAD_PDU_INT_EN,If this bit is set packet receive bad pdu interrupt is enabled. Effective only when bit 6 is set." "0,1"
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bitfld.long 0x8 8. "RX_GOOD_PDU_INT_EN,If this bit is set packet receive good pdu interrupt is enabled. Effective only when bit 6 is set." "0,1"
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bitfld.long 0x8 7. "CONN_UPDATE_INTR_EN,If this bit is set connection update interrupt is enabled." "0,1"
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bitfld.long 0x8 6. "CE_RX_INT_EN,If this bit is set interrupt is enabled for reception of packet in a connection event." "0,1"
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bitfld.long 0x8 5. "CE_TX_ACK_INT_EN,If this bit is set transmission acknowledgement interrupt is enabled:" "0,1"
|
|
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|
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bitfld.long 0x8 4. "CLOSE_CE_INT_EN,If this bit is set connection event closed interrupt is enabled." "0,1"
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bitfld.long 0x8 3. "START_CE_INT_EN,If this bit is set connection event start interrupt is enabled" "0,1"
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bitfld.long 0x8 2. "MAP_UPDT_INT_EN,If this bit is set channel map update interrupt is enabled." "0,1"
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newline
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bitfld.long 0x8 1. "CONN_ESTB_INT_EN,If this bit is set connection establishment interrupt is enabled." "0,1"
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bitfld.long 0x8 0. "CONN_CL_INT_EN,If this bit is set connection closed interrupt is enabled." "0,1"
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line.long 0xC "SLAVE_TIMING_CONTROL,slave timing control"
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hexmask.long.byte 0xC 8.--15. 1. "SLAVE_TIME_ADJ_VAL,Timing adjust value. The internal micro second counter is adjusted to this value whenever slave receives a good access address match at connection anchor point. This will ensure the slave gets synchronized to master timing."
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hexmask.long.byte 0xC 0.--7. 1. "SLAVE_TIME_SET_VAL,Programmable adjust value to the clock counter when slave is connected"
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line.long 0x10 "RECEIVE_TRIG_CTRL,Receive trigger control"
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hexmask.long.byte 0x10 8.--15. 1. "ACC_TRIGGER_TIMEOUT,If access address match does not occur then within this time from the start of receive operation the receive operation times out and stops. An internal counter value of 1usec resolution is continuously compared with the value.."
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hexmask.long.byte 0x10 0.--5. 1. "ACC_TRIGGER_THRESHOLD,Access address match threshold value. Number of bits of ac-cess address that should match with the expected access ad-dress to trigger an access code match."
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rgroup.long 0x200++0x27
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line.long 0x0 "LL_DBG_1,LL debug register 1"
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hexmask.long.word 0x0 0.--9. 1. "CONN_RX_WR_PTR,Connection receive FIFO write pointer"
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line.long 0x4 "LL_DBG_2,LL debug register 2"
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hexmask.long.word 0x4 0.--9. 1. "CONN_RX_RD_PTR,Connection receive FIFO read pointer"
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line.long 0x8 "LL_DBG_3,LL debug register 3"
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hexmask.long.word 0x8 0.--9. 1. "CONN_RX_WR_PTR_STORE,Connection receive FIFO stored write pointer for pointer restore"
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line.long 0xC "LL_DBG_4,LL debug register 4"
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hexmask.long.byte 0xC 6.--10. 1. "ADVERTISER_FSM_STATE,Advertiser FSM state"
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|
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bitfld.long 0xC 4.--5. "SLAVE_LATENCY_FSM_STATE,Slave Latency FSM state" "0,1,2,3"
|
|
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|
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hexmask.long.byte 0xC 0.--3. 1. "CONNECTION_FSM_STATE,Connection FSM state"
|
|
line.long 0x10 "LL_DBG_5,LL debug register 5"
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hexmask.long.byte 0x10 5.--9. 1. "SCAN_FSM_STATE,Scanner FSM state"
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|
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hexmask.long.byte 0x10 0.--4. 1. "INIT_FSM_STATE,Initiator FSM state"
|
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line.long 0x14 "LL_DBG_6,LL debug register 6"
|
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hexmask.long.byte 0x14 8.--13. 1. "ADV_TX_RD_PTR,Advertiser/ Scan Response FIFO read pointer"
|
|
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|
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hexmask.long.byte 0x14 4.--7. 1. "SCAN_RSP_TX_WR_PTR,Scan Response Transmit FIFO write pointer"
|
|
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|
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hexmask.long.byte 0x14 0.--3. 1. "ADV_TX_WR_PTR,Advertiser Transmit FIFO write pointer"
|
|
line.long 0x18 "LL_DBG_7,LL debug register 7"
|
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hexmask.long.byte 0x18 7.--13. 1. "ADV_RX_RD_PTR,Advertiser Receive FIFO read pointer"
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|
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hexmask.long.byte 0x18 0.--6. 1. "ADV_RX_WR_PTR,Advertiser Receive FIFO write pointer"
|
|
line.long 0x1C "LL_DBG_8,LL debug register 8"
|
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hexmask.long.byte 0x1C 7.--13. 1. "WLF_PTR,Whitelist FIFO pointer"
|
|
newline
|
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hexmask.long.byte 0x1C 0.--6. 1. "ADV_RX_WR_PTR_STORE,Advertiser Receive FIFO stored write pointer for pointer restore"
|
|
line.long 0x20 "LL_DBG_9,LL debug register 9"
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hexmask.long.word 0x20 0.--15. 1. "WINDOW_WIDEN,Window Widening value in us. The reset value of this register is 0x0000. After reset de-assertion at the first clock cycle the value 0x0010 is assigned to the register."
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line.long 0x24 "LL_DBG_10,LL debug register 10"
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hexmask.long.byte 0x24 0.--5. 1. "RF_CHANNEL_NUM,Active channel number"
|
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group.long 0x230++0x1F
|
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line.long 0x0 "PEER_ADDR_INIT_L,Lower 16 bit address of the peer device for INIT."
|
|
hexmask.long.word 0x0 0.--15. 1. "PEER_ADDR_L,Lower 16 bit of 48-bit address of the peer device. This is used only in MMMS mode"
|
|
line.long 0x4 "PEER_ADDR_INIT_M,Middle 16 bit address of the peer device for INIT."
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hexmask.long.word 0x4 0.--15. 1. "PEER_ADDR_M,Middle 16 bit of 48-bit address of the peer device. This is used only in MMMS mode"
|
|
line.long 0x8 "PEER_ADDR_INIT_H,Higher 16 bit address of the peer device for INIT."
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hexmask.long.word 0x8 0.--15. 1. "PEER_ADDR_H,Higher 16 bit of 48-bit address of the peer device. This is used only in MMMS mode"
|
|
line.long 0xC "PEER_SEC_ADDR_ADV_L,Lower 16 bits of the secondary address of the peer device for ADV_DIR."
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hexmask.long.word 0xC 0.--15. 1. "PEER_SEC_ADDR_L,Lower 16 bit of 48-bit secondary address of the peer device for ADV_DIR."
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line.long 0x10 "PEER_SEC_ADDR_ADV_M,Middle 16 bits of the secondary address of the peer device for ADV_DIR."
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hexmask.long.word 0x10 0.--15. 1. "PEER_SEC_ADDR_M,Middle 16 bit of 48-bit secondary address of the peer device for ADV_DIR."
|
|
line.long 0x14 "PEER_SEC_ADDR_ADV_H,Higher 16 bits of the secondary address of the peer device for ADV_DIR."
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hexmask.long.word 0x14 0.--15. 1. "PEER_SEC_ADDR_H,Higher 16 bit of 48-bit secondary address of the peer device for ADV_DIR."
|
|
line.long 0x18 "INIT_WINDOW_TIMER_CTRL,Initiator Window NI timer control"
|
|
bitfld.long 0x18 0. "INIT_WINDOW_OFFSET_SEL,Controls the INIT Window offset source" "0,1"
|
|
line.long 0x1C "CONN_CONFIG_EXT,Connection extended configuration register"
|
|
bitfld.long 0x1C 15. "MT_PDU_CE_EXPIRE,MMMS empty PDU CE expire handling control bit" "0,1"
|
|
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|
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bitfld.long 0x1C 14. "DEBUG_CE_EXPIRE,MMMS CE expire control bit" "0,1"
|
|
newline
|
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hexmask.long.byte 0x1C 8.--13. 1. "MMMS_RX_PKT_LIMIT,Receive Packet Limit for MMMS mode. This is the RX_FIFO Limit and applies to all connections together"
|
|
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hexmask.long.byte 0x1C 2.--6. 1. "FW_PKT_RCV_CONN_INDEX,Connection Index for which the FW generates Packet Received Command. In MMMS mode FW should write this field before giving PKT_RECEIVE_COMMAND to HW."
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bitfld.long 0x1C 1. "CONN_REQ_3SLOT_EARLY,This bit is used to enable extension of the Conn Request to arbiter to 3 slot early. When enabled the request length is 4 slots irrespective of the status of CONN_REQ_1SLOT_EARLY & CONN_REQ_2SLOT_EARLY bits." "0,1"
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|
newline
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bitfld.long 0x1C 0. "CONN_REQ_2SLOT_EARLY,This bit is used to enable extension of the Conn Request to arbiter to 2 slot early. When enabled the request length is 3 slots irrespective of the status of CONN_REQ_1SLOT_EARLY bit." "0,1"
|
|
group.long 0x258++0x3
|
|
line.long 0x0 "DPLL_CONFIG,DPLL & CY Correlator configuration register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DPLL_CORREL_CONFIG,If MXD_IF_OPTION is 0:"
|
|
group.long 0x260++0x3
|
|
line.long 0x0 "INIT_NI_VAL,Initiator Window NI instant"
|
|
hexmask.long.word 0x0 0.--15. 1. "INIT_NI_VAL,Initiator window Next Instant value used for spacing Master connections in time to minimize connection contention. This value is in 625us slots."
|
|
rgroup.long 0x264++0x7
|
|
line.long 0x0 "INIT_WINDOW_OFFSET,Initiator Window offset captured at conn request"
|
|
hexmask.long.word 0x0 0.--15. 1. "INIT_WINDOW_NI,Initiator Window offset captured at conn request. This value is in 1.25ms slots"
|
|
line.long 0x4 "INIT_WINDOW_NI_ANCHOR_PT,Initiator Window NI anchor point captured at conn request"
|
|
hexmask.long.word 0x4 0.--15. 1. "INIT_INT_OFF_CAPT,Initiator interval offset captured at conn request. The value indicates the master connection anchor point. This value is in 625us slots"
|
|
group.long 0x3A4++0xF
|
|
line.long 0x0 "CONN_UPDATE_NEW_INTERVAL,Connection update new interval"
|
|
hexmask.long.word 0x0 0.--15. 1. "CONN_UPDT_INTERVAL,This register will have the new connection interval that the hardware will use after the connection update instant. Before the instant the connection interval in the register CONN_INTERVAL will be used by hardware."
|
|
line.long 0x4 "CONN_UPDATE_NEW_LATENCY,Connection update new latency"
|
|
hexmask.long.word 0x4 0.--15. 1. "CONN_UPDT_SLV_LATENCY,This register will have the new slave latency parameter that the hardware will use after the connection update instant. Before the instant the connection interval in the register SLAVE_LATENCY will be used by hardware."
|
|
line.long 0x8 "CONN_UPDATE_NEW_SUP_TO,Connection update new supervision timeout"
|
|
hexmask.long.word 0x8 0.--15. 1. "CONN_UPDT_SUP_TO,This register will have the new supervision timeout that the hardware will use after the connection update instant. Before the instant the connection interval in the register SUP_TIMEOUT will be used by hardware."
|
|
line.long 0xC "CONN_UPDATE_NEW_SL_INTERVAL,Connection update new Slave Latency X Conn interval Value"
|
|
hexmask.long.word 0xC 0.--15. 1. "SL_CONN_INTERVAL_VAL,This register will have the new Slave Latency * Conn Interval value that the hardware will use after the connection update instant. Before the instant the connection interval in the register SL_CONN_INTERVAL will be used by hardware."
|
|
group.long 0x3C0++0x2F
|
|
line.long 0x0 "CONN_REQ_WORD0,Connection request address word 0"
|
|
hexmask.long.word 0x0 0.--15. 1. "ACCESS_ADDR_LOWER,This field defines the lower 16 bits of the access address that is to be sent in the connect request packet of the initiator."
|
|
line.long 0x4 "CONN_REQ_WORD1,Connection request address word 1"
|
|
hexmask.long.word 0x4 0.--15. 1. "ACCESS_ADDR_UPPER,This field defines the upper16 bits of the access address that is to be sent in the connect request packet of the initiator."
|
|
line.long 0x8 "CONN_REQ_WORD2,Connection request address word 2"
|
|
hexmask.long.byte 0x8 8.--15. 1. "CRC_INIT_LOWER,This field defines the lower byte [7:0] of the CRC initialization value."
|
|
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|
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hexmask.long.byte 0x8 0.--7. 1. "TX_WINDOW_SIZE_VAL,window_size along with the window_offset is used to calculate the first connection point anchor point for the master."
|
|
line.long 0xC "CONN_REQ_WORD3,Connection request address word 3"
|
|
hexmask.long.word 0xC 0.--15. 1. "CRC_INIT_UPPER,This field defines the upper byte [23:8] of the CRC initialization value that is to be sent in the connect request packet of the initiator."
|
|
line.long 0x10 "CONN_REQ_WORD4,Connection request address word 4"
|
|
hexmask.long.word 0x10 0.--15. 1. "TX_WINDOW_OFFSET,This is used to determine the anchor point for the master transmission."
|
|
line.long 0x14 "CONN_REQ_WORD5,Connection request address word 5"
|
|
hexmask.long.word 0x14 0.--15. 1. "CONNECTION_INTERVAL_VAL,The value configured in this register determines the spacing between the connection events."
|
|
line.long 0x18 "CONN_REQ_WORD6,Connection request address word 6"
|
|
hexmask.long.word 0x18 0.--15. 1. "SLAVE_LATENCY_VAL,The value configured in this field defines the number of consecutive connection events that the slave device is not required to listen for master. The value of connSlaveLatency should not cause a Supervision Timeout. This shall be an.."
|
|
line.long 0x1C "CONN_REQ_WORD7,Connection request address word 7"
|
|
hexmask.long.word 0x1C 0.--15. 1. "SUPERVISION_TIMEOUT_VAL,This field defines the maximum time between two received Data packet PDUs before the connection is considered lost."
|
|
line.long 0x20 "CONN_REQ_WORD8,Connection request address word 8"
|
|
hexmask.long.word 0x20 0.--15. 1. "DATA_CHANNELS_LOWER,This register field indicates which of the data channels are in use. This stores the information for the lower 16 (15:0) data channel indices."
|
|
line.long 0x24 "CONN_REQ_WORD9,Connection request address word 9"
|
|
hexmask.long.word 0x24 0.--15. 1. "DATA_CHANNELS_MID,This register field indicates which of the data channels are in use. This stores the information for the middle 16 (31:16) data channel indices."
|
|
line.long 0x28 "CONN_REQ_WORD10,Connection request address word 10"
|
|
hexmask.long.byte 0x28 0.--4. 1. "DATA_CHANNELS_UPPER,This register field indicates which of the data channels are in use. This stores the information for the upper 5 (36:32) data channel indices."
|
|
line.long 0x2C "CONN_REQ_WORD11,Connection request address word 11"
|
|
bitfld.long 0x2C 5.--7. "SCA_2,This field defines the sleep clock accuracies given in ppm." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--4. 1. "HOP_INCREMENT_2,This field is used for the data channel selection process."
|
|
group.long 0xA04++0x3
|
|
line.long 0x0 "PDU_RESP_TIMER,PDU response timer/Generic Timer (MMMS mode)"
|
|
hexmask.long.word 0x0 0.--15. 1. "PDU_RESP_TIME_VAL,Non MMMS mode: This register is loaded with the count value to monitor the time to get a response for a PDU from peer device."
|
|
rgroup.long 0xA08++0x7
|
|
line.long 0x0 "NEXT_RESP_TIMER_EXP,Next response timeout instant"
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT_RESPONSE_INSTANT,This field defines the clock instant at which the next PDU response timeout event will occur on a connection."
|
|
line.long 0x4 "NEXT_SUP_TO,Next supervision timeout instant"
|
|
hexmask.long.word 0x4 0.--15. 1. "NEXT_TIMEOUT_INSTANT,This field defines the clock instant at which the next connection supervision timeout event will occur on a connection"
|
|
group.long 0xA10++0x17
|
|
line.long 0x0 "LLH_FEATURE_CONFIG,Feature enable"
|
|
bitfld.long 0x0 2. "US_COUNTER_OFFSET_ADJ,Enable/Disable the connection US counter offset adjust. For non-MMMS mode this bit must be tied to 1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SL_DSM_EN,Enable/Disable Slave Latency Period DSM." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "QUICK_TRANSMIT,Quick transmit feature in slave latency is enabled by setting this bit." "0,1"
|
|
line.long 0x4 "WIN_MIN_STEP_SIZE,Window minimum step size"
|
|
hexmask.long.byte 0x4 8.--15. 1. "WINDOW_MIN_FW,Minimum window interval value programmed by firmware. While the slave receive window is decremented the windows_min_fw sets the lowest value of the window widen value to ensure packets are not missed. The unit is in microseconds."
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "STEPUP,If packets are missed the reference window is gradually increased by step up size until it receives 2 consecutive good packets. The unit is in microseconds"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "STEPDN,After receiving 2 consecutive good packets the reference window is gradually decremented by step down size until it reaches window minimum. The unit is in microseconds"
|
|
line.long 0x8 "SLV_WIN_ADJ,Slave window adjustment"
|
|
hexmask.long.word 0x8 0.--10. 1. "SLV_WIN_ADJ,Window Adjust value. This value is added to the calculated slave window widening value to be used as final window widen value."
|
|
line.long 0xC "SL_CONN_INTERVAL,Slave Latency X Conn Interval Value"
|
|
hexmask.long.word 0xC 0.--15. 1. "SL_CONN_INTERVAL_VAL,This field defines the (SL*CI) product for the ongoing connection. This value is used in calculation of next connection instant during slave latency."
|
|
line.long 0x10 "LE_PING_TIMER_ADDR,LE Ping connection timer address"
|
|
hexmask.long.word 0x10 0.--15. 1. "CONN_PING_TIMER_ADDR,The register used to configure the LE Au-thenticated payload Timeout (LE APTO) which is the Maximum amount of time specified between packets authenticated by a MIC."
|
|
line.long 0x14 "LE_PING_TIMER_OFFSET,LE Ping connection timer offset"
|
|
hexmask.long.word 0x14 0.--15. 1. "CONN_PING_TIMER_OFFSET,The value of ping timer nearly expired offset in the order of 10ms valid range 0x0 ~ 0xFFFF. This is the time period after which the ping timer nearly expired interrupt is generated."
|
|
rgroup.long 0xA28++0x7
|
|
line.long 0x0 "LE_PING_TIMER_NEXT_EXP,LE Ping timer next expiry instant"
|
|
hexmask.long.word 0x0 0.--15. 1. "CONN_PING_TIMER_NEXT_EXP,The value of ping timer next expiry instant in the terms of native clock value (least 16 bit value of the 17 bit ping counter)."
|
|
line.long 0x4 "LE_PING_TIMER_WRAP_COUNT,LE Ping Timer wrap count"
|
|
hexmask.long.word 0x4 0.--15. 1. "CONN_SEC_CURRENT_WRAP,This register holds the current position of the Ping timer."
|
|
group.long 0xE00++0xB
|
|
line.long 0x0 "TX_EN_EXT_DELAY,Transmit enable extension delay"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MOD_2M_COMP_DLY,2Mbps modulation delay delta compare to 1Mbps demod delay. This data is 2's comp data."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DEMOD_2M_COMP_DLY,2Mbps demod delay delta compare to 1Mbps demod delay. This data is 2's comp data."
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "RXEN_EXT_DELAY,receiver enable extension delay. This is to extend the active state (high) of dbus_rx_en signal after the last bit is received from demod. The unit is in microsecond and the supported range is 00 - 31 us."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "TXEN_EXT_DELAY,Transmit enable extension delay. This is to extend the active state (high) of rif_tx_en signal after the last bit is sent out from LLH. The unit is in microsecond and the supported range is 00 - 31 us."
|
|
line.long 0x4 "TX_RX_SYNTH_DELAY,Transmit/Receive enable delay"
|
|
hexmask.long.byte 0x4 8.--15. 1. "TX_EN_DELAY,The delay used to assert rif_tx_en exactly Tx_tRamp micro-seconds ahead of the first bit of the tx_data which can be used to turn on the Radio transmitter."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RX_EN_DELAY,The delay used to assert rif_rx_en Rx_tRamp micro-seconds ahead of first bit of the expected rx_data which can be used to turn on the Radio receiver."
|
|
line.long 0x8 "EXT_PA_LNA_DLY_CNFG,External TX PA and RX LNA delay configuration"
|
|
hexmask.long.byte 0x8 8.--15. 1. "PA_CTL_DELAY,The delay used to assert PA_CTL exactly PA_tRamp micro-seconds ahead of the first bit of the tx_data which can be used to turn on the external power amplifier."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "LNA_CTL_DELAY,The delay used to assert LNA_CTL LNA_tRamp micro-seconds ahead of first bit of the expected rx_data which can be used to turn on the external Low Noise Amplifier."
|
|
group.long 0xE10++0x3
|
|
line.long 0x0 "LL_CONFIG,Link Layer additional configuration"
|
|
bitfld.long 0x0 14. "ADV_DIR_DEVICE_PRIV_EN,Controls the ADV behavior while advertising ADV_DIR and only device privacy is set. When the ADV is transmitting INITA RPA the bahavior when an Identity address in received from the Initiator in the CONN_REQ is given below" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MULTI_ENGINE_LPM,Controls the LPM entry condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CHECK_DUP_CONN,Controls the duplicate connection checkin ADV and INIT" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "FORCE_TRIG_RCB_UPDATE,Controls the RCB update to radio on TX/RX enable. Applicable only when TX_RX_CTRL_SEL is 1'b1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RSSI_EACH_PKT,Controls the RSSI reads." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RSSI_ENERGY_RD,Controls the RSSI reads." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TX_PA_PWR_LVL_TYPE,Controls the TX power level format given to the CYBLERD55 chip." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TX_RX_PIN_DLY,Controls the delay from DBUS_TX DBUS_RX assertion to the assertion on the pins. This is applicable only when TX_RX_CTRL_SEL is set." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RSSI_EARLY_CNFG,Controls the early RSSI reads. This is applicable only when RSSI_SEL is 1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RSSI_INTR_SEL,Controls the engine interrupt generation based on RSSI reads. This is valid only if RSSI_SEL is 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TIMER_LF_SLOT_ENABLE,Controls the wakeup timer configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TIFS_ENABLE,Setting this bit enables the tx 1MHz pulse to match the received bpktctl from CYBLERD55. This will result is reduced TIFS variation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TX_RX_CTRL_SEL,Controls the mode of issueing TX_EN & RX_EN to the Radio" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RSSI_SEL,Controls the RSSI reads. When this bit is 1 the bit RSSI_INTR_SEL is don't care." "0,1"
|
|
group.long 0xF00++0xF
|
|
line.long 0x0 "LL_CONTROL,LL Backward compatibility"
|
|
bitfld.long 0x0 15. "ADVCH_FIFO_FLUSH,When set flushes the ADVCH FIFO. The bit is auto cleared." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "SLV_CONN_PEER_RPA_NOT_RSLVD,This bit is asserted when SLV_CONN_PEER_RPA_UNMCH_INTR is set. The device does not enter into Connection established state until this bit is cleared after the RPA is resoved by the firmware. If the firmware is not able to.." "0,1"
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|
newline
|
|
bitfld.long 0x0 13. "EN_CONN_RX_EN_MOD,This bit controls the Connection RX enable modification mode when SLV_CONN_PEER_RPA_NOT_RSLVD is set." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PRIV_1_2_INIT,Enables Privacy 1.2 for INIT engine" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PRIV_1_2_SCAN,Enables Privacy 1.2 for SCAN engine" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "PRIV_1_2_ADV,Enables Privacy 1.2 for ADV engine" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI,This bit controls the INIT engine behavior when a self address match occurs but a privacy mismatch occurs" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI,This bit controls the INIT engine behavior when an peer address match occurs but a privacy mismatch occurs" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN,This bit controls the SCAN engine behavior when an peer address match occurs but a privacy mismatch occurs" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV,This bit controls the ADV engine behavior when a scanner address match occurs but a privacy mismatch occurs" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV,This bit controls the ADV engine behavior when an initiator address match occurs but a privacy mismatch occurs" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "HW_RSLV_LIST_FULL,This bit indicates that the resolving list in the hardware is full and the list is extended in the FW. This will affect the behavior of address resolution." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL,Controls the ADVCH FIFO flushing when PRIV_1_2 is enabled." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "WL_READ_AS_MEM,The Whilelist read logic is controlled using this bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DLE,Enables Data Length extension feature in DTM connection and encryption modules." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PRIV_1_2,Enables Privacy 1.2 Feature." "0,1"
|
|
line.long 0x4 "DEV_PA_ADDR_L,Device Resolvable/Non-Resolvable Private address lower register"
|
|
hexmask.long.word 0x4 0.--15. 1. "DEV_PA_ADDR_L,Lower 16 bit of 48-bit Random Private address of the device."
|
|
line.long 0x8 "DEV_PA_ADDR_M,Device Resolvable/Non-Resolvable Private address middle register"
|
|
hexmask.long.word 0x8 0.--15. 1. "DEV_PA_ADDR_M,Middle 16 bit of 48-bit Random Private address of the device."
|
|
line.long 0xC "DEV_PA_ADDR_H,Device Resolvable/Non-Resolvable Private address higher register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DEV_PA_ADDR_H,Higher 16 bit of 48-bit Random Private address of the device."
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xF10)++0x3
|
|
line.long 0x0 "RSLV_LIST_ENABLE[$1],Resolving list entry control bit"
|
|
bitfld.long 0x0 10. "ENTRY_CONNECTED,Indicates if the entry is already in connection with our device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SELF_ADDR_TYPE_TX,Indicates the TX addr type to be used for SCANA and INITA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SELF_ADDR_INIT_RPA_SEL,When Initiator whitelist is disabled this bit indicates the specific device to from which ADV packets will be accepted." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SELF_ADDR_TX_RPA_VAL,Indicates that the self RPA in the list to be transmitted is valid" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "SELF_ADDR_RXD_RPA_VAL,Indicates that the received self RPA in the list is valid" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PEER_ADDR_RPA_VAL,Indicates that the peer device RPA in the list is valid" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PEER_ADDR_TYPE,Indicates the address type of the listed peer device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "WHITELISTED_PEER,Indicates if the listed peer device is in the whitelist" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SELF_ADDR_IRK_SET_RX,Indicates if the local IRK has been shared with the listed peer device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PEER_ADDR_IRK_SET,Indicates if the listed peer device has shared its IRK." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "VALID_ENTRY,Indicates if the index is valid" "0,1"
|
|
repeat.end
|
|
group.long 0xFA0++0x3
|
|
line.long 0x0 "WL_CONNECTION_STATUS,whitelist valid entry bit"
|
|
hexmask.long.word 0x0 0.--15. 1. "WL_ENTRY_CONNECTED,Stores the connection status of each of the sixteen device address stored in the whitelist."
|
|
group.long 0x1800++0x3
|
|
line.long 0x0 "CONN_RXMEM_BASE_ADDR_DLE,DLE Connection RX memory base address"
|
|
hexmask.long 0x0 0.--31. 1. "CONN_RX_MEM_BASE_ADDR_DLE,Data from Rx memory are read as 32-bit wide data. This memory is valid only if DLE is set."
|
|
group.long 0x2800++0x3
|
|
line.long 0x0 "CONN_TXMEM_BASE_ADDR_DLE,DLE Connection TX memory base address"
|
|
hexmask.long 0x0 0.--31. 1. "CONN_TX_MEM_BASE_ADDR_DLE,Data to Tx memory are written as 32-bit wide data. This memory is valid only if DLE is set."
|
|
group.long 0x12800++0x3
|
|
line.long 0x0 "CONN_1_PARAM_MEM_BASE_ADDR,Connection Parameter memory base address for connection 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CONN_1_PARAM,N/A"
|
|
group.long 0x12880++0x3
|
|
line.long 0x0 "CONN_2_PARAM_MEM_BASE_ADDR,Connection Parameter memory base address for connection 2"
|
|
hexmask.long.word 0x0 0.--15. 1. "CONN_2_PARAM,N/A"
|
|
group.long 0x12900++0x3
|
|
line.long 0x0 "CONN_3_PARAM_MEM_BASE_ADDR,Connection Parameter memory base address for connection 3"
|
|
hexmask.long.word 0x0 0.--15. 1. "CONN_3_PARAM,N/A"
|
|
group.long 0x12980++0x3
|
|
line.long 0x0 "CONN_4_PARAM_MEM_BASE_ADDR,Connection Parameter memory base address for connection 4"
|
|
hexmask.long.word 0x0 0.--15. 1. "CONN_4_PARAM,N/A"
|
|
group.long 0x14000++0xF
|
|
line.long 0x0 "NI_TIMER,Next Instant Timer"
|
|
hexmask.long.word 0x0 0.--15. 1. "NI_TIMER,BT Slot at which the next connection has to be serviced granularity is 625us. The NI timer has to be programmed 1.25ms before the connection event"
|
|
line.long 0x4 "US_OFFSET,Micro-second Offset"
|
|
hexmask.long.word 0x4 0.--9. 1. "US_OFFSET_SLOT_BOUNDARY,Micro Second Offset from the Slot Bounday at which the connection programmed in NEXT_CONN has to be serviced. This register along with NI_TIMER has to be programmed 1.25ms before the connection event. The granularity is 1us"
|
|
line.long 0x8 "NEXT_CONN,Next Connection"
|
|
bitfld.long 0x8 6. "NI_VALID,Flag indication if programmed NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the connection of if NI_TIMER is pointing to past value" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "NEXT_CONN_TYPE,Connection type" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "NEXT_CONN_INDEX,Connection Index to be serviced. Allowed values are 0 1 2 3."
|
|
line.long 0xC "NI_ABORT,Abort next scheduled connection"
|
|
bitfld.long 0xC 1. "ABORT_ACK,This bit will set if the scheduled NI is aborted" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "NI_ABORT,Setting this bit clears the schedule NI" "0,1"
|
|
rgroup.long 0x14020++0x1F
|
|
line.long 0x0 "CONN_NI_STATUS,Connection NI Status"
|
|
hexmask.long.word 0x0 0.--15. 1. "CONN_NI,HW updates this register with the next Connection Instant for current serviced connection granularity is 625us. The reset value is 0x0000. After reset deassertion then the very next clock the value assigned to the registers is 0xFFFF."
|
|
line.long 0x4 "NEXT_SUP_TO_STATUS,Next Supervision timeout Status"
|
|
hexmask.long.word 0x4 0.--15. 1. "NEXT_SUP_TO,HW updates this register for the SuperVision timeout next instant granularity is 625us"
|
|
line.long 0x8 "MMMS_CONN_STATUS,Connection Status"
|
|
bitfld.long 0x8 15. "ANCHOR_PT_STATE,Anchor Point State" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "PKT_MISS,1 - Packet Missed" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--13. 1. "LAST_UNMAPPED_CHANNEL,Last Unmapped Channel"
|
|
newline
|
|
bitfld.long 0x8 7. "NESN_CURR,Next Sequence Number" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "SN_CURR,Sequence Number of Packets exchanged" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "CURR_CONN_TYPE,Connection type" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "CURR_CONN_INDEX,Connection Index that was serviced. Legal values are 0 1 2 3."
|
|
line.long 0xC "BT_SLOT_CAPT_STATUS,BT Slot Captured Status"
|
|
hexmask.long.word 0xC 0.--15. 1. "BT_SLOT,During slave connection event HW updates this register with the captured BT_SLOT at anchor point granularity is 625us"
|
|
line.long 0x10 "US_CAPT_STATUS,Micro-second Capture Status"
|
|
hexmask.long.word 0x10 0.--9. 1. "US_CAPT,During slave connection event HW updates this register with the captured microsecond at anchor point granularity is 1us"
|
|
line.long 0x14 "US_OFFSET_STATUS,Micro-second Offset Status"
|
|
hexmask.long.word 0x14 0.--15. 1. "US_OFFSET,During slave connection event HW updates this register with the calculated us_offset at anchor point granularity is 1us. The reset value is 0x0000. After reset deassertion then the very next clock the value assigned to the registers is.."
|
|
line.long 0x18 "ACCU_WINDOW_WIDEN_STATUS,Accumulated Window Widen Status"
|
|
hexmask.long.word 0x18 0.--15. 1. "ACCU_WINDOW_WIDEN,Accumulated Window Widen Value. HW updates this register at the close of slave connection event"
|
|
line.long 0x1C "EARLY_INTR_STATUS,Status when early interrupt is raised"
|
|
hexmask.long.word 0x1C 6.--15. 1. "US_FOR_EARLY_INTR,US offset when early interrupt is raised"
|
|
newline
|
|
bitfld.long 0x1C 5. "CONN_TYPE_FOR_EARLY_INTR,Connection type for which early interrupt is raised." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--4. 1. "CONN_INDEX_FOR_EARLY_INTR,Connection Index for which early interrupt is raised"
|
|
group.long 0x14040++0x3
|
|
line.long 0x0 "MMMS_CONFIG,Multi-Master Multi-Slave Config"
|
|
bitfld.long 0x0 10. "RESET_RX_FIFO_PTR,Setting this bit resets the receive FIFO pointers" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CE_LEN_IMMEDIATE_EXPIRE,Enable for CE length immediate expiry" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--8. 1. "ADV_CONN_INDEX,This field specifies the connection index for which ADV is enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "CONN_PARAM_FROM_REG,By default the parameters for the connection are picked up from the connection parameters memory. Setting this bit disables this and the parameters are picked up from registers" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DISABLE_CONN_PARAM_MEM_WR,By default on end_ce the connection parameters memory is loaded with the updated connection parameters. Setting this bit prevent's this update." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DISABLE_CONN_REQ_PARAM_IN_MEM,If set to 1'b1 and MMMS enabled then the parameters received in connection request are not stored in CONN_REQ_PARAM memory. By default this bit is 1'b0 and the connection request parameters are stored in connection memory." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MMMS_ENABLE,Configuration bit to enable MMMS functionality" "0,1"
|
|
rgroup.long 0x14044++0x3
|
|
line.long 0x0 "US_COUNTER,Running US of the current BT Slot"
|
|
hexmask.long.word 0x0 0.--9. 1. "US_COUNTER,Current value of the US Counter"
|
|
group.long 0x14048++0x3
|
|
line.long 0x0 "US_CAPT_PREV,Previous captured US of the BT Slot"
|
|
hexmask.long.word 0x0 0.--9. 1. "US_CAPT_LOAD,HW uses this register to load the us_offset from connection parameter memory. This can be used by firmware as a fail safe option if the HW load from memory is disabled. In alll other conditions firmware should not use this register."
|
|
rgroup.long 0x1404C++0x3
|
|
line.long 0x0 "EARLY_INTR_NI,NI at early interrupt"
|
|
hexmask.long.word 0x0 0.--15. 1. "EARLY_INTR_NI,Connection Next instant when the early interrupt is triggered"
|
|
rgroup.long 0x14080++0xB
|
|
line.long 0x0 "MMMS_MASTER_CREATE_BT_CAPT,BT slot capture for master connection creation"
|
|
hexmask.long.word 0x0 0.--15. 1. "BT_SLOT,This register captures the BT_SLOT when master connection is created granularity is 625us"
|
|
line.long 0x4 "MMMS_SLAVE_CREATE_BT_CAPT,BT slot capture for slave connection creation"
|
|
hexmask.long.word 0x4 0.--9. 1. "US_CAPT,This register captures the BT_SLOT when slave connection is created granularity is 625us"
|
|
line.long 0x8 "MMMS_SLAVE_CREATE_US_CAPT,Micro second capture for slave connection creation"
|
|
hexmask.long.word 0x8 0.--15. 1. "US_OFFSET_SLAVE_CREATED,This register captures the us when slave connection is created granularity is 1us"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x14100)++0x3
|
|
line.long 0x0 "MMMS_DATA_MEM_DESCRIPTOR[$1],Data buffer descriptor 0 to 15"
|
|
hexmask.long.byte 0x0 2.--9. 1. "DATA_LENGTH_C1,This field indicates the length of the data packet. Bits [9:7] are valid only if DLE is set."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "LLID_C1,N/A" "0,1,2,3"
|
|
repeat.end
|
|
group.long 0x14200++0xB
|
|
line.long 0x0 "CONN_1_DATA_LIST_SENT,data list sent update and status for connection 1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "BUFFER_NUM_TX_SENT_3_0_C1,Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16 can be shared with up to 8.."
|
|
newline
|
|
bitfld.long 0x0 7. "SET_CLEAR_C1,Write: Used to set the SENT bit in hardware for the selected packet buffer." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "LIST_INDEX__TX_SENT_3_0_C1,Write:Indicates the buffer index for which the SENT bit is being updated by firmware."
|
|
line.long 0x4 "CONN_1_DATA_LIST_ACK,data list ack update and status for connection 1"
|
|
bitfld.long 0x4 7. "SET_CLEAR_C1,Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "LIST_INDEX__TX_ACK_3_0_C1,Write: Indicates the buffer index for which the ACK bit is being updated by firmware."
|
|
line.long 0x8 "CONN_1_CE_DATA_LIST_CFG,Connection specific pause resume for connection 1"
|
|
hexmask.long.byte 0x8 12.--15. 1. "CURRENT_PDU_INDEX_C1,The index of the transmit packet buffer that is currently in transmission/waiting for transmission."
|
|
newline
|
|
bitfld.long 0x8 11. "EMPTYPDU_SENT,This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "KILL_CONN_AFTER_TX,Kills the connection when the connection event is active and a TX is completed" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "KILL_CONN,Kills the connection immediately when the connection event is active" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "PAUSE_DATA_C1,Pause data." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "MD_BIT_CLEAR_C1,This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or 'hardware and software logic combined'" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "MD_C1,MD bit set to '1' indicates device has more data to be sent." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SLV_MD_CONFIG_C1,This bit is set to configure the MD bit control when the design is in slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "DATA_LIST_HEAD_UP_C1,Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "DATA_LIST_INDEX_LAST_ACK_INDEX_C1,Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded."
|
|
group.long 0x14210++0xB
|
|
line.long 0x0 "CONN_2_DATA_LIST_SENT,data list sent update and status for connection 2"
|
|
hexmask.long.byte 0x0 8.--11. 1. "BUFFER_NUM_TX_SENT_3_0_C1,Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16 can be shared with up to 8.."
|
|
newline
|
|
bitfld.long 0x0 7. "SET_CLEAR_C1,Write: Used to set the SENT bit in hardware for the selected packet buffer." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "LIST_INDEX__TX_SENT_3_0_C1,Write:Indicates the buffer index for which the SENT bit is being updated by firmware."
|
|
line.long 0x4 "CONN_2_DATA_LIST_ACK,data list ack update and status for connection 2"
|
|
bitfld.long 0x4 7. "SET_CLEAR_C1,Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "LIST_INDEX__TX_ACK_3_0_C1,Write: Indicates the buffer index for which the ACK bit is being updated by firmware."
|
|
line.long 0x8 "CONN_2_CE_DATA_LIST_CFG,Connection specific pause resume for connection 2"
|
|
hexmask.long.byte 0x8 12.--15. 1. "CURRENT_PDU_INDEX_C1,The index of the transmit packet buffer that is currently in transmission/waiting for transmission."
|
|
newline
|
|
bitfld.long 0x8 11. "EMPTYPDU_SENT,This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "KILL_CONN_AFTER_TX,Kills the connection when the connection event is active and a TX is completed" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "KILL_CONN,Kills the connection immediately when the connection event is active" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "PAUSE_DATA_C1,Pause data." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "MD_BIT_CLEAR_C1,This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or 'hardware and software logic combined'" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "MD_C1,MD bit set to '1' indicates device has more data to be sent." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SLV_MD_CONFIG_C1,This bit is set to configure the MD bit control when the design is in slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "DATA_LIST_HEAD_UP_C1,Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "DATA_LIST_INDEX_LAST_ACK_INDEX_C1,Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded."
|
|
group.long 0x14220++0xB
|
|
line.long 0x0 "CONN_3_DATA_LIST_SENT,data list sent update and status for connection 3"
|
|
hexmask.long.byte 0x0 8.--11. 1. "BUFFER_NUM_TX_SENT_3_0_C1,Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16 can be shared with up to 8.."
|
|
newline
|
|
bitfld.long 0x0 7. "SET_CLEAR_C1,Write: Used to set the SENT bit in hardware for the selected packet buffer." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "LIST_INDEX__TX_SENT_3_0_C1,Write:Indicates the buffer index for which the SENT bit is being updated by firmware."
|
|
line.long 0x4 "CONN_3_DATA_LIST_ACK,data list ack update and status for connection 3"
|
|
bitfld.long 0x4 7. "SET_CLEAR_C1,Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "LIST_INDEX__TX_ACK_3_0_C1,Write: Indicates the buffer index for which the ACK bit is being updated by firmware."
|
|
line.long 0x8 "CONN_3_CE_DATA_LIST_CFG,Connection specific pause resume for connection 3"
|
|
hexmask.long.byte 0x8 12.--15. 1. "CURRENT_PDU_INDEX_C1,The index of the transmit packet buffer that is currently in transmission/waiting for transmission."
|
|
newline
|
|
bitfld.long 0x8 11. "EMPTYPDU_SENT,This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "KILL_CONN_AFTER_TX,Kills the connection when the connection event is active and a TX is completed" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "KILL_CONN,Kills the connection immediately when the connection event is active" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "PAUSE_DATA_C1,Pause data." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "MD_BIT_CLEAR_C1,This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or 'hardware and software logic combined'" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "MD_C1,MD bit set to '1' indicates device has more data to be sent." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SLV_MD_CONFIG_C1,This bit is set to configure the MD bit control when the design is in slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "DATA_LIST_HEAD_UP_C1,Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "DATA_LIST_INDEX_LAST_ACK_INDEX_C1,Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded."
|
|
group.long 0x14230++0xB
|
|
line.long 0x0 "CONN_4_DATA_LIST_SENT,data list sent update and status for connection 4"
|
|
hexmask.long.byte 0x0 8.--11. 1. "BUFFER_NUM_TX_SENT_3_0_C1,Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16 can be shared with up to 8.."
|
|
newline
|
|
bitfld.long 0x0 7. "SET_CLEAR_C1,Write: Used to set the SENT bit in hardware for the selected packet buffer." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "LIST_INDEX__TX_SENT_3_0_C1,Write:Indicates the buffer index for which the SENT bit is being updated by firmware."
|
|
line.long 0x4 "CONN_4_DATA_LIST_ACK,data list ack update and status for connection 4"
|
|
bitfld.long 0x4 7. "SET_CLEAR_C1,Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "LIST_INDEX__TX_ACK_3_0_C1,Write: Indicates the buffer index for which the ACK bit is being updated by firmware."
|
|
line.long 0x8 "CONN_4_CE_DATA_LIST_CFG,Connection specific pause resume for connection 4"
|
|
hexmask.long.byte 0x8 12.--15. 1. "CURRENT_PDU_INDEX_C1,The index of the transmit packet buffer that is currently in transmission/waiting for transmission."
|
|
newline
|
|
bitfld.long 0x8 11. "EMPTYPDU_SENT,This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "KILL_CONN_AFTER_TX,Kills the connection when the connection event is active and a TX is completed" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "KILL_CONN,Kills the connection immediately when the connection event is active" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "PAUSE_DATA_C1,Pause data." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "MD_BIT_CLEAR_C1,This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or 'hardware and software logic combined'" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "MD_C1,MD bit set to '1' indicates device has more data to be sent." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SLV_MD_CONFIG_C1,This bit is set to configure the MD bit control when the design is in slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "DATA_LIST_HEAD_UP_C1,Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "DATA_LIST_INDEX_LAST_ACK_INDEX_C1,Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded."
|
|
group.long 0x14400++0xB
|
|
line.long 0x0 "MMMS_ADVCH_NI_ENABLE,Enable bits for ADV_NI. SCAN_NI and INIT_NI"
|
|
bitfld.long 0x0 2. "INIT_NI_ENABLE,This bit is used to enable the INIT NI timer and is valid when MMMS_ENABLE=1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SCAN_NI_ENABLE,This bit is used to enable the SCAN NI timer and is valid when MMMS_ENABLE=1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ADV_NI_ENABLE,This bit is used to enable the Advertisement NI timer and is valid when MMMS_ENABLE=1." "0,1"
|
|
line.long 0x4 "MMMS_ADVCH_NI_VALID,Next instant valid for ADV. SCAN. INIT"
|
|
bitfld.long 0x4 2. "INIT_NI_VALID,This bit indicates if the programmed initiator NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the initiator event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "SCAN_NI_VALID,This bit indicates if the programmed scan NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the scanner event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "ADV_NI_VALID,This bit indicates if the programmed advertisement NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the advertisment event" "0,1"
|
|
line.long 0x8 "MMMS_ADVCH_NI_ABORT,Abort the next instant of ADV. SCAN. INIT"
|
|
bitfld.long 0x8 1. "ADVCH_ABORT_STATUS,The link layer hardware logic will set this bit when the NI_TIMER is aborted. Firmware to clear this by writing 1'b1 to this register bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ADVCH_NI_ABORT,FW can use this bit to clear an unserviced NI_VALID for Advertisement or scanner or initiator. HW will clear NI_VALID for ADV/SCAN/INIT if the event has not yet started" "0,1"
|
|
group.long 0x14410++0x7
|
|
line.long 0x0 "CONN_PARAM_NEXT_SUP_TO,Register to configure the supervision timeout for next scheduled connection"
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT_SUP_TO_LOAD,HW uses this register to load the Supervision timeout Next instant from the connection memory. This can be used by firmware as a failsafe option when the hardware load is disabled. In all other conditions this register should not be.."
|
|
line.long 0x4 "CONN_PARAM_ACC_WIN_WIDEN,Register to configure Accumulated window widening for next scheduled connection"
|
|
hexmask.long.word 0x4 0.--9. 1. "ACC_WINDOW_WIDEN,HW uses this register to load the accumulated window windeing value from the connection memory. This can be used by firmware as a failsafe option when the hardware load is disabled. In all other conditions this register should not be.."
|
|
group.long 0x14420++0x3
|
|
line.long 0x0 "HW_LOAD_OFFSET,Register to configure offset from connection anchor point at which connection parameter memory should be read"
|
|
hexmask.long.byte 0x0 0.--4. 1. "LOAD_OFFSET,Load Offset in us before connection event at which the connection parameters are loaded from memory granularity is in 1us"
|
|
rgroup.long 0x14424++0x7
|
|
line.long 0x0 "ADV_RAND,Random number generated by Hardware for ADV NI calculation"
|
|
hexmask.long.byte 0x0 0.--3. 1. "ADV_RAND,Random ADV delay to be used for ADV next instant calculation. The granularity is in BT slot"
|
|
line.long 0x4 "MMMS_RX_PKT_CNTR,Packet Counter of packets in RX FIFO in MMMS mode"
|
|
hexmask.long.byte 0x4 0.--5. 1. "MMMS_RX_PKT_CNT,Count of all packets in the RX FIFO in MMMS mode"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x14430)++0x3
|
|
line.long 0x0 "CONN_RX_PKT_CNTR[$1],Packet Counter for Individual connection index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "RX_PKT_CNT,Number of packets received for the connection. Incremented when the packet is received during the connection event and decremented when firmware has processed the packet. The register field FW_PKT_RCV_CONN_INDEX should be programmed before.."
|
|
repeat.end
|
|
group.long 0x14800++0x3
|
|
line.long 0x0 "WHITELIST_BASE_ADDR,Whitelist base address"
|
|
hexmask.long.word 0x0 0.--15. 1. "WL_BASE_ADDR,Device address values written to white list memory are written as 16-bit wide address."
|
|
group.long 0x148C0++0x3
|
|
line.long 0x0 "RSLV_LIST_PEER_IDNTT_BASE_ADDR,Resolving list base address for storing Peer Identity address"
|
|
hexmask.long.word 0x0 0.--15. 1. "RSLV_LIST_PEER_IDNTT_BASE_ADDR,Device address values written to the list are written as 16-bit wide address."
|
|
group.long 0x14980++0x3
|
|
line.long 0x0 "RSLV_LIST_PEER_RPA_BASE_ADDR,Resolving list base address for storing resolved Peer RPA address"
|
|
hexmask.long.word 0x0 0.--15. 1. "RSLV_LIST_PEER_RPA_BASE_ADDR,Device address values written to the list are written as 16-bit wide address."
|
|
group.long 0x14A40++0x3
|
|
line.long 0x0 "RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR,Resolving list base address for storing Resolved received INITA RPA"
|
|
hexmask.long.word 0x0 0.--15. 1. "RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR,Device address values written to the list are written as 16-bit wide address."
|
|
group.long 0x14B00++0x3
|
|
line.long 0x0 "RSLV_LIST_TX_INIT_RPA_BASE_ADDR,Resolving list base address for storing generated TX INITA RPA"
|
|
hexmask.long.word 0x0 0.--15. 1. "RSLV_LIST_TX_INIT_RPA_BASE_ADDR,Device address values written to the list are written as 16-bit wide address."
|
|
tree.end
|
|
tree "BLESS (Bluetooth Low Energy Subsystem Miscellaneous)"
|
|
base ad:0x403DF000
|
|
group.long 0x60++0x1B
|
|
line.long 0x0 "DDFT_CONFIG,BLESS DDFT configuration register"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DDFT_MUX_CFG2,dbg_mux_pin2 selection combine with BLERD and BLESS"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DDFT_MUX_CFG1,dbg_mux_pin1 selection combine with BLERD and BLESS"
|
|
newline
|
|
bitfld.long 0x0 1. "BLERD_DDFT_EN,Enables the DDFT inputs from CYBLERD55 chip" "0: DDFT inputs are disabled,1: DDFT inputs are enabled"
|
|
bitfld.long 0x0 0. "DDFT_ENABLE,Enables the DDFT output from BLESS" "0: DDFT is disabled,1: DDFT is enabled"
|
|
line.long 0x4 "XTAL_CLK_DIV_CONFIG,Crystal clock divider configuration register"
|
|
bitfld.long 0x4 2.--3. "LLCLK_DIV,Link Layer clock pre-divider value. The 24 MHz crystal clock is divided to generate the Link Layer clock." "0: NO_DIV: LLCLK= XTALCLK/1,1: DIV_BY_2: LLCLK= XTALCLK/2,2: DIV_BY_4: LLCLK= XTALCLK/4,3: DIV_BY_8: LLCLK= XTALCLK/8"
|
|
bitfld.long 0x4 0.--1. "SYSCLK_DIV,System clock pre-divider value. The 24 MHz crystal clock is divided to generate the system clock." "0: NO_DIV: SYSCLK= XTALCLK/1,1: DIV_BY_2: SYSCLK= XTALCLK/2,2: DIV_BY_4: SYSCLK= XTALCLK/4,3: DIV_BY_8: SYSCLK= XTALCLK/8"
|
|
line.long 0x8 "INTR_STAT,Link Layer interrupt status register"
|
|
bitfld.long 0x8 11. "HVLDO_LV_DETECT_NEG,This interrupt is set on HVLDO LV Detector Fall edge. There is a 1cycle AHB clock glitch filter on the HVLDO LV Detector output" "0,1"
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bitfld.long 0x8 10. "HVLDO_LV_DETECT_POS,This interrupt is set on HVLDO LV Detector Rise edge. There is a 1cycle AHB clock glitch filter on the HVLDO LV Detector output" "0,1"
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newline
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rbitfld.long 0x8 9. "ENC_INTR,Encryption Interrupt Triggered" "0,1"
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|
bitfld.long 0x8 8. "XTAL_ON_INTR,enabled crystal stable signal rising edge interrupt. The interrupt can be cleared by writing one into this location." "0,1"
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|
newline
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bitfld.long 0x8 7. "EFUSE_INTR,This bit when set by efuse controller logic when the efuse read/write is completed" "0,1"
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|
bitfld.long 0x8 6. "GPIO_INTR,GPIO interrupt" "0,1"
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newline
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rbitfld.long 0x8 5. "LL_INTR,LL controller interrupt - Refer to EVENT_INTR register" "0,1"
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|
rbitfld.long 0x8 4. "RCB_INTR,RCB controller Interrupt - Refer to RCB_INTR_STAT register" "0,1"
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newline
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bitfld.long 0x8 3. "BLERD_ACTIVE_INTR,CYBLERD55 is in active mode. RF is active" "0,1"
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|
rbitfld.long 0x8 2. "RCBLL_DONE_INTR,RCB transaction Complete" "0,1"
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newline
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bitfld.long 0x8 1. "DSM_EXITED_INTR,On a firmware request to LL to exit from Deep Sleep Mode working on LF clock LL transitions from Deep Sleep Mode and asserts this interrupt when the Deep Sleep clock gater is turned ON. The interrupt can be cleared by writing one into.." "0,1"
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bitfld.long 0x8 0. "DSM_ENTERED_INTR,On a firmware request to LL to enter into state machine working on LF clock LL transitions into Deep Sleep Mode and asserts this interrupt. The interrupt can be cleared by writing one into this location." "0,1"
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line.long 0xC "INTR_MASK,Link Layer interrupt mask register"
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|
bitfld.long 0xC 12. "HVLDO_LV_DETECT_NEG_MASK,Mask for HVLDO LV Detector Fall edge interrupt" "0,1"
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|
bitfld.long 0xC 11. "HVLDO_LV_DETECT_POS_MASK,Mask for HVLDO LV Detector Rise edge interrupt" "0,1"
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|
newline
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bitfld.long 0xC 10. "ENC_INTR_MASK,Mask for Encryption interrupt" "0,1"
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|
bitfld.long 0xC 9. "EFUSE_INTR_MASK,This bit enables the efuse interrupt to firmware" "0,1"
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|
newline
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bitfld.long 0xC 8. "GPIO_INTR_MASK,Mask for GPIO interrupt" "0,1"
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|
bitfld.long 0xC 7. "LL_INTR_MASK,Mask for LL interrupt" "0,1"
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newline
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bitfld.long 0xC 6. "RCB_INTR_MASK,Mask for RCB interrupt" "0,1"
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|
bitfld.long 0xC 5. "BLERD_ACTIVE_INTR_MASK,Mask for CYBLERD55 Active Interrupt" "0,1"
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newline
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bitfld.long 0xC 4. "RCBLL_INTR_MASK,Mask for RCBLL interrupt" "0,1"
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|
bitfld.long 0xC 3. "XTAL_ON_INTR_MASK,Masks the Crystal Stable Interrupt when disabled." "0,1"
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|
newline
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bitfld.long 0xC 2. "DSM_EXITED_INTR_MASK,Masks the DSM Exited Interrupt when disabled." "0,1"
|
|
bitfld.long 0xC 1. "DSM_ENTERED_INTR_MASK,Masks the DSM Entered Interrupt when disabled." "0,1"
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newline
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bitfld.long 0xC 0. "DSM_EXIT,When the Link Layer is in Deep Sleep Mode firmware can set this bit to wake the Link Layer." "0,1"
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|
line.long 0x10 "LL_CLK_EN,Link Layer primary clock enable"
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bitfld.long 0x10 5. "DPSLP_HWRCB_EN,Controls the DPSLP entry and exit writes to RD and controls the active domain reset and clock." "0,1"
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|
bitfld.long 0x10 4. "BLESS_RESET,0: No Soft Reset" "0: No Soft Reset,1: Initiate Soft Reset"
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newline
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bitfld.long 0x10 3. "SEL_RCB_CLK,0: AHB clock (clk_sys) is used as the clock for RCB access" "0: AHB clock,1: LL clock"
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bitfld.long 0x10 2. "MXD_IF_OPTION,1: MXD IF option 0: CYBLERD55 correlates Access Code" "0: MXD IF option,1: LL correlates Access Code"
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newline
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bitfld.long 0x10 1. "CY_CORREL_EN,If MXD_IF option is 1 this bit needs to be set to enable configuring the correlator through BLELL.DPLL_CONFIG register" "0,1"
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bitfld.long 0x10 0. "CLK_EN,Set this bit 1 to enable the clock to Link Layer." "0,1"
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line.long 0x14 "LF_CLK_CTRL,BLESS LF clock control and BLESS revision ID indicator"
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rbitfld.long 0x14 29.--31. "M0S8BLESS_REV_ID,Indicates the m0s8bless IP revision." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 1. "ENABLE_ENC_CLK,This bit is used to enable the clock to the encryption engine" "0,1"
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newline
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bitfld.long 0x14 0. "DISABLE_LF_CLK,When set to 1 gates the LF clock input to the Link Layer. Ths is done for extended DSM mode where the DSM state machine needs to be forzen to prevent a default auto exit." "0,1"
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line.long 0x18 "EXT_PA_LNA_CTRL,External TX PA and RX LNA control"
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bitfld.long 0x18 5. "OUT_EN_DRIVE_VAL,Configures the drive value on the output enables of PA LNA and CHI_EN signals" "0,1"
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bitfld.long 0x18 4. "LNA_CTRL_POL,Controls the polarity of the LNA control signal" "0,1"
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newline
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bitfld.long 0x18 3. "PA_CTRL_POL,Controls the polarity of the PA control signal" "0,1"
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bitfld.long 0x18 2. "CHIP_EN_POL,Controls the polarity of the chip enable control signal" "0,1"
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newline
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bitfld.long 0x18 1. "ENABLE_EXT_PA_LNA,When set to 1 enables the external PA & LNA" "0,1"
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rgroup.long 0x80++0x7
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line.long 0x0 "LL_PKT_RSSI_CH_ENERGY,Link Layer Last Received packet RSSI/Channel energy and channel number"
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bitfld.long 0x0 22. "PKT_RSSI_OR_CH_ENERGY,This field indicates if the captured RSSI is for a received packet or is the channel energy" "0,1"
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hexmask.long.byte 0x0 16.--21. 1. "RX_CHANNEL,This field indicates the last channel for which the RSSI is captured"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RSSI,This field captures the RSSI of the packet when a packet reception is complete or gives the Channel energy when a Receive cycle is over without packet reception."
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line.long 0x4 "BT_CLOCK_CAPT,BT clock captured on an LL DSM exit"
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hexmask.long.word 0x4 0.--15. 1. "BT_CLOCK,This field captures the LF BT clock captured on an LL DSM exit. This register is valid only when MT_STATUS.LL_CLK_STATE is set. This value may be used to manage the low power entry."
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group.long 0xA0++0x13
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line.long 0x0 "MT_CFG,MT Configuration Register"
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bitfld.long 0x0 27. "HVLDO_POR_HV,Reset for HVLDO" "0,1"
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bitfld.long 0x0 26. "RET_LDO_OL,Overrie value for CYBLERD55 RET_LDO_OL_HV" "0,1"
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newline
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bitfld.long 0x0 25. "OVERRIDE_RET_LDO_OL,This register should be set to override the HW generated RET_LDO_OL_HV to CYBLERD55. When set CLK_EN is used." "0,1"
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bitfld.long 0x0 24. "BLERD_CLK_EN,Overrie value for CYBLERD55 CLK_EN" "0,1"
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newline
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bitfld.long 0x0 23. "OVERRIDE_CLK_EN,This register should be set to override the HW generated CLK_EN to CYBLERD55. When set CLK_EN is used." "0,1"
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bitfld.long 0x0 22. "XTAL_EN,Overrie value for CYBLERD55 XTAL_EN" "0,1"
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newline
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bitfld.long 0x0 21. "OVERRIDE_XTAL_EN,This register should be set to override the HW generated XTAL_EN to CYBLERD55. When set XTAL_EN is used." "0,1"
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bitfld.long 0x0 20. "RESET_N,Overrie value for CYBLERD55 RESET_N" "0,1"
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newline
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bitfld.long 0x0 19. "OVERRIDE_RESET_N,This register should be set to override the HW generated reset to CYBLERD55. When set RESET_N is used." "0,1"
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bitfld.long 0x0 18. "DPSLP_ECO_ON,This bit when set indicates that ECO clock should be kept on even in BLESS DPSLP. This bit must be toggled only when the Link Layer is active." "0,1"
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newline
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bitfld.long 0x0 17. "HVLDO_EN,Overrie value for HVLDO enable" "0: switch to standby LDO,1: switch to Active LDO"
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bitfld.long 0x0 16. "OVERRIDE_HVLDO_EN,This register should be set to override the HW generated enable to HVLSO. When set HVLDO_EN is used." "0,1"
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newline
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bitfld.long 0x0 15. "LL_CLK_EN,Override value for LL Clock gate" "0,1"
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bitfld.long 0x0 14. "OVERRIDE_LL_CLK_EN,This register should be set to override the HW generated ECO Clock gate. When set LL_CLK_EN is used to gate the clock" "0,1"
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newline
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bitfld.long 0x0 13. "ISOLATE_N,Override value for isolation to CYBLERD55" "0,1"
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bitfld.long 0x0 12. "OVERRIDE_ISOLATE,This register should be set to override the HW generated isolation signal to CYBLERD55. When set ISOLATE_N is driven to the IP" "0,1"
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newline
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bitfld.long 0x0 11. "RET_SWITCH,Override value for RET_SWITCH" "0,1"
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bitfld.long 0x0 10. "OVERRIDE_RET_SWITCH,This register should be set to override the HW generated signal to the retention switch of CYBLERD55. When set OVERRIDE_RET_SWITCH is driven to the IP" "0,1"
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newline
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bitfld.long 0x0 9. "DIG_REGULATOR_EN,Override value for digital regulator of CYBLERD55" "0,1"
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bitfld.long 0x0 8. "OVERRIDE_DIG_REGULATOR,This register should be set to override the HW generated signal to Digital regulator of CYBLERD55. When set DIG_REGULATOR_EN is driven to CYBLERD55" "0,1"
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newline
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bitfld.long 0x0 7. "ACT_REGULATOR_EN,Override value for ACT_LDO_EN/BUCK_EN" "0,1"
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bitfld.long 0x0 6. "OVERRIDE_ACT_REGULATOR,This register should be set to override the HW generated signal to enable ACTIVE_LDO/BUCK. When set ACT_REGULATOR_EN is driven to CYBLERD55" "0,1"
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newline
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bitfld.long 0x0 5. "HVLDO_BYPASS,Override value for HVLDO BYPASS" "0: bypass the HVLDO,1: Do not bypass the HVLDO"
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bitfld.long 0x0 4. "OVERRIDE_HVLDO_BYPASS,This register should be set to override the HW generated signal to HVLDO. When set HVLDO_BYPASS is driven to the IP" "0,1"
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newline
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bitfld.long 0x0 3. "ACT_LDO_NOT_BUCK,This register bit specifies whether the Active LDO or BUCK in CYBLERD55 is used in active mode" "0,1"
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bitfld.long 0x0 2. "DEEPSLEEP_EXITED,This register bit is used by FW to indicate that PSoC is out of DeepSleep" "0,1"
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newline
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bitfld.long 0x0 1. "DEEPSLEEP_EXIT_CFG,This register bit indicates the source for PSoC DeepSleep exit to BLESS" "0,1"
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bitfld.long 0x0 0. "ENABLE_BLERD,This register bit needs to be set to enable CYBLERD55" "0,1"
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line.long 0x4 "MT_DELAY_CFG,MT Delay configuration for state transitions"
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hexmask.long.byte 0x4 24.--31. 1. "HVLDO_DISABLE_DELAY,This register specifies the time from disabling XTAL to switching of the HVLDO."
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hexmask.long.byte 0x4 16.--23. 1. "ACT_TO_SWITCH_DELAY,This register specifies the time from assertion of ISOLATE_N to switching the CYBLERD55 logic to Retention LDO"
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newline
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hexmask.long.byte 0x4 8.--15. 1. "ISOLATE_DEASSERT_DELAY,This register specifies the time from switching the CYBLERD55 logic to Active regulator to removal of ISOLATE_N"
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hexmask.long.byte 0x4 0.--7. 1. "HVLDO_STARTUP_DELAY,This register specifies the startup delay for the HVLDO interms of number of LF Clock cycles. FW has to program this register based on the selected LF clock frequency"
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line.long 0x8 "MT_DELAY_CFG2,MT Delay configuration for state transitions"
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hexmask.long.byte 0x8 24.--31. 1. "DIG_LDO_STARTUP_DELAY,This register specifes the Digital LDO startup time in CYBLERD55.The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency. The logic in CYBLERD55 is switched to Active mode.."
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hexmask.long.byte 0x8 16.--23. 1. "ACT_STARTUP_DELAY,This register specifes the Active Regulator startup time in CYBLERD55. The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency. The digital LDO will be turned on after this time.."
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newline
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hexmask.long.byte 0x8 8.--15. 1. "DSM_OFFSET_TO_WAKEUP_INSTANT_LF,This register specifies the pre-processing time required in Link Layer. This is esentially the time from CLK_EN (ungating clock in CYBLERD55) to the time when logic in CYBLERD55 is switched to Active mode Regulator.The.."
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hexmask.long.byte 0x8 0.--7. 1. "OSC_STARTUP_DELAY_LF,This register specifies the time for OSC Startup. After this delay clock is enabled to the link layer. Clock is enabled after OSC_STARTUP_DELAY + 1 LF clock cycles. If PSoC was in DPSLP when XTAL is enabled then the wakeup delay.."
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line.long 0xC "MT_DELAY_CFG3,MT Delay configuration for state transitions"
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hexmask.long.byte 0xC 16.--23. 1. "VDDR_STABLE_DELAY,This field holds the delay after HVLDO Startup to VDDR Stable. Refer to memo AKK-410"
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hexmask.long.byte 0xC 8.--15. 1. "DIG_LDO_DISABLE_DELAY,This field holds the delay from the time of diabling Digital LDO to the time at which ACTIVE regulator is disabled"
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newline
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hexmask.long.byte 0xC 0.--7. 1. "XTAL_DISABLE_DELAY,This register specifies the time from switching of logic to Retention LDO in CYBLERD55 to XTAL Disable. This should include the post processing time"
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line.long 0x10 "MT_VIO_CTRL,MT Configuration Register to control VIO switches"
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bitfld.long 0x10 1. "SRSS_SWITCH_EN_DLY,Enable to turn on HVLDO (All legs). This must be enabled 64us after enabling SRSS_SWITCH_EN" "0,1"
|
|
bitfld.long 0x10 0. "SRSS_SWITCH_EN,Enable to turn on HVLDO (One leg)" "0,1"
|
|
rgroup.long 0xB4++0x7
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line.long 0x0 "MT_STATUS,MT Status Register"
|
|
bitfld.long 0x0 8. "LL_CLK_STATE,This bit indicates when the Link Layer registers are accessible upon a DSM exit. This bit should not be used after a DSM entry command has been issued." "0,1"
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bitfld.long 0x0 5.--7. "HVLDO_STARTUP_CURR_STATE,This register reflects the current state of the HVLDO Startup FSM" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x0 1.--4. 1. "MT_CURR_STATE,This register reflects the current state of the MT FSM"
|
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bitfld.long 0x0 0. "BLESS_STATE,1'b0 - BLESS in DPSLP state" "0,1"
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line.long 0x4 "PWR_CTRL_SM_ST,Link Layer Power Control FSM Status Register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PWR_CTRL_SM_CURR_STATE,This register reflects the current state of the LL Power Control FSM"
|
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group.long 0xC0++0x7
|
|
line.long 0x0 "HVLDO_CTRL,HVLDO Configuration register"
|
|
rbitfld.long 0x0 31. "STATUS,hvldo LV detect status" "0,1"
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|
bitfld.long 0x0 6. "VREF_EXT_EN,Vref ext input enable." "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 1.--4. 1. "ADFT_CTRL,ADFT select"
|
|
bitfld.long 0x0 0. "ADFT_EN,ADFT enable" "0,1"
|
|
line.long 0x4 "MISC_EN_CTRL,Radio Buck and Active regulator enable control"
|
|
bitfld.long 0x4 4. "LPM_ENTRY_CTRL_MODE,Controls the LPM entry control mode" "0,1"
|
|
bitfld.long 0x4 3. "LPM_DRIFT_MULTI,Controls the LPM drift multi level compensation." "0,1"
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|
newline
|
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bitfld.long 0x4 2. "LPM_DRIFT_EN,Controls the LPM drift calculation." "0,1"
|
|
bitfld.long 0x4 1. "ACT_REG_EN_CTRL,Active regulator enable control. This must be programmed before enabling the Radio." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "BUCK_EN_CTRL,Buck enable control. This must be programmed before enabling the Radio." "0,1"
|
|
group.long 0xD0++0xF
|
|
line.long 0x0 "EFUSE_CONFIG,EFUSE mode configuration register"
|
|
bitfld.long 0x0 2. "EFUSE_WRITE,This bit when set by firmware enables the write to EFUSE macro. It is cleared when the efuse write is completed" "0,1"
|
|
bitfld.long 0x0 1. "EFUSE_READ,This bit when set by firmware enables the read from EFUSE macro. It is cleared when the efuse read is completed" "0,1"
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|
newline
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bitfld.long 0x0 0. "EFUSE_MODE,This register enables the efuse mode in m0s8bless_ver3" "0,1"
|
|
line.long 0x4 "EFUSE_TIM_CTRL1,EFUSE timing control register (common for Program and Read modes)"
|
|
hexmask.long.byte 0x4 28.--31. 1. "RW_CS_HOLD_TIME,This field decides hold time between RW & CS (THR_RW: in read mode) or RW & AVDD (THP_RW: in Program mode)."
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hexmask.long.byte 0x4 24.--27. 1. "RW_CS_SETUP_TIME,This field decides setup time between RW & CS (TSR_RW: in read mode) or RW & AVDD (TSP_RW: in Program mode)."
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newline
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hexmask.long.byte 0x4 20.--23. 1. "CS_SCLK_HOLD_TIME,This register specifies the hold time between CS and SCLK"
|
|
hexmask.long.byte 0x4 16.--19. 1. "CS_SCLK_SETUP_TIME,This register specifies the setup time between CS and SCLK (TSR_CLK)"
|
|
newline
|
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hexmask.long.byte 0x4 8.--15. 1. "SCLK_LOW,Duration of SCLK LOW (TCLKP_R) or TCKLP_P"
|
|
hexmask.long.byte 0x4 0.--7. 1. "SCLK_HIGH,Decides the duration of TPGM (in Program mode) or TCKHP (in Read mode)"
|
|
line.long 0x8 "EFUSE_TIM_CTRL2,EFUSE timing control Register (for Read)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "DOUT_CS_HOLD_TIME,Wait time"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DATA_SAMPLE_TIME,This register specifies the time for data sampling from SCLK HIGH"
|
|
line.long 0xC "EFUSE_TIM_CTRL3,EFUSE timing control Register (for Program)"
|
|
hexmask.long.byte 0xC 16.--23. 1. "AVDD_CS_HOLD_TIME,AVDD to CS hold time out of program mode (THP_AVDD_CS)"
|
|
hexmask.long.byte 0xC 8.--15. 1. "AVDD_CS_SETUP_TIME,AVDD to CS setup time into program mode (TSP_AVDD_CS)"
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "PGM_SCLK_HOLD_TIME,PGM to SCLK hold time (TH_PGM)"
|
|
hexmask.long.byte 0xC 0.--3. 1. "PGM_SCLK_SETUP_TIME,PGM to SCLK setup time (TS_PGM)"
|
|
rgroup.long 0xE0++0x7
|
|
line.long 0x0 "EFUSE_RDATA_L,EFUSE Lower read data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,This register has the read value from the Efuse macro fuse bits[31:0]"
|
|
line.long 0x4 "EFUSE_RDATA_H,EFUSE higher read data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,This register has the read value from the Efuse macro fuse bits[63:32]"
|
|
group.long 0xE8++0xB
|
|
line.long 0x0 "EFUSE_WDATA_L,EFUSE lower write word"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,This register has the write value to the Efuse macro fuse bits[31:0]"
|
|
line.long 0x4 "EFUSE_WDATA_H,EFUSE higher write word"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,This register has the write value to the Efuse macro fuse bits[63:32]"
|
|
line.long 0x8 "DIV_BY_625_CFG,Divide by 625 for FW Use"
|
|
hexmask.long.word 0x8 8.--23. 1. "DIVIDEND,This field holds the dividend"
|
|
bitfld.long 0x8 1. "ENABLE,This bit enables the divider for use by FW" "0,1"
|
|
rgroup.long 0xF4++0x3
|
|
line.long 0x0 "DIV_BY_625_STS,Output of divide by 625 divider"
|
|
hexmask.long.word 0x0 8.--17. 1. "REMAINDER,Remainder value from the divider. Available 1 cycle after dividend is programmed."
|
|
hexmask.long.byte 0x0 0.--5. 1. "QUOTIENT,Quotient value from the divider. Available 1 cycle after dividend is programmed."
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "PACKET_COUNTER0,Packet counter 0"
|
|
hexmask.long 0x0 0.--31. 1. "PACKET_COUNTER_LOWER,Lower 32-bits of the packet counter value passed as part of Nonce for the packet to be encrypted."
|
|
line.long 0x4 "PACKET_COUNTER2,Packet counter 2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PACKET_COUNTER_UPPER,Upper 8 bits of the packet counter value passed as part of Nonce for the packet to be encrypted."
|
|
line.long 0x8 "IV_MASTER0,Master Initialization Vector 0"
|
|
hexmask.long 0x8 0.--31. 1. "IV_MASTER,This is the IVm field which contains the master's portion of the initialization vector."
|
|
line.long 0xC "IV_SLAVE0,Slave Initialization Vector 0"
|
|
hexmask.long 0xC 0.--31. 1. "IV_SLAVE,This is the IVs field which contains the slave's portion of the initialization vector."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x110)++0x3
|
|
line.long 0x0 "ENC_KEY[$1],Encryption Key register 0-3"
|
|
hexmask.long 0x0 0.--31. 1. "ENC_KEY,The encryption key / session key which is used in ECB encryption CCM encryption and CCM decryption."
|
|
repeat.end
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "MIC_IN0,MIC input register"
|
|
hexmask.long 0x0 0.--31. 1. "MIC_IN,This is the MIC field used for CCM decryption."
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "MIC_OUT0,MIC output register"
|
|
hexmask.long 0x0 0.--31. 1. "MIC_OUT,This is the MIC generated during CCM encryption."
|
|
group.long 0x128++0xF
|
|
line.long 0x0 "ENC_PARAMS,Encryption Parameter register"
|
|
bitfld.long 0x0 11. "MEM_LATENCY_HIDE,Controls the encryption memory access mode. Valid only when DLE is enabled." "0,1"
|
|
bitfld.long 0x0 8.--10. "PAYLOAD_LENGTH_LSB_EXT,3 Most significant bits of the LS byte of the length of the input data. Valid only when DLE is enabled." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 7. "DIRECTION,The directionBit shall be set to '1' for Data Channel PDUs sent by the master and set to '0' for Data Channel PDUs sent by the slave." "0,1"
|
|
hexmask.long.byte 0x0 2.--6. 1. "PAYLOAD_LENGTH_LSB,Length of the input data."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "DATA_PDU_HEADER,LLID of the packet." "0,1,2,3"
|
|
line.long 0x4 "ENC_CONFIG,Encryption Configuration"
|
|
bitfld.long 0x4 24. "AES_B0_DATA_OVERRIDE,Configuration to use B0 DATA provided by FW for CCM computation" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "B0_FLAGS,LS byte of the input data when B0 needs to be completely configurable. Valid only when AES_B0_DATA_OVERRIDE is enabled."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "PAYLOAD_LENGTH_MSB,MS byte of the length of the input data when B0 needs to be completely configurable. Valid only when AES_B0_DATA_OVERRIDE is enabled."
|
|
bitfld.long 0x4 2. "DEC_ENC,Decryption/Encryption" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ECB_CCM,0 - CCM" "0,1"
|
|
bitfld.long 0x4 0. "START_PROC,1 Start the AES processing" "0,1"
|
|
line.long 0x8 "ENC_INTR_EN,Encryption Interrupt enable"
|
|
bitfld.long 0x8 2. "CCM_PROC_INTR_EN,CCM processed interupt enable" "0,1"
|
|
bitfld.long 0x8 1. "ECB_PROC_INTR_EN,ECB processed interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "AUTH_PASS_INTR_EN,Authentication interrupt enable" "0,1"
|
|
line.long 0xC "ENC_INTR,Encryption Interrupt status and clear register"
|
|
bitfld.long 0xC 3. "IN_DATA_CLEAR,Clears the input data. Used for Zero padding of encryption for less than block sized data." "0,1"
|
|
bitfld.long 0xC 2. "CCM_PROC_INTR,CCM processed interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "ECB_PROC_INTR,ECB processed interrupt." "0,1"
|
|
bitfld.long 0xC 0. "AUTH_PASS_INTR,Authentication interrupt." "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x140)++0x3
|
|
line.long 0x0 "B1_DATA_REG[$1],Programmable B1 Data register (0-3)"
|
|
hexmask.long 0x0 0.--31. 1. "B1_DATA,Programmable B1 Data register"
|
|
repeat.end
|
|
group.long 0x150++0x3
|
|
line.long 0x0 "ENC_MEM_BASE_ADDR,Encryption memory base address"
|
|
hexmask.long 0x0 0.--31. 1. "ENC_MEM,Data values written to Enc memory are written as 16-bit wide data. This memory is valid only if DLE is set."
|
|
group.long 0xF00++0xF
|
|
line.long 0x0 "TRIM_LDO_0,LDO Trim register 0"
|
|
hexmask.long.byte 0x0 4.--7. 1. "ACT_LDO_ITAIL,To trim the bias currents for all the active mode blocks"
|
|
hexmask.long.byte 0x0 0.--3. 1. "ACT_LDO_VREG,To trim the regulated voltage in steps of 25mV typically"
|
|
line.long 0x4 "TRIM_LDO_1,LDO Trim register 1"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SB_BGRES,To trim standby regulator reference voltage"
|
|
hexmask.long.byte 0x4 0.--3. 1. "ACT_REF_BGR,To trim active regulator reference voltage"
|
|
line.long 0x8 "TRIM_LDO_2,LDO Trim register 2"
|
|
bitfld.long 0x8 5.--6. "SB_BMULT_NBIAS,To trim standby regulator beta-multiplier current" "0,1,2,3"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SB_BMULT_RES,To trim standby regulator beta-multiplier current"
|
|
line.long 0xC "TRIM_LDO_3,LDO Trim register 3"
|
|
bitfld.long 0xC 5.--6. "SLOPE_SB_BMULT,To trim standby regulator beta-multiplier temp-co slope" "0,1,2,3"
|
|
hexmask.long.byte 0xC 0.--4. 1. "LVDET,To trim the trip points of the LV-Detect block"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xF10)++0x3
|
|
line.long 0x0 "TRIM_MXD[$1],MXD die Trim registers"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MXD_TRIM_BITS,MXD trim bits"
|
|
repeat.end
|
|
group.long 0xF30++0x7
|
|
line.long 0x0 "TRIM_LDO_4,LDO Trim register 4"
|
|
hexmask.long.byte 0x0 0.--7. 1. "T_LDO,To debug post layout or post silicon"
|
|
line.long 0x4 "TRIM_LDO_5,LDO Trim register 5"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RSVD,N/A"
|
|
tree.end
|
|
base ad:0x403C0000
|
|
tree "RCB (Radio Control Bus (RCB) controller)"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,RCB control register."
|
|
bitfld.long 0x0 31. "ENABLED,N/A" "0,1"
|
|
bitfld.long 0x0 23. "DATA_WIDTH,N/A" "0,1"
|
|
hexmask.long.byte 0x0 19.--22. 1. "ADDR_WIDTH,N/A"
|
|
hexmask.long.byte 0x0 13.--18. 1. "DIV,N/A"
|
|
bitfld.long 0x0 12. "DIV_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "LAG,N/A" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "LEAD,N/A" "0,1,2,3"
|
|
bitfld.long 0x0 5. "SSEL_POLARITY,N/A" "0,1"
|
|
bitfld.long 0x0 4. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
bitfld.long 0x0 3. "RX_CLK_SRC,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RX_CLK_EDGE,N/A" "0,1"
|
|
bitfld.long 0x0 1. "TX_CLK_EDGE,N/A" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,RCB status register."
|
|
bitfld.long 0x0 0. "BUS_BUSY,RCB bus is busy. The bus is considered busy ('1') during an ongoing transaction." "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "TX_CTRL,Transmitter control register."
|
|
hexmask.long.byte 0x0 2.--6. 1. "TX_ENTRIES,This field determines the depth of the TX_FIFO. Allowed legal values are 8 and 16 only"
|
|
bitfld.long 0x0 1. "FIFO_RECONFIG,Setting this bit clears the FIFO and resets the pointer" "0,1"
|
|
bitfld.long 0x0 0. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')." "0,1"
|
|
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control register."
|
|
bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "TX_TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event is generated."
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status register."
|
|
hexmask.long.byte 0x0 24.--27. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
|
|
hexmask.long.byte 0x0 16.--19. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
|
|
bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED,Amount of enties in the transmitter FIFO. The value of this field ranges from 0 to 16"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write register."
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation."
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "RX_CTRL,Receiver control register."
|
|
bitfld.long 0x0 0. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')." "0,1"
|
|
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control register."
|
|
bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event is generated."
|
|
rgroup.long 0x28++0xB
|
|
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status register."
|
|
hexmask.long.byte 0x0 24.--27. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
|
|
hexmask.long.byte 0x0 16.--19. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
|
|
bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED,Amount of enties in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR."
|
|
line.long 0x4 "RX_FIFO_RD,Receiver FIFO read register."
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "RX_FIFO_RD_SILENT,Receiver FIFO read register."
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation."
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "INTR,Master interrupt request register."
|
|
bitfld.long 0x0 20. "RX_FIFO_UNDERFLOW,N/A" "0,1"
|
|
bitfld.long 0x0 19. "RX_FIFO_OVERFLOW,N/A" "0,1"
|
|
bitfld.long 0x0 18. "RX_FIFO_FULL,N/A" "0,1"
|
|
bitfld.long 0x0 17. "RX_FIFO_NOT_EMPTY,N/A" "0,1"
|
|
bitfld.long 0x0 16. "RX_FIFO_TRIGGER,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TX_FIFO_UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
bitfld.long 0x0 11. "TX_FIFO_OVERFLOW,N/A" "0,1"
|
|
bitfld.long 0x0 10. "TX_FIFO_EMPTY,N/A" "0,1"
|
|
bitfld.long 0x0 9. "TX_FIFO_NOT_FULL,N/A" "0,1"
|
|
bitfld.long 0x0 8. "TX_FIFO_TRIGGER,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RCB_DONE,N/A" "0,1"
|
|
line.long 0x4 "INTR_SET,Master interrupt set request register"
|
|
bitfld.long 0x4 20. "RX_FIFO_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 19. "RX_FIFO_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 18. "RX_FIFO_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 17. "RX_FIFO_NOT_EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 16. "RX_FIFO_TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "TX_FIFO_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 11. "TX_FIFO_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 10. "TX_FIFO_EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 9. "TX_FIFO_NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 8. "TX_FIFO_TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RCB_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Master interrupt mask register."
|
|
bitfld.long 0x8 20. "RX_FIFO_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 19. "RX_FIFO_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 18. "RX_FIFO_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 17. "RX_FIFO_NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 16. "RX_FIFO_TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "TX_FIFO_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 11. "TX_FIFO_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 10. "TX_FIFO_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 9. "TX_FIFO_NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 8. "TX_FIFO_TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RCB_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "INTR_MASKED,Master interrupt masked request register"
|
|
bitfld.long 0x0 20. "RX_FIFO_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 19. "RX_FIFO_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 18. "RX_FIFO_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 17. "RX_FIFO_NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 16. "RX_FIFO_TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TX_FIFO_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 11. "TX_FIFO_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 10. "TX_FIFO_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 9. "TX_FIFO_NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 8. "TX_FIFO_TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RCB_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
tree "RCBLL (Radio Control Bus (RCB) & Link Layer controller)"
|
|
base ad:0x403C0100
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,RCB LL control register."
|
|
bitfld.long 0x0 5. "ENABLE_RADIO_BOD,N/A" "0,1"
|
|
bitfld.long 0x0 4. "ALLOW_CPU_ACCESS_TX_RX,N/A" "0,1"
|
|
bitfld.long 0x0 3. "CPU_SINGLE_READ,N/A" "0,1"
|
|
bitfld.long 0x0 2. "CPU_SINGLE_WRITE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCBLL_CPU_REQ,N/A" "0,1"
|
|
bitfld.long 0x0 0. "RCBLL_CTRL,N/A" "0,1"
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "INTR,Master interrupt request register."
|
|
bitfld.long 0x0 3. "SINGLE_READ_DONE,N/A" "0,1"
|
|
bitfld.long 0x0 2. "SINGLE_WRITE_DONE,N/A" "0,1"
|
|
bitfld.long 0x0 0. "RCB_LL_DONE,RCB_LL is done and the access is given back to CPU" "0,1"
|
|
line.long 0x4 "INTR_SET,Master interrupt set request register"
|
|
bitfld.long 0x4 3. "SINGLE_READ_DONE,N/A" "0,1"
|
|
bitfld.long 0x4 2. "SINGLE_WRITE_DONE,N/A" "0,1"
|
|
bitfld.long 0x4 0. "RCB_LL_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Master interrupt mask register."
|
|
bitfld.long 0x8 3. "SINGLE_READ_DONE,N/A" "0,1"
|
|
bitfld.long 0x8 2. "SINGLE_WRITE_DONE,N/A" "0,1"
|
|
bitfld.long 0x8 0. "RCB_LL_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "INTR_MASKED,Master interrupt masked request register"
|
|
bitfld.long 0x0 3. "SINGLE_READ_DONE,N/A" "0,1"
|
|
bitfld.long 0x0 2. "SINGLE_WRITE_DONE,N/A" "0,1"
|
|
bitfld.long 0x0 0. "RCB_LL_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0x20++0x13
|
|
line.long 0x0 "RADIO_REG1_ADDR,Address of Register#1 in Radio (MDON)"
|
|
hexmask.long.word 0x0 0.--15. 1. "REG_ADDR,N/A"
|
|
line.long 0x4 "RADIO_REG2_ADDR,Address of Register#2 in Radio (RSSI)"
|
|
hexmask.long.word 0x4 0.--15. 1. "REG_ADDR,N/A"
|
|
line.long 0x8 "RADIO_REG3_ADDR,Address of Register#3 in Radio (ACCL)"
|
|
hexmask.long.word 0x8 0.--15. 1. "REG_ADDR,N/A"
|
|
line.long 0xC "RADIO_REG4_ADDR,Address of Register#4 in Radio (ACCH)"
|
|
hexmask.long.word 0xC 0.--15. 1. "REG_ADDR,N/A"
|
|
line.long 0x10 "RADIO_REG5_ADDR,Address of Register#5 in Radio (RSSI ENERGY)"
|
|
hexmask.long.word 0x10 0.--15. 1. "REG_ADDR,N/A"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "CPU_WRITE_REG,N/A"
|
|
hexmask.long.word 0x0 16.--31. 1. "WRITE_DATA,N/A"
|
|
hexmask.long.word 0x0 0.--15. 1. "ADDR,N/A"
|
|
line.long 0x4 "CPU_READ_REG,N/A"
|
|
hexmask.long.word 0x4 16.--31. 1. "READ_DATA,N/A"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADDR,N/A"
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYS06??4*")||cpuis("CYS06??5*"))
|
|
tree "CANFD (CAN Controller)"
|
|
base ad:0x40520000
|
|
tree "CH (FIFO wrapper around M_TTCAN 3PIP to enable DMA)"
|
|
tree "M_TTCAN (TTCAN 3PIP includes FD)"
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "CREL,Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day"
|
|
line.long 0x4 "ENDN,Endian Register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "DBTP,Data Bit Timing & Prescaler Register"
|
|
bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
|
|
newline
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hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
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|
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hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width"
|
|
line.long 0x4 "TEST,Test Register"
|
|
rbitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant,1: The CAN bus is recessive"
|
|
bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
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|
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bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0: Reset value,1: Loop Back Mode is enabled"
|
|
bitfld.long 0x4 3. "CAT,ASC is not supported by M_TTCAN" "0: Output pin m_ttcan_asct = '0',?"
|
|
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|
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bitfld.long 0x4 2. "CAM,ASC is not supported by M_TTCAN" "0: Output pin m_ttcan_ascm = '0',1: Output pin m_ttcan_ascm = '1'"
|
|
bitfld.long 0x4 1. "TAT,ASC is not supported by M_TTCAN" "0: Level at pin m_ttcan_asct controlled by FSE,1: Level at pin m_ttcan_asct = '1'"
|
|
newline
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bitfld.long 0x4 0. "TAM,ASC is not supported by M_TTCAN" "0: Level at pin m_ttcan_ascm controlled by FSE,1: Level at pin m_ttcan_ascm = '1'"
|
|
line.long 0x8 "RWD,RAM Watchdog"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration"
|
|
line.long 0xC "CCCR,CC Control Register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled"
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|
newline
|
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bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
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bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
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bitfld.long 0xC 7. "TEST,Test Mode Enable" "0: Normal operation,1: Test Mode"
|
|
bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
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|
newline
|
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bitfld.long 0xC 5. "MON_,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock Stop Request not supported by M_TTCAN use CTL.STOP_REQ at the group level instead." "0: No clock stop is requested,1: Clock stop requested"
|
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newline
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bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_TTCAN may be set in power down by stopping.."
|
|
bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active"
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newline
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bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
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|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started"
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line.long 0x10 "NBTP,Nominal Bit Timing & Prescaler Register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width"
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hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
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|
newline
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hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
|
|
line.long 0x14 "TSCC,Timestamp Counter Configuration"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler (still used for TOCC)"
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|
bitfld.long 0x14 0.--1. "TSS,Timestamp Select should always be set to external timestamp counter" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,?,?"
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|
line.long 0x18 "TSCV,Timestamp Counter Value"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter not used for M_TTCAN"
|
|
line.long 0x1C "TOCC,Timeout Counter Configuration"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period"
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bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,?,?"
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newline
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bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled"
|
|
line.long 0x20 "TOCV,Timeout Counter Value"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ECR,Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
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|
newline
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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|
newline
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bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0: Since this bit was reset by the CPU,1: Message in CAN FD format with FDF flag set has.."
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|
bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set"
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newline
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bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set"
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bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state"
|
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bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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newline
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bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state,1: The M_CAN is in the Error_Passive state"
|
|
bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing,1: Idle,?,?"
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newline
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bitfld.long 0x4 0.--2. "LEC,Last Error Code " "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the M_TTCAN..,4: Bit1Error: During the transmission of a message,5: Bit0Error: During the transmission of a message,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.."
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group.long 0x48++0x3
|
|
line.long 0x0 "TDCR,Transmitter Delay Compensation Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "IR,Interrupt Register"
|
|
bitfld.long 0x0 29. "ARA,N/A" "0,1"
|
|
bitfld.long 0x0 28. "PED,N/A" "0,1"
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|
newline
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bitfld.long 0x0 27. "PEA,N/A" "0,1"
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|
bitfld.long 0x0 26. "WDI,N/A" "0,1"
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newline
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bitfld.long 0x0 25. "BO_,N/A" "0,1"
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|
bitfld.long 0x0 24. "EW_,N/A" "0,1"
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newline
|
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bitfld.long 0x0 23. "EP_,N/A" "0,1"
|
|
bitfld.long 0x0 22. "ELO,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected"
|
|
bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "DRX,N/A" "0,1"
|
|
bitfld.long 0x0 18. "TOO,N/A" "0,1"
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|
newline
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bitfld.long 0x0 17. "MRAF,N/A" "0,1"
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|
bitfld.long 0x0 16. "TSW,N/A" "0,1"
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newline
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bitfld.long 0x0 15. "TEFL_,N/A" "0,1"
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|
bitfld.long 0x0 14. "TEFF,N/A" "0,1"
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newline
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bitfld.long 0x0 13. "TEFW,N/A" "0,1"
|
|
bitfld.long 0x0 12. "TEFN,N/A" "0,1"
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|
newline
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bitfld.long 0x0 11. "TFE,N/A" "0,1"
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|
bitfld.long 0x0 10. "TCF,N/A" "0,1"
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newline
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bitfld.long 0x0 9. "TC,N/A" "0,1"
|
|
bitfld.long 0x0 8. "HPM,N/A" "0,1"
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newline
|
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bitfld.long 0x0 7. "RF1L_,N/A" "0,1"
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|
bitfld.long 0x0 6. "RF1F,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 5. "RF1W,N/A" "0,1"
|
|
bitfld.long 0x0 4. "RF1N,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RF0L_,N/A" "0,1"
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|
bitfld.long 0x0 2. "RF0F,N/A" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "RF0W,N/A" "0,1"
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bitfld.long 0x0 0. "RF0N,N/A" "0,1"
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line.long 0x4 "IE,Interrupt Enable"
|
|
bitfld.long 0x4 29. "ARAE,N/A" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
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bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable (not used in M_TTCAN)" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
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bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
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bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
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bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
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bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIDO New Entry Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt Disabled,1: Interrupt EnabledTx FIFO Empty Interrupt Enable"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
line.long 0x8 "ILS,Interrupt Line Select"
|
|
bitfld.long 0x8 29. "ARAL,N/A" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
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bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 23. "EPL,Error Passive Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Select (not used in M_TTCAN)" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
line.long 0xC "ILE,Interrupt Line Enable"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line m_ttcan_int1 disabled,1: Interrupt line m_ttcan_int1 enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line m_ttcan_int0 disabled,1: Interrupt line m_ttcan_int0 enabled"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "GFC,Global Filter Configuration"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs"
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "XIDAM,Extended ID AND Mask"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "HPMS,High Priority Message Status"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,?,?"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x98++0xB
|
|
line.long 0x0 "NDAT1,New Data 1"
|
|
hexmask.long 0x0 0.--31. 1. "ND,New Data"
|
|
line.long 0x4 "NDAT2,New Data 2"
|
|
hexmask.long 0x4 0.--31. 1. "ND,New Data"
|
|
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "RXF0S,Rx FIFO 0 Status"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
|
|
group.long 0xA8++0xB
|
|
line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Rx Buffer Configuration"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Rx FIFO 1 Configuration"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address"
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state,1: Debug message A received,?,?"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level"
|
|
group.long 0xB8++0xB
|
|
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration"
|
|
bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
|
|
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
|
|
line.long 0x8 "TXBC,Tx Buffer Configuration"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "TXFQS,Tx FIFO/Queue Status"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "TXESC,Tx Buffer Element Size Configuration"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "TXBRP,Tx Buffer Request Pending"
|
|
hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "TXBAR,Tx Buffer Add Request"
|
|
hexmask.long 0x0 0.--31. 1. "AR,Add Request"
|
|
line.long 0x4 "TXBCR,Tx Buffer Cancellation Request"
|
|
hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request"
|
|
rgroup.long 0xD8++0x7
|
|
line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred"
|
|
hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred"
|
|
line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished"
|
|
hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
|
|
hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable"
|
|
line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
|
|
hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long 0xF4++0x3
|
|
line.long 0x0 "TXEFS,Tx Event FIFO Status"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
group.long 0x100++0x2B
|
|
line.long 0x0 "TTTMC,TT Trigger Memory Configuration"
|
|
hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements"
|
|
hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start Address"
|
|
line.long 0x4 "TTRMC,TT Reference Message Configuration"
|
|
bitfld.long 0x4 31. "RMPS,Reference Message Payload Select" "0: Message Marker MM,1: bytes 2-8"
|
|
bitfld.long 0x4 30. "XTD,Extended Identifier" "0: 11-bit standard identifier,1: 29-bit extended identifier"
|
|
newline
|
|
hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier"
|
|
line.long 0x8 "TTOCF,TT Operation Configuration"
|
|
bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0: Rising edge trigger,1: Falling edge trigger"
|
|
bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0: Automatic clock calibration in TTCAN Level 0,1: Automatic clock calibration in TTCAN Level 0"
|
|
newline
|
|
bitfld.long 0x8 24. "EGTF,Enable Global Time Filtering" "0: Global time filtering in TTCAN Level 0,1: Global time filtering in TTCAN Level 0"
|
|
hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit"
|
|
newline
|
|
bitfld.long 0x8 15. "EECS,Enable External Clock Synchronization" "0: External clock synchronization in TTCAN Level 0,1: External clock synchronization in TTCAN Level 0"
|
|
hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger Offset"
|
|
newline
|
|
bitfld.long 0x8 5.--7. "LDSDL,LD of Synchronization Deviation Limit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 4. "TM,Time Master" "0: Time Master function disabled,1: Potential Time Master"
|
|
newline
|
|
bitfld.long 0x8 3. "GEN,Gap Enable" "0: Strictly time-triggered operation,1: External event-synchronized time-triggered.."
|
|
bitfld.long 0x8 0.--1. "OM,Operation Mode" "0: Event-driven CAN communication,1: TTCAN level 1,?,?"
|
|
line.long 0xC "TTMLM,TT Matrix Limits"
|
|
hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx Triggers"
|
|
hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "CSS,N/A" "0,1,2,3"
|
|
hexmask.long.byte 0xC 0.--5. 1. "CCM,N/A"
|
|
line.long 0x10 "TURCF,TUR Configuration"
|
|
bitfld.long 0x10 31. "ELT,Enable Local Time" "0: Local time is stopped,1: Local time is enabled"
|
|
hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration Low"
|
|
line.long 0x14 "TTOCN,TT Operation Control"
|
|
rbitfld.long 0x14 15. "LCKC,TT Operation Control Register Locked" "0: Write access to TTOCN enabled,1: Write access to TTOCN locked"
|
|
bitfld.long 0x14 13. "ESCN,External Synchronization Control" "0: External synchronization disabled,1: External synchronization enabled"
|
|
newline
|
|
bitfld.long 0x14 12. "NIG,Next is Gap" "0: No action,1: Transmit next reference message with Next_is_Gap.."
|
|
bitfld.long 0x14 11. "TMG,Time Mark Gap" "0: Reset by each reference message,1: Next reference message started when Register.."
|
|
newline
|
|
bitfld.long 0x14 10. "FGP,Finish Gap" "0: No reference message requested,1: Application requested start of reference message"
|
|
bitfld.long 0x14 9. "GCS,Gap Control Select" "0: Gap control independent from m_ttcan_evt,1: Gap control by input pin m_ttcan_evt"
|
|
newline
|
|
bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse Enable" "0: Trigger Time Mark Interrupt output m_ttcan_tmp..,1: Trigger Time Mark Interrupt output m_ttcan_tmp.."
|
|
bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0: No Register Time Mark Interrupt generated,1: Register Time Mark Interrupt if Time Mark =..,?,?"
|
|
newline
|
|
bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse Enable" "0: Register Time Mark Interrupt output m_ttcan_rtp..,1: Register Time Mark Interrupt output m_ttcan_rtp.."
|
|
bitfld.long 0x14 3.--4. "SWS,Stop Watch Source" "0: Stop Watch disabled,1: Actual value of cycle time is copied to TTCPT,?,?"
|
|
newline
|
|
bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0: Rising edge trigger,1: Falling edge trigger"
|
|
bitfld.long 0x14 1. "ECS,External Clock Synchronization" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "SGT,Set Global time" "0,1"
|
|
line.long 0x18 "TTGTP,TT Global Time Preset"
|
|
hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase"
|
|
hexmask.long.word 0x18 0.--15. 1. "TP,N/A"
|
|
line.long 0x1C "TTTMK,TT Time Mark"
|
|
rbitfld.long 0x1C 31. "LCKM,TT Time Mark Register Locked" "0: Write access to TTTMK enabled,1: Write access to TTTMK locked"
|
|
hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "TM_,Time Mark"
|
|
line.long 0x20 "TTIR,TT Interrupt Register"
|
|
bitfld.long 0x20 18. "CER,Configuration Error" "0: No error found in trigger list,1: Error found in trigger list"
|
|
bitfld.long 0x20 17. "AW,Application Watchdog" "0: Application watchdog served in time,1: Application watchdog not served in time"
|
|
newline
|
|
bitfld.long 0x20 16. "WT,Watch Trigger" "0: cycle time 0xFF00,1: Missing reference message"
|
|
bitfld.long 0x20 15. "IWT,Initialization Watch Trigger" "0: No missing reference message during system startup,1: No system startup due to missing reference message"
|
|
newline
|
|
bitfld.long 0x20 14. "ELC,Error Level Changed" "0: No change in error level,1: Error level changed"
|
|
bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0: No scheduling error 2,1: Scheduling error 2 occurred"
|
|
newline
|
|
bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0: No scheduling error 1,1: Scheduling error 1 occurred"
|
|
bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0: Number of Tx Trigger as expected,1: More Tx trigger than expected in one matrix cycle"
|
|
newline
|
|
bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0: Number of Tx Trigger as expected,1: Less Tx trigger than expected in one matrix cycle"
|
|
bitfld.long 0x20 9. "GTE,Global Time Error" "0: Synchronization deviation within limit,1: Synchronization deviation exceeded limit"
|
|
newline
|
|
bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0: No discontinuity of global time,1: Discontinuity of global time"
|
|
bitfld.long 0x20 7. "GTW,Global Time Wrap" "0: No global time wrap occurred,1: Global time wrap from 0xFFFF to 0x0000 occurred"
|
|
newline
|
|
bitfld.long 0x20 6. "SWE,Stop Watch Event" "0: No rising/falling edge at stop watch trigger pin..,1: Rising/falling edge at stop watch trigger pin.."
|
|
bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event Internal" "0: cycle time TTOCF,1: Time mark reached"
|
|
newline
|
|
bitfld.long 0x20 4. "RTMI,Register Time Mark Interrupt" "0: Time mark not reached,1: Time mark reached"
|
|
bitfld.long 0x20 3. "SOG,Start of Gap" "0: No reference message seen with Next_is_Gap bit set,1: Reference message with Next_is_Gap bit set.."
|
|
newline
|
|
bitfld.long 0x20 2. "CSM_,Change of Synchronization Mode" "0: No change in master to slave relation or..,1: Master to slave relation or schedule.."
|
|
bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0: No Matrix Cycle started since bit has been reset,1: Matrix Cycle started"
|
|
newline
|
|
bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0: No Basic Cycle started since bit has been reset,1: Basic Cycle started"
|
|
line.long 0x24 "TTIE,TT Interrupt Enable"
|
|
bitfld.long 0x24 18. "CERE,Configuration Error Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 17. "AWE_,Application Watchdog Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 15. "IWTE,Initialization Watch Trigger Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
line.long 0x28 "TTILS,TT Interrupt Line Select"
|
|
bitfld.long 0x28 18. "CERL,Configuration Error Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 17. "AWL_,Application Watchdog Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 15. "IWTL,Initialization Watch Trigger Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
rgroup.long 0x12C++0x17
|
|
line.long 0x0 "TTOST,TT Operation Status"
|
|
bitfld.long 0x0 31. "SPL,Schedule Phase Lock" "0: Phase outside range,1: Phase inside range"
|
|
bitfld.long 0x0 30. "WECS,Wait for External Clock Synchronization" "0: No external clock synchronization pending,1: Node waits for external clock synchronization to.."
|
|
newline
|
|
bitfld.long 0x0 29. "AWE,Application Watchdog Event" "0: Application Watchdog served in time,1: Failed to serve Application Watchdog in time"
|
|
bitfld.long 0x0 28. "WFE,Wait for Event" "0: No Gap announced,1: Reference message with Next_is_Gap = '1' received"
|
|
newline
|
|
bitfld.long 0x0 27. "GSI,Gap Started Indicator" "0: No Gap in schedule,1: Gap time after Basic Cycle has started"
|
|
bitfld.long 0x0 24.--26. "TMP,Time Master Priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "GFI,Gap Finished Indicator" "0: Reset at the end of each reference message,1: Gap finished by M_TTCAN"
|
|
bitfld.long 0x0 22. "WGTD,Wait for Global Time Discontinuity" "0: No global time preset pending,1: Node waits for the global time preset to take.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference Trigger Offset"
|
|
bitfld.long 0x0 7. "QCS,Quality of Clock Speed" "0: Local clock speed not synchronized to Time..,1: Synchronization Deviation <= SDL"
|
|
newline
|
|
bitfld.long 0x0 6. "QGTP,Quality of Global Time Phase" "0: Global time not valid,1: Global time in phase with Time Master"
|
|
bitfld.long 0x0 4.--5. "SYS,Synchronization State" "0: Out of Synchronization,1: Synchronizing to TTCAN communication,?,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MS,Master State" "0: Master_Off,1: Operating as Time Slave,?,?"
|
|
bitfld.long 0x0 0.--1. "EL,Error Level" "0: Severity 0,1: Severity 1,?,?"
|
|
line.long 0x4 "TURNA,TUR Numerator Actual"
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "NAV,N/A"
|
|
line.long 0x8 "TTLGT,TT Local & Global Time"
|
|
hexmask.long.word 0x8 16.--31. 1. "GT,Global Time"
|
|
hexmask.long.word 0x8 0.--15. 1. "LT,Local Time"
|
|
line.long 0xC "TTCTC,TT Cycle Time & Count"
|
|
hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle Count"
|
|
hexmask.long.word 0xC 0.--15. 1. "CT,Cycle Time"
|
|
line.long 0x10 "TTCPT,TT Capture Time"
|
|
hexmask.long.word 0x10 16.--31. 1. "SWV,Stop Watch Value"
|
|
hexmask.long.byte 0x10 0.--5. 1. "CCV,Cycle Count Value"
|
|
line.long 0x14 "TTCSM,TT Cycle Sync Mark"
|
|
hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle Sync Mark"
|
|
tree.end
|
|
newline
|
|
group.long 0x180++0x3
|
|
newline
|
|
line.long 0x0 "RXFTOP_CTL,Receive FIFO Top control"
|
|
bitfld.long 0x0 1. "F1TPE,FIFO 1 Top Pointer Enable." "0,1"
|
|
bitfld.long 0x0 0. "F0TPE,FIFO 0 Top Pointer Enable." "0,1"
|
|
rgroup.long 0x1A0++0x3
|
|
line.long 0x0 "RXFTOP0_STAT,Receive FIFO 0 Top Status"
|
|
hexmask.long.word 0x0 0.--15. 1. "F0TA,Current FIFO 0 Top Address."
|
|
rgroup.long 0x1A8++0x3
|
|
line.long 0x0 "RXFTOP0_DATA,Receive FIFO 0 Top Data"
|
|
hexmask.long 0x0 0.--31. 1. "F0TD,When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met:"
|
|
rgroup.long 0x1B0++0x3
|
|
line.long 0x0 "RXFTOP1_STAT,Receive FIFO 1 Top Status"
|
|
hexmask.long.word 0x0 0.--15. 1. "F1TA,See F0TA description"
|
|
rgroup.long 0x1B8++0x3
|
|
line.long 0x0 "RXFTOP1_DATA,Receive FIFO 1 Top Data"
|
|
hexmask.long 0x0 0.--31. 1. "F1TD,See F0TD description"
|
|
tree.end
|
|
newline
|
|
group.long 0x1000++0x3
|
|
newline
|
|
line.long 0x0 "CTL,Global CAN control register"
|
|
bitfld.long 0x0 31. "MRAM_OFF,MRAM off" "0: Default MRAM on,1: Switch MRAM off"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STOP_REQ,N/A"
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "STATUS,Global CAN status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STOP_ACK,Clock Stop Acknowledge for each TTCAN IP."
|
|
rgroup.long 0x1010++0x7
|
|
line.long 0x0 "INTR0_CAUSE,Consolidated interrupt0 cause register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT0,Show pending m_ttcan_int0 of each channel"
|
|
line.long 0x4 "INTR1_CAUSE,Consolidated interrupt1 cause register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "INT1,Show pending m_ttcan_int1 of each channel"
|
|
group.long 0x1020++0x7
|
|
line.long 0x0 "TS_CTL,Time Stamp control register"
|
|
bitfld.long 0x0 31. "ENABLED,Counter enable bit" "0: Count disabled,1: Count enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. "PRESCALE,Time Stamp counter prescale value."
|
|
line.long 0x4 "TS_CNT,Time Stamp counter value"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALUE,The counter value of the Time Stamp Counter."
|
|
group.long 0x1080++0x7
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC for CANFD SRAM" "0,1"
|
|
line.long 0x4 "ECC_ERR_INJ,ECC error injection"
|
|
hexmask.long.byte 0x4 24.--30. 1. "ERR_PAR,ECC Parity bits to use for ECC error injection at address ERR_ADDR."
|
|
bitfld.long 0x4 20. "ERR_EN,Enable error injection (ECC_EN must be 1)." "0,1"
|
|
hexmask.long.word 0x4 2.--15. 1. "ERR_ADDR,Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x40210000
|
|
elif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
base ad:0x40200000
|
|
endif
|
|
tree "CPUSS (CPU Subsystem)"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CM0_CTL,CM0+ control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 1. "ENABLED,Processor enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "SLV_STALL,Processor debug access control:" "0: Access,1: Stall access"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "CM0_STATUS,CM0+ status"
|
|
bitfld.long 0x0 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field." "0,1"
|
|
bitfld.long 0x0 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode:" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CM0_CLOCK_CTL,CM0+ clock control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PERI_INT_DIV,Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1 256] (PERI_INT_DIV is in the range [0 .."
|
|
hexmask.long.byte 0x0 8.--15. 1. "SLOW_INT_DIV,Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1 256] (SLOW_INT_DIV is in the range [0 255])."
|
|
group.long 0x20++0x1F
|
|
line.long 0x0 "CM0_INT_CTL0,CM0+ interrupt control 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "MUX3_SEL,System interrupt select for CPU interrupt source 3."
|
|
hexmask.long.byte 0x0 16.--23. 1. "MUX2_SEL,System interrupt select for CPU interrupt source 2."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MUX1_SEL,System interrupt select for CPU interrupt source 1."
|
|
hexmask.long.byte 0x0 0.--7. 1. "MUX0_SEL,System interrupt select for CPU interrupt source 0. If the field value is 240 no system interrupt is connected and the CPU interrupt source is always '0'/de-activated."
|
|
line.long 0x4 "CM0_INT_CTL1,CM0+ interrupt control 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "MUX3_SEL,System interrupt select for CPU interrupt source 7."
|
|
hexmask.long.byte 0x4 16.--23. 1. "MUX2_SEL,System interrupt select for CPU interrupt source 6."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "MUX1_SEL,System interrupt select for CPU interrupt source 5."
|
|
hexmask.long.byte 0x4 0.--7. 1. "MUX0_SEL,System interrupt select for CPU interrupt source 4."
|
|
line.long 0x8 "CM0_INT_CTL2,CM0+ interrupt control 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. "MUX3_SEL,System interrupt select for CPU interrupt source 11."
|
|
hexmask.long.byte 0x8 16.--23. 1. "MUX2_SEL,System interrupt select for CPU interrupt source 10."
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "MUX1_SEL,System interrupt select for CPU interrupt source 9."
|
|
hexmask.long.byte 0x8 0.--7. 1. "MUX0_SEL,System interrupt select for CPU interrupt source 8."
|
|
line.long 0xC "CM0_INT_CTL3,CM0+ interrupt control 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. "MUX3_SEL,System interrupt select for CPU interrupt source 15."
|
|
hexmask.long.byte 0xC 16.--23. 1. "MUX2_SEL,System interrupt select for CPU interrupt source 14."
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "MUX1_SEL,System interrupt select for CPU interrupt source 13."
|
|
hexmask.long.byte 0xC 0.--7. 1. "MUX0_SEL,System interrupt select for CPU interrupt source 12."
|
|
line.long 0x10 "CM0_INT_CTL4,CM0+ interrupt control 4"
|
|
hexmask.long.byte 0x10 24.--31. 1. "MUX3_SEL,System interrupt select for CPU interrupt source 19."
|
|
hexmask.long.byte 0x10 16.--23. 1. "MUX2_SEL,System interrupt select for CPU interrupt source 18."
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "MUX1_SEL,System interrupt select for CPU interrupt source 17."
|
|
hexmask.long.byte 0x10 0.--7. 1. "MUX0_SEL,System interrupt select for CPU interrupt source 16."
|
|
line.long 0x14 "CM0_INT_CTL5,CM0+ interrupt control 5"
|
|
hexmask.long.byte 0x14 24.--31. 1. "MUX3_SEL,System interrupt select for CPU interrupt source 23."
|
|
hexmask.long.byte 0x14 16.--23. 1. "MUX2_SEL,System interrupt select for CPU interrupt source 22."
|
|
newline
|
|
hexmask.long.byte 0x14 8.--15. 1. "MUX1_SEL,System interrupt select for CPU interrupt source 21."
|
|
hexmask.long.byte 0x14 0.--7. 1. "MUX0_SEL,System interrupt select for CPU interrupt source 20."
|
|
line.long 0x18 "CM0_INT_CTL6,CM0+ interrupt control 6"
|
|
hexmask.long.byte 0x18 24.--31. 1. "MUX3_SEL,System interrupt select for CPU interrupt source 27."
|
|
hexmask.long.byte 0x18 16.--23. 1. "MUX2_SEL,System interrupt select for CPU interrupt source 26."
|
|
newline
|
|
hexmask.long.byte 0x18 8.--15. 1. "MUX1_SEL,System interrupt select for CPU interrupt source 25."
|
|
hexmask.long.byte 0x18 0.--7. 1. "MUX0_SEL,System interrupt select for CPU interrupt source 24."
|
|
line.long 0x1C "CM0_INT_CTL7,CM0+ interrupt control 7"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "MUX3_SEL,System interrupt select for CPU interrupt source 31."
|
|
hexmask.long.byte 0x1C 16.--23. 1. "MUX2_SEL,System interrupt select for CPU interrupt source 30."
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--15. 1. "MUX1_SEL,System interrupt select for CPU interrupt source 29."
|
|
hexmask.long.byte 0x1C 0.--7. 1. "MUX0_SEL,System interrupt select for CPU interrupt source 28."
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "CM4_PWR_CTL,CM4 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Set Power mode for CM4" "0: Switch CM4 off Power off clock off isolate reset..,1: Reset CM4 Clock off no isolated no retain and..,2: Put CM4 in Retained mode This can only become..,3: Switch CM4 on. Power on clock on no isolate no.."
|
|
line.long 0x4 "CM4_PWR_DELAY_CTL,CM4 power control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "CM4_STATUS,CM4 status"
|
|
bitfld.long 0x0 4. "PWR_DONE,After a PWR_MODE change this flag indicates if the new power mode has taken effect or not." "0,1"
|
|
bitfld.long 0x0 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode:" "0,1"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "CM4_CLOCK_CTL,CM4 clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FAST_INT_DIV,Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1 256] (FAST_INT_DIV is in the range [0 255])."
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "CM4_NMI_CTL,CM4 NMI control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MUX0_SEL,System interrupt select for CPU NMI. The reset value ensure that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset."
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "RAM0_CTL0,RAM 0 control 0"
|
|
bitfld.long 0x0 8.--9. "FAST_WS,Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "RAM1_CTL0,RAM 1 control 0"
|
|
bitfld.long 0x0 8.--9. "FAST_WS,Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
group.long 0x190++0x3
|
|
line.long 0x0 "RAM1_PWR_CTL,RAM1 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Set Power mode for SRAM1" "0: See CM4_PWR_CTL,1: undefined,2: See CM4_PWR_CTL,3: See CM4_PWR_CTL"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x0 "RAM2_CTL0,RAM 2 control 0"
|
|
bitfld.long 0x0 8.--9. "FAST_WS,Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
group.long 0x1B0++0x3
|
|
line.long 0x0 "RAM2_PWR_CTL,RAM2 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Set Power mode for SRAM2" "0: See CM4_PWR_CTL,1: undefined,2: See CM4_PWR_CTL,3: See CM4_PWR_CTL"
|
|
group.long 0x1C0++0x3
|
|
line.long 0x0 "RAM_PWR_DELAY_CTL,Power up delay used for all SRAM power domains"
|
|
hexmask.long.word 0x0 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x1D0++0x3
|
|
line.long 0x0 "ROM_CTL,ROM control"
|
|
bitfld.long 0x0 8.--9. "FAST_WS,Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
group.long 0x1F0++0x7
|
|
line.long 0x0 "UDB_PWR_CTL,UDB power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Set Power mode for UDBs" "0: See CM4_PWR_CTL,1: See CM4_PWR_CTL,2: See CM4_PWR_CTL,3: See CM4_PWR_CTL"
|
|
line.long 0x4 "UDB_PWR_DELAY_CTL,UDB power control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x0 "DP_STATUS,Debug port status"
|
|
bitfld.long 0x0 2. "SWJ_JTAG_SEL,Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected)." "0: SWD selected,1: JTAG selected"
|
|
bitfld.long 0x0 1. "SWJ_DEBUG_EN,Specifies if SWJ debug is enabled i.e. CDBGPWRUPACK is '1' and thus debug clocks are on:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "SWJ_CONNECTED,Specifies if the SWJ debug port is connected; i.e. debug host interface is active:" "0: Not connected/not active,1: Connected/active"
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "BUFF_CTL,Buffer control"
|
|
bitfld.long 0x0 0. "WRITE_BUFF,Specifies if write transfer can be buffered in the bus infrastructure bridges:" "0: Write transfers are not buffered,1: Write transfers can be buffered"
|
|
group.long 0x230++0x3
|
|
line.long 0x0 "DDFT_CTL,DDFT control"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DDFT_OUT1_SEL,Select signal for CPUSS DDFT[0]"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DDFT_OUT0_SEL,Select signal for CPUSS DDFT[0]"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "SYSTICK_CTL,SysTick timer control"
|
|
bitfld.long 0x0 31. "NOREF,Specifies if an external clock source is provided:" "0: An external clock source is provided,1: An external clock source is NOT provided and.."
|
|
bitfld.long 0x0 30. "SKEW,Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock:" "0: Precise,1: Imprecise"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "CLOCK_SOURCE,Specifies an external clock source:" "0: The low frequency clock 'clk_lf' is selected,1: The internal main oscillator,2: The external crystal oscillator,3: The SRSS 'clk_timer' is selected"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "TENMS,Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g. for a 32 768 Hz reference clock TENMS is 328 - 1 = 327."
|
|
group.long 0x2B0++0x3
|
|
line.long 0x0 "CM0_VECTOR_TABLE_BASE,CM0+ vector table base"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,Address of CM0+ vector table."
|
|
group.long 0x2C0++0x3
|
|
line.long 0x0 "CM4_VECTOR_TABLE_BASE,CM4 vector table base"
|
|
hexmask.long.tbyte 0x0 10.--31. 1. "ADDR22,Address of CM4 vector table."
|
|
group.long 0x320++0x3
|
|
line.long 0x0 "CM0_PC0_HANDLER,CM0+ protection context 0 handler"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt."
|
|
rgroup.long 0x400++0x3
|
|
line.long 0x0 "IDENTITY,Identity"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier of the transfer that reads the register."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context of the transfer that reads the register."
|
|
newline
|
|
bitfld.long 0x0 1. "NS,This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register." "0: secure mode,1: non-secure mode"
|
|
bitfld.long 0x0 0. "P,This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register." "0: user mode,1: privileged mode"
|
|
group.long 0x500++0x3
|
|
line.long 0x0 "PROTECTION,Protection status"
|
|
bitfld.long 0x0 0.--2. "STATE,Protection state:" "0: UNKNOWN,1: VIRGIN,2: NORMAL,3: SECURE,4: DEAD,?,?,?"
|
|
group.long 0x520++0x3
|
|
line.long 0x0 "CM0_NMI_CTL,CM0+ NMI control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MUX0_SEL,System interrupt select for CPU NMI. The reset value ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset."
|
|
group.long 0x540++0x3
|
|
line.long 0x0 "AP_CTL,Access port control"
|
|
bitfld.long 0x0 18. "SYS_DISABLE,Disables the system AP interface:" "0: Enabled,1: Disabled"
|
|
bitfld.long 0x0 17. "CM4_DISABLE,Disables the CM4 AP interface:" "0: Enabled,1: Disabled"
|
|
newline
|
|
bitfld.long 0x0 16. "CM0_DISABLE,Disables the CM0 AP interface:" "0: Enabled,1: Disabled"
|
|
bitfld.long 0x0 2. "SYS_ENABLE,Enables the system AP interface:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "CM4_ENABLE,Enables the CM4 AP interface:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "CM0_ENABLE,Enables the CM0 AP interface:" "0: Disabled,1: Enabled"
|
|
rgroup.long 0x5A0++0x3
|
|
line.long 0x0 "MBIST_STAT,Memory BIST status"
|
|
bitfld.long 0x0 1. "SFP_FAIL,Report status of the BIST run only valid if SFP_READY=1" "0,1"
|
|
bitfld.long 0x0 0. "SFP_READY,Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0." "0,1"
|
|
group.long 0xF000++0x7
|
|
line.long 0x0 "TRIM_ROM_CTL,ROM trim control"
|
|
bitfld.long 0x0 4. "RME,Read-Write margin enable control. This selects between the default Read-Write margin setting and the external pin Read-Write margin setting." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RM,N/A"
|
|
line.long 0x4 "TRIM_RAM_CTL,RAM trim control"
|
|
bitfld.long 0x4 12.--14. "WA,Write assist enable control (Active High)." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8.--9. "RA,Read Assist control for WL under-drive." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 5.--7. "WPULSE,Write Assist Pulse to control pulse width of negative voltage on SRAM bitline." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4. "RME,Read-Write margin enable control. This selects between the default Read-Write margin setting and the external RM[3:0] Read-Write margin setting." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "RM,N/A"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "IDENTITY,Identity"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier of the transfer that reads the register."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context of the transfer that reads the register."
|
|
newline
|
|
bitfld.long 0x0 1. "NS,This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register." "0: secure mode,1: non-secure mode"
|
|
bitfld.long 0x0 0. "P,This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register." "0: user mode,1: privileged mode"
|
|
line.long 0x4 "CM4_STATUS,CM4 status"
|
|
bitfld.long 0x4 4. "PWR_DONE,After a PWR_MODE change this flag indicates if the new power mode has taken effect or not." "0,1"
|
|
bitfld.long 0x4 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode:" "0,1"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "CM4_CLOCK_CTL,CM4 clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FAST_INT_DIV,Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1 256] (FAST_INT_DIV is in the range [0 255])."
|
|
line.long 0x4 "CM4_CTL,CM4 control"
|
|
bitfld.long 0x4 31. "IDC_MASK,CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
bitfld.long 0x4 28. "IXC_MASK,CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
newline
|
|
bitfld.long 0x4 27. "UFC_MASK,CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
bitfld.long 0x4 26. "OFC_MASK,CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
newline
|
|
bitfld.long 0x4 25. "DZC_MASK,CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
bitfld.long 0x4 24. "IOC_MASK,CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
rgroup.long 0x100++0x1F
|
|
line.long 0x0 "CM4_INT0_STATUS,CM4 interrupt 0 status"
|
|
bitfld.long 0x0 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 0."
|
|
line.long 0x4 "CM4_INT1_STATUS,CM4 interrupt 1 status"
|
|
bitfld.long 0x4 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 1."
|
|
line.long 0x8 "CM4_INT2_STATUS,CM4 interrupt 2 status"
|
|
bitfld.long 0x8 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 2."
|
|
line.long 0xC "CM4_INT3_STATUS,CM4 interrupt 3 status"
|
|
bitfld.long 0xC 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0xC 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 3."
|
|
line.long 0x10 "CM4_INT4_STATUS,CM4 interrupt 4 status"
|
|
bitfld.long 0x10 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x10 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 4."
|
|
line.long 0x14 "CM4_INT5_STATUS,CM4 interrupt 5 status"
|
|
bitfld.long 0x14 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x14 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 5."
|
|
line.long 0x18 "CM4_INT6_STATUS,CM4 interrupt 6 status"
|
|
bitfld.long 0x18 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x18 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 6."
|
|
line.long 0x1C "CM4_INT7_STATUS,CM4 interrupt 7 status"
|
|
bitfld.long 0x1C 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x1C 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 7."
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "CM4_VECTOR_TABLE_BASE,CM4 vector table base"
|
|
hexmask.long.tbyte 0x0 10.--31. 1. "ADDR22,Address of CM4 vector table. This register is used for CM4 warm and cold boot purposes: the CM0+ CPU initializes the CM4_VECTOR_TABLE_BASE register and the CM4 boot code uses the register to initialize the CM4 internal VTOR register."
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x240)++0x3
|
|
line.long 0x0 "CM4_NMI_CTL[$1],CM4 NMI control"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset."
|
|
repeat.end
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "UDB_PWR_CTL,UDB power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Set Power mode for UDBs" "0: See CM4_PWR_CTL,1: See CM4_PWR_CTL,2: See CM4_PWR_CTL,3: See CM4_PWR_CTL"
|
|
line.long 0x4 "UDB_PWR_DELAY_CTL,UDB power control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CM0_CTL,CM0+ control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 1. "ENABLED,Processor enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "SLV_STALL,Processor debug access control:" "0: Access,1: Stall access"
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "CM0_STATUS,CM0+ status"
|
|
bitfld.long 0x0 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field." "0,1"
|
|
bitfld.long 0x0 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode:" "0,1"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CM0_CLOCK_CTL,CM0+ clock control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PERI_INT_DIV,Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1 256] (PERI_INT_DIV is in the range [0 .."
|
|
hexmask.long.byte 0x0 8.--15. 1. "SLOW_INT_DIV,Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1 256] (SLOW_INT_DIV is in the range [0 255])."
|
|
rgroup.long 0x1100++0x1F
|
|
line.long 0x0 "CM0_INT0_STATUS,CM0+ interrupt 0 status"
|
|
bitfld.long 0x0 31. "SYSTEM_INT_VALID,Valid indication for SYSTEM_INT_IDX. When '0' no system interrupt for CPU interrupt 0 is valid/activated." "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 0."
|
|
line.long 0x4 "CM0_INT1_STATUS,CM0+ interrupt 1 status"
|
|
bitfld.long 0x4 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 1."
|
|
line.long 0x8 "CM0_INT2_STATUS,CM0+ interrupt 2 status"
|
|
bitfld.long 0x8 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 2."
|
|
line.long 0xC "CM0_INT3_STATUS,CM0+ interrupt 3 status"
|
|
bitfld.long 0xC 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0xC 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 3."
|
|
line.long 0x10 "CM0_INT4_STATUS,CM0+ interrupt 4 status"
|
|
bitfld.long 0x10 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x10 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 4."
|
|
line.long 0x14 "CM0_INT5_STATUS,CM0+ interrupt 5 status"
|
|
bitfld.long 0x14 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x14 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 5."
|
|
line.long 0x18 "CM0_INT6_STATUS,CM0+ interrupt 6 status"
|
|
bitfld.long 0x18 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x18 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 6."
|
|
line.long 0x1C "CM0_INT7_STATUS,CM0+ interrupt 7 status"
|
|
bitfld.long 0x1C 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x1C 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 7."
|
|
group.long 0x1120++0x3
|
|
line.long 0x0 "CM0_VECTOR_TABLE_BASE,CM0+ vector table base"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,Address of CM0+ vector table. This register is used for CM0+ warm boot purposes: the CM0+ warm boot code uses the register to initialize the CM0+ internal VTOR register."
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1140)++0x3
|
|
line.long 0x0 "CM0_NMI_CTL[$1],CM0+ NMI control"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset."
|
|
repeat.end
|
|
group.long 0x1200++0x7
|
|
line.long 0x0 "CM4_PWR_CTL,CM4 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Power mode." "0: Switch CM4 off Power off clock off isolate reset..,1: Reset CM4 Clock off no isolated no retain and..,2: Put CM4 in Retained mode This can only become..,3: Switch CM4 on. Power on clock on no isolate no.."
|
|
line.long 0x4 "CM4_PWR_DELAY_CTL,CM4 power control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x1300++0x3
|
|
line.long 0x0 "RAM0_CTL0,RAM 0 control"
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,Enable error injection for system SRAM 0." "0,1"
|
|
bitfld.long 0x0 17. "ECC_AUTO_CORRECT,HW ECC autocorrect functionality:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC checking:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 8.--9. "FAST_WS,Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
rgroup.long 0x1304++0x3
|
|
line.long 0x0 "RAM0_STATUS,RAM 0 status"
|
|
bitfld.long 0x0 0. "WB_EMPTY,Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode." "0: Write buffer NOT empty,1: Write buffer empty"
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x140)++0x3
|
|
line.long 0x0 "RAM0_PWR_MACRO_CTL[$1],RAM 0 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Set Power mode for 1 SRAM0 Macro" "0: See CM4_PWR_CTL,1: undefined,2: See CM4_PWR_CTL,3: See CM4_PWR_CTL"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1340)++0x3
|
|
line.long 0x0 "RAM0_PWR_MACRO_CTL[$1],RAM 0 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,SRAM Power mode." "0: Turn OFF the SRAM. This will trun OFF both array..,1: undefined,2: Keep SRAM in Retained mode. This will turn OFF..,3: Enable SRAM for regular operation. The SRAM.."
|
|
repeat.end
|
|
group.long 0x1380++0x3
|
|
line.long 0x0 "RAM1_CTL0,RAM 1 control"
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,See RAM0_CTL." "0,1"
|
|
bitfld.long 0x0 17. "ECC_AUTO_CORRECT,See RAM0_CTL." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,See RAM0_CTL." "0,1"
|
|
bitfld.long 0x0 8.--9. "FAST_WS,See RAM0_CTL." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,See RAM0_CTL." "0,1,2,3"
|
|
rgroup.long 0x1384++0x3
|
|
line.long 0x0 "RAM1_STATUS,RAM 1 status"
|
|
bitfld.long 0x0 0. "WB_EMPTY,See RAM0_STATUS." "0,1"
|
|
group.long 0x1388++0x3
|
|
line.long 0x0 "RAM1_PWR_CTL,RAM 1 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,See RAM0_PWR_MACRO_CTL."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Power mode." "0: See RAM0_PWR_MACRO_CTL.,1: undefined,2: See RAM0_PWR_MACRO_CTL.,3: See RAM0_PWR_MACRO_CTL."
|
|
group.long 0x13A0++0x3
|
|
line.long 0x0 "RAM2_CTL0,RAM 2 control"
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,See RAM0_CTL." "0,1"
|
|
bitfld.long 0x0 17. "ECC_AUTO_CORRECT,See RAM0_CTL." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,See RAM0_CTL." "0,1"
|
|
bitfld.long 0x0 8.--9. "FAST_WS,See RAM0_CTL." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,See RAM0_CTL." "0,1,2,3"
|
|
rgroup.long 0x13A4++0x3
|
|
line.long 0x0 "RAM2_STATUS,RAM 2 status"
|
|
bitfld.long 0x0 0. "WB_EMPTY,See RAM0_STATUS." "0,1"
|
|
group.long 0x13A8++0x3
|
|
line.long 0x0 "RAM2_PWR_CTL,RAM 2 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,See RAM0_PWR_MACRO_CTL."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Power mode." "0: See RAM0_PWR_MACRO_CTL.,1: undefined,2: See RAM0_PWR_MACRO_CTL.,3: See RAM0_PWR_MACRO_CTL."
|
|
group.long 0x13C0++0xB
|
|
line.long 0x0 "RAM_PWR_DELAY_CTL,Power up delay used for all SRAM power domains"
|
|
hexmask.long.word 0x0 0.--9. 1. "UP,Number clock cycles (clk_slow) delay needed after power domain power up"
|
|
line.long 0x4 "ROM_CTL,ROM control"
|
|
bitfld.long 0x4 8.--9. "FAST_WS,Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SLOW_WS,Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
line.long 0x8 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x8 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long 0x8 0.--24. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
rgroup.long 0x1400++0x3
|
|
line.long 0x0 "PRODUCT_ID,Product identifier and version (same as CoreSight RomTables)"
|
|
hexmask.long.byte 0x0 20.--23. 1. "MINOR_REV,Minor Revision starts with 1 increments with metal layer only tape-out (implemented with metal ECO-able tie-off)"
|
|
hexmask.long.byte 0x0 16.--19. 1. "MAJOR_REV,Major Revision starts with 1 increments with all layer tape-out (implemented with metal ECO-able tie-off)"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "FAMILY_ID,Family ID. Common ID for a product family."
|
|
rgroup.long 0x1410++0x3
|
|
line.long 0x0 "DP_STATUS,Debug port status"
|
|
bitfld.long 0x0 2. "SWJ_JTAG_SEL,Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected)." "0: SWD selected,1: JTAG selected"
|
|
bitfld.long 0x0 1. "SWJ_DEBUG_EN,Specifies if SWJ debug is enabled i.e. CDBGPWRUPACK is '1' and thus debug clocks are on:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "SWJ_CONNECTED,Specifies if the SWJ debug port is connected; i.e. debug host interface is active:" "0: Not connected/not active,1: Connected/active"
|
|
group.long 0x1414++0x3
|
|
line.long 0x0 "AP_CTL,Access port control"
|
|
bitfld.long 0x0 18. "SYS_DISABLE,Disables the system AP interface:" "0: Enabled,1: Disabled"
|
|
bitfld.long 0x0 17. "CM4_DISABLE,Disables the CM4 AP interface:" "0: Enabled,1: Disabled"
|
|
newline
|
|
bitfld.long 0x0 16. "CM0_DISABLE,Disables the CM0 AP interface:" "0: Enabled,1: Disabled"
|
|
bitfld.long 0x0 2. "SYS_ENABLE,Enables the system AP interface:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "CM4_ENABLE,Enables the CM4 AP interface:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "CM0_ENABLE,Enables the CM0 AP interface:" "0: Disabled,1: Enabled"
|
|
group.long 0x1500++0x3
|
|
line.long 0x0 "BUFF_CTL,Buffer control"
|
|
bitfld.long 0x0 0. "WRITE_BUFF,Specifies if write transfer can be buffered in the bus infrastructure bridges:" "0: Write transfers are not buffered,1: Write transfers can be buffered"
|
|
group.long 0x1600++0x3
|
|
line.long 0x0 "SYSTICK_CTL,SysTick timer control"
|
|
bitfld.long 0x0 31. "NOREF,Specifies if an external clock source is provided:" "0: An external clock source is provided,1: An external clock source is NOT provided and.."
|
|
bitfld.long 0x0 30. "SKEW,Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock:" "0: Precise,1: Imprecise"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "CLOCK_SOURCE,Specifies an external clock source:" "0: The low frequency clock 'clk_lf' is selected,1: The internal main oscillator,2: The external crystal oscillator,3: The SRSS 'clk_timer' is selected"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "TENMS,Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g. for a 32 768 Hz reference clock TENMS is 328 - 1 = 327."
|
|
rgroup.long 0x1704++0x3
|
|
line.long 0x0 "MBIST_STAT,Memory BIST status"
|
|
bitfld.long 0x0 1. "SFP_FAIL,Report status of the BIST run only valid if SFP_READY=1" "0,1"
|
|
bitfld.long 0x0 0. "SFP_READY,Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0." "0,1"
|
|
group.long 0x1800++0x7
|
|
line.long 0x0 "CAL_SUP_SET,Calibration support set and read"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Read without side effect write 1 to set"
|
|
line.long 0x4 "CAL_SUP_CLR,Calibration support clear and reset"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Read side effect: when read all bits are cleared write 1 to clear a specific bit"
|
|
group.long 0x2000++0x3
|
|
line.long 0x0 "CM0_PC_CTL,CM0+ protection context control"
|
|
hexmask.long.byte 0x0 0.--3. 1. "VALID,Valid fields for the protection context handler CM0_PCi_HANDLER registers:"
|
|
group.long 0x2040++0xF
|
|
line.long 0x0 "CM0_PC0_HANDLER,CM0+ protection context 0 handler"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt."
|
|
line.long 0x4 "CM0_PC1_HANDLER,CM0+ protection context 1 handler"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Address of the protection context 1 handler."
|
|
line.long 0x8 "CM0_PC2_HANDLER,CM0+ protection context 2 handler"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Address of the protection context 2 handler."
|
|
line.long 0xC "CM0_PC3_HANDLER,CM0+ protection context 3 handler"
|
|
hexmask.long 0xC 0.--31. 1. "ADDR,Address of the protection context 3 handler."
|
|
group.long 0x20C4++0x3
|
|
line.long 0x0 "PROTECTION,Protection status"
|
|
bitfld.long 0x0 0.--2. "STATE,Protection state:" "0: UNKNOWN,1: VIRGIN,2: NORMAL,3: SECURE,4: DEAD,?,?,?"
|
|
group.long 0x2100++0x7
|
|
line.long 0x0 "TRIM_ROM_CTL,ROM trim control"
|
|
hexmask.long 0x0 0.--31. 1. "TRIM,N/A"
|
|
line.long 0x4 "TRIM_RAM_CTL,RAM trim control"
|
|
hexmask.long 0x4 0.--31. 1. "TRIM,N/A"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 1023. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x8000)++0x3
|
|
line.long 0x0 "CM0_SYSTEM_INT_CTL[$1],CM0+ system interrupt control"
|
|
bitfld.long 0x0 31. "CPU_INT_VALID,Interrupt enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0.--2. "CPU_INT_IDX,CPU interrupt index (legal range [0 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g. if CPU_INT_IDX is '6' the system interrupt is mapped to CPU interrupt '6'." "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 1023. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xA000)++0x3
|
|
line.long 0x0 "CM4_SYSTEM_INT_CTL[$1],CM4 system interrupt control"
|
|
bitfld.long 0x0 31. "CPU_INT_VALID,N/A" "0,1"
|
|
bitfld.long 0x0 0.--2. "CPU_INT_IDX,N/A" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "IDENTITY,Identity"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier of the transfer that reads the register."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context of the transfer that reads the register."
|
|
newline
|
|
bitfld.long 0x0 1. "NS,This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register." "0: secure mode,1: non-secure mode"
|
|
bitfld.long 0x0 0. "P,This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register." "0: user mode,1: privileged mode"
|
|
line.long 0x4 "CM4_STATUS,CM4 status"
|
|
bitfld.long 0x4 4. "PWR_DONE,After a PWR_MODE change this flag indicates if the new power mode has taken effect or not." "0,1"
|
|
bitfld.long 0x4 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode:" "0,1"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "CM4_CLOCK_CTL,CM4 clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FAST_INT_DIV,Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1 256] (FAST_INT_DIV is in the range [0 255])."
|
|
line.long 0x4 "CM4_CTL,CM4 control"
|
|
bitfld.long 0x4 31. "IDC_MASK,CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
bitfld.long 0x4 28. "IXC_MASK,CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
newline
|
|
bitfld.long 0x4 27. "UFC_MASK,CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
bitfld.long 0x4 26. "OFC_MASK,CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
newline
|
|
bitfld.long 0x4 25. "DZC_MASK,CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
bitfld.long 0x4 24. "IOC_MASK,CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
rgroup.long 0x100++0x1F
|
|
line.long 0x0 "CM4_INT0_STATUS,CM4 interrupt 0 status"
|
|
bitfld.long 0x0 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 0."
|
|
line.long 0x4 "CM4_INT1_STATUS,CM4 interrupt 1 status"
|
|
bitfld.long 0x4 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 1."
|
|
line.long 0x8 "CM4_INT2_STATUS,CM4 interrupt 2 status"
|
|
bitfld.long 0x8 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 2."
|
|
line.long 0xC "CM4_INT3_STATUS,CM4 interrupt 3 status"
|
|
bitfld.long 0xC 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0xC 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 3."
|
|
line.long 0x10 "CM4_INT4_STATUS,CM4 interrupt 4 status"
|
|
bitfld.long 0x10 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x10 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 4."
|
|
line.long 0x14 "CM4_INT5_STATUS,CM4 interrupt 5 status"
|
|
bitfld.long 0x14 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x14 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 5."
|
|
line.long 0x18 "CM4_INT6_STATUS,CM4 interrupt 6 status"
|
|
bitfld.long 0x18 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x18 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 6."
|
|
line.long 0x1C "CM4_INT7_STATUS,CM4 interrupt 7 status"
|
|
bitfld.long 0x1C 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x1C 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 7."
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "CM4_VECTOR_TABLE_BASE,CM4 vector table base"
|
|
hexmask.long.tbyte 0x0 10.--31. 1. "ADDR22,Address of CM4 vector table. This register is used for CM4 warm and cold boot purposes: the CM0+ CPU initializes the CM4_VECTOR_TABLE_BASE register and the CM4 boot code uses the register to initialize the CM4 internal VTOR register."
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x240)++0x3
|
|
line.long 0x0 "CM4_NMI_CTL[$1],CM4 NMI control"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset."
|
|
repeat.end
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "UDB_PWR_CTL,UDB power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Set Power mode for UDBs" "0: See CM4_PWR_CTL,1: See CM4_PWR_CTL,2: See CM4_PWR_CTL,3: See CM4_PWR_CTL"
|
|
line.long 0x4 "UDB_PWR_DELAY_CTL,UDB power control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CM0_CTL,CM0+ control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 1. "ENABLED,Processor enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "SLV_STALL,Processor debug access control:" "0: Access,1: Stall access"
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "CM0_STATUS,CM0+ status"
|
|
bitfld.long 0x0 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field." "0,1"
|
|
bitfld.long 0x0 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode:" "0,1"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CM0_CLOCK_CTL,CM0+ clock control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PERI_INT_DIV,Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1 256] (PERI_INT_DIV is in the range [0 .."
|
|
hexmask.long.byte 0x0 8.--15. 1. "SLOW_INT_DIV,Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1 256] (SLOW_INT_DIV is in the range [0 255])."
|
|
rgroup.long 0x1100++0x1F
|
|
line.long 0x0 "CM0_INT0_STATUS,CM0+ interrupt 0 status"
|
|
bitfld.long 0x0 31. "SYSTEM_INT_VALID,Valid indication for SYSTEM_INT_IDX. When '0' no system interrupt for CPU interrupt 0 is valid/activated." "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 0."
|
|
line.long 0x4 "CM0_INT1_STATUS,CM0+ interrupt 1 status"
|
|
bitfld.long 0x4 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 1."
|
|
line.long 0x8 "CM0_INT2_STATUS,CM0+ interrupt 2 status"
|
|
bitfld.long 0x8 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 2."
|
|
line.long 0xC "CM0_INT3_STATUS,CM0+ interrupt 3 status"
|
|
bitfld.long 0xC 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0xC 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 3."
|
|
line.long 0x10 "CM0_INT4_STATUS,CM0+ interrupt 4 status"
|
|
bitfld.long 0x10 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x10 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 4."
|
|
line.long 0x14 "CM0_INT5_STATUS,CM0+ interrupt 5 status"
|
|
bitfld.long 0x14 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x14 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 5."
|
|
line.long 0x18 "CM0_INT6_STATUS,CM0+ interrupt 6 status"
|
|
bitfld.long 0x18 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x18 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 6."
|
|
line.long 0x1C "CM0_INT7_STATUS,CM0+ interrupt 7 status"
|
|
bitfld.long 0x1C 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x1C 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 7."
|
|
group.long 0x1120++0x3
|
|
line.long 0x0 "CM0_VECTOR_TABLE_BASE,CM0+ vector table base"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,Address of CM0+ vector table. This register is used for CM0+ warm boot purposes: the CM0+ warm boot code uses the register to initialize the CM0+ internal VTOR register."
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1140)++0x3
|
|
line.long 0x0 "CM0_NMI_CTL[$1],CM0+ NMI control"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset."
|
|
repeat.end
|
|
group.long 0x1200++0x7
|
|
line.long 0x0 "CM4_PWR_CTL,CM4 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Power mode." "0: Switch CM4 off Power off clock off isolate reset..,1: Reset CM4 Clock off no isolated no retain and..,2: Put CM4 in Retained mode This can only become..,3: Switch CM4 on. Power on clock on no isolate no.."
|
|
line.long 0x4 "CM4_PWR_DELAY_CTL,CM4 power control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x1300++0x3
|
|
line.long 0x0 "RAM0_CTL0,RAM 0 control"
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,Enable error injection for system SRAM 0." "0,1"
|
|
bitfld.long 0x0 17. "ECC_AUTO_CORRECT,HW ECC autocorrect functionality:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC checking:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 8.--9. "FAST_WS,Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
rgroup.long 0x1304++0x3
|
|
line.long 0x0 "RAM0_STATUS,RAM 0 status"
|
|
bitfld.long 0x0 0. "WB_EMPTY,Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode." "0: Write buffer NOT empty,1: Write buffer empty"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1340)++0x3
|
|
line.long 0x0 "RAM0_PWR_MACRO_CTL[$1],RAM 0 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,SRAM Power mode." "0: Turn OFF the SRAM. This will trun OFF both array..,1: undefined,2: Keep SRAM in Retained mode. This will turn OFF..,3: Enable SRAM for regular operation. The SRAM.."
|
|
repeat.end
|
|
group.long 0x1380++0x3
|
|
line.long 0x0 "RAM1_CTL0,RAM 1 control"
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,See RAM0_CTL." "0,1"
|
|
bitfld.long 0x0 17. "ECC_AUTO_CORRECT,See RAM0_CTL." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,See RAM0_CTL." "0,1"
|
|
bitfld.long 0x0 8.--9. "FAST_WS,See RAM0_CTL." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,See RAM0_CTL." "0,1,2,3"
|
|
rgroup.long 0x1384++0x3
|
|
line.long 0x0 "RAM1_STATUS,RAM 1 status"
|
|
bitfld.long 0x0 0. "WB_EMPTY,See RAM0_STATUS." "0,1"
|
|
group.long 0x1388++0x3
|
|
line.long 0x0 "RAM1_PWR_CTL,RAM 1 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,See RAM0_PWR_MACRO_CTL."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Power mode." "0: See RAM0_PWR_MACRO_CTL.,1: undefined,2: See RAM0_PWR_MACRO_CTL.,3: See RAM0_PWR_MACRO_CTL."
|
|
group.long 0x13A0++0x3
|
|
line.long 0x0 "RAM2_CTL0,RAM 2 control"
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,See RAM0_CTL." "0,1"
|
|
bitfld.long 0x0 17. "ECC_AUTO_CORRECT,See RAM0_CTL." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,See RAM0_CTL." "0,1"
|
|
bitfld.long 0x0 8.--9. "FAST_WS,See RAM0_CTL." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,See RAM0_CTL." "0,1,2,3"
|
|
rgroup.long 0x13A4++0x3
|
|
line.long 0x0 "RAM2_STATUS,RAM 2 status"
|
|
bitfld.long 0x0 0. "WB_EMPTY,See RAM0_STATUS." "0,1"
|
|
group.long 0x13A8++0x3
|
|
line.long 0x0 "RAM2_PWR_CTL,RAM 2 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,See RAM0_PWR_MACRO_CTL."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Power mode." "0: See RAM0_PWR_MACRO_CTL.,1: undefined,2: See RAM0_PWR_MACRO_CTL.,3: See RAM0_PWR_MACRO_CTL."
|
|
group.long 0x13C0++0xB
|
|
line.long 0x0 "RAM_PWR_DELAY_CTL,Power up delay used for all SRAM power domains"
|
|
hexmask.long.word 0x0 0.--9. 1. "UP,Number clock cycles (clk_slow) delay needed after power domain power up"
|
|
line.long 0x4 "ROM_CTL,ROM control"
|
|
bitfld.long 0x4 8.--9. "FAST_WS,Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SLOW_WS,Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
line.long 0x8 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x8 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long 0x8 0.--24. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
rgroup.long 0x1400++0x3
|
|
line.long 0x0 "PRODUCT_ID,Product identifier and version (same as CoreSight RomTables)"
|
|
hexmask.long.byte 0x0 20.--23. 1. "MINOR_REV,Minor Revision starts with 1 increments with metal layer only tape-out (implemented with metal ECO-able tie-off)"
|
|
hexmask.long.byte 0x0 16.--19. 1. "MAJOR_REV,Major Revision starts with 1 increments with all layer tape-out (implemented with metal ECO-able tie-off)"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "FAMILY_ID,Family ID. Common ID for a product family."
|
|
rgroup.long 0x1410++0x3
|
|
line.long 0x0 "DP_STATUS,Debug port status"
|
|
bitfld.long 0x0 2. "SWJ_JTAG_SEL,Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected)." "0: SWD selected,1: JTAG selected"
|
|
bitfld.long 0x0 1. "SWJ_DEBUG_EN,Specifies if SWJ debug is enabled i.e. CDBGPWRUPACK is '1' and thus debug clocks are on:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "SWJ_CONNECTED,Specifies if the SWJ debug port is connected; i.e. debug host interface is active:" "0: Not connected/not active,1: Connected/active"
|
|
group.long 0x1414++0x3
|
|
line.long 0x0 "AP_CTL,Access port control"
|
|
bitfld.long 0x0 18. "SYS_DISABLE,Disables the system AP interface:" "0: Enabled,1: Disabled"
|
|
bitfld.long 0x0 17. "CM4_DISABLE,Disables the CM4 AP interface:" "0: Enabled,1: Disabled"
|
|
newline
|
|
bitfld.long 0x0 16. "CM0_DISABLE,Disables the CM0 AP interface:" "0: Enabled,1: Disabled"
|
|
bitfld.long 0x0 2. "SYS_ENABLE,Enables the system AP interface:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "CM4_ENABLE,Enables the CM4 AP interface:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "CM0_ENABLE,Enables the CM0 AP interface:" "0: Disabled,1: Enabled"
|
|
group.long 0x1500++0x3
|
|
line.long 0x0 "BUFF_CTL,Buffer control"
|
|
bitfld.long 0x0 0. "WRITE_BUFF,Specifies if write transfer can be buffered in the bus infrastructure bridges:" "0: Write transfers are not buffered,1: Write transfers can be buffered"
|
|
group.long 0x1600++0x3
|
|
line.long 0x0 "SYSTICK_CTL,SysTick timer control"
|
|
bitfld.long 0x0 31. "NOREF,Specifies if an external clock source is provided:" "0: An external clock source is provided,1: An external clock source is NOT provided and.."
|
|
bitfld.long 0x0 30. "SKEW,Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock:" "0: Precise,1: Imprecise"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "CLOCK_SOURCE,Specifies an external clock source:" "0: The low frequency clock 'clk_lf' is selected,1: The internal main oscillator,2: The external crystal oscillator,3: The SRSS 'clk_timer' is selected"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "TENMS,Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g. for a 32 768 Hz reference clock TENMS is 328 - 1 = 327."
|
|
rgroup.long 0x1704++0x3
|
|
line.long 0x0 "MBIST_STAT,Memory BIST status"
|
|
bitfld.long 0x0 1. "SFP_FAIL,Report status of the BIST run only valid if SFP_READY=1" "0,1"
|
|
bitfld.long 0x0 0. "SFP_READY,Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0." "0,1"
|
|
group.long 0x1800++0x7
|
|
line.long 0x0 "CAL_SUP_SET,Calibration support set and read"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Read without side effect write 1 to set"
|
|
line.long 0x4 "CAL_SUP_CLR,Calibration support clear and reset"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Read side effect: when read all bits are cleared write 1 to clear a specific bit"
|
|
group.long 0x2000++0x3
|
|
line.long 0x0 "CM0_PC_CTL,CM0+ protection context control"
|
|
hexmask.long.byte 0x0 0.--3. 1. "VALID,Valid fields for the protection context handler CM0_PCi_HANDLER registers:"
|
|
group.long 0x2040++0xF
|
|
line.long 0x0 "CM0_PC0_HANDLER,CM0+ protection context 0 handler"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt."
|
|
line.long 0x4 "CM0_PC1_HANDLER,CM0+ protection context 1 handler"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Address of the protection context 1 handler."
|
|
line.long 0x8 "CM0_PC2_HANDLER,CM0+ protection context 2 handler"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Address of the protection context 2 handler."
|
|
line.long 0xC "CM0_PC3_HANDLER,CM0+ protection context 3 handler"
|
|
hexmask.long 0xC 0.--31. 1. "ADDR,Address of the protection context 3 handler."
|
|
group.long 0x20C4++0x3
|
|
line.long 0x0 "PROTECTION,Protection status"
|
|
bitfld.long 0x0 0.--2. "STATE,Protection state:" "0: UNKNOWN,1: VIRGIN,2: NORMAL,3: SECURE,4: DEAD,?,?,?"
|
|
group.long 0x2100++0x7
|
|
line.long 0x0 "TRIM_ROM_CTL,ROM trim control"
|
|
hexmask.long 0x0 0.--31. 1. "TRIM,N/A"
|
|
line.long 0x4 "TRIM_RAM_CTL,RAM trim control"
|
|
hexmask.long 0x4 0.--31. 1. "TRIM,N/A"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 1023. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x8000)++0x3
|
|
line.long 0x0 "CM0_SYSTEM_INT_CTL[$1],CM0+ system interrupt control"
|
|
bitfld.long 0x0 31. "CPU_INT_VALID,Interrupt enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0.--2. "CPU_INT_IDX,CPU interrupt index (legal range [0 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g. if CPU_INT_IDX is '6' the system interrupt is mapped to CPU interrupt '6'." "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 1023. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xA000)++0x3
|
|
line.long 0x0 "CM4_SYSTEM_INT_CTL[$1],CM4 system interrupt control"
|
|
bitfld.long 0x0 31. "CPU_INT_VALID,N/A" "0,1"
|
|
bitfld.long 0x0 0.--2. "CPU_INT_IDX,N/A" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "IDENTITY,Identity"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier of the transfer that reads the register."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context of the transfer that reads the register."
|
|
newline
|
|
bitfld.long 0x0 1. "NS,This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register." "0: secure mode,1: non-secure mode"
|
|
bitfld.long 0x0 0. "P,This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register." "0: user mode,1: privileged mode"
|
|
line.long 0x4 "CM4_STATUS,CM4 status"
|
|
bitfld.long 0x4 4. "PWR_DONE,After a PWR_MODE change this flag indicates if the new power mode has taken effect or not." "0,1"
|
|
bitfld.long 0x4 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode:" "0,1"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "CM4_CLOCK_CTL,CM4 clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FAST_INT_DIV,Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1 256] (FAST_INT_DIV is in the range [0 255])."
|
|
line.long 0x4 "CM4_CTL,CM4 control"
|
|
bitfld.long 0x4 31. "IDC_MASK,CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
bitfld.long 0x4 28. "IXC_MASK,CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
newline
|
|
bitfld.long 0x4 27. "UFC_MASK,CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
bitfld.long 0x4 26. "OFC_MASK,CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
newline
|
|
bitfld.long 0x4 25. "DZC_MASK,CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
bitfld.long 0x4 24. "IOC_MASK,CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
rgroup.long 0x100++0x1F
|
|
line.long 0x0 "CM4_INT0_STATUS,CM4 interrupt 0 status"
|
|
bitfld.long 0x0 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 0."
|
|
line.long 0x4 "CM4_INT1_STATUS,CM4 interrupt 1 status"
|
|
bitfld.long 0x4 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 1."
|
|
line.long 0x8 "CM4_INT2_STATUS,CM4 interrupt 2 status"
|
|
bitfld.long 0x8 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 2."
|
|
line.long 0xC "CM4_INT3_STATUS,CM4 interrupt 3 status"
|
|
bitfld.long 0xC 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0xC 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 3."
|
|
line.long 0x10 "CM4_INT4_STATUS,CM4 interrupt 4 status"
|
|
bitfld.long 0x10 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x10 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 4."
|
|
line.long 0x14 "CM4_INT5_STATUS,CM4 interrupt 5 status"
|
|
bitfld.long 0x14 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x14 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 5."
|
|
line.long 0x18 "CM4_INT6_STATUS,CM4 interrupt 6 status"
|
|
bitfld.long 0x18 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x18 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 6."
|
|
line.long 0x1C "CM4_INT7_STATUS,CM4 interrupt 7 status"
|
|
bitfld.long 0x1C 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x1C 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 7."
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "CM4_VECTOR_TABLE_BASE,CM4 vector table base"
|
|
hexmask.long.tbyte 0x0 10.--31. 1. "ADDR22,Address of CM4 vector table. This register is used for CM4 warm and cold boot purposes: the CM0+ CPU initializes the CM4_VECTOR_TABLE_BASE register and the CM4 boot code uses the register to initialize the CM4 internal VTOR register."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x240)++0x3
|
|
line.long 0x0 "CM4_NMI_CTL[$1],CM4 NMI control"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset."
|
|
repeat.end
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "UDB_PWR_CTL,UDB power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Set Power mode for UDBs" "0: See CM4_PWR_CTL,1: See CM4_PWR_CTL,2: See CM4_PWR_CTL,3: See CM4_PWR_CTL"
|
|
line.long 0x4 "UDB_PWR_DELAY_CTL,UDB power control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CM0_CTL,CM0+ control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 1. "ENABLED,Processor enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "SLV_STALL,Processor debug access control:" "0: Access,1: Stall access"
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "CM0_STATUS,CM0+ status"
|
|
bitfld.long 0x0 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field." "0,1"
|
|
bitfld.long 0x0 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode:" "0,1"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CM0_CLOCK_CTL,CM0+ clock control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PERI_INT_DIV,Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1 256] (PERI_INT_DIV is in the range [0 .."
|
|
hexmask.long.byte 0x0 8.--15. 1. "SLOW_INT_DIV,Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1 256] (SLOW_INT_DIV is in the range [0 255])."
|
|
rgroup.long 0x1100++0x1F
|
|
line.long 0x0 "CM0_INT0_STATUS,CM0+ interrupt 0 status"
|
|
bitfld.long 0x0 31. "SYSTEM_INT_VALID,Valid indication for SYSTEM_INT_IDX. When '0' no system interrupt for CPU interrupt 0 is valid/activated." "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 0."
|
|
line.long 0x4 "CM0_INT1_STATUS,CM0+ interrupt 1 status"
|
|
bitfld.long 0x4 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 1."
|
|
line.long 0x8 "CM0_INT2_STATUS,CM0+ interrupt 2 status"
|
|
bitfld.long 0x8 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 2."
|
|
line.long 0xC "CM0_INT3_STATUS,CM0+ interrupt 3 status"
|
|
bitfld.long 0xC 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0xC 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 3."
|
|
line.long 0x10 "CM0_INT4_STATUS,CM0+ interrupt 4 status"
|
|
bitfld.long 0x10 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x10 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 4."
|
|
line.long 0x14 "CM0_INT5_STATUS,CM0+ interrupt 5 status"
|
|
bitfld.long 0x14 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x14 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 5."
|
|
line.long 0x18 "CM0_INT6_STATUS,CM0+ interrupt 6 status"
|
|
bitfld.long 0x18 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x18 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 6."
|
|
line.long 0x1C "CM0_INT7_STATUS,CM0+ interrupt 7 status"
|
|
bitfld.long 0x1C 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x1C 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 7."
|
|
group.long 0x1120++0x3
|
|
line.long 0x0 "CM0_VECTOR_TABLE_BASE,CM0+ vector table base"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,Address of CM0+ vector table. This register is used for CM0+ warm boot purposes: the CM0+ warm boot code uses the register to initialize the CM0+ internal VTOR register."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1140)++0x3
|
|
line.long 0x0 "CM0_NMI_CTL[$1],CM0+ NMI control"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset."
|
|
repeat.end
|
|
group.long 0x1200++0x7
|
|
line.long 0x0 "CM4_PWR_CTL,CM4 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Power mode." "0: Switch CM4 off Power off clock off isolate reset..,1: Reset CM4 Clock off no isolated no retain and..,2: Put CM4 in Retained mode This can only become..,3: Switch CM4 on. Power on clock on no isolate no.."
|
|
line.long 0x4 "CM4_PWR_DELAY_CTL,CM4 power control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x1300++0x3
|
|
line.long 0x0 "RAM0_CTL0,RAM 0 control"
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,Enable error injection for system SRAM 0." "0,1"
|
|
bitfld.long 0x0 17. "ECC_AUTO_CORRECT,HW ECC autocorrect functionality:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC checking:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 8.--9. "FAST_WS,Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
rgroup.long 0x1304++0x3
|
|
line.long 0x0 "RAM0_STATUS,RAM 0 status"
|
|
bitfld.long 0x0 0. "WB_EMPTY,Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode." "0: Write buffer NOT empty,1: Write buffer empty"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1340)++0x3
|
|
line.long 0x0 "RAM0_PWR_MACRO_CTL[$1],RAM 0 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,SRAM Power mode." "0: Turn OFF the SRAM. This will trun OFF both array..,1: undefined,2: Keep SRAM in Retained mode. This will turn OFF..,3: Enable SRAM for regular operation. The SRAM.."
|
|
repeat.end
|
|
group.long 0x1380++0x3
|
|
line.long 0x0 "RAM1_CTL0,RAM 1 control"
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,See RAM0_CTL." "0,1"
|
|
bitfld.long 0x0 17. "ECC_AUTO_CORRECT,See RAM0_CTL." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,See RAM0_CTL." "0,1"
|
|
bitfld.long 0x0 8.--9. "FAST_WS,See RAM0_CTL." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,See RAM0_CTL." "0,1,2,3"
|
|
rgroup.long 0x1384++0x3
|
|
line.long 0x0 "RAM1_STATUS,RAM 1 status"
|
|
bitfld.long 0x0 0. "WB_EMPTY,See RAM0_STATUS." "0,1"
|
|
group.long 0x1388++0x3
|
|
line.long 0x0 "RAM1_PWR_CTL,RAM 1 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,See RAM0_PWR_MACRO_CTL."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Power mode." "0: See RAM0_PWR_MACRO_CTL.,1: undefined,2: See RAM0_PWR_MACRO_CTL.,3: See RAM0_PWR_MACRO_CTL."
|
|
group.long 0x13A0++0x3
|
|
line.long 0x0 "RAM2_CTL0,RAM 2 control"
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,See RAM0_CTL." "0,1"
|
|
bitfld.long 0x0 17. "ECC_AUTO_CORRECT,See RAM0_CTL." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,See RAM0_CTL." "0,1"
|
|
bitfld.long 0x0 8.--9. "FAST_WS,See RAM0_CTL." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,See RAM0_CTL." "0,1,2,3"
|
|
rgroup.long 0x13A4++0x3
|
|
line.long 0x0 "RAM2_STATUS,RAM 2 status"
|
|
bitfld.long 0x0 0. "WB_EMPTY,See RAM0_STATUS." "0,1"
|
|
group.long 0x13A8++0x3
|
|
line.long 0x0 "RAM2_PWR_CTL,RAM 2 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,See RAM0_PWR_MACRO_CTL."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Power mode." "0: See RAM0_PWR_MACRO_CTL.,1: undefined,2: See RAM0_PWR_MACRO_CTL.,3: See RAM0_PWR_MACRO_CTL."
|
|
group.long 0x13C0++0xB
|
|
line.long 0x0 "RAM_PWR_DELAY_CTL,Power up delay used for all SRAM power domains"
|
|
hexmask.long.word 0x0 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
line.long 0x4 "ROM_CTL,ROM control"
|
|
bitfld.long 0x4 8.--9. "FAST_WS,Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SLOW_WS,Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
line.long 0x8 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x8 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long 0x8 0.--24. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
rgroup.long 0x1400++0x3
|
|
line.long 0x0 "PRODUCT_ID,Product identifier and version (same as CoreSight RomTables)"
|
|
hexmask.long.byte 0x0 20.--23. 1. "MINOR_REV,Minor Revision starts with 1 increments with metal layer only tape-out (implemented with metal ECO-able tie-off)"
|
|
hexmask.long.byte 0x0 16.--19. 1. "MAJOR_REV,Major Revision starts with 1 increments with all layer tape-out (implemented with metal ECO-able tie-off)"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "FAMILY_ID,Family ID a.k.a. Partnumber a.k.a. Silicon ID"
|
|
rgroup.long 0x1410++0x3
|
|
line.long 0x0 "DP_STATUS,Debug port status"
|
|
bitfld.long 0x0 2. "SWJ_JTAG_SEL,Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected)." "0: SWD selected,1: JTAG selected"
|
|
bitfld.long 0x0 1. "SWJ_DEBUG_EN,Specifies if SWJ debug is enabled i.e. CDBGPWRUPACK is '1' and thus debug clocks are on:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "SWJ_CONNECTED,Specifies if the SWJ debug port is connected; i.e. debug host interface is active:" "0: Not connected/not active,1: Connected/active"
|
|
group.long 0x1414++0x3
|
|
line.long 0x0 "AP_CTL,Access port control"
|
|
bitfld.long 0x0 18. "SYS_DISABLE,Disables the system AP interface:" "0: Enabled,1: Disabled"
|
|
bitfld.long 0x0 17. "CM4_DISABLE,Disables the CM4 AP interface:" "0: Enabled,1: Disabled"
|
|
newline
|
|
bitfld.long 0x0 16. "CM0_DISABLE,Disables the CM0 AP interface:" "0: Enabled,1: Disabled"
|
|
bitfld.long 0x0 2. "SYS_ENABLE,Enables the system AP interface:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "CM4_ENABLE,Enables the CM4 AP interface:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "CM0_ENABLE,Enables the CM0 AP interface:" "0: Disabled,1: Enabled"
|
|
group.long 0x1500++0x3
|
|
line.long 0x0 "BUFF_CTL,Buffer control"
|
|
bitfld.long 0x0 0. "WRITE_BUFF,Specifies if write transfer can be buffered in the bus infrastructure bridges:" "0: Write transfers are not buffered,1: Write transfers can be buffered"
|
|
group.long 0x1600++0x3
|
|
line.long 0x0 "SYSTICK_CTL,SysTick timer control"
|
|
bitfld.long 0x0 31. "NOREF,Specifies if an external clock source is provided:" "0: An external clock source is provided,1: An external clock source is NOT provided and.."
|
|
bitfld.long 0x0 30. "SKEW,Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock:" "0: Precise,1: Imprecise"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "CLOCK_SOURCE,Specifies an external clock source:" "0: The low frequency clock 'clk_lf' is selected,1: The internal main oscillator,2: The external crystal oscillator,3: The SRSS 'clk_timer' is selected"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "TENMS,Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g. for a 32 768 Hz reference clock TENMS is 328 - 1 = 327."
|
|
rgroup.long 0x1704++0x3
|
|
line.long 0x0 "MBIST_STAT,Memory BIST status"
|
|
bitfld.long 0x0 1. "SFP_FAIL,Report status of the BIST run only valid if SFP_READY=1" "0,1"
|
|
bitfld.long 0x0 0. "SFP_READY,Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0." "0,1"
|
|
group.long 0x1800++0x7
|
|
line.long 0x0 "CAL_SUP_SET,Calibration support set and read"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Read without side effect write 1 to set"
|
|
line.long 0x4 "CAL_SUP_CLR,Calibration support clear and reset"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Read side effect: when read all bits are cleared write 1 to clear a specific bit"
|
|
group.long 0x2000++0x3
|
|
line.long 0x0 "CM0_PC_CTL,CM0+ protection context control"
|
|
hexmask.long.byte 0x0 0.--3. 1. "VALID,Valid fields for the protection context handler CM0_PCi_HANDLER registers:"
|
|
group.long 0x2040++0xF
|
|
line.long 0x0 "CM0_PC0_HANDLER,CM0+ protection context 0 handler"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt."
|
|
line.long 0x4 "CM0_PC1_HANDLER,CM0+ protection context 1 handler"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Address of the protection context 1 handler."
|
|
line.long 0x8 "CM0_PC2_HANDLER,CM0+ protection context 2 handler"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Address of the protection context 2 handler."
|
|
line.long 0xC "CM0_PC3_HANDLER,CM0+ protection context 3 handler"
|
|
hexmask.long 0xC 0.--31. 1. "ADDR,Address of the protection context 3 handler."
|
|
group.long 0x20C4++0x3
|
|
line.long 0x0 "PROTECTION,Protection status"
|
|
bitfld.long 0x0 0.--2. "STATE,Protection state:" "0: UNKNOWN,1: VIRGIN,2: NORMAL,3: SECURE,4: DEAD,?,?,?"
|
|
group.long 0x2100++0x7
|
|
line.long 0x0 "TRIM_ROM_CTL,ROM trim control"
|
|
hexmask.long 0x0 0.--31. 1. "TRIM,N/A"
|
|
line.long 0x4 "TRIM_RAM_CTL,RAM trim control"
|
|
hexmask.long 0x4 0.--31. 1. "TRIM,N/A"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 1023. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x8000)++0x3
|
|
line.long 0x0 "CM0_SYSTEM_INT_CTL[$1],CM0+ system interrupt control"
|
|
bitfld.long 0x0 31. "CPU_INT_VALID,Interrupt enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0.--2. "CPU_INT_IDX,CPU interrupt index (legal range [0 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g. if CPU_INT_IDX is '6' the system interrupt is mapped to CPU interrupt '6'." "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 1023. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xA000)++0x3
|
|
line.long 0x0 "CM4_SYSTEM_INT_CTL[$1],CM4 system interrupt control"
|
|
bitfld.long 0x0 31. "CPU_INT_VALID,N/A" "0,1"
|
|
bitfld.long 0x0 0.--2. "CPU_INT_IDX,N/A" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x40110000
|
|
elif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
base ad:0x40100000
|
|
endif
|
|
tree "CRYPTO (Cryptography Component)"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: Disabled,1: Enabled"
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x0 17. "ECC_INJ_EN,Enable parity injection for SRAM." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC checking:" "0: Disabled,1: Enabled"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
bitfld.long 0x0 17. "ECC_INJ_EN,Enable parity injection for SRAM." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC checking:" "0: Disabled,1: Enabled"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
bitfld.long 0x0 17. "ECC_INJ_EN,Enable parity injection for SRAM." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC checking:" "0: Disabled,1: Enabled"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Set power mode for memory buffer SRAM." "0: See CM4_PWR_CTL,1: undefined,2: See CM4_PWR_CTL,3: See CM4_PWR_CTL"
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "CMD_FF_BUSY,Reflects the state of the command FIFO (copy of CMD_FF_STATUS.BUSY):" "0: No instruction pending,1: Instruction pending"
|
|
bitfld.long 0x0 7. "VU_BUSY,Reflects the state of the vector unit component." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TR_BUSY,Reflects the state of the TR component." "0,1"
|
|
bitfld.long 0x0 5. "PR_BUSY,Reflects the state of the PR component." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "STR_BUSY,Reflects the state of the CRC component." "0,1"
|
|
bitfld.long 0x0 3. "CRC_BUSY,Reflects the state of the CRC component." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SHA_BUSY,Reflects the state of the SHA component." "0,1"
|
|
bitfld.long 0x0 1. "DES_BUSY,Reflects the state of the DES component." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "AES_BUSY,Reflects the state of the AES component:" "0: Component is not busy,1: Component is busy performing an instruction"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "RAM_PWRUP_DELAY,Power up delay used for SRAM power domain"
|
|
hexmask.long.word 0x0 0.--9. 1. "PWRUP_DELAY,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "INSTR_FF_CTL,Instruction FIFO control"
|
|
bitfld.long 0x0 17. "BLOCK,This field specifies the behavior when an instruction is written to a full FIFO (INSTR_FIFO_WR MMIO register):" "0: The write is ignored/dropped and the INTR,1: The write is blocked"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the instruction FIFO is cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EVENT_LEVEL,Event level. When the number of entries in the instruction FIFO is less than the amount of this field an event is generated:" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "INSTR_FF_STATUS,Instruction FIFO status"
|
|
bitfld.long 0x0 31. "BUSY,Reflects the state of the instruction FIFO:" "0: No instruction pending,1: Instruction pending"
|
|
bitfld.long 0x0 16. "EVENT,Instruction FIFO event." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USED,Number of instructions in the instruction FIFO. The value of this field ranges from 0 to 8."
|
|
wgroup.long 0x48++0x3
|
|
line.long 0x0 "INSTR_FF_WR,Instruction FIFO write"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Instruction or instruction operand data that is written to the instruction FIFO."
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x80)++0x3
|
|
line.long 0x0 "RF_DATA[$1],Register-file"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Register-file data."
|
|
repeat.end
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "AES_CTL,AES control"
|
|
bitfld.long 0x0 0.--1. "KEY_SIZE,AES key size:" "0: 128-bit key,1: 192-bit key,2: 256-bit key,3: Undefined"
|
|
rgroup.long 0x180++0x3
|
|
line.long 0x0 "STR_RESULT,String result"
|
|
bitfld.long 0x0 0. "MEMCMP,Result of a STR_MEMCMP operation:" "0: source 0 equals source 1,1: source 0 does NOT equal source 1"
|
|
group.long 0x210++0x3
|
|
line.long 0x0 "PR_RESULT,Pseudo random result"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Result of a pseudo random number generation operation. The resulting value DATA is in the range [0 MAX] with MAX specified by rsrc0. HW generates the number in this field."
|
|
group.long 0x288++0x3
|
|
line.long 0x0 "TR_RESULT,True random result"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Generated true random number. HW generates the number in the least significant bit positions of this field. The TR_DATA_AVAILABLE interrupt cause is activated when the number is generated."
|
|
group.long 0x300++0x3
|
|
line.long 0x0 "SHA_CTL,SHA control"
|
|
bitfld.long 0x0 0.--2. "MODE,SHA mode:" "0: SHA1,1: SHA224,2: SHA512/224,?,?,?,?,?"
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "CRC_CTL,CRC control"
|
|
bitfld.long 0x0 8. "REM_REVERSE,Specifies whether the remainder is bit reversed (reversal is performed after XORing):" "0: No,1: Yes"
|
|
bitfld.long 0x0 0. "DATA_REVERSE,Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):" "0: Most significant bit,1: Least significant bit"
|
|
group.long 0x410++0x3
|
|
line.long 0x0 "CRC_DATA_CTL,CRC data control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_XOR,Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal."
|
|
group.long 0x420++0x3
|
|
line.long 0x0 "CRC_POL_CTL,CRC polynomial control"
|
|
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less.."
|
|
group.long 0x430++0x3
|
|
line.long 0x0 "CRC_LFSR_CTL,CRC LFSR control"
|
|
hexmask.long 0x0 0.--31. 1. "LFSR32,State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value."
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "CRC_REM_CTL,CRC remainder control"
|
|
hexmask.long 0x0 0.--31. 1. "REM_XOR,Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal."
|
|
rgroup.long 0x448++0x3
|
|
line.long 0x0 "CRC_REM_RESULT,CRC remainder result"
|
|
hexmask.long 0x0 0.--31. 1. "REM,Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:"
|
|
group.long 0x480++0x7
|
|
line.long 0x0 "VU_CTL0,Vector unit control 0"
|
|
bitfld.long 0x0 0. "ALWAYS_EXECUTE,Specifies if a conditional instruction is executed or not when its condition code evaluates to false/'0'." "0: The instruction is NOT executed,1: The instruction is executed"
|
|
line.long 0x4 "VU_CTL1,Vector unit control 1"
|
|
hexmask.long.tbyte 0x4 14.--31. 1. "ADDR,Specifies base address of vector unit operands in memory. The register-file registers provide offsets wrt. this base address."
|
|
rgroup.long 0x490++0x3
|
|
line.long 0x0 "VU_STATUS,Vector unit status"
|
|
bitfld.long 0x0 3. "ONE,STATUS ONE field." "0,1"
|
|
bitfld.long 0x0 2. "ZERO,STATUS ZERO field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EVEN,STATUS EVEN field." "0,1"
|
|
bitfld.long 0x0 0. "CARRY,STATUS CARRY field." "0,1"
|
|
group.long 0x7C0++0xB
|
|
line.long 0x0 "INTR,Interrupt register"
|
|
bitfld.long 0x0 20. "TR_RC_DETECT_ERROR,This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a disproportionate occurrence of a specific bit value." "0,1"
|
|
bitfld.long 0x0 19. "TR_AP_DETECT_ERROR,This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a repetition of a specific bit value." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "BUS_ERROR,This interrupt cause is activated (HW sets the field to '1') when a AHB-Lite bus error is observed on the AHB-Lite master interface." "0,1"
|
|
bitfld.long 0x0 17. "INSTR_CC_ERROR,This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined condition code. This error is only generated for VU instructions." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "INSTR_OPC_ERROR,This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined operation code (opcode)." "0,1"
|
|
bitfld.long 0x0 4. "PR_DATA_AVAILABLE,This interrupt cause is activated (HW sets the field to '1') when the pseudo random number generator has generated a data value." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TR_DATA_AVAILABLE,This interrupt cause is activated (HW sets the field to '1') when the true random number generator has generated a data value of the specified bit size." "0,1"
|
|
bitfld.long 0x0 2. "TR_INITIALIZED,This interrupt cause is activated (HW sets the field to '1') when the true random number generator is initialized." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INSTR_FF_OVERFLOW,This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO overflows (an attempt is made to write to a full FIFO)." "0,1"
|
|
bitfld.long 0x0 0. "INSTR_FF_LEVEL,This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO event is activated." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set register"
|
|
bitfld.long 0x4 20. "TR_RC_DETECT_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 19. "TR_AP_DETECT_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "BUS_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 17. "INSTR_CC_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "INSTR_OPC_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 4. "PR_DATA_AVAILABLE,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TR_DATA_AVAILABLE,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 2. "TR_INITIALIZED,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "INSTR_FF_OVERFLOW,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "INSTR_FF_LEVEL,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 20. "TR_RC_DETECT_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 19. "TR_AP_DETECT_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "BUS_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 17. "INSTR_CC_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "INSTR_OPC_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 4. "PR_DATA_AVAILABLE,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "TR_DATA_AVAILABLE,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 2. "TR_INITIALIZED,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "INSTR_FF_OVERFLOW,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "INSTR_FF_LEVEL,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
rgroup.long 0x7CC++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x0 20. "TR_RC_DETECT_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 19. "TR_AP_DETECT_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 17. "INSTR_CC_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "INSTR_OPC_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 4. "PR_DATA_AVAILABLE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TR_DATA_AVAILABLE,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 2. "TR_INITIALIZED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INSTR_FF_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "INSTR_FF_LEVEL,Logical and of corresponding request and mask bits." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "RAM_PWR_CTL,SRAM power control"
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Set power mode for memory buffer SRAM." "0: See CM4_PWR_CTL,1: undefined,2: See CM4_PWR_CTL,3: See CM4_PWR_CTL"
|
|
line.long 0x4 "RAM_PWR_DELAY_CTL,SRAM power delay control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
line.long 0x8 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x8 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.word 0x8 0.--12. 1. "WORD_ADDR,Specifies the word address where the parity is injected."
|
|
group.long 0x100++0xB
|
|
line.long 0x0 "INTR,Interrupt register"
|
|
bitfld.long 0x0 21. "INSTR_DEV_KEY_ERROR,This interrupt cause is activated (HW sets the field to '1') when the LOAD_DEV_KEY instruction tries to load a device key whose DEV_KEY_ADDR_CTL.VALID or DEV_KEY_CTL.ALLOWED is set to '0'." "0,1"
|
|
bitfld.long 0x0 20. "TR_RC_DETECT_ERROR,This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a disproportionate occurrence of a specific bit value." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TR_AP_DETECT_ERROR,This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a repetition of a specific bit value." "0,1"
|
|
bitfld.long 0x0 18. "BUS_ERROR,This interrupt cause is activated (HW sets the field to '1') when a AHB-Lite bus error is observed on the AHB-Lite master interface." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "INSTR_CC_ERROR,This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined condition code. This error is only generated for VU instructions." "0,1"
|
|
bitfld.long 0x0 16. "INSTR_OPC_ERROR,This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined operation code (opcode)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PR_DATA_AVAILABLE,This interrupt cause is activated (HW sets the field to '1') when the pseudo random number generator has generated a data value." "0,1"
|
|
bitfld.long 0x0 3. "TR_DATA_AVAILABLE,This interrupt cause is activated (HW sets the field to '1') when the true random number generator has generated a data value of the specified bit size." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TR_INITIALIZED,This interrupt cause is activated (HW sets the field to '1') when the true random number generator is initialized." "0,1"
|
|
bitfld.long 0x0 1. "INSTR_FF_OVERFLOW,This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO overflows (an attempt is made to write to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "INSTR_FF_LEVEL,This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO event is activated." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set register"
|
|
bitfld.long 0x4 21. "INSTR_DEV_KEY_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 20. "TR_RC_DETECT_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "TR_AP_DETECT_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 18. "BUS_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "INSTR_CC_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 16. "INSTR_OPC_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PR_DATA_AVAILABLE,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 3. "TR_DATA_AVAILABLE,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TR_INITIALIZED,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 1. "INSTR_FF_OVERFLOW,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "INSTR_FF_LEVEL,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 21. "INSTR_DEV_KEY_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 20. "TR_RC_DETECT_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "TR_AP_DETECT_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 18. "BUS_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "INSTR_CC_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 16. "INSTR_OPC_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PR_DATA_AVAILABLE,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 3. "TR_DATA_AVAILABLE,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "TR_INITIALIZED,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 1. "INSTR_FF_OVERFLOW,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "INSTR_FF_LEVEL,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
rgroup.long 0x10C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x0 21. "INSTR_DEV_KEY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 20. "TR_RC_DETECT_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TR_AP_DETECT_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 18. "BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "INSTR_CC_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 16. "INSTR_OPC_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PR_DATA_AVAILABLE,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 3. "TR_DATA_AVAILABLE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TR_INITIALIZED,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 1. "INSTR_FF_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "INSTR_FF_LEVEL,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0x20C++0x7
|
|
line.long 0x0 "PR_MAX_CTL,Pseudo random maximum control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Maximum value of to be generated random number"
|
|
line.long 0x4 "PR_CMD,Pseudo random command"
|
|
bitfld.long 0x4 0. "START,Pseudo random command. On a generated number HW sets this field to '0' and sets INTR.PR_DATA_AVAILABLE to '1." "0,1"
|
|
group.long 0x218++0x3
|
|
line.long 0x0 "PR_RESULT,Pseudo random result"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Result of a pseudo random number generation operation. The resulting value DATA is in the range [0 PR_MAX_CTL.DATA32]. The PR_DATA_AVAILABLE interrupt cause is activated when the number is generated."
|
|
group.long 0x288++0x3
|
|
line.long 0x0 "TR_CTL2,True random control 2"
|
|
hexmask.long.byte 0x0 0.--5. 1. "SIZE,Bit size of generated random number in TR_RESULT. Legal range is in [0 32]."
|
|
rgroup.long 0x28C++0x3
|
|
line.long 0x0 "TR_STATUS,True random status"
|
|
bitfld.long 0x0 0. "INITIALIZED,Reflects the state of the true random number generator:" "0: Not initialized,1: Initialized"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "TR_CMD,True random command"
|
|
bitfld.long 0x0 0. "START,True random command. On completion of the command HW sets this field to '0' and sets INTR.TR_DATA_AVAILABLE to '1 when:" "0,1"
|
|
group.long 0x298++0x3
|
|
line.long 0x0 "TR_RESULT,True random result"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Generated true random number. HW generates the number in the least significant bit positions (TR_CTL2.SIZE) of this field. The TR_DATA_AVAILABLE interrupt cause is activated when the number is generated."
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "RAM_PWR_CTL,SRAM power control"
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Set power mode for memory buffer SRAM." "0: See CM4_PWR_CTL,1: undefined,2: See CM4_PWR_CTL,3: See CM4_PWR_CTL"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "RAM_PWR_CTL,SRAM power control"
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Set power mode for memory buffer SRAM." "0: See CM4_PWR_CTL,1: undefined,2: See CM4_PWR_CTL,3: See CM4_PWR_CTL"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "RAM_PWR_DELAY_CTL,SRAM power delay control"
|
|
hexmask.long.word 0x0 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "RAM_PWR_DELAY_CTL,SRAM power delay control"
|
|
hexmask.long.word 0x0 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.word 0x0 0.--12. 1. "WORD_ADDR,Specifies the word address where the parity is injected."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.word 0x0 0.--12. 1. "WORD_ADDR,Specifies the word address where the parity is injected."
|
|
endif
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "ERROR_STATUS0,Error status 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Captures error description information. For INSTR_OPC_ERROR:"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "ERROR_STATUS1,Error status 1"
|
|
bitfld.long 0x0 31. "VALID,Specifies if ERROR_STATUS0 and ERROR_STATUS1 capture valid error information." "0,1"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
bitfld.long 0x0 24.--26. "IDX,Error source:" "0: INSTR_OPC_ERROR,1: INSTR_CC_ERROR,2: BUS_ERROR,3: TR_AP_DETECT_ERROR,4: TR_RC_DETECT_ERROR,?,?,?"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "DATA23,Captures error description information. For BUS_ERROR:"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
rbitfld.long 0x0 24.--26. "IDX,Error source:" "0: INSTR_OPC_ERROR,1: INSTR_CC_ERROR,2: BUS_ERROR,3: TR_AP_DETECT_ERROR,4: TR_RC_DETECT_ERROR,5: INSTR_DEV_KEY_ERROR,?,?"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "DATA24,Specifies error description information."
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
rbitfld.long 0x0 24.--26. "IDX,Error source:" "0: INSTR_OPC_ERROR,1: INSTR_CC_ERROR,2: BUS_ERROR,3: TR_AP_DETECT_ERROR,4: TR_RC_DETECT_ERROR,5: INSTR_DEV_KEY_ERROR,?,?"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "DATA24,Specifies error description information."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
rbitfld.long 0x0 24.--26. "IDX,Error source:" "0: INSTR_OPC_ERROR,1: INSTR_CC_ERROR,2: BUS_ERROR,3: TR_AP_DETECT_ERROR,4: TR_RC_DETECT_ERROR,5: INSTR_DEV_KEY_ERROR,?,?"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "DATA24,Specifies error description information."
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "INTR,Interrupt register"
|
|
bitfld.long 0x0 21. "INSTR_DEV_KEY_ERROR,This interrupt cause is activated (HW sets the field to '1') when the LOAD_DEV_KEY instruction tries to load a device key whose DEV_KEY_ADDR_CTL.VALID or DEV_KEY_CTL.ALLOWED is set to '0'." "0,1"
|
|
bitfld.long 0x0 20. "TR_RC_DETECT_ERROR,This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a disproportionate occurrence of a specific bit value." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TR_AP_DETECT_ERROR,This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a repetition of a specific bit value." "0,1"
|
|
bitfld.long 0x0 18. "BUS_ERROR,This interrupt cause is activated (HW sets the field to '1') when a AHB-Lite bus error is observed on the AHB-Lite master interface." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "INSTR_CC_ERROR,This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined condition code. This error is only generated for VU instructions." "0,1"
|
|
bitfld.long 0x0 16. "INSTR_OPC_ERROR,This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined operation code (opcode)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PR_DATA_AVAILABLE,This interrupt cause is activated (HW sets the field to '1') when the pseudo random number generator has generated a data value." "0,1"
|
|
bitfld.long 0x0 3. "TR_DATA_AVAILABLE,This interrupt cause is activated (HW sets the field to '1') when the true random number generator has generated a data value of the specified bit size." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TR_INITIALIZED,This interrupt cause is activated (HW sets the field to '1') when the true random number generator is initialized." "0,1"
|
|
bitfld.long 0x0 1. "INSTR_FF_OVERFLOW,This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO overflows (an attempt is made to write to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "INSTR_FF_LEVEL,This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO event is activated." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "INTR,Interrupt register"
|
|
bitfld.long 0x0 21. "INSTR_DEV_KEY_ERROR,This interrupt cause is activated (HW sets the field to '1') when the LOAD_DEV_KEY instruction tries to load a device key whose DEV_KEY_ADDR_CTL.VALID or DEV_KEY_CTL.ALLOWED is set to '0'." "0,1"
|
|
bitfld.long 0x0 20. "TR_RC_DETECT_ERROR,This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a disproportionate occurrence of a specific bit value." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TR_AP_DETECT_ERROR,This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a repetition of a specific bit value." "0,1"
|
|
bitfld.long 0x0 18. "BUS_ERROR,This interrupt cause is activated (HW sets the field to '1') when a AHB-Lite bus error is observed on the AHB-Lite master interface." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "INSTR_CC_ERROR,This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined condition code. This error is only generated for VU instructions." "0,1"
|
|
bitfld.long 0x0 16. "INSTR_OPC_ERROR,This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined operation code (opcode)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PR_DATA_AVAILABLE,This interrupt cause is activated (HW sets the field to '1') when the pseudo random number generator has generated a data value." "0,1"
|
|
bitfld.long 0x0 3. "TR_DATA_AVAILABLE,This interrupt cause is activated (HW sets the field to '1') when the true random number generator has generated a data value of the specified bit size." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TR_INITIALIZED,This interrupt cause is activated (HW sets the field to '1') when the true random number generator is initialized." "0,1"
|
|
bitfld.long 0x0 1. "INSTR_FF_OVERFLOW,This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO overflows (an attempt is made to write to a full FIFO)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "INSTR_FF_LEVEL,This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO event is activated." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x104++0x3
|
|
line.long 0x0 "INTR_SET,Interrupt set register"
|
|
bitfld.long 0x0 21. "INSTR_DEV_KEY_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 20. "TR_RC_DETECT_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TR_AP_DETECT_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 18. "BUS_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "INSTR_CC_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 16. "INSTR_OPC_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PR_DATA_AVAILABLE,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 3. "TR_DATA_AVAILABLE,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TR_INITIALIZED,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 1. "INSTR_FF_OVERFLOW,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "INSTR_FF_LEVEL,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x104++0x3
|
|
line.long 0x0 "INTR_SET,Interrupt set register"
|
|
bitfld.long 0x0 21. "INSTR_DEV_KEY_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 20. "TR_RC_DETECT_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TR_AP_DETECT_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 18. "BUS_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "INSTR_CC_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 16. "INSTR_OPC_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PR_DATA_AVAILABLE,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 3. "TR_DATA_AVAILABLE,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TR_INITIALIZED,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 1. "INSTR_FF_OVERFLOW,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "INSTR_FF_LEVEL,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x0 21. "INSTR_DEV_KEY_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 20. "TR_RC_DETECT_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TR_AP_DETECT_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 18. "BUS_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "INSTR_CC_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 16. "INSTR_OPC_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PR_DATA_AVAILABLE,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 3. "TR_DATA_AVAILABLE,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TR_INITIALIZED,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 1. "INSTR_FF_OVERFLOW,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "INSTR_FF_LEVEL,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x0 21. "INSTR_DEV_KEY_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 20. "TR_RC_DETECT_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TR_AP_DETECT_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 18. "BUS_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "INSTR_CC_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 16. "INSTR_OPC_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PR_DATA_AVAILABLE,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 3. "TR_DATA_AVAILABLE,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TR_INITIALIZED,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x0 1. "INSTR_FF_OVERFLOW,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "INSTR_FF_LEVEL,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
rgroup.long 0x10C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x0 21. "INSTR_DEV_KEY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 20. "TR_RC_DETECT_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TR_AP_DETECT_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 18. "BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "INSTR_CC_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 16. "INSTR_OPC_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PR_DATA_AVAILABLE,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 3. "TR_DATA_AVAILABLE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TR_INITIALIZED,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 1. "INSTR_FF_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "INSTR_FF_LEVEL,Logical and of corresponding request and mask bits." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
rgroup.long 0x10C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x0 21. "INSTR_DEV_KEY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 20. "TR_RC_DETECT_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TR_AP_DETECT_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 18. "BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "INSTR_CC_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 16. "INSTR_OPC_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PR_DATA_AVAILABLE,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 3. "TR_DATA_AVAILABLE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TR_INITIALIZED,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 1. "INSTR_FF_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "INSTR_FF_LEVEL,Logical and of corresponding request and mask bits." "0,1"
|
|
endif
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "PR_LFSR_CTL0,Pseudo random LFSR control 0"
|
|
hexmask.long 0x0 0.--31. 1. "LFSR32,State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. This register needs to be initialized by SW. The initialization value should be different from '0'."
|
|
line.long 0x4 "PR_LFSR_CTL1,Pseudo random LFSR control 1"
|
|
hexmask.long 0x4 0.--30. 1. "LFSR31,State of a 31-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0."
|
|
line.long 0x8 "PR_LFSR_CTL2,Pseudo random LFSR control 2"
|
|
hexmask.long 0x8 0.--28. 1. "LFSR29,State of a 29-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0."
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x20C++0x3
|
|
line.long 0x0 "PR_MAX_CTL,Pseudo random maximum control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Maximum value of to be generated random number"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x20C++0x3
|
|
line.long 0x0 "PR_MAX_CTL,Pseudo random maximum control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Maximum value of to be generated random number"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x210++0x3
|
|
line.long 0x0 "PR_CMD,Pseudo random command"
|
|
bitfld.long 0x0 0. "START,Pseudo random command. On a generated number HW sets this field to '0' and sets INTR.PR_DATA_AVAILABLE to '1." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x210++0x3
|
|
line.long 0x0 "PR_CMD,Pseudo random command"
|
|
bitfld.long 0x0 0. "START,Pseudo random command. On a generated number HW sets this field to '0' and sets INTR.PR_DATA_AVAILABLE to '1." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x218++0x3
|
|
line.long 0x0 "PR_RESULT,Pseudo random result"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Result of a pseudo random number generation operation. The resulting value DATA is in the range [0 PR_MAX_CTL.DATA32]. The PR_DATA_AVAILABLE interrupt cause is activated when the number is generated."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x218++0x3
|
|
line.long 0x0 "PR_RESULT,Pseudo random result"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Result of a pseudo random number generation operation. The resulting value DATA is in the range [0 PR_MAX_CTL.DATA32]. The PR_DATA_AVAILABLE interrupt cause is activated when the number is generated."
|
|
endif
|
|
group.long 0x280++0x7
|
|
line.long 0x0 "TR_CTL0,True random control 0"
|
|
bitfld.long 0x0 29. "STOP_ON_RC_DETECT,Specifies if TRNG functionality is stopped on a repetition count test detection (when HW sets INTR.TR_RC_DETECT to '1'):" "0: Functionality is NOT stopped,1: Functionality is stopped"
|
|
bitfld.long 0x0 28. "STOP_ON_AP_DETECT,Specifies if TRNG functionality is stopped on an adaptive proportion test detection (when HW sets INTR.TR_AP_DETECT to '1'):" "0: Functionality is NOT stopped,1: Functionality is stopped"
|
|
newline
|
|
bitfld.long 0x0 24. "VON_NEUMANN_CORR,Specifies if the 'von Neumann corrector' is disabled or enabled:" "0: no bit is produced,1: '0' bit is produced"
|
|
hexmask.long.byte 0x0 16.--23. 1. "INIT_DELAY,Specifies an initialization delay: number of removed/dropped samples before reduced bits are generated. This field should be programmed in the range [1 255]. After starting the oscillators at least the first 2 samples should be.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RED_CLOCK_DIV,Specifies the clock divider that is used to produce reduced bits."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SAMPLE_CLOCK_DIV,Specifies the clock divider that is used to sample oscillator data. This clock divider is wrt. 'clk_sys'."
|
|
line.long 0x4 "TR_CTL1,True random control 1"
|
|
bitfld.long 0x4 5. "FIRO31_EN,FW sets this field to '1' to enable the programmable Fibonacci ring oscillator with up to 31 inverters. The TR_FIRO_CTL register specifies the programmable polynomial." "0,1"
|
|
bitfld.long 0x4 4. "FIRO15_EN,FW sets this field to '1' to enable the fixed Fibonacci ring oscillator with 15 inverters." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "GARO31_EN,FW sets this field to '1' to enable the programmable Galois ring oscillator with up to 31 inverters. The TR_GARO_CTL register specifies the programmable polynomial." "0,1"
|
|
bitfld.long 0x4 2. "GARO15_EN,FW sets this field to '1' to enable the fixed Galois ring oscillator with 15 inverters." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RO15_EN,FW sets this field to '1' to enable the ring oscillator with 15 inverters." "0,1"
|
|
bitfld.long 0x4 0. "RO11_EN,FW sets this field to '1' to enable the ring oscillator with 11 inverters." "0,1"
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x288++0x3
|
|
line.long 0x0 "TR_CTL2,True random control 2"
|
|
hexmask.long.byte 0x0 0.--5. 1. "SIZE,Bit size of generated random number in TR_RESULT. Legal range is in [0 32]."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x288++0x3
|
|
line.long 0x0 "TR_CTL2,True random control 2"
|
|
hexmask.long.byte 0x0 0.--5. 1. "SIZE,Bit size of generated random number in TR_RESULT. Legal range is in [0 32]."
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
rgroup.long 0x28C++0x3
|
|
line.long 0x0 "TR_STATUS,True random status"
|
|
bitfld.long 0x0 0. "INITIALIZED,Reflects the state of the true random number generator:" "0: Not initialized,1: Initialized"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
rgroup.long 0x28C++0x3
|
|
line.long 0x0 "TR_STATUS,True random status"
|
|
bitfld.long 0x0 0. "INITIALIZED,Reflects the state of the true random number generator:" "0: Not initialized,1: Initialized"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "TR_CMD,True random command"
|
|
bitfld.long 0x0 0. "START,True random command. On completion of the command HW sets this field to '0' and sets INTR.TR_DATA_AVAILABLE to '1 when:" "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "TR_CMD,True random command"
|
|
bitfld.long 0x0 0. "START,True random command. On completion of the command HW sets this field to '0' and sets INTR.TR_DATA_AVAILABLE to '1 when:" "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x298++0x3
|
|
line.long 0x0 "TR_RESULT,True random result"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Generated true random number. HW generates the number in the least significant bit positions (TR_CTL2.SIZE) of this field. The TR_DATA_AVAILABLE interrupt cause is activated when the number is generated."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x298++0x3
|
|
line.long 0x0 "TR_RESULT,True random result"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Generated true random number. HW generates the number in the least significant bit positions (TR_CTL2.SIZE) of this field. The TR_DATA_AVAILABLE interrupt cause is activated when the number is generated."
|
|
endif
|
|
group.long 0x2A0++0x7
|
|
line.long 0x0 "TR_GARO_CTL,True random GARO control"
|
|
hexmask.long 0x0 0.--30. 1. "POLYNOMIAL31,Polynomial for programmable Galois ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the.."
|
|
line.long 0x4 "TR_FIRO_CTL,True random FIRO control"
|
|
hexmask.long 0x4 0.--30. 1. "POLYNOMIAL31,Polynomial for programmable Fibonacci ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain.."
|
|
group.long 0x2C0++0x3
|
|
line.long 0x0 "TR_MON_CTL,True random monitor control"
|
|
bitfld.long 0x0 0.--1. "BITSTREAM_SEL,Selection of the bitstream:" "0: DAS bitstream,1: RED bitstream,2: TR bitstream,3: Undefined"
|
|
group.long 0x2C8++0x3
|
|
line.long 0x0 "TR_MON_CMD,True random monitor command"
|
|
bitfld.long 0x0 1. "START_RC,Repetition count (RC) test enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "START_AP,Adaptive proportion (AP) test enable:" "0: Stopped,1: Started"
|
|
group.long 0x2D0++0x3
|
|
line.long 0x0 "TR_MON_RC_CTL,True random monitor RC control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CUTOFF_COUNT8,Cutoff count (legal range is [1 255]):"
|
|
rgroup.long 0x2D8++0x7
|
|
line.long 0x0 "TR_MON_RC_STATUS0,True random monitor RC status 0"
|
|
bitfld.long 0x0 0. "BIT,Current active bit value:" "0: '0',1: '1'"
|
|
line.long 0x4 "TR_MON_RC_STATUS1,True random monitor RC status 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "REP_COUNT,Number of repetitions of the current active bit counter:"
|
|
group.long 0x2E0++0x3
|
|
line.long 0x0 "TR_MON_AP_CTL,True random monitor AP control"
|
|
hexmask.long.word 0x0 16.--31. 1. "WINDOW_SIZE,Window size (minus 1) :"
|
|
hexmask.long.word 0x0 0.--15. 1. "CUTOFF_COUNT16,Cutoff count (legal range is [1 65535])."
|
|
rgroup.long 0x2E8++0x7
|
|
line.long 0x0 "TR_MON_AP_STATUS0,True random monitor AP status 0"
|
|
bitfld.long 0x0 0. "BIT,Current active bit value:" "0: '0',1: '1'"
|
|
line.long 0x4 "TR_MON_AP_STATUS1,True random monitor AP status 1"
|
|
hexmask.long.word 0x4 16.--31. 1. "WINDOW_INDEX,Counter to keep track of the current index in the window (counts from '0' to TR_MON_AP_CTL.WINDOW_SIZE)."
|
|
hexmask.long.word 0x4 0.--15. 1. "OCC_COUNT,Number of occurrences of the current active bit counter:"
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "BUSY,Reflects the state of the IP:" "0: Idle/no busy,1: Busy:"
|
|
group.long 0x1040++0x3
|
|
line.long 0x0 "INSTR_FF_CTL,Instruction FIFO control"
|
|
bitfld.long 0x0 17. "BLOCK,This field specifies the behavior when an instruction is written to a full FIFO (INSTR_FIFO_WR MMIO register):" "0: The write is ignored/dropped and the INTR,1: The write is blocked"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the instruction FIFO is cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EVENT_LEVEL,Event level. When the number of entries in the instruction FIFO is less than the amount of this field an event is generated:" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1044++0x3
|
|
line.long 0x0 "INSTR_FF_STATUS,Instruction FIFO status"
|
|
bitfld.long 0x0 16. "EVENT,Instruction FIFO event." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "USED,Number of instructions in the instruction FIFO. The value of this field ranges from 0 to 8."
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INSTR_FF_WR,Instruction FIFO write"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Instruction or instruction operand data that is written to the instruction FIFO."
|
|
rgroup.long 0x10C0++0x3
|
|
line.long 0x0 "LOAD0_FF_STATUS,Load 0 FIFO status"
|
|
bitfld.long 0x0 31. "BUSY,Reflects the state of the FIFO:" "0: FIFO load engine is idle and a new FIFO..,1: FIFO load engine is busy and NO new FIFO.."
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED5,Number of Bytes in the FIFO. The value of this field is in the range [0 19]."
|
|
rgroup.long 0x10D0++0x3
|
|
line.long 0x0 "LOAD1_FF_STATUS,Load 1 FIFO status"
|
|
bitfld.long 0x0 31. "BUSY,See LOAD1_FF_STATUS.BUSY." "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED5,See LOAD1_FF_STATUS.USED."
|
|
rgroup.long 0x10F0++0x3
|
|
line.long 0x0 "STORE_FF_STATUS,Store FIFO status"
|
|
bitfld.long 0x0 31. "BUSY,Reflects the state of the FIFO:" "0: FIFO store engine is idle and a new FIFO..,1: FIFO store engine is busy and NO new FIFO.."
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED5,Number of Bytes in the FIFO. The value of this field is in the range [0 16]."
|
|
group.long 0x1100++0x3
|
|
line.long 0x0 "AES_CTL,AES control"
|
|
bitfld.long 0x0 0.--1. "KEY_SIZE,AES key size:" "0: 128-bit key,1: 192-bit key,2: 256-bit key,3: Undefined"
|
|
group.long 0x1180++0x3
|
|
line.long 0x0 "RESULT,Result"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,BLOCK_CMP operation (DATA[0]):"
|
|
group.long 0x1400++0x3
|
|
line.long 0x0 "CRC_CTL,CRC control"
|
|
bitfld.long 0x0 8. "REM_REVERSE,Specifies whether the remainder is bit reversed (reversal is performed after XORing):" "0: No,1: Yes"
|
|
bitfld.long 0x0 0. "DATA_REVERSE,Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):" "0: Most significant bit,1: Least significant bit"
|
|
group.long 0x1410++0x3
|
|
line.long 0x0 "CRC_DATA_CTL,CRC data control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_XOR,Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal."
|
|
group.long 0x1420++0x3
|
|
line.long 0x0 "CRC_POL_CTL,CRC polynomial control"
|
|
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less.."
|
|
group.long 0x1440++0x3
|
|
line.long 0x0 "CRC_REM_CTL,CRC remainder control"
|
|
hexmask.long 0x0 0.--31. 1. "REM_XOR,Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal."
|
|
rgroup.long 0x1448++0x3
|
|
line.long 0x0 "CRC_REM_RESULT,CRC remainder result"
|
|
hexmask.long 0x0 0.--31. 1. "REM,Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:"
|
|
group.long 0x1480++0xB
|
|
line.long 0x0 "VU_CTL0,Vector unit control 0"
|
|
bitfld.long 0x0 0. "ALWAYS_EXECUTE,Specifies if a conditional instruction is executed or not when its condition code evaluates to false/'0'." "0: The instruction is NOT executed,1: The instruction is executed"
|
|
line.long 0x4 "VU_CTL1,Vector unit control 1"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "ADDR24,Specifies the memory address for the vector unit operand memory region. The register-file registers provide 13-bit word offsets within this memory region. Given ADDR[31:8] VU_VTL2.MASK[14:8] and a 13-bit word offset offset[14:2] a vector operand.."
|
|
line.long 0x8 "VU_CTL2,Vector unit control 2"
|
|
hexmask.long.byte 0x8 8.--14. 1. "MASK,Specifies the size of the vector operand memory region. Legal values:"
|
|
rgroup.long 0x1490++0x3
|
|
line.long 0x0 "VU_STATUS,Vector unit status"
|
|
bitfld.long 0x0 3. "ONE,STATUS ONE field." "0,1"
|
|
bitfld.long 0x0 2. "ZERO,STATUS ZERO field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EVEN,STATUS EVEN field." "0,1"
|
|
bitfld.long 0x0 0. "CARRY,STATUS CARRY field." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x14C0)++0x3
|
|
line.long 0x0 "VU_RF_DATA[$1],Vector unit register-file"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Vector unit register-file data. A register-file register has the following layout:"
|
|
repeat.end
|
|
group.long 0x2000++0x7
|
|
line.long 0x0 "DEV_KEY_ADDR0_CTL,Device key address 0 control"
|
|
bitfld.long 0x0 31. "VALID,Specifies if the address in the associated DEV_KEY_ADDR0 is valid:" "0: Address not valid,1: Address valid"
|
|
line.long 0x4 "DEV_KEY_ADDR0,Device key address 0"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR32,Specifies the memory address of the device key in memory. A LOAD_DEV_KEY instruction uses this address to load a device key from memory into the IP register buffer blocks 4 and 5."
|
|
group.long 0x2020++0x7
|
|
line.long 0x0 "DEV_KEY_ADDR1_CTL,Device key address 1 control"
|
|
bitfld.long 0x0 31. "VALID,See DEV_KEY_ADDR0_CTL." "0,1"
|
|
line.long 0x4 "DEV_KEY_ADDR1,Device key address 1 control"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR32,See DEV_KEY_ADDR0."
|
|
rgroup.long 0x2080++0x3
|
|
line.long 0x0 "DEV_KEY_STATUS,Device key status"
|
|
bitfld.long 0x0 0. "LOADED,Specifies if a device key is present in the IP register buffer blocks 4 and 5." "0,1"
|
|
group.long 0x2100++0x3
|
|
line.long 0x0 "DEV_KEY_CTL0,Device key control 0"
|
|
bitfld.long 0x0 0. "ALLOWED,Specifies if a LOAD_DEV_KEY instruction is allowed to use the device key in memory:" "0: Not allowed,1: Allowed"
|
|
group.long 0x2120++0x3
|
|
line.long 0x0 "DEV_KEY_CTL1,Device key control 1"
|
|
bitfld.long 0x0 0. "ALLOWED,See DEV_KEY_CTL0." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "BUSY,Reflects the state of the IP:" "0: Idle/no busy,1: Busy:"
|
|
group.long 0x1040++0x3
|
|
line.long 0x0 "INSTR_FF_CTL,Instruction FIFO control"
|
|
bitfld.long 0x0 17. "BLOCK,This field specifies the behavior when an instruction is written to a full FIFO (INSTR_FIFO_WR MMIO register):" "0: The write is ignored/dropped and the INTR,1: The write is blocked"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the instruction FIFO is cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EVENT_LEVEL,Event level. When the number of entries in the instruction FIFO is less than the amount of this field an event is generated:" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1044++0x3
|
|
line.long 0x0 "INSTR_FF_STATUS,Instruction FIFO status"
|
|
bitfld.long 0x0 16. "EVENT,Instruction FIFO event." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "USED,Number of instructions in the instruction FIFO. The value of this field ranges from 0 to 8."
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INSTR_FF_WR,Instruction FIFO write"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Instruction or instruction operand data that is written to the instruction FIFO."
|
|
rgroup.long 0x10C0++0x3
|
|
line.long 0x0 "LOAD0_FF_STATUS,Load 0 FIFO status"
|
|
bitfld.long 0x0 31. "BUSY,Reflects the state of the FIFO:" "0: FIFO load engine is idle and a new FIFO..,1: FIFO load engine is busy and NO new FIFO.."
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED5,Number of Bytes in the FIFO. The value of this field is in the range [0 19]."
|
|
rgroup.long 0x10D0++0x3
|
|
line.long 0x0 "LOAD1_FF_STATUS,Load 1 FIFO status"
|
|
bitfld.long 0x0 31. "BUSY,See LOAD1_FF_STATUS.BUSY." "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED5,See LOAD1_FF_STATUS.USED."
|
|
rgroup.long 0x10F0++0x3
|
|
line.long 0x0 "STORE_FF_STATUS,Store FIFO status"
|
|
bitfld.long 0x0 31. "BUSY,Reflects the state of the FIFO:" "0: FIFO store engine is idle and a new FIFO..,1: FIFO store engine is busy and NO new FIFO.."
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED5,Number of Bytes in the FIFO. The value of this field is in the range [0 16]."
|
|
group.long 0x1100++0x3
|
|
line.long 0x0 "AES_CTL,AES control"
|
|
bitfld.long 0x0 0.--1. "KEY_SIZE,AES key size:" "0: 128-bit key,1: 192-bit key,2: 256-bit key,3: Undefined"
|
|
group.long 0x1180++0x3
|
|
line.long 0x0 "RESULT,Result"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,BLOCK_CMP operation (DATA[0]):"
|
|
group.long 0x1400++0x3
|
|
line.long 0x0 "CRC_CTL,CRC control"
|
|
bitfld.long 0x0 8. "REM_REVERSE,Specifies whether the remainder is bit reversed (reversal is performed after XORing):" "0: No,1: Yes"
|
|
bitfld.long 0x0 0. "DATA_REVERSE,Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):" "0: Most significant bit,1: Least significant bit"
|
|
group.long 0x1410++0x3
|
|
line.long 0x0 "CRC_DATA_CTL,CRC data control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_XOR,Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal."
|
|
group.long 0x1420++0x3
|
|
line.long 0x0 "CRC_POL_CTL,CRC polynomial control"
|
|
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less.."
|
|
group.long 0x1440++0x3
|
|
line.long 0x0 "CRC_REM_CTL,CRC remainder control"
|
|
hexmask.long 0x0 0.--31. 1. "REM_XOR,Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal."
|
|
rgroup.long 0x1448++0x3
|
|
line.long 0x0 "CRC_REM_RESULT,CRC remainder result"
|
|
hexmask.long 0x0 0.--31. 1. "REM,Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:"
|
|
group.long 0x1480++0xB
|
|
line.long 0x0 "VU_CTL0,Vector unit control 0"
|
|
bitfld.long 0x0 0. "ALWAYS_EXECUTE,Specifies if a conditional instruction is executed or not when its condition code evaluates to false/'0'." "0: The instruction is NOT executed,1: The instruction is executed"
|
|
line.long 0x4 "VU_CTL1,Vector unit control 1"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "ADDR24,Specifies the memory address for the vector unit operand memory region. The register-file registers provide 13-bit word offsets within this memory region. Given ADDR[31:8] VU_VTL2.MASK[14:8] and a 13-bit word offset offset[14:2] a vector operand.."
|
|
line.long 0x8 "VU_CTL2,Vector unit control 2"
|
|
hexmask.long.byte 0x8 8.--14. 1. "MASK,Specifies the size of the vector operand memory region. Legal values:"
|
|
rgroup.long 0x1490++0x3
|
|
line.long 0x0 "VU_STATUS,Vector unit status"
|
|
bitfld.long 0x0 3. "ONE,STATUS ONE field." "0,1"
|
|
bitfld.long 0x0 2. "ZERO,STATUS ZERO field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EVEN,STATUS EVEN field." "0,1"
|
|
bitfld.long 0x0 0. "CARRY,STATUS CARRY field." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x14C0)++0x3
|
|
line.long 0x0 "VU_RF_DATA[$1],Vector unit register-file"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Vector unit register-file data. A register-file register has the following layout:"
|
|
repeat.end
|
|
group.long 0x2000++0x7
|
|
line.long 0x0 "DEV_KEY_ADDR0_CTL,Device key address 0 control"
|
|
bitfld.long 0x0 31. "VALID,Specifies if the address in the associated DEV_KEY_ADDR0 is valid:" "0: Address not valid,1: Address valid"
|
|
line.long 0x4 "DEV_KEY_ADDR0,Device key address 0"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR32,Specifies the memory address of the device key in memory. A LOAD_DEV_KEY instruction uses this address to load a device key from memory into the IP register buffer blocks 4 and 5."
|
|
group.long 0x2020++0x7
|
|
line.long 0x0 "DEV_KEY_ADDR1_CTL,Device key address 1 control"
|
|
bitfld.long 0x0 31. "VALID,See DEV_KEY_ADDR0_CTL." "0,1"
|
|
line.long 0x4 "DEV_KEY_ADDR1,Device key address 1 control"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR32,See DEV_KEY_ADDR0."
|
|
rgroup.long 0x2080++0x3
|
|
line.long 0x0 "DEV_KEY_STATUS,Device key status"
|
|
bitfld.long 0x0 0. "LOADED,Specifies if a device key is present in the IP register buffer blocks 4 and 5." "0,1"
|
|
group.long 0x2100++0x3
|
|
line.long 0x0 "DEV_KEY_CTL0,Device key control 0"
|
|
bitfld.long 0x0 0. "ALLOWED,Specifies if a LOAD_DEV_KEY instruction is allowed to use the device key in memory:" "0: Not allowed,1: Allowed"
|
|
group.long 0x2120++0x3
|
|
line.long 0x0 "DEV_KEY_CTL1,Device key control 1"
|
|
bitfld.long 0x0 0. "ALLOWED,See DEV_KEY_CTL0." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "BUSY,Reflects the state of the IP:" "0: Idle/no busy,1: Busy:"
|
|
group.long 0x1040++0x3
|
|
line.long 0x0 "INSTR_FF_CTL,Instruction FIFO control"
|
|
bitfld.long 0x0 17. "BLOCK,This field specifies the behavior when an instruction is written to a full FIFO (INSTR_FIFO_WR MMIO register):" "0: The write is ignored/dropped and the INTR,1: The write is blocked"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the instruction FIFO is cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EVENT_LEVEL,Event level. When the number of entries in the instruction FIFO is less than the amount of this field an event is generated:" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1044++0x3
|
|
line.long 0x0 "INSTR_FF_STATUS,Instruction FIFO status"
|
|
bitfld.long 0x0 16. "EVENT,Instruction FIFO event." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "USED,Number of instructions in the instruction FIFO. The value of this field ranges from 0 to 8."
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INSTR_FF_WR,Instruction FIFO write"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Instruction or instruction operand data that is written to the instruction FIFO."
|
|
rgroup.long 0x10C0++0x3
|
|
line.long 0x0 "LOAD0_FF_STATUS,Load 0 FIFO status"
|
|
bitfld.long 0x0 31. "BUSY,Reflects the state of the FIFO:" "0: FIFO load engine is idle and a new FIFO..,1: FIFO load engine is busy and NO new FIFO.."
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED5,Number of Bytes in the FIFO. The value of this field is in the range [0 19]."
|
|
rgroup.long 0x10D0++0x3
|
|
line.long 0x0 "LOAD1_FF_STATUS,Load 1 FIFO status"
|
|
bitfld.long 0x0 31. "BUSY,See LOAD1_FF_STATUS.BUSY." "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED5,See LOAD1_FF_STATUS.USED."
|
|
rgroup.long 0x10F0++0x3
|
|
line.long 0x0 "STORE_FF_STATUS,Store FIFO status"
|
|
bitfld.long 0x0 31. "BUSY,Reflects the state of the FIFO:" "0: FIFO store engine is idle and a new FIFO..,1: FIFO store engine is busy and NO new FIFO.."
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED5,Number of Bytes in the FIFO. The value of this field is in the range [0 16]."
|
|
group.long 0x1100++0x3
|
|
line.long 0x0 "AES_CTL,AES control"
|
|
bitfld.long 0x0 0.--1. "KEY_SIZE,AES key size:" "0: 128-bit key,1: 192-bit key,2: 256-bit key,3: Undefined"
|
|
group.long 0x1180++0x3
|
|
line.long 0x0 "RESULT,Result"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,BLOCK_CMP operation (DATA[0]):"
|
|
group.long 0x1400++0x3
|
|
line.long 0x0 "CRC_CTL,CRC control"
|
|
bitfld.long 0x0 8. "REM_REVERSE,Specifies whether the remainder is bit reversed (reversal is performed after XORing):" "0: No,1: Yes"
|
|
bitfld.long 0x0 0. "DATA_REVERSE,Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):" "0: Most significant bit,1: Least significant bit"
|
|
group.long 0x1410++0x3
|
|
line.long 0x0 "CRC_DATA_CTL,CRC data control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_XOR,Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal."
|
|
group.long 0x1420++0x3
|
|
line.long 0x0 "CRC_POL_CTL,CRC polynomial control"
|
|
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less.."
|
|
group.long 0x1440++0x3
|
|
line.long 0x0 "CRC_REM_CTL,CRC remainder control"
|
|
hexmask.long 0x0 0.--31. 1. "REM_XOR,Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal."
|
|
rgroup.long 0x1448++0x3
|
|
line.long 0x0 "CRC_REM_RESULT,CRC remainder result"
|
|
hexmask.long 0x0 0.--31. 1. "REM,Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:"
|
|
group.long 0x1480++0xB
|
|
line.long 0x0 "VU_CTL0,Vector unit control 0"
|
|
bitfld.long 0x0 0. "ALWAYS_EXECUTE,Specifies if a conditional instruction is executed or not when its condition code evaluates to false/'0'." "0: The instruction is NOT executed,1: The instruction is executed"
|
|
line.long 0x4 "VU_CTL1,Vector unit control 1"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "ADDR24,Specifies the memory address for the vector unit operand memory region. The register-file registers provide 13-bit word offsets within this memory region. Given ADDR[31:8] VU_VTL2.MASK[14:8] and a 13-bit word offset offset[14:2] a vector operand.."
|
|
line.long 0x8 "VU_CTL2,Vector unit control 2"
|
|
hexmask.long.byte 0x8 8.--14. 1. "MASK,Specifies the size of the vector operand memory region. Legal values:"
|
|
rgroup.long 0x1490++0x3
|
|
line.long 0x0 "VU_STATUS,Vector unit status"
|
|
bitfld.long 0x0 3. "ONE,STATUS ONE field." "0,1"
|
|
bitfld.long 0x0 2. "ZERO,STATUS ZERO field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EVEN,STATUS EVEN field." "0,1"
|
|
bitfld.long 0x0 0. "CARRY,STATUS CARRY field." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x14C0)++0x3
|
|
line.long 0x0 "VU_RF_DATA[$1],Vector unit register-file"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Vector unit register-file data. A register-file register has the following layout:"
|
|
repeat.end
|
|
group.long 0x2000++0x7
|
|
line.long 0x0 "DEV_KEY_ADDR0_CTL,Device key address 0 control"
|
|
bitfld.long 0x0 31. "VALID,Specifies if the address in the associated DEV_KEY_ADDR0 is valid:" "0: Address not valid,1: Address valid"
|
|
line.long 0x4 "DEV_KEY_ADDR0,Device key address 0"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR32,Specifies the memory address of the device key in memory. A LOAD_DEV_KEY instruction uses this address to load a device key from memory into the IP register buffer blocks 4 and 5."
|
|
group.long 0x2020++0x7
|
|
line.long 0x0 "DEV_KEY_ADDR1_CTL,Device key address 1 control"
|
|
bitfld.long 0x0 31. "VALID,See DEV_KEY_ADDR0_CTL." "0,1"
|
|
line.long 0x4 "DEV_KEY_ADDR1,Device key address 1 control"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR32,See DEV_KEY_ADDR0."
|
|
rgroup.long 0x2080++0x3
|
|
line.long 0x0 "DEV_KEY_STATUS,Device key status"
|
|
bitfld.long 0x0 0. "LOADED,Specifies if a device key is present in the IP register buffer blocks 4 and 5." "0,1"
|
|
group.long 0x2100++0x3
|
|
line.long 0x0 "DEV_KEY_CTL0,Device key control 0"
|
|
bitfld.long 0x0 0. "ALLOWED,Specifies if a LOAD_DEV_KEY instruction is allowed to use the device key in memory:" "0: Not allowed,1: Allowed"
|
|
group.long 0x2120++0x3
|
|
line.long 0x0 "DEV_KEY_CTL1,Device key control 1"
|
|
bitfld.long 0x0 0. "ALLOWED,See DEV_KEY_CTL0." "0,1"
|
|
endif
|
|
tree.end
|
|
tree "CSD (Capsense Controller)"
|
|
base ad:0x40360000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CONFIG,Configuration and Control"
|
|
bitfld.long 0x0 31. "ENABLE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LP_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DSI_SENSE_EN,DSI_SENSE_EN = 1-> sensor clock is driven directly by DSI" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "SAMPLE_SYNC,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DSI_SAMPLE_EN,DSI_SAMPLE_EN = 1 -> COUNTER will count the samples generated by DSI" "0: COUNTER will count the samples generated by CSD..,1: COUNTER will count the samples generated by DSI"
|
|
newline
|
|
bitfld.long 0x0 24. "DSI_COUNT_SEL,N/A" "0: depending on the dsi_count_val_sel input either..,1: output ADC_RES.VIN_CNT on the dsi_count bus"
|
|
newline
|
|
bitfld.long 0x0 19. "CSX_DUAL_CNT,N/A" "0: Use one counter for both phases (source and sink).,1: Use two counters separate count for when.."
|
|
newline
|
|
bitfld.long 0x0 18. "MUTUAL_CAP,N/A" "0: Self-cap mode (configure sense line as CSD_SENSE),1: Mutual-cap mode (configure Tx line as CSD_SENSE.."
|
|
newline
|
|
bitfld.long 0x0 17. "FULL_WAVE,N/A" "0: Half Wave mode (normal). In this mode the..,1: Full Wave mode. In this mode the comparator.."
|
|
newline
|
|
bitfld.long 0x0 12. "SENSE_EN,Enables the sensor and shield clocks CSD modulator output and turns on the IDAC compensation current as selected by CSD_IDAC." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "SHIELD_DELAY,Configures the delay between shield clock and sensor clock" "0: Delay line is off csd_shield=csd_sense,1: Introduces a 5ns delay (typ),2: Introduces a 10ns delay (typ),3: Introduces a 20ns delay (typ)"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--8. 1. "FILTER_DELAY,Enables the digital filtering on the CSD comparator"
|
|
newline
|
|
bitfld.long 0x0 0. "IREF_SEL,N/A" "0: select SRSS Iref (default),1: select PASS.AREF Iref only available if PASS IP.."
|
|
line.long 0x4 "SPARE,Spare MMIO"
|
|
hexmask.long.byte 0x4 0.--3. 1. "SPARE,Spare MMIO"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "STATUS,Status Register"
|
|
bitfld.long 0x0 3. "CSDCMP_OUT,Only for Debug/test purpose the output status of CSD modulator can be read by CPU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "HSCMP_OUT,Only for Debug/test purpose the output status of CSD comparator can be read by CPU" "0: Vin < Vref,1: Vin > Vref"
|
|
newline
|
|
bitfld.long 0x0 1. "CSD_SENSE,Only for Debug/test purpose this internal signal (sensor clock) status can be read by CPU" "0,1"
|
|
line.long 0x4 "STAT_SEQ,Current Sequencer status"
|
|
bitfld.long 0x4 16.--18. "ADC_STATE,ADC sequencer state (only relevant after SEQ_STATE has reached SAMPLE_NORM and ADC sequencer has started)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "SEQ_STATE,CSD sequencer state" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "STAT_CNTS,Current status counts"
|
|
hexmask.long.word 0x8 0.--15. 1. "NUM_CONV,Current number of conversions remaining when in Sample_* states (note that in AutoZero* states the same down counter is reused to count the cycles)"
|
|
line.long 0xC "STAT_HCNT,Current count of the HSCMP counter"
|
|
hexmask.long.word 0xC 0.--15. 1. "CNT,Current value of HSCMP counter"
|
|
rgroup.long 0xD0++0x7
|
|
line.long 0x0 "RESULT_VAL1,Result CSD/CSX accumulation counter value 1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BAD_CONVS,Number of 'bad' conversion for which the CSD comparator did not trigger within the normal time window either because Vref was not crossed at all or if the Vref was already crossed before the window started. This counter is reset when the.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VALUE,Accumulated counter value for this result. In case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt) this counter counts when csd_sense is high."
|
|
line.long 0x4 "RESULT_VAL2,Result CSX accumulation counter value 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALUE,Only used in case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt) this counter counts when csd_sense is low."
|
|
rgroup.long 0xE0++0x3
|
|
line.long 0x0 "ADC_RES,ADC measurement"
|
|
bitfld.long 0x0 31. "ADC_ABORT,This flag is set when the ADC sequencer was aborted before tripping HSCMP." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "ADC_OVERFLOW,This flag is set when the ADC counter overflows. This is an indication to the firmware that the IDACB current level is too low." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "HSCMP_POL,Polarity used for IDACB for this last ADC result 0= source 1= sink" "0: source,1: sink"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VIN_CNT,Count to source/sink Cref1 + Cref2 from Vin to Vrefhi."
|
|
group.long 0xF0++0xB
|
|
line.long 0x0 "INTR,CSD Interrupt Request Register"
|
|
bitfld.long 0x0 8. "ADC_RES,ADC Result ready" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "INIT,Coarse initialization complete or Sample initialization complete (the latter is typically ignored)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SAMPLE,A normal sample is complete" "0,1"
|
|
line.long 0x4 "INTR_SET,CSD Interrupt set register"
|
|
bitfld.long 0x4 8. "ADC_RES,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "INIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "SAMPLE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,CSD Interrupt mask register"
|
|
bitfld.long 0x8 8. "ADC_RES,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "INIT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "SAMPLE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x0 "INTR_MASKED,CSD Interrupt masked register"
|
|
bitfld.long 0x0 8. "ADC_RES,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "INIT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SAMPLE,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0x180++0xF
|
|
line.long 0x0 "HSCMP,High Speed Comparator configuration"
|
|
bitfld.long 0x0 31. "AZ_EN,Auto-Zero enable allow the Sequencer to Auto-Zero this component" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "HSCMP_INVERT,Invert the HSCMP output before it is used to control switches and the CSD sequencer. This bit does not affect the ADC sequencer or the STATUS.HSCMP_OUT" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "HSCMP_EN,High Speed Comparator enable" "0: Disable comparator output is zero,1: On regular operation. Note that CONFIG.LP_MODE.."
|
|
line.long 0x4 "AMBUF,Reference Generator configuration"
|
|
bitfld.long 0x4 0.--1. "PWR_MODE,Amux buffer power level" "0: Disable buffer,1: On normal or low power level depending on..,2: On high or low power level depending on..,?"
|
|
line.long 0x8 "REFGEN,Reference Generator configuration"
|
|
bitfld.long 0x8 23. "VREFLO_INT,Ouput the resistor string tap either to Vreflo (0) or Vreflo_int (1)." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--20. 1. "VREFLO_SEL,Select resistor string tap for Vreflo/Vreflo_int 0= minimum vout 31= maximum vout = vrefhi (only works if the resistor string is enabled; RES_EN=1)"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--12. 1. "GAIN,Select resistor string tap for feedback 0= minimum vout 31= maximum vout = vrefhi -> gain=1 (only works if the resistor string is enabled; RES_EN=1)"
|
|
newline
|
|
bitfld.long 0x8 6. "RES_EN,Resistor string enable; 0= open switch on top of the resistor string (Vreflo=Vssa)" "0: open switch on top of the resistor string,?"
|
|
newline
|
|
bitfld.long 0x8 5. "VDDA_EN,Close Vdda switch to top of resistor string (or Vrefhi?)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "BYPASS,Bypass selected input reference unbuffered to Vrefhi" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "REFGEN_EN,Reference Generator Enable" "0: Disable Reference Generator,1: On regular operation. Note that CONFIG.LP_MODE.."
|
|
line.long 0xC "CSDCMP,CSD Comparator configuration"
|
|
bitfld.long 0xC 31. "AZ_EN,Auto-Zero enable allow the Sequencer to Auto-Zero this component" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "FEEDBACK_MODE,This bit controls whether the output directly from the comparator (csdcmp_out) or the flopped version (csdcmp_out_ff) is used. For CSD operation the selected signal controls the IDAC(s) in GP mode the signal goes out on dsi_sample_out." "0: Use feedback from sampling flip-flop (used in..,1: Use feedback from comparator directly (used in.."
|
|
newline
|
|
bitfld.long 0xC 28. "CMP_MODE,Select which signal to output on dsi_sample_out." "0: CSD mode: output the filtered sample signal on..,1: General Purpose mode: output the unfiltered.."
|
|
newline
|
|
bitfld.long 0xC 8.--9. "CMP_PHASE,Select in what phase(s) the comparator is active typically set to match the BAL_MODE of the used IDAC. Note this also determines when a bad conversion is detected namely at the beginning and end of the comparator active phase (also taking.." "0: Comparator is active from start of Phi2 and kept..,1: Comparator is active during Phi1 only. Currently..,2: Comparator is active during Phi2 only. Intended..,3: Comparator is activated at the start of both.."
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bitfld.long 0xC 4.--5. "POLARITY_SEL,Select which IDAC polarity to use to detect CSDCMP triggering" "0: Use idaca_pol (firmware setting with CSX and..,1: Use idacb_pol (firmware setting with optional..,2: Use the expression (csd_sense ? idaca_pol :..,?"
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bitfld.long 0xC 0. "CSDCMP_EN,CSD Comparator Enable" "0: Disable comparator output is zero,1: On regular operation. Note that CONFIG.LP_MODE.."
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group.long 0x1F0++0x3
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line.long 0x0 "SW_RES,Switch Resistance configuration"
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|
bitfld.long 0x0 18.--19. "RES_F2PT,Select resistance for the corresponding switch" "0,1,2,3"
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bitfld.long 0x0 16.--17. "RES_F1PM,Select resistance for the corresponding switch" "0: Low,1: Medium,2: High,3: N/A"
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bitfld.long 0x0 6.--7. "RES_HCBG,Select resistance or low EMI for the corresponding switch" "0,1,2,3"
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bitfld.long 0x0 4.--5. "RES_HCBV,Select resistance or low EMI for the corresponding switch" "0,1,2,3"
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bitfld.long 0x0 2.--3. "RES_HCAG,Select resistance or low EMI for the corresponding switch" "0,1,2,3"
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bitfld.long 0x0 0.--1. "RES_HCAV,Select resistance or low EMI (slow ramp) for the HCAV switch" "0: Low,1: Medium,2: High,3: Low EMI (slow ramp: 3 switches closed by fixed.."
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group.long 0x200++0x7
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line.long 0x0 "SENSE_PERIOD,Sense clock period"
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bitfld.long 0x0 26.--27. "LFSR_BITS,Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period." "0: use 2 bits: range = [-2 1],1: use 3 bits: range = [-4 3],2: use 4 bits: range = [-8 7],3: use 5 bits: range = [-16 15] (default)"
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bitfld.long 0x0 25. "SEL_LFSR_MSB,Use the MSB of configured LSFR size as csd_sense signal. Intended to be used only with bit 8 or 12-bit LFSR size for CSDv1 backward compatibility (PRS). When this bit is set then clock divider dithering is disabled and SENSE_WIDTH is disabled." "0,1"
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bitfld.long 0x0 24. "LFSR_CLEAR,When set forces the LFSR to it's initial state (all ones). This bit is automatically cleared by hardware after the LFSR is cleared which is at the next clk_csd positive edge. This bit should be set whenever this register is written and the.." "0,1"
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hexmask.long.byte 0x0 20.--23. 1. "LFSR_SCALE,Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV. This dithering is disabled when SEL_LSFR_MSB is set."
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bitfld.long 0x0 16.--18. "LFSR_SIZE,Selects the length of the LFSR which determines the LFSR repeat period. LFSR_BITS LSB of the LFSR are used for the clock dithering variation on the base period (was PRS in CSDv1). Whenever the LFSR is used (non zero value in this field) the.." "0: Don't use clock dithering (=spreadspectrum)..,1: 6-bit LFSR (G(x)=X^6 +X^4+X^3+ X+1 period= 63),2: 7-bit LFSR (G(x)=X^7 +X^4+X^3+X^2+1 period= 127),3: 9-bit LFSR (G(x)=X^9 +X^4+X^3+ X+1 period= 511),4: 10-bit LFSR (G(x)=X^10+X^4+X^3+ X+1 period= 1023),5: 8-bit LFSR (G(x)=X^8+X^4+X^3+X^2+1 period= 255),6: 12-bit LFSR (G(x)=X^12+X^7+X^4+X^3+1 period= 4095),?"
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hexmask.long.word 0x0 0.--11. 1. "SENSE_DIV,The length-1 of the Sense modulation 'clock' period in clk_csd cycles. For regular CSD one sense clock cycle = one conversion (=phi1+phi2) ."
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line.long 0x4 "SENSE_DUTY,Sense clock duty cycle"
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bitfld.long 0x4 19. "OVERLAP_PHI2,Same as OVERLAP_PHI1 but for Phi2 (csd_sense=1)." "0,1"
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bitfld.long 0x4 18. "OVERLAP_PHI1,NonOverlap or not for Phi1 (csd_sense=0)." "0: Non-overlap for Phi1,1: 'Overlap'"
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bitfld.long 0x4 16. "SENSE_POL,Polarity of the sense clock" "0: start with low phase,1: start with high phase"
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hexmask.long.word 0x4 0.--11. 1. "SENSE_WIDTH,Defines the length of the first phase of the sense clock in clk_csd cycles."
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group.long 0x280++0xB
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line.long 0x0 "SW_HS_P_SEL,HSCMP Pos input switch Waveform selection"
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bitfld.long 0x0 28. "SW_HMRH,Set corresponding switch" "0,1"
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bitfld.long 0x0 24. "SW_HMCB,Set corresponding switch" "0,1"
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bitfld.long 0x0 20. "SW_HMCA,Set corresponding switch" "0,1"
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bitfld.long 0x0 16. "SW_HMMB,Set corresponding switch" "0,1"
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bitfld.long 0x0 12. "SW_HMMA,Set corresponding switch" "0,1"
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bitfld.long 0x0 8. "SW_HMPS,Set corresponding switch" "0,1"
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bitfld.long 0x0 4. "SW_HMPT,Set corresponding switch" "0,1"
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bitfld.long 0x0 0. "SW_HMPM,Set HMPM switch" "0: static open,1: static closed"
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line.long 0x4 "SW_HS_N_SEL,HSCMP Neg input switch Waveform selection"
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bitfld.long 0x4 28.--30. "SW_HCRL,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 24.--26. "SW_HCRH,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 20. "SW_HCCD,Set corresponding switch" "0,1"
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bitfld.long 0x4 16. "SW_HCCC,Set corresponding switch" "0,1"
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line.long 0x8 "SW_SHIELD_SEL,Shielding switches Waveform selection"
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bitfld.long 0x8 20. "SW_HCCG,Set corresponding switch" "0,1"
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bitfld.long 0x8 16. "SW_HCCV,Set corresponding switch" "0,1"
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bitfld.long 0x8 12.--14. "SW_HCBG,Select waveform for corresponding switch using csd_shield as base" "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 8.--10. "SW_HCBV,N/A" "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 4.--6. "SW_HCAG,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 0.--2. "SW_HCAV,N/A" "0,1,2,3,4,5,6,7"
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group.long 0x290++0x7
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line.long 0x0 "SW_AMUXBUF_SEL,Amuxbuffer switches Waveform selection"
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bitfld.long 0x0 28. "SW_IRL,Set corresponding switch" "0,1"
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bitfld.long 0x0 24. "SW_IRH,Set corresponding switch" "0,1"
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bitfld.long 0x0 20. "SW_IRLI,Set corresponding switch" "0,1"
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bitfld.long 0x0 16.--18. "SW_ICB,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 12. "SW_ICA,Set corresponding switch" "0,1"
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bitfld.long 0x0 8. "SW_IRLB,Set corresponding switch" "0,1"
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bitfld.long 0x0 4. "SW_IRBY,Set corresponding switch" "0,1"
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line.long 0x4 "SW_BYP_SEL,AMUXBUS bypass switches Waveform selection"
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bitfld.long 0x4 20. "SW_CBCC,Set corresponding switch" "0,1"
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bitfld.long 0x4 16. "SW_BYB,Set corresponding switch" "0,1"
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bitfld.long 0x4 12. "SW_BYA,Set corresponding switch" "0,1"
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group.long 0x2A0++0xB
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line.long 0x0 "SW_CMP_P_SEL,CSDCMP Pos Switch Waveform selection"
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bitfld.long 0x0 24. "SW_SFCB,Set corresponding switch" "0,1"
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bitfld.long 0x0 20. "SW_SFCA,Set corresponding switch" "0,1"
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bitfld.long 0x0 16. "SW_SFMB,Set corresponding switch" "0,1"
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bitfld.long 0x0 12. "SW_SFMA,Set corresponding switch" "0,1"
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bitfld.long 0x0 8.--10. "SW_SFPS,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "SW_SFPT,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0.--2. "SW_SFPM,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
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line.long 0x4 "SW_CMP_N_SEL,CSDCMP Neg Switch Waveform selection"
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bitfld.long 0x4 28.--30. "SW_SCRL,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 24.--26. "SW_SCRH,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
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line.long 0x8 "SW_REFGEN_SEL,Reference Generator Switch Waveform selection"
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bitfld.long 0x8 28. "SW_SGR,Set corresponding switch" "0,1"
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bitfld.long 0x8 24. "SW_SGRE,Set corresponding switch" "0,1"
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bitfld.long 0x8 20. "SW_SGRP,Set corresponding switch" "0,1"
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bitfld.long 0x8 16. "SW_SGMB,Set corresponding switch" "0,1"
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bitfld.long 0x8 4. "SW_IBCB,Set corresponding switch" "0,1"
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bitfld.long 0x8 0. "SW_IAIB,Set corresponding switch" "0,1"
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group.long 0x2B0++0x7
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line.long 0x0 "SW_FW_MOD_SEL,Full Wave Cmod Switch Waveform selection"
|
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bitfld.long 0x0 28. "SW_C1F1,Set corresponding switch" "0,1"
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bitfld.long 0x0 24. "SW_C1CD,Set corresponding switch" "0,1"
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bitfld.long 0x0 20. "SW_C1CC,Set corresponding switch" "0,1"
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|
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bitfld.long 0x0 16.--18. "SW_F1CA,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 8.--10. "SW_F1MA,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
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|
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bitfld.long 0x0 0. "SW_F1PM,Set corresponding switch" "0,1"
|
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line.long 0x4 "SW_FW_TANK_SEL,Full Wave Csh_tank Switch Waveform selection"
|
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bitfld.long 0x4 28. "SW_C2F2,Set corresponding switch" "0,1"
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bitfld.long 0x4 24. "SW_C2CD,Set corresponding switch" "0,1"
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bitfld.long 0x4 20. "SW_C2CC,Set corresponding switch" "0,1"
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bitfld.long 0x4 16.--18. "SW_F2CB,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 12.--14. "SW_F2CA,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 8.--10. "SW_F2MA,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
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|
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bitfld.long 0x4 4. "SW_F2PT,Set corresponding switch" "0,1"
|
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group.long 0x2C0++0x3
|
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line.long 0x0 "SW_DSI_SEL,DSI output switch control Waveform selection"
|
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hexmask.long.byte 0x0 4.--7. 1. "DSI_CMOD,Select waveform for dsi_cmod output signal"
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hexmask.long.byte 0x0 0.--3. 1. "DSI_CSH_TANK,Select waveform for dsi_csh_tank output signal"
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group.long 0x2D0++0x3
|
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line.long 0x0 "IO_SEL,IO output control Waveform selection"
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hexmask.long.byte 0x0 24.--27. 1. "CSD_TX_N_AMUXA_EN,Select waveform for csd_tx_n_amuxa_en output signal"
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|
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hexmask.long.byte 0x0 20.--23. 1. "CSD_TX_N_OUT_EN,Select waveform for csd_tx_n_out_en output signal"
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|
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hexmask.long.byte 0x0 16.--19. 1. "CSD_TX_N_OUT,Select waveform for csd_tx_n_out output signal"
|
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|
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hexmask.long.byte 0x0 12.--15. 1. "CSD_TX_AMUXB_EN,Select waveform for csd_tx_amuxb_en output signal"
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|
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hexmask.long.byte 0x0 4.--7. 1. "CSD_TX_OUT_EN,Select waveform for csd_tx_out_en output signal"
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|
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hexmask.long.byte 0x0 0.--3. 1. "CSD_TX_OUT,Select waveform for csd_tx_out output signal"
|
|
group.long 0x300++0x3
|
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line.long 0x0 "SEQ_TIME,Sequencer Timing"
|
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hexmask.long.byte 0x0 0.--7. 1. "AZ_TIME,Define Auto-Zero time in csd_sense cycles -1."
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group.long 0x310++0x7
|
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line.long 0x0 "SEQ_INIT_CNT,Sequencer Initial conversion and sample counts"
|
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hexmask.long.word 0x0 0.--15. 1. "CONV_CNT,Number of conversion per Initialization sample if set to 0 the Sample_init state will be skipped."
|
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line.long 0x4 "SEQ_NORM_CNT,Sequencer Normal conversion and sample counts"
|
|
hexmask.long.word 0x4 0.--15. 1. "CONV_CNT,Number of conversion per sample if set to 0 the Sample_norm state will be skipped."
|
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group.long 0x320++0x3
|
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line.long 0x0 "ADC_CTL,ADC Control"
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bitfld.long 0x0 16.--17. "ADC_MODE,Enable ADC measurement. When enabled the ADC sequencer will be started when the main sequencer goes to the SAMPLE_NORM state" "0: No ADC measurement,1: Count time A to bring Cref1 + Cref2 up from Vssa..,2: Count time B to bring Cref1 + Cref2 back up to..,3: Determine HSCMP polarity and count time C to.."
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hexmask.long.byte 0x0 0.--7. 1. "ADC_TIME,ADC timing -1 in csd_sense clock cycles (actual time is ADC_TIME+1 cycles) either used to discharge Cref1&2 or as the aperture to capture the input voltage on Cref1&2"
|
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group.long 0x340++0x3
|
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line.long 0x0 "SEQ_START,Sequencer start"
|
|
bitfld.long 0x0 9. "AZ1_SKIP,When set the AutoZero_1 state will be skipped" "0,1"
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|
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|
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bitfld.long 0x0 8. "AZ0_SKIP,When set the AutoZero_0 state will be skipped" "0,1"
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|
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|
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bitfld.long 0x0 4. "DSI_START_EN,When this bit is set a positive edge on dsi_start will start the CSD sequencer and if enabled also the ADC sequencer." "0,1"
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bitfld.long 0x0 3. "ABORT,When a 1 is written the CSD and ADC sequencers will be aborted (if they are running) and the START bit will be cleared. This bit always read as 0." "0,1"
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|
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|
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bitfld.long 0x0 1. "SEQ_MODE,0 = regular CSD scan + optional ADC" "0: regular CSD scan + optional ADC,1: coarse initialization"
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|
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|
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bitfld.long 0x0 0. "START,Start the CSD sequencer. The sequencer will clear this bit when it is done. Depending on the mode the sequencer is done when a sample has been accumulated when the high speed comparator trips or if the sequencer is aborted. When the ADC is enabled.." "0,1"
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "IDACA,IDACA Configuration"
|
|
bitfld.long 0x0 25. "LEG2_EN,N/A" "0,1"
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|
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|
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bitfld.long 0x0 24. "LEG1_EN,N/A" "0,1"
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|
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|
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bitfld.long 0x0 22.--23. "RANGE,N/A" "0: 1 LSB = 37.5 nA,1: 1 LSB = 300 nA,2: 1 LSB = 2400 nA,?"
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|
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|
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bitfld.long 0x0 21. "DSI_CTRL_EN,N/A" "0,1"
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|
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|
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bitfld.long 0x0 18.--19. "LEG2_MODE,N/A" "0: General Purpose static mode: LEG2 is controlled..,1: General Purpose dynamic mode: LEG2 is controlled..,2: CSD static mode: LEG2 can only be on when the..,3: CSD dynamic mode: LEG2 can only be on when the.."
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|
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bitfld.long 0x0 16.--17. "LEG1_MODE,N/A" "0: General Purpose static mode: LEG1 and POLARITY..,1: General Purpose dynamic mode: LEG1 and POLARITY..,2: CSD static mode: LEG1 can only be on when the..,3: CSD dynamic mode: LEG1 can only be on when the.."
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|
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bitfld.long 0x0 10.--11. "BAL_MODE,N/A" "0: enabled from start of Phi2 until disabled by..,1: enabled from start of Phi1 and disabled by..,2: enabled from start of Phi2 and disabled by..,3: enabled from start of both Phi1 and Phi2 and.."
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|
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|
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bitfld.long 0x0 8.--9. "POLARITY,N/A" "0: Normal: switch between Vssa and Cmod. For..,1: Inverted: switch between Vdda and Cmod. For..,2: The polarity of the IDAC will follow the..,3: The polarity of the IDAC will follow the.."
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|
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|
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bitfld.long 0x0 7. "POL_DYN,N/A" "0: Static polarity. Polarity is expected to be..,1: Dynamic polarity. Polarity is expected to change.."
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|
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|
|
hexmask.long.byte 0x0 0.--6. 1. "VAL,N/A"
|
|
group.long 0x500++0x3
|
|
line.long 0x0 "IDACB,IDACB Configuration"
|
|
bitfld.long 0x0 26. "LEG3_EN,N/A" "0,1"
|
|
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|
|
bitfld.long 0x0 25. "LEG2_EN,N/A" "0,1"
|
|
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|
|
bitfld.long 0x0 24. "LEG1_EN,N/A" "0,1"
|
|
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|
|
bitfld.long 0x0 22.--23. "RANGE,N/A" "0: 1 LSB = 37.5 nA,1: 1 LSB = 300 nA,2: 1 LSB = 2400 nA,?"
|
|
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|
|
bitfld.long 0x0 21. "DSI_CTRL_EN,N/A" "0,1"
|
|
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|
|
bitfld.long 0x0 18.--19. "LEG2_MODE,N/A" "0: same as corresponding IDACA.LEG2_MODE,1: same as corresponding IDACA.LEG2_MODE,2: same as corresponding IDACA.LEG2_MODE,3: same as corresponding IDACA.LEG2_MODE"
|
|
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|
|
bitfld.long 0x0 16.--17. "LEG1_MODE,N/A" "0: same as corresponding IDACA.LEG1_MODE,1: same as corresponding IDACA.LEG1_MODE,2: same as corresponding IDACA.LEG1_MODE,3: same as corresponding IDACA.LEG1_MODE"
|
|
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|
|
bitfld.long 0x0 10.--11. "BAL_MODE,N/A" "0: same as corresponding IDACA Balancing mode,1: same as corresponding IDACA Balancing mode,2: same as corresponding IDACA Balancing mode,3: same as corresponding IDACA Balancing mode"
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|
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|
|
bitfld.long 0x0 8.--9. "POLARITY,N/A" "0: Normal: switch between Vssa and Cmod. For..,1: Inverted: switch between Vdda and Cmod. For..,2: The polarity of the IDAC will follow the..,3: The polarity of the IDAC will follow the.."
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|
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|
|
bitfld.long 0x0 7. "POL_DYN,N/A" "0: Static polarity. Polarity is expected to be..,1: Dynamic polarity. Polarity is expected to change.."
|
|
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|
|
hexmask.long.byte 0x0 0.--6. 1. "VAL,N/A"
|
|
tree.end
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x41100000
|
|
elif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
base ad:0x40900000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??4*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??4*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
tree "CTBM (Continuous Time Block Mini)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTB_CTRL,global CTB and power control"
|
|
bitfld.long 0x0 31. "ENABLED,- 0: CTBm disabled (put analog in power down open all switches)" "0: CTBm disabled,1: CTBm enabled"
|
|
newline
|
|
bitfld.long 0x0 30. "DEEPSLEEP_ON,- 0: CTBm is disabled during DeepSleep power mode" "0: CTBm is disabled during DeepSleep power mode,1: CTBm remains enabled during DeepSleep power mode"
|
|
line.long 0x4 "OA_RES0_CTRL,Opamp0 and resistor0 control"
|
|
bitfld.long 0x4 12. "OA0_BOOST_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "OA0_PUMP_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "OA0_COMPINT,Opamp comparator edge detect for interrupt and pulse mode of trigger" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
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|
newline
|
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bitfld.long 0x4 7. "OA0_DSI_LEVEL,Opamp comparator trigger output level :" "0: pulse,1: level"
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|
newline
|
|
bitfld.long 0x4 6. "OA0_BYPASS_DSI_SYNC,Opamp bypass comparator output synchronization for trigger output: 0=synchronize (level or pulse) 1=bypass (asynchronous output)." "0: synchronize,1: bypass"
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|
newline
|
|
bitfld.long 0x4 5. "OA0_HYST_EN,Opamp hysteresis enable. See the device Datasheet for hysteresis specifications." "0,1"
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|
newline
|
|
bitfld.long 0x4 4. "OA0_COMP_EN,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x4 3. "OA0_DRIVE_STR_SEL,Opamp output drive strength: 0=1x 1=10x. See the device Datasheet for exact current ranges and related specifications.This setting sets specific requirements for OA0_BOOST_EN and OA0_COMP_TRIM." "0: 1x,1: 10x"
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|
newline
|
|
bitfld.long 0x4 0.--2. "OA0_PWR_MODE,Opamp power level. Reduced power levels also reduce gain-bandwidth (GBW). See the 'Opamp Specifications' table in the device Datasheet for more details." "0: Off,1: Low power mode (IDD: 350uA GBW: 1MHz for both..,2: Medium power mode (IDD: 600uA GBW: 3MHz for 1x &..,3: High power mode for highest GBW (IDD: 1500uA..,4: N/A,5: Power Saver Low power mode (IDD: ~20uA with 1uA..,6: Power Saver Medium power mode (IDD: ~40uA with..,7: Power Saver Medium power mode (IDD: ~60uA with.."
|
|
line.long 0x8 "OA_RES1_CTRL,Opamp1 and resistor1 control"
|
|
bitfld.long 0x8 12. "OA1_BOOST_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "OA1_PUMP_EN,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x8 8.--9. "OA1_COMPINT,Opamp comparator edge detect for interrupt and pulse mode of trigger" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
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|
newline
|
|
bitfld.long 0x8 7. "OA1_DSI_LEVEL,Opamp comparator trigger output level :" "0: pulse,1: level"
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|
newline
|
|
bitfld.long 0x8 6. "OA1_BYPASS_DSI_SYNC,Opamp bypass comparator output synchronization for trigger output: 0=synchronize (level or pulse) 1=bypass (asynchronous output)." "0: synchronize,1: bypass"
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|
newline
|
|
bitfld.long 0x8 5. "OA1_HYST_EN,Opamp hysteresis enable. See the device Datasheet for hysteresis specifications." "0,1"
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|
newline
|
|
bitfld.long 0x8 4. "OA1_COMP_EN,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x8 3. "OA1_DRIVE_STR_SEL,Opamp output drive strength: 0=1x 1=10x. See the device Datasheet for exact current ranges and related specifications.This setting sets specific requirements for OA1_BOOST_EN and OA1_COMP_TRIM" "0: 1x,1: 10x"
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|
newline
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bitfld.long 0x8 0.--2. "OA1_PWR_MODE,Opamp power level. Reduced power levels also reduce gain-bandwidth (GBW). See the 'Opamp Specifications' table in the device Datasheet for more details." "0,1,2,3,4,5,6,7"
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|
rgroup.long 0xC++0x3
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|
line.long 0x0 "COMP_STAT,Comparator status"
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|
bitfld.long 0x0 16. "OA1_COMP,Opamp1 current comparator status" "0,1"
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|
newline
|
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bitfld.long 0x0 0. "OA0_COMP,Opamp0 current comparator status" "0,1"
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|
group.long 0x20++0xB
|
|
line.long 0x0 "INTR,Interrupt request register"
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|
bitfld.long 0x0 1. "COMP1,Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "COMP0,Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit." "0,1"
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|
line.long 0x4 "INTR_SET,Interrupt request set register"
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|
bitfld.long 0x4 1. "COMP1_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 0. "COMP0_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
line.long 0x8 "INTR_MASK,Interrupt request mask"
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|
bitfld.long 0x8 1. "COMP1_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
|
bitfld.long 0x8 0. "COMP0_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
rgroup.long 0x2C++0x3
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|
line.long 0x0 "INTR_MASKED,Interrupt request masked"
|
|
bitfld.long 0x0 1. "COMP1_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COMP0_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "OA0_SW,Opamp0 switch control"
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|
bitfld.long 0x0 21. "OA0O_D81,Switch that shorts Opamp's 1x and 10x outputs." "0,1"
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|
newline
|
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bitfld.long 0x0 18. "OA0O_D51,Switch that connects Opamp's output to SARBUS 0." "0,1"
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|
newline
|
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bitfld.long 0x0 14. "OA0M_A81,Switch that connects Opamp's inverting terminal to Opamp's output for follower mode." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "OA0M_A11,Switch that connects Opamp's inverting terminal to pin 1 of CTBm port ." "0,1"
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|
newline
|
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bitfld.long 0x0 3. "OA0P_A30,Switch that connects Opamp's non-inverting terminal to pin 6 of CTBm port. Note that this bus can have additional connections to or from the CTDAC. See the Architecture TRM for details." "0,1"
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|
newline
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bitfld.long 0x0 2. "OA0P_A20,Switch that connects Opamp's non-inverting terminal to pin 0 of CTBm port. See the device Datasheet for the location of CTBm port." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "OA0P_A00,Switch that connects Opamp's non-inverting terminal to AMUXBUS A." "0,1"
|
|
line.long 0x4 "OA0_SW_CLEAR,Opamp0 switch control clear"
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|
bitfld.long 0x4 21. "OA0O_D81,see corresponding bit in OA0_SW" "0,1"
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|
newline
|
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bitfld.long 0x4 18. "OA0O_D51,see corresponding bit in OA0_SW" "0,1"
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|
newline
|
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bitfld.long 0x4 14. "OA0M_A81,see corresponding bit in OA0_SW" "0,1"
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|
newline
|
|
bitfld.long 0x4 8. "OA0M_A11,see corresponding bit in OA0_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OA0P_A30,see corresponding bit in OA0_SW" "0,1"
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|
newline
|
|
bitfld.long 0x4 2. "OA0P_A20,see corresponding bit in OA0_SW" "0,1"
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|
newline
|
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bitfld.long 0x4 0. "OA0P_A00,see corresponding bit in OA0_SW" "0,1"
|
|
line.long 0x8 "OA1_SW,Opamp1 switch control"
|
|
bitfld.long 0x8 21. "OA1O_D82,Switch that shorts Opamp's 1x and 10x outputs." "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "OA1O_D62,Switch that connects Opamp's output to SARBUS 1." "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "OA1O_D52,Switch that connects Opamp's output to SARBUS 0." "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "OA1M_A82,Switch that connects Opamp's inverting terminal to Opamp's output for follower mode." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "OA1M_A22,Switch that connects Opamp's inverting terminal to pin 4 of CTBm port." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "OA1P_A73,Switch that connects Opamp's non-inverting terminal to VREF." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "OA1P_A43,Switch that connects Opamp's non-inverting terminal to pin 7 of CTBm port." "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "OA1P_A13,Switch that connects Opamp's non-inverting terminal to pin 5 of CTBm port. See the device Datasheet for the location of CTBm port." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "OA1P_A03,Switch that connects Opamp's non-inverting terminal to AMUXBUS B." "0,1"
|
|
line.long 0xC "OA1_SW_CLEAR,Opamp1 switch control clear"
|
|
bitfld.long 0xC 21. "OA1O_D82,see corresponding bit in OA1_SW" "0,1"
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|
newline
|
|
bitfld.long 0xC 19. "OA1O_D62,see corresponding bit in OA1_SW" "0,1"
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|
newline
|
|
bitfld.long 0xC 18. "OA1O_D52,see corresponding bit in OA1_SW" "0,1"
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|
newline
|
|
bitfld.long 0xC 14. "OA1M_A82,see corresponding bit in OA1_SW" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "OA1M_A22,see corresponding bit in OA1_SW" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "OA1P_A73,see corresponding bit in OA1_SW" "0,1"
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|
newline
|
|
bitfld.long 0xC 4. "OA1P_A43,see corresponding bit in OA1_SW" "0,1"
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|
newline
|
|
bitfld.long 0xC 1. "OA1P_A13,see corresponding bit in OA1_SW" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "OA1P_A03,see corresponding bit in OA1_SW" "0,1"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "CTD_SW,CTDAC connection switch control"
|
|
bitfld.long 0x0 15. "CTDH_ILR,Switch that shorts Opamp0's inverting and non-inverting inputs to reduce hold capacitor leakage." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CTDH_CIS,Switch that isolates hold capacitor from other inputs connected to Opamp0's non-inverting input." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CTDH_CA0,Switch that connects hold capacitor to Opamp0's non-inverting input." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CTDH_CHD,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CTDH_COB,Switch that connects hold capacitor to Opamp0's output. Used during hold mode in Sample and Hold operation." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTDO_COS,Switch that connects ctdvout to the internal hold capacitor (Sampling Switch). Note this switch will temporarily be opened for deglitching if CTDAC.DEGLITCH_COS is set." "0,1"
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|
newline
|
|
bitfld.long 0x0 8. "CTDO_C6H,Switch that connects pin 6 of the CTBm port to ctdvout (CTDAC Vout). See the device Datasheet for the location of CTBm port." "0,1"
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|
newline
|
|
bitfld.long 0x0 5. "CTDS_COR,Switch that connects Opamp1's inverting input to ctdvout (CTDAC Vout)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CTDS_CRS,Switch that connects Opamp1's inverting input to ctdrefsense (CTDAC Reference Sense)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CTDD_CRD,Switch that connects Opamp1's output to ctdrefdrive (CTDAC Reference Drive)." "0,1"
|
|
line.long 0x4 "CTD_SW_CLEAR,CTDAC connection switch control clear"
|
|
bitfld.long 0x4 15. "CTDH_ILR,see corresponding bit in CTD_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "CTDH_CIS,see corresponding bit in CTD_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CTDH_CA0,see corresponding bit in CTD_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CTDH_CHD,see corresponding bit in CTD_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "CTDH_COB,see corresponding bit in CTD_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CTDO_COS,see corresponding bit in CTD_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CTDO_C6H,see corresponding bit in CTD_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CTDS_COR,see corresponding bit in CTD_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CTDS_CRS,see corresponding bit in CTD_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CTDD_CRD,see corresponding bit in CTD_SW" "0,1"
|
|
group.long 0xC0++0x7
|
|
line.long 0x0 "CTB_SW_DS_CTRL,CTB bus switch control"
|
|
bitfld.long 0x0 31. "CTD_COS_DS_CTRL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P3_DS_CTRL23,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "P2_DS_CTRL23,N/A" "0,1"
|
|
line.long 0x4 "CTB_SW_SQ_CTRL,CTB bus switch Sar Sequencer control"
|
|
bitfld.long 0x4 11. "P3_SQ_CTRL23,for D52 D62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "P2_SQ_CTRL23,for D51" "0,1"
|
|
rgroup.long 0xC8++0x3
|
|
line.long 0x0 "CTB_SW_STATUS,CTB bus switch control status"
|
|
bitfld.long 0x0 31. "CTD_COS_STAT,see COS bit in CTD_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "OA1O_D62_STAT,see OA1O_D62 bit in OA1_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "OA1O_D52_STAT,see OA1O_D52 bit in OA1_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "OA0O_D51_STAT,see OA0O_D51 bit in OA0_SW" "0,1"
|
|
group.long 0xF00++0x17
|
|
line.long 0x0 "OA0_OFFSET_TRIM,Opamp0 trim control"
|
|
hexmask.long.byte 0x0 0.--5. 1. "OA0_OFFSET_TRIM,Opamp0 offset trim"
|
|
line.long 0x4 "OA0_SLOPE_OFFSET_TRIM,Opamp0 trim control"
|
|
hexmask.long.byte 0x4 0.--5. 1. "OA0_SLOPE_OFFSET_TRIM,Opamp0 slope offset drift trim"
|
|
line.long 0x8 "OA0_COMP_TRIM,Opamp0 trim control"
|
|
bitfld.long 0x8 0.--1. "OA0_COMP_TRIM,Opamp0 Compensation Capacitor Trim." "0,1,2,3"
|
|
line.long 0xC "OA1_OFFSET_TRIM,Opamp1 trim control"
|
|
hexmask.long.byte 0xC 0.--5. 1. "OA1_OFFSET_TRIM,Opamp1 offset trim"
|
|
line.long 0x10 "OA1_SLOPE_OFFSET_TRIM,Opamp1 trim control"
|
|
hexmask.long.byte 0x10 0.--5. 1. "OA1_SLOPE_OFFSET_TRIM,Opamp1 slope offset drift trim"
|
|
line.long 0x14 "OA1_COMP_TRIM,Opamp1 trim control"
|
|
bitfld.long 0x14 0.--1. "OA1_COMP_TRIM,Opamp1 Compensation Capacitor Trim." "0,1,2,3"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x41140000
|
|
elif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
base ad:0x40940000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??4*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??4*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
tree "CTDAC (Continuous Time DAC)"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTDAC_CTRL,Global CTDAC control"
|
|
bitfld.long 0x0 31. "ENABLED,0: CTDAC IP disabled (put analog in power down open all switches)" "0: CTDAC IP disabled,1: CTDAC IP enabled"
|
|
newline
|
|
bitfld.long 0x0 30. "DEEPSLEEP_ON,- 0: CTDAC IP disabled off during DeepSleep power mode" "0: CTDAC IP disabled off during DeepSleep power mode,1: CTDAC IP remains enabled during DeepSleep power.."
|
|
newline
|
|
bitfld.long 0x0 29. "DSI_STROBE_LEVEL,Select level or edge detect for DSI strobe" "0: DSI strobe signal is a pulse input,1: DSI strobe signal is a level input"
|
|
newline
|
|
bitfld.long 0x0 28. "DSI_STROBE_EN,DSI strobe input Enable. This enables CTDAC updates to be further throttled by DSI." "0: Ignore DSI strobe input,1: Only do a CTDAC update if allowed by the DSI.."
|
|
newline
|
|
bitfld.long 0x0 27. "DISABLED_MODE,Select the output value when the output is disabled (OUT_EN=0) (for risk mitigation)" "0: Tri-state CTDAC output when disabled,1: output Vssa or Vref when disabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "CTDAC_MODE,DAC mode this determines the Value decoding" "0: Unsigned 12-bit VDAC i.e. no value decoding.,1: Virtual signed 12-bits' VDAC. Value decoding:..,2: N/A,3: N/A"
|
|
newline
|
|
bitfld.long 0x0 23. "CTDAC_RANGE,By closing the bottom switch in the R2R network the output is lifted by one LSB effectively adding 1" "0: Range is [0,1: Range is [1"
|
|
newline
|
|
bitfld.long 0x0 22. "OUT_EN,Output enable intended to be used during the Hold phase of the Sample and Hold when power cycling :" "0: output disabled,1: output enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "DEGLITCH_COS,Force CTB.COS switch open after each VALUE change for the set number of clock cycles." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DEGLITCH_CO6,Force CTDAC.CO6 switch open after each VALUE change for the set number of clock cycles." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "DEGLITCH_CNT,To prevent glitches after VALUE changes from propagating the output switch can be opened for DEGLITCH_CNT+1 clk_peri clock cycles."
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "INTR,Interrupt request register"
|
|
bitfld.long 0x0 0. "VDAC_EMPTY,VDAC Interrupt: hardware sets this interrupt when VDAC next value field is empty i.e. was copied to the current VALUE. Write with '1' to clear bit." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt request set register"
|
|
bitfld.long 0x4 0. "VDAC_EMPTY_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt request mask"
|
|
bitfld.long 0x8 0. "VDAC_EMPTY_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt request masked"
|
|
bitfld.long 0x0 0. "VDAC_EMPTY_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "CTDAC_SW,CTDAC switch control"
|
|
bitfld.long 0x0 8. "CTDO_CO6,ctdvout to P6 pin. Note this switch will temporarily be opened for deglitching if DEGLITCH_CO6 is set" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CTDD_CVD,VDDA supply to ctdrefdrive" "0,1"
|
|
line.long 0x4 "CTDAC_SW_CLEAR,CTDAC switch control clear"
|
|
bitfld.long 0x4 8. "CTDO_CO6,see corresponding bit in CTD_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CTDD_CVD,see corresponding bit in CTD_SW" "0,1"
|
|
group.long 0x100++0x7
|
|
line.long 0x0 "CTDAC_VAL,DAC Value"
|
|
hexmask.long.word 0x0 0.--11. 1. "VALUE,Value in CTDAC_MODE 1 this value is decoded"
|
|
line.long 0x4 "CTDAC_VAL_NXT,Next DAC value (double buffering)"
|
|
hexmask.long.word 0x4 0.--11. 1. "VALUE,Next value for CTDAC_VAL.VALUE"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
tree "DMAC (Direct Memory Access Controller)"
|
|
base ad:0x402A0000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: Disabled,1: Enabled"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "ACTIVE,Active channels"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ACTIVE,Specifies active channels; i.e. enabled channels whose trigger got activated."
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x402A1000 ad:0x402A1100 ad:0x402A1200 ad:0x402A1300)
|
|
tree "CH[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0: highest priority,?,?,3: lowest priority"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
newline
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
newline
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long ($2+0x10)++0xB
|
|
line.long 0x0 "IDX,Channel current indices"
|
|
hexmask.long.word 0x0 16.--31. 1. "Y,Specifies the Y loop index with Y_COUNT taken from the current descriptor."
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "X,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "SRC,Channel current source address"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Current address of source location."
|
|
line.long 0x8 "DST,Channel current destination address"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Current address of destination location."
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "CURR,Channel current descriptor pointer"
|
|
hexmask.long 0x0 2.--31. 1. "PTR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
group.long ($2+0x28)++0x3
|
|
line.long 0x0 "TR_CMD,Channle software trigger"
|
|
bitfld.long 0x0 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
rgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "DESCR_STATUS,Channel descriptor status"
|
|
bitfld.long 0x0 31. "VALID,Indicates whether the descriptor information present in DESCR_CTL DESCR_SRC DESCR_DST DESCR_X_SIZE DESCR_X_INCR DESCR_Y_SIZE DESCR_Y_INCR DESCR_NEXT status registers is valid or not." "0,1"
|
|
rgroup.long ($2+0x60)++0x1F
|
|
line.long 0x0 "DESCR_CTL,Channel descriptor control"
|
|
bitfld.long 0x0 28.--30. "DESCR_TYPE,Specifies the descriptor type (not to be confused with the trigger type):" "0: Single transfer,1: 1D transfer,2: 2D transfer,3: Memory copy,4: Scatter transfer,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 27. "DST_TRANSFER_SIZE,Specifies the bus transfer size to the destination location:" "0: As specified by DATA_SIZE,1: Word"
|
|
newline
|
|
bitfld.long 0x0 26. "SRC_TRANSFER_SIZE,Specifies the bus transfer size to the source location:" "0: As specified by DATA_SIZE,1: Word"
|
|
newline
|
|
bitfld.long 0x0 24. "CH_DISABLE,Specifies whether the channel is disabled or not after completion of the current descriptor (independent of the value of the DESCR_NEXT_PTR value):" "0: Channel is not disabled,1: Channel is disabled"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "DATA_SIZE,Specifies the data element size:" "0: Byte,1: Halfword,2: Word,?"
|
|
newline
|
|
bitfld.long 0x0 8. "DATA_PREFETCH,Source data prefetch:" "0: No source data prefetch,1: Source data prefetch"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "TR_IN_TYPE,Specifies the input trigger type (not to be confused with the descriptor type):" "0: A trigger results in the execution of a single..,1: A trigger results in the execution of a single..,2: A trigger results in the execution of the..,3: A trigger results in the execution of the.."
|
|
newline
|
|
bitfld.long 0x0 4.--5. "TR_OUT_TYPE,Specifies when an output trigger is generated:" "0: An output trigger is generated after a single..,1: An output trigger is generated after a single 1D..,2: An output trigger is generated after the..,3: An output trigger is generated after the.."
|
|
newline
|
|
bitfld.long 0x0 2.--3. "INTR_TYPE,Specifies when a completion interrupt is generated (CH_STATUS.INTR_CAUSE is set to COMPLETION):" "0: An interrupt is generated after a single transfer,1: An interrupt is generated after a single 1D..,2: An interrupt is generated after the execution of..,3: An interrupt is generated after the execution of.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "WAIT_FOR_DEACT,Specifies whether the controller should wait for the input trigger to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller with the agent that generated the trigger. This field is.." "0: Do not wait for trigger de-activation,1: Wait for up to 4 cycles,2: Wait for up to 16 cycles,3: Wait indefinitely"
|
|
line.long 0x4 "DESCR_SRC,Channel descriptor source"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Base address of source location."
|
|
line.long 0x8 "DESCR_DST,Channel descriptor destination"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Base address of destination location."
|
|
line.long 0xC "DESCR_X_SIZE,Channel descriptor X size"
|
|
hexmask.long.word 0xC 0.--15. 1. "X_COUNT,Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0 65535] representing 1 through 65536 iterations."
|
|
line.long 0x10 "DESCR_X_INCR,Channel descriptor X increment"
|
|
hexmask.long.word 0x10 16.--31. 1. "DST_X,Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768 32767]. If this field is '0' the destination address is not.."
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "SRC_X,Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768 32767]. If this field is '0' the source address is not incremented."
|
|
line.long 0x14 "DESCR_Y_SIZE,Channel descriptor Y size"
|
|
hexmask.long.word 0x14 0.--15. 1. "Y_COUNT,Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0 65535] representing 1 through 65536 iterations."
|
|
line.long 0x18 "DESCR_Y_INCR,Channel descriptor Y increment"
|
|
hexmask.long.word 0x18 16.--31. 1. "DST_Y,Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-32768 32767]."
|
|
newline
|
|
hexmask.long.word 0x18 0.--15. 1. "SRC_Y,Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-32768 32767]."
|
|
line.long 0x1C "DESCR_NEXT,Channel descriptor next pointer"
|
|
hexmask.long 0x1C 2.--31. 1. "PTR,Address of next descriptor in descriptor list. When this field is '0' this is the last descriptor in the descriptor list."
|
|
group.long ($2+0x80)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 7. "DESCR_BUS_ERROR,Activated (set to '1') on a bus error for a load of the descriptor." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ACTIVE_CH_DISABLED,Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CURR_PTR_NULL,Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DST_MISAL,Activated (set to '1') on a misalignment of the destination address." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SRC_MISAL,Activated (set to '1') on a misalignment of the source address." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DST_BUS_ERROR,Activated (set to '1') on a bus error for a store to the destination." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SRC_BUS_ERROR,Activated (set to '1') on a bus error for a load from the source." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COMPLETION,Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 7. "DESCR_BUS_ERROR,Write this field with '1' to set INTR.DESCR_BUS_ERROR field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ACTIVE_CH_DISABLED,Write this field with '1' to set INTR.ACT_CH_DISABLED field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CURR_PTR_NULL,Write this field with '1' to set INTR.CURR_PTR_NULL field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DST_MISAL,Write this field with '1' to set INTR.DST_MISAL field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SRC_MISAL,Write this field with '1' to set INTR.SRC_MISAL field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DST_BUS_ERROR,Write this field with '1' to set INTR.DST_BUS_ERROR field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "SRC_BUS_ERROR,Write this field with '1' to set INTR.SRC_BUS_ERROR field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "COMPLETION,Write this field with '1' to set INTR.COMPLETION field to '1' (a write of '0' has no effect)." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 7. "DESCR_BUS_ERROR,Mask for INTR.DESCR_BUS_ERROR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ACTIVE_CH_DISABLED,Mask for INTR.ACTIVE_CH_DISABLED interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "CURR_PTR_NULL,Mask for INTR.CURR_PTR_NULL interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "DST_MISAL,Mask for INTR.DST_MISAL interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "SRC_MISAL,Mask for INTR.SRC_MISAL interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "DST_BUS_ERROR,Mask for INTR.DST_BUS_ERROR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "SRC_BUS_ERROR,Mask for INTR.SRC_BUS_ERROR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "COMPLETION,Mask for INTR.COMPLETION interrupt." "0,1"
|
|
rgroup.long ($2+0x8C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 7. "DESCR_BUS_ERROR,Logical and of corresponding INTR.DESCR_BUS_ERROR and INTR_MASK.DESCR_BUS_ERROR fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ACTIVE_CH_DISABLED,Logical and of corresponding INTR.ACTIVE_CH_DISABLED and INTR_MASK.ACTIVE_CH_DISABLED fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CURR_PTR_NULL,Logical and of corresponding INTR.CURR_PTR_NULL and INTR_MASK.CURR_PTR_NULL fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DST_MISAL,Logical and of corresponding INTR.DST_MISAL and INTR_MASK.DST_MISAL fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SRC_MISAL,Logical and of corresponding INTR.SRC_MISAL and INTR_MASK.SRC_MISAL fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DST_BUS_ERROR,Logical and of corresponding INTR.DST_BUS_ERROR and INTR_MASK.DST_BUS_ERROR fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SRC_BUS_ERROR,Logical and of corresponding INTR.SRC_BUS_ERROR and INTR_MASK.SRC_BUS_ERROR fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COMPLETION,Logical and of corresponding INTR.COMPLETION and INTR_MASK.COMPLETION fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x402A0000
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 2. (list 0x0 0x1)(list ad:0x402A1000 ad:0x402A1100)
|
|
tree "CH[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0: highest priority,?,?,3: lowest priority"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
newline
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
newline
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long ($2+0x10)++0xB
|
|
line.long 0x0 "IDX,Channel current indices"
|
|
hexmask.long.word 0x0 16.--31. 1. "Y,Specifies the Y loop index with Y_COUNT taken from the current descriptor."
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "X,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "SRC,Channel current source address"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Current address of source location."
|
|
line.long 0x8 "DST,Channel current destination address"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Current address of destination location."
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "CURR,Channel current descriptor pointer"
|
|
hexmask.long 0x0 2.--31. 1. "PTR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
group.long ($2+0x28)++0x3
|
|
line.long 0x0 "TR_CMD,Channle software trigger"
|
|
bitfld.long 0x0 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
rgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "DESCR_STATUS,Channel descriptor status"
|
|
bitfld.long 0x0 31. "VALID,Indicates whether the descriptor information present in DESCR_CTL DESCR_SRC DESCR_DST DESCR_X_SIZE DESCR_X_INCR DESCR_Y_SIZE DESCR_Y_INCR DESCR_NEXT status registers is valid or not." "0,1"
|
|
rgroup.long ($2+0x60)++0x1F
|
|
line.long 0x0 "DESCR_CTL,Channel descriptor control"
|
|
bitfld.long 0x0 28.--30. "DESCR_TYPE,Specifies the descriptor type (not to be confused with the trigger type):" "0: Single transfer,1: 1D transfer,2: 2D transfer,3: Memory copy,4: Scatter transfer,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 27. "DST_TRANSFER_SIZE,Specifies the bus transfer size to the destination location:" "0: As specified by DATA_SIZE,1: Word"
|
|
newline
|
|
bitfld.long 0x0 26. "SRC_TRANSFER_SIZE,Specifies the bus transfer size to the source location:" "0: As specified by DATA_SIZE,1: Word"
|
|
newline
|
|
bitfld.long 0x0 24. "CH_DISABLE,Specifies whether the channel is disabled or not after completion of the current descriptor (independent of the value of the DESCR_NEXT_PTR value):" "0: Channel is not disabled,1: Channel is disabled"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "DATA_SIZE,Specifies the data element size:" "0: Byte,1: Halfword,2: Word,?"
|
|
newline
|
|
bitfld.long 0x0 8. "DATA_PREFETCH,Source data prefetch:" "0: No source data prefetch,1: Source data prefetch"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "TR_IN_TYPE,Specifies the input trigger type (not to be confused with the descriptor type):" "0: A trigger results in the execution of a single..,1: A trigger results in the execution of a single..,2: A trigger results in the execution of the..,3: A trigger results in the execution of the.."
|
|
newline
|
|
bitfld.long 0x0 4.--5. "TR_OUT_TYPE,Specifies when an output trigger is generated:" "0: An output trigger is generated after a single..,1: An output trigger is generated after a single 1D..,2: An output trigger is generated after the..,3: An output trigger is generated after the.."
|
|
newline
|
|
bitfld.long 0x0 2.--3. "INTR_TYPE,Specifies when a completion interrupt is generated (CH_STATUS.INTR_CAUSE is set to COMPLETION):" "0: An interrupt is generated after a single transfer,1: An interrupt is generated after a single 1D..,2: An interrupt is generated after the execution of..,3: An interrupt is generated after the execution of.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "WAIT_FOR_DEACT,Specifies whether the controller should wait for the input trigger to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller with the agent that generated the trigger. This field is.." "0: Do not wait for trigger de-activation,1: Wait for up to 4 cycles,2: Wait for up to 16 cycles,3: Wait indefinitely"
|
|
line.long 0x4 "DESCR_SRC,Channel descriptor source"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Base address of source location."
|
|
line.long 0x8 "DESCR_DST,Channel descriptor destination"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Base address of destination location."
|
|
line.long 0xC "DESCR_X_SIZE,Channel descriptor X size"
|
|
hexmask.long.word 0xC 0.--15. 1. "X_COUNT,Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0 65535] representing 1 through 65536 iterations."
|
|
line.long 0x10 "DESCR_X_INCR,Channel descriptor X increment"
|
|
hexmask.long.word 0x10 16.--31. 1. "DST_X,Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768 32767]. If this field is '0' the destination address is not.."
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "SRC_X,Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768 32767]. If this field is '0' the source address is not incremented."
|
|
line.long 0x14 "DESCR_Y_SIZE,Channel descriptor Y size"
|
|
hexmask.long.word 0x14 0.--15. 1. "Y_COUNT,Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0 65535] representing 1 through 65536 iterations."
|
|
line.long 0x18 "DESCR_Y_INCR,Channel descriptor Y increment"
|
|
hexmask.long.word 0x18 16.--31. 1. "DST_Y,Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-32768 32767]."
|
|
newline
|
|
hexmask.long.word 0x18 0.--15. 1. "SRC_Y,Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-32768 32767]."
|
|
line.long 0x1C "DESCR_NEXT,Channel descriptor next pointer"
|
|
hexmask.long 0x1C 2.--31. 1. "PTR,Address of next descriptor in descriptor list. When this field is '0' this is the last descriptor in the descriptor list."
|
|
group.long ($2+0x80)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 7. "DESCR_BUS_ERROR,Activated (set to '1') on a bus error for a load of the descriptor." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ACTIVE_CH_DISABLED,Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CURR_PTR_NULL,Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DST_MISAL,Activated (set to '1') on a misalignment of the destination address." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SRC_MISAL,Activated (set to '1') on a misalignment of the source address." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DST_BUS_ERROR,Activated (set to '1') on a bus error for a store to the destination." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SRC_BUS_ERROR,Activated (set to '1') on a bus error for a load from the source." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COMPLETION,Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 7. "DESCR_BUS_ERROR,Write this field with '1' to set INTR.DESCR_BUS_ERROR field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ACTIVE_CH_DISABLED,Write this field with '1' to set INTR.ACT_CH_DISABLED field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CURR_PTR_NULL,Write this field with '1' to set INTR.CURR_PTR_NULL field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DST_MISAL,Write this field with '1' to set INTR.DST_MISAL field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SRC_MISAL,Write this field with '1' to set INTR.SRC_MISAL field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DST_BUS_ERROR,Write this field with '1' to set INTR.DST_BUS_ERROR field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "SRC_BUS_ERROR,Write this field with '1' to set INTR.SRC_BUS_ERROR field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "COMPLETION,Write this field with '1' to set INTR.COMPLETION field to '1' (a write of '0' has no effect)." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 7. "DESCR_BUS_ERROR,Mask for INTR.DESCR_BUS_ERROR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ACTIVE_CH_DISABLED,Mask for INTR.ACTIVE_CH_DISABLED interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "CURR_PTR_NULL,Mask for INTR.CURR_PTR_NULL interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "DST_MISAL,Mask for INTR.DST_MISAL interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "SRC_MISAL,Mask for INTR.SRC_MISAL interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "DST_BUS_ERROR,Mask for INTR.DST_BUS_ERROR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "SRC_BUS_ERROR,Mask for INTR.SRC_BUS_ERROR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "COMPLETION,Mask for INTR.COMPLETION interrupt." "0,1"
|
|
rgroup.long ($2+0x8C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 7. "DESCR_BUS_ERROR,Logical and of corresponding INTR.DESCR_BUS_ERROR and INTR_MASK.DESCR_BUS_ERROR fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ACTIVE_CH_DISABLED,Logical and of corresponding INTR.ACTIVE_CH_DISABLED and INTR_MASK.ACTIVE_CH_DISABLED fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CURR_PTR_NULL,Logical and of corresponding INTR.CURR_PTR_NULL and INTR_MASK.CURR_PTR_NULL fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DST_MISAL,Logical and of corresponding INTR.DST_MISAL and INTR_MASK.DST_MISAL fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SRC_MISAL,Logical and of corresponding INTR.SRC_MISAL and INTR_MASK.SRC_MISAL fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DST_BUS_ERROR,Logical and of corresponding INTR.DST_BUS_ERROR and INTR_MASK.DST_BUS_ERROR fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SRC_BUS_ERROR,Logical and of corresponding INTR.SRC_BUS_ERROR and INTR_MASK.SRC_BUS_ERROR fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COMPLETION,Logical and of corresponding INTR.COMPLETION and INTR_MASK.COMPLETION fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x402A0000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 2. (list 0x0 0x1)(list ad:0x402A1000 ad:0x402A1100)
|
|
tree "CH[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0: highest priority,?,?,3: lowest priority"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
newline
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
newline
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long ($2+0x10)++0xB
|
|
line.long 0x0 "IDX,Channel current indices"
|
|
hexmask.long.word 0x0 16.--31. 1. "Y,Specifies the Y loop index with Y_COUNT taken from the current descriptor."
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "X,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "SRC,Channel current source address"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Current address of source location."
|
|
line.long 0x8 "DST,Channel current destination address"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Current address of destination location."
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "CURR,Channel current descriptor pointer"
|
|
hexmask.long 0x0 2.--31. 1. "PTR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
group.long ($2+0x28)++0x3
|
|
line.long 0x0 "TR_CMD,Channle software trigger"
|
|
bitfld.long 0x0 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
rgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "DESCR_STATUS,Channel descriptor status"
|
|
bitfld.long 0x0 31. "VALID,Indicates whether the descriptor information present in DESCR_CTL DESCR_SRC DESCR_DST DESCR_X_SIZE DESCR_X_INCR DESCR_Y_SIZE DESCR_Y_INCR DESCR_NEXT status registers is valid or not." "0,1"
|
|
rgroup.long ($2+0x60)++0x1F
|
|
line.long 0x0 "DESCR_CTL,Channel descriptor control"
|
|
bitfld.long 0x0 28.--30. "DESCR_TYPE,Specifies the descriptor type (not to be confused with the trigger type):" "0: Single transfer,1: 1D transfer,2: 2D transfer,3: Memory copy,4: Scatter transfer,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 27. "DST_TRANSFER_SIZE,Specifies the bus transfer size to the destination location:" "0: As specified by DATA_SIZE,1: Word"
|
|
newline
|
|
bitfld.long 0x0 26. "SRC_TRANSFER_SIZE,Specifies the bus transfer size to the source location:" "0: As specified by DATA_SIZE,1: Word"
|
|
newline
|
|
bitfld.long 0x0 24. "CH_DISABLE,Specifies whether the channel is disabled or not after completion of the current descriptor (independent of the value of the DESCR_NEXT_PTR value):" "0: Channel is not disabled,1: Channel is disabled"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "DATA_SIZE,Specifies the data element size:" "0: Byte,1: Halfword,2: Word,?"
|
|
newline
|
|
bitfld.long 0x0 8. "DATA_PREFETCH,Source data prefetch:" "0: No source data prefetch,1: Source data prefetch"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "TR_IN_TYPE,Specifies the input trigger type (not to be confused with the descriptor type):" "0: A trigger results in the execution of a single..,1: A trigger results in the execution of a single..,2: A trigger results in the execution of the..,3: A trigger results in the execution of the.."
|
|
newline
|
|
bitfld.long 0x0 4.--5. "TR_OUT_TYPE,Specifies when an output trigger is generated:" "0: An output trigger is generated after a single..,1: An output trigger is generated after a single 1D..,2: An output trigger is generated after the..,3: An output trigger is generated after the.."
|
|
newline
|
|
bitfld.long 0x0 2.--3. "INTR_TYPE,Specifies when a completion interrupt is generated (CH_STATUS.INTR_CAUSE is set to COMPLETION):" "0: An interrupt is generated after a single transfer,1: An interrupt is generated after a single 1D..,2: An interrupt is generated after the execution of..,3: An interrupt is generated after the execution of.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "WAIT_FOR_DEACT,Specifies whether the controller should wait for the input trigger to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller with the agent that generated the trigger. This field is.." "0: Do not wait for trigger de-activation,1: Wait for up to 4 cycles,2: Wait for up to 16 cycles,3: Wait indefinitely"
|
|
line.long 0x4 "DESCR_SRC,Channel descriptor source"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Base address of source location."
|
|
line.long 0x8 "DESCR_DST,Channel descriptor destination"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Base address of destination location."
|
|
line.long 0xC "DESCR_X_SIZE,Channel descriptor X size"
|
|
hexmask.long.word 0xC 0.--15. 1. "X_COUNT,Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0 65535] representing 1 through 65536 iterations."
|
|
line.long 0x10 "DESCR_X_INCR,Channel descriptor X increment"
|
|
hexmask.long.word 0x10 16.--31. 1. "DST_X,Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768 32767]. If this field is '0' the destination address is not.."
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "SRC_X,Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768 32767]. If this field is '0' the source address is not incremented."
|
|
line.long 0x14 "DESCR_Y_SIZE,Channel descriptor Y size"
|
|
hexmask.long.word 0x14 0.--15. 1. "Y_COUNT,Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0 65535] representing 1 through 65536 iterations."
|
|
line.long 0x18 "DESCR_Y_INCR,Channel descriptor Y increment"
|
|
hexmask.long.word 0x18 16.--31. 1. "DST_Y,Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-32768 32767]."
|
|
newline
|
|
hexmask.long.word 0x18 0.--15. 1. "SRC_Y,Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-32768 32767]."
|
|
line.long 0x1C "DESCR_NEXT,Channel descriptor next pointer"
|
|
hexmask.long 0x1C 2.--31. 1. "PTR,Address of next descriptor in descriptor list. When this field is '0' this is the last descriptor in the descriptor list."
|
|
group.long ($2+0x80)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 7. "DESCR_BUS_ERROR,Activated (set to '1') on a bus error for a load of the descriptor." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ACTIVE_CH_DISABLED,Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CURR_PTR_NULL,Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DST_MISAL,Activated (set to '1') on a misalignment of the destination address." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SRC_MISAL,Activated (set to '1') on a misalignment of the source address." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DST_BUS_ERROR,Activated (set to '1') on a bus error for a store to the destination." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SRC_BUS_ERROR,Activated (set to '1') on a bus error for a load from the source." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COMPLETION,Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 7. "DESCR_BUS_ERROR,Write this field with '1' to set INTR.DESCR_BUS_ERROR field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ACTIVE_CH_DISABLED,Write this field with '1' to set INTR.ACT_CH_DISABLED field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CURR_PTR_NULL,Write this field with '1' to set INTR.CURR_PTR_NULL field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DST_MISAL,Write this field with '1' to set INTR.DST_MISAL field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SRC_MISAL,Write this field with '1' to set INTR.SRC_MISAL field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DST_BUS_ERROR,Write this field with '1' to set INTR.DST_BUS_ERROR field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "SRC_BUS_ERROR,Write this field with '1' to set INTR.SRC_BUS_ERROR field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "COMPLETION,Write this field with '1' to set INTR.COMPLETION field to '1' (a write of '0' has no effect)." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 7. "DESCR_BUS_ERROR,Mask for INTR.DESCR_BUS_ERROR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ACTIVE_CH_DISABLED,Mask for INTR.ACTIVE_CH_DISABLED interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "CURR_PTR_NULL,Mask for INTR.CURR_PTR_NULL interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "DST_MISAL,Mask for INTR.DST_MISAL interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "SRC_MISAL,Mask for INTR.SRC_MISAL interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "DST_BUS_ERROR,Mask for INTR.DST_BUS_ERROR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "SRC_BUS_ERROR,Mask for INTR.SRC_BUS_ERROR interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "COMPLETION,Mask for INTR.COMPLETION interrupt." "0,1"
|
|
rgroup.long ($2+0x8C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 7. "DESCR_BUS_ERROR,Logical and of corresponding INTR.DESCR_BUS_ERROR and INTR_MASK.DESCR_BUS_ERROR fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ACTIVE_CH_DISABLED,Logical and of corresponding INTR.ACTIVE_CH_DISABLED and INTR_MASK.ACTIVE_CH_DISABLED fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CURR_PTR_NULL,Logical and of corresponding INTR.CURR_PTR_NULL and INTR_MASK.CURR_PTR_NULL fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DST_MISAL,Logical and of corresponding INTR.DST_MISAL and INTR_MASK.DST_MISAL fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SRC_MISAL,Logical and of corresponding INTR.SRC_MISAL and INTR_MASK.SRC_MISAL fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DST_BUS_ERROR,Logical and of corresponding INTR.DST_BUS_ERROR and INTR_MASK.DST_BUS_ERROR fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SRC_BUS_ERROR,Logical and of corresponding INTR.SRC_BUS_ERROR and INTR_MASK.SRC_BUS_ERROR fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COMPLETION,Logical and of corresponding INTR.COMPLETION and INTR_MASK.COMPLETION fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x402A0000
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "DW (Datawire Controller)"
|
|
base ad:0x0
|
|
sif (cpuis("CY8C6??6*")||cpuis("CYB06??6*")||cpuis("CYS06??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??7*")||cpuis("CYS06??7*"))
|
|
tree "DW0"
|
|
base ad:0x40280000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: Disabled,1: Enabled"
|
|
rgroup.long 0x4++0x7
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "ACTIVE,Active channel present:" "0: No,1: Yes"
|
|
bitfld.long 0x0 20.--22. "STATE,State of the DW controller." "0: Default/inactive state,1: Loading descriptor,2: Loading data element from source location,3: Storing data element to destination location,4: Update of active control information,5: Wait for trigger de-activation,?,?"
|
|
bitfld.long 0x0 18. "PREEMPTABLE,Active channel preemptable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "PRIO,Active channel priority." "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "CH_IDX,Active channel index."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Active channel protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Active channel non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Active channel secure/non-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,Active channel user/privileged access control:" "0: user mode,1: privileged mode"
|
|
line.long 0x4 "PENDING,Pending channels"
|
|
hexmask.long 0x4 0.--31. 1. "CH_PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))."
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "STATUS_INTR,System interrupt control"
|
|
hexmask.long 0x0 0.--31. 1. "CH,Reflects the INTR.CH bit fields of all channels."
|
|
line.long 0x4 "STATUS_INTR_MASKED,Status of interrupts masked"
|
|
hexmask.long 0x4 0.--31. 1. "CH,Reflects the INTR_MASKED.CH bit fields of all channels."
|
|
rgroup.long 0x20++0xB
|
|
line.long 0x0 "ACT_DESCR_CTL,Active descriptor control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Copy of DESCR_CTL of the currently active descriptor."
|
|
line.long 0x4 "ACT_DESCR_SRC,Active descriptor source"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_SRC of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_DST,Active descriptor destination"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Copy of DESCR_DST of the currently active descriptor."
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "ACT_DESCR_X_CTL,Active descriptor X loop control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Copy of DESCR_X_CTL of the currently active descriptor."
|
|
line.long 0x4 "ACT_DESCR_Y_CTL,Active descriptor Y loop control"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_Y_CTL of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_NEXT_PTR,Active descriptor next pointer"
|
|
hexmask.long 0x8 2.--31. 1. "ADDR,Copy of DESCR_NEXT_PTR of the currently active descriptor."
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ACT_SRC,Active source"
|
|
hexmask.long 0x0 0.--31. 1. "SRC_ADDR,Current address of source location."
|
|
line.long 0x4 "ACT_DST,Active destination"
|
|
hexmask.long 0x4 0.--31. 1. "DST_ADDR,Current address of destination location."
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40280800 ad:0x40280820 ad:0x40280840 ad:0x40280860 ad:0x40280880 ad:0x402808A0 ad:0x402808C0 ad:0x402808E0 ad:0x40280900 ad:0x40280920 ad:0x40280940 ad:0x40280960 ad:0x40280980 ad:0x402809A0 ad:0x402809C0 ad:0x402809E0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 18. "PREEMPTABLE,Specifies if the channel is preemptable." "0: Not preemptable,1: Preemptable"
|
|
bitfld.long 0x0 16.--17. "PRIO,Channel priority:" "0: highest priority,?,?,3: lowest priority"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CYB06??6*")||cpuis("CYS06??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??7*")||cpuis("CYS06??7*"))
|
|
tree "DW1"
|
|
base ad:0x40281000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: Disabled,1: Enabled"
|
|
rgroup.long 0x4++0x7
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "ACTIVE,Active channel present:" "0: No,1: Yes"
|
|
bitfld.long 0x0 20.--22. "STATE,State of the DW controller." "0: Default/inactive state,1: Loading descriptor,2: Loading data element from source location,3: Storing data element to destination location,4: Update of active control information,5: Wait for trigger de-activation,?,?"
|
|
bitfld.long 0x0 18. "PREEMPTABLE,Active channel preemptable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "PRIO,Active channel priority." "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "CH_IDX,Active channel index."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Active channel protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Active channel non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Active channel secure/non-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,Active channel user/privileged access control:" "0: user mode,1: privileged mode"
|
|
line.long 0x4 "PENDING,Pending channels"
|
|
hexmask.long 0x4 0.--31. 1. "CH_PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))."
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "STATUS_INTR,System interrupt control"
|
|
hexmask.long 0x0 0.--31. 1. "CH,Reflects the INTR.CH bit fields of all channels."
|
|
line.long 0x4 "STATUS_INTR_MASKED,Status of interrupts masked"
|
|
hexmask.long 0x4 0.--31. 1. "CH,Reflects the INTR_MASKED.CH bit fields of all channels."
|
|
rgroup.long 0x20++0xB
|
|
line.long 0x0 "ACT_DESCR_CTL,Active descriptor control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Copy of DESCR_CTL of the currently active descriptor."
|
|
line.long 0x4 "ACT_DESCR_SRC,Active descriptor source"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_SRC of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_DST,Active descriptor destination"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Copy of DESCR_DST of the currently active descriptor."
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "ACT_DESCR_X_CTL,Active descriptor X loop control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Copy of DESCR_X_CTL of the currently active descriptor."
|
|
line.long 0x4 "ACT_DESCR_Y_CTL,Active descriptor Y loop control"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_Y_CTL of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_NEXT_PTR,Active descriptor next pointer"
|
|
hexmask.long 0x8 2.--31. 1. "ADDR,Copy of DESCR_NEXT_PTR of the currently active descriptor."
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ACT_SRC,Active source"
|
|
hexmask.long 0x0 0.--31. 1. "SRC_ADDR,Current address of source location."
|
|
line.long 0x4 "ACT_DST,Active destination"
|
|
hexmask.long 0x4 0.--31. 1. "DST_ADDR,Current address of destination location."
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40281800 ad:0x40281820 ad:0x40281840 ad:0x40281860 ad:0x40281880 ad:0x402818A0 ad:0x402818C0 ad:0x402818E0 ad:0x40281900 ad:0x40281920 ad:0x40281940 ad:0x40281960 ad:0x40281980 ad:0x402819A0 ad:0x402819C0 ad:0x402819E0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 18. "PREEMPTABLE,Specifies if the channel is preemptable." "0: Not preemptable,1: Preemptable"
|
|
bitfld.long 0x0 16.--17. "PRIO,Channel priority:" "0: highest priority,?,?,3: lowest priority"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CYB06??8*")||cpuis("CYS06??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??A*")||cpuis("CYS06??A*"))
|
|
tree "DW0"
|
|
base ad:0x40280000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 1. "ECC_INJ_EN,Enable parity injection for SRAM." "0,1"
|
|
bitfld.long 0x0 0. "ECC_EN,Enable ECC checking:" "0: Disabled,1: Enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "ACTIVE,Active channel present:" "0: No,1: Yes"
|
|
bitfld.long 0x0 28.--30. "STATE,State of the DW controller." "0: Default/inactive state,1: Loading descriptor,2: Loading data element from source location,3: Storing data element to destination location,4: CRC functionality,5: Update of active control information,6: Error,?"
|
|
hexmask.long.word 0x0 16.--24. 1. "CH_IDX,Active channel index."
|
|
newline
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Active channel preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Active channel priority." "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Active channel protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Active channel non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Active channel secure/non-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,Active channel user/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long 0x20++0xB
|
|
line.long 0x0 "ACT_DESCR_CTL,Active descriptor control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "ACT_DESCR_SRC,Active descriptor source"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_SRC of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_DST,Active descriptor destination"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Copy of DESCR_DST of the currently active descriptor."
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "ACT_DESCR_X_CTL,Active descriptor X loop control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Copy of DESCR_X_CTL of the currently active descriptor."
|
|
line.long 0x4 "ACT_DESCR_Y_CTL,Active descriptor Y loop control"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_Y_CTL of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_NEXT_PTR,Active descriptor next pointer"
|
|
hexmask.long 0x8 2.--31. 1. "ADDR,Copy of DESCR_NEXT_PTR of the currently active descriptor."
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ACT_SRC,Active source"
|
|
hexmask.long 0x0 0.--31. 1. "SRC_ADDR,Current address of source location."
|
|
line.long 0x4 "ACT_DST,Active destination"
|
|
hexmask.long 0x4 0.--31. 1. "DST_ADDR,Current address of destination location."
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.word 0x0 0.--9. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CRC_CTL,CRC control"
|
|
bitfld.long 0x0 8. "REM_REVERSE,Specifies whether the remainder is bit reversed (reversal is performed after XORing):" "0: No,1: Yes"
|
|
bitfld.long 0x0 0. "DATA_REVERSE,Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):" "0: Most significant bit,1: Least significant bit"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "CRC_DATA_CTL,CRC data control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_XOR,Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal."
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "CRC_POL_CTL,CRC polynomial control"
|
|
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less.."
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "CRC_LFSR_CTL,CRC LFSR control"
|
|
hexmask.long 0x0 0.--31. 1. "LFSR32,State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value."
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "CRC_REM_CTL,CRC remainder control"
|
|
hexmask.long 0x0 0.--31. 1. "REM_XOR,Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal."
|
|
rgroup.long 0x148++0x3
|
|
line.long 0x0 "CRC_REM_RESULT,CRC remainder result"
|
|
hexmask.long 0x0 0.--31. 1. "REM,Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40288000 ad:0x40288040 ad:0x40288080 ad:0x402880C0 ad:0x40288100 ad:0x40288140 ad:0x40288180 ad:0x402881C0 ad:0x40288200 ad:0x40288240 ad:0x40288280 ad:0x402882C0 ad:0x40288300 ad:0x40288340 ad:0x40288380 ad:0x402883C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0: Not preemptable,1: Preemptable"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0: highest priority,?,?,3: lowest priority"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 13. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C)(list ad:0x40288400 ad:0x40288440 ad:0x40288480 ad:0x402884C0 ad:0x40288500 ad:0x40288540 ad:0x40288580 ad:0x402885C0 ad:0x40288600 ad:0x40288640 ad:0x40288680 ad:0x402886C0 ad:0x40288700)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0: Not preemptable,1: Preemptable"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0: highest priority,?,?,3: lowest priority"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CYB06??8*")||cpuis("CYS06??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??A*")||cpuis("CYS06??A*"))
|
|
tree "DW1"
|
|
base ad:0x40290000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 1. "ECC_INJ_EN,Enable parity injection for SRAM." "0,1"
|
|
bitfld.long 0x0 0. "ECC_EN,Enable ECC checking:" "0: Disabled,1: Enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "ACTIVE,Active channel present:" "0: No,1: Yes"
|
|
bitfld.long 0x0 28.--30. "STATE,State of the DW controller." "0: Default/inactive state,1: Loading descriptor,2: Loading data element from source location,3: Storing data element to destination location,4: CRC functionality,5: Update of active control information,6: Error,?"
|
|
hexmask.long.word 0x0 16.--24. 1. "CH_IDX,Active channel index."
|
|
newline
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Active channel preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Active channel priority." "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Active channel protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Active channel non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Active channel secure/non-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,Active channel user/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long 0x20++0xB
|
|
line.long 0x0 "ACT_DESCR_CTL,Active descriptor control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "ACT_DESCR_SRC,Active descriptor source"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_SRC of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_DST,Active descriptor destination"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Copy of DESCR_DST of the currently active descriptor."
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "ACT_DESCR_X_CTL,Active descriptor X loop control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Copy of DESCR_X_CTL of the currently active descriptor."
|
|
line.long 0x4 "ACT_DESCR_Y_CTL,Active descriptor Y loop control"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_Y_CTL of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_NEXT_PTR,Active descriptor next pointer"
|
|
hexmask.long 0x8 2.--31. 1. "ADDR,Copy of DESCR_NEXT_PTR of the currently active descriptor."
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ACT_SRC,Active source"
|
|
hexmask.long 0x0 0.--31. 1. "SRC_ADDR,Current address of source location."
|
|
line.long 0x4 "ACT_DST,Active destination"
|
|
hexmask.long 0x4 0.--31. 1. "DST_ADDR,Current address of destination location."
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.word 0x0 0.--9. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CRC_CTL,CRC control"
|
|
bitfld.long 0x0 8. "REM_REVERSE,Specifies whether the remainder is bit reversed (reversal is performed after XORing):" "0: No,1: Yes"
|
|
bitfld.long 0x0 0. "DATA_REVERSE,Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):" "0: Most significant bit,1: Least significant bit"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "CRC_DATA_CTL,CRC data control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_XOR,Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal."
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "CRC_POL_CTL,CRC polynomial control"
|
|
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less.."
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "CRC_LFSR_CTL,CRC LFSR control"
|
|
hexmask.long 0x0 0.--31. 1. "LFSR32,State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value."
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "CRC_REM_CTL,CRC remainder control"
|
|
hexmask.long 0x0 0.--31. 1. "REM_XOR,Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal."
|
|
rgroup.long 0x148++0x3
|
|
line.long 0x0 "CRC_REM_RESULT,CRC remainder result"
|
|
hexmask.long 0x0 0.--31. 1. "REM,Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40298000 ad:0x40298040 ad:0x40298080 ad:0x402980C0 ad:0x40298100 ad:0x40298140 ad:0x40298180 ad:0x402981C0 ad:0x40298200 ad:0x40298240 ad:0x40298280 ad:0x402982C0 ad:0x40298300 ad:0x40298340 ad:0x40298380 ad:0x402983C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0: Not preemptable,1: Preemptable"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0: highest priority,?,?,3: lowest priority"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 13. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C)(list ad:0x40298400 ad:0x40298440 ad:0x40298480 ad:0x402984C0 ad:0x40298500 ad:0x40298540 ad:0x40298580 ad:0x402985C0 ad:0x40298600 ad:0x40298640 ad:0x40298680 ad:0x402986C0 ad:0x40298700)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0: Not preemptable,1: Preemptable"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0: highest priority,?,?,3: lowest priority"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYS06??4*")||cpuis("CYS06??5*"))
|
|
tree "DW0"
|
|
base ad:0x40280000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 1. "ECC_INJ_EN,Enable parity injection for SRAM." "0,1"
|
|
bitfld.long 0x0 0. "ECC_EN,Enable ECC checking:" "0: Disabled,1: Enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "ACTIVE,Active channel present:" "0: No,1: Yes"
|
|
bitfld.long 0x0 28.--30. "STATE,State of the DW controller." "0: Default/inactive state,1: Loading descriptor,2: Loading data element from source location,3: Storing data element to destination location,4: CRC functionality,5: Update of active control information,6: Error,?"
|
|
hexmask.long.word 0x0 16.--24. 1. "CH_IDX,Active channel index."
|
|
newline
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Active channel preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Active channel priority." "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Active channel protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Active channel non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Active channel secure/non-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,Active channel user/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long 0x20++0xB
|
|
line.long 0x0 "ACT_DESCR_CTL,Active descriptor control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "ACT_DESCR_SRC,Active descriptor source"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_SRC of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_DST,Active descriptor destination"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Copy of DESCR_DST of the currently active descriptor."
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "ACT_DESCR_X_CTL,Active descriptor X loop control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Copy of DESCR_X_CTL of the currently active descriptor."
|
|
line.long 0x4 "ACT_DESCR_Y_CTL,Active descriptor Y loop control"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_Y_CTL of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_NEXT_PTR,Active descriptor next pointer"
|
|
hexmask.long 0x8 2.--31. 1. "ADDR,Copy of DESCR_NEXT_PTR of the currently active descriptor."
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ACT_SRC,Active source"
|
|
hexmask.long 0x0 0.--31. 1. "SRC_ADDR,Current address of source location."
|
|
line.long 0x4 "ACT_DST,Active destination"
|
|
hexmask.long 0x4 0.--31. 1. "DST_ADDR,Current address of destination location."
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.word 0x0 0.--9. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CRC_CTL,CRC control"
|
|
bitfld.long 0x0 8. "REM_REVERSE,Specifies whether the remainder is bit reversed (reversal is performed after XORing):" "0: No,1: Yes"
|
|
bitfld.long 0x0 0. "DATA_REVERSE,Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):" "0: Most significant bit,1: Least significant bit"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "CRC_DATA_CTL,CRC data control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_XOR,Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal."
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "CRC_POL_CTL,CRC polynomial control"
|
|
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less.."
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "CRC_LFSR_CTL,CRC LFSR control"
|
|
hexmask.long 0x0 0.--31. 1. "LFSR32,State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value."
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "CRC_REM_CTL,CRC remainder control"
|
|
hexmask.long 0x0 0.--31. 1. "REM_XOR,Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal."
|
|
rgroup.long 0x148++0x3
|
|
line.long 0x0 "CRC_REM_RESULT,CRC remainder result"
|
|
hexmask.long 0x0 0.--31. 1. "REM,Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40288000 ad:0x40288040 ad:0x40288080 ad:0x402880C0 ad:0x40288100 ad:0x40288140 ad:0x40288180 ad:0x402881C0 ad:0x40288200 ad:0x40288240 ad:0x40288280 ad:0x402882C0 ad:0x40288300 ad:0x40288340 ad:0x40288380 ad:0x402883C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0: Not preemptable,1: Preemptable"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0: highest priority,?,?,3: lowest priority"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40288400 ad:0x40288440 ad:0x40288480 ad:0x402884C0 ad:0x40288500 ad:0x40288540 ad:0x40288580 ad:0x402885C0 ad:0x40288600 ad:0x40288640 ad:0x40288680 ad:0x402886C0 ad:0x40288700 ad:0x40288740 ad:0x40288780 ad:0x402887C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0: Not preemptable,1: Preemptable"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0: highest priority,?,?,3: lowest priority"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYS06??4*")||cpuis("CYS06??5*"))
|
|
tree "DW1"
|
|
base ad:0x40290000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 1. "ECC_INJ_EN,Enable parity injection for SRAM." "0,1"
|
|
bitfld.long 0x0 0. "ECC_EN,Enable ECC checking:" "0: Disabled,1: Enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "ACTIVE,Active channel present:" "0: No,1: Yes"
|
|
bitfld.long 0x0 28.--30. "STATE,State of the DW controller." "0: Default/inactive state,1: Loading descriptor,2: Loading data element from source location,3: Storing data element to destination location,4: CRC functionality,5: Update of active control information,6: Error,?"
|
|
hexmask.long.word 0x0 16.--24. 1. "CH_IDX,Active channel index."
|
|
newline
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Active channel preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Active channel priority." "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Active channel protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Active channel non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Active channel secure/non-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,Active channel user/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long 0x20++0xB
|
|
line.long 0x0 "ACT_DESCR_CTL,Active descriptor control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "ACT_DESCR_SRC,Active descriptor source"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_SRC of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_DST,Active descriptor destination"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Copy of DESCR_DST of the currently active descriptor."
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "ACT_DESCR_X_CTL,Active descriptor X loop control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Copy of DESCR_X_CTL of the currently active descriptor."
|
|
line.long 0x4 "ACT_DESCR_Y_CTL,Active descriptor Y loop control"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_Y_CTL of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_NEXT_PTR,Active descriptor next pointer"
|
|
hexmask.long 0x8 2.--31. 1. "ADDR,Copy of DESCR_NEXT_PTR of the currently active descriptor."
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ACT_SRC,Active source"
|
|
hexmask.long 0x0 0.--31. 1. "SRC_ADDR,Current address of source location."
|
|
line.long 0x4 "ACT_DST,Active destination"
|
|
hexmask.long 0x4 0.--31. 1. "DST_ADDR,Current address of destination location."
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.word 0x0 0.--9. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CRC_CTL,CRC control"
|
|
bitfld.long 0x0 8. "REM_REVERSE,Specifies whether the remainder is bit reversed (reversal is performed after XORing):" "0: No,1: Yes"
|
|
bitfld.long 0x0 0. "DATA_REVERSE,Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):" "0: Most significant bit,1: Least significant bit"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "CRC_DATA_CTL,CRC data control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_XOR,Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal."
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "CRC_POL_CTL,CRC polynomial control"
|
|
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less.."
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "CRC_LFSR_CTL,CRC LFSR control"
|
|
hexmask.long 0x0 0.--31. 1. "LFSR32,State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value."
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "CRC_REM_CTL,CRC remainder control"
|
|
hexmask.long 0x0 0.--31. 1. "REM_XOR,Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal."
|
|
rgroup.long 0x148++0x3
|
|
line.long 0x0 "CRC_REM_RESULT,CRC remainder result"
|
|
hexmask.long 0x0 0.--31. 1. "REM,Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40298000 ad:0x40298040 ad:0x40298080 ad:0x402980C0 ad:0x40298100 ad:0x40298140 ad:0x40298180 ad:0x402981C0 ad:0x40298200 ad:0x40298240 ad:0x40298280 ad:0x402982C0 ad:0x40298300 ad:0x40298340 ad:0x40298380 ad:0x402983C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0: Not preemptable,1: Preemptable"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0: highest priority,?,?,3: lowest priority"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40298400 ad:0x40298440 ad:0x40298480 ad:0x402984C0 ad:0x40298500 ad:0x40298540 ad:0x40298580 ad:0x402985C0 ad:0x40298600 ad:0x40298640 ad:0x40298680 ad:0x402986C0 ad:0x40298700 ad:0x40298740 ad:0x40298780 ad:0x402987C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0: Not preemptable,1: Preemptable"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0: highest priority,?,?,3: lowest priority"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "EFUSE"
|
|
base ad:0x402C0000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: Disabled,1: Enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CMD,Command"
|
|
bitfld.long 0x0 31. "START,FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed." "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "MACRO_ADDR,Macro address. This field specifies an eFUSE macro."
|
|
hexmask.long.byte 0x0 8.--12. 1. "BYTE_ADDR,Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B)."
|
|
bitfld.long 0x0 4.--6. "BIT_ADDR,Bit address. This field specifies a bit within a Byte." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "BIT_DATA,Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR BYTE_ADDR and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro." "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SEQ_DEFAULT,Sequencer Default value"
|
|
bitfld.long 0x0 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x0 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x0 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x0 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0x0 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x0 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x0 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
group.long 0x40++0x17
|
|
line.long 0x0 "SEQ_READ_CTL_0,Sequencer read control 0"
|
|
bitfld.long 0x0 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x0 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x0 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x0 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x0 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0x0 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x0 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x0 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x4 "SEQ_READ_CTL_1,Sequencer read control 1"
|
|
bitfld.long 0x4 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x4 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x4 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x4 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x4 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0x4 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x4 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x4 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x8 "SEQ_READ_CTL_2,Sequencer read control 2"
|
|
bitfld.long 0x8 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x8 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x8 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x8 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x8 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0x8 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x8 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x8 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0xC "SEQ_READ_CTL_3,Sequencer read control 3"
|
|
bitfld.long 0xC 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0xC 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0xC 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0xC 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0xC 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0xC 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0xC 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0xC 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
newline
|
|
hexmask.long.word 0xC 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x10 "SEQ_READ_CTL_4,Sequencer read control 4"
|
|
bitfld.long 0x10 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x10 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x10 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x10 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x10 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0x10 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x10 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x10 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
newline
|
|
hexmask.long.word 0x10 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x14 "SEQ_READ_CTL_5,Sequencer read control 5"
|
|
bitfld.long 0x14 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x14 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x14 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x14 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x14 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0x14 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x14 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x14 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
newline
|
|
hexmask.long.word 0x14 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
group.long 0x60++0x17
|
|
line.long 0x0 "SEQ_PROGRAM_CTL_0,Sequencer program control 0"
|
|
bitfld.long 0x0 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x0 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x0 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x0 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x0 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0x0 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x0 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x0 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x4 "SEQ_PROGRAM_CTL_1,Sequencer program control 1"
|
|
bitfld.long 0x4 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x4 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x4 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x4 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x4 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0x4 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x4 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x4 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x8 "SEQ_PROGRAM_CTL_2,Sequencer program control 2"
|
|
bitfld.long 0x8 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x8 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x8 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x8 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x8 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0x8 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x8 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x8 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0xC "SEQ_PROGRAM_CTL_3,Sequencer program control 3"
|
|
bitfld.long 0xC 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0xC 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0xC 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0xC 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0xC 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0xC 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0xC 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0xC 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
newline
|
|
hexmask.long.word 0xC 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x10 "SEQ_PROGRAM_CTL_4,Sequencer program control 4"
|
|
bitfld.long 0x10 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x10 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x10 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x10 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x10 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0x10 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x10 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x10 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
newline
|
|
hexmask.long.word 0x10 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x14 "SEQ_PROGRAM_CTL_5,Sequencer program control 5"
|
|
bitfld.long 0x14 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x14 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x14 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x14 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x14 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0x14 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x14 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x14 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
newline
|
|
hexmask.long.word 0x14 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
tree.end
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x40220000
|
|
elif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
base ad:0x40210000
|
|
endif
|
|
tree "FAULT (Fault Structures)"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 2. (list 0x0 0x1)(list ad:0x40220000 ad:0x40220100)
|
|
tree "STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Fault control"
|
|
bitfld.long 0x0 2. "RESET_REQ_EN,Reset request enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 1. "OUT_EN,IO output signal enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "TR_EN,Trigger output enable:" "0: Disabled,1: Enabled"
|
|
group.long ($2+0xC)++0x3
|
|
line.long 0x0 "STATUS,Fault status"
|
|
bitfld.long 0x0 31. "VALID,Valid indication:" "0: Invalid,1: Valid"
|
|
hexmask.long.byte 0x0 0.--6. 1. "IDX,The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "DATA[$1],Fault data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Captured fault source data."
|
|
repeat.end
|
|
rgroup.long ($2+0x40)++0xB
|
|
line.long 0x0 "PENDING0,Fault pending 0"
|
|
hexmask.long 0x0 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
line.long 0x4 "PENDING1,Fault pending 1"
|
|
hexmask.long 0x4 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
line.long 0x8 "PENDING2,Fault pending 2"
|
|
hexmask.long 0x8 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
group.long ($2+0x50)++0xB
|
|
line.long 0x0 "MASK0,Fault mask 0"
|
|
hexmask.long 0x0 0.--31. 1. "SOURCE,Fault source enables:"
|
|
line.long 0x4 "MASK1,Fault mask 1"
|
|
hexmask.long 0x4 0.--31. 1. "SOURCE,Fault source enables:"
|
|
line.long 0x8 "MASK2,Fault mask 2"
|
|
hexmask.long 0x8 0.--31. 1. "SOURCE,Fault source enables:"
|
|
group.long ($2+0xC0)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 0. "FAULT,This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured:" "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 0. "FAULT,SW writes a '1' to this field to set the corresponding field in the INTR register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 0. "FAULT,Mask bit for corresponding field in the INTR register." "0,1"
|
|
rgroup.long ($2+0xCC)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "FAULT,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40220000
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 2. (list 0x0 0x1)(list ad:0x40210000 ad:0x40210100)
|
|
tree "STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Fault control"
|
|
bitfld.long 0x0 2. "RESET_REQ_EN,Reset request enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 1. "OUT_EN,IO output signal enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "TR_EN,Trigger output enable:" "0: Disabled,1: Enabled"
|
|
group.long ($2+0xC)++0x3
|
|
line.long 0x0 "STATUS,Fault status"
|
|
bitfld.long 0x0 31. "VALID,Valid indication:" "0: Invalid,1: Valid"
|
|
hexmask.long.byte 0x0 0.--6. 1. "IDX,The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "DATA[$1],Fault data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Captured fault source data."
|
|
repeat.end
|
|
rgroup.long ($2+0x40)++0xB
|
|
line.long 0x0 "PENDING0,Fault pending 0"
|
|
hexmask.long 0x0 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
line.long 0x4 "PENDING1,Fault pending 1"
|
|
hexmask.long 0x4 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
line.long 0x8 "PENDING2,Fault pending 2"
|
|
hexmask.long 0x8 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
group.long ($2+0x50)++0xB
|
|
line.long 0x0 "MASK0,Fault mask 0"
|
|
hexmask.long 0x0 0.--31. 1. "SOURCE,Fault source enables:"
|
|
line.long 0x4 "MASK1,Fault mask 1"
|
|
hexmask.long 0x4 0.--31. 1. "SOURCE,Fault source enables:"
|
|
line.long 0x8 "MASK2,Fault mask 2"
|
|
hexmask.long 0x8 0.--31. 1. "SOURCE,Fault source enables:"
|
|
group.long ($2+0xC0)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 0. "FAULT,This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured:" "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 0. "FAULT,SW writes a '1' to this field to set the corresponding field in the INTR register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 0. "FAULT,Mask bit for corresponding field in the INTR register." "0,1"
|
|
rgroup.long ($2+0xCC)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "FAULT,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40220000
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 2. (list 0x0 0x1)(list ad:0x40210000 ad:0x40210100)
|
|
tree "STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Fault control"
|
|
bitfld.long 0x0 2. "RESET_REQ_EN,Reset request enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 1. "OUT_EN,IO output signal enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "TR_EN,Trigger output enable:" "0: Disabled,1: Enabled"
|
|
group.long ($2+0xC)++0x3
|
|
line.long 0x0 "STATUS,Fault status"
|
|
bitfld.long 0x0 31. "VALID,Valid indication:" "0: Invalid,1: Valid"
|
|
hexmask.long.byte 0x0 0.--6. 1. "IDX,The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "DATA[$1],Fault data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Captured fault source data."
|
|
repeat.end
|
|
rgroup.long ($2+0x40)++0xB
|
|
line.long 0x0 "PENDING0,Fault pending 0"
|
|
hexmask.long 0x0 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
line.long 0x4 "PENDING1,Fault pending 1"
|
|
hexmask.long 0x4 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
line.long 0x8 "PENDING2,Fault pending 2"
|
|
hexmask.long 0x8 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
group.long ($2+0x50)++0xB
|
|
line.long 0x0 "MASK0,Fault mask 0"
|
|
hexmask.long 0x0 0.--31. 1. "SOURCE,Fault source enables:"
|
|
line.long 0x4 "MASK1,Fault mask 1"
|
|
hexmask.long 0x4 0.--31. 1. "SOURCE,Fault source enables:"
|
|
line.long 0x8 "MASK2,Fault mask 2"
|
|
hexmask.long 0x8 0.--31. 1. "SOURCE,Fault source enables:"
|
|
group.long ($2+0xC0)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 0. "FAULT,This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured:" "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 0. "FAULT,SW writes a '1' to this field to set the corresponding field in the INTR register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 0. "FAULT,Mask bit for corresponding field in the INTR register." "0,1"
|
|
rgroup.long ($2+0xCC)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "FAULT,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40220000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 2. (list 0x0 0x1)(list ad:0x40210000 ad:0x40210100)
|
|
tree "STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Fault control"
|
|
bitfld.long 0x0 2. "RESET_REQ_EN,Reset request enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 1. "OUT_EN,IO output signal enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "TR_EN,Trigger output enable:" "0: Disabled,1: Enabled"
|
|
group.long ($2+0xC)++0x3
|
|
line.long 0x0 "STATUS,Fault status"
|
|
bitfld.long 0x0 31. "VALID,Valid indication:" "0: Invalid,1: Valid"
|
|
hexmask.long.byte 0x0 0.--6. 1. "IDX,The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "DATA[$1],Fault data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Captured fault source data."
|
|
repeat.end
|
|
rgroup.long ($2+0x40)++0xB
|
|
line.long 0x0 "PENDING0,Fault pending 0"
|
|
hexmask.long 0x0 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
line.long 0x4 "PENDING1,Fault pending 1"
|
|
hexmask.long 0x4 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
line.long 0x8 "PENDING2,Fault pending 2"
|
|
hexmask.long 0x8 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
group.long ($2+0x50)++0xB
|
|
line.long 0x0 "MASK0,Fault mask 0"
|
|
hexmask.long 0x0 0.--31. 1. "SOURCE,Fault source enables:"
|
|
line.long 0x4 "MASK1,Fault mask 1"
|
|
hexmask.long 0x4 0.--31. 1. "SOURCE,Fault source enables:"
|
|
line.long 0x8 "MASK2,Fault mask 2"
|
|
hexmask.long 0x8 0.--31. 1. "SOURCE,Fault source enables:"
|
|
group.long ($2+0xC0)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 0. "FAULT,This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured:" "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 0. "FAULT,SW writes a '1' to this field to set the corresponding field in the INTR register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 0. "FAULT,Mask bit for corresponding field in the INTR register." "0,1"
|
|
rgroup.long ($2+0xCC)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "FAULT,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40220000
|
|
endif
|
|
tree.end
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x40250000
|
|
elif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
base ad:0x40240000
|
|
endif
|
|
tree "FLASHC (Flash Controller)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "FLASH_CTL,Control"
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x0 22. "WORK_ERR_SILENT,N/A" "0,1"
|
|
bitfld.long 0x0 21. "WORK_ECC_INJ_EN,N/A" "0,1"
|
|
bitfld.long 0x0 20. "WORK_ECC_EN,N/A" "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
bitfld.long 0x0 22. "WORK_ERR_SILENT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "WORK_ECC_INJ_EN,N/A" "0,1"
|
|
bitfld.long 0x0 20. "WORK_ECC_EN,N/A" "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
bitfld.long 0x0 22. "WORK_ERR_SILENT,N/A" "0,1"
|
|
bitfld.long 0x0 21. "WORK_ECC_INJ_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "WORK_ECC_EN,N/A" "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x0 18. "MAIN_ERR_SILENT,N/A" "0,1"
|
|
bitfld.long 0x0 17. "MAIN_ECC_INJ_EN,N/A" "0,1"
|
|
bitfld.long 0x0 16. "MAIN_ECC_EN,N/A" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
bitfld.long 0x0 18. "MAIN_ERR_SILENT,N/A" "0,1"
|
|
bitfld.long 0x0 17. "MAIN_ECC_INJ_EN,N/A" "0,1"
|
|
bitfld.long 0x0 16. "MAIN_ECC_EN,N/A" "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
bitfld.long 0x0 18. "MAIN_ERR_SILENT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MAIN_ECC_INJ_EN,N/A" "0,1"
|
|
bitfld.long 0x0 16. "MAIN_ECC_EN,N/A" "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x0 13. "WORK_BANK_MODE,N/A" "0,1"
|
|
bitfld.long 0x0 12. "MAIN_BANK_MODE,N/A" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
bitfld.long 0x0 13. "WORK_BANK_MODE,N/A" "0,1"
|
|
bitfld.long 0x0 12. "MAIN_BANK_MODE,N/A" "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
bitfld.long 0x0 13. "WORK_BANK_MODE,N/A" "0,1"
|
|
bitfld.long 0x0 12. "MAIN_BANK_MODE,N/A" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x0 9. "WORK_MAP,N/A" "0,1"
|
|
bitfld.long 0x0 8. "MAIN_MAP,N/A" "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
bitfld.long 0x0 9. "WORK_MAP,N/A" "0,1"
|
|
bitfld.long 0x0 8. "MAIN_MAP,N/A" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
bitfld.long 0x0 9. "WORK_MAP,N/A" "0,1"
|
|
bitfld.long 0x0 8. "MAIN_MAP,N/A" "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
bitfld.long 0x0 8. "REMAP,Specifies remapping of FLASH macro main region." "0: [0x1004:0000,1: [0x1006:0000"
|
|
endif
|
|
hexmask.long.byte 0x0 0.--3. 1. "MAIN_WS,FLASH macro main interface wait states:"
|
|
line.long 0x4 "FLASH_PWR_CTL,Flash power control"
|
|
bitfld.long 0x4 1. "ENABLE_HV,Controls 'enable_hv' pin of the Flash memory." "0,1"
|
|
bitfld.long 0x4 0. "ENABLE,Controls 'enable' pin of the Flash memory." "0,1"
|
|
line.long 0x8 "FLASH_CMD,Command"
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x8 1. "BUFF_INV,Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and.." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
bitfld.long 0x8 1. "BUFF_INV,Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and.." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
bitfld.long 0x8 1. "BUFF_INV,Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and.." "0,1"
|
|
endif
|
|
bitfld.long 0x8 0. "INV,FLASH cache and buffer invalidation for ALL cache and buffers. SW writes a '1' to clear the cache and buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the.." "0,1"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
group.long 0x100++0xB
|
|
line.long 0x0 "BIST_CTL,BIST control"
|
|
bitfld.long 0x0 7. "STOP_ON_ERROR,Specifies the BIST to continue indefinitely regardless of occurrence of errors or not." "0: BIST controller doesn't stop on the data failures,1: BIST controller stops on when the first data.."
|
|
bitfld.long 0x0 6. "INCR_DECR_BOTH,Specifies to generate patterns where both column address and row address are incremented/decremented simultaneously." "0: Generate normal increment/decrement patterns,1: Generate address patterns with both row and.."
|
|
newline
|
|
bitfld.long 0x0 5. "ADDR_COMPLIMENT_ENABLED,Specifies to generate address compliment patterns." "0: Generate normal increment/decrement patterns,1: Generate address patterns which interleaves.."
|
|
bitfld.long 0x0 4. "ADDR_START_ENABLED,Specifies Flash BIST start addresses:" "0: Row and column addresses start with their..,1: Row and column addresses start with their values.."
|
|
newline
|
|
bitfld.long 0x0 3. "ROW_FIRST,Specifies how the Flash BIST addresses are generated:" "0: Column address is incremented/decremented till..,1: Row address is incremented/decremented till it.."
|
|
bitfld.long 0x0 2. "UP,Specifies direction in which Flash BIST steps through addresses:" "0: BIST steps through the Flash from the maximum..,1: BIST steps through the Flash from the minimum.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "OPCODE,This field specifies how the data check should be performed after reading the data from Flash memory." "0: Read the Flash and compare the output to BIST_DATA,1: Read the Flash and compare the output to the..,?,3: Read the Flash and compare with BIST_DATA[] and.."
|
|
line.long 0x4 "BIST_CMD,BIST command"
|
|
bitfld.long 0x4 0. "START,1: Start FLASH BIST. Hardware set this field to '0' when BIST is completed." "?,1: Start FLASH BIST"
|
|
line.long 0x8 "BIST_ADDR_START,BIST address start register"
|
|
hexmask.long.word 0x8 16.--31. 1. "ROW_ADDR_START,Row start address. Useful to apply BIST to a part of an Flash. The value of this field should be in a legal range (a value outside of the legal range has an undefined result and may lock up the BIST state machine). This legal range is.."
|
|
hexmask.long.word 0x8 0.--15. 1. "COL_ADDR_START,Column start address. Useful to apply BIST to a part of an Flash. The value of this field should be in a legal range (a value outside of the legal range has an undefined result and may lock up the BIST state machine). This legal range is.."
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x10C)++0x3
|
|
line.long 0x0 "BIST_DATA[$1],BIST data register(s)"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,BIST data register to store the expected value for data comparison."
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x12C)++0x3
|
|
line.long 0x0 "BIST_DATA_ACT[$1],BIST data actual register(s)"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,This field specified the actual Flash data output that caused the BIST failure."
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x14C)++0x3
|
|
line.long 0x0 "BIST_DATA_EXP[$1],BIST data expected register(s)"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,This field specified the expected Flash data output."
|
|
repeat.end
|
|
rgroup.long 0x16C++0x3
|
|
line.long 0x0 "BIST_ADDR,BIST address register"
|
|
hexmask.long.word 0x0 16.--31. 1. "ROW_ADDR,Current row address."
|
|
hexmask.long.word 0x0 0.--15. 1. "COL_ADDR,Current column address."
|
|
group.long 0x170++0x3
|
|
line.long 0x0 "BIST_STATUS,BIST status register"
|
|
bitfld.long 0x0 0. "FAIL,0: BIST passed." "0: BIST passed,1: BIST failed"
|
|
group.long 0x40C++0x3
|
|
line.long 0x0 "CM0_CA_CMD,CM0+ cache command"
|
|
bitfld.long 0x0 0. "INV,FLASH cache invalidation. SW writes a '1' to clear the cache. W sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The cache's LRU structure.." "0,1"
|
|
group.long 0x48C++0x3
|
|
line.long 0x0 "CM4_CA_CMD,CM4 cache command"
|
|
bitfld.long 0x0 0. "INV,See CM0_CA_CMD." "0,1"
|
|
group.long 0x508++0x3
|
|
line.long 0x0 "CRYPTO_BUFF_CMD,Cryptography buffer command"
|
|
bitfld.long 0x0 0. "INV,FLASH buffer invalidation. SW writes a '1' to clear the buffer. HW sets this field to '0' when the operation is completed." "0,1"
|
|
group.long 0x588++0x3
|
|
line.long 0x0 "DW0_BUFF_CMD,Datawire 0 buffer command"
|
|
bitfld.long 0x0 0. "INV,See CRYPTO_BUFF_CMD." "0,1"
|
|
group.long 0x608++0x3
|
|
line.long 0x0 "DW1_BUFF_CMD,Datawire 1 buffer command"
|
|
bitfld.long 0x0 0. "INV,See CRYPTO_BUFF_CMD." "0,1"
|
|
group.long 0x680++0x3
|
|
line.long 0x0 "DAP_BUFF_CTL,Debug access port buffer control"
|
|
bitfld.long 0x0 31. "ENABLED,See CRYPTO_BUFF_CTL." "0,1"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
group.long 0x688++0x3
|
|
line.long 0x0 "DAP_BUFF_CMD,Debug access port buffer command"
|
|
bitfld.long 0x0 0. "INV,See CRYPTO_BUFF_CMD." "0,1"
|
|
group.long 0x708++0x3
|
|
line.long 0x0 "EXT_MS0_BUFF_CMD,External master 0 buffer command"
|
|
bitfld.long 0x0 0. "INV,See CRYPTO_BUFF_CMD." "0,1"
|
|
group.long 0x788++0x3
|
|
line.long 0x0 "EXT_MS1_BUFF_CMD,External master 1 buffer command"
|
|
bitfld.long 0x0 0. "INV,See CRYPTO_BUFF_CMD." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x2B0++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL0,eCT Flash SRAM ECC control 0"
|
|
hexmask.long 0x0 0.--31. 1. "ECC_INJ_DATA,32-bit data for ECC error injection test of eCT Flash SRAM ECC logic."
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x2B0++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL0,eCT Flash SRAM ECC control 0"
|
|
hexmask.long 0x0 0.--31. 1. "ECC_INJ_DATA,32-bit data for ECC error injection test of eCT Flash SRAM ECC logic."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x2B0++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL0,eCT Flash SRAM ECC control 0"
|
|
hexmask.long 0x0 0.--31. 1. "ECC_INJ_DATA,32-bit data for ECC error injection test of eCT Flash SRAM ECC logic."
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x2B4++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL1,eCT Flash SRAM ECC control 1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ECC_INJ_PARITY,7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic."
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x2B4++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL1,eCT Flash SRAM ECC control 1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ECC_INJ_PARITY,7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x2B4++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL1,eCT Flash SRAM ECC control 1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ECC_INJ_PARITY,7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic."
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
rgroup.long 0x2B8++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL2,eCT Flash SRAM ECC control 2"
|
|
hexmask.long 0x0 0.--31. 1. "CORRECTED_DATA,32-bit corrected data output of the ECC syndrome logic."
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
rgroup.long 0x2B8++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL2,eCT Flash SRAM ECC control 2"
|
|
hexmask.long 0x0 0.--31. 1. "CORRECTED_DATA,32-bit corrected data output of the ECC syndrome logic."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
rgroup.long 0x2B8++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL2,eCT Flash SRAM ECC control 2"
|
|
hexmask.long 0x0 0.--31. 1. "CORRECTED_DATA,32-bit corrected data output of the ECC syndrome logic."
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x2BC++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL3,eCT Flash SRAM ECC control 3"
|
|
rbitfld.long 0x0 8. "ECC_TEST_FAIL,Status of ECC test." "0: ECC was performed,1: ECC test failed because eCT Flash macro is busy.."
|
|
bitfld.long 0x0 4. "ECC_INJ_EN,eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ECC_ENABLE,ECC generation/check enable for eCT Flash SRAM memory." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x2BC++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL3,eCT Flash SRAM ECC control 3"
|
|
rbitfld.long 0x0 8. "ECC_TEST_FAIL,Status of ECC test." "0: ECC was performed,1: ECC test failed because eCT Flash macro is busy.."
|
|
bitfld.long 0x0 4. "ECC_INJ_EN,eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ECC_ENABLE,ECC generation/check enable for eCT Flash SRAM memory." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x2BC++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL3,eCT Flash SRAM ECC control 3"
|
|
rbitfld.long 0x0 8. "ECC_TEST_FAIL,Status of ECC test." "0: ECC was performed,1: ECC test failed because eCT Flash macro is busy.."
|
|
bitfld.long 0x0 4. "ECC_INJ_EN,eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ECC_ENABLE,ECC generation/check enable for eCT Flash SRAM memory." "0,1"
|
|
endif
|
|
group.long 0x400++0xB
|
|
line.long 0x0 "CM0_CA_CTL0,CM0+ cache control"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
bitfld.long 0x0 31. "ENABLED,Cache enable:" "0: Disabled,1: Enabled"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x0 31. "CA_EN,Cache enable:" "0: Disabled,1: Enabled"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
bitfld.long 0x0 31. "CA_EN,Cache enable:" "0: Disabled,1: Enabled"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
bitfld.long 0x0 31. "CA_EN,Cache enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 30. "PREF_EN,Prefetch enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 24.--26. "SET_ADDR,Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. "WAY,Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2." "0,1,2,3"
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x0 1. "RAM_ECC_INJ_EN,Enable error injection for cache." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RAM_ECC_EN,Enable ECC checking for cache accesses:" "0: Disabled,1: Enabled"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
bitfld.long 0x0 1. "RAM_ECC_INJ_EN,Enable error injection for cache." "0,1"
|
|
bitfld.long 0x0 0. "RAM_ECC_EN,Enable ECC checking for cache accesses:" "0: Disabled,1: Enabled"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
bitfld.long 0x0 1. "RAM_ECC_INJ_EN,Enable error injection for cache." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RAM_ECC_EN,Enable ECC checking for cache accesses:" "0: Disabled,1: Enabled"
|
|
endif
|
|
line.long 0x4 "CM0_CA_CTL1,CM0+ cache control"
|
|
hexmask.long.word 0x4 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x4 0.--1. "PWR_MODE,Set Power mode for CM0 cache" "0: See CM4_PWR_CTL,1: undefined,2: See CM4_PWR_CTL,3: See CM4_PWR_CTL"
|
|
line.long 0x8 "CM0_CA_CTL2,CM0+ cache control"
|
|
hexmask.long.word 0x8 0.--9. 1. "PWRUP_DELAY,Number clock cycles delay needed after power domain power up"
|
|
rgroup.long 0x440++0xB
|
|
line.long 0x0 "CM0_CA_STATUS0,CM0+ cache status 0"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
hexmask.long.word 0x0 0.--15. 1. "VALID16,Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR."
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
hexmask.long 0x0 0.--31. 1. "VALID32,Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR."
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
hexmask.long 0x0 0.--31. 1. "VALID32,Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
hexmask.long 0x0 0.--31. 1. "VALID32,Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR."
|
|
endif
|
|
line.long 0x4 "CM0_CA_STATUS1,CM0+ cache status 1"
|
|
hexmask.long 0x4 0.--31. 1. "TAG,Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR."
|
|
line.long 0x8 "CM0_CA_STATUS2,CM0+ cache status 2"
|
|
hexmask.long.byte 0x8 0.--5. 1. "LRU,Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y):"
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x460++0x3
|
|
line.long 0x0 "CM0_STATUS,CM0+ interface status"
|
|
bitfld.long 0x0 1. "WORK_INTERNAL_ERR,See CM0_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x0 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ access (or debug access via SYS_AP/CM0_AP)." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x460++0x3
|
|
line.long 0x0 "CM0_STATUS,CM0+ interface status"
|
|
bitfld.long 0x0 1. "WORK_INTERNAL_ERR,See CM0_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x0 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ access (or debug access via SYS_AP/CM0_AP)." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x460++0x3
|
|
line.long 0x0 "CM0_STATUS,CM0+ interface status"
|
|
bitfld.long 0x0 1. "WORK_INTERNAL_ERR,See CM0_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x0 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ access (or debug access via SYS_AP/CM0_AP)." "0,1"
|
|
endif
|
|
group.long 0x480++0xB
|
|
line.long 0x0 "CM4_CA_CTL0,CM4 cache control"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
bitfld.long 0x0 31. "ENABLED,See CM0_CA_CTL." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x0 31. "CA_EN,Cache enable:" "0: Disabled,1: Enabled"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
bitfld.long 0x0 31. "CA_EN,Cache enable:" "0: Disabled,1: Enabled"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
bitfld.long 0x0 31. "CA_EN,Cache enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 30. "PREF_EN,See CM0_CA_CTL." "0,1"
|
|
bitfld.long 0x0 24.--26. "SET_ADDR,See CM0_CA_CTL." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. "WAY,See CM0_CA_CTL." "0,1,2,3"
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x0 1. "RAM_ECC_INJ_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RAM_ECC_EN,N/A" "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
bitfld.long 0x0 1. "RAM_ECC_INJ_EN,N/A" "0,1"
|
|
bitfld.long 0x0 0. "RAM_ECC_EN,N/A" "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
bitfld.long 0x0 1. "RAM_ECC_INJ_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RAM_ECC_EN,N/A" "0,1"
|
|
endif
|
|
line.long 0x4 "CM4_CA_CTL1,CM4 cache control"
|
|
hexmask.long.word 0x4 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x4 0.--1. "PWR_MODE,Set Power mode for CM4 cache" "0: See CM4_PWR_CTL,1: undefined,2: See CM4_PWR_CTL,3: See CM4_PWR_CTL"
|
|
line.long 0x8 "CM4_CA_CTL2,CM4 cache control"
|
|
hexmask.long.word 0x8 0.--9. 1. "PWRUP_DELAY,Number clock cycles delay needed after power domain power up"
|
|
rgroup.long 0x4C0++0xB
|
|
line.long 0x0 "CM4_CA_STATUS0,CM4 cache status 0"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
hexmask.long.word 0x0 0.--15. 1. "VALID16,See CM0_CA_STATUS0."
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
hexmask.long 0x0 0.--31. 1. "VALID32,See CM0_CA_STATUS0."
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
hexmask.long 0x0 0.--31. 1. "VALID32,See CM0_CA_STATUS0."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
hexmask.long 0x0 0.--31. 1. "VALID32,See CM0_CA_STATUS0."
|
|
endif
|
|
line.long 0x4 "CM4_CA_STATUS1,CM4 cache status 1"
|
|
hexmask.long 0x4 0.--31. 1. "TAG,See CM0_CA_STATUS1."
|
|
line.long 0x8 "CM4_CA_STATUS2,CM4 cache status 2"
|
|
hexmask.long.byte 0x8 0.--5. 1. "LRU,See CM0_CA_STATUS2."
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x4E0++0x3
|
|
line.long 0x0 "CM4_STATUS,CM4 interface status"
|
|
bitfld.long 0x0 1. "WORK_INTERNAL_ERR,See CM4_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x0 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM4 access (or debug access via SYS_AP/CM4_AP)." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x4E0++0x3
|
|
line.long 0x0 "CM4_STATUS,CM4 interface status"
|
|
bitfld.long 0x0 1. "WORK_INTERNAL_ERR,See CM4_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x0 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM4 access (or debug access via SYS_AP/CM4_AP)." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x4E0++0x3
|
|
line.long 0x0 "CM4_STATUS,CM4 interface status"
|
|
bitfld.long 0x0 1. "WORK_INTERNAL_ERR,See CM4_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x0 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM4 access (or debug access via SYS_AP/CM4_AP)." "0,1"
|
|
endif
|
|
group.long 0x500++0x3
|
|
line.long 0x0 "CRYPTO_BUFF_CTL,Cryptography buffer control"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
bitfld.long 0x0 31. "ENABLED,Cache enable:" "0: Disabled,1: Enabled"
|
|
endif
|
|
bitfld.long 0x0 30. "PREF_EN,Prefetch enable:" "0: Disabled,1: Enabled"
|
|
group.long 0x580++0x3
|
|
line.long 0x0 "DW0_BUFF_CTL,Datawire 0 buffer control"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
bitfld.long 0x0 31. "ENABLED,See CRYPTO_BUFF_CTL." "0,1"
|
|
endif
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
group.long 0x600++0x3
|
|
line.long 0x0 "DW1_BUFF_CTL,Datawire 1 buffer control"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
bitfld.long 0x0 31. "ENABLED,See CRYPTO_BUFF_CTL." "0,1"
|
|
endif
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x680++0x3
|
|
line.long 0x0 "DMAC_BUFF_CTL,DMA controller buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x680++0x3
|
|
line.long 0x0 "DMAC_BUFF_CTL,DMA controller buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x680++0x3
|
|
line.long 0x0 "DMAC_BUFF_CTL,DMA controller buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
endif
|
|
group.long 0x700++0x3
|
|
line.long 0x0 "EXT_MS0_BUFF_CTL,External master 0 buffer control"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
bitfld.long 0x0 31. "ENABLED,See CRYPTO_BUFF_CTL." "0,1"
|
|
endif
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
group.long 0x780++0x3
|
|
line.long 0x0 "EXT_MS1_BUFF_CTL,External master 1 buffer control"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
bitfld.long 0x0 31. "ENABLED,See CRYPTO_BUFF_CTL." "0,1"
|
|
endif
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
tree "FM_CTL (Flash Macro Registers)"
|
|
base ad:0x4024F000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FM_CTL,Flash macro control"
|
|
bitfld.long 0x0 25. "WR_EN,0: normal mode" "0: normal mode,1: Fm Write Enable"
|
|
newline
|
|
bitfld.long 0x0 24. "IF_SEL,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DAA_MUX_SEL,N/A"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FM_SEQ,N/A" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "FM_MODE,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PUMP_NDAC,Test_only internal node: regif ndac outputs to pos pump"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PUMP_PDAC,Test_only internal node: regif pdac outputs to pos pump"
|
|
newline
|
|
bitfld.long 0x0 23. "RQ_ERROR,Test_only internal node: rq_error sync-de in clk_c domain" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CBUS_RED_ROW_EN,Test_only internal node: mpcon red_row_en" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "CBUS_RA_MATCH,Test_only internal node: mpcon ra match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "HVOP_BULK_ALL,Test_only internal node: mpcon bk_all" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "HVOP_SECTOR,Test_only internal node: mpcon bk_sec" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "HVOP_SUB_SECTOR_N,Test_only internal node: mpcon bk_subb" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ROW_EVEN,Test_only internal node: mpcon row_even" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ROW_ODD,Test_only internal node: mpcon row_odd" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RESET_MM,Test_only internal node: mpcon reset_mm" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "SECTOR0_SR,0: Sector 0 does not contain special rows. The special rows are located in separate special sectors." "0: Sector 0 does not contain special rows,1: Sector 0 contains special rows"
|
|
newline
|
|
bitfld.long 0x0 13. "MAX_DOUT_WIDTH,Internal memory core max data out size" "0: x128 bits,1: x256 bits"
|
|
newline
|
|
bitfld.long 0x0 12. "RWW,FM Type (Read While Write or Not Read While Write):" "0: Non RWW FM Type,1: RWW FM Type"
|
|
newline
|
|
bitfld.long 0x0 11. "NEG_PUMP_VHI,NEG pump VHI" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "POS_PUMP_VLO,POS pump VLO" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "FM_READY,0: FM not ready" "0: FM not ready,1: FM ready"
|
|
newline
|
|
bitfld.long 0x0 8. "FM_BUSY,0': FM not busy" "0: FM not busy,1: FM BUSY : R_GRANT is 0 as result of a busy.."
|
|
newline
|
|
bitfld.long 0x0 7. "R_GRANT_DELAY_STATUS,0: R_GRANT_DELAY timer is not running" "0: R_GRANT_DELAY timer is not running,1: R_GRANT_DELAY timer is running"
|
|
newline
|
|
bitfld.long 0x0 6. "TIMER_STATUS,The actual timer state sync-ed in clk_c domain:" "0: timer is not running:,1: timer is running"
|
|
newline
|
|
bitfld.long 0x0 5. "IF_SEL_MON,FM_CTL.IF_SEL bit after being synchronized in clk_r domain" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "WR_EN_MON,FM_CTL.WR_EN bit after being synchronized in clk_r domain" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TURBO_N,After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.." "0: turbo mode,1: normal mode"
|
|
newline
|
|
bitfld.long 0x0 2. "ILLEGAL_HVOP,Indicates a bulk sector erase program has been requested when axa=1" "0: no error,1: illegal HV operation error"
|
|
newline
|
|
bitfld.long 0x0 1. "HV_REGS_ISOLATED,Indicates the isolation status at HV trim and redundancy registers inputs" "0: Not isolated,1: isolated writing disabled"
|
|
newline
|
|
bitfld.long 0x0 0. "TIMER_ENABLED,This is the timer_en bit set by writing a '1' in the TIMER_CTL bit 31. It is reset by HW when the timer expires" "0: timer not running,1: Timer is enabled and not expired yet"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "FM_ADDR,Flash macro address"
|
|
bitfld.long 0x0 24. "AXA,Auxiliary address field:" "0: regular flash memory,1: supervisory flash memory"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "BA,Bank address."
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RA,Row address."
|
|
line.long 0x4 "BOOKMARK,Bookmark register - keeps the current FW HV seq"
|
|
hexmask.long 0x4 0.--31. 1. "BOOKMARK,Used by FW. Keeps the Current HV cycle sequence"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "GEOMETRY,Regular flash geometry"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PAGE_SIZE_LOG2,Number of Bytes per page (log 2):"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "WORD_SIZE_LOG2,Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access:"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "BANK_COUNT,Number of banks (minus 1):"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "ROW_COUNT,Number of rows (minus 1):"
|
|
line.long 0x4 "GEOMETRY_SUPERVISORY,Supervisory flash geometry"
|
|
hexmask.long.byte 0x4 28.--31. 1. "PAGE_SIZE_LOG2,Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2."
|
|
newline
|
|
hexmask.long.byte 0x4 24.--27. 1. "WORD_SIZE_LOG2,Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2."
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "BANK_COUNT,Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT."
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "ROW_COUNT,Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "ANA_CTL0,Analog control 0"
|
|
bitfld.long 0x0 30.--31. "SCALE_PRG_PEOFF,PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE OFF transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x0 28.--29. "SCALE_PRG_PEON,PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE On transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SCALE_SEQ30,PROG&PRE_PROG& ERASE: Scale for R_GRANT_DELAY on seq3-seq0 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "SCALE_PRG_SEQ23,PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq2-seq3 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "SCALE_PRG_SEQ12,PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq1-seq2 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SCALE_PRG_SEQ01,PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq0-seq1 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PDAC_MIN,PDAC staircase min value"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "NDAC_MIN,NDAC staircase min value"
|
|
newline
|
|
bitfld.long 0x0 11. "FLIP_AMUXBUS_AB,Flips amuxbusa and amuxbusb" "0: amuxbusa,1: amuxbusb"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "CSLDAC,Trimming of common source line DAC." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "MDAC,Trimming of the output margin Voltage as a function of Vpos and Vneg."
|
|
line.long 0x4 "ANA_CTL1,Analog control 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "NPDAC_ZERO_TIME,Ndac/Pdac LO duration: (1uS .. 255uS) * 8"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "NPDAC_STEP_TIME,Ndac/Pdac step duration: (1uS .. 255uS) * 8"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "PDAC_STEP,Pdac step increment"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "PDAC_MAX,Pdac Max Value.Trimming of positive pump output Voltage:"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "NDAC_STEP,Ndac step increment"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "NDAC_MAX,Ndac Max Value.Trimming of negative pump output Voltage."
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "WAIT_CTL,Wait State control"
|
|
bitfld.long 0x0 29. "PL_SOFT_SET_EN,Page latch soft set enable 0 = disabled 1 = enabled (at end of seq_2) taken care in API" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 28. "MBA,0: Normal" "0: Normal,1: Test mode to enable Master Bulk Access which.."
|
|
newline
|
|
bitfld.long 0x0 27. "DRMM,0: Normal" "0: Normal,1: Test mode to enable Margin mode for 2 rows at a.."
|
|
newline
|
|
bitfld.long 0x0 26. "LV_SPARE_1,Spare register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "FM_RWW_MODE,00: Full CBUS MODE" "0: Full CBUS MODE,1: RWW,?,?"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "WAIT_FM_HV_WR,Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "WAIT_FM_HV_RD,Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "WAIT_FM_MEM_RD,Number of C interface wait cycles (on 'clk_c') for a read from the memory"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "TIMER_CLK_CTL,Timer prescaler (clk_t to timer clock frequency divider)"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RGRANT_DELAY_PRG_SEQ01,PROG&PRE_PROG: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RGRANT_DELAY_PRG_PEOFF,PROG&PRE_PROG: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RGRANT_DELAY_PRG_PEON,PROG&PRE_PROG: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TIMER_CLOCK_FREQ,Clk_t frequency divider to provide the 1MHz reference clock for the Regif Timer."
|
|
line.long 0x4 "TIMER_CTL,Timer control"
|
|
bitfld.long 0x4 31. "TIMER_EN,Timer enable:" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x4 30. "ACLK_EN,ACLK enable (generates a single cycle pulse for the FM):" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x4 29. "PUMP_EN,Pump enable:" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x4 26. "PRE_PROG_CSL,0: CSL lines driven by CSL_DAC" "0: CSL lines driven by CSL_DAC,1: CSL lines driven by VNEG_G"
|
|
newline
|
|
bitfld.long 0x4 25. "PRE_PROG,1 during pre-program operation" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "AUTO_SEQUENCE,1': Starts1 the HV automatic sequencing" "?,1: Starts1 the HV automatic sequencing"
|
|
newline
|
|
bitfld.long 0x4 15. "SCALE,Timer tick scale:" "0: 1 microsecond,1: 100 microseconds"
|
|
newline
|
|
hexmask.long.word 0x4 0.--14. 1. "PERIOD,Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples."
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "ACLK_CTL,MPCON clock"
|
|
bitfld.long 0x0 0. "ACLK_GEN,A write to this register generates the clock pulse for HV control registers (mpcon outputs)" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 0. "TIMER_EXPIRED,Set to '1' when event is detected. Write INTR field with '1' to clear bit. Write INTR_SET field with '1' to set bit." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 0. "TIMER_EXPIRED,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 0. "TIMER_EXPIRED,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "TIMER_EXPIRED,Logical and of corresponding request and mask fields." "0,1"
|
|
group.long 0x50++0x1F
|
|
line.long 0x0 "CAL_CTL0,Cal control BG LO trim bits"
|
|
bitfld.long 0x0 19. "IPREF_TRIMA_LO_HV,Adds 100-150nA boost on IPREF_LO" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "ICREF_TC_TRIM_LO_HV,LO Bandgap Current Temperature Compensation trim control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 13.--15. "VBG_TC_TRIM_LO_HV,LO Bandgap Voltage Temperature Compensation trim control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "VBG_TRIM_LO_HV,LO Bandgap Voltage trim control."
|
|
newline
|
|
bitfld.long 0x0 5.--7. "CDAC_LO_HV,LO Temperature compensated trim DAC. To control Vcstat slope for Vpos." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "VCT_TRIM_LO_HV,LO Bandgap Voltage Temperature Compensation trim control."
|
|
line.long 0x4 "CAL_CTL1,Cal control BG HI trim bits"
|
|
bitfld.long 0x4 19. "IPREF_TRIMA_HI_HV,Adds 100-150nA boost on IPREF_HI" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "ICREF_TC_TRIM_HI_HV,HI Bandgap Current Temperature Compensation trim control." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "VBG_TC_TRIM_HI_HV,HI Bandgap Voltage Temperature Compensation trim control." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "VBG_TRIM_HI_HV,HI Bandgap Voltage trim control."
|
|
newline
|
|
bitfld.long 0x4 5.--7. "CDAC_HI_HV,HI Temperature compensated trim DAC. To control Vcstat slope for Vpos." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "VCT_TRIM_HI_HV,HI Bandgap Voltage Temperature Compensation trim control."
|
|
line.long 0x8 "CAL_CTL2,Cal control BG LO&HI trim bits"
|
|
hexmask.long.byte 0x8 15.--19. 1. "IPREF_TRIM_HI_HV,HI Bandgap IPTAT trim control."
|
|
newline
|
|
hexmask.long.byte 0x8 10.--14. 1. "IPREF_TRIM_LO_HV,LO Bandgap IPTAT trim control."
|
|
newline
|
|
hexmask.long.byte 0x8 5.--9. 1. "ICREF_TRIM_HI_HV,HI Bandgap Current trim control."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "ICREF_TRIM_LO_HV,LO Bandgap Current trim control."
|
|
line.long 0xC "CAL_CTL3,Cal control osc trim bits. idac. sdac. itim"
|
|
bitfld.long 0xC 19. "LP_ULP_SW_HV,LP<-->ULP switch for trim signals:" "0: LP,1: ULP"
|
|
newline
|
|
bitfld.long 0xC 18. "R_GRANT_EN_HV,0: r_grant handshake disabled r_grant always 1." "0: r_grant handshake disabled,1: r_grand handshake enabled"
|
|
newline
|
|
bitfld.long 0xC 17. "CL_ISO_DIS_HV,0: The internal logic controls the CL isolation" "0: The internal logic controls the CL isolation,1: Forces CL bypass"
|
|
newline
|
|
bitfld.long 0xC 16. "BGHI_EN_HV,0: Normal (Automatic change over from HI to LO)" "0: Normal,1: Force enable HI Bandgap"
|
|
newline
|
|
bitfld.long 0xC 15. "BGLO_EN_HV,0: Normal (Automatic change over from HI to LO)" "0: Normal,1: Force enable LO Bandgap"
|
|
newline
|
|
bitfld.long 0xC 13.--14. "TURBO_PULSEW_HV,Turbo pulse width trim (Typical)" "0: 40 us,1: 20 us,?,?"
|
|
newline
|
|
bitfld.long 0xC 12. "VDDHI_HV,0: vdd < 2.3V" "0: vdd < 2,1: vdd >= 2"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "FDIV_TRIM_HV,FDIV_TRIM_HV[1:0]: Assuming oscillator frequency of 8MHz in standby." "0: F = 1MHz,1: F = 0,?,?"
|
|
newline
|
|
bitfld.long 0xC 9. "REG_ACT_HV,0: VBST regulator will operate in active/standby mode based on control signal." "0: VBST regulator will operate in active/standby..,1: Forces the VBST regulator in active mode all the.."
|
|
newline
|
|
bitfld.long 0xC 8. "IREF_SEL_HV,Current reference:" "0: internal current reference,1: external current reference"
|
|
newline
|
|
bitfld.long 0xC 7. "VREF_SEL_HV,Voltage reference:" "0: internal bandgap reference,1: external voltage reference"
|
|
newline
|
|
bitfld.long 0xC 6. "IPREF_TC_HV,0: Increases the IPREF Tempco by subtracting ICREF from IPREF - IPREF internal will be 0.5uA" "0: Increases the IPREF Tempco by subtracting ICREF..,1: Reduces the IPREF Tempco without subtracting.."
|
|
newline
|
|
bitfld.long 0xC 5. "VPROT_ACT_HV,Forces VPROT in active mode all the time" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "OSC_RANGE_TRIM_HV,0: Oscillator High Frequency Range" "0: Oscillator High Frequency Range,1: Oscillator Low Frequency range"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "OSC_TRIM_HV,Flash macro pump clock trim control."
|
|
line.long 0x10 "CAL_CTL4,Cal Control Vlim. SA. fdiv. reg_act"
|
|
bitfld.long 0x10 19. "UGB_EN_HV,UGB enable in TM control" "0,1"
|
|
newline
|
|
bitfld.long 0x10 18. "AUTO_HVPULSE_HV,0: HV Pulse controlled by FW" "0: HV Pulse controlled by FW,1: HV Pulse controlled by Hardware"
|
|
newline
|
|
bitfld.long 0x10 17. "VBST_S_DIS_HV,0: VBST_S voltage for each sector to allow VBST level to be dropped to VCC during Erase in the selected sector reducing coupling to GBL." "0: VBST_S voltage for each sector to allow VBST..,1: VBST_S voltage for each sector stays at VBST.."
|
|
newline
|
|
bitfld.long 0x10 16. "READY_RESTART_N_HV,Toggle: 1-->0 ready goes low ready will remain low as long as the bit is low. Toggle the bit back to 1 to activate the ready logic. To be used by API only." "0,1"
|
|
newline
|
|
bitfld.long 0x10 15. "SPARE451_ULP_HV,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13.--14. "FM_READY_DEL_ULP_HV,00: Default : delay 1ns" "0: Default : delay 1ns,1: Delayed by 1,?,?"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--12. 1. "ITIM_ULP_HV,Trimming of timing current"
|
|
newline
|
|
bitfld.long 0x10 6.--7. "SDAC_ULP_HV,Sets the sense current reference temp slope. Refer to trim tables for details." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x10 2.--5. 1. "IDAC_ULP_HV,Sets the sense current reference offset value. Refer to trim tables for details."
|
|
newline
|
|
bitfld.long 0x10 0.--1. "VLIM_TRIM_ULP_HV,VLIM_TRIM[1:0]:" "0: V2 = 650mV,1: V2 = 600mV,?,?"
|
|
line.long 0x14 "CAL_CTL5,Cal control"
|
|
bitfld.long 0x14 18.--19. "AMUX_SEL_HV,Amux Select in AMUX_UGB" "0: Bypass UGB for both amuxbusa and amuxbusb,1: Bypass UGB for amuxbusb while passing amuxbusa..,?,?"
|
|
newline
|
|
bitfld.long 0x14 16.--17. "SPARE52_HV,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 15. "SPARE451_LP_HV,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x14 13.--14. "FM_READY_DEL_LP_HV,00: Delayed by 1us" "0: Delayed by 1us,1: Delayed by 1,?,?"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--12. 1. "ITIM_LP_HV,Trimming of timing current"
|
|
newline
|
|
bitfld.long 0x14 6.--7. "SDAC_LP_HV,Sets the sense current reference temp slope. Refer to trim tables for details." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x14 2.--5. 1. "IDAC_LP_HV,Sets the sense current reference offset value. Refer to trim tables for details."
|
|
newline
|
|
bitfld.long 0x14 0.--1. "VLIM_TRIM_LP_HV,VLIM_TRIM[1:0]:" "0: V2 = 650mV,1: V2 = 600mV,?,?"
|
|
line.long 0x18 "CAL_CTL6,SA trim LP/ULP"
|
|
bitfld.long 0x18 19. "SA_CTL_TRIM_T8_LP_HV,saen3 pulse width trim (Current trim)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 17.--18. "SA_CTL_TRIM_T6_LP_HV,SA_CTL_TRIM_T6_LP_HV<1>= eni (enable current trim)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 14.--16. "SA_CTL_TRIM_T5_LP_HV,SA_CTL_TRIM_T5_LP_HV<2>= evi (integration current trim)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 11.--13. "SA_CTL_TRIM_T4_LP_HV,SA_CTL_TRIM_T4_LP_HV<2>= eqi (eq current trim)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 10. "SA_CTL_TRIM_T1_LP_HV,clk_trk delay" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "SA_CTL_TRIM_T8_ULP_HV,saen3 pulse width trim (Current trim)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7.--8. "SA_CTL_TRIM_T6_ULP_HV,SA_CTL_TRIM_T6_ULP_HV<1>= eni (enable current trim)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 4.--6. "SA_CTL_TRIM_T5_ULP_HV,SA_CTL_TRIM_T5_ULP_HV<2>= evi (integration current trim)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 1.--3. "SA_CTL_TRIM_T4_ULP_HV,SA_CTL_TRIM_T4_ULP_HV<2>= eqi (eq current trim)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 0. "SA_CTL_TRIM_T1_ULP_HV,clk_trk delay" "0,1"
|
|
line.long 0x1C "CAL_CTL7,Cal control"
|
|
hexmask.long.byte 0x1C 15.--19. 1. "SPARE7_LP_HV,N/A"
|
|
newline
|
|
hexmask.long.byte 0x1C 10.--14. 1. "SPARE7_ULP_HV,N/A"
|
|
newline
|
|
bitfld.long 0x1C 8.--9. "SPARE7_HV,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1C 7. "DISABLE_LOAD_ONCE_HV,0: Load common HV params during API HV operations depends on the HV_PARAMS_LOADED bit in RGRANT_DELAY_PRG register." "0: Load common HV params during API HV operations..,1: All HV params are loaded during every API HV.."
|
|
newline
|
|
bitfld.long 0x1C 6. "ERSX8_EN_ALL_HV,0': Staggered turn on/off of GWL" "0: Staggered turn on/off of GWL,1: GWL are turned on/off at the same time"
|
|
newline
|
|
bitfld.long 0x1C 5. "FM_READY_DIS_HV,0': fm ready is enabled" "0: fm ready is enabled,1: fm ready is disabled"
|
|
newline
|
|
bitfld.long 0x1C 4. "NPDAC_HWCTL_DIS_HV,0': ndac pdac staircase hardware controlled" "0: ndac,1: ndac"
|
|
newline
|
|
bitfld.long 0x1C 3. "TURBO_EXT_HV,0: Normal operation" "0: Normal operation,1: Uses external turbo pulse"
|
|
newline
|
|
bitfld.long 0x1C 2. "FM_ACTIVE_HV,0: Normal operation" "0: Normal operation,1: Forces FM SYS in active mode"
|
|
newline
|
|
bitfld.long 0x1C 0.--1. "ERSX8_CLK_SEL_HV,Clock frequency into the ersx8 shift register block" "0: Oscillator clock,1: Oscillator clock / 2,?,?"
|
|
group.long 0x80++0x13
|
|
line.long 0x0 "RED_CTL01,Redundancy Control normal sectors 0.1"
|
|
bitfld.long 0x0 24. "RED_EN_1,1: Redundancy Enable for Sector 1" "?,1: Redundancy Enable for Sector 1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RED_ADDR_1,Bad Row Pair Address for Sector 1"
|
|
newline
|
|
bitfld.long 0x0 8. "RED_EN_0,1: Redundancy Enable for Sector 0" "?,1: Redundancy Enable for Sector 0"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RED_ADDR_0,Bad Row Pair Address for Sector 0"
|
|
line.long 0x4 "RED_CTL23,Redundancy Control normal sectors 2.3"
|
|
bitfld.long 0x4 24. "RED_EN_3,1: Redundancy Enable for Sector 3" "?,1: Redundancy Enable for Sector 3"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "RED_ADDR_3,Bad Row Pair Address for Sector 3"
|
|
newline
|
|
bitfld.long 0x4 8. "RED_EN_2,1: Redundancy Enable for Sector 2" "?,1: Redundancy Enable for Sector 2"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RED_ADDR_2,Bad Row Pair Address for Sector 2"
|
|
line.long 0x8 "RED_CTL45,Redundancy Control normal sectors 4.5"
|
|
bitfld.long 0x8 24. "RED_EN_5,1: Redundancy Enable for Sector 5" "?,1: Redundancy Enable for Sector 5"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--23. 1. "RED_ADDR_5,Bad Row Pair Address for Sector 5"
|
|
newline
|
|
bitfld.long 0x8 8. "RED_EN_4,1: Redundancy Enable for Sector 4" "?,1: Redundancy Enable for Sector 4"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "RED_ADDR_4,Bad Row Pair Address for Sector 4"
|
|
line.long 0xC "RED_CTL67,Redundancy Control normal sectors 6.7"
|
|
bitfld.long 0xC 24. "RED_EN_7,1: Redundancy Enable for Sector 7" "?,1: Redundancy Enable for Sector 7"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--23. 1. "RED_ADDR_7,Bad Row Pair Address for Sector 7"
|
|
newline
|
|
bitfld.long 0xC 8. "RED_EN_6,1: Redundancy Enable for Sector 6" "?,1: Redundancy Enable for Sector 6"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "RED_ADDR_6,Bad Row Pair Address for Sector 6"
|
|
line.long 0x10 "RED_CTL_SM01,Redundancy Control special sectors 0.1"
|
|
bitfld.long 0x10 24. "RED_EN_SM1,Redundancy Enable for Special Sector 1" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--23. 1. "RED_ADDR_SM1,Bad Row Pair Address for Special Sector 1"
|
|
newline
|
|
bitfld.long 0x10 8. "RED_EN_SM0,Redundancy Enable for Special Sector 0" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "RED_ADDR_SM0,Bad Row Pair Address for Special Sector 0"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "RGRANT_DELAY_PRG,R-grant delay for program"
|
|
bitfld.long 0x0 31. "HV_PARAMS_LOADED,0: HV Pulse common params not loaded" "0: HV Pulse common params not loaded,1: HV Pulse common params loaded: r-grant delays"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "RGRANT_DELAY_CLK,Frequency divider from clk_t to create the 8MHz reference clock for R_grant delay"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RGRANT_DELAY_SEQ30,PROG&PRE_PROG & ERASE: R-grant blocking delay on seq3-seq0 transition. Scale = ANA_CTL0.SCALE_SEQ30"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RGRANT_DELAY_PRG_SEQ23,PROG&PRE_PROG: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RGRANT_DELAY_PRG_SEQ12,PROG&PRE_PROG: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12"
|
|
group.long 0xA0++0xF
|
|
line.long 0x0 "PW_SEQ12,HV Pulse Delay for seq 1&2 pre"
|
|
hexmask.long.word 0x0 16.--31. 1. "PW_SEQ2_PRE,Seq2 pre delay"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PW_SEQ1,Seq1 delay"
|
|
line.long 0x4 "PW_SEQ23,HV Pulse Delay for seq2 post & seq3"
|
|
hexmask.long.word 0x4 16.--31. 1. "PW_SEQ3,Seq3 delay"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "PW_SEQ2_POST,Seq2 post delay"
|
|
line.long 0x8 "RGRANT_SCALE_ERS,R-grant delay scale for erase"
|
|
hexmask.long.byte 0x8 24.--31. 1. "RGRANT_DELAY_ERS_PEOFF,ERASE: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--23. 1. "RGRANT_DELAY_ERS_PEON,ERASE: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "SCALE_ERS_PEOFF,ERASE: Scale for R_GRANT_DELAY on PE OFF transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "SCALE_ERS_PEON,ERASE: Scale for R_GRANT_DELAY on PE On transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "SCALE_ERS_SEQ23,ERASE: Scale for R_GRANT_DELAY on seq2-seq3 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "SCALE_ERS_SEQ12,ERASE: Scale for R_GRANT_DELAY on seq1-seq2 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "SCALE_ERS_SEQ01,ERASE: Scale for R_GRANT_DELAY on seq0-seq1 transition:" "0: 0,1: 1uS,?,?"
|
|
line.long 0xC "RGRANT_DELAY_ERS,R-grant delay for erase"
|
|
hexmask.long.byte 0xC 16.--23. 1. "RGRANT_DELAY_ERS_SEQ23,ERASE: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "RGRANT_DELAY_ERS_SEQ12,ERASE: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "RGRANT_DELAY_ERS_SEQ01,ERASE: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01"
|
|
group.long 0x7FC++0x3
|
|
line.long 0x0 "FM_PL_WRDATA_ALL,Flash macro write page latches all"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Write all high Voltage page latches with the same 32-bit data in a single write cycle"
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x800)++0x3
|
|
line.long 0x0 "FM_PL_DATA[$1],Flash macro Page Latches data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Four page latch Bytes"
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0xC00)++0x3
|
|
line.long 0x0 "FM_MEM_DATA[$1],Flash macro memory sense amplifier and column decoder data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL:"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
tree "FM_CTL (Flash Macro Registers)"
|
|
base ad:0x4024F000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FM_CTL,Flash macro control"
|
|
bitfld.long 0x0 25. "WR_EN,0: normal mode" "0: normal mode,1: Fm Write Enable"
|
|
newline
|
|
bitfld.long 0x0 24. "IF_SEL,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DAA_MUX_SEL,N/A"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FM_SEQ,N/A" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "FM_MODE,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PUMP_NDAC,Test_only internal node: regif ndac outputs to pos pump"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PUMP_PDAC,Test_only internal node: regif pdac outputs to pos pump"
|
|
newline
|
|
bitfld.long 0x0 23. "RQ_ERROR,Test_only internal node: rq_error sync-de in clk_c domain" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CBUS_RED_ROW_EN,Test_only internal node: mpcon red_row_en" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "CBUS_RA_MATCH,Test_only internal node: mpcon ra match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "HVOP_BULK_ALL,Test_only internal node: mpcon bk_all" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "HVOP_SECTOR,Test_only internal node: mpcon bk_sec" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "HVOP_SUB_SECTOR_N,Test_only internal node: mpcon bk_subb" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ROW_EVEN,Test_only internal node: mpcon row_even" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ROW_ODD,Test_only internal node: mpcon row_odd" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RESET_MM,Test_only internal node: mpcon reset_mm" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "SECTOR0_SR,0: Sector 0 does not contain special rows. The special rows are located in separate special sectors." "0: Sector 0 does not contain special rows,1: Sector 0 contains special rows"
|
|
newline
|
|
bitfld.long 0x0 13. "MAX_DOUT_WIDTH,Internal memory core max data out size" "0: x128 bits,1: x256 bits"
|
|
newline
|
|
bitfld.long 0x0 12. "RWW,FM Type (Read While Write or Not Read While Write):" "0: Non RWW FM Type,1: RWW FM Type"
|
|
newline
|
|
bitfld.long 0x0 11. "NEG_PUMP_VHI,NEG pump VHI" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "POS_PUMP_VLO,POS pump VLO" "0,1"
|
|
newline
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bitfld.long 0x0 9. "FM_READY,0: FM not ready" "0: FM not ready,1: FM ready"
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bitfld.long 0x0 8. "FM_BUSY,0': FM not busy" "0: FM not busy,1: FM BUSY : R_GRANT is 0 as result of a busy.."
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bitfld.long 0x0 7. "R_GRANT_DELAY_STATUS,0: R_GRANT_DELAY timer is not running" "0: R_GRANT_DELAY timer is not running,1: R_GRANT_DELAY timer is running"
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bitfld.long 0x0 6. "TIMER_STATUS,The actual timer state sync-ed in clk_c domain:" "0: timer is not running:,1: timer is running"
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bitfld.long 0x0 5. "IF_SEL_MON,FM_CTL.IF_SEL bit after being synchronized in clk_r domain" "0,1"
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bitfld.long 0x0 4. "WR_EN_MON,FM_CTL.WR_EN bit after being synchronized in clk_r domain" "0,1"
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bitfld.long 0x0 3. "TURBO_N,After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.." "0: turbo mode,1: normal mode"
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bitfld.long 0x0 2. "ILLEGAL_HVOP,Indicates a bulk sector erase program has been requested when axa=1" "0: no error,1: illegal HV operation error"
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bitfld.long 0x0 1. "HV_REGS_ISOLATED,Indicates the isolation status at HV trim and redundancy registers inputs" "0: Not isolated,1: isolated writing disabled"
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bitfld.long 0x0 0. "TIMER_ENABLED,This is the timer_en bit set by writing a '1' in the TIMER_CTL bit 31. It is reset by HW when the timer expires" "0: timer not running,1: Timer is enabled and not expired yet"
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group.long 0x8++0x7
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line.long 0x0 "FM_ADDR,Flash macro address"
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bitfld.long 0x0 24. "AXA,Auxiliary address field:" "0: regular flash memory,1: supervisory flash memory"
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hexmask.long.byte 0x0 16.--23. 1. "BA,Bank address."
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hexmask.long.word 0x0 0.--15. 1. "RA,Row address."
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line.long 0x4 "BOOKMARK,Bookmark register - keeps the current FW HV seq"
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hexmask.long 0x4 0.--31. 1. "BOOKMARK,Used by FW. Keeps the Current HV cycle sequence"
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rgroup.long 0x10++0x7
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line.long 0x0 "GEOMETRY,Regular flash geometry"
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hexmask.long.byte 0x0 28.--31. 1. "PAGE_SIZE_LOG2,Number of Bytes per page (log 2):"
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hexmask.long.byte 0x0 24.--27. 1. "WORD_SIZE_LOG2,Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access:"
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hexmask.long.byte 0x0 16.--23. 1. "BANK_COUNT,Number of banks (minus 1):"
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hexmask.long.word 0x0 0.--15. 1. "ROW_COUNT,Number of rows (minus 1):"
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line.long 0x4 "GEOMETRY_SUPERVISORY,Supervisory flash geometry"
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hexmask.long.byte 0x4 28.--31. 1. "PAGE_SIZE_LOG2,Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2."
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hexmask.long.byte 0x4 24.--27. 1. "WORD_SIZE_LOG2,Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2."
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hexmask.long.byte 0x4 16.--23. 1. "BANK_COUNT,Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT."
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hexmask.long.word 0x4 0.--15. 1. "ROW_COUNT,Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT"
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group.long 0x18++0x7
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line.long 0x0 "ANA_CTL0,Analog control 0"
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bitfld.long 0x0 30.--31. "SCALE_PRG_PEOFF,PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE OFF transition:" "0: 0,1: 1uS,?,?"
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bitfld.long 0x0 28.--29. "SCALE_PRG_PEON,PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE On transition:" "0: 0,1: 1uS,?,?"
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bitfld.long 0x0 26.--27. "SCALE_SEQ30,PROG&PRE_PROG& ERASE: Scale for R_GRANT_DELAY on seq3-seq0 transition:" "0: 0,1: 1uS,?,?"
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bitfld.long 0x0 24.--25. "SCALE_PRG_SEQ23,PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq2-seq3 transition:" "0: 0,1: 1uS,?,?"
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bitfld.long 0x0 22.--23. "SCALE_PRG_SEQ12,PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq1-seq2 transition:" "0: 0,1: 1uS,?,?"
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bitfld.long 0x0 20.--21. "SCALE_PRG_SEQ01,PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq0-seq1 transition:" "0: 0,1: 1uS,?,?"
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hexmask.long.byte 0x0 16.--19. 1. "PDAC_MIN,PDAC staircase min value"
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hexmask.long.byte 0x0 12.--15. 1. "NDAC_MIN,NDAC staircase min value"
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bitfld.long 0x0 11. "FLIP_AMUXBUS_AB,Flips amuxbusa and amuxbusb" "0: amuxbusa,1: amuxbusb"
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bitfld.long 0x0 8.--10. "CSLDAC,Trimming of common source line DAC." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 0.--7. 1. "MDAC,Trimming of the output margin Voltage as a function of Vpos and Vneg."
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line.long 0x4 "ANA_CTL1,Analog control 1"
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hexmask.long.byte 0x4 24.--31. 1. "NPDAC_ZERO_TIME,Ndac/Pdac LO duration: (1uS .. 255uS) * 8"
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hexmask.long.byte 0x4 16.--23. 1. "NPDAC_STEP_TIME,Ndac/Pdac step duration: (1uS .. 255uS) * 8"
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hexmask.long.byte 0x4 12.--15. 1. "PDAC_STEP,Pdac step increment"
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hexmask.long.byte 0x4 8.--11. 1. "PDAC_MAX,Pdac Max Value.Trimming of positive pump output Voltage:"
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hexmask.long.byte 0x4 4.--7. 1. "NDAC_STEP,Ndac step increment"
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hexmask.long.byte 0x4 0.--3. 1. "NDAC_MAX,Ndac Max Value.Trimming of negative pump output Voltage."
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group.long 0x28++0x3
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line.long 0x0 "WAIT_CTL,Wait State control"
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bitfld.long 0x0 29. "PL_SOFT_SET_EN,Page latch soft set enable 0 = disabled 1 = enabled (at end of seq_2) taken care in API" "0: disabled,1: enabled"
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bitfld.long 0x0 28. "MBA,0: Normal" "0: Normal,1: Test mode to enable Master Bulk Access which.."
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bitfld.long 0x0 27. "DRMM,0: Normal" "0: Normal,1: Test mode to enable Margin mode for 2 rows at a.."
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bitfld.long 0x0 26. "LV_SPARE_1,Spare register" "0,1"
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bitfld.long 0x0 24.--25. "FM_RWW_MODE,00: Full CBUS MODE" "0: Full CBUS MODE,1: RWW,?,?"
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bitfld.long 0x0 16.--18. "WAIT_FM_HV_WR,Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 8.--11. 1. "WAIT_FM_HV_RD,Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches."
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hexmask.long.byte 0x0 0.--3. 1. "WAIT_FM_MEM_RD,Number of C interface wait cycles (on 'clk_c') for a read from the memory"
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group.long 0x34++0x7
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line.long 0x0 "TIMER_CLK_CTL,Timer prescaler (clk_t to timer clock frequency divider)"
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hexmask.long.byte 0x0 24.--31. 1. "RGRANT_DELAY_PRG_SEQ01,PROG&PRE_PROG: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01"
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hexmask.long.byte 0x0 16.--23. 1. "RGRANT_DELAY_PRG_PEOFF,PROG&PRE_PROG: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF"
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hexmask.long.byte 0x0 8.--15. 1. "RGRANT_DELAY_PRG_PEON,PROG&PRE_PROG: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON"
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hexmask.long.byte 0x0 0.--7. 1. "TIMER_CLOCK_FREQ,Clk_t frequency divider to provide the 1MHz reference clock for the Regif Timer."
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line.long 0x4 "TIMER_CTL,Timer control"
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bitfld.long 0x4 31. "TIMER_EN,Timer enable:" "0: disabled,1: enabled"
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bitfld.long 0x4 30. "ACLK_EN,ACLK enable (generates a single cycle pulse for the FM):" "0: disabled,1: enabled"
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bitfld.long 0x4 29. "PUMP_EN,Pump enable:" "0: disabled,1: enabled"
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bitfld.long 0x4 26. "PRE_PROG_CSL,0: CSL lines driven by CSL_DAC" "0: CSL lines driven by CSL_DAC,1: CSL lines driven by VNEG_G"
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bitfld.long 0x4 25. "PRE_PROG,1 during pre-program operation" "0,1"
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bitfld.long 0x4 24. "AUTO_SEQUENCE,1': Starts1 the HV automatic sequencing" "?,1: Starts1 the HV automatic sequencing"
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newline
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bitfld.long 0x4 15. "SCALE,Timer tick scale:" "0: 1 microsecond,1: 100 microseconds"
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newline
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hexmask.long.word 0x4 0.--14. 1. "PERIOD,Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples."
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wgroup.long 0x3C++0x3
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line.long 0x0 "ACLK_CTL,MPCON clock"
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bitfld.long 0x0 0. "ACLK_GEN,A write to this register generates the clock pulse for HV control registers (mpcon outputs)" "0,1"
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group.long 0x40++0xB
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line.long 0x0 "INTR,Interrupt"
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bitfld.long 0x0 0. "TIMER_EXPIRED,Set to '1' when event is detected. Write INTR field with '1' to clear bit. Write INTR_SET field with '1' to set bit." "0,1"
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line.long 0x4 "INTR_SET,Interrupt set"
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bitfld.long 0x4 0. "TIMER_EXPIRED,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
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line.long 0x8 "INTR_MASK,Interrupt mask"
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bitfld.long 0x8 0. "TIMER_EXPIRED,Mask for corresponding field in INTR register." "0,1"
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rgroup.long 0x4C++0x3
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line.long 0x0 "INTR_MASKED,Interrupt masked"
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bitfld.long 0x0 0. "TIMER_EXPIRED,Logical and of corresponding request and mask fields." "0,1"
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group.long 0x50++0x1F
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line.long 0x0 "CAL_CTL0,Cal control BG LO trim bits"
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bitfld.long 0x0 19. "IPREF_TRIMA_LO_HV,Adds 100-150nA boost on IPREF_LO" "0,1"
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bitfld.long 0x0 16.--18. "ICREF_TC_TRIM_LO_HV,LO Bandgap Current Temperature Compensation trim control" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 13.--15. "VBG_TC_TRIM_LO_HV,LO Bandgap Voltage Temperature Compensation trim control" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 8.--12. 1. "VBG_TRIM_LO_HV,LO Bandgap Voltage trim control."
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newline
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bitfld.long 0x0 5.--7. "CDAC_LO_HV,LO Temperature compensated trim DAC. To control Vcstat slope for Vpos." "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x0 0.--4. 1. "VCT_TRIM_LO_HV,LO Bandgap Voltage Temperature Compensation trim control."
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line.long 0x4 "CAL_CTL1,Cal control BG HI trim bits"
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bitfld.long 0x4 19. "IPREF_TRIMA_HI_HV,Adds 100-150nA boost on IPREF_HI" "0,1"
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newline
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bitfld.long 0x4 16.--18. "ICREF_TC_TRIM_HI_HV,HI Bandgap Current Temperature Compensation trim control." "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x4 13.--15. "VBG_TC_TRIM_HI_HV,HI Bandgap Voltage Temperature Compensation trim control." "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x4 8.--12. 1. "VBG_TRIM_HI_HV,HI Bandgap Voltage trim control."
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newline
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bitfld.long 0x4 5.--7. "CDAC_HI_HV,HI Temperature compensated trim DAC. To control Vcstat slope for Vpos." "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x4 0.--4. 1. "VCT_TRIM_HI_HV,HI Bandgap Voltage Temperature Compensation trim control."
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line.long 0x8 "CAL_CTL2,Cal control BG LO&HI trim bits"
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hexmask.long.byte 0x8 15.--19. 1. "IPREF_TRIM_HI_HV,HI Bandgap IPTAT trim control."
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newline
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hexmask.long.byte 0x8 10.--14. 1. "IPREF_TRIM_LO_HV,LO Bandgap IPTAT trim control."
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newline
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hexmask.long.byte 0x8 5.--9. 1. "ICREF_TRIM_HI_HV,HI Bandgap Current trim control."
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newline
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hexmask.long.byte 0x8 0.--4. 1. "ICREF_TRIM_LO_HV,LO Bandgap Current trim control."
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line.long 0xC "CAL_CTL3,Cal control osc trim bits. idac. sdac. itim"
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bitfld.long 0xC 19. "LP_ULP_SW_HV,LP<-->ULP switch for trim signals:" "0: LP,1: ULP"
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newline
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bitfld.long 0xC 18. "R_GRANT_EN_HV,0: r_grant handshake disabled r_grant always 1." "0: r_grant handshake disabled,1: r_grand handshake enabled"
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newline
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bitfld.long 0xC 17. "CL_ISO_DIS_HV,0: The internal logic controls the CL isolation" "0: The internal logic controls the CL isolation,1: Forces CL bypass"
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newline
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bitfld.long 0xC 16. "BGHI_EN_HV,0: Normal (Automatic change over from HI to LO)" "0: Normal,1: Force enable HI Bandgap"
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newline
|
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bitfld.long 0xC 15. "BGLO_EN_HV,0: Normal (Automatic change over from HI to LO)" "0: Normal,1: Force enable LO Bandgap"
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newline
|
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bitfld.long 0xC 13.--14. "TURBO_PULSEW_HV,Turbo pulse width trim (Typical)" "0: 40 us,1: 20 us,?,?"
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newline
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bitfld.long 0xC 12. "VDDHI_HV,0: vdd < 2.3V" "0: vdd < 2,1: vdd >= 2"
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newline
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bitfld.long 0xC 10.--11. "FDIV_TRIM_HV,FDIV_TRIM_HV[1:0]: Assuming oscillator frequency of 8MHz in standby." "0: F = 1MHz,1: F = 0,?,?"
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newline
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bitfld.long 0xC 9. "REG_ACT_HV,0: VBST regulator will operate in active/standby mode based on control signal." "0: VBST regulator will operate in active/standby..,1: Forces the VBST regulator in active mode all the.."
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newline
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bitfld.long 0xC 8. "IREF_SEL_HV,Current reference:" "0: internal current reference,1: external current reference"
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newline
|
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bitfld.long 0xC 7. "VREF_SEL_HV,Voltage reference:" "0: internal bandgap reference,1: external voltage reference"
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newline
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bitfld.long 0xC 6. "IPREF_TC_HV,0: Increases the IPREF Tempco by subtracting ICREF from IPREF - IPREF internal will be 0.5uA" "0: Increases the IPREF Tempco by subtracting ICREF..,1: Reduces the IPREF Tempco without subtracting.."
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bitfld.long 0xC 5. "VPROT_ACT_HV,Forces VPROT in active mode all the time" "0,1"
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newline
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bitfld.long 0xC 4. "OSC_RANGE_TRIM_HV,0: Oscillator High Frequency Range" "0: Oscillator High Frequency Range,1: Oscillator Low Frequency range"
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newline
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hexmask.long.byte 0xC 0.--3. 1. "OSC_TRIM_HV,Flash macro pump clock trim control."
|
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line.long 0x10 "CAL_CTL4,Cal Control Vlim. SA. fdiv. reg_act"
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bitfld.long 0x10 19. "UGB_EN_HV,UGB enable in TM control" "0,1"
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newline
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bitfld.long 0x10 18. "AUTO_HVPULSE_HV,0: HV Pulse controlled by FW" "0: HV Pulse controlled by FW,1: HV Pulse controlled by Hardware"
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newline
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bitfld.long 0x10 17. "VBST_S_DIS_HV,0: VBST_S voltage for each sector to allow VBST level to be dropped to VCC during Erase in the selected sector reducing coupling to GBL." "0: VBST_S voltage for each sector to allow VBST..,1: VBST_S voltage for each sector stays at VBST.."
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bitfld.long 0x10 16. "READY_RESTART_N_HV,Toggle: 1-->0 ready goes low ready will remain low as long as the bit is low. Toggle the bit back to 1 to activate the ready logic. To be used by API only." "0,1"
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bitfld.long 0x10 15. "SPARE451_ULP_HV,N/A" "0,1"
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bitfld.long 0x10 13.--14. "FM_READY_DEL_ULP_HV,00: Default : delay 1ns" "0: Default : delay 1ns,1: Delayed by 1,?,?"
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|
newline
|
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hexmask.long.byte 0x10 8.--12. 1. "ITIM_ULP_HV,Trimming of timing current"
|
|
newline
|
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bitfld.long 0x10 6.--7. "SDAC_ULP_HV,Sets the sense current reference temp slope. Refer to trim tables for details." "0,1,2,3"
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newline
|
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hexmask.long.byte 0x10 2.--5. 1. "IDAC_ULP_HV,Sets the sense current reference offset value. Refer to trim tables for details."
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bitfld.long 0x10 0.--1. "VLIM_TRIM_ULP_HV,VLIM_TRIM[1:0]:" "0: V2 = 650mV,1: V2 = 600mV,?,?"
|
|
line.long 0x14 "CAL_CTL5,Cal control"
|
|
bitfld.long 0x14 18.--19. "AMUX_SEL_HV,Amux Select in AMUX_UGB" "0: Bypass UGB for both amuxbusa and amuxbusb,1: Bypass UGB for amuxbusb while passing amuxbusa..,?,?"
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bitfld.long 0x14 16.--17. "SPARE52_HV,N/A" "0,1,2,3"
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|
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bitfld.long 0x14 15. "SPARE451_LP_HV,N/A" "0,1"
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|
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|
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bitfld.long 0x14 13.--14. "FM_READY_DEL_LP_HV,00: Delayed by 1us" "0: Delayed by 1us,1: Delayed by 1,?,?"
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|
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hexmask.long.byte 0x14 8.--12. 1. "ITIM_LP_HV,Trimming of timing current"
|
|
newline
|
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bitfld.long 0x14 6.--7. "SDAC_LP_HV,Sets the sense current reference temp slope. Refer to trim tables for details." "0,1,2,3"
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newline
|
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hexmask.long.byte 0x14 2.--5. 1. "IDAC_LP_HV,Sets the sense current reference offset value. Refer to trim tables for details."
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|
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bitfld.long 0x14 0.--1. "VLIM_TRIM_LP_HV,VLIM_TRIM[1:0]:" "0: V2 = 650mV,1: V2 = 600mV,?,?"
|
|
line.long 0x18 "CAL_CTL6,SA trim LP/ULP"
|
|
bitfld.long 0x18 19. "SA_CTL_TRIM_T8_LP_HV,saen3 pulse width trim (Current trim)" "0,1"
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bitfld.long 0x18 17.--18. "SA_CTL_TRIM_T6_LP_HV,SA_CTL_TRIM_T6_LP_HV<1>= eni (enable current trim)" "0,1,2,3"
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bitfld.long 0x18 14.--16. "SA_CTL_TRIM_T5_LP_HV,SA_CTL_TRIM_T5_LP_HV<2>= evi (integration current trim)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 11.--13. "SA_CTL_TRIM_T4_LP_HV,SA_CTL_TRIM_T4_LP_HV<2>= eqi (eq current trim)" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x18 10. "SA_CTL_TRIM_T1_LP_HV,clk_trk delay" "0,1"
|
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newline
|
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bitfld.long 0x18 9. "SA_CTL_TRIM_T8_ULP_HV,saen3 pulse width trim (Current trim)" "0,1"
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newline
|
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bitfld.long 0x18 7.--8. "SA_CTL_TRIM_T6_ULP_HV,SA_CTL_TRIM_T6_ULP_HV<1>= eni (enable current trim)" "0,1,2,3"
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newline
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bitfld.long 0x18 4.--6. "SA_CTL_TRIM_T5_ULP_HV,SA_CTL_TRIM_T5_ULP_HV<2>= evi (integration current trim)" "0,1,2,3,4,5,6,7"
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newline
|
|
bitfld.long 0x18 1.--3. "SA_CTL_TRIM_T4_ULP_HV,SA_CTL_TRIM_T4_ULP_HV<2>= eqi (eq current trim)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 0. "SA_CTL_TRIM_T1_ULP_HV,clk_trk delay" "0,1"
|
|
line.long 0x1C "CAL_CTL7,Cal control"
|
|
hexmask.long.byte 0x1C 15.--19. 1. "SPARE7_LP_HV,N/A"
|
|
newline
|
|
hexmask.long.byte 0x1C 10.--14. 1. "SPARE7_ULP_HV,N/A"
|
|
newline
|
|
bitfld.long 0x1C 8.--9. "SPARE7_HV,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1C 7. "DISABLE_LOAD_ONCE_HV,0: Load common HV params during API HV operations depends on the HV_PARAMS_LOADED bit in RGRANT_DELAY_PRG register." "0: Load common HV params during API HV operations..,1: All HV params are loaded during every API HV.."
|
|
newline
|
|
bitfld.long 0x1C 6. "ERSX8_EN_ALL_HV,0': Staggered turn on/off of GWL" "0: Staggered turn on/off of GWL,1: GWL are turned on/off at the same time"
|
|
newline
|
|
bitfld.long 0x1C 5. "FM_READY_DIS_HV,0': fm ready is enabled" "0: fm ready is enabled,1: fm ready is disabled"
|
|
newline
|
|
bitfld.long 0x1C 4. "NPDAC_HWCTL_DIS_HV,0': ndac pdac staircase hardware controlled" "0: ndac,1: ndac"
|
|
newline
|
|
bitfld.long 0x1C 3. "TURBO_EXT_HV,0: Normal operation" "0: Normal operation,1: Uses external turbo pulse"
|
|
newline
|
|
bitfld.long 0x1C 2. "FM_ACTIVE_HV,0: Normal operation" "0: Normal operation,1: Forces FM SYS in active mode"
|
|
newline
|
|
bitfld.long 0x1C 0.--1. "ERSX8_CLK_SEL_HV,Clock frequency into the ersx8 shift register block" "0: Oscillator clock,1: Oscillator clock / 2,?,?"
|
|
group.long 0x80++0x13
|
|
line.long 0x0 "RED_CTL01,Redundancy Control normal sectors 0.1"
|
|
bitfld.long 0x0 24. "RED_EN_1,1: Redundancy Enable for Sector 1" "?,1: Redundancy Enable for Sector 1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RED_ADDR_1,Bad Row Pair Address for Sector 1"
|
|
newline
|
|
bitfld.long 0x0 8. "RED_EN_0,1: Redundancy Enable for Sector 0" "?,1: Redundancy Enable for Sector 0"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RED_ADDR_0,Bad Row Pair Address for Sector 0"
|
|
line.long 0x4 "RED_CTL23,Redundancy Control normal sectors 2.3"
|
|
bitfld.long 0x4 24. "RED_EN_3,1: Redundancy Enable for Sector 3" "?,1: Redundancy Enable for Sector 3"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "RED_ADDR_3,Bad Row Pair Address for Sector 3"
|
|
newline
|
|
bitfld.long 0x4 8. "RED_EN_2,1: Redundancy Enable for Sector 2" "?,1: Redundancy Enable for Sector 2"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RED_ADDR_2,Bad Row Pair Address for Sector 2"
|
|
line.long 0x8 "RED_CTL45,Redundancy Control normal sectors 4.5"
|
|
bitfld.long 0x8 24. "RED_EN_5,1: Redundancy Enable for Sector 5" "?,1: Redundancy Enable for Sector 5"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--23. 1. "RED_ADDR_5,Bad Row Pair Address for Sector 5"
|
|
newline
|
|
bitfld.long 0x8 8. "RED_EN_4,1: Redundancy Enable for Sector 4" "?,1: Redundancy Enable for Sector 4"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "RED_ADDR_4,Bad Row Pair Address for Sector 4"
|
|
line.long 0xC "RED_CTL67,Redundancy Control normal sectors 6.7"
|
|
bitfld.long 0xC 24. "RED_EN_7,1: Redundancy Enable for Sector 7" "?,1: Redundancy Enable for Sector 7"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--23. 1. "RED_ADDR_7,Bad Row Pair Address for Sector 7"
|
|
newline
|
|
bitfld.long 0xC 8. "RED_EN_6,1: Redundancy Enable for Sector 6" "?,1: Redundancy Enable for Sector 6"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "RED_ADDR_6,Bad Row Pair Address for Sector 6"
|
|
line.long 0x10 "RED_CTL_SM01,Redundancy Control special sectors 0.1"
|
|
bitfld.long 0x10 24. "RED_EN_SM1,Redundancy Enable for Special Sector 1" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--23. 1. "RED_ADDR_SM1,Bad Row Pair Address for Special Sector 1"
|
|
newline
|
|
bitfld.long 0x10 8. "RED_EN_SM0,Redundancy Enable for Special Sector 0" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "RED_ADDR_SM0,Bad Row Pair Address for Special Sector 0"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "RGRANT_DELAY_PRG,R-grant delay for program"
|
|
bitfld.long 0x0 31. "HV_PARAMS_LOADED,0: HV Pulse common params not loaded" "0: HV Pulse common params not loaded,1: HV Pulse common params loaded: r-grant delays"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "RGRANT_DELAY_CLK,Frequency divider from clk_t to create the 8MHz reference clock for R_grant delay"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RGRANT_DELAY_SEQ30,PROG&PRE_PROG & ERASE: R-grant blocking delay on seq3-seq0 transition. Scale = ANA_CTL0.SCALE_SEQ30"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RGRANT_DELAY_PRG_SEQ23,PROG&PRE_PROG: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RGRANT_DELAY_PRG_SEQ12,PROG&PRE_PROG: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12"
|
|
group.long 0xA0++0xF
|
|
line.long 0x0 "PW_SEQ12,HV Pulse Delay for seq 1&2 pre"
|
|
hexmask.long.word 0x0 16.--31. 1. "PW_SEQ2_PRE,Seq2 pre delay"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PW_SEQ1,Seq1 delay"
|
|
line.long 0x4 "PW_SEQ23,HV Pulse Delay for seq2 post & seq3"
|
|
hexmask.long.word 0x4 16.--31. 1. "PW_SEQ3,Seq3 delay"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "PW_SEQ2_POST,Seq2 post delay"
|
|
line.long 0x8 "RGRANT_SCALE_ERS,R-grant delay scale for erase"
|
|
hexmask.long.byte 0x8 24.--31. 1. "RGRANT_DELAY_ERS_PEOFF,ERASE: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--23. 1. "RGRANT_DELAY_ERS_PEON,ERASE: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "SCALE_ERS_PEOFF,ERASE: Scale for R_GRANT_DELAY on PE OFF transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "SCALE_ERS_PEON,ERASE: Scale for R_GRANT_DELAY on PE On transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "SCALE_ERS_SEQ23,ERASE: Scale for R_GRANT_DELAY on seq2-seq3 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "SCALE_ERS_SEQ12,ERASE: Scale for R_GRANT_DELAY on seq1-seq2 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "SCALE_ERS_SEQ01,ERASE: Scale for R_GRANT_DELAY on seq0-seq1 transition:" "0: 0,1: 1uS,?,?"
|
|
line.long 0xC "RGRANT_DELAY_ERS,R-grant delay for erase"
|
|
hexmask.long.byte 0xC 16.--23. 1. "RGRANT_DELAY_ERS_SEQ23,ERASE: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "RGRANT_DELAY_ERS_SEQ12,ERASE: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "RGRANT_DELAY_ERS_SEQ01,ERASE: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01"
|
|
group.long 0x7FC++0x3
|
|
line.long 0x0 "FM_PL_WRDATA_ALL,Flash macro write page latches all"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Write all high Voltage page latches with the same 32-bit data in a single write cycle"
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x800)++0x3
|
|
line.long 0x0 "FM_PL_DATA[$1],Flash macro Page Latches data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Four page latch Bytes"
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0xC00)++0x3
|
|
line.long 0x0 "FM_MEM_DATA[$1],Flash macro memory sense amplifier and column decoder data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL:"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x4025F000
|
|
elif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
base ad:0x4024F000
|
|
endif
|
|
tree "FM_CTL (Flash Macro Registers)"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FM_CTL,Flash macro control"
|
|
bitfld.long 0x0 25. "WR_EN,'0': normal mode" "0: normal mode,1: Fm Write Enable"
|
|
newline
|
|
bitfld.long 0x0 24. "IF_SEL,Interface selection. Specifies the interface that is used for flash memory read operations:" "0: R interface is used,1: C interface is used"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DAA_MUX_SEL,Direct memory cell access address."
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FM_SEQ,Flash macro sequence select:" "0: TBD,1: TBD,2: TBD,3: TBD"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "FM_MODE,Flash macro mode selection:"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
hexmask.long.byte 0x0 28.--31. 1. "PUMP_NDAC,Test_only internal node: regif ndac outputs to pos pump"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PUMP_PDAC,Test_only internal node: regif pdac outputs to pos pump"
|
|
newline
|
|
rbitfld.long 0x0 23. "RQ_ERROR,Test_only internal node: rq_error sync-de in clk_c domain" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 22. "CBUS_RED_ROW_EN,Test_only internal node: mpcon red_row_en" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 21. "CBUS_RA_MATCH,Test_only internal node: mpcon ra match" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 20. "HVOP_BULK_ALL,Test_only internal node: mpcon bk_all" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 19. "HVOP_SECTOR,Test_only internal node: mpcon bk_sec" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 18. "HVOP_SUB_SECTOR_N,Test_only internal node: mpcon bk_subb" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 17. "ROW_EVEN,Test_only internal node: mpcon row_even" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "ROW_ODD,Test_only internal node: mpcon row_odd" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 15. "RESET_MM,Test_only internal node: mpcon reset_mm" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 14. "SECTOR0_SR,0: Sector 0 does not contain special rows. The special rows are located in separate special sectors." "0: Sector 0 does not contain special rows,1: Sector 0 contains special rows"
|
|
newline
|
|
rbitfld.long 0x0 13. "MAX_DOUT_WIDTH,Internal memory core max data out size" "0: x128 bits,1: x256 bits"
|
|
newline
|
|
rbitfld.long 0x0 12. "RWW,FM Type (Read While Write or Not Read While Write):" "0: Non RWW FM Type,1: RWW FM Type"
|
|
newline
|
|
rbitfld.long 0x0 11. "NEG_PUMP_VHI,NEG pump VHI" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 10. "POS_PUMP_VLO,POS pump VLO" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 9. "FM_READY,0: FM not ready" "0: FM not ready,1: FM ready"
|
|
newline
|
|
rbitfld.long 0x0 8. "FM_BUSY,0': FM not busy" "0: FM not busy,1: FM BUSY : R_GRANT is 0 as result of a busy.."
|
|
newline
|
|
rbitfld.long 0x0 7. "R_GRANT_DELAY_STATUS,0: R_GRANT_DELAY timer is not running" "0: R_GRANT_DELAY timer is not running,1: R_GRANT_DELAY timer is running"
|
|
newline
|
|
rbitfld.long 0x0 6. "TIMER_STATUS,The actual timer state sync-ed in clk_c domain:" "0: timer is not running:,1: timer is running"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x0 5. "IF_SEL_MON,FM_CTL.IF_SEL bit after being synchronized in clk_r domain" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "WR_EN_MON,FM_CTL.WR_EN bit after being synchronized in clk_r domain" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "TURBO_N,After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 2. "ILLEGAL_HVOP,Indicates a bulk sector erase program has been requested when axa=1" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "HV_REGS_ISOLATED,Indicates the isolation status at HV trim and redundancy registers inputs" "0,1"
|
|
newline
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
rbitfld.long 0x0 0. "HV_TIMER_RUNNING,Indicates if the high voltage timer is running:" "0: not running,1: running"
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
rbitfld.long 0x0 0. "TIMER_ENABLED,This is the timer_en bit set by writing a '1' in the TIMER_CTL bit 31. It is reset by HW when the timer expires" "0: timer not running,1: Timer is enabled and not expired yet"
|
|
endif
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "FM_ADDR,Flash macro address"
|
|
bitfld.long 0x0 24. "AXA,Auxiliary address field:" "0: regular flash memory,1: supervisory flash memory"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "BA,Bank address."
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RA,Row address."
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
rgroup.long 0xC++0x7
|
|
line.long 0x0 "GEOMETRY,Regular flash geometry"
|
|
hexmask.long.byte 0x0 24.--31. 1. "BANK_COUNT,Number of banks (minus 1):"
|
|
hexmask.long.word 0x0 8.--23. 1. "ROW_COUNT,Number of rows (minus 1):"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PAGE_SIZE_LOG2,Number of Bytes per page (log 2):"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WORD_SIZE_LOG2,Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access:"
|
|
line.long 0x4 "GEOMETRY_SUPERVISORY,Supervisory flash geometry"
|
|
hexmask.long.byte 0x4 24.--31. 1. "BANK_COUNT,Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT."
|
|
hexmask.long.word 0x4 8.--23. 1. "ROW_COUNT,Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "PAGE_SIZE_LOG2,Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2."
|
|
hexmask.long.byte 0x4 0.--3. 1. "WORD_SIZE_LOG2,Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2."
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TIMER_CTL,Timer control"
|
|
bitfld.long 0x0 31. "TIMER_EN,Timer enable:" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 30. "ACLK_EN,ACLK enable (generates a single cycle pulse for the FM):" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 29. "PUMP_EN,Pump enable:" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 26. "PRE_PROG_CSL,'0' CSL lines driven by CSL_DAC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PRE_PROG,'1' during pre-program operation" "0,1"
|
|
bitfld.long 0x0 24. "PUMP_CLOCK_SEL,Pump clock select:" "0: internal clock,1: external clock"
|
|
newline
|
|
bitfld.long 0x0 16. "SCALE,Timer tick scale:" "0: 1 microsecond,1: 100 microseconds"
|
|
hexmask.long.word 0x0 0.--15. 1. "PERIOD,Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples."
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "GEOMETRY_GEN,N/A. DNU"
|
|
bitfld.long 0x0 3. "DNU_0X20_3,N/A" "0,1"
|
|
bitfld.long 0x0 2. "DNU_0X20_2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DNU_0X20_1,N/A" "0,1"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TEST_CTL,Test mode control"
|
|
bitfld.long 0x0 31. "UNSCRAMBLE_WA,See BSN-242 memo" "0: normal,1: disables the Word Address scrambling"
|
|
bitfld.long 0x0 18. "ENABLE_OSC,0': the oscillator enable logic has control over the internal oscillator" "0: the oscillator enable logic has control over the..,1: forces oscillator enable HI"
|
|
newline
|
|
bitfld.long 0x0 17. "CSL_DEBUG,Engineering Debug Register" "0,1"
|
|
bitfld.long 0x0 16. "EN_CLK_MON,1: enables the oscillator output monitor" "?,1: enables the oscillator output monitor"
|
|
newline
|
|
bitfld.long 0x0 11. "TM_DISNEG,Test mode negative pump disable" "0,1"
|
|
bitfld.long 0x0 10. "TM_DISPOS,Test mode positive pump disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TM_PE,PUMP_EN override: Pump Enable =PUMP_EN | PE_TM" "0,1"
|
|
bitfld.long 0x0 8. "PN_CTL,Positive/negative margin mode control:" "0: negative margin control,1: positive margin control"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "TEST_MODE,Test mode control:"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "MONITOR_STATUS,Monitor Status"
|
|
bitfld.long 0x0 2. "NEG_PUMP_VHI,NEG pump VHI" "0,1"
|
|
bitfld.long 0x0 1. "POS_PUMP_VLO,POS pump VLO" "0,1"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "SCRATCH_CTL,Scratch Control"
|
|
hexmask.long 0x0 0.--31. 1. "DUMMY32,Scratchpad register fields. Provided for test purposes."
|
|
line.long 0x4 "HV_CTL,High voltage control"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TIMER_CLOCK_FREQ,Specifies the frequency in MHz of the timer clock 'clk_t' as provide to the flash macro. E.g. if '4' the timer clock 'clk_t' has a frequency of 4 MHz."
|
|
wgroup.long 0x38++0x3
|
|
line.long 0x0 "ACLK_CTL,Aclk control"
|
|
bitfld.long 0x0 0. "ACLK_GEN,A write to this register generates a ACLK pulse for the flash macro (also requires FM_CTL.IF_SEL to be '1')." "0,1"
|
|
group.long 0x3C++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 0. "TIMER_EXPIRED,Set to '1' when event is detected. Write INTR field with '1' to clear bit. Write INTR_SET field with '1' to set bit." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 0. "TIMER_EXPIRED,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 0. "TIMER_EXPIRED,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "TIMER_EXPIRED,Logical and of corresponding request and mask fields." "0,1"
|
|
wgroup.long 0x4C++0x3
|
|
line.long 0x0 "FM_HV_DATA_ALL,Flash macro high Voltage page latches data (for all page latches)"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Write all high Voltage page latches with the same 32-bit data in a single write cycle"
|
|
wgroup.long 0x60++0x3
|
|
line.long 0x0 "BOOKMARK,Bookmark register - keeps the current FW HV seq"
|
|
hexmask.long 0x0 0.--31. 1. "BOOKMARK,Used by FW. Keeps the Current HV cycle sequence"
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x100)++0x3
|
|
line.long 0x0 "TM_CMPR[$1],Do Not Use"
|
|
bitfld.long 0x0 0. "DATA_COMP_RESULT,The result of a comparison between the flash macro data output and the content of the high voltage page latches." "0: FALSE,1: TRUE"
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x800)++0x3
|
|
line.long 0x0 "FM_HV_DATA[$1],Flash macro high Voltage page latches data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Four page latch Bytes (when writing to the page latches it also requires FM_CTL.IF_SEL to be '1')."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "BOOKMARK,Bookmark register - keeps the current FW HV seq"
|
|
hexmask.long 0x0 0.--31. 1. "BOOKMARK,Used by FW. Keeps the Current HV cycle sequence"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "GEOMETRY,Regular flash geometry"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PAGE_SIZE_LOG2,Number of Bytes per page (log 2):"
|
|
hexmask.long.byte 0x0 24.--27. 1. "WORD_SIZE_LOG2,Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access:"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "BANK_COUNT,Number of banks (minus 1):"
|
|
hexmask.long.word 0x0 0.--15. 1. "ROW_COUNT,Number of rows (minus 1):"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "GEOMETRY_SUPERVISORY,Supervisory flash geometry"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PAGE_SIZE_LOG2,Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2."
|
|
hexmask.long.byte 0x0 24.--27. 1. "WORD_SIZE_LOG2,Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "BANK_COUNT,Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT."
|
|
hexmask.long.word 0x0 0.--15. 1. "ROW_COUNT,Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT"
|
|
endif
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "ANA_CTL0,Analog control 0"
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x0 30.--31. "SCALE_PRG_PEOFF,PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE OFF transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x0 28.--29. "SCALE_PRG_PEON,PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE On transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SCALE_SEQ30,PROG&PRE_PROG& ERASE: Scale for R_GRANT_DELAY on seq3-seq0 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "SCALE_PRG_SEQ23,PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq2-seq3 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "SCALE_PRG_SEQ12,PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq1-seq2 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SCALE_PRG_SEQ01,PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq0-seq1 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PDAC_MIN,PDAC staircase min value"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "NDAC_MIN,NDAC staircase min value"
|
|
newline
|
|
bitfld.long 0x0 11. "FLIP_AMUXBUS_AB,Flips amuxbusa and amuxbusb" "0: amuxbusa,1: amuxbusb"
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
bitfld.long 0x0 27. "FLIP_AMUXBUS_AB,Flips amuxbusa and amuxbusb" "0: amuxbusa,1: amuxbusb"
|
|
newline
|
|
bitfld.long 0x0 24. "VCC_SEL,Vcc select:" "0: 1,1: 0"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 8.--10. "CSLDAC,Trimming of common source line DAC." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
hexmask.long.byte 0x0 0.--7. 1. "MDAC,Trimming of the output margin Voltage as a function of Vpos and Vneg."
|
|
endif
|
|
line.long 0x4 "ANA_CTL1,Analog control 1"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
bitfld.long 0x4 30. "RST_SFT_HVPL,'1': Page Latches Soft Reset" "?,1: Page Latches Soft Reset"
|
|
newline
|
|
bitfld.long 0x4 29. "R_GRANT_CTL,r_grant control:" "0: r_grant normal functionality,1: forces r_grant LO synchronized on clk_r"
|
|
newline
|
|
bitfld.long 0x4 28. "VPROT_OVERRIDE,'0': vprot = BG.vprot." "0: vprot = BG,1: vprot = vcc"
|
|
newline
|
|
hexmask.long.byte 0x4 24.--27. 1. "NDAC,Trimming of negative pump output Voltage:"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "PDAC,Trimming of positive pump output Voltage:"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "MDAC,Trimming of the output margin Voltage as a function of Vpos and Vneg."
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. "NPDAC_ZERO_TIME,Ndac/Pdac LO duration: (1uS .. 255uS) * 8"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "NPDAC_STEP_TIME,Ndac/Pdac step duration: (1uS .. 255uS) * 8"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "PDAC_STEP,Pdac step increment"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "PDAC_MAX,Pdac Max Value.Trimming of positive pump output Voltage:"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "NDAC_STEP,Ndac step increment"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "NDAC_MAX,Ndac Max Value.Trimming of negative pump output Voltage."
|
|
endif
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "WAIT_CTL,Wiat State control"
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x0 29. "PL_SOFT_SET_EN,Page latch soft set enable 0 = disabled 1 = enabled (at end of seq_2) taken care in API" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 28. "MBA,0: Normal" "0: Normal,1: Test mode to enable Master Bulk Access which.."
|
|
newline
|
|
bitfld.long 0x0 27. "DRMM,0: Normal" "0: Normal,1: Test mode to enable Margin mode for 2 rows at a.."
|
|
newline
|
|
bitfld.long 0x0 26. "LV_SPARE_1,Spare register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "FM_RWW_MODE,00: Full CBUS MODE" "0: Full CBUS MODE,1: RWW,?,?"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 16.--18. "WAIT_FM_HV_WR,Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "WAIT_FM_HV_RD,Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "WAIT_FM_MEM_RD,Number of C interface wait cycles (on 'clk_c') for a read from the memory"
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "TIMER_CLK_CTL,Timer prescaler (clk_t to timer clock frequency divider)"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RGRANT_DELAY_PRG_SEQ01,PROG&PRE_PROG: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RGRANT_DELAY_PRG_PEOFF,PROG&PRE_PROG: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RGRANT_DELAY_PRG_PEON,PROG&PRE_PROG: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TIMER_CLOCK_FREQ,Clk_t frequency divider to provide the 1MHz reference clock for the Regif Timer."
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "TIMER_CTL,Timer control"
|
|
bitfld.long 0x0 31. "TIMER_EN,Timer enable:" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 30. "ACLK_EN,ACLK enable (generates a single cycle pulse for the FM):" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 29. "PUMP_EN,Pump enable:" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 26. "PRE_PROG_CSL,0: CSL lines driven by CSL_DAC" "0: CSL lines driven by CSL_DAC,1: CSL lines driven by VNEG_G"
|
|
newline
|
|
bitfld.long 0x0 25. "PRE_PROG,1 during pre-program operation" "0,1"
|
|
bitfld.long 0x0 24. "AUTO_SEQUENCE,1': Starts1 the HV automatic sequencing" "?,1: Starts1 the HV automatic sequencing"
|
|
newline
|
|
bitfld.long 0x0 15. "SCALE,Timer tick scale:" "0: 1 microsecond,1: 100 microseconds"
|
|
hexmask.long.word 0x0 0.--14. 1. "PERIOD,Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples."
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "ACLK_CTL,MPCON clock"
|
|
bitfld.long 0x0 0. "ACLK_GEN,A write to this register generates the clock pulse for HV control registers (mpcon outputs)" "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 0. "TIMER_EXPIRED,Set to '1' when event is detected. Write INTR field with '1' to clear bit. Write INTR_SET field with '1' to set bit." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x0 0. "TIMER_EXPIRED,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x0 0. "TIMER_EXPIRED,Mask for corresponding field in INTR register." "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "TIMER_EXPIRED,Logical and of corresponding request and mask fields." "0,1"
|
|
endif
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "CAL_CTL0,Cal control BG LO trim bits"
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x0 19. "IPREF_TRIMA_LO_HV,Adds 100-150nA boost on IPREF_LO" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "ICREF_TC_TRIM_LO_HV,LO Bandgap Current Temperature Compensation trim control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
hexmask.long.byte 0x0 16.--19. 1. "IPREF_TRIM_LO_HV,LO Bandgap IPTAT trim control."
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 13.--15. "VBG_TC_TRIM_LO_HV,LO Bandgap Voltage Temperature Compensation trim control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "VBG_TRIM_LO_HV,LO Bandgap Voltage trim control."
|
|
newline
|
|
bitfld.long 0x0 5.--7. "CDAC_LO_HV,LO Temperature compensated trim DAC. To control Vcstat slope for Vpos." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "VCT_TRIM_LO_HV,LO Bandgap Voltage Temperature Compensation trim control."
|
|
line.long 0x4 "CAL_CTL1,Cal control BG HI trim bits"
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x4 19. "IPREF_TRIMA_HI_HV,Adds 100-150nA boost on IPREF_HI" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "ICREF_TC_TRIM_HI_HV,HI Bandgap Current Temperature Compensation trim control." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
hexmask.long.byte 0x4 16.--19. 1. "IPREF_TRIM_HI_HV,HI Bandgap IPTAT trim control."
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 13.--15. "VBG_TC_TRIM_HI_HV,HI Bandgap Voltage Temperature Compensation trim control." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "VBG_TRIM_HI_HV,HI Bandgap Voltage trim control."
|
|
newline
|
|
bitfld.long 0x4 5.--7. "CDAC_HI_HV,HI Temperature compensated trim DAC. To control Vcstat slope for Vpos." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "VCT_TRIM_HI_HV,HI Bandgap Voltage Temperature Compensation trim control."
|
|
line.long 0x8 "CAL_CTL2,Cal control BG LO&HI ipref trim. ref sel. fm_active. turbo_ext"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
bitfld.long 0x8 19. "TURBO_EXT_HV,0: turbo signal generated internally" "0: turbo signal generated internally,1: turbo cleared by clk_pump_ext HI"
|
|
newline
|
|
bitfld.long 0x8 18. "FM_ACTIVE_HV,0: No Action" "0: No Action,1: Forces FM SYS in active mode"
|
|
newline
|
|
bitfld.long 0x8 17. "IREF_SEL_HV,Current reference:" "0: internal current reference,1: external current reference"
|
|
newline
|
|
bitfld.long 0x8 16. "VREF_SEL_HV,Voltage reference:" "0: internal bandgap reference,1: external voltage reference"
|
|
newline
|
|
bitfld.long 0x8 13.--15. "ICREF_TC_TRIM_HI_HV,HI Bandgap Current Temperature Compensation trim control." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--12. 1. "ICREF_TRIM_HI_HV,HI Bandgap Current trim control."
|
|
newline
|
|
bitfld.long 0x8 5.--7. "ICREF_TC_TRIM_LO_HV,LO Bandgap Current Temperature Compensation trim control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
hexmask.long.byte 0x8 15.--19. 1. "IPREF_TRIM_HI_HV,HI Bandgap IPTAT trim control."
|
|
newline
|
|
hexmask.long.byte 0x8 10.--14. 1. "IPREF_TRIM_LO_HV,LO Bandgap IPTAT trim control."
|
|
newline
|
|
hexmask.long.byte 0x8 5.--9. 1. "ICREF_TRIM_HI_HV,HI Bandgap Current trim control."
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x8 0.--4. 1. "ICREF_TRIM_LO_HV,LO Bandgap Current trim control."
|
|
line.long 0xC "CAL_CTL3,Cal control osc trim bits. idac. sdac. itim. bdac."
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
bitfld.long 0xC 19. "BGHI_EN_HV,HI Bandgap Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 18. "BGLO_EN_HV,LO Bandgap Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 16.--17. "TURBO_PULSEW_HV,Turbo pulse width trim" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 15. "VDDHI_HV,0': vdd<2.3V" "0: vdd<2,1: vdd>=2"
|
|
newline
|
|
hexmask.long.byte 0xC 11.--14. 1. "ITIM_HV,Trimming of timing current"
|
|
newline
|
|
bitfld.long 0xC 9.--10. "SDAC_HV,N/A" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0xC 5.--8. 1. "IDAC_HV,N/A"
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0xC 19. "LP_ULP_SW_HV,LP<-->ULP switch for trim signals:" "0: LP,1: ULP"
|
|
newline
|
|
bitfld.long 0xC 18. "R_GRANT_EN_HV,0: r_grant handshake disabled r_grant always 1." "0: r_grant handshake disabled,1: r_grand handshake enabled"
|
|
newline
|
|
bitfld.long 0xC 17. "CL_ISO_DIS_HV,0: The internal logic controls the CL isolation" "0: The internal logic controls the CL isolation,1: Forces CL bypass"
|
|
newline
|
|
bitfld.long 0xC 16. "BGHI_EN_HV,0: Normal (Automatic change over from HI to LO)" "0: Normal,1: Force enable HI Bandgap"
|
|
newline
|
|
bitfld.long 0xC 15. "BGLO_EN_HV,0: Normal (Automatic change over from HI to LO)" "0: Normal,1: Force enable LO Bandgap"
|
|
newline
|
|
bitfld.long 0xC 13.--14. "TURBO_PULSEW_HV,Turbo pulse width trim (Typical)" "0: 40 us,1: 20 us,?,?"
|
|
newline
|
|
bitfld.long 0xC 12. "VDDHI_HV,0: vdd < 2.3V" "0: vdd < 2,1: vdd >= 2"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "FDIV_TRIM_HV,FDIV_TRIM_HV[1:0]: Assuming oscillator frequency of 8MHz in standby." "0: F = 1MHz,1: F = 0,?,?"
|
|
newline
|
|
bitfld.long 0xC 9. "REG_ACT_HV,0: VBST regulator will operate in active/standby mode based on control signal." "0: VBST regulator will operate in active/standby..,1: Forces the VBST regulator in active mode all the.."
|
|
newline
|
|
bitfld.long 0xC 8. "IREF_SEL_HV,Current reference:" "0: internal current reference,1: external current reference"
|
|
newline
|
|
bitfld.long 0xC 7. "VREF_SEL_HV,Voltage reference:" "0: internal bandgap reference,1: external voltage reference"
|
|
newline
|
|
bitfld.long 0xC 6. "IPREF_TC_HV,0: Increases the IPREF Tempco by subtracting ICREF from IPREF - IPREF internal will be 0.5uA" "0: Increases the IPREF Tempco by subtracting ICREF..,1: Reduces the IPREF Tempco without subtracting.."
|
|
newline
|
|
bitfld.long 0xC 5. "VPROT_ACT_HV,Forces VPROT in active mode all the time" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0xC 4. "OSC_RANGE_TRIM_HV,0: Oscillator High Frequency Range" "0: Oscillator High Frequency Range,1: Oscillator Low Frequency range"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "OSC_TRIM_HV,Flash macro pump clock trim control."
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "CAL_CTL4,Cal Control Vlim. SA. fdiv. reg_act"
|
|
bitfld.long 0x0 19. "UGB_EN_HV,UGB enable in TM control" "0,1"
|
|
bitfld.long 0x0 18. "AUTO_HVPULSE_HV,0: HV Pulse controlled by FW" "0: HV Pulse controlled by FW,1: HV Pulse controlled by Hardware"
|
|
newline
|
|
bitfld.long 0x0 17. "VBST_S_DIS_HV,0: VBST_S voltage for each sector to allow VBST level to be dropped to VCC during Erase in the selected sector reducing coupling to GBL." "0: VBST_S voltage for each sector to allow VBST..,1: VBST_S voltage for each sector stays at VBST.."
|
|
bitfld.long 0x0 16. "READY_RESTART_N_HV,Toggle: 1-->0 ready goes low ready will remain low as long as the bit is low. Toggle the bit back to 1 to activate the ready logic. To be used by API only." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "SPARE451_ULP_HV,N/A" "0,1"
|
|
bitfld.long 0x0 13.--14. "FM_READY_DEL_ULP_HV,00: Default : delay 1ns" "0: Default : delay 1ns,1: Delayed by 1,?,?"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "ITIM_ULP_HV,Trimming of timing current"
|
|
bitfld.long 0x0 6.--7. "SDAC_ULP_HV,Sets the sense current reference temp slope. Refer to trim tables for details." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 2.--5. 1. "IDAC_ULP_HV,Sets the sense current reference offset value. Refer to trim tables for details."
|
|
bitfld.long 0x0 0.--1. "VLIM_TRIM_ULP_HV,VLIM_TRIM[1:0]:" "0: V2 = 650mV,1: V2 = 600mV,?,?"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "CAL_CTL5,Cal control"
|
|
bitfld.long 0x0 18.--19. "AMUX_SEL_HV,Amux Select in AMUX_UGB" "0: Bypass UGB for both amuxbusa and amuxbusb,1: Bypass UGB for amuxbusb while passing amuxbusa..,?,?"
|
|
bitfld.long 0x0 16.--17. "SPARE52_HV,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 15. "SPARE451_LP_HV,N/A" "0,1"
|
|
bitfld.long 0x0 13.--14. "FM_READY_DEL_LP_HV,00: Delayed by 1us" "0: Delayed by 1us,1: Delayed by 1,?,?"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "ITIM_LP_HV,Trimming of timing current"
|
|
bitfld.long 0x0 6.--7. "SDAC_LP_HV,Sets the sense current reference temp slope. Refer to trim tables for details." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 2.--5. 1. "IDAC_LP_HV,Sets the sense current reference offset value. Refer to trim tables for details."
|
|
bitfld.long 0x0 0.--1. "VLIM_TRIM_LP_HV,VLIM_TRIM[1:0]:" "0: V2 = 650mV,1: V2 = 600mV,?,?"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "CAL_CTL6,SA trim LP/ULP"
|
|
bitfld.long 0x0 19. "SA_CTL_TRIM_T8_LP_HV,saen3 pulse width trim (Current trim)" "0,1"
|
|
bitfld.long 0x0 17.--18. "SA_CTL_TRIM_T6_LP_HV,SA_CTL_TRIM_T6_LP_HV<1>= eni (enable current trim)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 14.--16. "SA_CTL_TRIM_T5_LP_HV,SA_CTL_TRIM_T5_LP_HV<2>= evi (integration current trim)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11.--13. "SA_CTL_TRIM_T4_LP_HV,SA_CTL_TRIM_T4_LP_HV<2>= eqi (eq current trim)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 10. "SA_CTL_TRIM_T1_LP_HV,clk_trk delay" "0,1"
|
|
bitfld.long 0x0 9. "SA_CTL_TRIM_T8_ULP_HV,saen3 pulse width trim (Current trim)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7.--8. "SA_CTL_TRIM_T6_ULP_HV,SA_CTL_TRIM_T6_ULP_HV<1>= eni (enable current trim)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--6. "SA_CTL_TRIM_T5_ULP_HV,SA_CTL_TRIM_T5_ULP_HV<2>= evi (integration current trim)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 1.--3. "SA_CTL_TRIM_T4_ULP_HV,SA_CTL_TRIM_T4_ULP_HV<2>= eqi (eq current trim)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "SA_CTL_TRIM_T1_ULP_HV,clk_trk delay" "0,1"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "CAL_CTL7,Cal control"
|
|
hexmask.long.byte 0x0 15.--19. 1. "SPARE7_LP_HV,N/A"
|
|
hexmask.long.byte 0x0 10.--14. 1. "SPARE7_ULP_HV,N/A"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "SPARE7_HV,N/A" "0,1,2,3"
|
|
bitfld.long 0x0 7. "DISABLE_LOAD_ONCE_HV,0: Load common HV params during API HV operations depends on the HV_PARAMS_LOADED bit in RGRANT_DELAY_PRG register." "0: Load common HV params during API HV operations..,1: All HV params are loaded during every API HV.."
|
|
newline
|
|
bitfld.long 0x0 6. "ERSX8_EN_ALL_HV,0': Staggered turn on/off of GWL" "0: Staggered turn on/off of GWL,1: GWL are turned on/off at the same time"
|
|
bitfld.long 0x0 5. "FM_READY_DIS_HV,0': fm ready is enabled" "0: fm ready is enabled,1: fm ready is disabled"
|
|
newline
|
|
bitfld.long 0x0 4. "NPDAC_HWCTL_DIS_HV,0': ndac pdac staircase hardware controlled" "0: ndac,1: ndac"
|
|
bitfld.long 0x0 3. "TURBO_EXT_HV,0: Normal operation" "0: Normal operation,1: Uses external turbo pulse"
|
|
newline
|
|
bitfld.long 0x0 2. "FM_ACTIVE_HV,0: Normal operation" "0: Normal operation,1: Forces FM SYS in active mode"
|
|
bitfld.long 0x0 0.--1. "ERSX8_CLK_SEL_HV,Clock frequency into the ersx8 shift register block" "0: Oscillator clock,1: Oscillator clock / 2,?,?"
|
|
endif
|
|
group.long 0x80++0x13
|
|
line.long 0x0 "RED_CTL01,Redundancy Control normal sectors 0.1"
|
|
bitfld.long 0x0 24. "RED_EN_1,'1': Redundancy Enable for Sector 1" "?,1: Redundancy Enable for Sector 1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RED_ADDR_1,Bad Row Pair Address for Sector 1"
|
|
newline
|
|
bitfld.long 0x0 8. "RED_EN_0,'1': Redundancy Enable for Sector 0" "?,1: Redundancy Enable for Sector 0"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RED_ADDR_0,Bad Row Pair Address for Sector 0"
|
|
line.long 0x4 "RED_CTL23,Redundancy Controll normal sectors 2.3"
|
|
bitfld.long 0x4 24. "RED_EN_3,1': Redundancy Enable for Sector 3" "?,1: Redundancy Enable for Sector 3"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "RED_ADDR_3,Bad Row Pair Address for Sector 3"
|
|
newline
|
|
bitfld.long 0x4 8. "RED_EN_2,1': Redundancy Enable for Sector 2" "?,1: Redundancy Enable for Sector 2"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RED_ADDR_2,Bad Row Pair Address for Sector 2"
|
|
line.long 0x8 "RED_CTL45,Redundancy Controll normal sectors 4.5"
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x8 24. "RED_EN_5,1: Redundancy Enable for Sector 5" "?,1: Redundancy Enable for Sector 5"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--23. 1. "RED_ADDR_5,Bad Row Pair Address for Sector 5"
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
hexmask.long.byte 0x8 16.--23. 1. "DNU_45_23_16,Not Used"
|
|
newline
|
|
bitfld.long 0x8 8. "DNU_45_8,Not Used" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "VLIM_TRIM_HV_0,'2b00' V2 = 650mV see vlim_trim_hv<1> value as well" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "DNU_45_6,Not Used" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "FDIV_TRIM_HV_1,'2b00' F = 1MHz see fdiv_trim_hv<0> value as well" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "DNU_45_5,Not Used" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FDIV_TRIM_HV_0,'2b00' F = 1MHz see fdiv_trim_hv<1> value as well" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "DNU_45_3,Not Used" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "REG_ACT_HV,Forces the VBST regulator in active mode all the time" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "DNU_45_1,Not Used" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x8 8. "RED_EN_4,1: Redundancy Enable for Sector 4" "?,1: Redundancy Enable for Sector 4"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "RED_ADDR_4,Bad Row Pair Address for Sector 4"
|
|
endif
|
|
line.long 0xC "RED_CTL67,Redundancy Controll normal sectors 6.7"
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0xC 24. "RED_EN_7,1: Redundancy Enable for Sector 7" "?,1: Redundancy Enable for Sector 7"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--23. 1. "RED_ADDR_7,Bad Row Pair Address for Sector 7"
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
hexmask.long.byte 0xC 16.--23. 1. "DNU_67_23_16,Not Used"
|
|
newline
|
|
bitfld.long 0xC 8. "IPREF_TRIMA_LO_HV,Adds 200-300nA boost on IPREF_LO" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "DNU_67_7,Not Used" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "IPREF_TRIMA_HI_HV,Adds 200-300nA boost on IPREF_HI" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "DNU_67_5,Not Used" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "IPREF_TC_HV,Reduces the IPREF Tempco by not subtracting ICREF form IPREF - IPREF will be 1uA" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "DNU_67_3,Not Used" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "VPROT_ACT_HV,Forces VPROT in active mode all the time" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "DNU_67_1,Not Used" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "VLIM_TRIM_HV_1,'2b00' V2 = 650mV see vlim_trim_hv<0> value as well" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0xC 8. "RED_EN_6,1: Redundancy Enable for Sector 6" "?,1: Redundancy Enable for Sector 6"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "RED_ADDR_6,Bad Row Pair Address for Sector 6"
|
|
endif
|
|
line.long 0x10 "RED_CTL_SM01,Redundancy Controll special sectors 0.1"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
bitfld.long 0x10 31. "R_GRANT_EN,'0': r_grant handshake disabled r_grant always 1." "0: r_grant handshake disabled,1: r_grand handshake enabled"
|
|
newline
|
|
bitfld.long 0x10 30. "TRKD,Sense Amp Control tracking delay" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x10 24. "RED_EN_SM1,Redundancy Enable for Special Sector 1" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--23. 1. "RED_ADDR_SM1,Bad Row Pair Address for Special Sector 1"
|
|
newline
|
|
bitfld.long 0x10 8. "RED_EN_SM0,Redundancy Enable for Special Sector 0" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "RED_ADDR_SM0,Bad Row Pair Address for Special Sector 0"
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "RGRANT_DELAY_PRG,R-grant delay for program"
|
|
bitfld.long 0x0 31. "HV_PARAMS_LOADED,0: HV Pulse common params not loaded" "0: HV Pulse common params not loaded,1: HV Pulse common params loaded: r-grant delays"
|
|
hexmask.long.byte 0x0 24.--27. 1. "RGRANT_DELAY_CLK,Frequency divider from clk_t to create the 8MHz reference clock for R_grant delay"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RGRANT_DELAY_SEQ30,PROG&PRE_PROG & ERASE: R-grant blocking delay on seq3-seq0 transition. Scale = ANA_CTL0.SCALE_SEQ30"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RGRANT_DELAY_PRG_SEQ23,PROG&PRE_PROG: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RGRANT_DELAY_PRG_SEQ12,PROG&PRE_PROG: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12"
|
|
group.long 0xA0++0xF
|
|
line.long 0x0 "PW_SEQ12,HV Pulse Delay for seq 1&2 pre"
|
|
hexmask.long.word 0x0 16.--31. 1. "PW_SEQ2_PRE,Seq2 pre delay"
|
|
hexmask.long.word 0x0 0.--15. 1. "PW_SEQ1,Seq1 delay"
|
|
line.long 0x4 "PW_SEQ23,HV Pulse Delay for seq2 post & seq3"
|
|
hexmask.long.word 0x4 16.--31. 1. "PW_SEQ3,Seq3 delay"
|
|
hexmask.long.word 0x4 0.--15. 1. "PW_SEQ2_POST,Seq2 post delay"
|
|
line.long 0x8 "RGRANT_SCALE_ERS,R-grant delay scale for erase"
|
|
hexmask.long.byte 0x8 24.--31. 1. "RGRANT_DELAY_ERS_PEOFF,ERASE: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF"
|
|
hexmask.long.byte 0x8 16.--23. 1. "RGRANT_DELAY_ERS_PEON,ERASE: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "SCALE_ERS_PEOFF,ERASE: Scale for R_GRANT_DELAY on PE OFF transition:" "0: 0,1: 1uS,?,?"
|
|
bitfld.long 0x8 6.--7. "SCALE_ERS_PEON,ERASE: Scale for R_GRANT_DELAY on PE On transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "SCALE_ERS_SEQ23,ERASE: Scale for R_GRANT_DELAY on seq2-seq3 transition:" "0: 0,1: 1uS,?,?"
|
|
bitfld.long 0x8 2.--3. "SCALE_ERS_SEQ12,ERASE: Scale for R_GRANT_DELAY on seq1-seq2 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "SCALE_ERS_SEQ01,ERASE: Scale for R_GRANT_DELAY on seq0-seq1 transition:" "0: 0,1: 1uS,?,?"
|
|
line.long 0xC "RGRANT_DELAY_ERS,R-grant delay for erase"
|
|
hexmask.long.byte 0xC 16.--23. 1. "RGRANT_DELAY_ERS_SEQ23,ERASE: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23"
|
|
hexmask.long.byte 0xC 8.--15. 1. "RGRANT_DELAY_ERS_SEQ12,ERASE: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "RGRANT_DELAY_ERS_SEQ01,ERASE: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01"
|
|
group.long 0x7FC++0x3
|
|
line.long 0x0 "FM_PL_WRDATA_ALL,Flash macro write page latches all"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Write all high Voltage page latches with the same 32-bit data in a single write cycle"
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x800)++0x3
|
|
line.long 0x0 "FM_PL_DATA[$1],Flash macro Page Latches data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Four page latch Bytes"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0xC00)++0x3
|
|
line.long 0x0 "FM_MEM_DATA[$1],Flash macro memory sense amplifier and column decoder data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL:"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0xC00)++0x3
|
|
line.long 0x0 "FM_MEM_DATA[$1],Flash macro memory sense amplifier and column decoder data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL:"
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x40320000
|
|
elif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
base ad:0x40310000
|
|
endif
|
|
tree "GPIO (GPIO Port Control/Configuration)"
|
|
rgroup.long 0x4000++0x13
|
|
line.long 0x0 "INTR_CAUSE0,Interrupt port cause register 0"
|
|
hexmask.long 0x0 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line.."
|
|
line.long 0x4 "INTR_CAUSE1,Interrupt port cause register 1"
|
|
hexmask.long 0x4 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line.."
|
|
line.long 0x8 "INTR_CAUSE2,Interrupt port cause register 2"
|
|
hexmask.long 0x8 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line.."
|
|
line.long 0xC "INTR_CAUSE3,Interrupt port cause register 3"
|
|
hexmask.long 0xC 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line.."
|
|
line.long 0x10 "VDD_ACTIVE,Extern power supply detection register"
|
|
bitfld.long 0x10 31. "VDDD_ACTIVE,This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in.." "0,1"
|
|
bitfld.long 0x10 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x10 0.--15. 1. "VDDIO_ACTIVE,Indicates presence or absence of VDDIO supplies (i.e. other than VDDD VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate robust brown-out detection is.."
|
|
group.long 0x4014++0x7
|
|
line.long 0x0 "VDD_INTR,Supply detection interrupt register"
|
|
bitfld.long 0x0 31. "VDDD_ACTIVE,The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'." "0,1"
|
|
bitfld.long 0x0 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "VDDIO_ACTIVE,Supply state change detected."
|
|
line.long 0x4 "VDD_INTR_MASK,Supply detection interrupt mask register"
|
|
bitfld.long 0x4 31. "VDDD_ACTIVE,Same as VDDIO_ACTIVE for the digital supply VDDD." "0,1"
|
|
bitfld.long 0x4 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "VDDIO_ACTIVE,Masks supply interrupt on VDDIO."
|
|
rgroup.long 0x401C++0x3
|
|
line.long 0x0 "VDD_INTR_MASKED,Supply detection interrupt masked register"
|
|
bitfld.long 0x0 31. "VDDD_ACTIVE,Same as VDDIO_ACTIVE for the digital supply VDDD." "0,1"
|
|
bitfld.long 0x0 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "VDDIO_ACTIVE,Supply transition detected AND masked"
|
|
group.long 0x4020++0x3
|
|
line.long 0x0 "VDD_INTR_SET,Supply detection interrupt set register"
|
|
bitfld.long 0x0 31. "VDDD_ACTIVE,Same as VDDIO_ACTIVE for the digital supply VDDD." "0,1"
|
|
bitfld.long 0x0 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "VDDIO_ACTIVE,Sets supply interrupt."
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 15. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE)(list ad:0x40320000 ad:0x40320080 ad:0x40320100 ad:0x40320180 ad:0x40320200 ad:0x40320280 ad:0x40320300 ad:0x40320380 ad:0x40320400 ad:0x40320480 ad:0x40320500 ad:0x40320580 ad:0x40320600 ad:0x40320680 ad:0x40320700)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "OUT,Port output data register"
|
|
bitfld.long 0x0 7. "OUT7,IO output data for pin 7" "0,1"
|
|
bitfld.long 0x0 6. "OUT6,IO output data for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUT5,IO output data for pin 5" "0,1"
|
|
bitfld.long 0x0 4. "OUT4,IO output data for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OUT3,IO output data for pin 3" "0,1"
|
|
bitfld.long 0x0 2. "OUT2,IO output data for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OUT1,IO output data for pin 1" "0,1"
|
|
bitfld.long 0x0 0. "OUT0,IO output data for pin 0" "0: Output state set to '0',1: Output state set to '1'"
|
|
line.long 0x4 "OUT_CLR,Port output data clear register"
|
|
bitfld.long 0x4 7. "OUT7,IO clear output for pin 7" "0,1"
|
|
bitfld.long 0x4 6. "OUT6,IO clear output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OUT5,IO clear output for pin 5" "0,1"
|
|
bitfld.long 0x4 4. "OUT4,IO clear output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OUT3,IO clear output for pin 3" "0,1"
|
|
bitfld.long 0x4 2. "OUT2,IO clear output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OUT1,IO clear output for pin 1" "0,1"
|
|
bitfld.long 0x4 0. "OUT0,IO clear output for pin 0:" "0: Output state not affected,1: Output state set to '0'"
|
|
line.long 0x8 "OUT_SET,Port output data set register"
|
|
bitfld.long 0x8 7. "OUT7,IO set output for pin 7" "0,1"
|
|
bitfld.long 0x8 6. "OUT6,IO set output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OUT5,IO set output for pin 5" "0,1"
|
|
bitfld.long 0x8 4. "OUT4,IO set output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "OUT3,IO set output for pin 3" "0,1"
|
|
bitfld.long 0x8 2. "OUT2,IO set output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "OUT1,IO set output for pin 1" "0,1"
|
|
bitfld.long 0x8 0. "OUT0,IO set output for pin 0:" "0: Output state not affected,1: Output state set to '1'"
|
|
line.long 0xC "OUT_INV,Port output data invert register"
|
|
bitfld.long 0xC 7. "OUT7,IO invert output for pin 7" "0,1"
|
|
bitfld.long 0xC 6. "OUT6,IO invert output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "OUT5,IO invert output for pin 5" "0,1"
|
|
bitfld.long 0xC 4. "OUT4,IO invert output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "OUT3,IO invert output for pin 3" "0,1"
|
|
bitfld.long 0xC 2. "OUT2,IO invert output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "OUT1,IO invert output for pin 1" "0,1"
|
|
bitfld.long 0xC 0. "OUT0,IO invert output for pin 0:" "0: '1',1: '0'"
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "IN,Port input state register"
|
|
bitfld.long 0x0 8. "FLT_IN,Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register." "0,1"
|
|
bitfld.long 0x0 7. "IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "IN6,IO pin state for pin 6" "0,1"
|
|
bitfld.long 0x0 5. "IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IN4,IO pin state for pin 4" "0,1"
|
|
bitfld.long 0x0 3. "IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IN2,IO pin state for pin 2" "0,1"
|
|
bitfld.long 0x0 1. "IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN0,IO pin state for pin 0" "0: Low logic level present on pin,1: High logic level present on pin"
|
|
group.long ($2+0x14)++0x7
|
|
line.long 0x0 "INTR,Port interrupt status register"
|
|
rbitfld.long 0x0 24. "FLT_IN_IN,Filtered pin state for pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
rbitfld.long 0x0 23. "IN_IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 22. "IN_IN6,IO pin state for pin 6" "0,1"
|
|
rbitfld.long 0x0 21. "IN_IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 20. "IN_IN4,IO pin state for pin 4" "0,1"
|
|
rbitfld.long 0x0 19. "IN_IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 18. "IN_IN2,IO pin state for pin 2" "0,1"
|
|
rbitfld.long 0x0 17. "IN_IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "IN_IN0,IO pin state for pin 0" "0,1"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "EDGE7,Edge detect for IO pin 7" "0,1"
|
|
bitfld.long 0x0 6. "EDGE6,Edge detect for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EDGE5,Edge detect for IO pin 5" "0,1"
|
|
bitfld.long 0x0 4. "EDGE4,Edge detect for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EDGE3,Edge detect for IO pin 3" "0,1"
|
|
bitfld.long 0x0 2. "EDGE2,Edge detect for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EDGE1,Edge detect for IO pin 1" "0,1"
|
|
bitfld.long 0x0 0. "EDGE0,Edge detect for IO pin 0" "0: No edge was detected on pin,1: An edge was detected on pin"
|
|
line.long 0x4 "INTR_MASK,Port interrupt mask register"
|
|
bitfld.long 0x4 8. "FLT_EDGE,Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x4 7. "EDGE7,Masks edge interrupt on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "EDGE6,Masks edge interrupt on IO pin 6" "0,1"
|
|
bitfld.long 0x4 5. "EDGE5,Masks edge interrupt on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EDGE4,Masks edge interrupt on IO pin 4" "0,1"
|
|
bitfld.long 0x4 3. "EDGE3,Masks edge interrupt on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EDGE2,Masks edge interrupt on IO pin 2" "0,1"
|
|
bitfld.long 0x4 1. "EDGE1,Masks edge interrupt on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EDGE0,Masks edge interrupt on IO pin 0" "0: Pin interrupt forwarding disabled,1: Pin interrupt forwarding enabled"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Port interrupt masked status register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Edge detected and masked on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Edge detected and masked on IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Edge detected and masked on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Edge detected and masked on IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Edge detected and masked on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Edge detected and masked on IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Edge detected and masked on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Edge detected AND masked on IO pin 0" "0: Interrupt was not forwarded to CPU,1: Interrupt occurred and was forwarded to CPU"
|
|
group.long ($2+0x20)++0x17
|
|
line.long 0x0 "INTR_SET,Port interrupt set register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Sets edge detect interrupt for IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Sets edge detect interrupt for IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Sets edge detect interrupt for IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Sets edge detect interrupt for IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Sets edge detect interrupt for IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Sets edge detect interrupt for IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Sets edge detect interrupt for IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Sets edge detect interrupt for IO pin 0" "0: Interrupt state not affected,1: Interrupt set"
|
|
line.long 0x4 "INTR_CFG,Port interrupt configuration register"
|
|
bitfld.long 0x4 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--17. "FLT_EDGE_SEL,Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "EDGE7_SEL,Sets which edge will trigger an IRQ for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "EDGE6_SEL,Sets which edge will trigger an IRQ for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "EDGE5_SEL,Sets which edge will trigger an IRQ for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "EDGE4_SEL,Sets which edge will trigger an IRQ for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "EDGE3_SEL,Sets which edge will trigger an IRQ for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "EDGE2_SEL,Sets which edge will trigger an IRQ for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 2.--3. "EDGE1_SEL,Sets which edge will trigger an IRQ for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pin 0" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
line.long 0x8 "CFG,Port configuration register"
|
|
bitfld.long 0x8 31. "IN_EN7,Enables the input buffer for IO pin 7" "0,1"
|
|
bitfld.long 0x8 28.--30. "DRIVE_MODE7,The GPIO drive mode for IO pin 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 27. "IN_EN6,Enables the input buffer for IO pin 6" "0,1"
|
|
bitfld.long 0x8 24.--26. "DRIVE_MODE6,The GPIO drive mode for IO pin 6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 23. "IN_EN5,Enables the input buffer for IO pin 5" "0,1"
|
|
bitfld.long 0x8 20.--22. "DRIVE_MODE5,The GPIO drive mode for IO pin 5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 19. "IN_EN4,Enables the input buffer for IO pin 4" "0,1"
|
|
bitfld.long 0x8 16.--18. "DRIVE_MODE4,The GPIO drive mode for IO pin4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 15. "IN_EN3,Enables the input buffer for IO pin 3" "0,1"
|
|
bitfld.long 0x8 12.--14. "DRIVE_MODE3,The GPIO drive mode for IO pin 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 11. "IN_EN2,Enables the input buffer for IO pin 2" "0,1"
|
|
bitfld.long 0x8 8.--10. "DRIVE_MODE2,The GPIO drive mode for IO pin 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 7. "IN_EN1,Enables the input buffer for IO pin 1" "0,1"
|
|
bitfld.long 0x8 4.--6. "DRIVE_MODE1,The GPIO drive mode for IO pin 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 3. "IN_EN0,Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue." "0: Input buffer disabled,1: Input buffer enabled"
|
|
bitfld.long 0x8 0.--2. "DRIVE_MODE0,The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
line.long 0xC "CFG_IN,Port input buffer configuration register"
|
|
bitfld.long 0xC 7. "VTRIP_SEL7_0,N/A" "0,1"
|
|
bitfld.long 0xC 6. "VTRIP_SEL6_0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "VTRIP_SEL5_0,N/A" "0,1"
|
|
bitfld.long 0xC 4. "VTRIP_SEL4_0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "VTRIP_SEL3_0,N/A" "0,1"
|
|
bitfld.long 0xC 2. "VTRIP_SEL2_0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "VTRIP_SEL1_0,N/A" "0,1"
|
|
bitfld.long 0xC 0. "VTRIP_SEL0_0,N/A" "0: S40S: Input buffer compatible with CMOS and I2C..,1: S40S: Input buffer compatible with TTL and.."
|
|
line.long 0x10 "CFG_OUT,Port output buffer configuration register"
|
|
bitfld.long 0x10 30.--31. "DRIVE_SEL7,Sets the GPIO drive strength for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0x10 28.--29. "DRIVE_SEL6,Sets the GPIO drive strength for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 26.--27. "DRIVE_SEL5,Sets the GPIO drive strength for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0x10 24.--25. "DRIVE_SEL4,Sets the GPIO drive strength for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 22.--23. "DRIVE_SEL3,Sets the GPIO drive strength for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0x10 20.--21. "DRIVE_SEL2,Sets the GPIO drive strength for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 18.--19. "DRIVE_SEL1,Sets the GPIO drive strength for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "DRIVE_SEL0,Sets the GPIO drive strength for IO pin 0" "0: Full drive strength: GPIO drives current at its..,1: 1/2 drive strength: GPIO drives current at 1/2..,2: 1/4 drive strength: GPIO drives current at 1/4..,3: 1/8 drive strength: GPIO drives current at 1/8.."
|
|
newline
|
|
bitfld.long 0x10 7. "SLOW7,Enables slow slew rate for IO pin 7" "0,1"
|
|
bitfld.long 0x10 6. "SLOW6,Enables slow slew rate for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "SLOW5,Enables slow slew rate for IO pin 5" "0,1"
|
|
bitfld.long 0x10 4. "SLOW4,Enables slow slew rate for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "SLOW3,Enables slow slew rate for IO pin 3" "0,1"
|
|
bitfld.long 0x10 2. "SLOW2,Enables slow slew rate for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "SLOW1,Enables slow slew rate for IO pin 1" "0,1"
|
|
bitfld.long 0x10 0. "SLOW0,Enables slow slew rate for IO pin 0" "0: Fast slew rate,1: Slow slew rate"
|
|
line.long 0x14 "CFG_SIO,Port SIO configuration register"
|
|
bitfld.long 0x14 29.--31. "VOH_SEL67,N/A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 27.--28. "VREF_SEL67,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 26. "VTRIP_SEL67,N/A" "0,1"
|
|
bitfld.long 0x14 25. "IBUF_SEL67,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x14 24. "VREG_EN67,N/A" "0,1"
|
|
bitfld.long 0x14 21.--23. "VOH_SEL45,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 19.--20. "VREF_SEL45,N/A" "0,1,2,3"
|
|
bitfld.long 0x14 18. "VTRIP_SEL45,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x14 17. "IBUF_SEL45,N/A" "0,1"
|
|
bitfld.long 0x14 16. "VREG_EN45,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x14 13.--15. "VOH_SEL23,N/A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 11.--12. "VREF_SEL23,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 10. "VTRIP_SEL23,N/A" "0,1"
|
|
bitfld.long 0x14 9. "IBUF_SEL23,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x14 8. "VREG_EN23,N/A" "0,1"
|
|
bitfld.long 0x14 5.--7. "VOH_SEL01,Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'):" "0: Trip point=0,1: a,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x14 3.--4. "VREF_SEL01,N/A" "0,1,2,3"
|
|
bitfld.long 0x14 2. "VTRIP_SEL01,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "IBUF_SEL01,N/A" "0,1"
|
|
bitfld.long 0x14 0. "VREG_EN01,The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output.." "0,1"
|
|
group.long ($2+0x3C)++0x3
|
|
line.long 0x0 "CFG_IN_GPIO5V,Port GPIO5V input buffer configuration register"
|
|
bitfld.long 0x0 7. "VTRIP_SEL7_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 6. "VTRIP_SEL6_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "VTRIP_SEL5_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 4. "VTRIP_SEL4_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "VTRIP_SEL3_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 2. "VTRIP_SEL2_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "VTRIP_SEL1_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 0. "VTRIP_SEL0_1,Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field." "0: input buffer is not compatible with automotive,1: input buffer is compatible with automotive"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40320000
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 15. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE)(list ad:0x40310000 ad:0x40310080 ad:0x40310100 ad:0x40310180 ad:0x40310200 ad:0x40310280 ad:0x40310300 ad:0x40310380 ad:0x40310400 ad:0x40310480 ad:0x40310500 ad:0x40310580 ad:0x40310600 ad:0x40310680 ad:0x40310700)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "OUT,Port output data register"
|
|
bitfld.long 0x0 7. "OUT7,IO output data for pin 7" "0,1"
|
|
bitfld.long 0x0 6. "OUT6,IO output data for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUT5,IO output data for pin 5" "0,1"
|
|
bitfld.long 0x0 4. "OUT4,IO output data for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OUT3,IO output data for pin 3" "0,1"
|
|
bitfld.long 0x0 2. "OUT2,IO output data for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OUT1,IO output data for pin 1" "0,1"
|
|
bitfld.long 0x0 0. "OUT0,IO output data for pin 0" "0: Output state set to '0',1: Output state set to '1'"
|
|
line.long 0x4 "OUT_CLR,Port output data clear register"
|
|
bitfld.long 0x4 7. "OUT7,IO clear output for pin 7" "0,1"
|
|
bitfld.long 0x4 6. "OUT6,IO clear output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OUT5,IO clear output for pin 5" "0,1"
|
|
bitfld.long 0x4 4. "OUT4,IO clear output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OUT3,IO clear output for pin 3" "0,1"
|
|
bitfld.long 0x4 2. "OUT2,IO clear output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OUT1,IO clear output for pin 1" "0,1"
|
|
bitfld.long 0x4 0. "OUT0,IO clear output for pin 0:" "0: Output state not affected,1: Output state set to '0'"
|
|
line.long 0x8 "OUT_SET,Port output data set register"
|
|
bitfld.long 0x8 7. "OUT7,IO set output for pin 7" "0,1"
|
|
bitfld.long 0x8 6. "OUT6,IO set output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OUT5,IO set output for pin 5" "0,1"
|
|
bitfld.long 0x8 4. "OUT4,IO set output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "OUT3,IO set output for pin 3" "0,1"
|
|
bitfld.long 0x8 2. "OUT2,IO set output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "OUT1,IO set output for pin 1" "0,1"
|
|
bitfld.long 0x8 0. "OUT0,IO set output for pin 0:" "0: Output state not affected,1: Output state set to '1'"
|
|
line.long 0xC "OUT_INV,Port output data invert register"
|
|
bitfld.long 0xC 7. "OUT7,IO invert output for pin 7" "0,1"
|
|
bitfld.long 0xC 6. "OUT6,IO invert output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "OUT5,IO invert output for pin 5" "0,1"
|
|
bitfld.long 0xC 4. "OUT4,IO invert output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "OUT3,IO invert output for pin 3" "0,1"
|
|
bitfld.long 0xC 2. "OUT2,IO invert output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "OUT1,IO invert output for pin 1" "0,1"
|
|
bitfld.long 0xC 0. "OUT0,IO invert output for pin 0:" "0: '1',1: '0'"
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "IN,Port input state register"
|
|
bitfld.long 0x0 8. "FLT_IN,Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register." "0,1"
|
|
bitfld.long 0x0 7. "IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "IN6,IO pin state for pin 6" "0,1"
|
|
bitfld.long 0x0 5. "IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IN4,IO pin state for pin 4" "0,1"
|
|
bitfld.long 0x0 3. "IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IN2,IO pin state for pin 2" "0,1"
|
|
bitfld.long 0x0 1. "IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN0,IO pin state for pin 0" "0: Low logic level present on pin,1: High logic level present on pin"
|
|
group.long ($2+0x14)++0x7
|
|
line.long 0x0 "INTR,Port interrupt status register"
|
|
rbitfld.long 0x0 24. "FLT_IN_IN,Filtered pin state for pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
rbitfld.long 0x0 23. "IN_IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 22. "IN_IN6,IO pin state for pin 6" "0,1"
|
|
rbitfld.long 0x0 21. "IN_IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 20. "IN_IN4,IO pin state for pin 4" "0,1"
|
|
rbitfld.long 0x0 19. "IN_IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 18. "IN_IN2,IO pin state for pin 2" "0,1"
|
|
rbitfld.long 0x0 17. "IN_IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "IN_IN0,IO pin state for pin 0" "0,1"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "EDGE7,Edge detect for IO pin 7" "0,1"
|
|
bitfld.long 0x0 6. "EDGE6,Edge detect for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EDGE5,Edge detect for IO pin 5" "0,1"
|
|
bitfld.long 0x0 4. "EDGE4,Edge detect for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EDGE3,Edge detect for IO pin 3" "0,1"
|
|
bitfld.long 0x0 2. "EDGE2,Edge detect for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EDGE1,Edge detect for IO pin 1" "0,1"
|
|
bitfld.long 0x0 0. "EDGE0,Edge detect for IO pin 0" "0: No edge was detected on pin,1: An edge was detected on pin"
|
|
line.long 0x4 "INTR_MASK,Port interrupt mask register"
|
|
bitfld.long 0x4 8. "FLT_EDGE,Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x4 7. "EDGE7,Masks edge interrupt on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "EDGE6,Masks edge interrupt on IO pin 6" "0,1"
|
|
bitfld.long 0x4 5. "EDGE5,Masks edge interrupt on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EDGE4,Masks edge interrupt on IO pin 4" "0,1"
|
|
bitfld.long 0x4 3. "EDGE3,Masks edge interrupt on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EDGE2,Masks edge interrupt on IO pin 2" "0,1"
|
|
bitfld.long 0x4 1. "EDGE1,Masks edge interrupt on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EDGE0,Masks edge interrupt on IO pin 0" "0: Pin interrupt forwarding disabled,1: Pin interrupt forwarding enabled"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Port interrupt masked status register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Edge detected and masked on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Edge detected and masked on IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Edge detected and masked on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Edge detected and masked on IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Edge detected and masked on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Edge detected and masked on IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Edge detected and masked on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Edge detected AND masked on IO pin 0" "0: Interrupt was not forwarded to CPU,1: Interrupt occurred and was forwarded to CPU"
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "INTR_SET,Port interrupt set register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Sets edge detect interrupt for IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Sets edge detect interrupt for IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Sets edge detect interrupt for IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Sets edge detect interrupt for IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Sets edge detect interrupt for IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Sets edge detect interrupt for IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Sets edge detect interrupt for IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Sets edge detect interrupt for IO pin 0" "0: Interrupt state not affected,1: Interrupt set"
|
|
group.long ($2+0x40)++0x13
|
|
line.long 0x0 "INTR_CFG,Port interrupt configuration register"
|
|
bitfld.long 0x0 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. "FLT_EDGE_SEL,Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "EDGE7_SEL,Sets which edge will trigger an IRQ for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "EDGE6_SEL,Sets which edge will trigger an IRQ for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "EDGE5_SEL,Sets which edge will trigger an IRQ for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EDGE4_SEL,Sets which edge will trigger an IRQ for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "EDGE3_SEL,Sets which edge will trigger an IRQ for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "EDGE2_SEL,Sets which edge will trigger an IRQ for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "EDGE1_SEL,Sets which edge will trigger an IRQ for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pin 0" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
line.long 0x4 "CFG,Port configuration register"
|
|
bitfld.long 0x4 31. "IN_EN7,Enables the input buffer for IO pin 7" "0,1"
|
|
bitfld.long 0x4 28.--30. "DRIVE_MODE7,The GPIO drive mode for IO pin 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 27. "IN_EN6,Enables the input buffer for IO pin 6" "0,1"
|
|
bitfld.long 0x4 24.--26. "DRIVE_MODE6,The GPIO drive mode for IO pin 6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 23. "IN_EN5,Enables the input buffer for IO pin 5" "0,1"
|
|
bitfld.long 0x4 20.--22. "DRIVE_MODE5,The GPIO drive mode for IO pin 5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 19. "IN_EN4,Enables the input buffer for IO pin 4" "0,1"
|
|
bitfld.long 0x4 16.--18. "DRIVE_MODE4,The GPIO drive mode for IO pin4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 15. "IN_EN3,Enables the input buffer for IO pin 3" "0,1"
|
|
bitfld.long 0x4 12.--14. "DRIVE_MODE3,The GPIO drive mode for IO pin 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "IN_EN2,Enables the input buffer for IO pin 2" "0,1"
|
|
bitfld.long 0x4 8.--10. "DRIVE_MODE2,The GPIO drive mode for IO pin 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 7. "IN_EN1,Enables the input buffer for IO pin 1" "0,1"
|
|
bitfld.long 0x4 4.--6. "DRIVE_MODE1,The GPIO drive mode for IO pin 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "IN_EN0,Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue." "0: Input buffer disabled,1: Input buffer enabled"
|
|
bitfld.long 0x4 0.--2. "DRIVE_MODE0,The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
line.long 0x8 "CFG_IN,Port input buffer configuration register"
|
|
bitfld.long 0x8 7. "VTRIP_SEL7_0,Configures the pin 7 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 6. "VTRIP_SEL6_0,Configures the pin 6 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "VTRIP_SEL5_0,Configures the pin 5 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 4. "VTRIP_SEL4_0,Configures the pin 4 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "VTRIP_SEL3_0,Configures the pin 3 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 2. "VTRIP_SEL2_0,Configures the pin 2 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "VTRIP_SEL1_0,Configures the pin 1 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 0. "VTRIP_SEL0_0,Configures the pin 0 input buffer mode (trip points and hysteresis)" "0: PSoC 6:: Input buffer compatible with CMOS and..,1: PSoC 6:: Input buffer compatible with TTL and.."
|
|
line.long 0xC "CFG_OUT,Port output buffer configuration register"
|
|
bitfld.long 0xC 30.--31. "DRIVE_SEL7,N/A" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "DRIVE_SEL6,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "DRIVE_SEL5,N/A" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "DRIVE_SEL4,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "DRIVE_SEL3,N/A" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "DRIVE_SEL2,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "DRIVE_SEL1,N/A" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "DRIVE_SEL0,Documentation:" "0: Please refer to architecture TRM section I/O..,1: Please refer to architecture TRM section I/O..,2: Please refer to architecture TRM section I/O..,3: Please refer to architecture TRM section I/O.."
|
|
newline
|
|
bitfld.long 0xC 7. "SLOW7,N/A" "0,1"
|
|
bitfld.long 0xC 6. "SLOW6,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "SLOW5,N/A" "0,1"
|
|
bitfld.long 0xC 4. "SLOW4,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "SLOW3,N/A" "0,1"
|
|
bitfld.long 0xC 2. "SLOW2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "SLOW1,N/A" "0,1"
|
|
bitfld.long 0xC 0. "SLOW0,N/A" "0,1"
|
|
line.long 0x10 "CFG_SIO,Port SIO configuration register"
|
|
bitfld.long 0x10 29.--31. "VOH_SEL67,N/A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 27.--28. "VREF_SEL67,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 26. "VTRIP_SEL67,N/A" "0,1"
|
|
bitfld.long 0x10 25. "IBUF_SEL67,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "VREG_EN67,N/A" "0,1"
|
|
bitfld.long 0x10 21.--23. "VOH_SEL45,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 19.--20. "VREF_SEL45,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 18. "VTRIP_SEL45,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "IBUF_SEL45,N/A" "0,1"
|
|
bitfld.long 0x10 16. "VREG_EN45,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13.--15. "VOH_SEL23,N/A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 11.--12. "VREF_SEL23,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10. "VTRIP_SEL23,N/A" "0,1"
|
|
bitfld.long 0x10 9. "IBUF_SEL23,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "VREG_EN23,N/A" "0,1"
|
|
bitfld.long 0x10 5.--7. "VOH_SEL01,Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'):" "0: Trip point=0,1: a,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x10 3.--4. "VREF_SEL01,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 2. "VTRIP_SEL01,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "IBUF_SEL01,N/A" "0,1"
|
|
bitfld.long 0x10 0. "VREG_EN01,The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output.." "0,1"
|
|
group.long ($2+0x58)++0x3
|
|
line.long 0x0 "CFG_IN_AUTOLVL,Port input buffer AUTOLVL configuration register"
|
|
bitfld.long 0x0 7. "VTRIP_SEL7_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 6. "VTRIP_SEL6_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "VTRIP_SEL5_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 4. "VTRIP_SEL4_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "VTRIP_SEL3_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 2. "VTRIP_SEL2_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "VTRIP_SEL1_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 0. "VTRIP_SEL0_1,Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below:" "0: input buffer is compatible with automotive,1: input buffer is compatible with automotvie"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40320000
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 15. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE)(list ad:0x40310000 ad:0x40310080 ad:0x40310100 ad:0x40310180 ad:0x40310200 ad:0x40310280 ad:0x40310300 ad:0x40310380 ad:0x40310400 ad:0x40310480 ad:0x40310500 ad:0x40310580 ad:0x40310600 ad:0x40310680 ad:0x40310700)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "OUT,Port output data register"
|
|
bitfld.long 0x0 7. "OUT7,IO output data for pin 7" "0,1"
|
|
bitfld.long 0x0 6. "OUT6,IO output data for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUT5,IO output data for pin 5" "0,1"
|
|
bitfld.long 0x0 4. "OUT4,IO output data for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OUT3,IO output data for pin 3" "0,1"
|
|
bitfld.long 0x0 2. "OUT2,IO output data for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OUT1,IO output data for pin 1" "0,1"
|
|
bitfld.long 0x0 0. "OUT0,IO output data for pin 0" "0: Output state set to '0',1: Output state set to '1'"
|
|
line.long 0x4 "OUT_CLR,Port output data clear register"
|
|
bitfld.long 0x4 7. "OUT7,IO clear output for pin 7" "0,1"
|
|
bitfld.long 0x4 6. "OUT6,IO clear output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OUT5,IO clear output for pin 5" "0,1"
|
|
bitfld.long 0x4 4. "OUT4,IO clear output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OUT3,IO clear output for pin 3" "0,1"
|
|
bitfld.long 0x4 2. "OUT2,IO clear output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OUT1,IO clear output for pin 1" "0,1"
|
|
bitfld.long 0x4 0. "OUT0,IO clear output for pin 0:" "0: Output state not affected,1: Output state set to '0'"
|
|
line.long 0x8 "OUT_SET,Port output data set register"
|
|
bitfld.long 0x8 7. "OUT7,IO set output for pin 7" "0,1"
|
|
bitfld.long 0x8 6. "OUT6,IO set output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OUT5,IO set output for pin 5" "0,1"
|
|
bitfld.long 0x8 4. "OUT4,IO set output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "OUT3,IO set output for pin 3" "0,1"
|
|
bitfld.long 0x8 2. "OUT2,IO set output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "OUT1,IO set output for pin 1" "0,1"
|
|
bitfld.long 0x8 0. "OUT0,IO set output for pin 0:" "0: Output state not affected,1: Output state set to '1'"
|
|
line.long 0xC "OUT_INV,Port output data invert register"
|
|
bitfld.long 0xC 7. "OUT7,IO invert output for pin 7" "0,1"
|
|
bitfld.long 0xC 6. "OUT6,IO invert output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "OUT5,IO invert output for pin 5" "0,1"
|
|
bitfld.long 0xC 4. "OUT4,IO invert output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "OUT3,IO invert output for pin 3" "0,1"
|
|
bitfld.long 0xC 2. "OUT2,IO invert output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "OUT1,IO invert output for pin 1" "0,1"
|
|
bitfld.long 0xC 0. "OUT0,IO invert output for pin 0:" "0: '1',1: '0'"
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "IN,Port input state register"
|
|
bitfld.long 0x0 8. "FLT_IN,Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register." "0,1"
|
|
bitfld.long 0x0 7. "IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "IN6,IO pin state for pin 6" "0,1"
|
|
bitfld.long 0x0 5. "IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IN4,IO pin state for pin 4" "0,1"
|
|
bitfld.long 0x0 3. "IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IN2,IO pin state for pin 2" "0,1"
|
|
bitfld.long 0x0 1. "IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN0,IO pin state for pin 0" "0: Low logic level present on pin,1: High logic level present on pin"
|
|
group.long ($2+0x14)++0x7
|
|
line.long 0x0 "INTR,Port interrupt status register"
|
|
rbitfld.long 0x0 24. "FLT_IN_IN,Filtered pin state for pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
rbitfld.long 0x0 23. "IN_IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 22. "IN_IN6,IO pin state for pin 6" "0,1"
|
|
rbitfld.long 0x0 21. "IN_IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 20. "IN_IN4,IO pin state for pin 4" "0,1"
|
|
rbitfld.long 0x0 19. "IN_IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 18. "IN_IN2,IO pin state for pin 2" "0,1"
|
|
rbitfld.long 0x0 17. "IN_IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "IN_IN0,IO pin state for pin 0" "0,1"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "EDGE7,Edge detect for IO pin 7" "0,1"
|
|
bitfld.long 0x0 6. "EDGE6,Edge detect for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EDGE5,Edge detect for IO pin 5" "0,1"
|
|
bitfld.long 0x0 4. "EDGE4,Edge detect for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EDGE3,Edge detect for IO pin 3" "0,1"
|
|
bitfld.long 0x0 2. "EDGE2,Edge detect for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EDGE1,Edge detect for IO pin 1" "0,1"
|
|
bitfld.long 0x0 0. "EDGE0,Edge detect for IO pin 0" "0: No edge was detected on pin,1: An edge was detected on pin"
|
|
line.long 0x4 "INTR_MASK,Port interrupt mask register"
|
|
bitfld.long 0x4 8. "FLT_EDGE,Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x4 7. "EDGE7,Masks edge interrupt on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "EDGE6,Masks edge interrupt on IO pin 6" "0,1"
|
|
bitfld.long 0x4 5. "EDGE5,Masks edge interrupt on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EDGE4,Masks edge interrupt on IO pin 4" "0,1"
|
|
bitfld.long 0x4 3. "EDGE3,Masks edge interrupt on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EDGE2,Masks edge interrupt on IO pin 2" "0,1"
|
|
bitfld.long 0x4 1. "EDGE1,Masks edge interrupt on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EDGE0,Masks edge interrupt on IO pin 0" "0: Pin interrupt forwarding disabled,1: Pin interrupt forwarding enabled"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Port interrupt masked status register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Edge detected and masked on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Edge detected and masked on IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Edge detected and masked on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Edge detected and masked on IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Edge detected and masked on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Edge detected and masked on IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Edge detected and masked on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Edge detected AND masked on IO pin 0" "0: Interrupt was not forwarded to CPU,1: Interrupt occurred and was forwarded to CPU"
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "INTR_SET,Port interrupt set register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Sets edge detect interrupt for IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Sets edge detect interrupt for IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Sets edge detect interrupt for IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Sets edge detect interrupt for IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Sets edge detect interrupt for IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Sets edge detect interrupt for IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Sets edge detect interrupt for IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Sets edge detect interrupt for IO pin 0" "0: Interrupt state not affected,1: Interrupt set"
|
|
group.long ($2+0x40)++0x13
|
|
line.long 0x0 "INTR_CFG,Port interrupt configuration register"
|
|
bitfld.long 0x0 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. "FLT_EDGE_SEL,Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "EDGE7_SEL,Sets which edge will trigger an IRQ for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "EDGE6_SEL,Sets which edge will trigger an IRQ for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "EDGE5_SEL,Sets which edge will trigger an IRQ for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EDGE4_SEL,Sets which edge will trigger an IRQ for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "EDGE3_SEL,Sets which edge will trigger an IRQ for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "EDGE2_SEL,Sets which edge will trigger an IRQ for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "EDGE1_SEL,Sets which edge will trigger an IRQ for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pin 0" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
line.long 0x4 "CFG,Port configuration register"
|
|
bitfld.long 0x4 31. "IN_EN7,Enables the input buffer for IO pin 7" "0,1"
|
|
bitfld.long 0x4 28.--30. "DRIVE_MODE7,The GPIO drive mode for IO pin 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 27. "IN_EN6,Enables the input buffer for IO pin 6" "0,1"
|
|
bitfld.long 0x4 24.--26. "DRIVE_MODE6,The GPIO drive mode for IO pin 6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 23. "IN_EN5,Enables the input buffer for IO pin 5" "0,1"
|
|
bitfld.long 0x4 20.--22. "DRIVE_MODE5,The GPIO drive mode for IO pin 5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 19. "IN_EN4,Enables the input buffer for IO pin 4" "0,1"
|
|
bitfld.long 0x4 16.--18. "DRIVE_MODE4,The GPIO drive mode for IO pin4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 15. "IN_EN3,Enables the input buffer for IO pin 3" "0,1"
|
|
bitfld.long 0x4 12.--14. "DRIVE_MODE3,The GPIO drive mode for IO pin 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "IN_EN2,Enables the input buffer for IO pin 2" "0,1"
|
|
bitfld.long 0x4 8.--10. "DRIVE_MODE2,The GPIO drive mode for IO pin 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 7. "IN_EN1,Enables the input buffer for IO pin 1" "0,1"
|
|
bitfld.long 0x4 4.--6. "DRIVE_MODE1,The GPIO drive mode for IO pin 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "IN_EN0,Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue." "0: Input buffer disabled,1: Input buffer enabled"
|
|
bitfld.long 0x4 0.--2. "DRIVE_MODE0,The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
line.long 0x8 "CFG_IN,Port input buffer configuration register"
|
|
bitfld.long 0x8 7. "VTRIP_SEL7_0,Configures the pin 7 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 6. "VTRIP_SEL6_0,Configures the pin 6 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "VTRIP_SEL5_0,Configures the pin 5 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 4. "VTRIP_SEL4_0,Configures the pin 4 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "VTRIP_SEL3_0,Configures the pin 3 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 2. "VTRIP_SEL2_0,Configures the pin 2 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "VTRIP_SEL1_0,Configures the pin 1 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 0. "VTRIP_SEL0_0,Configures the pin 0 input buffer mode (trip points and hysteresis)" "0: PSoC 6:: Input buffer compatible with CMOS and..,1: PSoC 6:: Input buffer compatible with TTL and.."
|
|
line.long 0xC "CFG_OUT,Port output buffer configuration register"
|
|
bitfld.long 0xC 30.--31. "DRIVE_SEL7,N/A" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "DRIVE_SEL6,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "DRIVE_SEL5,N/A" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "DRIVE_SEL4,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "DRIVE_SEL3,N/A" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "DRIVE_SEL2,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "DRIVE_SEL1,N/A" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "DRIVE_SEL0,Documentation:" "0: Please refer to architecture TRM section I/O..,1: Please refer to architecture TRM section I/O..,2: Please refer to architecture TRM section I/O..,3: Please refer to architecture TRM section I/O.."
|
|
newline
|
|
bitfld.long 0xC 7. "SLOW7,N/A" "0,1"
|
|
bitfld.long 0xC 6. "SLOW6,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "SLOW5,N/A" "0,1"
|
|
bitfld.long 0xC 4. "SLOW4,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "SLOW3,N/A" "0,1"
|
|
bitfld.long 0xC 2. "SLOW2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "SLOW1,N/A" "0,1"
|
|
bitfld.long 0xC 0. "SLOW0,N/A" "0,1"
|
|
line.long 0x10 "CFG_SIO,Port SIO configuration register"
|
|
bitfld.long 0x10 29.--31. "VOH_SEL67,N/A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 27.--28. "VREF_SEL67,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 26. "VTRIP_SEL67,N/A" "0,1"
|
|
bitfld.long 0x10 25. "IBUF_SEL67,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "VREG_EN67,N/A" "0,1"
|
|
bitfld.long 0x10 21.--23. "VOH_SEL45,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 19.--20. "VREF_SEL45,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 18. "VTRIP_SEL45,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "IBUF_SEL45,N/A" "0,1"
|
|
bitfld.long 0x10 16. "VREG_EN45,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13.--15. "VOH_SEL23,N/A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 11.--12. "VREF_SEL23,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10. "VTRIP_SEL23,N/A" "0,1"
|
|
bitfld.long 0x10 9. "IBUF_SEL23,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "VREG_EN23,N/A" "0,1"
|
|
bitfld.long 0x10 5.--7. "VOH_SEL01,Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'):" "0: Trip point=0,1: a,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x10 3.--4. "VREF_SEL01,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 2. "VTRIP_SEL01,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "IBUF_SEL01,N/A" "0,1"
|
|
bitfld.long 0x10 0. "VREG_EN01,The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output.." "0,1"
|
|
group.long ($2+0x58)++0x3
|
|
line.long 0x0 "CFG_IN_AUTOLVL,Port input buffer AUTOLVL configuration register"
|
|
bitfld.long 0x0 7. "VTRIP_SEL7_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 6. "VTRIP_SEL6_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "VTRIP_SEL5_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 4. "VTRIP_SEL4_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "VTRIP_SEL3_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 2. "VTRIP_SEL2_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "VTRIP_SEL1_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 0. "VTRIP_SEL0_1,Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below:" "0: input buffer is compatible with automotive,1: input buffer is compatible with automotvie"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40320000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 15. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE)(list ad:0x40310000 ad:0x40310080 ad:0x40310100 ad:0x40310180 ad:0x40310200 ad:0x40310280 ad:0x40310300 ad:0x40310380 ad:0x40310400 ad:0x40310480 ad:0x40310500 ad:0x40310580 ad:0x40310600 ad:0x40310680 ad:0x40310700)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "OUT,Port output data register"
|
|
bitfld.long 0x0 7. "OUT7,IO output data for pin 7" "0,1"
|
|
bitfld.long 0x0 6. "OUT6,IO output data for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUT5,IO output data for pin 5" "0,1"
|
|
bitfld.long 0x0 4. "OUT4,IO output data for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OUT3,IO output data for pin 3" "0,1"
|
|
bitfld.long 0x0 2. "OUT2,IO output data for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OUT1,IO output data for pin 1" "0,1"
|
|
bitfld.long 0x0 0. "OUT0,IO output data for pin 0" "0: Output state set to '0',1: Output state set to '1'"
|
|
line.long 0x4 "OUT_CLR,Port output data clear register"
|
|
bitfld.long 0x4 7. "OUT7,IO clear output for pin 7" "0,1"
|
|
bitfld.long 0x4 6. "OUT6,IO clear output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OUT5,IO clear output for pin 5" "0,1"
|
|
bitfld.long 0x4 4. "OUT4,IO clear output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OUT3,IO clear output for pin 3" "0,1"
|
|
bitfld.long 0x4 2. "OUT2,IO clear output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OUT1,IO clear output for pin 1" "0,1"
|
|
bitfld.long 0x4 0. "OUT0,IO clear output for pin 0:" "0: Output state not affected,1: Output state set to '0'"
|
|
line.long 0x8 "OUT_SET,Port output data set register"
|
|
bitfld.long 0x8 7. "OUT7,IO set output for pin 7" "0,1"
|
|
bitfld.long 0x8 6. "OUT6,IO set output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OUT5,IO set output for pin 5" "0,1"
|
|
bitfld.long 0x8 4. "OUT4,IO set output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "OUT3,IO set output for pin 3" "0,1"
|
|
bitfld.long 0x8 2. "OUT2,IO set output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "OUT1,IO set output for pin 1" "0,1"
|
|
bitfld.long 0x8 0. "OUT0,IO set output for pin 0:" "0: Output state not affected,1: Output state set to '1'"
|
|
line.long 0xC "OUT_INV,Port output data invert register"
|
|
bitfld.long 0xC 7. "OUT7,IO invert output for pin 7" "0,1"
|
|
bitfld.long 0xC 6. "OUT6,IO invert output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "OUT5,IO invert output for pin 5" "0,1"
|
|
bitfld.long 0xC 4. "OUT4,IO invert output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "OUT3,IO invert output for pin 3" "0,1"
|
|
bitfld.long 0xC 2. "OUT2,IO invert output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "OUT1,IO invert output for pin 1" "0,1"
|
|
bitfld.long 0xC 0. "OUT0,IO invert output for pin 0:" "0: '1',1: '0'"
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "IN,Port input state register"
|
|
bitfld.long 0x0 8. "FLT_IN,Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register." "0,1"
|
|
bitfld.long 0x0 7. "IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "IN6,IO pin state for pin 6" "0,1"
|
|
bitfld.long 0x0 5. "IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IN4,IO pin state for pin 4" "0,1"
|
|
bitfld.long 0x0 3. "IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IN2,IO pin state for pin 2" "0,1"
|
|
bitfld.long 0x0 1. "IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN0,IO pin state for pin 0" "0: Low logic level present on pin,1: High logic level present on pin"
|
|
group.long ($2+0x14)++0x7
|
|
line.long 0x0 "INTR,Port interrupt status register"
|
|
rbitfld.long 0x0 24. "FLT_IN_IN,Filtered pin state for pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
rbitfld.long 0x0 23. "IN_IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 22. "IN_IN6,IO pin state for pin 6" "0,1"
|
|
rbitfld.long 0x0 21. "IN_IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 20. "IN_IN4,IO pin state for pin 4" "0,1"
|
|
rbitfld.long 0x0 19. "IN_IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 18. "IN_IN2,IO pin state for pin 2" "0,1"
|
|
rbitfld.long 0x0 17. "IN_IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "IN_IN0,IO pin state for pin 0" "0,1"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "EDGE7,Edge detect for IO pin 7" "0,1"
|
|
bitfld.long 0x0 6. "EDGE6,Edge detect for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EDGE5,Edge detect for IO pin 5" "0,1"
|
|
bitfld.long 0x0 4. "EDGE4,Edge detect for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EDGE3,Edge detect for IO pin 3" "0,1"
|
|
bitfld.long 0x0 2. "EDGE2,Edge detect for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EDGE1,Edge detect for IO pin 1" "0,1"
|
|
bitfld.long 0x0 0. "EDGE0,Edge detect for IO pin 0" "0: No edge was detected on pin,1: An edge was detected on pin"
|
|
line.long 0x4 "INTR_MASK,Port interrupt mask register"
|
|
bitfld.long 0x4 8. "FLT_EDGE,Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x4 7. "EDGE7,Masks edge interrupt on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "EDGE6,Masks edge interrupt on IO pin 6" "0,1"
|
|
bitfld.long 0x4 5. "EDGE5,Masks edge interrupt on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EDGE4,Masks edge interrupt on IO pin 4" "0,1"
|
|
bitfld.long 0x4 3. "EDGE3,Masks edge interrupt on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EDGE2,Masks edge interrupt on IO pin 2" "0,1"
|
|
bitfld.long 0x4 1. "EDGE1,Masks edge interrupt on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EDGE0,Masks edge interrupt on IO pin 0" "0: Pin interrupt forwarding disabled,1: Pin interrupt forwarding enabled"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Port interrupt masked status register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Edge detected and masked on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Edge detected and masked on IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Edge detected and masked on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Edge detected and masked on IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Edge detected and masked on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Edge detected and masked on IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Edge detected and masked on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Edge detected AND masked on IO pin 0" "0: Interrupt was not forwarded to CPU,1: Interrupt occurred and was forwarded to CPU"
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "INTR_SET,Port interrupt set register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Sets edge detect interrupt for IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Sets edge detect interrupt for IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Sets edge detect interrupt for IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Sets edge detect interrupt for IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Sets edge detect interrupt for IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Sets edge detect interrupt for IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Sets edge detect interrupt for IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Sets edge detect interrupt for IO pin 0" "0: Interrupt state not affected,1: Interrupt set"
|
|
group.long ($2+0x40)++0x13
|
|
line.long 0x0 "INTR_CFG,Port interrupt configuration register"
|
|
bitfld.long 0x0 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. "FLT_EDGE_SEL,Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "EDGE7_SEL,Sets which edge will trigger an IRQ for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "EDGE6_SEL,Sets which edge will trigger an IRQ for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "EDGE5_SEL,Sets which edge will trigger an IRQ for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EDGE4_SEL,Sets which edge will trigger an IRQ for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "EDGE3_SEL,Sets which edge will trigger an IRQ for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "EDGE2_SEL,Sets which edge will trigger an IRQ for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "EDGE1_SEL,Sets which edge will trigger an IRQ for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pin 0" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
line.long 0x4 "CFG,Port configuration register"
|
|
bitfld.long 0x4 31. "IN_EN7,Enables the input buffer for IO pin 7" "0,1"
|
|
bitfld.long 0x4 28.--30. "DRIVE_MODE7,The GPIO drive mode for IO pin 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 27. "IN_EN6,Enables the input buffer for IO pin 6" "0,1"
|
|
bitfld.long 0x4 24.--26. "DRIVE_MODE6,The GPIO drive mode for IO pin 6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 23. "IN_EN5,Enables the input buffer for IO pin 5" "0,1"
|
|
bitfld.long 0x4 20.--22. "DRIVE_MODE5,The GPIO drive mode for IO pin 5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 19. "IN_EN4,Enables the input buffer for IO pin 4" "0,1"
|
|
bitfld.long 0x4 16.--18. "DRIVE_MODE4,The GPIO drive mode for IO pin4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 15. "IN_EN3,Enables the input buffer for IO pin 3" "0,1"
|
|
bitfld.long 0x4 12.--14. "DRIVE_MODE3,The GPIO drive mode for IO pin 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "IN_EN2,Enables the input buffer for IO pin 2" "0,1"
|
|
bitfld.long 0x4 8.--10. "DRIVE_MODE2,The GPIO drive mode for IO pin 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 7. "IN_EN1,Enables the input buffer for IO pin 1" "0,1"
|
|
bitfld.long 0x4 4.--6. "DRIVE_MODE1,The GPIO drive mode for IO pin 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "IN_EN0,Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue." "0: Input buffer disabled,1: Input buffer enabled"
|
|
bitfld.long 0x4 0.--2. "DRIVE_MODE0,The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
line.long 0x8 "CFG_IN,Port input buffer configuration register"
|
|
bitfld.long 0x8 7. "VTRIP_SEL7_0,Configures the pin 7 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 6. "VTRIP_SEL6_0,Configures the pin 6 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "VTRIP_SEL5_0,Configures the pin 5 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 4. "VTRIP_SEL4_0,Configures the pin 4 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "VTRIP_SEL3_0,Configures the pin 3 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 2. "VTRIP_SEL2_0,Configures the pin 2 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "VTRIP_SEL1_0,Configures the pin 1 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 0. "VTRIP_SEL0_0,Configures the pin 0 input buffer mode (trip points and hysteresis)" "0: PSoC 6:: Input buffer compatible with CMOS and..,1: PSoC 6:: Input buffer compatible with TTL and.."
|
|
line.long 0xC "CFG_OUT,Port output buffer configuration register"
|
|
bitfld.long 0xC 30.--31. "DRIVE_SEL7,N/A" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "DRIVE_SEL6,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "DRIVE_SEL5,N/A" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "DRIVE_SEL4,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "DRIVE_SEL3,N/A" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "DRIVE_SEL2,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "DRIVE_SEL1,N/A" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "DRIVE_SEL0,Documentation:" "0: Please refer to architecture TRM section I/O..,1: Please refer to architecture TRM section I/O..,2: Please refer to architecture TRM section I/O..,3: Please refer to architecture TRM section I/O.."
|
|
newline
|
|
bitfld.long 0xC 7. "SLOW7,N/A" "0,1"
|
|
bitfld.long 0xC 6. "SLOW6,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "SLOW5,N/A" "0,1"
|
|
bitfld.long 0xC 4. "SLOW4,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "SLOW3,N/A" "0,1"
|
|
bitfld.long 0xC 2. "SLOW2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "SLOW1,N/A" "0,1"
|
|
bitfld.long 0xC 0. "SLOW0,N/A" "0,1"
|
|
line.long 0x10 "CFG_SIO,Port SIO configuration register"
|
|
bitfld.long 0x10 29.--31. "VOH_SEL67,N/A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 27.--28. "VREF_SEL67,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 26. "VTRIP_SEL67,N/A" "0,1"
|
|
bitfld.long 0x10 25. "IBUF_SEL67,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "VREG_EN67,N/A" "0,1"
|
|
bitfld.long 0x10 21.--23. "VOH_SEL45,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 19.--20. "VREF_SEL45,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 18. "VTRIP_SEL45,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "IBUF_SEL45,N/A" "0,1"
|
|
bitfld.long 0x10 16. "VREG_EN45,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13.--15. "VOH_SEL23,N/A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 11.--12. "VREF_SEL23,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10. "VTRIP_SEL23,N/A" "0,1"
|
|
bitfld.long 0x10 9. "IBUF_SEL23,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "VREG_EN23,N/A" "0,1"
|
|
bitfld.long 0x10 5.--7. "VOH_SEL01,Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'):" "0: Trip point=0,1: a,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x10 3.--4. "VREF_SEL01,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 2. "VTRIP_SEL01,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "IBUF_SEL01,N/A" "0,1"
|
|
bitfld.long 0x10 0. "VREG_EN01,The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output.." "0,1"
|
|
group.long ($2+0x58)++0x3
|
|
line.long 0x0 "CFG_IN_AUTOLVL,Port input buffer AUTOLVL configuration register"
|
|
bitfld.long 0x0 7. "VTRIP_SEL7_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 6. "VTRIP_SEL6_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "VTRIP_SEL5_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 4. "VTRIP_SEL4_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "VTRIP_SEL3_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 2. "VTRIP_SEL2_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "VTRIP_SEL1_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 0. "VTRIP_SEL0_1,Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below:" "0: input buffer is compatible with automotive,1: input buffer is compatible with automotvie"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40320000
|
|
endif
|
|
tree.end
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x40310000
|
|
elif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
base ad:0x40300000
|
|
endif
|
|
tree "HSIOM (High Speed IO Matrix)"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 15. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE)(list ad:0x40310000 ad:0x40310010 ad:0x40310020 ad:0x40310030 ad:0x40310040 ad:0x40310050 ad:0x40310060 ad:0x40310070 ad:0x40310080 ad:0x40310090 ad:0x403100A0 ad:0x403100B0 ad:0x403100C0 ad:0x403100D0 ad:0x403100E0)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PORT_SEL0,Port selection 0"
|
|
hexmask.long.byte 0x0 24.--28. 1. "IO3_SEL,Selects the peripheral connections of Pin 3."
|
|
hexmask.long.byte 0x0 16.--20. 1. "IO2_SEL,Selects the peripheral connections of Pin 2."
|
|
hexmask.long.byte 0x0 8.--12. 1. "IO1_SEL,Selects the peripheral connections of Pin 1."
|
|
hexmask.long.byte 0x0 0.--4. 1. "IO0_SEL,Selects the peripheral connections of Pin 0. Note that available connectivity options vary depending on the device port and the pin. See the device Datasheet for a list of peripheral connections available at each pin."
|
|
line.long 0x4 "PORT_SEL1,Port selection 1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "IO7_SEL,Selects the peripheral connections of Pin 6."
|
|
hexmask.long.byte 0x4 16.--20. 1. "IO6_SEL,Selects the peripheral connections of Pin 5."
|
|
hexmask.long.byte 0x4 8.--12. 1. "IO5_SEL,Selects the peripheral connections of Pin 4."
|
|
hexmask.long.byte 0x4 0.--4. 1. "IO4_SEL,Selects the peripheral connections of Pin 4. See PORT_SEL0 for connection details."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40310000
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 15. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE)(list ad:0x40300000 ad:0x40300010 ad:0x40300020 ad:0x40300030 ad:0x40300040 ad:0x40300050 ad:0x40300060 ad:0x40300070 ad:0x40300080 ad:0x40300090 ad:0x403000A0 ad:0x403000B0 ad:0x403000C0 ad:0x403000D0 ad:0x403000E0)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PORT_SEL0,Port selection 0"
|
|
hexmask.long.byte 0x0 24.--28. 1. "IO3_SEL,Selects the peripheral connections of Pin 3."
|
|
hexmask.long.byte 0x0 16.--20. 1. "IO2_SEL,Selects the peripheral connections of Pin 2."
|
|
hexmask.long.byte 0x0 8.--12. 1. "IO1_SEL,Selects the peripheral connections of Pin 1."
|
|
hexmask.long.byte 0x0 0.--4. 1. "IO0_SEL,Selects the peripheral connections of Pin 0. Note that available connectivity options vary depending on the device port and the pin. See the device Datasheet for a list of peripheral connections available at each pin."
|
|
line.long 0x4 "PORT_SEL1,Port selection 1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "IO7_SEL,Selects the peripheral connections of Pin 6."
|
|
hexmask.long.byte 0x4 16.--20. 1. "IO6_SEL,Selects the peripheral connections of Pin 5."
|
|
hexmask.long.byte 0x4 8.--12. 1. "IO5_SEL,Selects the peripheral connections of Pin 4."
|
|
hexmask.long.byte 0x4 0.--4. 1. "IO4_SEL,Selects the peripheral connections of Pin 4. See PORT_SEL0 for connection details."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40310000
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x2000)++0x3
|
|
line.long 0x0 "AMUX_SPLIT_CTL[$1],AMUX splitter cell control"
|
|
bitfld.long 0x0 6. "SWITCH_BB_S0,T-switch control for AMUXBUSB vssa/ground switch." "0,1"
|
|
bitfld.long 0x0 5. "SWITCH_BB_SR,T-switch control for Right AMUXBUSB switch." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SWITCH_BB_SL,T-switch control for Left AMUXBUSB switch." "0,1"
|
|
bitfld.long 0x0 2. "SWITCH_AA_S0,T-switch control for AMUXBUSA vssa/ground switch:" "0: switch open,1: switch closed"
|
|
newline
|
|
bitfld.long 0x0 1. "SWITCH_AA_SR,T-switch control for Right AMUXBUSA switch:" "0: switch open,1: switch closed"
|
|
bitfld.long 0x0 0. "SWITCH_AA_SL,T-switch control for Left AMUXBUSA switch:" "0: switch open,1: switch closed"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x2000)++0x3
|
|
line.long 0x0 "AMUX_SPLIT_CTL[$1],AMUX splitter cell control"
|
|
bitfld.long 0x0 6. "SWITCH_BB_S0,T-switch control for AMUXBUSB vssa/ground switch." "0,1"
|
|
bitfld.long 0x0 5. "SWITCH_BB_SR,T-switch control for Right AMUXBUSB switch." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SWITCH_BB_SL,T-switch control for Left AMUXBUSB switch." "0,1"
|
|
bitfld.long 0x0 2. "SWITCH_AA_S0,T-switch control for AMUXBUSA vssa/ground switch:" "0: switch open,1: switch closed"
|
|
newline
|
|
bitfld.long 0x0 1. "SWITCH_AA_SR,T-switch control for Right AMUXBUSA switch:" "0: switch open,1: switch closed"
|
|
bitfld.long 0x0 0. "SWITCH_AA_SL,T-switch control for Left AMUXBUSA switch:" "0: switch open,1: switch closed"
|
|
repeat.end
|
|
group.long 0x2200++0xF
|
|
line.long 0x0 "MONITOR_CTL_0,Power/Ground Monitor cell control 0"
|
|
hexmask.long 0x0 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0x4 "MONITOR_CTL_1,Power/Ground Monitor cell control 1"
|
|
hexmask.long 0x4 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0x8 "MONITOR_CTL_2,Power/Ground Monitor cell control 2"
|
|
hexmask.long 0x8 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0xC "MONITOR_CTL_3,Power/Ground Monitor cell control 3"
|
|
hexmask.long 0xC 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
group.long 0x2240++0x3
|
|
line.long 0x0 "ALT_JTAG_EN,Alternate JTAG IF selection register"
|
|
bitfld.long 0x0 31. "ENABLE,Provides the selection for alternate JTAG IF connectivity." "0: Primary JTAG interface is selected,1: Secondary"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 15. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE)(list ad:0x40300000 ad:0x40300010 ad:0x40300020 ad:0x40300030 ad:0x40300040 ad:0x40300050 ad:0x40300060 ad:0x40300070 ad:0x40300080 ad:0x40300090 ad:0x403000A0 ad:0x403000B0 ad:0x403000C0 ad:0x403000D0 ad:0x403000E0)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PORT_SEL0,Port selection 0"
|
|
hexmask.long.byte 0x0 24.--28. 1. "IO3_SEL,Selects the peripheral connections of Pin 3."
|
|
hexmask.long.byte 0x0 16.--20. 1. "IO2_SEL,Selects the peripheral connections of Pin 2."
|
|
hexmask.long.byte 0x0 8.--12. 1. "IO1_SEL,Selects the peripheral connections of Pin 1."
|
|
hexmask.long.byte 0x0 0.--4. 1. "IO0_SEL,Selects the peripheral connections of Pin 0. Note that available connectivity options vary depending on the device port and the pin. See the device Datasheet for a list of peripheral connections available at each pin."
|
|
line.long 0x4 "PORT_SEL1,Port selection 1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "IO7_SEL,Selects the peripheral connections of Pin 6."
|
|
hexmask.long.byte 0x4 16.--20. 1. "IO6_SEL,Selects the peripheral connections of Pin 5."
|
|
hexmask.long.byte 0x4 8.--12. 1. "IO5_SEL,Selects the peripheral connections of Pin 4."
|
|
hexmask.long.byte 0x4 0.--4. 1. "IO4_SEL,Selects the peripheral connections of Pin 4. See PORT_SEL0 for connection details."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40310000
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x2000)++0x3
|
|
line.long 0x0 "AMUX_SPLIT_CTL[$1],AMUX splitter cell control"
|
|
bitfld.long 0x0 6. "SWITCH_BB_S0,T-switch control for AMUXBUSB vssa/ground switch." "0,1"
|
|
bitfld.long 0x0 5. "SWITCH_BB_SR,T-switch control for Right AMUXBUSB switch." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SWITCH_BB_SL,T-switch control for Left AMUXBUSB switch." "0,1"
|
|
bitfld.long 0x0 2. "SWITCH_AA_S0,T-switch control for AMUXBUSA vssa/ground switch:" "0: switch open,1: switch closed"
|
|
newline
|
|
bitfld.long 0x0 1. "SWITCH_AA_SR,T-switch control for Right AMUXBUSA switch:" "0: switch open,1: switch closed"
|
|
bitfld.long 0x0 0. "SWITCH_AA_SL,T-switch control for Left AMUXBUSA switch:" "0: switch open,1: switch closed"
|
|
repeat.end
|
|
group.long 0x2200++0xF
|
|
line.long 0x0 "MONITOR_CTL_0,Power/Ground Monitor cell control 0"
|
|
hexmask.long 0x0 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0x4 "MONITOR_CTL_1,Power/Ground Monitor cell control 1"
|
|
hexmask.long 0x4 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0x8 "MONITOR_CTL_2,Power/Ground Monitor cell control 2"
|
|
hexmask.long 0x8 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0xC "MONITOR_CTL_3,Power/Ground Monitor cell control 3"
|
|
hexmask.long 0xC 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
group.long 0x2240++0x3
|
|
line.long 0x0 "ALT_JTAG_EN,Alternate JTAG IF selection register"
|
|
bitfld.long 0x0 31. "ENABLE,Provides the selection for alternate JTAG IF connectivity." "0: Primary JTAG interface is selected,1: Secondary"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 15. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE)(list ad:0x40300000 ad:0x40300010 ad:0x40300020 ad:0x40300030 ad:0x40300040 ad:0x40300050 ad:0x40300060 ad:0x40300070 ad:0x40300080 ad:0x40300090 ad:0x403000A0 ad:0x403000B0 ad:0x403000C0 ad:0x403000D0 ad:0x403000E0)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PORT_SEL0,Port selection 0"
|
|
hexmask.long.byte 0x0 24.--28. 1. "IO3_SEL,Selects the peripheral connections of Pin 3."
|
|
hexmask.long.byte 0x0 16.--20. 1. "IO2_SEL,Selects the peripheral connections of Pin 2."
|
|
hexmask.long.byte 0x0 8.--12. 1. "IO1_SEL,Selects the peripheral connections of Pin 1."
|
|
hexmask.long.byte 0x0 0.--4. 1. "IO0_SEL,Selects the peripheral connections of Pin 0. Note that available connectivity options vary depending on the device port and the pin. See the device Datasheet for a list of peripheral connections available at each pin."
|
|
line.long 0x4 "PORT_SEL1,Port selection 1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "IO7_SEL,Selects the peripheral connections of Pin 6."
|
|
hexmask.long.byte 0x4 16.--20. 1. "IO6_SEL,Selects the peripheral connections of Pin 5."
|
|
hexmask.long.byte 0x4 8.--12. 1. "IO5_SEL,Selects the peripheral connections of Pin 4."
|
|
hexmask.long.byte 0x4 0.--4. 1. "IO4_SEL,Selects the peripheral connections of Pin 4. See PORT_SEL0 for connection details."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40310000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x2000)++0x3
|
|
line.long 0x0 "AMUX_SPLIT_CTL[$1],AMUX splitter cell control"
|
|
bitfld.long 0x0 6. "SWITCH_BB_S0,T-switch control for AMUXBUSB vssa/ground switch." "0,1"
|
|
bitfld.long 0x0 5. "SWITCH_BB_SR,T-switch control for Right AMUXBUSB switch." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SWITCH_BB_SL,T-switch control for Left AMUXBUSB switch." "0,1"
|
|
bitfld.long 0x0 2. "SWITCH_AA_S0,T-switch control for AMUXBUSA vssa/ground switch:" "0: switch open,1: switch closed"
|
|
newline
|
|
bitfld.long 0x0 1. "SWITCH_AA_SR,T-switch control for Right AMUXBUSA switch:" "0: switch open,1: switch closed"
|
|
bitfld.long 0x0 0. "SWITCH_AA_SL,T-switch control for Left AMUXBUSA switch:" "0: switch open,1: switch closed"
|
|
repeat.end
|
|
group.long 0x2200++0xF
|
|
line.long 0x0 "MONITOR_CTL_0,Power/Ground Monitor cell control 0"
|
|
hexmask.long 0x0 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0x4 "MONITOR_CTL_1,Power/Ground Monitor cell control 1"
|
|
hexmask.long 0x4 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0x8 "MONITOR_CTL_2,Power/Ground Monitor cell control 2"
|
|
hexmask.long 0x8 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0xC "MONITOR_CTL_3,Power/Ground Monitor cell control 3"
|
|
hexmask.long 0xC 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
group.long 0x2240++0x3
|
|
line.long 0x0 "ALT_JTAG_EN,Alternate JTAG IF selection register"
|
|
bitfld.long 0x0 31. "ENABLE,Provides the selection for alternate JTAG IF connectivity." "0: Primary JTAG interface is selected,1: Secondary"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??6*")||cpuis("CYS06??7*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
tree "I2S (Inter IC Sound)"
|
|
base ad:0x0
|
|
sif (cpuis("CY8C6??6*")||cpuis("CYB06??6*")||cpuis("CYS06??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??7*")||cpuis("CYS06??7*"))
|
|
tree "I2S0"
|
|
base ad:0x42A10000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "RX_ENABLED,Enables the I2S RX component:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 30. "TX_ENABLED,Enables the I2S TX component:" "0: Disabled,1: Enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CLOCK_CTL,Clock control"
|
|
bitfld.long 0x0 8. "CLOCK_SEL,Selects clock to be used by I2S:" "0: Internal clock,1: External clock"
|
|
hexmask.long.byte 0x0 0.--5. 1. "CLOCK_DIV,Frequency divisor for generating I2S clock frequency."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CMD,Command"
|
|
bitfld.long 0x0 16. "RX_START,Receiver enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 8. "TX_PAUSE,Pause enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "TX_START,Transmitter enable:" "0: Disabled,1: Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "TR_CTL,Trigger control"
|
|
bitfld.long 0x0 16. "RX_REQ_EN,Trigger output ('tr_i2s_rx_req') enable for requests of DMA transfer in reception" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "TX_REQ_EN,Trigger output ('tr_i2s_tx_req') enable for requests of DMA transfer in transmission" "0: Disabled,1: Enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "TX_CTL,Transmitter control"
|
|
bitfld.long 0x0 25. "SCKI_POL,N/A" "0,1"
|
|
bitfld.long 0x0 24. "SCKO_POL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--22. "WORD_LEN,Word length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
bitfld.long 0x0 16.--18. "CH_LEN,Channel length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
newline
|
|
bitfld.long 0x0 13. "WD_EN,N/A" "0,1"
|
|
bitfld.long 0x0 12. "OVHDATA,Set overhead value:" "0: Set to '0',1: Set to '1'"
|
|
newline
|
|
bitfld.long 0x0 10. "WS_PULSE,Set WS pulse width in TDM mode:" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
|
|
bitfld.long 0x0 8.--9. "I2S_MODE,Select I2S left-justified or TDM:" "0: Left Justified,1: I2S mode,2: TDM mode A the 1st Channel align to WSO Rising..,3: TDM mode B the 1st Channel align to WSO Rising.."
|
|
newline
|
|
bitfld.long 0x0 7. "MS,Set interface in master or slave mode:" "0: Slave,1: Master"
|
|
bitfld.long 0x0 4.--6. "CH_NR,Specifies number of channels per frame:" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
|
|
newline
|
|
bitfld.long 0x0 3. "B_CLOCK_INV,Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX slave mode." "0: Serial data will be transmitted off the SCK..,1: Serial data will be transmitted off the SCK.."
|
|
line.long 0x4 "TX_WATCHDOG,Transmitter watchdog"
|
|
hexmask.long 0x4 0.--31. 1. "WD_COUNTER,Start value of the TX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'."
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "RX_CTL,Receiver control"
|
|
bitfld.long 0x0 25. "SCKI_POL,N/A" "0,1"
|
|
bitfld.long 0x0 24. "SCKO_POL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "BIT_EXTENSION,N/A" "0,1"
|
|
bitfld.long 0x0 20.--22. "WORD_LEN,Word length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "CH_LEN,Channel length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
bitfld.long 0x0 13. "WD_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "WS_PULSE,Set WS pulse width in TDM mode:" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
|
|
bitfld.long 0x0 8.--9. "I2S_MODE,Select I2S left-justified or TDM:" "0: Left Justified,1: I2S mode,2: TDM mode A the 1st Channel align to WSO Rising..,3: TDM mode B the 1st Channel align to WSO Rising.."
|
|
newline
|
|
bitfld.long 0x0 7. "MS,Set interface in master or slave mode:" "0: Slave,1: Master"
|
|
bitfld.long 0x0 4.--6. "CH_NR,Specifies number of channels per frame:" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
|
|
newline
|
|
bitfld.long 0x0 3. "B_CLOCK_INV,Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master mode." "0: Serial data will be captured by the SCK falling..,1: Serial data will be captured by the SCK rising.."
|
|
line.long 0x4 "RX_WATCHDOG,Receiver watchdog"
|
|
hexmask.long 0x4 0.--31. 1. "WD_COUNTER,Start value of the RX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'."
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "TX_FIFO_CTL,TX FIFO control"
|
|
bitfld.long 0x0 17. "FREEZE,When '1' hardware reads from the TX FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. This field is used only for debugging purposes." "0,1"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the TX FIFO and TX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the TX FIFO has less entries than the number of this field a transmitter trigger event is generated."
|
|
rgroup.long 0x204++0x3
|
|
line.long 0x0 "TX_FIFO_STATUS,TX FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,TX FIFO write pointer: FIFO location at which a new data frame is written by the host. This field is used only for debugging purposes."
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,Number of entries in the TX FIFO. The field value is in the range [0 256]."
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "TX_FIFO_WR,TX FIFO write"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data written into the TX FIFO. Behavior is similar to that of a PUSH operation."
|
|
group.long 0x300++0x3
|
|
line.long 0x0 "RX_FIFO_CTL,RX FIFO control"
|
|
bitfld.long 0x0 17. "FREEZE,When '1' hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer. This field is used only for debugging purposee." "0,1"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the RX FIFO has more entries than the number of this field a receiver trigger event is generated."
|
|
rgroup.long 0x304++0xB
|
|
line.long 0x0 "RX_FIFO_STATUS,RX FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware. This field is used only for debugging purposes."
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,RX FIFO read pointer: FIFO location from which a data frame is read by the host. This field is used only for debugging purposes."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,Number of entries in the RX FIFO. The field value is in the range [0 256]."
|
|
line.long 0x4 "RX_FIFO_RD,RX FIFO read"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the RX FIFO. Reading a data frame will remove the data frame from the RX FIFO; i.e. behavior is similar to that of a POP operation."
|
|
line.long 0x8 "RX_FIFO_RD_SILENT,RX FIFO silent read"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes."
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR,Interrupt register"
|
|
bitfld.long 0x0 24. "RX_WD,Triggers (sets to '1') when the Rx watchdog event occurs." "0,1"
|
|
bitfld.long 0x0 22. "RX_UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RX_OVERFLOW,Attempt to write to a full RX FIFO." "0,1"
|
|
bitfld.long 0x0 19. "RX_FULL,RX FIFO is full." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RX_NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
bitfld.long 0x0 16. "RX_TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TX_WD,Triggers (sets to '1') when the Tx watchdog event occurs." "0,1"
|
|
bitfld.long 0x0 6. "TX_UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and TX_EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TX_OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
|
|
bitfld.long 0x0 4. "TX_EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TX_NOT_FULL,TX FIFO is not full." "0,1"
|
|
bitfld.long 0x0 0. "TX_TRIGGER,Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set register"
|
|
bitfld.long 0x4 24. "RX_WD,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 22. "RX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "RX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 19. "RX_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "RX_NOT_EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 16. "RX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TX_WD,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 6. "TX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 4. "TX_EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TX_NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "TX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 24. "RX_WD,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 22. "RX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "RX_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 19. "RX_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "RX_NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 16. "RX_TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "TX_WD,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 6. "TX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "TX_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 4. "TX_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TX_NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "TX_TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x0 24. "RX_WD,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 22. "RX_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RX_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 19. "RX_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RX_NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 16. "RX_TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TX_WD,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 6. "TX_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TX_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 4. "TX_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TX_NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "TX_TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CYB06??8*")||cpuis("CYS06??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??A*")||cpuis("CYS06??A*"))
|
|
tree "I2S0"
|
|
base ad:0x40A10000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "RX_ENABLED,Enables the I2S RX component:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 30. "TX_ENABLED,Enables the I2S TX component:" "0: Disabled,1: Enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CLOCK_CTL,Clock control"
|
|
bitfld.long 0x0 8. "CLOCK_SEL,Selects clock to be used by I2S:" "0: Internal clock,1: External clock"
|
|
hexmask.long.byte 0x0 0.--5. 1. "CLOCK_DIV,Frequency divisor for generating I2S clock frequency."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CMD,Command"
|
|
bitfld.long 0x0 16. "RX_START,Receiver enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 8. "TX_PAUSE,Pause enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "TX_START,Transmitter enable:" "0: Disabled,1: Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "TR_CTL,Trigger control"
|
|
bitfld.long 0x0 16. "RX_REQ_EN,Trigger output ('tr_i2s_rx_req') enable for requests of DMA transfer in reception" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "TX_REQ_EN,Trigger output ('tr_i2s_tx_req') enable for requests of DMA transfer in transmission" "0: Disabled,1: Enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "TX_CTL,Transmitter control"
|
|
bitfld.long 0x0 25. "SCKI_POL,N/A" "0,1"
|
|
bitfld.long 0x0 24. "SCKO_POL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--22. "WORD_LEN,Word length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
bitfld.long 0x0 16.--18. "CH_LEN,Channel length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
newline
|
|
bitfld.long 0x0 13. "WD_EN,N/A" "0,1"
|
|
bitfld.long 0x0 12. "OVHDATA,Set overhead value:" "0: Set to '0',1: Set to '1'"
|
|
newline
|
|
bitfld.long 0x0 10. "WS_PULSE,Set WS pulse width in TDM mode:" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
|
|
bitfld.long 0x0 8.--9. "I2S_MODE,Select I2S left-justified or TDM:" "0: Left Justified,1: I2S mode,2: TDM mode A the 1st Channel align to WSO Rising..,3: TDM mode B the 1st Channel align to WSO Rising.."
|
|
newline
|
|
bitfld.long 0x0 7. "MS,Set interface in master or slave mode:" "0: Slave,1: Master"
|
|
bitfld.long 0x0 4.--6. "CH_NR,Specifies number of channels per frame:" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
|
|
newline
|
|
bitfld.long 0x0 3. "B_CLOCK_INV,Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX slave mode." "0: Serial data will be transmitted off the SCK..,1: Serial data will be transmitted off the SCK.."
|
|
line.long 0x4 "TX_WATCHDOG,Transmitter watchdog"
|
|
hexmask.long 0x4 0.--31. 1. "WD_COUNTER,Start value of the TX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'."
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "RX_CTL,Receiver control"
|
|
bitfld.long 0x0 25. "SCKI_POL,N/A" "0,1"
|
|
bitfld.long 0x0 24. "SCKO_POL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "BIT_EXTENSION,N/A" "0,1"
|
|
bitfld.long 0x0 20.--22. "WORD_LEN,Word length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "CH_LEN,Channel length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
bitfld.long 0x0 13. "WD_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "WS_PULSE,Set WS pulse width in TDM mode:" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
|
|
bitfld.long 0x0 8.--9. "I2S_MODE,Select I2S left-justified or TDM:" "0: Left Justified,1: I2S mode,2: TDM mode A the 1st Channel align to WSO Rising..,3: TDM mode B the 1st Channel align to WSO Rising.."
|
|
newline
|
|
bitfld.long 0x0 7. "MS,Set interface in master or slave mode:" "0: Slave,1: Master"
|
|
bitfld.long 0x0 4.--6. "CH_NR,Specifies number of channels per frame:" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
|
|
newline
|
|
bitfld.long 0x0 3. "B_CLOCK_INV,Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master mode." "0: Serial data will be captured by the SCK falling..,1: Serial data will be captured by the SCK rising.."
|
|
line.long 0x4 "RX_WATCHDOG,Receiver watchdog"
|
|
hexmask.long 0x4 0.--31. 1. "WD_COUNTER,Start value of the RX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'."
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "TX_FIFO_CTL,TX FIFO control"
|
|
bitfld.long 0x0 17. "FREEZE,When '1' hardware reads from the TX FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. This field is used only for debugging purposes." "0,1"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the TX FIFO and TX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the TX FIFO has less entries than the number of this field a transmitter trigger event is generated."
|
|
rgroup.long 0x204++0x3
|
|
line.long 0x0 "TX_FIFO_STATUS,TX FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,TX FIFO write pointer: FIFO location at which a new data frame is written by the host. This field is used only for debugging purposes."
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,Number of entries in the TX FIFO. The field value is in the range [0 256]."
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "TX_FIFO_WR,TX FIFO write"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data written into the TX FIFO. Behavior is similar to that of a PUSH operation."
|
|
group.long 0x300++0x3
|
|
line.long 0x0 "RX_FIFO_CTL,RX FIFO control"
|
|
bitfld.long 0x0 17. "FREEZE,When '1' hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer. This field is used only for debugging purposee." "0,1"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the RX FIFO has more entries than the number of this field a receiver trigger event is generated."
|
|
rgroup.long 0x304++0xB
|
|
line.long 0x0 "RX_FIFO_STATUS,RX FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware. This field is used only for debugging purposes."
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,RX FIFO read pointer: FIFO location from which a data frame is read by the host. This field is used only for debugging purposes."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,Number of entries in the RX FIFO. The field value is in the range [0 256]."
|
|
line.long 0x4 "RX_FIFO_RD,RX FIFO read"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the RX FIFO. Reading a data frame will remove the data frame from the RX FIFO; i.e. behavior is similar to that of a POP operation."
|
|
line.long 0x8 "RX_FIFO_RD_SILENT,RX FIFO silent read"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes."
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR,Interrupt register"
|
|
bitfld.long 0x0 24. "RX_WD,Triggers (sets to '1') when the Rx watchdog event occurs." "0,1"
|
|
bitfld.long 0x0 22. "RX_UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RX_OVERFLOW,Attempt to write to a full RX FIFO." "0,1"
|
|
bitfld.long 0x0 19. "RX_FULL,RX FIFO is full." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RX_NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
bitfld.long 0x0 16. "RX_TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TX_WD,Triggers (sets to '1') when the Tx watchdog event occurs." "0,1"
|
|
bitfld.long 0x0 6. "TX_UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and TX_EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TX_OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
|
|
bitfld.long 0x0 4. "TX_EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TX_NOT_FULL,TX FIFO is not full." "0,1"
|
|
bitfld.long 0x0 0. "TX_TRIGGER,Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set register"
|
|
bitfld.long 0x4 24. "RX_WD,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 22. "RX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "RX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 19. "RX_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "RX_NOT_EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 16. "RX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TX_WD,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 6. "TX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 4. "TX_EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TX_NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "TX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 24. "RX_WD,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 22. "RX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "RX_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 19. "RX_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "RX_NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 16. "RX_TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "TX_WD,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 6. "TX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "TX_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 4. "TX_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TX_NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "TX_TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x0 24. "RX_WD,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 22. "RX_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RX_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 19. "RX_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RX_NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 16. "RX_TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TX_WD,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 6. "TX_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TX_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 4. "TX_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TX_NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "TX_TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CYB06??8*")||cpuis("CYS06??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??A*")||cpuis("CYS06??A*"))
|
|
tree "I2S1"
|
|
base ad:0x40A11000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "RX_ENABLED,Enables the I2S RX component:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 30. "TX_ENABLED,Enables the I2S TX component:" "0: Disabled,1: Enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CLOCK_CTL,Clock control"
|
|
bitfld.long 0x0 8. "CLOCK_SEL,Selects clock to be used by I2S:" "0: Internal clock,1: External clock"
|
|
hexmask.long.byte 0x0 0.--5. 1. "CLOCK_DIV,Frequency divisor for generating I2S clock frequency."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CMD,Command"
|
|
bitfld.long 0x0 16. "RX_START,Receiver enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 8. "TX_PAUSE,Pause enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "TX_START,Transmitter enable:" "0: Disabled,1: Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "TR_CTL,Trigger control"
|
|
bitfld.long 0x0 16. "RX_REQ_EN,Trigger output ('tr_i2s_rx_req') enable for requests of DMA transfer in reception" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "TX_REQ_EN,Trigger output ('tr_i2s_tx_req') enable for requests of DMA transfer in transmission" "0: Disabled,1: Enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "TX_CTL,Transmitter control"
|
|
bitfld.long 0x0 25. "SCKI_POL,N/A" "0,1"
|
|
bitfld.long 0x0 24. "SCKO_POL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--22. "WORD_LEN,Word length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
bitfld.long 0x0 16.--18. "CH_LEN,Channel length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
newline
|
|
bitfld.long 0x0 13. "WD_EN,N/A" "0,1"
|
|
bitfld.long 0x0 12. "OVHDATA,Set overhead value:" "0: Set to '0',1: Set to '1'"
|
|
newline
|
|
bitfld.long 0x0 10. "WS_PULSE,Set WS pulse width in TDM mode:" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
|
|
bitfld.long 0x0 8.--9. "I2S_MODE,Select I2S left-justified or TDM:" "0: Left Justified,1: I2S mode,2: TDM mode A the 1st Channel align to WSO Rising..,3: TDM mode B the 1st Channel align to WSO Rising.."
|
|
newline
|
|
bitfld.long 0x0 7. "MS,Set interface in master or slave mode:" "0: Slave,1: Master"
|
|
bitfld.long 0x0 4.--6. "CH_NR,Specifies number of channels per frame:" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
|
|
newline
|
|
bitfld.long 0x0 3. "B_CLOCK_INV,Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX slave mode." "0: Serial data will be transmitted off the SCK..,1: Serial data will be transmitted off the SCK.."
|
|
line.long 0x4 "TX_WATCHDOG,Transmitter watchdog"
|
|
hexmask.long 0x4 0.--31. 1. "WD_COUNTER,Start value of the TX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'."
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "RX_CTL,Receiver control"
|
|
bitfld.long 0x0 25. "SCKI_POL,N/A" "0,1"
|
|
bitfld.long 0x0 24. "SCKO_POL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "BIT_EXTENSION,N/A" "0,1"
|
|
bitfld.long 0x0 20.--22. "WORD_LEN,Word length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "CH_LEN,Channel length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
bitfld.long 0x0 13. "WD_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "WS_PULSE,Set WS pulse width in TDM mode:" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
|
|
bitfld.long 0x0 8.--9. "I2S_MODE,Select I2S left-justified or TDM:" "0: Left Justified,1: I2S mode,2: TDM mode A the 1st Channel align to WSO Rising..,3: TDM mode B the 1st Channel align to WSO Rising.."
|
|
newline
|
|
bitfld.long 0x0 7. "MS,Set interface in master or slave mode:" "0: Slave,1: Master"
|
|
bitfld.long 0x0 4.--6. "CH_NR,Specifies number of channels per frame:" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
|
|
newline
|
|
bitfld.long 0x0 3. "B_CLOCK_INV,Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master mode." "0: Serial data will be captured by the SCK falling..,1: Serial data will be captured by the SCK rising.."
|
|
line.long 0x4 "RX_WATCHDOG,Receiver watchdog"
|
|
hexmask.long 0x4 0.--31. 1. "WD_COUNTER,Start value of the RX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'."
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "TX_FIFO_CTL,TX FIFO control"
|
|
bitfld.long 0x0 17. "FREEZE,When '1' hardware reads from the TX FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. This field is used only for debugging purposes." "0,1"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the TX FIFO and TX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the TX FIFO has less entries than the number of this field a transmitter trigger event is generated."
|
|
rgroup.long 0x204++0x3
|
|
line.long 0x0 "TX_FIFO_STATUS,TX FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,TX FIFO write pointer: FIFO location at which a new data frame is written by the host. This field is used only for debugging purposes."
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,Number of entries in the TX FIFO. The field value is in the range [0 256]."
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "TX_FIFO_WR,TX FIFO write"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data written into the TX FIFO. Behavior is similar to that of a PUSH operation."
|
|
group.long 0x300++0x3
|
|
line.long 0x0 "RX_FIFO_CTL,RX FIFO control"
|
|
bitfld.long 0x0 17. "FREEZE,When '1' hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer. This field is used only for debugging purposee." "0,1"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the RX FIFO has more entries than the number of this field a receiver trigger event is generated."
|
|
rgroup.long 0x304++0xB
|
|
line.long 0x0 "RX_FIFO_STATUS,RX FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware. This field is used only for debugging purposes."
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,RX FIFO read pointer: FIFO location from which a data frame is read by the host. This field is used only for debugging purposes."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,Number of entries in the RX FIFO. The field value is in the range [0 256]."
|
|
line.long 0x4 "RX_FIFO_RD,RX FIFO read"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the RX FIFO. Reading a data frame will remove the data frame from the RX FIFO; i.e. behavior is similar to that of a POP operation."
|
|
line.long 0x8 "RX_FIFO_RD_SILENT,RX FIFO silent read"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes."
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR,Interrupt register"
|
|
bitfld.long 0x0 24. "RX_WD,Triggers (sets to '1') when the Rx watchdog event occurs." "0,1"
|
|
bitfld.long 0x0 22. "RX_UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RX_OVERFLOW,Attempt to write to a full RX FIFO." "0,1"
|
|
bitfld.long 0x0 19. "RX_FULL,RX FIFO is full." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RX_NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
bitfld.long 0x0 16. "RX_TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TX_WD,Triggers (sets to '1') when the Tx watchdog event occurs." "0,1"
|
|
bitfld.long 0x0 6. "TX_UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and TX_EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TX_OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
|
|
bitfld.long 0x0 4. "TX_EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TX_NOT_FULL,TX FIFO is not full." "0,1"
|
|
bitfld.long 0x0 0. "TX_TRIGGER,Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set register"
|
|
bitfld.long 0x4 24. "RX_WD,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 22. "RX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "RX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 19. "RX_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "RX_NOT_EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 16. "RX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TX_WD,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 6. "TX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 4. "TX_EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TX_NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "TX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 24. "RX_WD,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 22. "RX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "RX_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 19. "RX_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "RX_NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 16. "RX_TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "TX_WD,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 6. "TX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "TX_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 4. "TX_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TX_NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "TX_TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x0 24. "RX_WD,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 22. "RX_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RX_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 19. "RX_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RX_NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 16. "RX_TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TX_WD,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 6. "TX_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TX_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 4. "TX_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TX_NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "TX_TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x40230000
|
|
elif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
base ad:0x40220000
|
|
endif
|
|
tree "IPC (Inter-Processor Communication)"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40230000 ad:0x40230020 ad:0x40230040 ad:0x40230060 ad:0x40230080 ad:0x402300A0 ad:0x402300C0 ad:0x402300E0 ad:0x40230100 ad:0x40230120 ad:0x40230140 ad:0x40230160 ad:0x40230180 ad:0x402301A0 ad:0x402301C0 ad:0x402301E0)
|
|
tree "STRUCT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "ACQUIRE,IPC acquire"
|
|
bitfld.long 0x0 31. "SUCCESS,Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED):" "0: Not successfully acquired,1: Successfully acquired"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier that successfully acquired the lock."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context that successfully acquired the lock."
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
wgroup.long ($2+0x4)++0x7
|
|
line.long 0x0 "RELEASE,IPC release"
|
|
hexmask.long.word 0x0 0.--15. 1. "INTR_RELEASE,This field allows for the generation of release events to the IPC interrupt structures but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1' but.."
|
|
line.long 0x4 "NOTIFY,IPC notification"
|
|
hexmask.long.word 0x4 0.--15. 1. "INTR_NOTIFY,This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1' but only for those IPC interrupt structures for which the.."
|
|
group.long ($2+0xC)++0x3
|
|
line.long 0x0 "DATA,IPC data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,This field holds a 32-bit data element that is associated with the IPC structure."
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "LOCK_STATUS,IPC lock status"
|
|
bitfld.long 0x0 31. "ACQUIRED,Specifies if the lock is acquired. This field is set to '1' if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1')." "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier that successfully acquired the lock."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context that successfully acquired the lock."
|
|
bitfld.long 0x0 1. "NS,This field specifies the cecure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,This field specifies the user/privileged access control:" "0: user mode,1: privileged mode"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40230000
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40220000 ad:0x40220020 ad:0x40220040 ad:0x40220060 ad:0x40220080 ad:0x402200A0 ad:0x402200C0 ad:0x402200E0 ad:0x40220100 ad:0x40220120 ad:0x40220140 ad:0x40220160 ad:0x40220180 ad:0x402201A0 ad:0x402201C0 ad:0x402201E0)
|
|
tree "STRUCT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "ACQUIRE,IPC acquire"
|
|
bitfld.long 0x0 31. "SUCCESS,Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED):" "0: Not successfully acquired,1: Successfully acquired"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier that successfully acquired the lock."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context that successfully acquired the lock."
|
|
bitfld.long 0x0 1. "NS,Secure/non-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
wgroup.long ($2+0x4)++0x7
|
|
line.long 0x0 "RELEASE,IPC release"
|
|
hexmask.long.word 0x0 0.--15. 1. "INTR_RELEASE,Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC.."
|
|
line.long 0x4 "NOTIFY,IPC notification"
|
|
hexmask.long.word 0x4 0.--15. 1. "INTR_NOTIFY,This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1' but only for those IPC interrupt structures for which the.."
|
|
group.long ($2+0xC)++0x7
|
|
line.long 0x0 "DATA0,IPC data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,This field holds a 32-bit data element that is associated with the IPC structure."
|
|
line.long 0x4 "DATA1,IPC data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,This field holds a 32-bit data element that is associated with the IPC structure."
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "LOCK_STATUS,IPC lock status"
|
|
bitfld.long 0x0 31. "ACQUIRED,Specifies if the lock is acquired. This field is set to '1' if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero P NS PC and MS are not valid." "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier that successfully acquired the lock."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context that successfully acquired the lock."
|
|
bitfld.long 0x0 1. "NS,This field specifies the secure/non-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,This field specifies the user/privileged access control:" "0: user mode,1: privileged mode"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40230000
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40231000 ad:0x40231020 ad:0x40231040 ad:0x40231060 ad:0x40231080 ad:0x402310A0 ad:0x402310C0 ad:0x402310E0 ad:0x40231100 ad:0x40231120 ad:0x40231140 ad:0x40231160 ad:0x40231180 ad:0x402311A0 ad:0x402311C0 ad:0x402311E0)
|
|
tree "INTR_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
hexmask.long.word 0x0 16.--31. 1. "NOTIFY,These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause."
|
|
hexmask.long.word 0x0 0.--15. 1. "RELEASE,These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause."
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
hexmask.long.word 0x4 16.--31. 1. "NOTIFY,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
hexmask.long.word 0x4 0.--15. 1. "RELEASE,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
hexmask.long.word 0x8 16.--31. 1. "NOTIFY,Mask bit for corresponding field in the INTR register."
|
|
hexmask.long.word 0x8 0.--15. 1. "RELEASE,Mask bit for corresponding field in the INTR register."
|
|
rgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
hexmask.long.word 0x0 16.--31. 1. "NOTIFY,Logical and of corresponding INTR and INTR_MASK fields."
|
|
hexmask.long.word 0x0 0.--15. 1. "RELEASE,Logical and of corresponding request and mask bits."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40230000
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40221000 ad:0x40221020 ad:0x40221040 ad:0x40221060 ad:0x40221080 ad:0x402210A0 ad:0x402210C0 ad:0x402210E0 ad:0x40221100 ad:0x40221120 ad:0x40221140 ad:0x40221160 ad:0x40221180 ad:0x402211A0 ad:0x402211C0 ad:0x402211E0)
|
|
tree "INTR_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
hexmask.long.word 0x0 16.--31. 1. "NOTIFY,These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause."
|
|
hexmask.long.word 0x0 0.--15. 1. "RELEASE,These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause."
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
hexmask.long.word 0x4 16.--31. 1. "NOTIFY,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
hexmask.long.word 0x4 0.--15. 1. "RELEASE,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
hexmask.long.word 0x8 16.--31. 1. "NOTIFY,Mask bit for corresponding field in the INTR register."
|
|
hexmask.long.word 0x8 0.--15. 1. "RELEASE,Mask bit for corresponding field in the INTR register."
|
|
rgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
hexmask.long.word 0x0 16.--31. 1. "NOTIFY,Logical and of corresponding INTR and INTR_MASK fields."
|
|
hexmask.long.word 0x0 0.--15. 1. "RELEASE,Logical and of corresponding request and mask bits."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40230000
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40220000 ad:0x40220020 ad:0x40220040 ad:0x40220060 ad:0x40220080 ad:0x402200A0 ad:0x402200C0 ad:0x402200E0 ad:0x40220100 ad:0x40220120 ad:0x40220140 ad:0x40220160 ad:0x40220180 ad:0x402201A0 ad:0x402201C0 ad:0x402201E0)
|
|
tree "STRUCT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "ACQUIRE,IPC acquire"
|
|
bitfld.long 0x0 31. "SUCCESS,Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED):" "0: Not successfully acquired,1: Successfully acquired"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier that successfully acquired the lock."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context that successfully acquired the lock."
|
|
bitfld.long 0x0 1. "NS,Secure/non-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
wgroup.long ($2+0x4)++0x7
|
|
line.long 0x0 "RELEASE,IPC release"
|
|
hexmask.long.word 0x0 0.--15. 1. "INTR_RELEASE,Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC.."
|
|
line.long 0x4 "NOTIFY,IPC notification"
|
|
hexmask.long.word 0x4 0.--15. 1. "INTR_NOTIFY,This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1' but only for those IPC interrupt structures for which the.."
|
|
group.long ($2+0xC)++0x7
|
|
line.long 0x0 "DATA0,IPC data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,This field holds a 32-bit data element that is associated with the IPC structure."
|
|
line.long 0x4 "DATA1,IPC data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,This field holds a 32-bit data element that is associated with the IPC structure."
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "LOCK_STATUS,IPC lock status"
|
|
bitfld.long 0x0 31. "ACQUIRED,Specifies if the lock is acquired. This field is set to '1' if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero P NS PC and MS are not valid." "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier that successfully acquired the lock."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context that successfully acquired the lock."
|
|
bitfld.long 0x0 1. "NS,This field specifies the secure/non-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,This field specifies the user/privileged access control:" "0: user mode,1: privileged mode"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40230000
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40221000 ad:0x40221020 ad:0x40221040 ad:0x40221060 ad:0x40221080 ad:0x402210A0 ad:0x402210C0 ad:0x402210E0 ad:0x40221100 ad:0x40221120 ad:0x40221140 ad:0x40221160 ad:0x40221180 ad:0x402211A0 ad:0x402211C0 ad:0x402211E0)
|
|
tree "INTR_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
hexmask.long.word 0x0 16.--31. 1. "NOTIFY,These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause."
|
|
hexmask.long.word 0x0 0.--15. 1. "RELEASE,These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause."
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
hexmask.long.word 0x4 16.--31. 1. "NOTIFY,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
hexmask.long.word 0x4 0.--15. 1. "RELEASE,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
hexmask.long.word 0x8 16.--31. 1. "NOTIFY,Mask bit for corresponding field in the INTR register."
|
|
hexmask.long.word 0x8 0.--15. 1. "RELEASE,Mask bit for corresponding field in the INTR register."
|
|
rgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
hexmask.long.word 0x0 16.--31. 1. "NOTIFY,Logical and of corresponding INTR and INTR_MASK fields."
|
|
hexmask.long.word 0x0 0.--15. 1. "RELEASE,Logical and of corresponding request and mask bits."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40230000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40220000 ad:0x40220020 ad:0x40220040 ad:0x40220060 ad:0x40220080 ad:0x402200A0 ad:0x402200C0 ad:0x402200E0 ad:0x40220100 ad:0x40220120 ad:0x40220140 ad:0x40220160 ad:0x40220180 ad:0x402201A0 ad:0x402201C0 ad:0x402201E0)
|
|
tree "STRUCT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "ACQUIRE,IPC acquire"
|
|
bitfld.long 0x0 31. "SUCCESS,Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED):" "0: Not successfully acquired,1: Successfully acquired"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier that successfully acquired the lock."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context that successfully acquired the lock."
|
|
bitfld.long 0x0 1. "NS,Secure/non-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
wgroup.long ($2+0x4)++0x7
|
|
line.long 0x0 "RELEASE,IPC release"
|
|
hexmask.long.word 0x0 0.--15. 1. "INTR_RELEASE,Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC.."
|
|
line.long 0x4 "NOTIFY,IPC notification"
|
|
hexmask.long.word 0x4 0.--15. 1. "INTR_NOTIFY,This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1' but only for those IPC interrupt structures for which the.."
|
|
group.long ($2+0xC)++0x7
|
|
line.long 0x0 "DATA0,IPC data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,This field holds a 32-bit data element that is associated with the IPC structure."
|
|
line.long 0x4 "DATA1,IPC data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,This field holds a 32-bit data element that is associated with the IPC structure."
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "LOCK_STATUS,IPC lock status"
|
|
bitfld.long 0x0 31. "ACQUIRED,Specifies if the lock is acquired. This field is set to '1' if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero P NS PC and MS are not valid." "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier that successfully acquired the lock."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context that successfully acquired the lock."
|
|
bitfld.long 0x0 1. "NS,This field specifies the secure/non-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,This field specifies the user/privileged access control:" "0: user mode,1: privileged mode"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40230000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40221000 ad:0x40221020 ad:0x40221040 ad:0x40221060 ad:0x40221080 ad:0x402210A0 ad:0x402210C0 ad:0x402210E0 ad:0x40221100 ad:0x40221120 ad:0x40221140 ad:0x40221160 ad:0x40221180 ad:0x402211A0 ad:0x402211C0 ad:0x402211E0)
|
|
tree "INTR_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
hexmask.long.word 0x0 16.--31. 1. "NOTIFY,These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause."
|
|
hexmask.long.word 0x0 0.--15. 1. "RELEASE,These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause."
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
hexmask.long.word 0x4 16.--31. 1. "NOTIFY,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
hexmask.long.word 0x4 0.--15. 1. "RELEASE,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
hexmask.long.word 0x8 16.--31. 1. "NOTIFY,Mask bit for corresponding field in the INTR register."
|
|
hexmask.long.word 0x8 0.--15. 1. "RELEASE,Mask bit for corresponding field in the INTR register."
|
|
rgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
hexmask.long.word 0x0 16.--31. 1. "NOTIFY,Logical and of corresponding INTR and INTR_MASK fields."
|
|
hexmask.long.word 0x0 0.--15. 1. "RELEASE,Logical and of corresponding request and mask bits."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40230000
|
|
endif
|
|
tree.end
|
|
tree "LCD (LCD Controller Block)"
|
|
base ad:0x403B0000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ID,ID & Revision"
|
|
hexmask.long.word 0x0 16.--31. 1. "REVISION,the version number is 0x0001"
|
|
hexmask.long.word 0x0 0.--15. 1. "ID,the ID of LCD controller peripheral is 0xF0F0"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "DIVIDER,LCD Divider Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DEAD_DIV,Length of the dead time period in cycles. When set to zero no dead time period exists."
|
|
hexmask.long.word 0x0 0.--15. 1. "SUBFR_DIV,Input clock frequency divide value to generate the 1/4 sub-frame period. The sub-frame period is 4*(SUBFR_DIV+1) cycles long."
|
|
line.long 0x4 "CONTROL,LCD Configuration Register"
|
|
rbitfld.long 0x4 31. "LS_EN_STAT,LS enable status bit. This bit is a copy of LS_EN that is synchronized to the low speed clock domain and back to the system clock domain. Firmware can use this bit to observe whether LS_EN has taken effect in the low speed clock domain." "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "COM_NUM,The number of COM connections minus 2. So:"
|
|
newline
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
bitfld.long 0x4 7. "CLOCK_LS_SEL,Low speed (LS) generator clock source selection" "0: select clk_lf,1: select clk_mf"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
bitfld.long 0x4 7. "CLOCK_LS_SEL,Low speed (LS) generator clock source selection" "0: select clk_lf,1: select clk_mf"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 5.--6. "BIAS,PWM bias selection" "0: 1/2 Bias,1: 1/3 Bias,2: 1/4 Bias (not supported by LS generator),3: 1/5 Bias (not supported by LS generator)"
|
|
bitfld.long 0x4 4. "OP_MODE,Driving mode configuration" "0: PWM Mode,1: Digital Correlation Mode"
|
|
newline
|
|
bitfld.long 0x4 3. "TYPE,LCD driving waveform type configuration." "0: Type A - Each frame addresses each COM pin only..,1: Type B - Each frame addresses each COM pin twice.."
|
|
bitfld.long 0x4 2. "LCD_MODE,HS/LS Mode selection" "0: Select Low Speed (32kHz) Generator (Works in..,1: Select High Speed (system clock) Generator.."
|
|
newline
|
|
bitfld.long 0x4 1. "HS_EN,High speed (HS) generator enable" "0: disable,1: enable"
|
|
bitfld.long 0x4 0. "LS_EN,Low speed (LS) generator enable" "0: disable,1: enable"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x100)++0x3
|
|
line.long 0x0 "DATA0[$1],LCD Pin Data Registers"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb)."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x100)++0x3
|
|
line.long 0x0 "DATA0[$1],LCD Pin Data Registers"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb)."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x300)++0x3
|
|
line.long 0x0 "DATA2[$1],LCD Pin Data Registers"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb)."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x300)++0x3
|
|
line.long 0x0 "DATA2[$1],LCD Pin Data Registers"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb)."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x100)++0x3
|
|
line.long 0x0 "DATA0[$1],LCD Pin Data Registers"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb)."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??6*")||cpuis("CYS06??7*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x200)++0x3
|
|
line.long 0x0 "DATA1[$1],LCD Pin Data Registers"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb)."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x200)++0x3
|
|
line.long 0x0 "DATA1[$1],LCD Pin Data Registers"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb)."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x300)++0x3
|
|
line.long 0x0 "DATA2[$1],LCD Pin Data Registers"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb)."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??6*")||cpuis("CYS06??7*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x400)++0x3
|
|
line.long 0x0 "DATA3[$1],LCD Pin Data Registers"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb)."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x400)++0x3
|
|
line.long 0x0 "DATA3[$1],LCD Pin Data Registers"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb)."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x100)++0x3
|
|
line.long 0x0 "DATA0[$1],LCD Pin Data Registers"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb)."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x200)++0x3
|
|
line.long 0x0 "DATA1[$1],LCD Pin Data Registers"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb)."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x300)++0x3
|
|
line.long 0x0 "DATA2[$1],LCD Pin Data Registers"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb)."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x400)++0x3
|
|
line.long 0x0 "DATA3[$1],LCD Pin Data Registers"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb)."
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
tree "LPCOMP (Low Power Comparators)"
|
|
base ad:0x40350000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CONFIG,LPCOMP Configuration Register"
|
|
bitfld.long 0x0 31. "ENABLED,- 0: LPCOMP disabled (puts analog in power down opens all switches all clocks turned off)" "0: LPCOMP disabled,1: LPCOMP enabled"
|
|
bitfld.long 0x0 30. "LPREF_EN,Enable the local reference generator circuit to generate the local Vref and Ibias. Ibias current is an alternative to the reference current IREF generated by SRSS. This bit must be set for System Deep Sleep and System Hibernate operation." "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,LPCOMP Status Register"
|
|
bitfld.long 0x0 16. "OUT1,Current output value of the comparator 1." "0,1"
|
|
bitfld.long 0x0 0. "OUT0,Current output value of the comparator 0." "0,1"
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "INTR,LPCOMP Interrupt request register"
|
|
bitfld.long 0x0 1. "COMP1,Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit." "0,1"
|
|
bitfld.long 0x0 0. "COMP0,Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit." "0,1"
|
|
line.long 0x4 "INTR_SET,LPCOMP Interrupt set register"
|
|
bitfld.long 0x4 1. "COMP1,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "COMP0,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,LPCOMP Interrupt request mask"
|
|
bitfld.long 0x8 1. "COMP1_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "COMP0_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "INTR_MASKED,LPCOMP Interrupt request masked"
|
|
bitfld.long 0x0 1. "COMP1_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "COMP0_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CMP0_CTRL,Comparator 0 control Register"
|
|
bitfld.long 0x0 11. "DSI_LEVEL0,Synchronous comparator output (trigger):" "0: pulse,1: level"
|
|
bitfld.long 0x0 10. "DSI_BYPASS0,Asynchronous: bypass comparator output synchronization:" "0: synchronize,1: bypass"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "INTTYPE0,N/A" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
bitfld.long 0x0 5. "HYST0,Add hysteresis to the comparator" "0: Disable Hysteresis,1: Enable Hysteresis"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "MODE0,N/A" "0: Off,1: Ultra lowpower operating mode (uses less power <..,2: Low Power operating mode (uses more power <10uA..,3: Normal full speed power operating mode (uses.."
|
|
group.long 0x50++0x7
|
|
line.long 0x0 "CMP0_SW,Comparator 0 switch control"
|
|
bitfld.long 0x0 7. "CMP0_VN0,Comparator 0 negative terminal switch to local Vref (LPREF_EN must be set)" "0,1"
|
|
bitfld.long 0x0 6. "CMP0_BN0,Comparator 0 negative terminal switch to amuxbusB" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CMP0_AN0,Comparator 0 negative terminal switch to amuxbusA" "0,1"
|
|
bitfld.long 0x0 4. "CMP0_IN0,Comparator 0 negative terminal isolation switch to GPIO" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CMP0_BP0,Comparator 0 positive terminal switch to amuxbusB" "0,1"
|
|
bitfld.long 0x0 1. "CMP0_AP0,Comparator 0 positive terminal switch to amuxbusA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMP0_IP0,Comparator 0 positive terminal isolation switch to GPIO" "0,1"
|
|
line.long 0x4 "CMP0_SW_CLEAR,Comparator 0 switch control clear"
|
|
bitfld.long 0x4 7. "CMP0_VN0,see corresponding bit in CMP0_SW" "0,1"
|
|
bitfld.long 0x4 6. "CMP0_BN0,see corresponding bit in CMP0_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CMP0_AN0,see corresponding bit in CMP0_SW" "0,1"
|
|
bitfld.long 0x4 4. "CMP0_IN0,see corresponding bit in CMP0_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CMP0_BP0,see corresponding bit in CMP0_SW" "0,1"
|
|
bitfld.long 0x4 1. "CMP0_AP0,see corresponding bit in CMP0_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMP0_IP0,see corresponding bit in CMP0_SW" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "CMP1_CTRL,Comparator 1 control Register"
|
|
bitfld.long 0x0 11. "DSI_LEVEL1,Synchronous comparator output (trigger):" "0: pulse,1: level"
|
|
bitfld.long 0x0 10. "DSI_BYPASS1,Asynchronous: bypass comparator output synchronization:" "0: synchronize,1: bypass"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "INTTYPE1,N/A" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
bitfld.long 0x0 5. "HYST1,Add hysteresis to the comparator" "0: Disable Hysteresis,1: Enable Hysteresis"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "MODE1,N/A" "0: Off,1: Ultra lowpower operating mode (uses less power <..,2: Low Power operating mode (uses more power <10uA..,3: Normal full speed power operating mode (uses.."
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "CMP1_SW,Comparator 1 switch control"
|
|
bitfld.long 0x0 7. "CMP1_VN1,Comparator 1 negative terminal switch to local Vref (LPREF_EN must be set)" "0,1"
|
|
bitfld.long 0x0 6. "CMP1_BN1,Comparator 1 negative terminal switch to amuxbusB" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CMP1_AN1,Comparator 1 negative terminal switch to amuxbusA" "0,1"
|
|
bitfld.long 0x0 4. "CMP1_IN1,Comparator 1 negative terminal isolation switch to GPIO" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CMP1_BP1,Comparator 1 positive terminal switch to amuxbusB" "0,1"
|
|
bitfld.long 0x0 1. "CMP1_AP1,Comparator 1 positive terminal switch to amuxbusA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMP1_IP1,Comparator 1 positive terminal isolation switch to GPIO" "0,1"
|
|
line.long 0x4 "CMP1_SW_CLEAR,Comparator 1 switch control clear"
|
|
bitfld.long 0x4 7. "CMP1_VN1,see corresponding bit in CMP1_SW" "0,1"
|
|
bitfld.long 0x4 6. "CMP1_BN1,see corresponding bit in CMP1_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CMP1_AN1,see corresponding bit in CMP1_SW" "0,1"
|
|
bitfld.long 0x4 4. "CMP1_IN1,see corresponding bit in CMP1_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CMP1_BP1,see corresponding bit in CMP1_SW" "0,1"
|
|
bitfld.long 0x4 1. "CMP1_AP1,see corresponding bit in CMP1_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMP1_IP1,see corresponding bit in CMP1_SW" "0,1"
|
|
tree.end
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x411F0000
|
|
elif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
base ad:0x409F0000
|
|
endif
|
|
tree "PASS"
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "INTR_CAUSE,Interrupt cause register"
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
rbitfld.long 0x0 15. "FIFO3_INT,FIFO3 interrupt pending" "0,1"
|
|
rbitfld.long 0x0 14. "FIFO2_INT,FIFO2 interrupt pending" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 13. "FIFO1_INT,FIFO1 interrupt pending" "0,1"
|
|
rbitfld.long 0x0 12. "FIFO0_INT,FIFO0 interrupt pending" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 11. "SAR3_INT,SAR3 interrupt pending" "0,1"
|
|
rbitfld.long 0x0 10. "SAR2_INT,SAR2 interrupt pending" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 9. "SAR1_INT,SAR1 interrupt pending" "0,1"
|
|
rbitfld.long 0x0 8. "SAR0_INT,SAR0 interrupt pending" "0,1"
|
|
endif
|
|
rbitfld.long 0x0 7. "CTDAC3_INT,CTDAC3 interrupt pending" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 6. "CTDAC2_INT,CTDAC2 interrupt pending" "0,1"
|
|
rbitfld.long 0x0 5. "CTDAC1_INT,CTDAC1 interrupt pending" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "CTDAC0_INT,CTDAC0 interrupt pending" "0,1"
|
|
rbitfld.long 0x0 3. "CTB3_INT,CTB3 interrupt pending" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 2. "CTB2_INT,CTB2 interrupt pending" "0,1"
|
|
rbitfld.long 0x0 1. "CTB1_INT,CTB1 interrupt pending" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 0. "CTB0_INT,CTB0 interrupt pending" "0,1"
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
tree "TIMER (Programmable Analog Subsystem)"
|
|
base ad:0x409F0100
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRL,Timer trigger control register"
|
|
bitfld.long 0x0 31. "ENABLED,0=disabled 1=enabled" "0: disabled,1: enabled"
|
|
line.long 0x4 "CONFIG,Timer trigger configuration register"
|
|
bitfld.long 0x4 0.--1. "CLOCK_SEL,Select Clock source of the Timer" "0: Timer clocked from CLK_PERI,1: Timer clocked from CLK_DPSLP,2: Timer clocked from CLK_LF,3: N/A"
|
|
line.long 0x8 "PERIOD,Timer trigger period register"
|
|
hexmask.long.word 0x8 0.--15. 1. "PER_VAL,Actual timer period is PER_VAL+1 (1 to 65536)."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
tree "LPOSC (LPOSC configuration)"
|
|
base ad:0x409F0200
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRL,Low Power Oscillator control"
|
|
bitfld.long 0x0 31. "ENABLED,Master enable for LPOSC oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the LPOSC during System Deep Sleep (unless DEEPSLEEP_MODE is set)" "0,1"
|
|
line.long 0x4 "CONFIG,Low Power Oscillator configuration register"
|
|
bitfld.long 0x4 0. "DEEPSLEEP_MODE,LPOSC functionality while in System Deep Sleep" "0: LPOSC enabled by TIMER trigger,1: LPOSC always on in deepsleep"
|
|
line.long 0x8 "ADFT,Retention. Hidden"
|
|
bitfld.long 0x8 0.--1. "ADFT_SEL,ADFT selection for LPOSC." "0: DFT disabled,1: Measure Vdo,2: Measure Ibias_ptat,3: Measure Ibias_ctat"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
tree "AREF (AREF configuration)"
|
|
base ad:0x409F0E00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "AREF_CTRL,global AREF control"
|
|
bitfld.long 0x0 31. "ENABLED,Disable AREF" "0,1"
|
|
bitfld.long 0x0 30. "DEEPSLEEP_ON,- 0: AREF IP disabled/off during DeepSleep power mode" "0: AREF IP disabled/off during DeepSleep power mode,1: AREF IP remains enabled during DeepSleep power.."
|
|
newline
|
|
bitfld.long 0x0 28.--29. "DEEPSLEEP_MODE,AREF DeepSleep Operation Modes (only applies if DEEPSLEEP_ON = 1)" "0: All blocks 'OFF' in DeepSleep,1: IPTAT bias generator 'ON' in DeepSleep (used for..,2: IPTAT bias generator and outputs 'ON' in..,3: IPTAT VREF and IZTAT generators 'ON' in.."
|
|
bitfld.long 0x0 20.--21. "VREF_SEL,bandgap voltage select control" "0: Use 0.8V Vref from SRSS,1: Use locally generated Vref,2: Use externally supplied Vref (aref_ext_vref),?"
|
|
newline
|
|
bitfld.long 0x0 19. "CLOCK_PUMP_PERI_SEL,CTBm charge pump clock source select. This field has nothing to do with the AREF." "0: Use the dedicated pump clock from SRSS,1: Use one of the CLK_PERI dividers"
|
|
bitfld.long 0x0 16. "IZTAT_SEL,iztat current select control" "0: Use 250nA IZTAT from SRSS,1: Use locally generated 250nA"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CTB_IPTAT_REDIRECT,Re-direct the CTB IPTAT output current. This can be used to reduce amplifier bias glitches during power mode transitions (for PSoC4A/B DSAB backwards compatibility)."
|
|
bitfld.long 0x0 7. "CTB_IPTAT_SCALE,CTB IPTAT current scaler. This bit must be set in order to operate the CTB amplifiers in the lowest power mode. This bit is chip-wide (controls all CTB amplifiers)." "0: 1uA,1: 100nA"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "AREF_RMB,AREF control signals (RMB)." "0: normal VBG offset correction DAC operation,1: VBG offset correction DAC is enabled while VBG..,2: Manual enable of VBG offset correction DAC,?,?,?,?,?"
|
|
bitfld.long 0x0 2.--3. "AREF_BIAS_SCALE,BIAS Current Control for all AREF Amplifiers. (These are risk mitigation bits that should not be touched by the customer: the impact on IDDA/noise/startup still needs to be characterized)" "0: 125nA,1: 250nA,2: 375nA,3: 500nA"
|
|
newline
|
|
bitfld.long 0x0 0. "AREF_MODE,Control bit to trade off AREF settling and noise performance" "0: Nominal noise normal startup mode (meets normal..,1: High noise fast startup mode (meets fast mode.."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x411F0E00
|
|
elif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
base ad:0x409F0E00
|
|
endif
|
|
tree "AREF (AREF configuration)"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "AREF_CTRL,global AREF control"
|
|
bitfld.long 0x0 31. "ENABLED,Disable AREF" "0,1"
|
|
bitfld.long 0x0 30. "DEEPSLEEP_ON,- 0: AREF IP disabled/off during DeepSleep power mode" "0: AREF IP disabled/off during DeepSleep power mode,1: AREF IP remains enabled during DeepSleep power.."
|
|
newline
|
|
bitfld.long 0x0 28.--29. "DEEPSLEEP_MODE,AREF DeepSleep Operation Modes (only applies if DEEPSLEEP_ON = 1)" "0: All blocks 'OFF' in DeepSleep,1: IPTAT bias generator 'ON' in DeepSleep (used for..,2: IPTAT bias generator and outputs 'ON' in..,3: IPTAT VREF and IZTAT generators 'ON' in.."
|
|
bitfld.long 0x0 20.--21. "VREF_SEL,bandgap voltage select control" "0: Use 0.8V Vref from SRSS,1: Use locally generated Vref,2: Use externally supplied Vref (aref_ext_vref),?"
|
|
newline
|
|
bitfld.long 0x0 19. "CLOCK_PUMP_PERI_SEL,CTBm charge pump clock source select. This field has nothing to do with the AREF." "0: Use the dedicated pump clock from SRSS,1: Use one of the CLK_PERI dividers"
|
|
bitfld.long 0x0 16. "IZTAT_SEL,iztat current select control" "0: Use 250nA IZTAT from SRSS,1: Use locally generated 250nA"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CTB_IPTAT_REDIRECT,Re-direct the CTB IPTAT output current. This can be used to reduce amplifier bias glitches during power mode transitions (for PSoC4A/B DSAB backwards compatibility)."
|
|
bitfld.long 0x0 7. "CTB_IPTAT_SCALE,CTB IPTAT current scaler. This bit must be set in order to operate the CTB amplifiers in the lowest power mode. This bit is chip-wide (controls all CTB amplifiers)." "0: 1uA,1: 100nA"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "AREF_RMB,AREF control signals (RMB)." "0: normal VBG offset correction DAC operation,1: VBG offset correction DAC is enabled while VBG..,2: Manual enable of VBG offset correction DAC,?,?,?,?,?"
|
|
bitfld.long 0x0 2.--3. "AREF_BIAS_SCALE,BIAS Current Control for all AREF Amplifiers. (These are risk mitigation bits that should not be touched by the customer: the impact on IDDA/noise/startup still needs to be characterized)" "0: 125nA,1: 250nA,2: 375nA,3: 500nA"
|
|
newline
|
|
bitfld.long 0x0 0. "AREF_MODE,Control bit to trade off AREF settling and noise performance" "0: Nominal noise normal startup mode (meets normal..,1: High noise fast startup mode (meets fast mode.."
|
|
tree.end
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "DPSLP_CLOCK_SEL,Deepsleep clock select"
|
|
bitfld.long 0x0 4.--6. "DPSLP_CLOCK_DIV,CLK_DPSLP divider" "0: Transparent mode feed through selected clock..,1: Divide selected clock source by 2,2: Divide selected clock source by 4,3: Divide selected clock source by 8,4: Divide selected clock source by 16,5: N/A,6: N/A,7: N/A"
|
|
bitfld.long 0x0 0. "DPSLP_CLOCK_SEL,Select source for PASS DPSLP Clock" "0: CLK_DPSLP is set to CLK_LPOSC,1: CLK_DPSLP is set to CLK_MF"
|
|
line.long 0x4 "ANA_PWR_CFG,Analog power configuration"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DUTY_CYCLE_SAR_ACT_EN,Enable duty cycling the SAR resulting in power reduction. This feature works irrespective of the device power mode. To use this feature the SAR must be configured for deepsleep clocking (SAR_CLOCK_SEL.CLOCK_SEL must be set to.."
|
|
hexmask.long.byte 0x4 0.--7. 1. "PWR_UP_DELAY,Power up time for analog blocks. Fastest power up time is achieved with a setting of 0. Additional time can be added to allow for analog settling. The power up time is in CLK_DPSLP cycles. This field is only applicable when CLK_DPSLP is.."
|
|
endif
|
|
group.long 0xF00++0x1F
|
|
line.long 0x0 "VREF_TRIM0,VREF Trim bits"
|
|
hexmask.long.byte 0x0 0.--7. 1. "VREF_ABS_TRIM,N/A"
|
|
line.long 0x4 "VREF_TRIM1,VREF Trim bits"
|
|
hexmask.long.byte 0x4 0.--7. 1. "VREF_TEMPCO_TRIM,N/A"
|
|
line.long 0x8 "VREF_TRIM2,VREF Trim bits"
|
|
hexmask.long.byte 0x8 0.--7. 1. "VREF_CURV_TRIM,N/A"
|
|
line.long 0xC "VREF_TRIM3,VREF Trim bits"
|
|
hexmask.long.byte 0xC 0.--3. 1. "VREF_ATTEN_TRIM,Obsolete"
|
|
line.long 0x10 "IZTAT_TRIM0,IZTAT Trim bits"
|
|
hexmask.long.byte 0x10 0.--7. 1. "IZTAT_ABS_TRIM,N/A"
|
|
line.long 0x14 "IZTAT_TRIM1,IZTAT Trim bits"
|
|
hexmask.long.byte 0x14 0.--7. 1. "IZTAT_TC_TRIM,IZTAT temperature correction trim (RMB)"
|
|
line.long 0x18 "IPTAT_TRIM0,IPTAT Trim bits"
|
|
hexmask.long.byte 0x18 4.--7. 1. "IPTAT_CTBM_TRIM,CTMB PTAT Current Trim"
|
|
hexmask.long.byte 0x18 0.--3. 1. "IPTAT_CORE_TRIM,IPTAT trim"
|
|
line.long 0x1C "ICTAT_TRIM0,ICTAT Trim bits"
|
|
hexmask.long.byte 0x1C 0.--3. 1. "ICTAT_TRIM,ICTAT trim"
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "CTBM_CLOCK_SEL[$1],Clock select for CTBm"
|
|
bitfld.long 0x0 0. "PUMP_CLOCK_SEL,Select source for CTBm Pump Clock." "0: CTBm pump clock set by..,1: CTBm pump clock sourced from CLK_DPSLP When.."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "SAR_DPSLP_CTRL[$1],Deepsleep control for SARv3"
|
|
bitfld.long 0x0 31. "ENABLED,enable for SAR deepsleep operation. SAR_CLOCK_SEL.CLOCK_SEL must be set to 1 for this field to affect SAR operation." "0: SAR deeepsleep operation disabled,1: SAR deepsleep operation enabled"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "SAR_CLOCK_SEL[$1],Clock select for SARv3"
|
|
bitfld.long 0x0 30. "CLOCK_SEL,SAR clock select" "0: - 0: legacy: SAR clock source is CLK_PERI (SAR..,1: - 1: SAR clock source is CLK_DPSLP (SAR can be.."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x50)++0x3
|
|
line.long 0x0 "SAR_TR_SCAN_CNT_STATUS[$1],SAR trigger scan control status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SCAN_CNT_STATUS,A read from this register returns the current sample count (possible values are 1 through SCAN_TR_SCAN_CNT.SCAN_CNT+1). This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1."
|
|
repeat.end
|
|
group.long 0x60++0x13
|
|
line.long 0x0 "SAR_TR_SCAN_CNT,SAR trigger scan control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SCAN_CNT,SAR trigger sample counter. This field determines the number of samples a SAR will take when triggered. The number of samples is SCAN_COUNT+1."
|
|
line.long 0x4 "SAR_OVR_CTRL,SAR HW trigger override"
|
|
hexmask.long.byte 0x4 8.--11. 1. "EOS_INTR_SCAN_CNT_SEL,SAR EOS interrupt source select (one bit per SAR). This feature is not available for FW or Continuous triggering."
|
|
hexmask.long.byte 0x4 4.--7. 1. "TR_SCAN_CNT_SEL,SAR trigger sample select (one bit per SAR)."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "HW_TR_TIMER_SEL,SAR hardware trigger source select (one bit per SAR). SAR must be configured for hardware triggering (SAR.SAMPLE_CTRL.DSI_TRIGGER_EN must be set to 1)."
|
|
line.long 0x8 "SAR_SIMULT_CTRL,SAR simultaneous trigger control"
|
|
bitfld.long 0x8 21. "SIMULT_EOS_INTR_SCAN_CNT_SEL,Simultaneous SAR EOS interrupt source select. This feature is not available for FW or Continuous triggering." "0,1"
|
|
bitfld.long 0x8 20. "SIMULT_TR_SCAN_CNT_SEL,Simultaneous trigger sample select" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "SIMULT_HW_SYNC_TR,- 0: bypass clock domain synchronization of the Simult trigger signal." "0: bypass clock domain synchronization of the..,1: synchronize the Simult trigger signal to the SAR.."
|
|
bitfld.long 0x8 18. "SIMULT_HW_TR_LEVEL,- 0: trigger signal is a pulse input a positive edge detected on the trigger signal triggers a new scan." "0: trigger signal is a pulse input,1: trigger signal is a level input"
|
|
newline
|
|
bitfld.long 0x8 8. "SIMULT_HW_TR_TIMER_SEL,SAR hardware trigger source select" "0,1"
|
|
bitfld.long 0x8 4.--5. "SIMULT_HW_TR_SRC,Source for Simult Hardware trigger" "0: SAR 0 HW Trigger Input,1: SAR 1 HW Trigger Input,2: SAR 2 HW Trigger Input,3: SAR 3 HW Trigger Input"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "SIMULT_HW_TR_EN,SAR simultaneous hardware triggering enable (one bit per SAR)"
|
|
line.long 0xC "SAR_SIMULT_FW_START_CTRL,SAR simultaneous start control"
|
|
hexmask.long.byte 0xC 16.--19. 1. "CONTINUOUS,This field is used to configure two or more SARs for continuous operation."
|
|
hexmask.long.byte 0xC 0.--3. 1. "FW_TRIGGER,This field is used to simultaneously FW trigger two or more SARs."
|
|
line.long 0x10 "SAR_TR_OUT_CTRL,SAR trigger out control"
|
|
bitfld.long 0x10 3. "SAR3_TR_OUT_SEL,SAR3 Trigger Out Source Select" "0: sar output trigger is set by..,1: sar output trigger is set by.."
|
|
bitfld.long 0x10 2. "SAR2_TR_OUT_SEL,SAR2 Trigger Out Source Select" "0: sar output trigger is set by..,1: sar output trigger is set by.."
|
|
newline
|
|
bitfld.long 0x10 1. "SAR1_TR_OUT_SEL,SAR1 Trigger Out Source Select" "0: sar output trigger is set by..,1: sar output trigger is set by.."
|
|
bitfld.long 0x10 0. "SAR0_TR_OUT_SEL,SAR0 Trigger Out Source Select" "0: sar output trigger is set by..,1: sar output trigger is set by.."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 2. (list 0x0 0x1)(list ad:0x409F0300 ad:0x409F0400)
|
|
tree "FIFO[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "CTRL,FIFO control register"
|
|
bitfld.long 0x0 31. "ENABLED,Enable for SAR FIFO functionality. If CONFIG.CHAIN_TO_NXT is set the ENABLED bit of the NEXT FIFO is set when FIFO[0] is enabled." "0: FIFO disabled,1: FIFO enabled"
|
|
line.long 0x4 "CONFIG,FIFO configuration register"
|
|
bitfld.long 0x4 2. "TR_INTR_CLR_RD_EN,Enable for FIFO read clearing the FIFO level trigger and level interrupt." "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 1. "CHAIN_TO_NXT,Chain FIFO to next FIFO (i.e. chain FIFO0 and FIFO1)." "0: FIFO not chained,1: FIFO chained to next FIFO"
|
|
newline
|
|
bitfld.long 0x4 0. "CHAN_ID_EN,channel number (ID) enable bit" "0,1"
|
|
line.long 0x8 "CLEAR,FIFO clear register"
|
|
bitfld.long 0x8 0. "CLEAR,When firmware writes a 1 here it will trigger and clearing of the FIFO status registers (excluding interrupts) hardware clears this bit." "0,1"
|
|
line.long 0xC "LEVEL,FIFO level register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "LEVEL,FIFO level set. A trigger (and optional interrupt) event occurs when USED.USED = LEVEL+1. (Trigger generation is also affect by CONFIG.TR_CLR_RD_EN)."
|
|
rgroup.long ($2+0x10)++0xB
|
|
line.long 0x0 "USED,FIFO used register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "USED,Number of used/occupied entries in the FIFO."
|
|
line.long 0x4 "STATUS,FIFO status register"
|
|
hexmask.long.byte 0x4 8.--15. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data is written by the hardware."
|
|
hexmask.long.byte 0x4 0.--7. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data is read."
|
|
line.long 0x8 "RD_DATA,FIFO read data register"
|
|
hexmask.long.byte 0x8 16.--19. 1. "CHAN_ID,Channel number for a given SAR result. Requires CTRL.CHAN_ID_EN to be set."
|
|
hexmask.long.word 0x8 0.--15. 1. "RESULT,SAR result. Results from all enabled channels are stored in the buffer."
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "INTR,Interrupt register"
|
|
bitfld.long 0x0 2. "FIFO_UNDERFLOW,HW sets this field to '1' when reading from an empty FIFO. HW tracks underflow after FIFO is being written to and FIFO_CTRL.ENABLE==1." "0,1"
|
|
bitfld.long 0x0 1. "FIFO_OVERFLOW,HW sets this field to '1' when writing to a full FIFO (FIFO_USED.USED is '64')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FIFO_LEVEL,HW sets this field to '1' when USED.USED >= LEVEL.LEVEL+1" "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set register"
|
|
bitfld.long 0x4 2. "FIFO_UNDERFLOW,Write this field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 1. "FIFO_OVERFLOW,Write this field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FIFO_LEVEL,Write this field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 2. "FIFO_UNDERFLOW,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 1. "FIFO_OVERFLOW,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "FIFO_LEVEL,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x2C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x0 2. "FIFO_UNDERFLOW,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 1. "FIFO_OVERFLOW,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FIFO_LEVEL,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree "AREFV2 (AREF configuration)"
|
|
base ad:0x409F0E00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "AREF_CTRL,global AREF control"
|
|
bitfld.long 0x0 31. "ENABLED,- 0: AREF disabled" "0: AREF disabled,1: AREF enabled"
|
|
bitfld.long 0x0 30. "DEEPSLEEP_ON,- 0: AREF disabled/off during System Deep Sleep power mode" "0: AREF disabled/off during System Deep Sleep power..,1: AREF remains enabled during System Deep Sleep.."
|
|
newline
|
|
bitfld.long 0x0 28.--29. "DEEPSLEEP_MODE,AREF System Deep Sleep Operation Modes (only applies if DEEPSLEEP_ON = 1)" "0: All blocks 'OFF' in DeepSleep,1: IPTAT bias generator 'ON' in DeepSleep (used for..,2: IPTAT bias generator and outputs 'ON' in..,3: IPTAT VREF and IZTAT generators 'ON' in.."
|
|
bitfld.long 0x0 20.--21. "VREF_SEL,N/A" "0: Use 0.8V Vref from SRSS,1: Use locally generated Vref,2: Use externally supplied Vref (aref_ext_vref),?"
|
|
newline
|
|
bitfld.long 0x0 19. "CLOCK_PUMP_PERI_SEL,CTBm charge pump clock source select." "0: Use the dedicated pump clock from SRSS,1: Use one of the CLK_PERI dividers"
|
|
bitfld.long 0x0 16. "IZTAT_SEL,N/A" "0: Use 250nA IZTAT from SRSS,1: Use locally generated 250nA"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CTB_IPTAT_REDIRECT,Re-direct the CTBm IPTAT output current. This can be used to reduce amplifier bias glitches during power mode transitions."
|
|
bitfld.long 0x0 7. "CTB_IPTAT_SCALE,CTBm IPTAT current scaler. This bit must be set in order to operate the CTBm opamps in the lowest power mode. This bit is chip-wide (controls all CTBm opamps)." "0: 1uA,1: 100nA"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "AREF_RMB,N/A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2.--3. "AREF_BIAS_SCALE,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0. "AREF_MODE,N/A" "0: Nominal noise normal startup mode (meets normal..,1: High noise fast startup mode (meets fast mode.."
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x42A20000
|
|
elif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
base ad:0x40A00000
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??6*")||cpuis("CYS06??7*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
tree "PDM (Pulse Density Modulation)"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,Enables the PDM component:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 17. "STEP_SEL,Set fine gain step for smooth PGA or Soft-Mute attenuation transition." "0: 0,1: 0"
|
|
newline
|
|
bitfld.long 0x0 16. "SOFT_MUTE,Soft mute function to mute the volume smoothly" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PGA_L,Left channel PGA gain:"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PGA_R,Right channel PGA gain:"
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "CLOCK_CTL,Clock control"
|
|
hexmask.long.byte 0x0 16.--22. 1. "SINC_RATE,SINC Decimation Rate. For details see the data sheet provided by Archband."
|
|
hexmask.long.byte 0x0 8.--11. 1. "CKO_CLOCK_DIV,PDM CKO (FPDM_CKO) clock divider (3rd divider):"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "MCLKQ_CLOCK_DIV,MCLKQ divider (2nd divider)" "0: Divide by 1,1: Divide by 2 (no 50 percent duty cycle),2: Divide by 3 (no 50 percent duty cycle),3: Divide by 4 (no 50 percent duty cycle)"
|
|
bitfld.long 0x0 0.--1. "CLK_CLOCK_DIV,PDM CLK (FPDM_CLK) (1st divider):" "0: Divide by 1,1: Divide by 2 (no 50 percent duty cycle),2: Divide by 3 (no 50 percent duty cycle),3: Divide by 4 (no 50 percent duty cycle)"
|
|
line.long 0x4 "MODE_CTL,Mode control"
|
|
bitfld.long 0x4 28. "HPF_EN_N,Enable high pass filter (active low)" "0: Enabled,1: Disabled"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HPF_GAIN,Adjust high pass filter coefficients."
|
|
newline
|
|
bitfld.long 0x4 16.--18. "CKO_DELAY,Phase difference from the rising edge of internal sampler clock (CLK_IS) to that of PDM_CKO clock:" "0: CLK_IS is 3*PDM_CLK period early,1: CLK_IS is 2*PDM_CLK period early,2: CLK_IS is 1*PDM_CLK period early,3: CLK_IS is the same as PDM_CKO,4: CLK_IS is 1*PDM_CLK period late,5: CLK_IS is 2*PDM_CLK period late,6: CLK_IS is 3*PDM_CLK period late,7: CLK_IS is 4*PDM_CLK period late"
|
|
bitfld.long 0x4 8.--10. "S_CYCLES,Set time step for gain change during PGA or soft mute operation in" "0: 64steps,1: 96steps,2: 128steps,3: 160steps,4: 192steps,5: 256steps,6: 384steps,7: 512steps"
|
|
newline
|
|
bitfld.long 0x4 2. "SWAP_LR,Input data L/R channel swap:" "0: No Swap,1: Right/Left channel recording swap"
|
|
bitfld.long 0x4 0.--1. "PCM_CH_SET,Specifies PCM output channels as mono or stereo:" "0: Channel disabled,1: Mono left channel enable,2: Mono right channel enable,3: Stereo channel enable"
|
|
line.long 0x8 "DATA_CTL,Data control"
|
|
bitfld.long 0x8 8. "BIT_EXTENSION,When reception word length is shorter than the word length of RX_FIFO_RD extension mode of upper bit should be set." "0: Extended by '0',1: Extended by sign bit"
|
|
bitfld.long 0x8 0.--1. "WORD_LEN,PCM Word Length in number of bits:" "0: 16-bit,1: 18-bit,2: 20-bit,3: 24-bit"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CMD,Command"
|
|
bitfld.long 0x0 0. "STREAM_EN,Enable data streaming flow:" "0: Disabled,1: Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "TR_CTL,Trigger control"
|
|
bitfld.long 0x0 16. "RX_REQ_EN,Trigger output ('tr_pdm_rx_req') enable for requests of DMA transfer" "0: Disabled,1: Enabled"
|
|
group.long 0x300++0x3
|
|
line.long 0x0 "RX_FIFO_CTL,RX FIFO control"
|
|
bitfld.long 0x0 17. "FREEZE,When '1' hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer.This field is used only for debugging purposes." "0,1"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the RX FIFO has more entries than the number of this field a receiver trigger event is generated."
|
|
rgroup.long 0x304++0xB
|
|
line.long 0x0 "RX_FIFO_STATUS,RX FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,RX FIFO write pointer: RX FIFO location at which a new data frame is written by the hardware.This field is used only for debugging purposes."
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,RX FIFO read pointer: RX FIFO location from which a data frame is read by the host.This field is used only for debugging purposes."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "USED,Number of entries in the RX FIFO. The field value is in the range [0 255]. When this is zero the RX FIFO is empty."
|
|
line.long 0x4 "RX_FIFO_RD,RX FIFO read"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the RX FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation."
|
|
line.long 0x8 "RX_FIFO_RD_SILENT,RX FIFO silent read"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes."
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR,Interrupt register"
|
|
bitfld.long 0x0 22. "RX_UNDERFLOW,Attempt to read from an empty RX FIFO" "0,1"
|
|
bitfld.long 0x0 21. "RX_OVERFLOW,Attempt to write to a full RX FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RX_NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
bitfld.long 0x0 16. "RX_TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTL." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set register"
|
|
bitfld.long 0x4 22. "RX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 21. "RX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "RX_NOT_EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 16. "RX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 22. "RX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 21. "RX_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "RX_NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 16. "RX_TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x0 22. "RX_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 21. "RX_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RX_NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 16. "RX_TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x40010000
|
|
elif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
base ad:0x40000000
|
|
endif
|
|
tree "PERI (Peripheral Interconnect)"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 11. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA)(list ad:0x40010000 ad:0x40010040 ad:0x40010080 ad:0x400100C0 ad:0x40010100 ad:0x40010140 ad:0x40010180 ad:0x400101C0 ad:0x40010200 ad:0x40010240 ad:0x40010280)
|
|
tree "GR[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CLOCK_CTL,Clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT8_DIV,Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1 256]."
|
|
group.long ($2+0x20)++0x7
|
|
line.long 0x0 "SL_CTL,Slave control"
|
|
bitfld.long 0x0 15. "ENABLED_15,N/A" "0,1"
|
|
bitfld.long 0x0 14. "ENABLED_14,N/A" "0,1"
|
|
bitfld.long 0x0 13. "ENABLED_13,N/A" "0,1"
|
|
bitfld.long 0x0 12. "ENABLED_12,N/A" "0,1"
|
|
bitfld.long 0x0 11. "ENABLED_11,N/A" "0,1"
|
|
bitfld.long 0x0 10. "ENABLED_10,N/A" "0,1"
|
|
bitfld.long 0x0 9. "ENABLED_9,N/A" "0,1"
|
|
bitfld.long 0x0 8. "ENABLED_8,N/A" "0,1"
|
|
bitfld.long 0x0 7. "ENABLED_7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ENABLED_6,N/A" "0,1"
|
|
bitfld.long 0x0 5. "ENABLED_5,N/A" "0,1"
|
|
bitfld.long 0x0 4. "ENABLED_4,N/A" "0,1"
|
|
bitfld.long 0x0 3. "ENABLED_3,N/A" "0,1"
|
|
bitfld.long 0x0 2. "ENABLED_2,Peripheral group slave 2 enable. If the slave is disabled its clock is gated off (constant '0') and its resets are activated." "0,1"
|
|
bitfld.long 0x0 1. "ENABLED_1,Peripheral group slave 1 enable. If the slave is disabled its clock is gated off (constant '0') and its resets are activated." "0,1"
|
|
rbitfld.long 0x0 0. "ENABLED_0,Peripheral group slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled." "0,1"
|
|
line.long 0x4 "TIMEOUT_CTL,Timeout control"
|
|
hexmask.long.word 0x4 0.--15. 1. "TIMEOUT,This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection) the bus transfer is terminated with an AHB-Lite bus error and a fault is.."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
newline
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x800)++0x3
|
|
line.long 0x0 "DIV_8_CTL[$1],Divider control register (for 8.0 divider)"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1 256]. Note: this type of divider does NOT allow for a fractional division."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x900)++0x3
|
|
line.long 0x0 "DIV_16_CTL[$1],Divider control register (for 16.0 divider)"
|
|
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: this type of divider does NOT allow for a fractional division."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xA00)++0x3
|
|
line.long 0x0 "DIV_16_5_CTL[$1],Divider control register (for 16.5 divider)"
|
|
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: combined with fractional division this divider type allows for a division in the range [1 65 536 31/32] in 1/32 increments."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods."
|
|
newline
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
repeat 63. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xB00)++0x3
|
|
line.long 0x0 "DIV_24_5_CTL[$1],Divider control register (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1 16 777 216]. Note: combined with fractional division this divider type allows for a division in the range [1 16 777 216 31/32] in 1/32 increments."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods."
|
|
newline
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
repeat 128. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xC00)++0x3
|
|
line.long 0x0 "CLOCK_CTL[$1],Clock control register"
|
|
bitfld.long 0x0 6.--7. "TYPE_SEL,Specifies divider type:" "0: 8,1: 16,2: 16,3: 24"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL."
|
|
repeat.end
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "TR_CMD,Trigger command register"
|
|
bitfld.long 0x0 31. "ACTIVATE,SW sets this field to '1' by to activate (set to '1') a trigger as identified by TR_SEL and OUT_SEL for COUNT cycles. HW sets this field to '0' when the cycle counter is decremented to '0'. Note: a COUNT value of 255 is a special case and.." "0,1"
|
|
bitfld.long 0x0 30. "OUT_SEL,Specifies whether trigger activation is for a specific input or ouput trigger of the trigger multiplexer. Activation of a specific input trigger will result in activation of all output triggers that have the specific input trigger selected.." "0: TR_SEL selection and trigger activation is for..,1: TR_SEL selection and trigger activation is for.."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "COUNT,Amount of 'clk_peri' cycles a specific trigger is activated. During activation (ACTIVATE is '1') HW decrements this field to '0' using a cycle counter. During activation SW should not modify this register field. A value of 255 is a special case:.."
|
|
hexmask.long.byte 0x0 8.--11. 1. "GROUP_SEL,Specifies the trigger group."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TR_SEL,Specifies the activated trigger when ACTIVATE is '1'. OUT_SEL specifies whether the activated trigger is an input trigger or output trigger to the trigger multiplexer. During activation (ACTIVATE is '1') SW should not modify this register field."
|
|
repeat 15. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE)(list ad:0x40012000 ad:0x40012200 ad:0x40012400 ad:0x40012600 ad:0x40012800 ad:0x40012A00 ad:0x40012C00 ad:0x40012E00 ad:0x40013000 ad:0x40013200 ad:0x40013400 ad:0x40013600 ad:0x40013800 ad:0x40013A00 ad:0x40013C00)
|
|
tree "TR_GR[$1]"
|
|
base $2
|
|
repeat 128. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "TR_OUT_CTL[$1],Trigger control register"
|
|
bitfld.long 0x0 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger." "0: level sensitive,1: edge sensitive trigger"
|
|
bitfld.long 0x0 8. "TR_INV,Specifies if the output trigger is inverted." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TR_SEL,Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0.."
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40014000 ad:0x40014040 ad:0x40014080 ad:0x400140C0 ad:0x40014100 ad:0x40014140 ad:0x40014180 ad:0x400141C0 ad:0x40014200 ad:0x40014240 ad:0x40014280 ad:0x400142C0 ad:0x40014300 ad:0x40014340 ad:0x40014380 ad:0x400143C0)
|
|
tree "PPU_PR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ADDR0,PPU region address 0 (slave structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result some of the lesser significant address.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
line.long 0x4 "ATT0,PPU region attributes 0 (slave structure)"
|
|
bitfld.long 0x4 31. "ENABLED,Region enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 30. "PC_MATCH,This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:" "0: PC field participates in 'access evaluation',1: PC field participates in 'matching'"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
newline
|
|
hexmask.long.word 0x4 9.--23. 1. "PC_MASK_15_TO_1,This field specifies protection context identifier based access control."
|
|
rbitfld.long 0x4 8. "PC_MASK_0,This field specifies protection context identifier based access control for protection context '0'." "0,1"
|
|
bitfld.long 0x4 6. "NS,Non-secure:" "0: Secure,1: Non-secure"
|
|
newline
|
|
rbitfld.long 0x4 5. "PX,Privileged execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 4. "PW,Privileged write enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 3. "PR,Privileged read enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
rbitfld.long 0x4 2. "UX,User execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 1. "UW,User write enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 0. "UR,User read enable:" "0: Disabled,1: Enabled"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "ADDR1,PPU region address 1 (master structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,See corresponding field for PPU structure with programmable address."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,See corresponding field for PPU structure with programmable address."
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "ATT1,PPU region attributes 1 (master structure)"
|
|
bitfld.long 0x0 31. "ENABLED,See corresponding field for PPU structure with programmable address." "0,1"
|
|
bitfld.long 0x0 30. "PC_MATCH,See corresponding field for PPU structure with programmable address." "0,1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "REGION_SIZE,See corresponding field for PPU structure with programmable address."
|
|
newline
|
|
hexmask.long.word 0x0 9.--23. 1. "PC_MASK_15_TO_1,See corresponding field for PPU structure with programmable address."
|
|
rbitfld.long 0x0 8. "PC_MASK_0,See corresponding field for PPU structure with programmable address." "0,1"
|
|
bitfld.long 0x0 6. "NS,See corresponding field for PPU structure with programmable address." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 5. "PX,See corresponding field for PPU structure with programmable address." "0,1"
|
|
bitfld.long 0x0 4. "PW,See corresponding field for PPU structure with programmable address." "0,1"
|
|
rbitfld.long 0x0 3. "PR,See corresponding field for PPU structure with programmable address." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 2. "UX,See corresponding field for PPU structure with programmable address." "0,1"
|
|
bitfld.long 0x0 1. "UW,See corresponding field for PPU structure with programmable address." "0,1"
|
|
rbitfld.long 0x0 0. "UR,See corresponding field for PPU structure with programmable address." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 11. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA)(list ad:0x40015000 ad:0x40015040 ad:0x40015080 ad:0x400150C0 ad:0x40015100 ad:0x40015140 ad:0x40015180 ad:0x400151C0 ad:0x40015200 ad:0x40015240 ad:0x40015280)
|
|
tree "PPU_GR[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "ADDR0,PPU region address 0 (slave structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,See corresponding field for PPU structure with programmable address."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,See corresponding field for PPU structure with programmable address."
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "ATT0,PPU region attributes 0 (slave structure)"
|
|
bitfld.long 0x0 31. "ENABLED,See corresponding field for PPU structure with programmable address." "0,1"
|
|
bitfld.long 0x0 30. "PC_MATCH,See corresponding field for PPU structure with programmable address." "0,1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "REGION_SIZE,See corresponding field for PPU structure with programmable address."
|
|
hexmask.long.word 0x0 9.--23. 1. "PC_MASK_15_TO_1,See corresponding field for PPU structure with programmable address."
|
|
rbitfld.long 0x0 8. "PC_MASK_0,See corresponding field for PPU structure with programmable address." "0,1"
|
|
bitfld.long 0x0 6. "NS,See corresponding field for PPU structure with programmable address." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 5. "PX,See corresponding field for PPU structure with programmable address." "0,1"
|
|
bitfld.long 0x0 4. "PW,See corresponding field for PPU structure with programmable address." "0,1"
|
|
bitfld.long 0x0 3. "PR,See corresponding field for PPU structure with programmable address." "0,1"
|
|
rbitfld.long 0x0 2. "UX,See corresponding field for PPU structure with programmable address." "0,1"
|
|
bitfld.long 0x0 1. "UW,See corresponding field for PPU structure with programmable address." "0,1"
|
|
bitfld.long 0x0 0. "UR,See corresponding field for PPU structure with programmable address." "0,1"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "ADDR1,PPU region address 1 (master structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,See corresponding field for PPU structure with programmable address."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,See corresponding field for PPU structure with programmable address."
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "ATT1,PPU region attributes 1 (master structure)"
|
|
bitfld.long 0x0 31. "ENABLED,See corresponding field for PPU structure with programmable address." "0,1"
|
|
bitfld.long 0x0 30. "PC_MATCH,See corresponding field for PPU structure with programmable address." "0,1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "REGION_SIZE,See corresponding field for PPU structure with programmable address."
|
|
hexmask.long.word 0x0 9.--23. 1. "PC_MASK_15_TO_1,See corresponding field for PPU structure with programmable address."
|
|
rbitfld.long 0x0 8. "PC_MASK_0,See corresponding field for PPU structure with programmable address." "0,1"
|
|
bitfld.long 0x0 6. "NS,See corresponding field for PPU structure with programmable address." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 5. "PX,See corresponding field for PPU structure with programmable address." "0,1"
|
|
bitfld.long 0x0 4. "PW,See corresponding field for PPU structure with programmable address." "0,1"
|
|
rbitfld.long 0x0 3. "PR,See corresponding field for PPU structure with programmable address." "0,1"
|
|
rbitfld.long 0x0 2. "UX,See corresponding field for PPU structure with programmable address." "0,1"
|
|
bitfld.long 0x0 1. "UW,See corresponding field for PPU structure with programmable address." "0,1"
|
|
rbitfld.long 0x0 0. "UR,See corresponding field for PPU structure with programmable address." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "TIMEOUT_CTL,Timeout control"
|
|
hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection) the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and.."
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "TR_CMD,Trigger command"
|
|
bitfld.long 0x0 31. "ACTIVATE,SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles." "0,1"
|
|
bitfld.long 0x0 30. "OUT_SEL,Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger will result in activation of all output triggers that have the specific input trigger selected.." "0: TR_SEL selection and trigger activation is for..,1: TR_SEL selection and trigger activation is for.."
|
|
newline
|
|
bitfld.long 0x0 29. "TR_EDGE,Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger." "0: level sensitive,1: edge sensitive trigger"
|
|
hexmask.long.byte 0x0 8.--12. 1. "GROUP_SEL,Specifies the trigger group:"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TR_SEL,Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present the trigger activation has no effect."
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "TIMEOUT_CTL,Timeout control"
|
|
hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection) the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and.."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "TIMEOUT_CTL,Timeout control"
|
|
hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection) the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and.."
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "TR_CMD,Trigger command"
|
|
bitfld.long 0x0 31. "ACTIVATE,SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles." "0,1"
|
|
bitfld.long 0x0 30. "OUT_SEL,Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger will result in activation of all output triggers that have the specific input trigger selected.." "0: TR_SEL selection and trigger activation is for..,1: TR_SEL selection and trigger activation is for.."
|
|
newline
|
|
bitfld.long 0x0 29. "TR_EDGE,Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger." "0: level sensitive,1: edge sensitive trigger"
|
|
hexmask.long.byte 0x0 8.--12. 1. "GROUP_SEL,Specifies the trigger group:"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TR_SEL,Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present the trigger activation has no effect."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "TR_CMD,Trigger command"
|
|
bitfld.long 0x0 31. "ACTIVATE,SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles." "0,1"
|
|
bitfld.long 0x0 30. "OUT_SEL,Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger will result in activation of all output triggers that have the specific input trigger selected.." "0: TR_SEL selection and trigger activation is for..,1: TR_SEL selection and trigger activation is for.."
|
|
newline
|
|
bitfld.long 0x0 29. "TR_EDGE,Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger." "0: level sensitive,1: edge sensitive trigger"
|
|
hexmask.long.byte 0x0 8.--12. 1. "GROUP_SEL,Specifies the trigger group:"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TR_SEL,Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present the trigger activation has no effect."
|
|
endif
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "DIV_CMD,Divider command register"
|
|
bitfld.long 0x0 31. "ENABLE,Clock divider enable command (mutually exclusive with DISABLE). Typically SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled its integer and.." "0: Disable the divider using the DIV_CMD,1: Configure the divider's DIV_XXX_CTL register"
|
|
bitfld.long 0x0 30. "DISABLE,Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'." "0,1"
|
|
newline
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x0 24.--25. "PA_TYPE_SEL,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command:" "0: 8,1: 16,2: 16,3: 24"
|
|
hexmask.long.byte 0x0 16.--23. 1. "PA_DIV_SEL,(PA_TYPE_SEL PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other even when they are.."
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
bitfld.long 0x0 24.--25. "PA_TYPE_SEL,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command:" "0: 8,1: 16,2: 16,3: 24"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "PA_DIV_SEL,(PA_TYPE_SEL PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other even when they are.."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
bitfld.long 0x0 24.--25. "PA_TYPE_SEL,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command:" "0: 8,1: 16,2: 16,3: 24"
|
|
hexmask.long.byte 0x0 16.--23. 1. "PA_DIV_SEL,(PA_TYPE_SEL PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other even when they are.."
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
bitfld.long 0x0 14.--15. "PA_TYPE_SEL,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command:" "0: 8,1: 16,2: 16,3: 24"
|
|
hexmask.long.byte 0x0 8.--13. 1. "PA_DIV_SEL,(PA_TYPE_SEL PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other even when they are.."
|
|
newline
|
|
bitfld.long 0x0 6.--7. "TYPE_SEL,Specifies the divider type of the divider on which the command is performed:" "0: 8,1: 16,2: 16,3: 24"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DIV_SEL,(TYPE_SEL DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed."
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
bitfld.long 0x0 8.--9. "TYPE_SEL,Specifies the divider type of the divider on which the command is performed:" "0: 8,1: 16,2: 16,3: 24"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV_SEL,(TYPE_SEL DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
bitfld.long 0x0 8.--9. "TYPE_SEL,Specifies the divider type of the divider on which the command is performed:" "0: 8,1: 16,2: 16,3: 24"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV_SEL,(TYPE_SEL DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed."
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
bitfld.long 0x0 8.--9. "TYPE_SEL,Specifies the divider type of the divider on which the command is performed:" "0: 8,1: 16,2: 16,3: 24"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV_SEL,(TYPE_SEL DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed."
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xC00)++0x3
|
|
line.long 0x0 "CLOCK_CTL[$1],Clock control"
|
|
bitfld.long 0x0 8.--9. "TYPE_SEL,Specifies divider type:" "0: 8,1: 16,2: 16,3: 24"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1000)++0x3
|
|
line.long 0x0 "DIV_8_CTL[$1],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1 256]. Note: this type of divider does NOT allow for a fractional division."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1400)++0x3
|
|
line.long 0x0 "DIV_16_CTL[$1],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: this type of divider does NOT allow for a fractional division."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1800)++0x3
|
|
line.long 0x0 "DIV_16_5_CTL[$1],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: combined with fractional division this divider type allows for a division in the range [1 65 536 31/32] in 1/32 increments."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods."
|
|
newline
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 255. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1C00)++0x3
|
|
line.long 0x0 "DIV_24_5_CTL[$1],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1 16 777 216]. Note: combined with fractional division this divider type allows for a division in the range [1 16 777 216 31/32] in 1/32 increments."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods."
|
|
newline
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
group.long 0x2000++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,Enable error injection for PERI protection structure SRAM." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC checking:" "0: Disabled,1: Enabled"
|
|
hexmask.long.word 0x0 0.--10. 1. "WORD_ADDR,Specifies the word address where the parity is injected."
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 11. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA)(list ad:0x40004000 ad:0x40004020 ad:0x40004040 ad:0x40004060 ad:0x40004080 ad:0x400040A0 ad:0x400040C0 ad:0x400040E0 ad:0x40004100 ad:0x40004120 ad:0x40004140)
|
|
tree "GR[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CLOCK_CTL,Clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT8_DIV,Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1 256]."
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "SL_CTL,Slave control"
|
|
bitfld.long 0x0 31. "DISABLED_15,N/A" "0,1"
|
|
bitfld.long 0x0 30. "DISABLED_14,N/A" "0,1"
|
|
bitfld.long 0x0 29. "DISABLED_13,N/A" "0,1"
|
|
bitfld.long 0x0 28. "DISABLED_12,N/A" "0,1"
|
|
bitfld.long 0x0 27. "DISABLED_11,N/A" "0,1"
|
|
bitfld.long 0x0 26. "DISABLED_10,N/A" "0,1"
|
|
bitfld.long 0x0 25. "DISABLED_9,N/A" "0,1"
|
|
bitfld.long 0x0 24. "DISABLED_8,N/A" "0,1"
|
|
bitfld.long 0x0 23. "DISABLED_7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "DISABLED_6,N/A" "0,1"
|
|
bitfld.long 0x0 21. "DISABLED_5,N/A" "0,1"
|
|
bitfld.long 0x0 20. "DISABLED_4,N/A" "0,1"
|
|
bitfld.long 0x0 19. "DISABLED_3,N/A" "0,1"
|
|
bitfld.long 0x0 18. "DISABLED_2,N/A" "0,1"
|
|
bitfld.long 0x0 17. "DISABLED_1,N/A" "0,1"
|
|
bitfld.long 0x0 16. "DISABLED_0,Peripheral group slave 0 permanent disable. Setting this bit to 1 has the same effect as setting ENABLED_0 to 0. However once set to 1 this bit cannot be changed back to 0 anymore." "0,1"
|
|
bitfld.long 0x0 15. "ENABLED_15,N/A" "0,1"
|
|
bitfld.long 0x0 14. "ENABLED_14,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENABLED_13,N/A" "0,1"
|
|
bitfld.long 0x0 12. "ENABLED_12,N/A" "0,1"
|
|
bitfld.long 0x0 11. "ENABLED_11,N/A" "0,1"
|
|
bitfld.long 0x0 10. "ENABLED_10,N/A" "0,1"
|
|
bitfld.long 0x0 9. "ENABLED_9,N/A" "0,1"
|
|
bitfld.long 0x0 8. "ENABLED_8,N/A" "0,1"
|
|
bitfld.long 0x0 7. "ENABLED_7,N/A" "0,1"
|
|
bitfld.long 0x0 6. "ENABLED_6,N/A" "0,1"
|
|
bitfld.long 0x0 5. "ENABLED_5,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENABLED_4,N/A" "0,1"
|
|
bitfld.long 0x0 3. "ENABLED_3,N/A" "0,1"
|
|
bitfld.long 0x0 2. "ENABLED_2,N/A" "0,1"
|
|
bitfld.long 0x0 1. "ENABLED_1,Peripheral group slave 1 enable. If the slave is disabled its clock is gated off (constant '0') and its resets are activated." "0,1"
|
|
bitfld.long 0x0 0. "ENABLED_0,Peripheral group slave 0 enable. If the slave is disabled its clock is gated off (constant '0') and its resets are activated." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40008000 ad:0x40008400 ad:0x40008800 ad:0x40008C00 ad:0x40009000 ad:0x40009400 ad:0x40009800 ad:0x40009C00 ad:0x4000A000 ad:0x4000A400)
|
|
tree "TR_GR[$1]"
|
|
base $2
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "TR_CTL[$1],Trigger control register"
|
|
bitfld.long 0x0 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation." "0,1"
|
|
bitfld.long 0x0 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger." "0: level sensitive,1: edge sensitive trigger"
|
|
bitfld.long 0x0 8. "TR_INV,Specifies if the output trigger is inverted." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TR_SEL,Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0.."
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0x4000C000 ad:0x4000C400 ad:0x4000C800 ad:0x4000CC00 ad:0x4000D000 ad:0x4000D400 ad:0x4000D800)
|
|
tree "TR_1TO1_GR[$1]"
|
|
base $2
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "TR_CTL[$1],Trigger control register"
|
|
bitfld.long 0x0 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation." "0,1"
|
|
bitfld.long 0x0 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger." "0: level sensitive,1: edge sensitive trigger"
|
|
bitfld.long 0x0 8. "TR_INV,Specifies if the output trigger is inverted." "0,1"
|
|
bitfld.long 0x0 0. "TR_SEL,Specifies input trigger:" "0: constant signal level '0',1: input trigger"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xC00)++0x3
|
|
line.long 0x0 "CLOCK_CTL[$1],Clock control"
|
|
bitfld.long 0x0 8.--9. "TYPE_SEL,Specifies divider type:" "0: 8,1: 16,2: 16,3: 24"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1000)++0x3
|
|
line.long 0x0 "DIV_8_CTL[$1],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1 256]. Note: this type of divider does NOT allow for a fractional division."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1400)++0x3
|
|
line.long 0x0 "DIV_16_CTL[$1],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: this type of divider does NOT allow for a fractional division."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1800)++0x3
|
|
line.long 0x0 "DIV_16_5_CTL[$1],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: combined with fractional division this divider type allows for a division in the range [1 65 536 31/32] in 1/32 increments."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods."
|
|
newline
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 255. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1C00)++0x3
|
|
line.long 0x0 "DIV_24_5_CTL[$1],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1 16 777 216]. Note: combined with fractional division this divider type allows for a division in the range [1 16 777 216 31/32] in 1/32 increments."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods."
|
|
newline
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
group.long 0x2000++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,Enable error injection for PERI protection structure SRAM." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC checking:" "0: Disabled,1: Enabled"
|
|
hexmask.long.word 0x0 0.--10. 1. "WORD_ADDR,Specifies the word address where the parity is injected."
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40004000 ad:0x40004020 ad:0x40004040 ad:0x40004060 ad:0x40004080 ad:0x400040A0 ad:0x400040C0 ad:0x400040E0 ad:0x40004100 ad:0x40004120)
|
|
tree "GR[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CLOCK_CTL,Clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT8_DIV,Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1 256]."
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "SL_CTL,Slave control"
|
|
bitfld.long 0x0 31. "DISABLED_15,N/A" "0,1"
|
|
bitfld.long 0x0 30. "DISABLED_14,N/A" "0,1"
|
|
bitfld.long 0x0 29. "DISABLED_13,N/A" "0,1"
|
|
bitfld.long 0x0 28. "DISABLED_12,N/A" "0,1"
|
|
bitfld.long 0x0 27. "DISABLED_11,N/A" "0,1"
|
|
bitfld.long 0x0 26. "DISABLED_10,N/A" "0,1"
|
|
bitfld.long 0x0 25. "DISABLED_9,N/A" "0,1"
|
|
bitfld.long 0x0 24. "DISABLED_8,N/A" "0,1"
|
|
bitfld.long 0x0 23. "DISABLED_7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "DISABLED_6,N/A" "0,1"
|
|
bitfld.long 0x0 21. "DISABLED_5,N/A" "0,1"
|
|
bitfld.long 0x0 20. "DISABLED_4,N/A" "0,1"
|
|
bitfld.long 0x0 19. "DISABLED_3,N/A" "0,1"
|
|
bitfld.long 0x0 18. "DISABLED_2,N/A" "0,1"
|
|
bitfld.long 0x0 17. "DISABLED_1,N/A" "0,1"
|
|
bitfld.long 0x0 16. "DISABLED_0,Peripheral group slave 0 permanent disable. Setting this bit to 1 has the same effect as setting ENABLED_0 to 0. However once set to 1 this bit cannot be changed back to 0 anymore." "0,1"
|
|
bitfld.long 0x0 15. "ENABLED_15,N/A" "0,1"
|
|
bitfld.long 0x0 14. "ENABLED_14,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENABLED_13,N/A" "0,1"
|
|
bitfld.long 0x0 12. "ENABLED_12,N/A" "0,1"
|
|
bitfld.long 0x0 11. "ENABLED_11,N/A" "0,1"
|
|
bitfld.long 0x0 10. "ENABLED_10,N/A" "0,1"
|
|
bitfld.long 0x0 9. "ENABLED_9,N/A" "0,1"
|
|
bitfld.long 0x0 8. "ENABLED_8,N/A" "0,1"
|
|
bitfld.long 0x0 7. "ENABLED_7,N/A" "0,1"
|
|
bitfld.long 0x0 6. "ENABLED_6,N/A" "0,1"
|
|
bitfld.long 0x0 5. "ENABLED_5,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENABLED_4,N/A" "0,1"
|
|
bitfld.long 0x0 3. "ENABLED_3,N/A" "0,1"
|
|
bitfld.long 0x0 2. "ENABLED_2,N/A" "0,1"
|
|
bitfld.long 0x0 1. "ENABLED_1,Peripheral group slave 1 enable. If the slave is disabled its clock is gated off (constant '0') and its resets are activated." "0,1"
|
|
bitfld.long 0x0 0. "ENABLED_0,Peripheral group slave 0 enable. If the slave is disabled its clock is gated off (constant '0') and its resets are activated." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 11. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA)(list ad:0x40008000 ad:0x40008400 ad:0x40008800 ad:0x40008C00 ad:0x40009000 ad:0x40009400 ad:0x40009800 ad:0x40009C00 ad:0x4000A000 ad:0x4000A400 ad:0x4000A800)
|
|
tree "TR_GR[$1]"
|
|
base $2
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "TR_CTL[$1],Trigger control register"
|
|
bitfld.long 0x0 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation." "0,1"
|
|
bitfld.long 0x0 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger." "0: level sensitive,1: edge sensitive trigger"
|
|
bitfld.long 0x0 8. "TR_INV,Specifies if the output trigger is inverted." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TR_SEL,Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0.."
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x4000C000 ad:0x4000C400 ad:0x4000C800 ad:0x4000CC00 ad:0x4000D000 ad:0x4000D400 ad:0x4000D800 ad:0x4000DC00)
|
|
tree "TR_1TO1_GR[$1]"
|
|
base $2
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "TR_CTL[$1],Trigger control register"
|
|
bitfld.long 0x0 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation." "0,1"
|
|
bitfld.long 0x0 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger." "0: level sensitive,1: edge sensitive trigger"
|
|
bitfld.long 0x0 8. "TR_INV,Specifies if the output trigger is inverted." "0,1"
|
|
bitfld.long 0x0 0. "TR_SEL,Specifies input trigger:" "0: constant signal level '0',1: input trigger"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xC00)++0x3
|
|
line.long 0x0 "CLOCK_CTL[$1],Clock control"
|
|
bitfld.long 0x0 8.--9. "TYPE_SEL,Specifies divider type:" "0: 8,1: 16,2: 16,3: 24"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1000)++0x3
|
|
line.long 0x0 "DIV_8_CTL[$1],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1 256]. Note: this type of divider does NOT allow for a fractional division."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1400)++0x3
|
|
line.long 0x0 "DIV_16_CTL[$1],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: this type of divider does NOT allow for a fractional division."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1800)++0x3
|
|
line.long 0x0 "DIV_16_5_CTL[$1],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: combined with fractional division this divider type allows for a division in the range [1 65 536 31/32] in 1/32 increments."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods."
|
|
newline
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 255. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1C00)++0x3
|
|
line.long 0x0 "DIV_24_5_CTL[$1],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1 16 777 216]. Note: combined with fractional division this divider type allows for a division in the range [1 16 777 216 31/32] in 1/32 increments."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods."
|
|
newline
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
group.long 0x2000++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,Enable error injection for PERI protection structure SRAM." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC checking:" "0: Disabled,1: Enabled"
|
|
hexmask.long.word 0x0 0.--10. 1. "WORD_ADDR,Specifies the word address where the parity is injected."
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40004000 ad:0x40004020 ad:0x40004040 ad:0x40004060 ad:0x40004080 ad:0x400040A0 ad:0x400040C0 ad:0x400040E0 ad:0x40004100 ad:0x40004120)
|
|
tree "GR[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CLOCK_CTL,Clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT8_DIV,Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1 256]."
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "SL_CTL,Slave control"
|
|
bitfld.long 0x0 31. "DISABLED_15,N/A" "0,1"
|
|
bitfld.long 0x0 30. "DISABLED_14,N/A" "0,1"
|
|
bitfld.long 0x0 29. "DISABLED_13,N/A" "0,1"
|
|
bitfld.long 0x0 28. "DISABLED_12,N/A" "0,1"
|
|
bitfld.long 0x0 27. "DISABLED_11,N/A" "0,1"
|
|
bitfld.long 0x0 26. "DISABLED_10,N/A" "0,1"
|
|
bitfld.long 0x0 25. "DISABLED_9,N/A" "0,1"
|
|
bitfld.long 0x0 24. "DISABLED_8,N/A" "0,1"
|
|
bitfld.long 0x0 23. "DISABLED_7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "DISABLED_6,N/A" "0,1"
|
|
bitfld.long 0x0 21. "DISABLED_5,N/A" "0,1"
|
|
bitfld.long 0x0 20. "DISABLED_4,N/A" "0,1"
|
|
bitfld.long 0x0 19. "DISABLED_3,N/A" "0,1"
|
|
bitfld.long 0x0 18. "DISABLED_2,N/A" "0,1"
|
|
bitfld.long 0x0 17. "DISABLED_1,N/A" "0,1"
|
|
bitfld.long 0x0 16. "DISABLED_0,Peripheral group slave 0 permanent disable. Setting this bit to 1 has the same effect as setting ENABLED_0 to 0. However once set to 1 this bit cannot be changed back to 0 anymore." "0,1"
|
|
bitfld.long 0x0 15. "ENABLED_15,N/A" "0,1"
|
|
bitfld.long 0x0 14. "ENABLED_14,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENABLED_13,N/A" "0,1"
|
|
bitfld.long 0x0 12. "ENABLED_12,N/A" "0,1"
|
|
bitfld.long 0x0 11. "ENABLED_11,N/A" "0,1"
|
|
bitfld.long 0x0 10. "ENABLED_10,N/A" "0,1"
|
|
bitfld.long 0x0 9. "ENABLED_9,N/A" "0,1"
|
|
bitfld.long 0x0 8. "ENABLED_8,N/A" "0,1"
|
|
bitfld.long 0x0 7. "ENABLED_7,N/A" "0,1"
|
|
bitfld.long 0x0 6. "ENABLED_6,N/A" "0,1"
|
|
bitfld.long 0x0 5. "ENABLED_5,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENABLED_4,N/A" "0,1"
|
|
bitfld.long 0x0 3. "ENABLED_3,N/A" "0,1"
|
|
bitfld.long 0x0 2. "ENABLED_2,N/A" "0,1"
|
|
bitfld.long 0x0 1. "ENABLED_1,Peripheral group slave 1 enable. If the slave is disabled its clock is gated off (constant '0') and its resets are activated." "0,1"
|
|
bitfld.long 0x0 0. "ENABLED_0,Peripheral group slave 0 enable. If the slave is disabled its clock is gated off (constant '0') and its resets are activated." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 12. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB)(list ad:0x40008000 ad:0x40008400 ad:0x40008800 ad:0x40008C00 ad:0x40009000 ad:0x40009400 ad:0x40009800 ad:0x40009C00 ad:0x4000A000 ad:0x4000A400 ad:0x4000A800 ad:0x4000AC00)
|
|
tree "TR_GR[$1]"
|
|
base $2
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "TR_CTL[$1],Trigger control register"
|
|
bitfld.long 0x0 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation." "0,1"
|
|
bitfld.long 0x0 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger." "0: level sensitive,1: edge sensitive trigger"
|
|
bitfld.long 0x0 8. "TR_INV,Specifies if the output trigger is inverted." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TR_SEL,Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0.."
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 9. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8)(list ad:0x4000C000 ad:0x4000C400 ad:0x4000C800 ad:0x4000CC00 ad:0x4000D000 ad:0x4000D400 ad:0x4000D800 ad:0x4000DC00 ad:0x4000E000)
|
|
tree "TR_1TO1_GR[$1]"
|
|
base $2
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "TR_CTL[$1],Trigger control register"
|
|
bitfld.long 0x0 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation." "0,1"
|
|
bitfld.long 0x0 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger." "0: level sensitive,1: edge sensitive trigger"
|
|
bitfld.long 0x0 8. "TR_INV,Specifies if the output trigger is inverted." "0,1"
|
|
bitfld.long 0x0 0. "TR_SEL,Specifies input trigger:" "0: constant signal level '0',1: input trigger"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
endif
|
|
tree.end
|
|
sif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
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tree "PERI_MS (Peripheral Interconnect - Master Interface)"
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base ad:0x40010000
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|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40010800 ad:0x40010840 ad:0x40010880 ad:0x400108C0 ad:0x40010900 ad:0x40010940 ad:0x40010980 ad:0x400109C0 ad:0x40010A00 ad:0x40010A40 ad:0x40010A80 ad:0x40010AC0 ad:0x40010B00 ad:0x40010B40 ad:0x40010B80 ad:0x40010BC0)
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tree "PPU_FX[$1]"
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|
base $2
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rgroup.long ($2)++0x7
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line.long 0x0 "SL_ADDR,Slave region. base address"
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|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
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|
line.long 0x4 "SL_SIZE,Slave region. size"
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|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
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|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
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|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
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|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
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|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
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|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
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|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
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|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
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|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
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|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
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|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
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|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
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|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
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|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
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|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
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|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
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|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
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|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
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|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
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|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
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|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
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|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
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|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
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|
line.long 0x4 "SL_ATT1,Slave attributes 1"
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|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
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|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
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|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
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|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
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|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
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|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
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|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
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|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
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|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
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|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
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|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
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|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
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|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
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|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
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|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
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|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
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|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
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|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
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|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
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|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
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|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
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|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
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|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
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|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
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|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
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|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
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|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
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|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
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|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
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|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
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|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
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|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
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|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
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|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40010C00 ad:0x40010C40 ad:0x40010C80 ad:0x40010CC0 ad:0x40010D00 ad:0x40010D40 ad:0x40010D80 ad:0x40010DC0 ad:0x40010E00 ad:0x40010E40 ad:0x40010E80 ad:0x40010EC0 ad:0x40010F00 ad:0x40010F40 ad:0x40010F80 ad:0x40010FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F)(list ad:0x40011000 ad:0x40011040 ad:0x40011080 ad:0x400110C0 ad:0x40011100 ad:0x40011140 ad:0x40011180 ad:0x400111C0 ad:0x40011200 ad:0x40011240 ad:0x40011280 ad:0x400112C0 ad:0x40011300 ad:0x40011340 ad:0x40011380 ad:0x400113C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F)(list ad:0x40011400 ad:0x40011440 ad:0x40011480 ad:0x400114C0 ad:0x40011500 ad:0x40011540 ad:0x40011580 ad:0x400115C0 ad:0x40011600 ad:0x40011640 ad:0x40011680 ad:0x400116C0 ad:0x40011700 ad:0x40011740 ad:0x40011780 ad:0x400117C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F)(list ad:0x40011800 ad:0x40011840 ad:0x40011880 ad:0x400118C0 ad:0x40011900 ad:0x40011940 ad:0x40011980 ad:0x400119C0 ad:0x40011A00 ad:0x40011A40 ad:0x40011A80 ad:0x40011AC0 ad:0x40011B00 ad:0x40011B40 ad:0x40011B80 ad:0x40011BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F)(list ad:0x40011C00 ad:0x40011C40 ad:0x40011C80 ad:0x40011CC0 ad:0x40011D00 ad:0x40011D40 ad:0x40011D80 ad:0x40011DC0 ad:0x40011E00 ad:0x40011E40 ad:0x40011E80 ad:0x40011EC0 ad:0x40011F00 ad:0x40011F40 ad:0x40011F80 ad:0x40011FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F)(list ad:0x40012000 ad:0x40012040 ad:0x40012080 ad:0x400120C0 ad:0x40012100 ad:0x40012140 ad:0x40012180 ad:0x400121C0 ad:0x40012200 ad:0x40012240 ad:0x40012280 ad:0x400122C0 ad:0x40012300 ad:0x40012340 ad:0x40012380 ad:0x400123C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F)(list ad:0x40012400 ad:0x40012440 ad:0x40012480 ad:0x400124C0 ad:0x40012500 ad:0x40012540 ad:0x40012580 ad:0x400125C0 ad:0x40012600 ad:0x40012640 ad:0x40012680 ad:0x400126C0 ad:0x40012700 ad:0x40012740 ad:0x40012780 ad:0x400127C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F)(list ad:0x40012800 ad:0x40012840 ad:0x40012880 ad:0x400128C0 ad:0x40012900 ad:0x40012940 ad:0x40012980 ad:0x400129C0 ad:0x40012A00 ad:0x40012A40 ad:0x40012A80 ad:0x40012AC0 ad:0x40012B00 ad:0x40012B40 ad:0x40012B80 ad:0x40012BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F)(list ad:0x40012C00 ad:0x40012C40 ad:0x40012C80 ad:0x40012CC0 ad:0x40012D00 ad:0x40012D40 ad:0x40012D80 ad:0x40012DC0 ad:0x40012E00 ad:0x40012E40 ad:0x40012E80 ad:0x40012EC0 ad:0x40012F00 ad:0x40012F40 ad:0x40012F80 ad:0x40012FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF)(list ad:0x40013000 ad:0x40013040 ad:0x40013080 ad:0x400130C0 ad:0x40013100 ad:0x40013140 ad:0x40013180 ad:0x400131C0 ad:0x40013200 ad:0x40013240 ad:0x40013280 ad:0x400132C0 ad:0x40013300 ad:0x40013340 ad:0x40013380 ad:0x400133C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF)(list ad:0x40013400 ad:0x40013440 ad:0x40013480 ad:0x400134C0 ad:0x40013500 ad:0x40013540 ad:0x40013580 ad:0x400135C0 ad:0x40013600 ad:0x40013640 ad:0x40013680 ad:0x400136C0 ad:0x40013700 ad:0x40013740 ad:0x40013780 ad:0x400137C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF)(list ad:0x40013800 ad:0x40013840 ad:0x40013880 ad:0x400138C0 ad:0x40013900 ad:0x40013940 ad:0x40013980 ad:0x400139C0 ad:0x40013A00 ad:0x40013A40 ad:0x40013A80 ad:0x40013AC0 ad:0x40013B00 ad:0x40013B40 ad:0x40013B80 ad:0x40013BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40010000 ad:0x40010040 ad:0x40010080 ad:0x400100C0 ad:0x40010100 ad:0x40010140 ad:0x40010180 ad:0x400101C0)
|
|
tree "PPU_PR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF)(list ad:0x40013C00 ad:0x40013C40 ad:0x40013C80 ad:0x40013CC0 ad:0x40013D00 ad:0x40013D40 ad:0x40013D80 ad:0x40013DC0 ad:0x40013E00 ad:0x40013E40 ad:0x40013E80 ad:0x40013EC0 ad:0x40013F00 ad:0x40013F40 ad:0x40013F80 ad:0x40013FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 6. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5)(list ad:0x40014000 ad:0x40014040 ad:0x40014080 ad:0x400140C0 ad:0x40014100 ad:0x40014140)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40010000 ad:0x40010040 ad:0x40010080 ad:0x400100C0 ad:0x40010100 ad:0x40010140 ad:0x40010180 ad:0x400101C0)
|
|
tree "PPU_PR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 13. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC)(list ad:0x40013C00 ad:0x40013C40 ad:0x40013C80 ad:0x40013CC0 ad:0x40013D00 ad:0x40013D40 ad:0x40013D80 ad:0x40013DC0 ad:0x40013E00 ad:0x40013E40 ad:0x40013E80 ad:0x40013EC0 ad:0x40013F00)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40010000 ad:0x40010040 ad:0x40010080 ad:0x400100C0 ad:0x40010100 ad:0x40010140 ad:0x40010180 ad:0x400101C0)
|
|
tree "PPU_PR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF)(list ad:0x40013C00 ad:0x40013C40 ad:0x40013C80 ad:0x40013CC0 ad:0x40013D00 ad:0x40013D40 ad:0x40013D80 ad:0x40013DC0 ad:0x40013E00 ad:0x40013E40 ad:0x40013E80 ad:0x40013EC0 ad:0x40013F00 ad:0x40013F40 ad:0x40013F80 ad:0x40013FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 3. (list 0xE0 0xE1 0xE2)(list ad:0x40014000 ad:0x40014040 ad:0x40014080)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "?,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0: Secure,1: Non-secure"
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40010000
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??6*")||cpuis("CYS06??7*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
tree "PROFILE (Energy Profiler IP)"
|
|
base ad:0x402D0000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Profile control"
|
|
bitfld.long 0x0 31. "ENABLED,Enables the profiling block:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "WIN_MODE,Specifies the profiling time window mode:" "0: Start / stop mode,1: Enable mode"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Profile status"
|
|
bitfld.long 0x0 0. "WIN_ACTIVE,Indicates if the profiling time window is active." "0: Not active,1: Active"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CMD,Profile command"
|
|
bitfld.long 0x0 8. "CLR_ALL_CNT,Counter clear. When written with '1' all profiling counter registers are cleared to 0x00." "0,1"
|
|
bitfld.long 0x0 1. "STOP_TR,Software stop trigger for the profiling time window. When written with '1' the profiling time window is stopped." "0,1"
|
|
bitfld.long 0x0 0. "START_TR,Software start trigger for the profiling time window. When written with '1' the profiling time window is started." "0,1"
|
|
group.long 0x7C0++0xB
|
|
line.long 0x0 "INTR,Profile interrupt"
|
|
hexmask.long 0x0 0.--31. 1. "CNT_OVFLW,This interrupt cause field is activated (HW sets the field to '1') when an profiling counter overflow (from 0xFFFFFFFF to 0x00000000) is captured. There is one bit per profling counter."
|
|
line.long 0x4 "INTR_SET,Profile interrupt set"
|
|
hexmask.long 0x4 0.--31. 1. "CNT_OVFLW,SW writes a '1' to a bit of this field to set the corresponding bit in the INTR register."
|
|
line.long 0x8 "INTR_MASK,Profile interrupt mask"
|
|
hexmask.long 0x8 0.--31. 1. "CNT_OVFLW,Mask bit for corresponding field in the INTR register."
|
|
rgroup.long 0x7CC++0x3
|
|
line.long 0x0 "INTR_MASKED,Profile interrupt masked"
|
|
hexmask.long 0x0 0.--31. 1. "CNT_OVFLW,Logical and of corresponding INTR and INTR_MASK fields."
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x402D0800 ad:0x402D0810 ad:0x402D0820 ad:0x402D0830 ad:0x402D0840 ad:0x402D0850 ad:0x402D0860 ad:0x402D0870)
|
|
tree "CNT_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Profile counter configuration"
|
|
bitfld.long 0x0 31. "ENABLED,Enables the profiling counter:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x0 16.--22. 1. "MON_SEL,This field specifies the montior input signal to be observed by the profiling counter."
|
|
bitfld.long 0x0 4.--6. "REF_CLK_SEL,This field specifies the reference clock used for a counting time base when counting durations. Has no effect when CTL.CNT_DURATION=0." "0: Timer clock (divided or undivided high frequency..,1: IMO - Internal Main Oscillator,2: ECO - External-Crystal Oscillator,3: Low frequency clock (ILO WCO or ALTLF).,4: High frequuency clock ('clk_hfx').,5: Peripheral clock ('clk_peri').,6: N/A,7: N/A"
|
|
bitfld.long 0x0 0. "CNT_DURATION,This field specifies if events (edges) or a duration of the monitor signal is counted." "0: Events are monitored,1: A duration is monitored"
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "CNT,Profile counter value"
|
|
hexmask.long 0x0 0.--31. 1. "CNT,This field shows / specifies the actual value of the profiling counter. It allows reading as well as writing the profiling counter."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x402D0000
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x402D0800 ad:0x402D0810 ad:0x402D0820 ad:0x402D0830 ad:0x402D0840 ad:0x402D0850 ad:0x402D0860 ad:0x402D0870)
|
|
tree "CNT_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Profile counter configuration"
|
|
bitfld.long 0x0 31. "ENABLED,Enables the profiling counter:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x0 16.--22. 1. "MON_SEL,This field specifies the montior input signal to be observed by the profiling counter."
|
|
bitfld.long 0x0 4.--6. "REF_CLK_SEL,This field specifies the reference clock used for a counting time base when counting durations. Has no effect when CTL.CNT_DURATION=0." "0: Timer clock (divided or undivided high frequency..,1: IMO - Internal Main Oscillator,2: ECO - External-Crystal Oscillator,3: Low frequency clock (ILO WCO or ALTLF).,4: High frequuency clock ('clk_hfx').,5: Peripheral clock ('clk_peri').,6: N/A,7: N/A"
|
|
bitfld.long 0x0 0. "CNT_DURATION,This field specifies if events (edges) or a duration of the monitor signal is counted." "0: Events are monitored,1: A duration is monitored"
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "CNT,Profile counter value"
|
|
hexmask.long 0x0 0.--31. 1. "CNT,This field shows / specifies the actual value of the profiling counter. It allows reading as well as writing the profiling counter."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x402D0000
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x40240000
|
|
elif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
base ad:0x40230000
|
|
endif
|
|
tree "PROT (Protection)"
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
tree "SMPU (SMPU)"
|
|
base ad:0x40230000
|
|
group.long 0x0++0x3F
|
|
line.long 0x0 "MS0_CTL,Master 0 protection context control"
|
|
hexmask.long.word 0x0 17.--31. 1. "PC_MASK_15_TO_1,Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1':"
|
|
rbitfld.long 0x0 16. "PC_MASK_0,Protection context mask for protection context '0'. This field is a constant '0':" "0: MPU MS_CTL,?"
|
|
bitfld.long 0x0 8.--9. "PRIO,Device wide bus arbitration priority setting ('0': highest priority '3': lowest priority)." "0: highest priority,?,?,3: lowest priority"
|
|
bitfld.long 0x0 1. "NS,Security setting ('0': secure mode; '1': non-secure mode)." "0: secure mode,1: non-secure mode"
|
|
newline
|
|
bitfld.long 0x0 0. "P,Privileged setting ('0': user mode; '1': privileged mode)." "0: user mode,1: privileged mode"
|
|
line.long 0x4 "MS1_CTL,Master 1 protection context control"
|
|
hexmask.long.word 0x4 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x4 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x4 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x4 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x8 "MS2_CTL,Master 2 protection context control"
|
|
hexmask.long.word 0x8 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x8 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x8 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x8 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0xC "MS3_CTL,Master 3 protection context control"
|
|
hexmask.long.word 0xC 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0xC 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0xC 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0xC 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x10 "MS4_CTL,Master 4 protection context control"
|
|
hexmask.long.word 0x10 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x10 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x10 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x10 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x14 "MS5_CTL,Master 5 protection context control"
|
|
hexmask.long.word 0x14 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x14 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x14 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x14 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x18 "MS6_CTL,Master 6 protection context control"
|
|
hexmask.long.word 0x18 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x18 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x18 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x18 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x1C "MS7_CTL,Master 7 protection context control"
|
|
hexmask.long.word 0x1C 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x1C 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x1C 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x1C 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x20 "MS8_CTL,Master 8 protection context control"
|
|
hexmask.long.word 0x20 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x20 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x20 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x20 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x24 "MS9_CTL,Master 9 protection context control"
|
|
hexmask.long.word 0x24 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x24 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x24 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x24 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x28 "MS10_CTL,Master 10 protection context control"
|
|
hexmask.long.word 0x28 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x28 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x28 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x28 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x28 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x2C "MS11_CTL,Master 11 protection context control"
|
|
hexmask.long.word 0x2C 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x2C 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x2C 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x2C 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x30 "MS12_CTL,Master 12 protection context control"
|
|
hexmask.long.word 0x30 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x30 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x30 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x30 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x30 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x34 "MS13_CTL,Master 13 protection context control"
|
|
hexmask.long.word 0x34 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x34 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x34 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x34 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x34 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x38 "MS14_CTL,Master 14 protection context control"
|
|
hexmask.long.word 0x38 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x38 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x38 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x38 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x38 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x3C "MS15_CTL,Master 15 protection context control"
|
|
hexmask.long.word 0x3C 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x3C 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x3C 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x3C 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x3C 0. "P,See MS0_CTL.P." "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40232000 ad:0x40232040 ad:0x40232080 ad:0x402320C0 ad:0x40232100 ad:0x40232140 ad:0x40232180 ad:0x402321C0 ad:0x40232200 ad:0x40232240 ad:0x40232280 ad:0x402322C0 ad:0x40232300 ad:0x40232340 ad:0x40232380 ad:0x402323C0)
|
|
tree "SMPU_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ADDR0,SMPU region address 0 (slave structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result some of the lesser significant address bits of.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
line.long 0x4 "ATT0,SMPU region attributes 0 (slave structure)"
|
|
bitfld.long 0x4 31. "ENABLED,Region enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 30. "PC_MATCH,This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:" "0: PC field participates in 'access evaluation',1: PC field participates in 'matching'"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
newline
|
|
hexmask.long.word 0x4 9.--23. 1. "PC_MASK_15_TO_1,This field specifies protection context identifier based access control."
|
|
rbitfld.long 0x4 8. "PC_MASK_0,This field specifies protection context identifier based access control for protection context '0'." "0,1"
|
|
bitfld.long 0x4 6. "NS,Non-secure:" "0: Secure,1: Non-secure"
|
|
newline
|
|
bitfld.long 0x4 5. "PX,Privileged execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 4. "PW,Privileged write enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 3. "PR,Privileged read enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x4 2. "UX,User execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 1. "UW,User write enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 0. "UR,User read enable:" "0: Disabled,1: Enabled"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "ADDR1,SMPU region address 1 (master structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "ATT1,SMPU region attributes 1 (master structure)"
|
|
bitfld.long 0x0 31. "ENABLED,Region enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 30. "PC_MATCH,This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:" "0: PC field participates in 'access evaluation',1: PC field participates in 'matching'"
|
|
hexmask.long.byte 0x0 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
newline
|
|
hexmask.long.word 0x0 9.--23. 1. "PC_MASK_15_TO_1,This field specifies protection context identifier based access control."
|
|
rbitfld.long 0x0 8. "PC_MASK_0,This field specifies protection context identifier based access control for protection context '0'." "0,1"
|
|
bitfld.long 0x0 6. "NS,Non-secure:" "0: Secure,1: Non-secure"
|
|
newline
|
|
rbitfld.long 0x0 5. "PX,Privileged execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 4. "PW,Privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 3. "PR,Privileged read enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
rbitfld.long 0x0 2. "UX,User execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 1. "UW,User write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "UR,User read enable:" "0: Disabled,1: Enabled"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
tree "SMPU (SMPU)"
|
|
base ad:0x40230000
|
|
group.long 0x0++0x3F
|
|
line.long 0x0 "MS0_CTL,Master 0 protection context control"
|
|
hexmask.long.word 0x0 17.--31. 1. "PC_MASK_15_TO_1,Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1':"
|
|
rbitfld.long 0x0 16. "PC_MASK_0,Protection context mask for protection context '0'. This field is a constant '0':" "0: MPU MS_CTL,?"
|
|
bitfld.long 0x0 8.--9. "PRIO,Device wide bus arbitration priority setting ('0': highest priority '3': lowest priority)." "0: highest priority,?,?,3: lowest priority"
|
|
bitfld.long 0x0 1. "NS,Security setting ('0': secure mode; '1': non-secure mode)." "0: secure mode,1: non-secure mode"
|
|
newline
|
|
bitfld.long 0x0 0. "P,Privileged setting ('0': user mode; '1': privileged mode)." "0: user mode,1: privileged mode"
|
|
line.long 0x4 "MS1_CTL,Master 1 protection context control"
|
|
hexmask.long.word 0x4 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x4 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x4 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x4 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x8 "MS2_CTL,Master 2 protection context control"
|
|
hexmask.long.word 0x8 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x8 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x8 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x8 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0xC "MS3_CTL,Master 3 protection context control"
|
|
hexmask.long.word 0xC 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0xC 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0xC 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0xC 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x10 "MS4_CTL,Master 4 protection context control"
|
|
hexmask.long.word 0x10 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x10 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x10 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x10 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x14 "MS5_CTL,Master 5 protection context control"
|
|
hexmask.long.word 0x14 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x14 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x14 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x14 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x18 "MS6_CTL,Master 6 protection context control"
|
|
hexmask.long.word 0x18 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x18 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x18 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x18 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x1C "MS7_CTL,Master 7 protection context control"
|
|
hexmask.long.word 0x1C 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x1C 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x1C 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x1C 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x20 "MS8_CTL,Master 8 protection context control"
|
|
hexmask.long.word 0x20 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x20 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x20 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x20 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x24 "MS9_CTL,Master 9 protection context control"
|
|
hexmask.long.word 0x24 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x24 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x24 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x24 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x28 "MS10_CTL,Master 10 protection context control"
|
|
hexmask.long.word 0x28 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x28 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x28 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x28 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x28 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x2C "MS11_CTL,Master 11 protection context control"
|
|
hexmask.long.word 0x2C 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x2C 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x2C 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x2C 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x30 "MS12_CTL,Master 12 protection context control"
|
|
hexmask.long.word 0x30 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x30 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x30 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x30 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x30 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x34 "MS13_CTL,Master 13 protection context control"
|
|
hexmask.long.word 0x34 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x34 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x34 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x34 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x34 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x38 "MS14_CTL,Master 14 protection context control"
|
|
hexmask.long.word 0x38 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x38 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x38 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x38 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x38 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x3C "MS15_CTL,Master 15 protection context control"
|
|
hexmask.long.word 0x3C 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x3C 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x3C 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x3C 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x3C 0. "P,See MS0_CTL.P." "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40232000 ad:0x40232040 ad:0x40232080 ad:0x402320C0 ad:0x40232100 ad:0x40232140 ad:0x40232180 ad:0x402321C0 ad:0x40232200 ad:0x40232240 ad:0x40232280 ad:0x402322C0 ad:0x40232300 ad:0x40232340 ad:0x40232380 ad:0x402323C0)
|
|
tree "SMPU_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ADDR0,SMPU region address 0 (slave structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result some of the lesser significant address bits of.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
line.long 0x4 "ATT0,SMPU region attributes 0 (slave structure)"
|
|
bitfld.long 0x4 31. "ENABLED,Region enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 30. "PC_MATCH,This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:" "0: PC field participates in 'access evaluation',1: PC field participates in 'matching'"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
newline
|
|
hexmask.long.word 0x4 9.--23. 1. "PC_MASK_15_TO_1,This field specifies protection context identifier based access control."
|
|
rbitfld.long 0x4 8. "PC_MASK_0,This field specifies protection context identifier based access control for protection context '0'." "0,1"
|
|
bitfld.long 0x4 6. "NS,Non-secure:" "0: Secure,1: Non-secure"
|
|
newline
|
|
bitfld.long 0x4 5. "PX,Privileged execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 4. "PW,Privileged write enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 3. "PR,Privileged read enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x4 2. "UX,User execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 1. "UW,User write enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 0. "UR,User read enable:" "0: Disabled,1: Enabled"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "ADDR1,SMPU region address 1 (master structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "ATT1,SMPU region attributes 1 (master structure)"
|
|
bitfld.long 0x0 31. "ENABLED,Region enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 30. "PC_MATCH,This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:" "0: PC field participates in 'access evaluation',1: PC field participates in 'matching'"
|
|
hexmask.long.byte 0x0 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
newline
|
|
hexmask.long.word 0x0 9.--23. 1. "PC_MASK_15_TO_1,This field specifies protection context identifier based access control."
|
|
rbitfld.long 0x0 8. "PC_MASK_0,This field specifies protection context identifier based access control for protection context '0'." "0,1"
|
|
bitfld.long 0x0 6. "NS,Non-secure:" "0: Secure,1: Non-secure"
|
|
newline
|
|
rbitfld.long 0x0 5. "PX,Privileged execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 4. "PW,Privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 3. "PR,Privileged read enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
rbitfld.long 0x0 2. "UX,User execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 1. "UW,User write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "UR,User read enable:" "0: Disabled,1: Enabled"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x40240000
|
|
elif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
base ad:0x40230000
|
|
endif
|
|
tree "SMPU (SMPU)"
|
|
group.long 0x0++0x3F
|
|
line.long 0x0 "MS0_CTL,Master 0 protection context control"
|
|
hexmask.long.word 0x0 17.--31. 1. "PC_MASK_15_TO_1,Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1':"
|
|
rbitfld.long 0x0 16. "PC_MASK_0,Protection context mask for protection context '0'. This field is a constant '0':" "0: MPU MS_CTL,?"
|
|
bitfld.long 0x0 8.--9. "PRIO,Device wide bus arbitration priority setting ('0': highest priority '3': lowest priority)." "0: highest priority,?,?,3: lowest priority"
|
|
bitfld.long 0x0 1. "NS,Security setting ('0': secure mode; '1': non-secure mode)." "0: secure mode,1: non-secure mode"
|
|
newline
|
|
bitfld.long 0x0 0. "P,Privileged setting ('0': user mode; '1': privileged mode)." "0: user mode,1: privileged mode"
|
|
line.long 0x4 "MS1_CTL,Master 1 protection context control"
|
|
hexmask.long.word 0x4 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x4 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x4 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x4 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x8 "MS2_CTL,Master 2 protection context control"
|
|
hexmask.long.word 0x8 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x8 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x8 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x8 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0xC "MS3_CTL,Master 3 protection context control"
|
|
hexmask.long.word 0xC 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0xC 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0xC 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0xC 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x10 "MS4_CTL,Master 4 protection context control"
|
|
hexmask.long.word 0x10 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x10 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x10 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x10 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x14 "MS5_CTL,Master 5 protection context control"
|
|
hexmask.long.word 0x14 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x14 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x14 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x14 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x18 "MS6_CTL,Master 6 protection context control"
|
|
hexmask.long.word 0x18 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x18 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x18 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x18 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x1C "MS7_CTL,Master 7 protection context control"
|
|
hexmask.long.word 0x1C 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x1C 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x1C 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x1C 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x20 "MS8_CTL,Master 8 protection context control"
|
|
hexmask.long.word 0x20 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x20 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x20 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x20 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x24 "MS9_CTL,Master 9 protection context control"
|
|
hexmask.long.word 0x24 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x24 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x24 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x24 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x28 "MS10_CTL,Master 10 protection context control"
|
|
hexmask.long.word 0x28 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x28 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x28 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x28 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x28 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x2C "MS11_CTL,Master 11 protection context control"
|
|
hexmask.long.word 0x2C 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x2C 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x2C 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x2C 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x30 "MS12_CTL,Master 12 protection context control"
|
|
hexmask.long.word 0x30 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x30 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x30 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x30 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x30 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x34 "MS13_CTL,Master 13 protection context control"
|
|
hexmask.long.word 0x34 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x34 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x34 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x34 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x34 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x38 "MS14_CTL,Master 14 protection context control"
|
|
hexmask.long.word 0x38 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x38 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x38 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x38 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x38 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x3C "MS15_CTL,Master 15 protection context control"
|
|
hexmask.long.word 0x3C 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x3C 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x3C 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x3C 1. "NS,See MS0_CTL.NS." "0,1"
|
|
newline
|
|
bitfld.long 0x3C 0. "P,See MS0_CTL.P." "0,1"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40242000 ad:0x40242040 ad:0x40242080 ad:0x402420C0 ad:0x40242100 ad:0x40242140 ad:0x40242180 ad:0x402421C0 ad:0x40242200 ad:0x40242240 ad:0x40242280 ad:0x402422C0 ad:0x40242300 ad:0x40242340 ad:0x40242380 ad:0x402423C0)
|
|
tree "SMPU_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ADDR0,SMPU region address 0 (slave structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result some of the lesser significant address bits of.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
line.long 0x4 "ATT0,SMPU region attributes 0 (slave structure)"
|
|
bitfld.long 0x4 31. "ENABLED,Region enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 30. "PC_MATCH,This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:" "0: PC field participates in 'access evaluation',1: PC field participates in 'matching'"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
newline
|
|
hexmask.long.word 0x4 9.--23. 1. "PC_MASK_15_TO_1,This field specifies protection context identifier based access control."
|
|
rbitfld.long 0x4 8. "PC_MASK_0,This field specifies protection context identifier based access control for protection context '0'." "0,1"
|
|
bitfld.long 0x4 6. "NS,Non-secure:" "0: Secure,1: Non-secure"
|
|
newline
|
|
bitfld.long 0x4 5. "PX,Privileged execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 4. "PW,Privileged write enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 3. "PR,Privileged read enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x4 2. "UX,User execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 1. "UW,User write enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 0. "UR,User read enable:" "0: Disabled,1: Enabled"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "ADDR1,SMPU region address 1 (master structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "ATT1,SMPU region attributes 1 (master structure)"
|
|
bitfld.long 0x0 31. "ENABLED,Region enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 30. "PC_MATCH,This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:" "0: PC field participates in 'access evaluation',1: PC field participates in 'matching'"
|
|
hexmask.long.byte 0x0 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
newline
|
|
hexmask.long.word 0x0 9.--23. 1. "PC_MASK_15_TO_1,This field specifies protection context identifier based access control."
|
|
rbitfld.long 0x0 8. "PC_MASK_0,This field specifies protection context identifier based access control for protection context '0'." "0,1"
|
|
bitfld.long 0x0 6. "NS,Non-secure:" "0: Secure,1: Non-secure"
|
|
newline
|
|
rbitfld.long 0x0 5. "PX,Privileged execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 4. "PW,Privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 3. "PR,Privileged read enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
rbitfld.long 0x0 2. "UX,User execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 1. "UW,User write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "UR,User read enable:" "0: Disabled,1: Enabled"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40240000
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40232000 ad:0x40232040 ad:0x40232080 ad:0x402320C0 ad:0x40232100 ad:0x40232140 ad:0x40232180 ad:0x402321C0 ad:0x40232200 ad:0x40232240 ad:0x40232280 ad:0x402322C0 ad:0x40232300 ad:0x40232340 ad:0x40232380 ad:0x402323C0)
|
|
tree "SMPU_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ADDR0,SMPU region address 0 (slave structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result some of the lesser significant address bits of.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
line.long 0x4 "ATT0,SMPU region attributes 0 (slave structure)"
|
|
bitfld.long 0x4 31. "ENABLED,Region enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 30. "PC_MATCH,This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:" "0: PC field participates in 'access evaluation',1: PC field participates in 'matching'"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
newline
|
|
hexmask.long.word 0x4 9.--23. 1. "PC_MASK_15_TO_1,This field specifies protection context identifier based access control."
|
|
rbitfld.long 0x4 8. "PC_MASK_0,This field specifies protection context identifier based access control for protection context '0'." "0,1"
|
|
bitfld.long 0x4 6. "NS,Non-secure:" "0: Secure,1: Non-secure"
|
|
newline
|
|
bitfld.long 0x4 5. "PX,Privileged execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 4. "PW,Privileged write enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 3. "PR,Privileged read enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x4 2. "UX,User execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 1. "UW,User write enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 0. "UR,User read enable:" "0: Disabled,1: Enabled"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "ADDR1,SMPU region address 1 (master structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "ATT1,SMPU region attributes 1 (master structure)"
|
|
bitfld.long 0x0 31. "ENABLED,Region enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 30. "PC_MATCH,This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:" "0: PC field participates in 'access evaluation',1: PC field participates in 'matching'"
|
|
hexmask.long.byte 0x0 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
newline
|
|
hexmask.long.word 0x0 9.--23. 1. "PC_MASK_15_TO_1,This field specifies protection context identifier based access control."
|
|
rbitfld.long 0x0 8. "PC_MASK_0,This field specifies protection context identifier based access control for protection context '0'." "0,1"
|
|
bitfld.long 0x0 6. "NS,Non-secure:" "0: Secure,1: Non-secure"
|
|
newline
|
|
rbitfld.long 0x0 5. "PX,Privileged execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 4. "PW,Privileged write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 3. "PR,Privileged read enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
rbitfld.long 0x0 2. "UX,User execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 1. "UW,User write enable:" "0: Disabled,1: Enabled"
|
|
rbitfld.long 0x0 0. "UR,User read enable:" "0: Disabled,1: Enabled"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40240000
|
|
endif
|
|
tree.end
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40244000 ad:0x40244400 ad:0x40244800 ad:0x40244C00 ad:0x40245000 ad:0x40245400 ad:0x40245800 ad:0x40245C00 ad:0x40246000 ad:0x40246400 ad:0x40246800 ad:0x40246C00 ad:0x40247000 ad:0x40247400 ad:0x40247800 ad:0x40247C00)
|
|
tree "MPU[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "MS_CTL,Master control"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PC_SAVED,Saved protection context. Modifications to this field are constrained by the associated MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields."
|
|
hexmask.long.byte 0x0 0.--3. 1. "PC,N/A"
|
|
repeat 127. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "MS_CTL_READ_MIR[$1],Master control read mirror"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PC,Read-only mirror of MS_CTL.PC"
|
|
repeat.end
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x200 0x220 0x240 0x260 0x280 0x2A0 0x2C0 0x2E0)
|
|
tree "MPU_STRUCT[$1]"
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ADDR,MPU region address"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result some of the lesser significant address bits of.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
line.long 0x4 "ATT,MPU region attrributes"
|
|
bitfld.long 0x4 31. "ENABLED,Region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
bitfld.long 0x4 6. "NS,Non-secure:" "0: Secure,1: Non-secure"
|
|
bitfld.long 0x4 5. "PX,Privileged execute enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x4 4. "PW,Privileged write enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 3. "PR,Privileged read enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 2. "UX,User execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 1. "UW,User write enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x4 0. "UR,User read enable:" "0: Disabled,1: Enabled"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40240000
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40234000 ad:0x40234400 ad:0x40234800 ad:0x40234C00 ad:0x40235000 ad:0x40235400 ad:0x40235800 ad:0x40235C00 ad:0x40236000 ad:0x40236400 ad:0x40236800 ad:0x40236C00 ad:0x40237000 ad:0x40237400 ad:0x40237800 ad:0x40237C00)
|
|
tree "MPU[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "MS_CTL,Master control"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PC_SAVED,Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields."
|
|
hexmask.long.byte 0x0 0.--3. 1. "PC,Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition a write transfer with protection context '0' can change this field (protection.."
|
|
repeat 127. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "MS_CTL_READ_MIR[$1],Master control read mirror"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PC,Read-only mirror of MS_CTL.PC"
|
|
repeat.end
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x200 0x220 0x240 0x260 0x280 0x2A0 0x2C0 0x2E0)
|
|
tree "MPU_STRUCT[$1]"
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ADDR,MPU region address"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result some of the lesser significant address bits of.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
line.long 0x4 "ATT,MPU region attrributes"
|
|
bitfld.long 0x4 31. "ENABLED,Region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
bitfld.long 0x4 6. "NS,Non-secure:" "0: Secure,1: Non-secure"
|
|
bitfld.long 0x4 5. "PX,Privileged execute enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x4 4. "PW,Privileged write enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 3. "PR,Privileged read enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 2. "UX,User execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 1. "UW,User write enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x4 0. "UR,User read enable:" "0: Disabled,1: Enabled"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40240000
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40234000 ad:0x40234400 ad:0x40234800 ad:0x40234C00 ad:0x40235000 ad:0x40235400 ad:0x40235800 ad:0x40235C00 ad:0x40236000 ad:0x40236400 ad:0x40236800 ad:0x40236C00 ad:0x40237000 ad:0x40237400 ad:0x40237800 ad:0x40237C00)
|
|
tree "MPU[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "MS_CTL,Master control"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PC_SAVED,Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields."
|
|
hexmask.long.byte 0x0 0.--3. 1. "PC,Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition a write transfer with protection context '0' can change this field (protection.."
|
|
repeat 127. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "MS_CTL_READ_MIR[$1],Master control read mirror"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PC,Read-only mirror of MS_CTL.PC"
|
|
repeat.end
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x200 0x220 0x240 0x260 0x280 0x2A0 0x2C0 0x2E0)
|
|
tree "MPU_STRUCT[$1]"
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ADDR,MPU region address"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result some of the lesser significant address bits of.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
line.long 0x4 "ATT,MPU region attrributes"
|
|
bitfld.long 0x4 31. "ENABLED,Region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
bitfld.long 0x4 6. "NS,Non-secure:" "0: Secure,1: Non-secure"
|
|
bitfld.long 0x4 5. "PX,Privileged execute enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x4 4. "PW,Privileged write enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 3. "PR,Privileged read enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 2. "UX,User execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 1. "UW,User write enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x4 0. "UR,User read enable:" "0: Disabled,1: Enabled"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40240000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40234000 ad:0x40234400 ad:0x40234800 ad:0x40234C00 ad:0x40235000 ad:0x40235400 ad:0x40235800 ad:0x40235C00 ad:0x40236000 ad:0x40236400 ad:0x40236800 ad:0x40236C00 ad:0x40237000 ad:0x40237400 ad:0x40237800 ad:0x40237C00)
|
|
tree "MPU[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "MS_CTL,Master control"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PC_SAVED,Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields."
|
|
hexmask.long.byte 0x0 0.--3. 1. "PC,Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition a write transfer with protection context '0' can change this field (protection.."
|
|
repeat 127. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "MS_CTL_READ_MIR[$1],Master control read mirror"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PC,Read-only mirror of MS_CTL.PC"
|
|
repeat.end
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x200 0x220 0x240 0x260 0x280 0x2A0 0x2C0 0x2E0)
|
|
tree "MPU_STRUCT[$1]"
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ADDR,MPU region address"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result some of the lesser significant address bits of.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
line.long 0x4 "ATT,MPU region attrributes"
|
|
bitfld.long 0x4 31. "ENABLED,Region enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
bitfld.long 0x4 6. "NS,Non-secure:" "0: Secure,1: Non-secure"
|
|
bitfld.long 0x4 5. "PX,Privileged execute enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x4 4. "PW,Privileged write enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 3. "PR,Privileged read enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 2. "UX,User execute enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x4 1. "UW,User write enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x4 0. "UR,User read enable:" "0: Disabled,1: Enabled"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40240000
|
|
endif
|
|
tree.end
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x411D0000
|
|
elif (cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
base ad:0x409D0000
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??5*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??5*")||cpuis("CYS06??6*")||cpuis("CYS06??7*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
tree "SAR (SAR ADC with Sequencer)"
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTRL,Analog control register."
|
|
bitfld.long 0x0 31. "ENABLED,- 0: SAR disabled (put analog in power down and stop clocks) also can clear FW_TRIGGER on write." "0: SAR disabled,1: SAR IP enabled"
|
|
newline
|
|
bitfld.long 0x0 30. "SWITCH_DISABLE,Disable SAR sequencer from enabling routing switches" "0: Normal mode,1: Switches disabled"
|
|
newline
|
|
bitfld.long 0x0 29. "DSI_MODE,SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1)" "0: Normal mode,1: CHAN_EN and channel configurations in.."
|
|
newline
|
|
bitfld.long 0x0 28. "DSI_SYNC_CONFIG,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DEEPSLEEP_ON,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "COMP_PWR,Comparator power mode." "0: Power = 100 percent Use this for SAR Clock..,1: N/A,2: Power = 60 percent Use this for SAR Clock..,3: N/A,4: N/A,5: N/A,6: Power = 20 percent Use this for SAR Clock..,7: N/A"
|
|
newline
|
|
bitfld.long 0x0 21. "REFBUF_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "BOOSTPUMP_EN,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "SPARE,N/A"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "COMP_DLY,N/A" "0: 2.5ns delay use this for 2.5Msps,1: 4.0ns delay use this for 2.0Msps,2: 10ns delay use this for 1.5Msps,3: 12ns delay use this for 1.0Msps or less"
|
|
newline
|
|
bitfld.long 0x0 13. "SAR_HW_CTRL_NEGVREF,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "NEG_SEL,N/A" "0: NEG input of SARADC is connected to..,1: NEG input of SARADC is connected to VSSA in..,2: NEG input of SARADC is connected to P1 pin of..,3: NEG input of SARADC is connected to P3 pin of..,4: NEG input of SARADC is connected to P5 pin of..,5: NEG input of SARADC is connected to P7 pin of..,6: NEG input of SARADC is connected to an ACORE in..,7: NEG input of SARADC is shorted with VREF input.."
|
|
newline
|
|
bitfld.long 0x0 7. "VREF_BYP_CAP_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "VREF_SEL,N/A" "0: VREF0 from PRB (VREF buffer on),1: VREF1 from PRB (VREF buffer on),2: VREF2 from PRB (VREF buffer on),3: VREF from AROUTE (VREF buffer on),4: 1.024V from BandGap (VREF buffer on),5: External precision Vref direct from a pin (low..,6: Vdda/2 (VREF buffer on),7: Vdda."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "PWR_CTRL_VREF,VREF buffer low power mode." "0: full power (100 percent) (default) bypass cap..,1: 80 percent power,2: 60 percent power,3: 50 percent power,4: 40 percent power,5: 30 percent power,6: 20 percent power,7: 10 percent power"
|
|
line.long 0x4 "SAMPLE_CTRL,Sample control register."
|
|
bitfld.long 0x4 31. "EOS_DSI_OUT_EN,Enable to output EOS_INTR. When enabled each time EOS_INTR is set by the hardware also a trigger pulse is send on the tr_sar_out signal." "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TRIGGER_OUT_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "VALID_IGNORE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "VALID_SEL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24.--26. "VALID_SEL,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 23. "REPEAT_INVALID,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "UAB_SCAN_MODE,N/A" "0: Unscheduled UABs: one or more of the UABs..,1: Scheduled UABs: All UABs scanned by the SAR are.."
|
|
newline
|
|
bitfld.long 0x4 19. "DSI_SYNC_TRIGGER,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "DSI_TRIGGER_LEVEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "DSI_TRIGGER_EN,- 0: firmware trigger only: disable hardware trigger tr_sar_in." "0: firmware trigger only: disable hardware trigger..,1: enable hardware trigger tr_sar_in"
|
|
newline
|
|
bitfld.long 0x4 16. "CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "AVG_MODE,Averaging mode" "0: Accumulate and Dump (1st order accumulate and..,1: Interleaved: Each scan (trigger) one sample is.."
|
|
newline
|
|
bitfld.long 0x4 7. "AVG_SHIFT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "AVG_CNT,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "DIFFERENTIAL_SIGNED,N/A" "0: result data is unsigned (zero extended if needed),1: Default: result data is signed (sign extended if.."
|
|
newline
|
|
bitfld.long 0x4 2. "SINGLE_ENDED_SIGNED,N/A" "0: Default: result data is unsigned (zero extended..,1: result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x4 1. "LEFT_ALIGN,N/A" "0,1"
|
|
group.long 0x10++0x17
|
|
line.long 0x0 "SAMPLE_TIME01,Sample time specification ST0 and ST1"
|
|
hexmask.long.word 0x0 16.--25. 1. "SAMPLE_TIME1,Sample time1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "SAMPLE_TIME0,Sample time0 (aperture) in ADC clock cycles. Note that actual sample time is one clock less than specified here. The minimum sample time is 167ns which is 3.0 cycles (4 in this field) with an 18MHz clock. Minimum legal value in this.."
|
|
line.long 0x4 "SAMPLE_TIME23,Sample time specification ST2 and ST3"
|
|
hexmask.long.word 0x4 16.--25. 1. "SAMPLE_TIME3,Sample time3"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SAMPLE_TIME2,Sample time2"
|
|
line.long 0x8 "RANGE_THRES,Global range detect threshold register."
|
|
hexmask.long.word 0x8 16.--31. 1. "RANGE_HIGH,High threshold for range detect."
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "RANGE_LOW,Low threshold for range detect."
|
|
line.long 0xC "RANGE_COND,Global range detect mode register."
|
|
bitfld.long 0xC 30.--31. "RANGE_COND,Range condition select." "0: result < RANGE_LOW,1: RANGE_LOW <= result < RANGE_HIGH,2: RANGE_HIGH <= result,3: result < RANGE_LOW || RANGE_HIGH <= result"
|
|
line.long 0x10 "CHAN_EN,Enable bits for the channels"
|
|
hexmask.long.word 0x10 0.--15. 1. "CHAN_EN,Channel enable."
|
|
line.long 0x14 "START_CTRL,Start control register (firmware trigger)."
|
|
bitfld.long 0x14 0. "FW_TRIGGER,When firmware writes a 1 here it will trigger the next scan of enabled channels hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after.." "0,1"
|
|
rgroup.long 0x200++0xF
|
|
line.long 0x0 "CHAN_WORK_UPDATED,Channel working data register 'updated' bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "CHAN_WORK_UPDATED,If set the corresponding WORK register was updated i.e. was already sampled during the current scan and in case of Interleaved averaging reached the averaging count. If this bit is low then either the channel is not enabled or the.."
|
|
line.long 0x4 "CHAN_RESULT_UPDATED,Channel result data register 'updated' bits"
|
|
hexmask.long.word 0x4 0.--15. 1. "CHAN_RESULT_UPDATED,If set the corresponding RESULT register was updated i.e. was sampled during the previous scan and in case of Interleaved averaging reached the averaging count. If this bit is low then either the channel is not enabled or the.."
|
|
line.long 0x8 "CHAN_WORK_NEWVALUE,Channel working data register 'new value' bits"
|
|
hexmask.long.word 0x8 0.--15. 1. "CHAN_WORK_NEWVALUE,If set the corresponding WORK data received a new value i.e. was already sampled during the current scan and data was valid."
|
|
line.long 0xC "CHAN_RESULT_NEWVALUE,Channel result data register 'new value' bits"
|
|
hexmask.long.word 0xC 0.--15. 1. "CHAN_RESULT_NEWVALUE,If set the corresponding RESULT data received a new value i.e. was sampled during the last scan and data was valid."
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "INTR,Interrupt request register."
|
|
bitfld.long 0x0 7. "INJ_COLLISION_INTR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INJ_RANGE_INTR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "INJ_SATURATE_INTR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "INJ_EOC_INTR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DSI_COLLISION_INTR,This interrupt is set when a hardware trigger signal is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the hardware trigger has been completed i.e. not when the preceding scan with which.." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "FW_COLLISION_INTR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OVERFLOW_INTR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EOS_INTR,N/A" "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x4 7. "INJ_COLLISION_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "INJ_RANGE_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "INJ_SATURATE_SET,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "INJ_EOC_SET,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "DSI_COLLISION_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "FW_COLLISION_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OVERFLOW_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EOS_SET,N/A" "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register."
|
|
bitfld.long 0x8 7. "INJ_COLLISION_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "INJ_RANGE_MASK,N/A" "0,1"
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|
newline
|
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bitfld.long 0x8 5. "INJ_SATURATE_MASK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "INJ_EOC_MASK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x8 3. "DSI_COLLISION_MASK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "FW_COLLISION_MASK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "OVERFLOW_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "EOS_MASK,N/A" "0,1"
|
|
rgroup.long 0x21C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 7. "INJ_COLLISION_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INJ_RANGE_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "INJ_SATURATE_MASKED,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "INJ_EOC_MASKED,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "DSI_COLLISION_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FW_COLLISION_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OVERFLOW_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EOS_MASKED,N/A" "0,1"
|
|
group.long 0x220++0xB
|
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line.long 0x0 "SATURATE_INTR,Saturate interrupt request register."
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|
hexmask.long.word 0x0 0.--15. 1. "SATURATE_INTR,Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF this is an indication that the ADC likely saturated. Write with '1' to clear bit."
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line.long 0x4 "SATURATE_INTR_SET,Saturate interrupt set request register"
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hexmask.long.word 0x4 0.--15. 1. "SATURATE_SET,Write with '1' to set corresponding bit in interrupt request register."
|
|
line.long 0x8 "SATURATE_INTR_MASK,Saturate interrupt mask register."
|
|
hexmask.long.word 0x8 0.--15. 1. "SATURATE_MASK,Mask bit for corresponding bit in interrupt request register."
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|
rgroup.long 0x22C++0x3
|
|
line.long 0x0 "SATURATE_INTR_MASKED,Saturate interrupt masked request register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SATURATE_MASKED,Logical and of corresponding request and mask bits."
|
|
group.long 0x230++0xB
|
|
line.long 0x0 "RANGE_INTR,Range detect interrupt request register."
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hexmask.long.word 0x0 0.--15. 1. "RANGE_INTR,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit."
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|
line.long 0x4 "RANGE_INTR_SET,Range detect interrupt set request register"
|
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hexmask.long.word 0x4 0.--15. 1. "RANGE_SET,Write with '1' to set corresponding bit in interrupt request register."
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line.long 0x8 "RANGE_INTR_MASK,Range detect interrupt mask register."
|
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hexmask.long.word 0x8 0.--15. 1. "RANGE_MASK,Mask bit for corresponding bit in interrupt request register."
|
|
rgroup.long 0x23C++0x7
|
|
line.long 0x0 "RANGE_INTR_MASKED,Range interrupt masked request register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RANGE_MASKED,Logical and of corresponding request and mask bits."
|
|
line.long 0x4 "INTR_CAUSE,Interrupt cause register"
|
|
bitfld.long 0x4 31. "RANGE_MASKED_RED,N/A" "0,1"
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newline
|
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bitfld.long 0x4 30. "SATURATE_MASKED_RED,N/A" "0,1"
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newline
|
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bitfld.long 0x4 7. "INJ_COLLISION_MASKED_MIR,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "INJ_RANGE_MASKED_MIR,N/A" "0,1"
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newline
|
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bitfld.long 0x4 5. "INJ_SATURATE_MASKED_MIR,N/A" "0,1"
|
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newline
|
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bitfld.long 0x4 4. "INJ_EOC_MASKED_MIR,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "DSI_COLLISION_MASKED_MIR,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "FW_COLLISION_MASKED_MIR,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "OVERFLOW_MASKED_MIR,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "EOS_MASKED_MIR,N/A" "0,1"
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "INJ_CHAN_CONFIG,Injection channel configuration register."
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bitfld.long 0x0 31. "INJ_START_EN,N/A" "0,1"
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newline
|
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bitfld.long 0x0 30. "INJ_TAILGATING,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 12.--13. "INJ_SAMPLE_TIME_SEL,N/A" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x0 10. "INJ_AVG_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "INJ_DIFFERENTIAL_EN,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 4.--6. "INJ_PORT_ADDR,N/A" "0: SARMUX pins.,1: CTB0,2: CTB1,3: CTB2,4: CTB3,?,6: AROUTE virtual port,7: SARMUX virtual port"
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newline
|
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bitfld.long 0x0 0.--2. "INJ_PIN_ADDR,N/A" "0,1,2,3,4,5,6,7"
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|
rgroup.long 0x290++0x3
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line.long 0x0 "INJ_RESULT,Injection channel result register"
|
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bitfld.long 0x0 31. "INJ_EOC_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
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|
newline
|
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bitfld.long 0x0 30. "INJ_RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
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newline
|
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bitfld.long 0x0 29. "INJ_SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
|
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newline
|
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bitfld.long 0x0 28. "INJ_COLLISION_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
|
|
newline
|
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bitfld.long 0x0 27. "INJ_NEWVALUE,The data in this register received a new value (only relevant for UAB this bit shows the value of the UAB valid bit)" "0,1"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "INJ_RESULT,SAR conversion result of the channel."
|
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rgroup.long 0x2A0++0x7
|
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line.long 0x0 "STATUS,Current status of internal SAR registers (mostly for debug)"
|
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bitfld.long 0x0 31. "BUSY,If high then the SAR is busy with a conversion. This bit is always high when CONTINUOUS is set. Firmware should wait for this bit to be low before putting the SAR in power down." "0,1"
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newline
|
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bitfld.long 0x0 30. "SW_VREF_NEG,the current switch status including DSI and sequencer controls of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL)." "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 0.--4. 1. "CUR_CHAN,current channel being sampled (channel 16 indicates the injection channel) only valid if BUSY."
|
|
line.long 0x4 "AVG_STAT,Current averaging status (for debug)"
|
|
hexmask.long.byte 0x4 24.--31. 1. "CUR_AVG_CNT,the current value of the averaging counter. Note that the value shown is updated after the sampling time and therefore runs ahead of the accumulator update."
|
|
newline
|
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bitfld.long 0x4 23. "INTRLV_BUSY,If high then the SAR is in the middle of Interleaved averaging spanning several scans. While this bit is high the Firmware should not make any changes to the configuration registers otherwise some results may be incorrect. Note that the.." "0,1"
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|
newline
|
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hexmask.long.tbyte 0x4 0.--19. 1. "CUR_AVG_ACCU,the current value of the averaging accumulator"
|
|
group.long 0x300++0x7
|
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line.long 0x0 "MUX_SWITCH0,SARMUX Firmware switch controls"
|
|
bitfld.long 0x0 29. "MUX_FW_P7_COREIO3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "MUX_FW_P6_COREIO2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "MUX_FW_P5_COREIO1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "MUX_FW_P4_COREIO0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "MUX_FW_SARBUS1_VMINUS,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "MUX_FW_SARBUS0_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "MUX_FW_SARBUS1_VPLUS,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 22. "MUX_FW_SARBUS0_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MUX_FW_AMUXBUSB_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "MUX_FW_AMUXBUSA_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MUX_FW_AMUXBUSB_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "MUX_FW_AMUXBUSA_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MUX_FW_TEMP_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MUX_FW_VSSA_VMINUS,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "MUX_FW_P7_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "MUX_FW_P6_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MUX_FW_P5_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "MUX_FW_P4_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MUX_FW_P3_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "MUX_FW_P2_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MUX_FW_P1_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MUX_FW_P0_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MUX_FW_P7_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "MUX_FW_P6_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MUX_FW_P5_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MUX_FW_P4_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MUX_FW_P3_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MUX_FW_P2_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MUX_FW_P1_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MUX_FW_P0_VPLUS,N/A" "0,1"
|
|
line.long 0x4 "MUX_SWITCH_CLEAR0,SARMUX Firmware switch control clear"
|
|
bitfld.long 0x4 29. "MUX_FW_P7_COREIO3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "MUX_FW_P6_COREIO2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "MUX_FW_P5_COREIO1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "MUX_FW_P4_COREIO0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "MUX_FW_SARBUS1_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "MUX_FW_SARBUS0_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "MUX_FW_SARBUS1_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "MUX_FW_SARBUS0_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "MUX_FW_AMUXBUSB_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "MUX_FW_AMUXBUSA_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "MUX_FW_AMUXBUSB_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "MUX_FW_AMUXBUSA_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MUX_FW_TEMP_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MUX_FW_VSSA_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "MUX_FW_P7_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "MUX_FW_P6_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MUX_FW_P5_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "MUX_FW_P4_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MUX_FW_P3_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "MUX_FW_P2_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MUX_FW_P1_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "MUX_FW_P0_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MUX_FW_P7_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "MUX_FW_P6_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MUX_FW_P5_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "MUX_FW_P4_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MUX_FW_P3_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MUX_FW_P2_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MUX_FW_P1_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "MUX_FW_P0_VPLUS,N/A" "0,1"
|
|
group.long 0x340++0x7
|
|
line.long 0x0 "MUX_SWITCH_DS_CTRL,SARMUX switch DSI control"
|
|
bitfld.long 0x0 23. "MUX_DS_CTRL_SARBUS1,for sarbus1 switch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "MUX_DS_CTRL_SARBUS0,for sarbus0 switch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MUX_DS_CTRL_AMUXBUSB,for amuxbusb switches" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "MUX_DS_CTRL_AMUXBUSA,for amuxbusa switch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MUX_DS_CTRL_TEMP,for temp switch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MUX_DS_CTRL_VSSA,for vssa switch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MUX_DS_CTRL_P7,for P7 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "MUX_DS_CTRL_P6,for P6 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MUX_DS_CTRL_P5,for P5 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MUX_DS_CTRL_P4,for P4 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MUX_DS_CTRL_P3,for P3 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MUX_DS_CTRL_P2,for P2 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MUX_DS_CTRL_P1,for P1 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MUX_DS_CTRL_P0,for P0 switches" "0,1"
|
|
line.long 0x4 "MUX_SWITCH_SQ_CTRL,SARMUX switch Sar Sequencer control"
|
|
bitfld.long 0x4 23. "MUX_SQ_CTRL_SARBUS1,for sarbus1 switch" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "MUX_SQ_CTRL_SARBUS0,for sarbus0 switch" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "MUX_SQ_CTRL_AMUXBUSB,for amuxbusb switches" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "MUX_SQ_CTRL_AMUXBUSA,for amuxbusa switch" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MUX_SQ_CTRL_TEMP,for temp switch" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MUX_SQ_CTRL_VSSA,for vssa switch" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MUX_SQ_CTRL_P7,for P7 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "MUX_SQ_CTRL_P6,for P6 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MUX_SQ_CTRL_P5,for P5 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "MUX_SQ_CTRL_P4,for P4 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MUX_SQ_CTRL_P3,for P3 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MUX_SQ_CTRL_P2,for P2 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MUX_SQ_CTRL_P1,for P1 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "MUX_SQ_CTRL_P0,for P0 switches" "0,1"
|
|
rgroup.long 0x348++0x3
|
|
line.long 0x0 "MUX_SWITCH_STATUS,SARMUX switch status"
|
|
bitfld.long 0x0 25. "MUX_FW_SARBUS1_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "MUX_FW_SARBUS0_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "MUX_FW_SARBUS1_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "MUX_FW_SARBUS0_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MUX_FW_AMUXBUSB_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "MUX_FW_AMUXBUSA_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MUX_FW_AMUXBUSB_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "MUX_FW_AMUXBUSA_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MUX_FW_TEMP_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MUX_FW_VSSA_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MUX_FW_P7_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "MUX_FW_P6_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MUX_FW_P5_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "MUX_FW_P4_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MUX_FW_P3_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "MUX_FW_P2_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MUX_FW_P1_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MUX_FW_P0_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MUX_FW_P7_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "MUX_FW_P6_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MUX_FW_P5_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MUX_FW_P4_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MUX_FW_P3_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MUX_FW_P2_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MUX_FW_P1_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MUX_FW_P0_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
|
|
group.long 0xF00++0x7
|
|
line.long 0x0 "ANA_TRIM0,Analog trim register."
|
|
bitfld.long 0x0 5. "TRIMUNIT,Attenuation cap trimming" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "CAP_TRIM,Attenuation cap trimming"
|
|
line.long 0x4 "ANA_TRIM1,Analog trim register."
|
|
hexmask.long.byte 0x4 0.--5. 1. "SAR_REF_BUF_TRIM,SAR Reference buffer trim"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "CHAN_CONFIG[$1],Channel configuration register."
|
|
bitfld.long 0x0 31. "DSI_OUT_EN,N/A" "0,1"
|
|
bitfld.long 0x0 24. "NEG_ADDR_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--22. "NEG_PORT_ADDR,N/A" "0: SARMUX pins.,?,?,?,?,5: AROUTE virtual port2 (VPORT2),6: AROUTE virtual port1 (VPORT1),7: SARMUX virtual port (VPORT0)"
|
|
bitfld.long 0x0 16.--18. "NEG_PIN_ADDR,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "SAMPLE_TIME_SEL,N/A" "0,1,2,3"
|
|
bitfld.long 0x0 10. "AVG_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIFFERENTIAL_EN,N/A" "0,1"
|
|
bitfld.long 0x0 4.--6. "POS_PORT_ADDR,N/A" "0: SARMUX pins.,1: CTB0,2: CTB1,3: CTB2,4: CTB3,5: AROUTE virtual port2 (VPORT2),6: AROUTE virtual port1 (VPORT1),7: SARMUX virtual port (VPORT0)"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "POS_PIN_ADDR,N/A" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "CHAN_CONFIG[$1],Channel configuration register."
|
|
bitfld.long 0x0 31. "DSI_OUT_EN,N/A" "0,1"
|
|
bitfld.long 0x0 24. "NEG_ADDR_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--22. "NEG_PORT_ADDR,N/A" "0: SARMUX pins.,?,?,?,?,5: AROUTE virtual port2 (VPORT2),6: AROUTE virtual port1 (VPORT1),7: SARMUX virtual port (VPORT0)"
|
|
bitfld.long 0x0 16.--18. "NEG_PIN_ADDR,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "SAMPLE_TIME_SEL,N/A" "0,1,2,3"
|
|
bitfld.long 0x0 10. "AVG_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIFFERENTIAL_EN,N/A" "0,1"
|
|
bitfld.long 0x0 4.--6. "POS_PORT_ADDR,N/A" "0: SARMUX pins.,1: CTB0,2: CTB1,3: CTB2,4: CTB3,5: AROUTE virtual port2 (VPORT2),6: AROUTE virtual port1 (VPORT1),7: SARMUX virtual port (VPORT0)"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "POS_PIN_ADDR,N/A" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x100)++0x3
|
|
line.long 0x0 "CHAN_WORK[$1],Channel working data register"
|
|
bitfld.long 0x0 31. "CHAN_WORK_UPDATED_MIR,mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "0,1"
|
|
bitfld.long 0x0 27. "CHAN_WORK_NEWVALUE_MIR,mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "WORK,SAR conversion working data of the channel. The data is written here right after sampling this channel."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x100)++0x3
|
|
line.long 0x0 "CHAN_WORK[$1],Channel working data register"
|
|
bitfld.long 0x0 31. "CHAN_WORK_UPDATED_MIR,mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "0,1"
|
|
bitfld.long 0x0 27. "CHAN_WORK_NEWVALUE_MIR,mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "WORK,SAR conversion working data of the channel. The data is written here right after sampling this channel."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x180)++0x3
|
|
line.long 0x0 "CHAN_RESULT[$1],Channel result data register"
|
|
bitfld.long 0x0 31. "CHAN_RESULT_UPDATED_MIR,mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "0,1"
|
|
bitfld.long 0x0 30. "RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_RANGE_INTR register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_SATURATE_INTR register" "0,1"
|
|
bitfld.long 0x0 27. "CHAN_RESULT_NEWVALUE_MIR,mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RESULT,SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x180)++0x3
|
|
line.long 0x0 "CHAN_RESULT[$1],Channel result data register"
|
|
bitfld.long 0x0 31. "CHAN_RESULT_UPDATED_MIR,mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "0,1"
|
|
bitfld.long 0x0 30. "RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_RANGE_INTR register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_SATURATE_INTR register" "0,1"
|
|
bitfld.long 0x0 27. "CHAN_RESULT_NEWVALUE_MIR,mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RESULT,SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "CHAN_CONFIG[$1],Channel configuration register."
|
|
bitfld.long 0x0 31. "DSI_OUT_EN,N/A" "0,1"
|
|
bitfld.long 0x0 24. "NEG_ADDR_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--22. "NEG_PORT_ADDR,N/A" "0: SARMUX pins.,?,?,?,?,5: AROUTE virtual port2 (VPORT2),6: AROUTE virtual port1 (VPORT1),7: SARMUX virtual port (VPORT0)"
|
|
bitfld.long 0x0 16.--18. "NEG_PIN_ADDR,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "SAMPLE_TIME_SEL,N/A" "0,1,2,3"
|
|
bitfld.long 0x0 10. "AVG_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIFFERENTIAL_EN,N/A" "0,1"
|
|
bitfld.long 0x0 4.--6. "POS_PORT_ADDR,N/A" "0: SARMUX pins.,1: CTB0,2: CTB1,3: CTB2,4: CTB3,5: AROUTE virtual port2 (VPORT2),6: AROUTE virtual port1 (VPORT1),7: SARMUX virtual port (VPORT0)"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "POS_PIN_ADDR,N/A" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x100)++0x3
|
|
line.long 0x0 "CHAN_WORK[$1],Channel working data register"
|
|
bitfld.long 0x0 31. "CHAN_WORK_UPDATED_MIR,mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "0,1"
|
|
bitfld.long 0x0 27. "CHAN_WORK_NEWVALUE_MIR,mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "WORK,SAR conversion working data of the channel. The data is written here right after sampling this channel."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x180)++0x3
|
|
line.long 0x0 "CHAN_RESULT[$1],Channel result data register"
|
|
bitfld.long 0x0 31. "CHAN_RESULT_UPDATED_MIR,mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "0,1"
|
|
bitfld.long 0x0 30. "RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_RANGE_INTR register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_SATURATE_INTR register" "0,1"
|
|
bitfld.long 0x0 27. "CHAN_RESULT_NEWVALUE_MIR,mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RESULT,SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled."
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
tree "SAR_ADC (SAR ADC with Sequencer)"
|
|
base ad:0x0
|
|
tree "SAR0"
|
|
base ad:0x409B0000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTRL,Analog control register."
|
|
bitfld.long 0x0 31. "ENABLED,- 0: SAR disabled (put analog in power down and stop clocks) also can clear FW_TRIGGER on write." "0: SAR disabled,1: SAR IP enabled"
|
|
newline
|
|
bitfld.long 0x0 30. "SWITCH_DISABLE,Disable SAR sequencer from enabling routing switches" "0: Normal mode,1: Switches disabled"
|
|
newline
|
|
bitfld.long 0x0 29. "DSI_MODE,SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1)" "0: Normal mode,1: CHAN_EN and channel configurations in.."
|
|
newline
|
|
bitfld.long 0x0 28. "DSI_SYNC_CONFIG,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DEEPSLEEP_ON,- 0: SARMUX disabled during System Deep Sleep power mode" "0: SARMUX disabled during System Deep Sleep power..,1: SARMUX remains enabled during System Deep Sleep.."
|
|
newline
|
|
bitfld.long 0x0 24.--26. "COMP_PWR,Comparator power mode." "0: Power = 100 percent Use this for SAR Clock..,1: N/A,2: Power = 60 percent Use this for SAR Clock..,3: N/A,4: N/A,5: N/A,6: Power = 20 percent Use this for SAR Clock..,7: N/A"
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|
newline
|
|
bitfld.long 0x0 21. "REFBUF_EN,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 20. "BOOSTPUMP_EN,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "SPARE,N/A"
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|
newline
|
|
bitfld.long 0x0 14.--15. "COMP_DLY,N/A" "0: 2.5ns delay use this for 2.5Msps,1: 4.0ns delay use this for 2.0Msps,2: 10ns delay use this for 1.5Msps,3: 12ns delay use this for 1.0Msps or less"
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|
newline
|
|
bitfld.long 0x0 13. "SAR_HW_CTRL_NEGVREF,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 9.--11. "NEG_SEL,N/A" "0: NEG input of SARADC is connected to..,1: NEG input of SARADC is connected to VSSA in..,2: NEG input of SARADC is connected to P1 pin of..,3: NEG input of SARADC is connected to P3 pin of..,4: NEG input of SARADC is connected to P5 pin of..,5: NEG input of SARADC is connected to P7 pin of..,6: NEG input of SARADC is connected to an ACORE in..,7: NEG input of SARADC is shorted with VREF input.."
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|
newline
|
|
bitfld.long 0x0 7. "VREF_BYP_CAP_EN,VREF bypass cap enable when VREF buffer is on" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "VREF_SEL,N/A" "0: VREF0 from PRB (VREF buffer on),1: VREF1 from PRB (VREF buffer on),2: VREF2 from PRB (VREF buffer on),3: VREF from AROUTE (VREF buffer on),4: 1.024V from BandGap (VREF buffer on),5: External precision Vref direct from a pin (low..,6: Vdda/2 (VREF buffer on),7: Vdda."
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|
newline
|
|
bitfld.long 0x0 0.--2. "PWR_CTRL_VREF,VREF buffer low power mode." "0: full power (100 percent) (default) bypass cap..,1: 80 percent power,2: 60 percent power,3: 50 percent power,4: 40 percent power,5: 30 percent power,6: 20 percent power,7: 10 percent power"
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|
line.long 0x4 "SAMPLE_CTRL,Sample control register."
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|
bitfld.long 0x4 31. "EOS_DSI_OUT_EN,Enable to output EOS_INTR. When enabled each time EOS_INTR is set by the hardware also a trigger pulse is send on the tr_sar_out signal." "0,1"
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|
newline
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bitfld.long 0x4 30. "TRIGGER_OUT_EN,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x4 28. "VALID_IGNORE,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x4 27. "VALID_SEL_EN,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x4 24.--26. "VALID_SEL,N/A" "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x4 23. "REPEAT_INVALID,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x4 22. "UAB_SCAN_MODE,N/A" "0: Unscheduled UABs: one or more of the UABs..,1: Scheduled UABs: All UABs scanned by the SAR are.."
|
|
newline
|
|
bitfld.long 0x4 19. "DSI_SYNC_TRIGGER,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x4 18. "DSI_TRIGGER_LEVEL,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x4 17. "DSI_TRIGGER_EN,- 0: firmware trigger only: disable hardware trigger tr_sar_in." "0: firmware trigger only: disable hardware trigger..,1: enable hardware trigger tr_sar_in"
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|
newline
|
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bitfld.long 0x4 16. "CONTINUOUS,N/A" "0,1"
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|
newline
|
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bitfld.long 0x4 8. "AVG_MODE,Averaging mode" "0: Accumulate and Dump (1st order accumulate and..,1: Interleaved: Each scan (trigger) one sample is.."
|
|
newline
|
|
bitfld.long 0x4 7. "AVG_SHIFT,N/A" "0,1"
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|
newline
|
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bitfld.long 0x4 4.--6. "AVG_CNT,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x4 3. "DIFFERENTIAL_SIGNED,N/A" "0: result data is unsigned (zero extended if needed),1: Default: result data is signed (sign extended if.."
|
|
newline
|
|
bitfld.long 0x4 2. "SINGLE_ENDED_SIGNED,N/A" "0: Default: result data is unsigned (zero extended..,1: result data is signed (sign extended if needed)"
|
|
newline
|
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bitfld.long 0x4 1. "LEFT_ALIGN,N/A" "0,1"
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|
group.long 0x10++0x17
|
|
line.long 0x0 "SAMPLE_TIME01,Sample time specification ST0 and ST1"
|
|
hexmask.long.word 0x0 16.--25. 1. "SAMPLE_TIME1,Sample time1"
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|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "SAMPLE_TIME0,Sample time0 (aperture) in ADC clock cycles. Note that actual sample time is one clock less than specified here. The minimum sample time is 167ns which is 3.0 cycles (4 in this field) with an 18MHz clock. Minimum legal value in this.."
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|
line.long 0x4 "SAMPLE_TIME23,Sample time specification ST2 and ST3"
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|
hexmask.long.word 0x4 16.--25. 1. "SAMPLE_TIME3,Sample time3"
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|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SAMPLE_TIME2,Sample time2"
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|
line.long 0x8 "RANGE_THRES,Global range detect threshold register."
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|
hexmask.long.word 0x8 16.--31. 1. "RANGE_HIGH,High threshold for range detect."
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|
newline
|
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hexmask.long.word 0x8 0.--15. 1. "RANGE_LOW,Low threshold for range detect."
|
|
line.long 0xC "RANGE_COND,Global range detect mode register."
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|
bitfld.long 0xC 30.--31. "RANGE_COND,Range condition select." "0: result < RANGE_LOW,1: RANGE_LOW <= result < RANGE_HIGH,2: RANGE_HIGH <= result,3: result < RANGE_LOW || RANGE_HIGH <= result"
|
|
line.long 0x10 "CHAN_EN,Enable bits for the channels"
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|
hexmask.long.word 0x10 0.--15. 1. "CHAN_EN,Channel enable."
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|
line.long 0x14 "START_CTRL,Start control register (firmware trigger)."
|
|
bitfld.long 0x14 0. "FW_TRIGGER,When firmware writes a 1 here it will trigger the next scan of enabled channels hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after.." "0,1"
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|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
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|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "CHAN_CONFIG[$1],Channel configuration register."
|
|
bitfld.long 0x0 31. "DSI_OUT_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "NEG_ADDR_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--22. "NEG_PORT_ADDR,N/A" "0: SARMUX pins.,?,?,?,?,5: AROUTE virtual port2 (VPORT2),6: AROUTE virtual port1 (VPORT1),7: SARMUX virtual port (VPORT0)"
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|
newline
|
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bitfld.long 0x0 16.--18. "NEG_PIN_ADDR,Address of the neg pin to be sampled by this channel." "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x0 12.--13. "SAMPLE_TIME_SEL,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10. "AVG_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIFFERENTIAL_EN,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 4.--6. "POS_PORT_ADDR,N/A" "0: SARMUX pins.,1: CTB0,2: CTB1,3: CTB2,4: CTB3,5: AROUTE virtual port2 (VPORT2),6: AROUTE virtual port1 (VPORT1),7: SARMUX virtual port (VPORT0)"
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|
newline
|
|
bitfld.long 0x0 0.--2. "POS_PIN_ADDR,Address of the pin to be sampled by this channel (connected to Vplus)." "0,1,2,3,4,5,6,7"
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|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x100)++0x3
|
|
line.long 0x0 "CHAN_WORK[$1],Channel working data register"
|
|
bitfld.long 0x0 31. "CHAN_WORK_UPDATED_MIR,mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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|
newline
|
|
bitfld.long 0x0 27. "CHAN_WORK_NEWVALUE_MIR,mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "WORK,SAR conversion working data of the channel. The data is written here right after sampling this channel. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1."
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|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
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|
rgroup.long ($2+0x180)++0x3
|
|
line.long 0x0 "CHAN_RESULT[$1],Channel result data register"
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bitfld.long 0x0 31. "CHAN_RESULT_UPDATED_MIR,mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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|
newline
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bitfld.long 0x0 30. "RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_RANGE_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
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bitfld.long 0x0 29. "SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_SATURATE_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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|
newline
|
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bitfld.long 0x0 27. "CHAN_RESULT_NEWVALUE_MIR,mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RESULT,SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1."
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|
repeat.end
|
|
rgroup.long 0x200++0xF
|
|
line.long 0x0 "CHAN_WORK_UPDATED,Channel working data register 'updated' bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "CHAN_WORK_UPDATED,If set the corresponding WORK register was updated i.e. was already sampled during the current scan and in case of Interleaved averaging reached the averaging count. If this bit is low then either the channel is not enabled or the.."
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line.long 0x4 "CHAN_RESULT_UPDATED,Channel result data register 'updated' bits"
|
|
hexmask.long.word 0x4 0.--15. 1. "CHAN_RESULT_UPDATED,If set the corresponding RESULT register was updated i.e. was sampled during the previous scan and in case of Interleaved averaging reached the averaging count. If this bit is low then either the channel is not enabled or the.."
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|
line.long 0x8 "CHAN_WORK_NEWVALUE,Channel working data register 'new value' bits"
|
|
hexmask.long.word 0x8 0.--15. 1. "CHAN_WORK_NEWVALUE,If set the corresponding WORK data received a new value i.e. was already sampled during the current scan and data was valid."
|
|
line.long 0xC "CHAN_RESULT_NEWVALUE,Channel result data register 'new value' bits"
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|
hexmask.long.word 0xC 0.--15. 1. "CHAN_RESULT_NEWVALUE,If set the corresponding RESULT data received a new value i.e. was sampled during the last scan and data was valid."
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "INTR,Interrupt request register."
|
|
bitfld.long 0x0 7. "INJ_COLLISION_INTR,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "INJ_RANGE_INTR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "INJ_SATURATE_INTR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "INJ_EOC_INTR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DSI_COLLISION_INTR,This interrupt is set when a hardware trigger signal is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the hardware trigger has been completed i.e. not when the preceding scan with which.." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "FW_COLLISION_INTR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OVERFLOW_INTR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EOS_INTR,N/A" "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x4 7. "INJ_COLLISION_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "INJ_RANGE_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "INJ_SATURATE_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "INJ_EOC_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DSI_COLLISION_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "FW_COLLISION_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OVERFLOW_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EOS_SET,N/A" "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register."
|
|
bitfld.long 0x8 7. "INJ_COLLISION_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "INJ_RANGE_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "INJ_SATURATE_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "INJ_EOC_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DSI_COLLISION_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "FW_COLLISION_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "OVERFLOW_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "EOS_MASK,N/A" "0,1"
|
|
rgroup.long 0x21C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 7. "INJ_COLLISION_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INJ_RANGE_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "INJ_SATURATE_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "INJ_EOC_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DSI_COLLISION_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FW_COLLISION_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OVERFLOW_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EOS_MASKED,N/A" "0,1"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "SATURATE_INTR,Saturate interrupt request register."
|
|
hexmask.long.word 0x0 0.--15. 1. "SATURATE_INTR,Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF this is an indication that the ADC likely saturated. Write with '1' to clear bit."
|
|
line.long 0x4 "SATURATE_INTR_SET,Saturate interrupt set request register"
|
|
hexmask.long.word 0x4 0.--15. 1. "SATURATE_SET,Write with '1' to set corresponding bit in interrupt request register."
|
|
line.long 0x8 "SATURATE_INTR_MASK,Saturate interrupt mask register."
|
|
hexmask.long.word 0x8 0.--15. 1. "SATURATE_MASK,Mask bit for corresponding bit in interrupt request register."
|
|
rgroup.long 0x22C++0x3
|
|
line.long 0x0 "SATURATE_INTR_MASKED,Saturate interrupt masked request register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SATURATE_MASKED,Logical and of corresponding request and mask bits."
|
|
group.long 0x230++0xB
|
|
line.long 0x0 "RANGE_INTR,Range detect interrupt request register."
|
|
hexmask.long.word 0x0 0.--15. 1. "RANGE_INTR,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit."
|
|
line.long 0x4 "RANGE_INTR_SET,Range detect interrupt set request register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RANGE_SET,Write with '1' to set corresponding bit in interrupt request register."
|
|
line.long 0x8 "RANGE_INTR_MASK,Range detect interrupt mask register."
|
|
hexmask.long.word 0x8 0.--15. 1. "RANGE_MASK,Mask bit for corresponding bit in interrupt request register."
|
|
rgroup.long 0x23C++0x7
|
|
line.long 0x0 "RANGE_INTR_MASKED,Range interrupt masked request register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RANGE_MASKED,Logical and of corresponding request and mask bits."
|
|
line.long 0x4 "INTR_CAUSE,Interrupt cause register"
|
|
bitfld.long 0x4 31. "RANGE_MASKED_RED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "SATURATE_MASKED_RED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "INJ_COLLISION_MASKED_MIR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "INJ_RANGE_MASKED_MIR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "INJ_SATURATE_MASKED_MIR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "INJ_EOC_MASKED_MIR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DSI_COLLISION_MASKED_MIR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "FW_COLLISION_MASKED_MIR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OVERFLOW_MASKED_MIR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EOS_MASKED_MIR,N/A" "0,1"
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "INJ_CHAN_CONFIG,Injection channel configuration register."
|
|
bitfld.long 0x0 31. "INJ_START_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "INJ_TAILGATING,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "INJ_SAMPLE_TIME_SEL,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10. "INJ_AVG_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "INJ_DIFFERENTIAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "INJ_PORT_ADDR,N/A" "0: SARMUX pins.,1: CTB0,2: CTB1,3: CTB2,4: CTB3,?,6: AROUTE virtual port,7: SARMUX virtual port"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "INJ_PIN_ADDR,N/A" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x290++0x3
|
|
line.long 0x0 "INJ_RESULT,Injection channel result register"
|
|
bitfld.long 0x0 31. "INJ_EOC_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "INJ_RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "INJ_SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "INJ_COLLISION_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "INJ_NEWVALUE,The data in this register received a new value (only relevant for UAB this bit shows the value of the UAB valid bit). This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "INJ_RESULT,SAR conversion result of the channel. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1."
|
|
rgroup.long 0x2A0++0x7
|
|
line.long 0x0 "STATUS,Current status of internal SAR registers (mostly for debug)"
|
|
bitfld.long 0x0 31. "BUSY,If high then the SAR is busy with a conversion. This bit is always high when CONTINUOUS is set. Firmware should wait for this bit to be low before putting the SAR in power down." "0,1"
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newline
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bitfld.long 0x0 30. "SW_VREF_NEG,the current switch status including DSI and sequencer controls of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL). This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
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hexmask.long.byte 0x0 0.--4. 1. "CUR_CHAN,current channel being sampled (channel 16 indicates the injection channel) only valid if BUSY. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1."
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line.long 0x4 "AVG_STAT,Current averaging status (for debug)"
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hexmask.long.byte 0x4 24.--31. 1. "CUR_AVG_CNT,the current value of the averaging counter. Note that the value shown is updated after the sampling time and therefore runs ahead of the accumulator update. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1."
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newline
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bitfld.long 0x4 23. "INTRLV_BUSY,If high then the SAR is in the middle of Interleaved averaging spanning several scans. While this bit is high the Firmware should not make any changes to the configuration registers otherwise some results may be incorrect. Note that the.." "0,1"
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newline
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hexmask.long.tbyte 0x4 0.--19. 1. "CUR_AVG_ACCU,the current value of the averaging accumulator. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1."
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group.long 0x300++0x7
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line.long 0x0 "MUX_SWITCH0,SARMUX Firmware switch controls"
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bitfld.long 0x0 29. "MUX_FW_P7_COREIO3,N/A" "0,1"
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newline
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bitfld.long 0x0 28. "MUX_FW_P6_COREIO2,N/A" "0,1"
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newline
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bitfld.long 0x0 27. "MUX_FW_P5_COREIO1,N/A" "0,1"
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newline
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bitfld.long 0x0 26. "MUX_FW_P4_COREIO0,N/A" "0,1"
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newline
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bitfld.long 0x0 25. "MUX_FW_SARBUS1_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x0 24. "MUX_FW_SARBUS0_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x0 23. "MUX_FW_SARBUS1_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x0 22. "MUX_FW_SARBUS0_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x0 21. "MUX_FW_AMUXBUSB_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x0 20. "MUX_FW_AMUXBUSA_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x0 19. "MUX_FW_AMUXBUSB_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x0 18. "MUX_FW_AMUXBUSA_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x0 17. "MUX_FW_TEMP_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x0 16. "MUX_FW_VSSA_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x0 15. "MUX_FW_P7_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x0 14. "MUX_FW_P6_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x0 13. "MUX_FW_P5_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x0 12. "MUX_FW_P4_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x0 11. "MUX_FW_P3_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x0 10. "MUX_FW_P2_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x0 9. "MUX_FW_P1_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "MUX_FW_P0_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x0 7. "MUX_FW_P7_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x0 6. "MUX_FW_P6_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x0 5. "MUX_FW_P5_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "MUX_FW_P4_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x0 3. "MUX_FW_P3_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "MUX_FW_P2_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "MUX_FW_P1_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x0 0. "MUX_FW_P0_VPLUS,N/A" "0,1"
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line.long 0x4 "MUX_SWITCH_CLEAR0,SARMUX Firmware switch control clear"
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bitfld.long 0x4 29. "MUX_FW_P7_COREIO3,N/A" "0,1"
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newline
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bitfld.long 0x4 28. "MUX_FW_P6_COREIO2,N/A" "0,1"
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newline
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bitfld.long 0x4 27. "MUX_FW_P5_COREIO1,N/A" "0,1"
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newline
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bitfld.long 0x4 26. "MUX_FW_P4_COREIO0,N/A" "0,1"
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newline
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bitfld.long 0x4 25. "MUX_FW_SARBUS1_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x4 24. "MUX_FW_SARBUS0_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x4 23. "MUX_FW_SARBUS1_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x4 22. "MUX_FW_SARBUS0_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x4 21. "MUX_FW_AMUXBUSB_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x4 20. "MUX_FW_AMUXBUSA_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x4 19. "MUX_FW_AMUXBUSB_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x4 18. "MUX_FW_AMUXBUSA_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x4 17. "MUX_FW_TEMP_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x4 16. "MUX_FW_VSSA_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x4 15. "MUX_FW_P7_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x4 14. "MUX_FW_P6_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x4 13. "MUX_FW_P5_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x4 12. "MUX_FW_P4_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x4 11. "MUX_FW_P3_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x4 10. "MUX_FW_P2_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x4 9. "MUX_FW_P1_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x4 8. "MUX_FW_P0_VMINUS,N/A" "0,1"
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newline
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bitfld.long 0x4 7. "MUX_FW_P7_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x4 6. "MUX_FW_P6_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x4 5. "MUX_FW_P5_VPLUS,N/A" "0,1"
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newline
|
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bitfld.long 0x4 4. "MUX_FW_P4_VPLUS,N/A" "0,1"
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newline
|
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bitfld.long 0x4 3. "MUX_FW_P3_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x4 2. "MUX_FW_P2_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x4 1. "MUX_FW_P1_VPLUS,N/A" "0,1"
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newline
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bitfld.long 0x4 0. "MUX_FW_P0_VPLUS,N/A" "0,1"
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group.long 0x344++0x3
|
|
line.long 0x0 "MUX_SWITCH_SQ_CTRL,SARMUX switch Sar Sequencer control"
|
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bitfld.long 0x0 23. "MUX_SQ_CTRL_SARBUS1,for sarbus1 switch" "0,1"
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newline
|
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bitfld.long 0x0 22. "MUX_SQ_CTRL_SARBUS0,for sarbus0 switch" "0,1"
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newline
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bitfld.long 0x0 19. "MUX_SQ_CTRL_AMUXBUSB,for amuxbusb switches" "0,1"
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newline
|
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bitfld.long 0x0 18. "MUX_SQ_CTRL_AMUXBUSA,for amuxbusa switch" "0,1"
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newline
|
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bitfld.long 0x0 17. "MUX_SQ_CTRL_TEMP,for temp switch" "0,1"
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newline
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bitfld.long 0x0 16. "MUX_SQ_CTRL_VSSA,for vssa switch" "0,1"
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newline
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bitfld.long 0x0 7. "MUX_SQ_CTRL_P7,for P7 switches" "0,1"
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newline
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bitfld.long 0x0 6. "MUX_SQ_CTRL_P6,for P6 switches" "0,1"
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newline
|
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bitfld.long 0x0 5. "MUX_SQ_CTRL_P5,for P5 switches" "0,1"
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newline
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bitfld.long 0x0 4. "MUX_SQ_CTRL_P4,for P4 switches" "0,1"
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newline
|
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bitfld.long 0x0 3. "MUX_SQ_CTRL_P3,for P3 switches" "0,1"
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newline
|
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bitfld.long 0x0 2. "MUX_SQ_CTRL_P2,for P2 switches" "0,1"
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newline
|
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bitfld.long 0x0 1. "MUX_SQ_CTRL_P1,for P1 switches" "0,1"
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newline
|
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bitfld.long 0x0 0. "MUX_SQ_CTRL_P0,for P0 switches" "0,1"
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rgroup.long 0x348++0x3
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line.long 0x0 "MUX_SWITCH_STATUS,SARMUX switch status"
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bitfld.long 0x0 25. "MUX_FW_SARBUS1_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 24. "MUX_FW_SARBUS0_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
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bitfld.long 0x0 23. "MUX_FW_SARBUS1_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 22. "MUX_FW_SARBUS0_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 21. "MUX_FW_AMUXBUSB_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 20. "MUX_FW_AMUXBUSA_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 19. "MUX_FW_AMUXBUSB_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 18. "MUX_FW_AMUXBUSA_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 17. "MUX_FW_TEMP_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 16. "MUX_FW_VSSA_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 15. "MUX_FW_P7_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 14. "MUX_FW_P6_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 13. "MUX_FW_P5_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 12. "MUX_FW_P4_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 11. "MUX_FW_P3_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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|
newline
|
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bitfld.long 0x0 10. "MUX_FW_P2_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 9. "MUX_FW_P1_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "MUX_FW_P0_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 7. "MUX_FW_P7_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 6. "MUX_FW_P6_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 5. "MUX_FW_P5_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 4. "MUX_FW_P4_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 3. "MUX_FW_P3_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 2. "MUX_FW_P2_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 1. "MUX_FW_P1_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
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newline
|
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bitfld.long 0x0 0. "MUX_FW_P0_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
tree.end
|
|
tree "SAR1"
|
|
base ad:0x409C0000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTRL,Analog control register."
|
|
bitfld.long 0x0 31. "ENABLED,- 0: SAR disabled (put analog in power down and stop clocks) also can clear FW_TRIGGER on write." "0: SAR disabled,1: SAR IP enabled"
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|
newline
|
|
bitfld.long 0x0 30. "SWITCH_DISABLE,Disable SAR sequencer from enabling routing switches" "0: Normal mode,1: Switches disabled"
|
|
newline
|
|
bitfld.long 0x0 29. "DSI_MODE,SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1)" "0: Normal mode,1: CHAN_EN and channel configurations in.."
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|
newline
|
|
bitfld.long 0x0 28. "DSI_SYNC_CONFIG,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DEEPSLEEP_ON,- 0: SARMUX disabled during System Deep Sleep power mode" "0: SARMUX disabled during System Deep Sleep power..,1: SARMUX remains enabled during System Deep Sleep.."
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|
newline
|
|
bitfld.long 0x0 24.--26. "COMP_PWR,Comparator power mode." "0: Power = 100 percent Use this for SAR Clock..,1: N/A,2: Power = 60 percent Use this for SAR Clock..,3: N/A,4: N/A,5: N/A,6: Power = 20 percent Use this for SAR Clock..,7: N/A"
|
|
newline
|
|
bitfld.long 0x0 21. "REFBUF_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "BOOSTPUMP_EN,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "SPARE,N/A"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "COMP_DLY,N/A" "0: 2.5ns delay use this for 2.5Msps,1: 4.0ns delay use this for 2.0Msps,2: 10ns delay use this for 1.5Msps,3: 12ns delay use this for 1.0Msps or less"
|
|
newline
|
|
bitfld.long 0x0 13. "SAR_HW_CTRL_NEGVREF,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "NEG_SEL,N/A" "0: NEG input of SARADC is connected to..,1: NEG input of SARADC is connected to VSSA in..,2: NEG input of SARADC is connected to P1 pin of..,3: NEG input of SARADC is connected to P3 pin of..,4: NEG input of SARADC is connected to P5 pin of..,5: NEG input of SARADC is connected to P7 pin of..,6: NEG input of SARADC is connected to an ACORE in..,7: NEG input of SARADC is shorted with VREF input.."
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|
newline
|
|
bitfld.long 0x0 7. "VREF_BYP_CAP_EN,VREF bypass cap enable when VREF buffer is on" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "VREF_SEL,N/A" "0: VREF0 from PRB (VREF buffer on),1: VREF1 from PRB (VREF buffer on),2: VREF2 from PRB (VREF buffer on),3: VREF from AROUTE (VREF buffer on),4: 1.024V from BandGap (VREF buffer on),5: External precision Vref direct from a pin (low..,6: Vdda/2 (VREF buffer on),7: Vdda."
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|
newline
|
|
bitfld.long 0x0 0.--2. "PWR_CTRL_VREF,VREF buffer low power mode." "0: full power (100 percent) (default) bypass cap..,1: 80 percent power,2: 60 percent power,3: 50 percent power,4: 40 percent power,5: 30 percent power,6: 20 percent power,7: 10 percent power"
|
|
line.long 0x4 "SAMPLE_CTRL,Sample control register."
|
|
bitfld.long 0x4 31. "EOS_DSI_OUT_EN,Enable to output EOS_INTR. When enabled each time EOS_INTR is set by the hardware also a trigger pulse is send on the tr_sar_out signal." "0,1"
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|
newline
|
|
bitfld.long 0x4 30. "TRIGGER_OUT_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "VALID_IGNORE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "VALID_SEL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24.--26. "VALID_SEL,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 23. "REPEAT_INVALID,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "UAB_SCAN_MODE,N/A" "0: Unscheduled UABs: one or more of the UABs..,1: Scheduled UABs: All UABs scanned by the SAR are.."
|
|
newline
|
|
bitfld.long 0x4 19. "DSI_SYNC_TRIGGER,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "DSI_TRIGGER_LEVEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "DSI_TRIGGER_EN,- 0: firmware trigger only: disable hardware trigger tr_sar_in." "0: firmware trigger only: disable hardware trigger..,1: enable hardware trigger tr_sar_in"
|
|
newline
|
|
bitfld.long 0x4 16. "CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "AVG_MODE,Averaging mode" "0: Accumulate and Dump (1st order accumulate and..,1: Interleaved: Each scan (trigger) one sample is.."
|
|
newline
|
|
bitfld.long 0x4 7. "AVG_SHIFT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "AVG_CNT,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "DIFFERENTIAL_SIGNED,N/A" "0: result data is unsigned (zero extended if needed),1: Default: result data is signed (sign extended if.."
|
|
newline
|
|
bitfld.long 0x4 2. "SINGLE_ENDED_SIGNED,N/A" "0: Default: result data is unsigned (zero extended..,1: result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x4 1. "LEFT_ALIGN,N/A" "0,1"
|
|
group.long 0x10++0x17
|
|
line.long 0x0 "SAMPLE_TIME01,Sample time specification ST0 and ST1"
|
|
hexmask.long.word 0x0 16.--25. 1. "SAMPLE_TIME1,Sample time1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "SAMPLE_TIME0,Sample time0 (aperture) in ADC clock cycles. Note that actual sample time is one clock less than specified here. The minimum sample time is 167ns which is 3.0 cycles (4 in this field) with an 18MHz clock. Minimum legal value in this.."
|
|
line.long 0x4 "SAMPLE_TIME23,Sample time specification ST2 and ST3"
|
|
hexmask.long.word 0x4 16.--25. 1. "SAMPLE_TIME3,Sample time3"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SAMPLE_TIME2,Sample time2"
|
|
line.long 0x8 "RANGE_THRES,Global range detect threshold register."
|
|
hexmask.long.word 0x8 16.--31. 1. "RANGE_HIGH,High threshold for range detect."
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "RANGE_LOW,Low threshold for range detect."
|
|
line.long 0xC "RANGE_COND,Global range detect mode register."
|
|
bitfld.long 0xC 30.--31. "RANGE_COND,Range condition select." "0: result < RANGE_LOW,1: RANGE_LOW <= result < RANGE_HIGH,2: RANGE_HIGH <= result,3: result < RANGE_LOW || RANGE_HIGH <= result"
|
|
line.long 0x10 "CHAN_EN,Enable bits for the channels"
|
|
hexmask.long.word 0x10 0.--15. 1. "CHAN_EN,Channel enable."
|
|
line.long 0x14 "START_CTRL,Start control register (firmware trigger)."
|
|
bitfld.long 0x14 0. "FW_TRIGGER,When firmware writes a 1 here it will trigger the next scan of enabled channels hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after.." "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "CHAN_CONFIG[$1],Channel configuration register."
|
|
bitfld.long 0x0 31. "DSI_OUT_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "NEG_ADDR_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--22. "NEG_PORT_ADDR,N/A" "0: SARMUX pins.,?,?,?,?,5: AROUTE virtual port2 (VPORT2),6: AROUTE virtual port1 (VPORT1),7: SARMUX virtual port (VPORT0)"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "NEG_PIN_ADDR,Address of the neg pin to be sampled by this channel." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "SAMPLE_TIME_SEL,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10. "AVG_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIFFERENTIAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "POS_PORT_ADDR,N/A" "0: SARMUX pins.,1: CTB0,2: CTB1,3: CTB2,4: CTB3,5: AROUTE virtual port2 (VPORT2),6: AROUTE virtual port1 (VPORT1),7: SARMUX virtual port (VPORT0)"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "POS_PIN_ADDR,Address of the pin to be sampled by this channel (connected to Vplus)." "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x100)++0x3
|
|
line.long 0x0 "CHAN_WORK[$1],Channel working data register"
|
|
bitfld.long 0x0 31. "CHAN_WORK_UPDATED_MIR,mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "CHAN_WORK_NEWVALUE_MIR,mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "WORK,SAR conversion working data of the channel. The data is written here right after sampling this channel. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1."
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x180)++0x3
|
|
line.long 0x0 "CHAN_RESULT[$1],Channel result data register"
|
|
bitfld.long 0x0 31. "CHAN_RESULT_UPDATED_MIR,mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_RANGE_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_SATURATE_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "CHAN_RESULT_NEWVALUE_MIR,mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RESULT,SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1."
|
|
repeat.end
|
|
rgroup.long 0x200++0xF
|
|
line.long 0x0 "CHAN_WORK_UPDATED,Channel working data register 'updated' bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "CHAN_WORK_UPDATED,If set the corresponding WORK register was updated i.e. was already sampled during the current scan and in case of Interleaved averaging reached the averaging count. If this bit is low then either the channel is not enabled or the.."
|
|
line.long 0x4 "CHAN_RESULT_UPDATED,Channel result data register 'updated' bits"
|
|
hexmask.long.word 0x4 0.--15. 1. "CHAN_RESULT_UPDATED,If set the corresponding RESULT register was updated i.e. was sampled during the previous scan and in case of Interleaved averaging reached the averaging count. If this bit is low then either the channel is not enabled or the.."
|
|
line.long 0x8 "CHAN_WORK_NEWVALUE,Channel working data register 'new value' bits"
|
|
hexmask.long.word 0x8 0.--15. 1. "CHAN_WORK_NEWVALUE,If set the corresponding WORK data received a new value i.e. was already sampled during the current scan and data was valid."
|
|
line.long 0xC "CHAN_RESULT_NEWVALUE,Channel result data register 'new value' bits"
|
|
hexmask.long.word 0xC 0.--15. 1. "CHAN_RESULT_NEWVALUE,If set the corresponding RESULT data received a new value i.e. was sampled during the last scan and data was valid."
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "INTR,Interrupt request register."
|
|
bitfld.long 0x0 7. "INJ_COLLISION_INTR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INJ_RANGE_INTR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "INJ_SATURATE_INTR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "INJ_EOC_INTR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DSI_COLLISION_INTR,This interrupt is set when a hardware trigger signal is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the hardware trigger has been completed i.e. not when the preceding scan with which.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FW_COLLISION_INTR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OVERFLOW_INTR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EOS_INTR,N/A" "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x4 7. "INJ_COLLISION_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "INJ_RANGE_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "INJ_SATURATE_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "INJ_EOC_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DSI_COLLISION_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "FW_COLLISION_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OVERFLOW_SET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EOS_SET,N/A" "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register."
|
|
bitfld.long 0x8 7. "INJ_COLLISION_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "INJ_RANGE_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "INJ_SATURATE_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "INJ_EOC_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DSI_COLLISION_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "FW_COLLISION_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "OVERFLOW_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "EOS_MASK,N/A" "0,1"
|
|
rgroup.long 0x21C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 7. "INJ_COLLISION_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INJ_RANGE_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "INJ_SATURATE_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "INJ_EOC_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DSI_COLLISION_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FW_COLLISION_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OVERFLOW_MASKED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EOS_MASKED,N/A" "0,1"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "SATURATE_INTR,Saturate interrupt request register."
|
|
hexmask.long.word 0x0 0.--15. 1. "SATURATE_INTR,Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF this is an indication that the ADC likely saturated. Write with '1' to clear bit."
|
|
line.long 0x4 "SATURATE_INTR_SET,Saturate interrupt set request register"
|
|
hexmask.long.word 0x4 0.--15. 1. "SATURATE_SET,Write with '1' to set corresponding bit in interrupt request register."
|
|
line.long 0x8 "SATURATE_INTR_MASK,Saturate interrupt mask register."
|
|
hexmask.long.word 0x8 0.--15. 1. "SATURATE_MASK,Mask bit for corresponding bit in interrupt request register."
|
|
rgroup.long 0x22C++0x3
|
|
line.long 0x0 "SATURATE_INTR_MASKED,Saturate interrupt masked request register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SATURATE_MASKED,Logical and of corresponding request and mask bits."
|
|
group.long 0x230++0xB
|
|
line.long 0x0 "RANGE_INTR,Range detect interrupt request register."
|
|
hexmask.long.word 0x0 0.--15. 1. "RANGE_INTR,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit."
|
|
line.long 0x4 "RANGE_INTR_SET,Range detect interrupt set request register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RANGE_SET,Write with '1' to set corresponding bit in interrupt request register."
|
|
line.long 0x8 "RANGE_INTR_MASK,Range detect interrupt mask register."
|
|
hexmask.long.word 0x8 0.--15. 1. "RANGE_MASK,Mask bit for corresponding bit in interrupt request register."
|
|
rgroup.long 0x23C++0x7
|
|
line.long 0x0 "RANGE_INTR_MASKED,Range interrupt masked request register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RANGE_MASKED,Logical and of corresponding request and mask bits."
|
|
line.long 0x4 "INTR_CAUSE,Interrupt cause register"
|
|
bitfld.long 0x4 31. "RANGE_MASKED_RED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "SATURATE_MASKED_RED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "INJ_COLLISION_MASKED_MIR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "INJ_RANGE_MASKED_MIR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "INJ_SATURATE_MASKED_MIR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "INJ_EOC_MASKED_MIR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DSI_COLLISION_MASKED_MIR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "FW_COLLISION_MASKED_MIR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OVERFLOW_MASKED_MIR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EOS_MASKED_MIR,N/A" "0,1"
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "INJ_CHAN_CONFIG,Injection channel configuration register."
|
|
bitfld.long 0x0 31. "INJ_START_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "INJ_TAILGATING,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "INJ_SAMPLE_TIME_SEL,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10. "INJ_AVG_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "INJ_DIFFERENTIAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "INJ_PORT_ADDR,N/A" "0: SARMUX pins.,1: CTB0,2: CTB1,3: CTB2,4: CTB3,?,6: AROUTE virtual port,7: SARMUX virtual port"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "INJ_PIN_ADDR,N/A" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x290++0x3
|
|
line.long 0x0 "INJ_RESULT,Injection channel result register"
|
|
bitfld.long 0x0 31. "INJ_EOC_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "INJ_RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "INJ_SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "INJ_COLLISION_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "INJ_NEWVALUE,The data in this register received a new value (only relevant for UAB this bit shows the value of the UAB valid bit). This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "INJ_RESULT,SAR conversion result of the channel. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1."
|
|
rgroup.long 0x2A0++0x7
|
|
line.long 0x0 "STATUS,Current status of internal SAR registers (mostly for debug)"
|
|
bitfld.long 0x0 31. "BUSY,If high then the SAR is busy with a conversion. This bit is always high when CONTINUOUS is set. Firmware should wait for this bit to be low before putting the SAR in power down." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SW_VREF_NEG,the current switch status including DSI and sequencer controls of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL). This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "CUR_CHAN,current channel being sampled (channel 16 indicates the injection channel) only valid if BUSY. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1."
|
|
line.long 0x4 "AVG_STAT,Current averaging status (for debug)"
|
|
hexmask.long.byte 0x4 24.--31. 1. "CUR_AVG_CNT,the current value of the averaging counter. Note that the value shown is updated after the sampling time and therefore runs ahead of the accumulator update. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1."
|
|
newline
|
|
bitfld.long 0x4 23. "INTRLV_BUSY,If high then the SAR is in the middle of Interleaved averaging spanning several scans. While this bit is high the Firmware should not make any changes to the configuration registers otherwise some results may be incorrect. Note that the.." "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "CUR_AVG_ACCU,the current value of the averaging accumulator. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1."
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "MUX_SWITCH0,SARMUX Firmware switch controls"
|
|
bitfld.long 0x0 29. "MUX_FW_P7_COREIO3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "MUX_FW_P6_COREIO2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "MUX_FW_P5_COREIO1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "MUX_FW_P4_COREIO0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "MUX_FW_SARBUS1_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "MUX_FW_SARBUS0_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "MUX_FW_SARBUS1_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "MUX_FW_SARBUS0_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MUX_FW_AMUXBUSB_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "MUX_FW_AMUXBUSA_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MUX_FW_AMUXBUSB_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "MUX_FW_AMUXBUSA_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MUX_FW_TEMP_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MUX_FW_VSSA_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MUX_FW_P7_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "MUX_FW_P6_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MUX_FW_P5_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "MUX_FW_P4_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MUX_FW_P3_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "MUX_FW_P2_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MUX_FW_P1_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MUX_FW_P0_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MUX_FW_P7_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "MUX_FW_P6_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MUX_FW_P5_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MUX_FW_P4_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MUX_FW_P3_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MUX_FW_P2_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MUX_FW_P1_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MUX_FW_P0_VPLUS,N/A" "0,1"
|
|
line.long 0x4 "MUX_SWITCH_CLEAR0,SARMUX Firmware switch control clear"
|
|
bitfld.long 0x4 29. "MUX_FW_P7_COREIO3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "MUX_FW_P6_COREIO2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "MUX_FW_P5_COREIO1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "MUX_FW_P4_COREIO0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "MUX_FW_SARBUS1_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "MUX_FW_SARBUS0_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "MUX_FW_SARBUS1_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "MUX_FW_SARBUS0_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "MUX_FW_AMUXBUSB_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "MUX_FW_AMUXBUSA_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "MUX_FW_AMUXBUSB_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "MUX_FW_AMUXBUSA_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MUX_FW_TEMP_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MUX_FW_VSSA_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "MUX_FW_P7_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "MUX_FW_P6_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MUX_FW_P5_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "MUX_FW_P4_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MUX_FW_P3_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "MUX_FW_P2_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MUX_FW_P1_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "MUX_FW_P0_VMINUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MUX_FW_P7_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "MUX_FW_P6_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MUX_FW_P5_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "MUX_FW_P4_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MUX_FW_P3_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MUX_FW_P2_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MUX_FW_P1_VPLUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "MUX_FW_P0_VPLUS,N/A" "0,1"
|
|
group.long 0x344++0x3
|
|
line.long 0x0 "MUX_SWITCH_SQ_CTRL,SARMUX switch Sar Sequencer control"
|
|
bitfld.long 0x0 23. "MUX_SQ_CTRL_SARBUS1,for sarbus1 switch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "MUX_SQ_CTRL_SARBUS0,for sarbus0 switch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MUX_SQ_CTRL_AMUXBUSB,for amuxbusb switches" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "MUX_SQ_CTRL_AMUXBUSA,for amuxbusa switch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MUX_SQ_CTRL_TEMP,for temp switch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MUX_SQ_CTRL_VSSA,for vssa switch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MUX_SQ_CTRL_P7,for P7 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "MUX_SQ_CTRL_P6,for P6 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MUX_SQ_CTRL_P5,for P5 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MUX_SQ_CTRL_P4,for P4 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MUX_SQ_CTRL_P3,for P3 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MUX_SQ_CTRL_P2,for P2 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MUX_SQ_CTRL_P1,for P1 switches" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MUX_SQ_CTRL_P0,for P0 switches" "0,1"
|
|
rgroup.long 0x348++0x3
|
|
line.long 0x0 "MUX_SWITCH_STATUS,SARMUX switch status"
|
|
bitfld.long 0x0 25. "MUX_FW_SARBUS1_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "MUX_FW_SARBUS0_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "MUX_FW_SARBUS1_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "MUX_FW_SARBUS0_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MUX_FW_AMUXBUSB_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "MUX_FW_AMUXBUSA_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MUX_FW_AMUXBUSB_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "MUX_FW_AMUXBUSA_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MUX_FW_TEMP_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MUX_FW_VSSA_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MUX_FW_P7_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "MUX_FW_P6_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MUX_FW_P5_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "MUX_FW_P4_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MUX_FW_P3_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "MUX_FW_P2_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MUX_FW_P1_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MUX_FW_P0_VMINUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MUX_FW_P7_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "MUX_FW_P6_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MUX_FW_P5_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MUX_FW_P4_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MUX_FW_P3_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MUX_FW_P2_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MUX_FW_P1_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MUX_FW_P0_VPLUS,switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1." "0,1"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "SCB (Serial Communication Block (SPI/UART/I2C))"
|
|
base ad:0x0
|
|
sif (cpuis("CY8C6??6*")||cpuis("CYB06??6*")||cpuis("CYS06??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??7*")||cpuis("CYS06??7*"))
|
|
tree "SCB0"
|
|
base ad:0x40610000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
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bitfld.long 0x8 4. "PARITY,N/A" "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
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bitfld.long 0x0 4. "S_READ,N/A" "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
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bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
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bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
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group.long 0xE88++0x3
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xEC0++0x3
|
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
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group.long 0xEC8++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
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|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
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line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
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|
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
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|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
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|
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
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|
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bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
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|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
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|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
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|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
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|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
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|
newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
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|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
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|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
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|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
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|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
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|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
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newline
|
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bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
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|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
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bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CYB06??6*")||cpuis("CYS06??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??7*")||cpuis("CYS06??7*"))
|
|
tree "SCB1"
|
|
base ad:0x40620000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
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bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
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newline
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bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
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rgroup.long 0x4++0x3
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line.long 0x0 "STATUS,Generic status"
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bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
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group.long 0x8++0x3
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line.long 0x0 "CMD_RESP_CTRL,Command/response control"
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hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
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newline
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
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rgroup.long 0xC++0x3
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line.long 0x0 "CMD_RESP_STATUS,Command/response status"
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bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
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newline
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
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newline
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
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newline
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
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group.long 0x20++0x3
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line.long 0x0 "SPI_CTRL,SPI control"
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bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
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newline
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bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
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newline
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bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
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newline
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bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
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newline
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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newline
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bitfld.long 0x0 3. "CPOL,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "CPHA,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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newline
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "SPI_STATUS,SPI status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
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newline
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bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
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group.long 0x40++0xB
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line.long 0x0 "UART_CTRL,UART control"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
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bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
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newline
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bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
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newline
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bitfld.long 0x4 4. "PARITY,N/A" "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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newline
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
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newline
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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newline
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
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newline
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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newline
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
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newline
|
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
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newline
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bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
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newline
|
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bitfld.long 0x8 4. "PARITY,N/A" "0,1"
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newline
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
|
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
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group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
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newline
|
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
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newline
|
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
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newline
|
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bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
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newline
|
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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newline
|
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
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newline
|
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
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newline
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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newline
|
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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newline
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
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newline
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
|
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newline
|
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
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rgroup.long 0x64++0x3
|
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line.long 0x0 "I2C_STATUS,I2C status"
|
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
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newline
|
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "S_READ,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
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newline
|
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
|
|
line.long 0x0 "I2C_M_CMD,I2C master command"
|
|
bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
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newline
|
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
|
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line.long 0x4 "I2C_S_CMD,I2C slave command"
|
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
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newline
|
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
|
|
line.long 0x8 "I2C_CFG,I2C configuration"
|
|
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
|
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newline
|
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
|
|
group.long 0x200++0x7
|
|
line.long 0x0 "TX_CTRL,Transmitter control"
|
|
bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
|
|
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
|
|
newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
|
bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
wgroup.long 0x240++0x3
|
|
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "RX_CTRL,Receiver control"
|
|
bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
|
|
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
|
|
rgroup.long 0x308++0x3
|
|
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
|
bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "RX_MATCH,Slave address and mask"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
|
|
rgroup.long 0x340++0x7
|
|
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
|
|
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
|
hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
|
|
rgroup.long 0xE00++0x3
|
|
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
|
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xE8C++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xEC0++0x3
|
|
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CYB06??6*")||cpuis("CYS06??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??7*")||cpuis("CYS06??7*"))
|
|
tree "SCB2"
|
|
base ad:0x40630000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
|
|
newline
|
|
bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
|
|
newline
|
|
bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "I2C_STATUS,I2C status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 5. "M_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "S_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
|
|
group.long 0x68++0xB
|
|
line.long 0x0 "I2C_M_CMD,I2C master command"
|
|
bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
|
|
line.long 0x4 "I2C_S_CMD,I2C slave command"
|
|
bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
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newline
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
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newline
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
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newline
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
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group.long 0xE88++0x3
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
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group.long 0xEC8++0x3
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xECC++0x3
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xF00++0xB
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line.long 0x0 "INTR_M,Master interrupt request"
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bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xF0C++0x3
|
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
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bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xF40++0xB
|
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line.long 0x0 "INTR_S,Slave interrupt request"
|
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bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
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newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
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newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
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newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
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newline
|
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
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line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
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bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CYB06??6*")||cpuis("CYS06??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??7*")||cpuis("CYS06??7*"))
|
|
tree "SCB3"
|
|
base ad:0x40640000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
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|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
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newline
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
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newline
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
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newline
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bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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newline
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
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newline
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
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newline
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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newline
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
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newline
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
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newline
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "S_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
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newline
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bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
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newline
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
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newline
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
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newline
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
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newline
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
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newline
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
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hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
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newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
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newline
|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
|
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
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group.long 0xE88++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xEC0++0x3
|
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
|
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group.long 0xEC8++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
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line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
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line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
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newline
|
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
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newline
|
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bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
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|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
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newline
|
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bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
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newline
|
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bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
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line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CYB06??6*")||cpuis("CYS06??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??7*")||cpuis("CYS06??7*"))
|
|
tree "SCB4"
|
|
base ad:0x40650000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
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group.long 0x20++0x3
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line.long 0x0 "SPI_CTRL,SPI control"
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bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
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newline
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bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
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newline
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bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
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newline
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bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
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newline
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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bitfld.long 0x0 3. "CPOL,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "CPHA,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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newline
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "SPI_STATUS,SPI status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
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bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
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group.long 0x40++0xB
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line.long 0x0 "UART_CTRL,UART control"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
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bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
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newline
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bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
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newline
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bitfld.long 0x4 4. "PARITY,N/A" "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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newline
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
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newline
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
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newline
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bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
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newline
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bitfld.long 0x8 4. "PARITY,N/A" "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
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newline
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
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newline
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
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newline
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bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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newline
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
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newline
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
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newline
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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newline
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
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newline
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
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newline
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "S_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
|
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bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
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newline
|
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bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
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newline
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
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newline
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
|
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
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newline
|
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
|
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newline
|
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
|
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newline
|
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
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group.long 0x200++0x7
|
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line.long 0x0 "TX_CTRL,Transmitter control"
|
|
bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
|
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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|
rgroup.long 0x208++0x3
|
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
|
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
wgroup.long 0x240++0x3
|
|
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "RX_CTRL,Receiver control"
|
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bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
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newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
|
|
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
|
|
newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
|
|
rgroup.long 0x308++0x3
|
|
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
|
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "RX_MATCH,Slave address and mask"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
|
|
rgroup.long 0x340++0x7
|
|
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
|
|
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
|
hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
|
|
rgroup.long 0xE00++0x3
|
|
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
|
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xE8C++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xEC0++0x3
|
|
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
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|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CYB06??6*")||cpuis("CYS06??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??7*")||cpuis("CYS06??7*"))
|
|
tree "SCB5"
|
|
base ad:0x40660000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
|
|
newline
|
|
bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
|
|
newline
|
|
bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "I2C_STATUS,I2C status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 5. "M_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "S_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
|
|
group.long 0x68++0xB
|
|
line.long 0x0 "I2C_M_CMD,I2C master command"
|
|
bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
|
|
line.long 0x4 "I2C_S_CMD,I2C slave command"
|
|
bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
|
|
line.long 0x8 "I2C_CFG,I2C configuration"
|
|
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
|
|
group.long 0x200++0x7
|
|
line.long 0x0 "TX_CTRL,Transmitter control"
|
|
bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
|
|
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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|
wgroup.long 0x240++0x3
|
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
|
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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|
rgroup.long 0x308++0x3
|
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
|
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hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
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|
rgroup.long 0x340++0x7
|
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
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hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
|
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
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group.long 0xE88++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
|
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group.long 0xEC8++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xECC++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xF00++0xB
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line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
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line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
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|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
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line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CYB06??6*")||cpuis("CYS06??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??7*")||cpuis("CYS06??7*"))
|
|
tree "SCB6"
|
|
base ad:0x40670000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
|
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newline
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
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newline
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
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newline
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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newline
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
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newline
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
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newline
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "S_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
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newline
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bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
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newline
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
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newline
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
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newline
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
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newline
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
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newline
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
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group.long 0xE88++0x3
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
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group.long 0xEC8++0x3
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xECC++0x3
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xF00++0xB
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line.long 0x0 "INTR_M,Master interrupt request"
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bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
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line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
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|
newline
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
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newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CYB06??6*")||cpuis("CYS06??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??7*")||cpuis("CYS06??7*"))
|
|
tree "SCB7"
|
|
base ad:0x40680000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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|
newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
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newline
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bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
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|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
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|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
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newline
|
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bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
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|
newline
|
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bitfld.long 0x4 4. "PARITY,N/A" "0,1"
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|
newline
|
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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|
newline
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
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|
newline
|
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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|
newline
|
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
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|
newline
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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newline
|
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
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|
newline
|
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
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|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
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newline
|
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
|
|
newline
|
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
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|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
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|
group.long 0x60++0x3
|
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line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
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|
newline
|
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bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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|
newline
|
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
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|
newline
|
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
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newline
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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|
newline
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
|
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newline
|
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
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newline
|
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "I2C_STATUS,I2C status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
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|
newline
|
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 4. "S_READ,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
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|
group.long 0x68++0xB
|
|
line.long 0x0 "I2C_M_CMD,I2C master command"
|
|
bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
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newline
|
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
|
|
line.long 0x4 "I2C_S_CMD,I2C slave command"
|
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
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|
newline
|
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
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|
line.long 0x8 "I2C_CFG,I2C configuration"
|
|
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
|
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newline
|
|
bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
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|
group.long 0x200++0x7
|
|
line.long 0x0 "TX_CTRL,Transmitter control"
|
|
bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
|
|
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
|
|
newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
|
bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
wgroup.long 0x240++0x3
|
|
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "RX_CTRL,Receiver control"
|
|
bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
|
|
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
|
|
rgroup.long 0x308++0x3
|
|
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
|
bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "RX_MATCH,Slave address and mask"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
|
|
rgroup.long 0x340++0x7
|
|
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
|
|
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
|
hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
|
|
rgroup.long 0xE00++0x3
|
|
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
|
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xE8C++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xEC0++0x3
|
|
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CYB06??6*")||cpuis("CYS06??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??7*")||cpuis("CYS06??7*"))
|
|
tree "SCB8"
|
|
base ad:0x40690000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
|
|
newline
|
|
bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
|
|
newline
|
|
bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "I2C_STATUS,I2C status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 5. "M_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "S_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
|
|
group.long 0x68++0xB
|
|
line.long 0x0 "I2C_M_CMD,I2C master command"
|
|
bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
|
|
line.long 0x4 "I2C_S_CMD,I2C slave command"
|
|
bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
|
|
line.long 0x8 "I2C_CFG,I2C configuration"
|
|
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
|
|
group.long 0x200++0x7
|
|
line.long 0x0 "TX_CTRL,Transmitter control"
|
|
bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
|
|
newline
|
|
bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
|
|
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
|
bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
wgroup.long 0x240++0x3
|
|
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "RX_CTRL,Receiver control"
|
|
bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
|
|
bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
|
|
rgroup.long 0x308++0x3
|
|
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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|
group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
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|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
|
|
rgroup.long 0x340++0x7
|
|
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
|
|
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
|
hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
|
|
rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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|
newline
|
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
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|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xE8C++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xEC0++0x3
|
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
|
|
group.long 0xEC8++0x3
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
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line.long 0x0 "INTR_M,Master interrupt request"
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|
bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
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|
newline
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xF0C++0x3
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
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bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
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line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
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newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
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newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
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newline
|
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
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newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
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line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
tree "SCB0"
|
|
base ad:0x40600000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
|
|
newline
|
|
bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
|
|
newline
|
|
bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
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newline
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "S_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
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newline
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bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
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newline
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
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newline
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
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newline
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
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newline
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
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newline
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
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group.long 0xE88++0x3
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
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group.long 0xEC8++0x3
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xECC++0x3
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xF00++0xB
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line.long 0x0 "INTR_M,Master interrupt request"
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bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xF0C++0x3
|
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
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bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
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line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
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newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
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newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
tree "SCB1"
|
|
base ad:0x40610000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
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|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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|
newline
|
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x4 4. "PARITY,N/A" "0,1"
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|
newline
|
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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newline
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
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|
newline
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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|
newline
|
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
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newline
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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newline
|
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
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|
newline
|
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bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
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|
newline
|
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
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|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
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|
newline
|
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
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|
newline
|
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
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group.long 0x60++0x3
|
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line.long 0x0 "I2C_CTRL,I2C control"
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|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
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newline
|
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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newline
|
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
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newline
|
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
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newline
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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newline
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
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newline
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "I2C_STATUS,I2C status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
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|
newline
|
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 4. "S_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
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|
group.long 0x68++0xB
|
|
line.long 0x0 "I2C_M_CMD,I2C master command"
|
|
bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
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newline
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
|
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
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newline
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
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|
line.long 0x8 "I2C_CFG,I2C configuration"
|
|
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
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newline
|
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
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|
newline
|
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
|
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newline
|
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
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group.long 0x200++0x7
|
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line.long 0x0 "TX_CTRL,Transmitter control"
|
|
bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
|
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
|
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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|
newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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|
rgroup.long 0x208++0x3
|
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
|
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
wgroup.long 0x240++0x3
|
|
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
|
|
group.long 0x300++0x7
|
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line.long 0x0 "RX_CTRL,Receiver control"
|
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bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
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newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
|
|
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
|
|
newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
|
|
rgroup.long 0x308++0x3
|
|
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "RX_MATCH,Slave address and mask"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
|
|
rgroup.long 0x340++0x7
|
|
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
|
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
|
hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
|
|
rgroup.long 0xE00++0x3
|
|
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xE8C++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xEC0++0x3
|
|
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
tree "SCB2"
|
|
base ad:0x40620000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
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|
newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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|
newline
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
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|
newline
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
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|
newline
|
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
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newline
|
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bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
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|
newline
|
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bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
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|
newline
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bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
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|
newline
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
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rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
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group.long 0x8++0x3
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line.long 0x0 "CMD_RESP_CTRL,Command/response control"
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hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
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newline
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
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rgroup.long 0xC++0x3
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line.long 0x0 "CMD_RESP_STATUS,Command/response status"
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|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
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|
newline
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
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newline
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
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|
newline
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
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group.long 0x20++0x3
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line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
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newline
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bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
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newline
|
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bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
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newline
|
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bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
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newline
|
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
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newline
|
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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newline
|
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bitfld.long 0x0 3. "CPOL,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 2. "CPHA,N/A" "0,1"
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newline
|
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
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|
rgroup.long 0x24++0x3
|
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line.long 0x0 "SPI_STATUS,SPI status"
|
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
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newline
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bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
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newline
|
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bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
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|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
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bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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newline
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
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newline
|
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
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newline
|
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
|
|
newline
|
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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newline
|
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "PARITY,N/A" "0,1"
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|
newline
|
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
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group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
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group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
|
|
newline
|
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
|
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newline
|
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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|
newline
|
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
|
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newline
|
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "I2C_STATUS,I2C status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
|
|
newline
|
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "S_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
|
|
group.long 0x68++0xB
|
|
line.long 0x0 "I2C_M_CMD,I2C master command"
|
|
bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
|
|
line.long 0x4 "I2C_S_CMD,I2C slave command"
|
|
bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
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|
newline
|
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
|
|
line.long 0x8 "I2C_CFG,I2C configuration"
|
|
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
|
|
group.long 0x200++0x7
|
|
line.long 0x0 "TX_CTRL,Transmitter control"
|
|
bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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|
newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
|
|
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
|
bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
wgroup.long 0x240++0x3
|
|
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "RX_CTRL,Receiver control"
|
|
bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
|
|
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
|
|
rgroup.long 0x308++0x3
|
|
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
|
bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "RX_MATCH,Slave address and mask"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
|
|
rgroup.long 0x340++0x7
|
|
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
|
|
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
|
hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
|
|
rgroup.long 0xE00++0x3
|
|
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
|
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xE8C++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xEC0++0x3
|
|
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
tree "SCB3"
|
|
base ad:0x40630000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
|
|
newline
|
|
bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
|
|
newline
|
|
bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "I2C_STATUS,I2C status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 5. "M_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "S_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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|
line.long 0x0 "I2C_M_CMD,I2C master command"
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|
bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
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newline
|
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bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
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newline
|
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bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
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newline
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
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newline
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
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newline
|
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
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newline
|
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
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|
newline
|
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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|
wgroup.long 0x240++0x3
|
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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|
newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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|
rgroup.long 0x308++0x3
|
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
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|
rgroup.long 0x340++0x7
|
|
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
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hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
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group.long 0xE88++0x3
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
|
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group.long 0xEC8++0x3
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xECC++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
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line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
|
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
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|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
tree "SCB4"
|
|
base ad:0x40640000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
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newline
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bitfld.long 0x8 4. "PARITY,N/A" "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
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newline
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
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bitfld.long 0x0 4. "S_READ,N/A" "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
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bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
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bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
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newline
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
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newline
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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|
newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x308++0x3
|
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
|
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hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
|
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
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rgroup.long 0x340++0x7
|
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
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hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
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rgroup.long 0xE00++0x3
|
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
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newline
|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
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group.long 0xE80++0x3
|
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
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group.long 0xE88++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xEC0++0x3
|
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
|
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group.long 0xEC8++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
tree "SCB5"
|
|
base ad:0x40650000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
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rgroup.long 0x4++0x3
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line.long 0x0 "STATUS,Generic status"
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bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
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group.long 0x8++0x3
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line.long 0x0 "CMD_RESP_CTRL,Command/response control"
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hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
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newline
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
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rgroup.long 0xC++0x3
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line.long 0x0 "CMD_RESP_STATUS,Command/response status"
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bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
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newline
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
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newline
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
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newline
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
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group.long 0x20++0x3
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line.long 0x0 "SPI_CTRL,SPI control"
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bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
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newline
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bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
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newline
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bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
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newline
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bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
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newline
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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newline
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bitfld.long 0x0 3. "CPOL,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "CPHA,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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newline
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "SPI_STATUS,SPI status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
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newline
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bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
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group.long 0x40++0xB
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line.long 0x0 "UART_CTRL,UART control"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
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bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
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newline
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bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
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newline
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bitfld.long 0x4 4. "PARITY,N/A" "0,1"
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newline
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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newline
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
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newline
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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newline
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
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newline
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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newline
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
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newline
|
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
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newline
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bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
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newline
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bitfld.long 0x8 4. "PARITY,N/A" "0,1"
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newline
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
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newline
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
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newline
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
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newline
|
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bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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newline
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
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newline
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
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newline
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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newline
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
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newline
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
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newline
|
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
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rgroup.long 0x64++0x3
|
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
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newline
|
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
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newline
|
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bitfld.long 0x0 4. "S_READ,N/A" "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
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newline
|
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
|
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line.long 0x0 "I2C_M_CMD,I2C master command"
|
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bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
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newline
|
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bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
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newline
|
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
|
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line.long 0x4 "I2C_S_CMD,I2C slave command"
|
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
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newline
|
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
|
|
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
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newline
|
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
|
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newline
|
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
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newline
|
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
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group.long 0x200++0x7
|
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line.long 0x0 "TX_CTRL,Transmitter control"
|
|
bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
|
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
|
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
|
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newline
|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
|
|
newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
wgroup.long 0x240++0x3
|
|
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "RX_CTRL,Receiver control"
|
|
bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
|
|
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
|
|
rgroup.long 0x308++0x3
|
|
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
|
bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
|
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "RX_MATCH,Slave address and mask"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
|
|
rgroup.long 0x340++0x7
|
|
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
|
|
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
|
hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
|
|
rgroup.long 0xE00++0x3
|
|
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
|
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xE8C++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xEC0++0x3
|
|
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
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|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
tree "SCB6"
|
|
base ad:0x40660000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
|
|
newline
|
|
bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
|
|
newline
|
|
bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "I2C_STATUS,I2C status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 5. "M_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "S_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
|
|
group.long 0x68++0xB
|
|
line.long 0x0 "I2C_M_CMD,I2C master command"
|
|
bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
|
|
line.long 0x4 "I2C_S_CMD,I2C slave command"
|
|
bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
|
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
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newline
|
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
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newline
|
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
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newline
|
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
|
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
|
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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wgroup.long 0x240++0x3
|
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
|
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
|
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rgroup.long 0x308++0x3
|
|
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
|
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hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
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rgroup.long 0x340++0x7
|
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
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hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
|
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
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newline
|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xEC0++0x3
|
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
|
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group.long 0xEC8++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xECC++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
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line.long 0x0 "INTR_M,Master interrupt request"
|
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bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
|
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
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line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
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|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CYB06??8*")||cpuis("CYS06??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??A*")||cpuis("CYS06??A*"))
|
|
tree "SCB7"
|
|
base ad:0x40670000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
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|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
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newline
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
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newline
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
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newline
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bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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newline
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
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newline
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
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newline
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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newline
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
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newline
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
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newline
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "S_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
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newline
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bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
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newline
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
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newline
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
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newline
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
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newline
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
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newline
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
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hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
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newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
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newline
|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
|
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
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group.long 0xE88++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xEC0++0x3
|
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
|
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group.long 0xEC8++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
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|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
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line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
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line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
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newline
|
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
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newline
|
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bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
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newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
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newline
|
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bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
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newline
|
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bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
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|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
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line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CYB06??8*")||cpuis("CYS06??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??A*")||cpuis("CYS06??A*"))
|
|
tree "SCB8"
|
|
base ad:0x40680000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
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group.long 0x20++0x3
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line.long 0x0 "SPI_CTRL,SPI control"
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bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
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newline
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bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
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newline
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bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
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newline
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bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
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newline
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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bitfld.long 0x0 3. "CPOL,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "CPHA,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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newline
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "SPI_STATUS,SPI status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
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bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
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group.long 0x40++0xB
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line.long 0x0 "UART_CTRL,UART control"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
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bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
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newline
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bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
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newline
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bitfld.long 0x4 4. "PARITY,N/A" "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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newline
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
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newline
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
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newline
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bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
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newline
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bitfld.long 0x8 4. "PARITY,N/A" "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
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newline
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
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newline
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
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newline
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bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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newline
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
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newline
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
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newline
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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newline
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
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newline
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
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newline
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "S_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
|
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bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
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newline
|
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bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
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newline
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
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newline
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
|
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
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newline
|
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
|
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newline
|
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
|
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newline
|
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
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group.long 0x200++0x7
|
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line.long 0x0 "TX_CTRL,Transmitter control"
|
|
bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
|
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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|
rgroup.long 0x208++0x3
|
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
|
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
wgroup.long 0x240++0x3
|
|
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "RX_CTRL,Receiver control"
|
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bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
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newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
|
|
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
|
|
newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
|
|
rgroup.long 0x308++0x3
|
|
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
|
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "RX_MATCH,Slave address and mask"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
|
|
rgroup.long 0x340++0x7
|
|
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
|
|
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
|
hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
|
|
rgroup.long 0xE00++0x3
|
|
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
|
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xE8C++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xEC0++0x3
|
|
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
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|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CYB06??8*")||cpuis("CYS06??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??A*")||cpuis("CYS06??A*"))
|
|
tree "SCB9"
|
|
base ad:0x40690000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
|
|
newline
|
|
bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
|
|
newline
|
|
bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "I2C_STATUS,I2C status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 5. "M_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "S_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
|
|
group.long 0x68++0xB
|
|
line.long 0x0 "I2C_M_CMD,I2C master command"
|
|
bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
|
|
line.long 0x4 "I2C_S_CMD,I2C slave command"
|
|
bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
|
|
line.long 0x8 "I2C_CFG,I2C configuration"
|
|
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
|
|
group.long 0x200++0x7
|
|
line.long 0x0 "TX_CTRL,Transmitter control"
|
|
bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
|
|
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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|
wgroup.long 0x240++0x3
|
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
|
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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|
rgroup.long 0x308++0x3
|
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
|
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hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
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|
rgroup.long 0x340++0x7
|
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
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hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
|
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
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group.long 0xE88++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
|
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group.long 0xEC8++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xECC++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xF00++0xB
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line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
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line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
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|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
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line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CYB06??8*")||cpuis("CYS06??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??A*")||cpuis("CYS06??A*"))
|
|
tree "SCB10 (Serial Communications Block (SPI/UART/I2C))"
|
|
base ad:0x406A0000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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|
newline
|
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
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|
newline
|
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
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|
newline
|
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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|
newline
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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|
newline
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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newline
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
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newline
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
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|
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|
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
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rgroup.long 0x64++0x3
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|
line.long 0x0 "I2C_STATUS,I2C status"
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|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
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newline
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "S_READ,N/A" "0,1"
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|
newline
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bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
|
|
bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
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newline
|
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bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
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newline
|
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bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
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newline
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
|
|
line.long 0x4 "I2C_S_CMD,I2C slave command"
|
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
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newline
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
|
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
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newline
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
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|
newline
|
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
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newline
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
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|
newline
|
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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|
bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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|
wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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|
newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x308++0x3
|
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
|
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
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rgroup.long 0x340++0x7
|
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
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hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
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rgroup.long 0xE00++0x3
|
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
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newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
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newline
|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
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group.long 0xE80++0x3
|
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
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group.long 0xE88++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xEC0++0x3
|
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
|
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group.long 0xEC8++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CYB06??8*")||cpuis("CYS06??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??A*")||cpuis("CYS06??A*"))
|
|
tree "SCB11 (Serial Communications Block (SPI/UART/I2C))"
|
|
base ad:0x406B0000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
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|
newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
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newline
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bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
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|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
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|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
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newline
|
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bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
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|
newline
|
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bitfld.long 0x4 4. "PARITY,N/A" "0,1"
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|
newline
|
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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|
newline
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
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|
newline
|
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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|
newline
|
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
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|
newline
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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newline
|
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
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|
newline
|
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
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|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
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newline
|
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
|
|
newline
|
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
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|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
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|
group.long 0x60++0x3
|
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line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
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|
newline
|
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bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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|
newline
|
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
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|
newline
|
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
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newline
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
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|
newline
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
|
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newline
|
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
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newline
|
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "I2C_STATUS,I2C status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
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|
newline
|
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 4. "S_READ,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
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|
group.long 0x68++0xB
|
|
line.long 0x0 "I2C_M_CMD,I2C master command"
|
|
bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
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newline
|
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
|
|
line.long 0x4 "I2C_S_CMD,I2C slave command"
|
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
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|
newline
|
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
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|
line.long 0x8 "I2C_CFG,I2C configuration"
|
|
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
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newline
|
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
|
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newline
|
|
bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
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|
group.long 0x200++0x7
|
|
line.long 0x0 "TX_CTRL,Transmitter control"
|
|
bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
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newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
|
|
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
|
|
newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
|
bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
wgroup.long 0x240++0x3
|
|
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "RX_CTRL,Receiver control"
|
|
bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
|
|
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
|
|
rgroup.long 0x308++0x3
|
|
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
|
bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "RX_MATCH,Slave address and mask"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
|
|
rgroup.long 0x340++0x7
|
|
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
|
|
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
|
hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
|
|
rgroup.long 0xE00++0x3
|
|
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
|
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xE8C++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xEC0++0x3
|
|
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CYB06??8*")||cpuis("CYS06??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??A*")||cpuis("CYS06??A*"))
|
|
tree "SCB12 (Serial Communications Block (SPI/UART/I2C))"
|
|
base ad:0x406C0000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,0': Block Disabled" "0: Block Disabled,1: Block Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states" "0: Do not block,1: Block"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO:." "0: Matching address does not go in RX FIFO,1: Match address does go in RX FIFO"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "BYTE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,This field determines if EZ mode is enabled or disabled for the SCB block" "0: EZ Mode Disabled,1: EZ Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block after the address phase" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)" "0: Internally clocked mode,1: Externally clocked mode"
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|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus.." "0,1"
|
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group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the SCB." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
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|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,N/A" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is sent to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is disabled"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: clock stretching is performed,1: a received data element byte the slave is.."
|
|
newline
|
|
bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,Only used for FIFO mode NOT EZ or CMD_RESP mode." "0: in Active/Sleep mode clock stretching is..,1: In Active/Sleep mode a received"
|
|
newline
|
|
bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0' clock stretching is used instead (till the RX FIFO is no longer full)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median filtering."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "I2C_STATUS,I2C status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1')."
|
|
newline
|
|
bitfld.long 0x0 5. "M_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "S_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the SCB is disabled BUS_BUSY is '0'. After.." "0,1"
|
|
group.long 0x68++0xB
|
|
line.long 0x0 "I2C_M_CMD,I2C master command"
|
|
bitfld.long 0x0 4. "M_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "M_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "M_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START." "0,1"
|
|
line.long 0x4 "I2C_S_CMD,I2C slave command"
|
|
bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode). This command has a.." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ and CMD_RESP mode this field should be set to '0' (it is only to be used in FIFO mode)." "0,1"
|
|
line.long 0x8 "I2C_CFG,I2C configuration"
|
|
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 12. "SCL_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4. "SDA_IN_FILT_SEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0: disable clk_scb,1: enable clk_scb,?,?"
|
|
group.long 0x200++0x7
|
|
line.long 0x0 "TX_CTRL,Transmitter control"
|
|
bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave.." "0: Normal operation mode,1: Open drain operation mode"
|
|
newline
|
|
bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
|
|
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
|
|
newline
|
|
bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
|
|
wgroup.long 0x240++0x3
|
|
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,N/A"
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "RX_CTRL,Receiver control"
|
|
bitfld.long 0x0 9. "MEDIAN,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'. For EZ and CMD_RESP this field must be set to '1'" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,N/A"
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,N/A" "0,1"
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newline
|
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bitfld.long 0x4 16. "CLEAR,N/A" "0,1"
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newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,N/A"
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,N/A"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,N/A"
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newline
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bitfld.long 0x0 15. "SR_VALID,N/A" "0,1"
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newline
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hexmask.long.word 0x0 0.--8. 1. "USED,N/A"
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,N/A"
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long.word 0x4 0.--15. 1. "DATA,N/A"
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
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group.long 0xE88++0x3
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
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|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request." "0,1"
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group.long 0xEC8++0x3
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xECC++0x3
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xF00++0xB
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line.long 0x0 "INTR_M,Master interrupt request"
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bitfld.long 0x0 9. "SPI_DONE,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,N/A" "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF0C++0x3
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
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bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xF40++0xB
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line.long 0x0 "INTR_S,Slave interrupt request"
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bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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newline
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bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
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newline
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. Firmware may decide to.." "0,1"
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newline
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO." "0,1"
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newline
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
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newline
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
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newline
|
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
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line.long 0x4 "INTR_S_SET,Slave interrupt set request"
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bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
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bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
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line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU write can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame is send to the RX FIFO. In SmartCard submode negatively.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,UART Frame error in received data frame." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,CPU read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
tree "SDHC (SD/eMMC Host Controller)"
|
|
base ad:0x0
|
|
tree "SDHC0"
|
|
base ad:0x40460000
|
|
tree "CORE (MMIO for Synopsys Mobile Storage Host Controller IP)"
|
|
base ad:0x40461000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SDMASA_R,SDMA System Address register"
|
|
hexmask.long 0x0 0.--31. 1. "BLOCKCNT_SDMASA,32-bit Block Count (SDMA System Address)"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "BLOCKSIZE_R,Block Size register"
|
|
bitfld.word 0x0 12.--14. "SDMA_BUF_BDARY,SDMA Buffer Boundary" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x0 0.--11. 1. "XFER_BLOCK_SIZE,Transfer Block Size"
|
|
line.word 0x2 "BLOCKCOUNT_R,16-bit Block Count register"
|
|
hexmask.word 0x2 0.--15. 1. "BLOCK_CNT,16-bit Block Count"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ARGUMENT_R,Argument register"
|
|
hexmask.long 0x0 0.--31. 1. "ARGUMENT,Command Argument"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "XFER_MODE_R,Transfer Mode register"
|
|
bitfld.word 0x0 8. "RESP_INT_DISABLE,Response Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "RESP_ERR_CHK_ENABLE,Response Error Check Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "RESP_TYPE,Response Type R1/R5" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "MULTI_BLK_SEL,Multi/Single Block Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "DATA_XFER_DIR,Data Transfer Direction Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2.--3. "AUTO_CMD_ENABLE,Auto Command Enable" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 1. "BLOCK_COUNT_ENABLE,Block Count Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "DMA_ENABLE,DMA Enable" "0,1"
|
|
line.word 0x2 "CMD_R,Command register"
|
|
hexmask.word.byte 0x2 8.--13. 1. "CMD_INDEX,Command Index"
|
|
newline
|
|
bitfld.word 0x2 6.--7. "CMD_TYPE,Command Type" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x2 5. "DATA_PRESENT_SEL,Data Present Select" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "CMD_IDX_CHK_ENABLE,Command Index Check Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 3. "CMD_CRC_CHK_ENABLE,Command CRC Check Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "SUB_CMD_FLAG,Sub Command Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0.--1. "RESP_TYPE_SELECT,Response Type Select" "0,1,2,3"
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "RESP01_R,Response Register 0/1"
|
|
hexmask.long 0x0 0.--31. 1. "RESP01,Command Response"
|
|
line.long 0x4 "RESP23_R,Response Register 2/3"
|
|
hexmask.long 0x4 0.--31. 1. "RESP23,Command Response"
|
|
line.long 0x8 "RESP45_R,Response Register 4/5"
|
|
hexmask.long 0x8 0.--31. 1. "RESP45,Command Response"
|
|
line.long 0xC "RESP67_R,Response Register 6/7"
|
|
hexmask.long 0xC 0.--31. 1. "RESP67,Command Response"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "BUF_DATA_R,Buffer Data Port Register"
|
|
hexmask.long 0x0 0.--31. 1. "BUF_DATA,Buffer Data"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "PSTATE_REG,Present State Register"
|
|
bitfld.long 0x0 28. "SUB_CMD_STAT,Sub Command Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "CMD_ISSU_ERR,Command Not Issued by Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "HOST_REG_VOL,Host Regulator Voltage Stable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "CMD_LINE_LVL,Command-Line Signal Level" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "DAT_3_0,DAT[3:0] Line Signal Level"
|
|
newline
|
|
bitfld.long 0x0 19. "WR_PROTECT_SW_LVL,Write Protect Switch Pin Level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CARD_DETECT_PIN_LEVEL,Card Detect Pin Level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CARD_STABLE,Card Stable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CARD_INSERTED,Card Inserted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BUF_RD_ENABLE,Buffer Read Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BUF_WR_ENABLE,Buffer Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RD_XFER_ACTIVE,Read Transfer Active" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "WR_XFER_ACTIVE,Write Transfer Active" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DAT_7_4,DAT[7:4] Line Signal Level"
|
|
newline
|
|
bitfld.long 0x0 2. "DAT_LINE_ACTIVE,DAT Line Active (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CMD_INHIBIT_DAT,Command Inhibit (DAT)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMD_INHIBIT,Command Inhibit (CMD)" "0,1"
|
|
group.byte 0x28++0x3
|
|
line.byte 0x0 "HOST_CTRL1_R,Host Control 1 Register"
|
|
bitfld.byte 0x0 7. "CARD_DETECT_SIG_SEL,Card Detect Signal Selection" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "CARD_DETECT_TEST_LVL,Card Detect Test Level" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "EXT_DAT_XFER,Extended Data Transfer Width" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3.--4. "DMA_SEL,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.byte 0x0 2. "HIGH_SPEED_EN,High Speed Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "DAT_XFER_WIDTH,Data Transfer Width" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "LED_CTRL,LED Control" "0,1"
|
|
line.byte 0x1 "PWR_CTRL_R,Power Control Register"
|
|
bitfld.byte 0x1 1.--3. "SD_BUS_VOL_VDD1,These bits are NON-operational (they can be written and read but they have no effect). In a generic HCI host these would select the card supply voltage. But for the applications targeted for this block it is assumed that the card.." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.byte 0x1 0. "SD_BUS_PWR_VDD1,SD Bus Power for VDD1" "0,1"
|
|
line.byte 0x2 "BGAP_CTRL_R,Block Gap Control Register"
|
|
bitfld.byte 0x2 3. "INT_AT_BGAP,Interrupt At Block Gap" "0,1"
|
|
newline
|
|
bitfld.byte 0x2 2. "RD_WAIT_CTRL,N/A" "0,1"
|
|
newline
|
|
bitfld.byte 0x2 1. "CONTINUE_REQ,Continue Request" "0,1"
|
|
newline
|
|
bitfld.byte 0x2 0. "STOP_BG_REQ,Stop At Block Gap Request" "0,1"
|
|
line.byte 0x3 "WUP_CTRL_R,Wakeup Control Register"
|
|
bitfld.byte 0x3 2. "WUP_CARD_REMOVAL,Wakeup Event Enable on SD Card Removal" "0,1"
|
|
newline
|
|
bitfld.byte 0x3 1. "WUP_CARD_INSERT,Wakeup Event Enable on SD Card Insertion" "0,1"
|
|
newline
|
|
bitfld.byte 0x3 0. "WUP_CARD_INT,Wakeup Event Enable on SDIO Card Interrupt (through DAT[1])." "0,1"
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "CLK_CTRL_R,Clock Control Register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "FREQ_SEL,SDCLK Frequency Select"
|
|
newline
|
|
bitfld.word 0x0 6.--7. "UPPER_FREQ_SEL,These bits specify the upper 2 bits of 10-bit SDCLK" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 5. "CLK_GEN_SELECT,Clock Generator Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PLL_ENABLE,PLL Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "SD_CLK_EN,SD/eMMC Clock Enable" "0,1"
|
|
newline
|
|
rbitfld.word 0x0 1. "INTERNAL_CLK_STABLE,Internal Clock Stable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INTERNAL_CLK_EN,Internal Clock Enable" "0,1"
|
|
group.byte 0x2E++0x1
|
|
line.byte 0x0 "TOUT_CTRL_R,Timeout Control Register"
|
|
hexmask.byte 0x0 0.--3. 1. "TOUT_CNT,N/A"
|
|
line.byte 0x1 "SW_RST_R,Software Reset Register"
|
|
bitfld.byte 0x1 2. "SW_RST_DAT,Software Reset For DAT line" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 1. "SW_RST_CMD,Software Reset For CMD line" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "SW_RST_ALL,Software Reset For All" "0,1"
|
|
group.word 0x30++0xB
|
|
line.word 0x0 "NORMAL_INT_STAT_R,Normal Interrupt Status Register"
|
|
rbitfld.word 0x0 15. "ERR_INTERRUPT,Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x0 14. "CQE_EVENT,Command Queuing Event" "0,1"
|
|
newline
|
|
rbitfld.word 0x0 13. "FX_EVENT,FX Event" "0,1"
|
|
newline
|
|
rbitfld.word 0x0 8. "CARD_INTERRUPT,Card Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "CARD_REMOVAL,Card Removal" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "CARD_INSERTION,Card Insertion" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "BUF_RD_READY,Buffer Read Ready" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "BUF_WR_READY,Buffer Write Ready" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DMA_INTERRUPT,DMA Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BGAP_EVENT,Block Gap Event" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "XFER_COMPLETE,Transfer Complete" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "CMD_COMPLETE,Command Complete" "0,1"
|
|
line.word 0x2 "ERROR_INT_STAT_R,Error Interrupt Status Register"
|
|
bitfld.word 0x2 12. "BOOT_ACK_ERR,Boot Acknowledgement Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 11. "RESP_ERR,Response Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 10. "TUNING_ERR,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x2 9. "ADMA_ERR,ADMA Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 8. "AUTO_CMD_ERR,Auto CMD Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "CUR_LMT_ERR,Current Limit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "DATA_END_BIT_ERR,Data End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 5. "DATA_CRC_ERR,Data CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "DATA_TOUT_ERR,Data Timeout Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 3. "CMD_IDX_ERR,Command Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "CMD_END_BIT_ERR,Command End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "CMD_CRC_ERR,Command CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "CMD_TOUT_ERR,Command Timeout Error" "0,1"
|
|
line.word 0x4 "NORMAL_INT_STAT_EN_R,Normal Interrupt Status Enable Register"
|
|
bitfld.word 0x4 14. "CQE_EVENT_STAT_EN,CQE Event Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 13. "FX_EVENT_STAT_EN,FX Event Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 12. "RE_TUNE_EVENT_STAT_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x4 11. "INT_C_STAT_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x4 10. "INT_B_STAT_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x4 9. "INT_A_STAT_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x4 8. "CARD_INTERRUPT_STAT_EN,Card Interrupt Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 7. "CARD_REMOVAL_STAT_EN,Card Removal Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 6. "CARD_INSERTION_STAT_EN,Card Insertion Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 5. "BUF_RD_READY_STAT_EN,Buffer Read Ready Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 4. "BUF_WR_READY_STAT_EN,Buffer Write Ready Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 3. "DMA_INTERRUPT_STAT_EN,DMA Interrupt Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 2. "BGAP_EVENT_STAT_EN,Block Gap Event Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 1. "XFER_COMPLETE_STAT_EN,Transfer Complete Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 0. "CMD_COMPLETE_STAT_EN,Command Complete Status Enable" "0,1"
|
|
line.word 0x6 "ERROR_INT_STAT_EN_R,Error Interrupt Status Enable Register"
|
|
bitfld.word 0x6 15. "VENDOR_ERR_STAT_EN3,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x6 14. "VENDOR_ERR_STAT_EN2,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x6 13. "VENDOR_ERR_STAT_EN1,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x6 12. "BOOT_ACK_ERR_STAT_EN,Boot Acknowledgment Error (eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 11. "RESP_ERR_STAT_EN,Response Error Status Enable (SD Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 10. "TUNING_ERR_STAT_EN,Tuning Error Status Enable (UHS-I Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 9. "ADMA_ERR_STAT_EN,ADMA Error Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 8. "AUTO_CMD_ERR_STAT_EN,Auto CMD Error Status Enable (SD/eMMC Mode only)." "0,1"
|
|
newline
|
|
bitfld.word 0x6 7. "CUR_LMT_ERR_STAT_EN,Current Limit Error Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 6. "DATA_END_BIT_ERR_STAT_EN,Data End Bit Error Status Enable (SD/eMMC Mode only)." "0,1"
|
|
newline
|
|
bitfld.word 0x6 5. "DATA_CRC_ERR_STAT_EN,Data CRC Error Status Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 4. "DATA_TOUT_ERR_STAT_EN,Data Timeout Error Status Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 3. "CMD_IDX_ERR_STAT_EN,Command Index Error Status Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 2. "CMD_END_BIT_ERR_STAT_EN,Command End Bit Error Status Enable (SD/eMMC Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x6 1. "CMD_CRC_ERR_STAT_EN,ommand CRC Error Status Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 0. "CMD_TOUT_ERR_STAT_EN,Command Timeout Error Status Enable (SD/eMMC Mode" "0,1"
|
|
line.word 0x8 "NORMAL_INT_SIGNAL_EN_R,Normal Interrupt Signal Enable Register"
|
|
bitfld.word 0x8 14. "CQE_EVENT_SIGNAL_EN,Command Queuing Engine Event Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 13. "FX_EVENT_SIGNAL_EN,FX Event Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 12. "RE_TUNE_EVENT_SIGNAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x8 11. "INT_C_SIGNAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x8 10. "INT_B_SIGNAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x8 9. "INT_A_SIGNAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x8 8. "CARD_INTERRUPT_SIGNAL_EN,Card Interrupt Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 7. "CARD_REMOVAL_SIGNAL_EN,Card Removal Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 6. "CARD_INSERTION_SIGNAL_EN,Card Insertion Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 5. "BUF_RD_READY_SIGNAL_EN,Buffer Read Ready Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 4. "BUF_WR_READY_SIGNAL_EN,Buffer Write Ready Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 3. "DMA_INTERRUPT_SIGNAL_EN,DMA Interrupt Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 2. "BGAP_EVENT_SIGNAL_EN,Block Gap Event Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 1. "XFER_COMPLETE_SIGNAL_EN,Transfer Complete Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 0. "CMD_COMPLETE_SIGNAL_EN,Command Complete Signal Enable" "0,1"
|
|
line.word 0xA "ERROR_INT_SIGNAL_EN_R,Error Interrupt Signal Enable Register"
|
|
bitfld.word 0xA 15. "VENDOR_ERR_SIGNAL_EN3,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0xA 14. "VENDOR_ERR_SIGNAL_EN2,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0xA 13. "VENDOR_ERR_SIGNAL_EN1,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0xA 12. "BOOT_ACK_ERR_SIGNAL_EN,Boot Acknowledgment Error (eMMC Mode only)." "0,1"
|
|
newline
|
|
bitfld.word 0xA 11. "RESP_ERR_SIGNAL_EN,Response Error Signal Enable (SD Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 10. "TUNING_ERR_SIGNAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0xA 9. "ADMA_ERR_SIGNAL_EN,ADMA Error Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0xA 8. "AUTO_CMD_ERR_SIGNAL_EN,Auto CMD Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 7. "CUR_LMT_ERR_SIGNAL_EN,Current Limit Error Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0xA 6. "DATA_END_BIT_ERR_SIGNAL_EN,Data End Bit Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 5. "DATA_CRC_ERR_SIGNAL_EN,Data CRC Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 4. "DATA_TOUT_ERR_SIGNAL_EN,Data Timeout Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 3. "CMD_IDX_ERR_SIGNAL_EN,Command Index Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 2. "CMD_END_BIT_ERR_SIGNAL_EN,Command End Bit Error Signal Enable (SD/eMMC Mode" "0,1"
|
|
newline
|
|
bitfld.word 0xA 1. "CMD_CRC_ERR_SIGNAL_EN,Command CRC Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 0. "CMD_TOUT_ERR_SIGNAL_EN,Command Timeout Error Signal Enable (SD/eMMC Mode" "0,1"
|
|
rgroup.word 0x3C++0x1
|
|
line.word 0x0 "AUTO_CMD_STAT_R,Auto CMD Status Register"
|
|
bitfld.word 0x0 7. "CMD_NOT_ISSUED_AUTO_CMD12,Command Not Issued By Auto CMD12 Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "AUTO_CMD_RESP_ERR,Auto CMD Response Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "AUTO_CMD_IDX_ERR,Auto CMD Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "AUTO_CMD_EBIT_ERR,Auto CMD End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "AUTO_CMD_CRC_ERR,Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "AUTO_CMD_TOUT_ERR,Auto CMD Timeout Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "AUTO_CMD12_NOT_EXEC,Auto CMD12 Not Executed" "0,1"
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HOST_CTRL2_R,Host Control 2 Register"
|
|
bitfld.word 0x0 15. "PRESET_VAL_ENABLE,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 14. "ASYNC_INT_ENABLE,Asynchronous Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "ADDRESSING,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 12. "HOST_VER4_ENABLE,Host Version 4 Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "CMD23_ENABLE,CMD23 Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "ADMA2_LEN_MODE,ADMA2 Length Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "UHS2_IF_ENABLE,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "SAMPLE_CLK_SEL,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "EXEC_TUNING,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4.--5. "DRV_STRENGTH_SEL,Driver Strength Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 3. "SIGNALING_EN,1.8V Signaling Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0.--2. "UHS_MODE_SEL,N/A" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x40++0xF
|
|
line.long 0x0 "CAPABILITIES1_R,Capabilities 1 Register - 0 to 31"
|
|
bitfld.long 0x0 30.--31. "SLOT_TYPE_R,Slot Type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 29. "ASYNC_INT_SUPPORT,Asynchronous Interrupt Support (SD Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "SYS_ADDR_64_V3,64-bit System Address Support for V3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SYS_ADDR_64_V4,64-bit System Address Support for V4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "VOLT_18,Voltage Support 1.8V" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "VOLT_30,Voltage Support 3.0V" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "VOLT_33,Voltage Support 3.3V" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SUS_RES_SUPPORT,Suspense/Resume Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "SDMA_SUPPORT,SDMA Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "HIGH_SPEED_SUPPORT,High Speed Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ADMA2_SUPPORT,ADMA2 Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "EMBEDDED_8_BIT,8-bit Support for Embedded Device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "MAX_BLK_LEN,N/A" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "BASE_CLK_FREQ,Base Clock Frequency for SD clock"
|
|
newline
|
|
bitfld.long 0x0 7. "TOUT_CLK_UNIT,Timeout Clock Unit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TOUT_CLK_FREQ,Timeout Clock Frequency"
|
|
line.long 0x4 "CAPABILITIES2_R,Capabilities Register - 32 to 63"
|
|
bitfld.long 0x4 28. "VDD2_18V_SUPPORT,1.8V VDD2 Support" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "ADMA3_SUPPORT,ADMA3 Support" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "CLK_MUL,Clock Multiplier"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "RE_TUNING_MODES,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 13. "USE_TUNING_SDR50,Use Tuning for SDR50 (UHS-I only)" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "RETUNE_CNT,N/A"
|
|
newline
|
|
bitfld.long 0x4 6. "DRV_TYPED,Driver Type D Support (UHS-I only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DRV_TYPEC,Driver Type C Support (UHS-I only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DRV_TYPEA,Driver Type A Support (UHS-I only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "UHS2_SUPPORT,UHS-II Support (UHS-II only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DDR50_SUPPORT,DDR50 Support (UHS-I only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "SDR104_SUPPORT,SDR104 Support (UHS-I only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SDR50_SUPPORT,SDR50 Support (UHS-I only)" "0,1"
|
|
line.long 0x8 "CURR_CAPABILITIES1_R,Current Capabilities Register - 0 to 31"
|
|
hexmask.long.byte 0x8 16.--23. 1. "MAX_CUR_18V,Maximum Current for 1.8V"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "MAX_CUR_30V,Maximum Current for 3.0V"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "MAX_CUR_33V,Maximum Current for 3.3V"
|
|
line.long 0xC "CURR_CAPABILITIES2_R,Maximum Current Capabilities Register - 32 to 63"
|
|
hexmask.long.byte 0xC 0.--7. 1. "MAX_CUR_VDD2_18V,Maximum Current for 1.8V VDD2"
|
|
wgroup.word 0x50++0x1
|
|
line.word 0x0 "FORCE_AUTO_CMD_STAT_R,Force Event Register for Auto CMD Error Status register"
|
|
bitfld.word 0x0 7. "FORCE_CMD_NOT_ISSUED_AUTO_CMD12,Force Event for Command Not Issued By Auto CMD12 Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "FORCE_AUTO_CMD_RESP_ERR,Force Event for Auto CMD Response Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "FORCE_AUTO_CMD_IDX_ERR,Force Event for Auto CMD Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "FORCE_AUTO_CMD_EBIT_ERR,Force Event for Auto CMD End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "FORCE_AUTO_CMD_CRC_ERR,Force Event for Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "FORCE_AUTO_CMD_TOUT_ERR,Force Event for Auto CMD Timeout Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "FORCE_AUTO_CMD12_NOT_EXEC,Force Event for Auto CMD12 Not Executed" "0,1"
|
|
group.word 0x52++0x1
|
|
line.word 0x0 "FORCE_ERROR_INT_STAT_R,Force Event Register for Error Interrupt Status"
|
|
bitfld.word 0x0 15. "FORCE_VENDOR_ERR3,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 14. "FORCE_VENDOR_ERR2,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "FORCE_VENDOR_ERR1,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 12. "FORCE_BOOT_ACK_ERR,Force Event for Boot Ack error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "FORCE_RESP_ERR,Force Event for Response Error (SD Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FORCE_TUNING_ERR,Force Event for Tuning Error (UHS-I Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "FORCE_ADMA_ERR,Force Event for ADMA Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "FORCE_AUTO_CMD_ERR,Force Event for Auto CMD Error (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "FORCE_CUR_LMT_ERR,Force Event for Current Limit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FORCE_DATA_END_BIT_ERR,Force Event for Data End Bit Error (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "FORCE_DATA_CRC_ERR,Force Event for Data CRC Error (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "FORCE_DATA_TOUT_ERR,Force Event for Data Timeout Error (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "FORCE_CMD_IDX_ERR,Force Event for Command Index Error (SD/eMMC Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "FORCE_CMD_END_BIT_ERR,Force Event for Command End Bit Error (SD/eMMC Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "FORCE_CMD_CRC_ERR,Force Event for Command CRC Error (SD/eMMC Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "FORCE_CMD_TOUT_ERR,Force Event for Command Timeout Error (SD/eMMC Mode" "0,1"
|
|
rgroup.byte 0x54++0x0
|
|
line.byte 0x0 "ADMA_ERR_STAT_R,ADMA Error Status Register"
|
|
bitfld.byte 0x0 2. "ADMA_LEN_ERR,ADMA Length Mismatch Error States" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0.--1. "ADMA_ERR_STATES,ADMA Error States" "0,1,2,3"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "ADMA_SA_LOW_R,ADMA System Address Register - Low"
|
|
hexmask.long 0x0 0.--31. 1. "ADMA_SA_LOW,ADMA System Address"
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "ADMA_ID_LOW_R,ADMA3 Integrated Descriptor Address Register - Low"
|
|
hexmask.long 0x0 0.--31. 1. "ADMA_ID_LOW,ADMA Integrated Descriptor Address"
|
|
rgroup.word 0xFE++0x1
|
|
line.word 0x0 "HOST_CNTRL_VERS_R,Host Controller Version"
|
|
hexmask.word.byte 0x0 8.--15. 1. "VENDOR_VERSION_NUM,N/A"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "SPEC_VERSION_NUM,N/A"
|
|
rgroup.long 0x180++0x7
|
|
line.long 0x0 "CQVER,Command Queuing Version register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "EMMC_VER_MAJOR,This bit indicates the eMMC major version (1st digit left of"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "EMMC_VER_MINOR,This bit indicates the eMMC minor version (1st digit right of"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "EMMC_VER_SUFFIX,This bit indicates the eMMC version suffix (2nd digit right of"
|
|
line.long 0x4 "CQCAP,Command Queuing Capabilities register"
|
|
bitfld.long 0x4 28. "CRYPTO_SUPPORT,Crypto Support" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "ITCFMUL,N/A"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "ITCFVAL,Internal Timer Clock Frequency Value (ITCFVAL)"
|
|
group.long 0x188++0x1B
|
|
line.long 0x0 "CQCFG,Command Queuing Configuration register"
|
|
bitfld.long 0x0 12. "DCMD_EN,This bit indicates to the hardware whether the Task" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TASK_DESC_SIZE,Bit Value Description" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CR_GENERAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CQ_EN,Enable command queuing engine (CQE)." "0,1"
|
|
line.long 0x4 "CQCTL,Command Queuing Control register"
|
|
bitfld.long 0x4 8. "CLR_ALL_TASKS,Clear all tasks" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "HALT,Halt request and resume" "0,1"
|
|
line.long 0x8 "CQIS,Command Queuing Interrupt Status register"
|
|
bitfld.long 0x8 5. "ICCE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "GCE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "TCL,Task cleared interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "RED,Response error detected interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TCC,Task complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "HAC,Halt complete interrupt" "0,1"
|
|
line.long 0xC "CQISE,Command Queuing Interrupt Status Enable register"
|
|
bitfld.long 0xC 5. "ICCE_STE,Invalid Crypto Configuration Error interrupt status enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "GCE_STE,General Crypto Error interrupt status enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "TCL_STE,Task cleared interrupt status enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "RED_STE,Response error detected interrupt status enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TCC_STE,Task complete interrupt status enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "HAC_STE,Halt complete interrupt status enable" "0,1"
|
|
line.long 0x10 "CQISGE,Command Queuing Interrupt signal enable register"
|
|
bitfld.long 0x10 5. "ICCE_SGE,Invalid Crypto Configuration Error interrupt signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "GCE_SGE,General Crypto Error interrupt signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "TCL_SGE,Task cleared interrupt signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "RED_SGE,Response error detected interrupt signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "TCC_SGE,Task complete interrupt signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "HAC_SGE,Halt complete interrupt signal enable" "0,1"
|
|
line.long 0x14 "CQIC,Command Queuing Interrupt Coalescing register"
|
|
bitfld.long 0x14 31. "INTC_EN,Interrupt Coalescing Enable Bit" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 20. "INTC_STAT,Interrupt Coalescing Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 16. "INTC_RST,Counter and Timer Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x14 15. "INTC_TH_WEN,Interrupt Coalescing Counter Threshold Write Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--12. 1. "INTC_TH,Interrupt Coalescing Counter Threshold filed"
|
|
newline
|
|
bitfld.long 0x14 7. "TOUT_VAL_WEN,When software writes 1 to this bit the value TOUT_VAL is" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--6. 1. "TOUT_VAL,Interrupt Coalescing Timeout Value"
|
|
line.long 0x18 "CQTDLBA,Command Queuing Task Descriptor List Base Address register"
|
|
hexmask.long 0x18 0.--31. 1. "TDLBA,This register stores the LSB bits (31:0) of the byte address of"
|
|
group.long 0x1A8++0x7
|
|
line.long 0x0 "CQTDBR,Command Queuing DoorBell register"
|
|
hexmask.long 0x0 0.--31. 1. "DBR,The software configures TDLBA and TDLBAU and enable"
|
|
line.long 0x4 "CQTCN,Command Queuing TaskClear Notification register"
|
|
hexmask.long 0x4 0.--31. 1. "TCN,Task Completion Notification"
|
|
rgroup.long 0x1B0++0x7
|
|
line.long 0x0 "CQDQS,Device queue status register"
|
|
hexmask.long 0x0 0.--31. 1. "DQS,Device Queue Status"
|
|
line.long 0x4 "CQDPT,Device pending tasks register"
|
|
hexmask.long 0x4 0.--31. 1. "DPT,Device-Pending Tasks"
|
|
group.long 0x1B8++0x3
|
|
line.long 0x0 "CQTCLR,Command Queuing DoorBell register"
|
|
hexmask.long 0x0 0.--31. 1. "TCLR,Writing 1 to bit n of this register orders CQE to clear a task"
|
|
group.long 0x1C0++0x7
|
|
line.long 0x0 "CQSSC1,CQ Send Status Configuration 1 register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQSCMD_BLK_CNT,This field indicates when SQS CMD is sent while data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "SQSCMD_IDLE_TMR,This field configures the polling period to be used when"
|
|
line.long 0x4 "CQSSC2,CQ Send Status Configuration 2 register"
|
|
hexmask.long.word 0x4 0.--15. 1. "SQSCMD_RCA,This field provides CQE with the contents of the 16-bit RCA"
|
|
rgroup.long 0x1C8++0x3
|
|
line.long 0x0 "CQCRDCT,Command response for direct command register"
|
|
hexmask.long 0x0 0.--31. 1. "DCMD_RESP,This register contains the response of the command"
|
|
group.long 0x1D0++0x3
|
|
line.long 0x0 "CQRMEM,Command response mode error mask register"
|
|
hexmask.long 0x0 0.--31. 1. "RESP_ERR_MASK,The bits of this field are bit mapped to the device response."
|
|
rgroup.long 0x1D4++0xB
|
|
line.long 0x0 "CQTERRI,CQ Task Error Information register"
|
|
bitfld.long 0x0 31. "TRANS_ERR_FIELDS_VALID,This bit is updated when an error is detected while a data" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--28. 1. "TRANS_ERR_TASKID,This field captures the ID of the task that was executed and"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TRANS_ERR_CMD_INDX,This field captures the index of the command that was"
|
|
newline
|
|
bitfld.long 0x0 15. "RESP_ERR_FIELDS_VALID,This bit is updated when an error is detected while a" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "RESP_ERR_TASKID,This field captures the ID of the task which was executed on"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "RESP_ERR_CMD_INDX,This field captures the index of the command that was"
|
|
line.long 0x4 "CQCRI,CQ Command response index"
|
|
hexmask.long.byte 0x4 0.--5. 1. "CMD_RESP_INDX,Last Command Response index"
|
|
line.long 0x8 "CQCRA,CQ Command response argument register"
|
|
hexmask.long 0x8 0.--31. 1. "CMD_RESP_ARG,Last Command Response argument"
|
|
rgroup.long 0x500++0x7
|
|
line.long 0x0 "MSHC_VER_ID_R,MSHC version"
|
|
hexmask.long 0x0 0.--31. 1. "MSHC_VER_ID,Current release number"
|
|
line.long 0x4 "MSHC_VER_TYPE_R,MSHC version type"
|
|
hexmask.long 0x4 0.--31. 1. "MSHC_VER_TYPE,Current release type"
|
|
group.byte 0x508++0x0
|
|
line.byte 0x0 "MSHC_CTRL_R,MSHC Control register"
|
|
bitfld.byte 0x0 4. "SW_CG_DIS,Internal clock gating disable control" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "CMD_CONFLICT_CHECK,Command conflict check" "0,1"
|
|
group.byte 0x510++0x0
|
|
line.byte 0x0 "MBIU_CTRL_R,MBIU Control register"
|
|
bitfld.byte 0x0 3. "BURST_INCR16_EN,INCR16 Burst" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "BURST_INCR8_EN,INCR8 Burst" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "BURST_INCR4_EN,INCR4 Burst" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "UNDEFL_INCR_EN,Undefined INCR Burst" "0,1"
|
|
group.word 0x52C++0x3
|
|
line.word 0x0 "EMMC_CTRL_R,eMMC Control register"
|
|
bitfld.word 0x0 10. "CQE_PREFETCH_DISABLE,Enable or Disable CQE's PREFETCH feature" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "CQE_ALGO_SEL,Scheduler algorithm selected for execution" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "EMMC_RST_N_OE,Output Enable (OE) control for EMMC Device Reset signal (card_emmc_reset_n)." "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "EMMC_RST_N,EMMC Device Reset signal control." "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "DISABLE_DATA_CRC_CHK,Disable Data CRC Check" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "CARD_IS_EMMC,eMMC Card present" "0,1"
|
|
line.word 0x2 "BOOT_CTRL_R,eMMC Boot Control register"
|
|
hexmask.word.byte 0x2 12.--15. 1. "BOOT_TOUT_CNT,N/A"
|
|
newline
|
|
bitfld.word 0x2 8. "BOOT_ACK_ENABLE,Boot Acknowledge Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "VALIDATE_BOOT,Validate Mandatory Boot Enable bit" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "MAN_BOOT_EN,Mandatory Boot Enable" "0,1"
|
|
rgroup.long 0x530++0x3
|
|
line.long 0x0 "GP_IN_R,General Purpose Input register"
|
|
bitfld.long 0x0 0. "GP_IN,It reflects the value of gp_in ports." "0,1"
|
|
group.long 0x534++0x3
|
|
line.long 0x0 "GP_OUT_R,General Purpose Output register"
|
|
bitfld.long 0x0 8.--9. "CARD_CLOCK_IN_DLY,Delay CARD_CLOCK input internally to optimally sample CMD/DAT; set according to interface mode:" "0: SD Default Speed,1: SD SDR25,?,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CARD_CLOCK_OUT_DLY,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 5. "IO_VOLT_SEL_OE,Active high output enable for the IO voltage selection signal (io_volt_sel) controlled through HOST_CTRL_2.SIGNALING_EN:" "0: disable OE to the io_volt_sel output,1: enable OE to the io_volt_sel output"
|
|
newline
|
|
bitfld.long 0x0 4. "CARD_IF_PWR_EN_OE,Active high output enable for the card interface power enable output (card_if_pwr_en) controlled through PWR_CTRL_R.SD_BUS_PWR_VDD1:" "0: disable OE to the card_if_pwr_en output,1: enable OE to the card_if_pwr_en output"
|
|
newline
|
|
bitfld.long 0x0 3. "CARD_CLOCK_OE,Active high output enable for the card clock output (clk_card) which is gated by CLK_CTRL_R.SD_CLK_EN:" "0: disable OE to the clk_card output,1: enable OE to the clk_card output"
|
|
newline
|
|
bitfld.long 0x0 2. "LED_CTRL_OE,Active high output enable for the LED output signal (led_ctrl) controlled through HOST_CTRL1_R.LED_CTRL:" "0: disable OE associated with the led_ctrl output,1: enable OE associated with the led_ctrl output"
|
|
newline
|
|
bitfld.long 0x0 1. "CARD_MECH_WRITE_PROT_EN,card_mech_write_prot despite its name is an active low signal (per the SD Host Controller Standard spec it is officially called SDWP#). Consider that in the following:" "0: Force card_mech_write_prot input to 0 internally,1: Allow card_mech_write_prot to work normally per.."
|
|
newline
|
|
bitfld.long 0x0 0. "CARD_DETECT_EN,0: Force card_detect_n input to 0" "0: Force card_detect_n input to 0,1: Normal card_detect_n operation allowing card.."
|
|
tree.end
|
|
base ad:0x40460000
|
|
tree "WRAP (MMIO at SDHC wrapper level)"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Top level wrapper control"
|
|
bitfld.long 0x0 31. "ENABLE,IP Enable:" "0: IP disabled,1: IP enabled"
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("CY8C6??8*")||cpuis("CYB06??8*")||cpuis("CYS06??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??A*")||cpuis("CYS06??A*"))
|
|
tree "SDHC1"
|
|
base ad:0x40470000
|
|
tree "CORE (MMIO for Synopsys Mobile Storage Host Controller IP)"
|
|
base ad:0x40470000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SDMASA_R,SDMA System Address register"
|
|
hexmask.long 0x0 0.--31. 1. "BLOCKCNT_SDMASA,32-bit Block Count (SDMA System Address)"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "BLOCKSIZE_R,Block Size register"
|
|
bitfld.word 0x0 12.--14. "SDMA_BUF_BDARY,SDMA Buffer Boundary" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x0 0.--11. 1. "XFER_BLOCK_SIZE,Transfer Block Size"
|
|
line.word 0x2 "BLOCKCOUNT_R,16-bit Block Count register"
|
|
hexmask.word 0x2 0.--15. 1. "BLOCK_CNT,16-bit Block Count"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ARGUMENT_R,Argument register"
|
|
hexmask.long 0x0 0.--31. 1. "ARGUMENT,Command Argument"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "XFER_MODE_R,Transfer Mode register"
|
|
bitfld.word 0x0 8. "RESP_INT_DISABLE,Response Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "RESP_ERR_CHK_ENABLE,Response Error Check Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "RESP_TYPE,Response Type R1/R5" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "MULTI_BLK_SEL,Multi/Single Block Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "DATA_XFER_DIR,Data Transfer Direction Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2.--3. "AUTO_CMD_ENABLE,Auto Command Enable" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 1. "BLOCK_COUNT_ENABLE,Block Count Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "DMA_ENABLE,DMA Enable" "0,1"
|
|
line.word 0x2 "CMD_R,Command register"
|
|
hexmask.word.byte 0x2 8.--13. 1. "CMD_INDEX,Command Index"
|
|
newline
|
|
bitfld.word 0x2 6.--7. "CMD_TYPE,Command Type" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x2 5. "DATA_PRESENT_SEL,Data Present Select" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "CMD_IDX_CHK_ENABLE,Command Index Check Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 3. "CMD_CRC_CHK_ENABLE,Command CRC Check Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "SUB_CMD_FLAG,Sub Command Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0.--1. "RESP_TYPE_SELECT,Response Type Select" "0,1,2,3"
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "RESP01_R,Response Register 0/1"
|
|
hexmask.long 0x0 0.--31. 1. "RESP01,Command Response"
|
|
line.long 0x4 "RESP23_R,Response Register 2/3"
|
|
hexmask.long 0x4 0.--31. 1. "RESP23,Command Response"
|
|
line.long 0x8 "RESP45_R,Response Register 4/5"
|
|
hexmask.long 0x8 0.--31. 1. "RESP45,Command Response"
|
|
line.long 0xC "RESP67_R,Response Register 6/7"
|
|
hexmask.long 0xC 0.--31. 1. "RESP67,Command Response"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "BUF_DATA_R,Buffer Data Port Register"
|
|
hexmask.long 0x0 0.--31. 1. "BUF_DATA,Buffer Data"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "PSTATE_REG,Present State Register"
|
|
bitfld.long 0x0 28. "SUB_CMD_STAT,Sub Command Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "CMD_ISSU_ERR,Command Not Issued by Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "HOST_REG_VOL,Host Regulator Voltage Stable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "CMD_LINE_LVL,Command-Line Signal Level" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "DAT_3_0,DAT[3:0] Line Signal Level"
|
|
newline
|
|
bitfld.long 0x0 19. "WR_PROTECT_SW_LVL,Write Protect Switch Pin Level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CARD_DETECT_PIN_LEVEL,Card Detect Pin Level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CARD_STABLE,Card Stable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CARD_INSERTED,Card Inserted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BUF_RD_ENABLE,Buffer Read Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BUF_WR_ENABLE,Buffer Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RD_XFER_ACTIVE,Read Transfer Active" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "WR_XFER_ACTIVE,Write Transfer Active" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DAT_7_4,DAT[7:4] Line Signal Level"
|
|
newline
|
|
bitfld.long 0x0 2. "DAT_LINE_ACTIVE,DAT Line Active (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CMD_INHIBIT_DAT,Command Inhibit (DAT)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMD_INHIBIT,Command Inhibit (CMD)" "0,1"
|
|
group.byte 0x28++0x3
|
|
line.byte 0x0 "HOST_CTRL1_R,Host Control 1 Register"
|
|
bitfld.byte 0x0 7. "CARD_DETECT_SIG_SEL,Card Detect Signal Selection" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "CARD_DETECT_TEST_LVL,Card Detect Test Level" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "EXT_DAT_XFER,Extended Data Transfer Width" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3.--4. "DMA_SEL,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.byte 0x0 2. "HIGH_SPEED_EN,High Speed Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "DAT_XFER_WIDTH,Data Transfer Width" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "LED_CTRL,LED Control" "0,1"
|
|
line.byte 0x1 "PWR_CTRL_R,Power Control Register"
|
|
bitfld.byte 0x1 1.--3. "SD_BUS_VOL_VDD1,These bits are NON-operational (they can be written and read but they have no effect). In a generic HCI host these would select the card supply voltage. But for the applications targeted for this block it is assumed that the card.." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.byte 0x1 0. "SD_BUS_PWR_VDD1,SD Bus Power for VDD1" "0,1"
|
|
line.byte 0x2 "BGAP_CTRL_R,Block Gap Control Register"
|
|
bitfld.byte 0x2 3. "INT_AT_BGAP,Interrupt At Block Gap" "0,1"
|
|
newline
|
|
bitfld.byte 0x2 2. "RD_WAIT_CTRL,N/A" "0,1"
|
|
newline
|
|
bitfld.byte 0x2 1. "CONTINUE_REQ,Continue Request" "0,1"
|
|
newline
|
|
bitfld.byte 0x2 0. "STOP_BG_REQ,Stop At Block Gap Request" "0,1"
|
|
line.byte 0x3 "WUP_CTRL_R,Wakeup Control Register"
|
|
bitfld.byte 0x3 2. "WUP_CARD_REMOVAL,Wakeup Event Enable on SD Card Removal" "0,1"
|
|
newline
|
|
bitfld.byte 0x3 1. "WUP_CARD_INSERT,Wakeup Event Enable on SD Card Insertion" "0,1"
|
|
newline
|
|
bitfld.byte 0x3 0. "WUP_CARD_INT,Wakeup Event Enable on SDIO Card Interrupt (through DAT[1])." "0,1"
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "CLK_CTRL_R,Clock Control Register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "FREQ_SEL,SDCLK Frequency Select"
|
|
newline
|
|
bitfld.word 0x0 6.--7. "UPPER_FREQ_SEL,These bits specify the upper 2 bits of 10-bit SDCLK" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 5. "CLK_GEN_SELECT,Clock Generator Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PLL_ENABLE,PLL Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "SD_CLK_EN,SD/eMMC Clock Enable" "0,1"
|
|
newline
|
|
rbitfld.word 0x0 1. "INTERNAL_CLK_STABLE,Internal Clock Stable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INTERNAL_CLK_EN,Internal Clock Enable" "0,1"
|
|
group.byte 0x2E++0x1
|
|
line.byte 0x0 "TOUT_CTRL_R,Timeout Control Register"
|
|
hexmask.byte 0x0 0.--3. 1. "TOUT_CNT,N/A"
|
|
line.byte 0x1 "SW_RST_R,Software Reset Register"
|
|
bitfld.byte 0x1 2. "SW_RST_DAT,Software Reset For DAT line" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 1. "SW_RST_CMD,Software Reset For CMD line" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "SW_RST_ALL,Software Reset For All" "0,1"
|
|
group.word 0x30++0xB
|
|
line.word 0x0 "NORMAL_INT_STAT_R,Normal Interrupt Status Register"
|
|
rbitfld.word 0x0 15. "ERR_INTERRUPT,Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x0 14. "CQE_EVENT,Command Queuing Event" "0,1"
|
|
newline
|
|
rbitfld.word 0x0 13. "FX_EVENT,FX Event" "0,1"
|
|
newline
|
|
rbitfld.word 0x0 8. "CARD_INTERRUPT,Card Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "CARD_REMOVAL,Card Removal" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "CARD_INSERTION,Card Insertion" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "BUF_RD_READY,Buffer Read Ready" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "BUF_WR_READY,Buffer Write Ready" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DMA_INTERRUPT,DMA Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BGAP_EVENT,Block Gap Event" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "XFER_COMPLETE,Transfer Complete" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "CMD_COMPLETE,Command Complete" "0,1"
|
|
line.word 0x2 "ERROR_INT_STAT_R,Error Interrupt Status Register"
|
|
bitfld.word 0x2 12. "BOOT_ACK_ERR,Boot Acknowledgement Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 11. "RESP_ERR,Response Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 10. "TUNING_ERR,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x2 9. "ADMA_ERR,ADMA Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 8. "AUTO_CMD_ERR,Auto CMD Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "CUR_LMT_ERR,Current Limit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "DATA_END_BIT_ERR,Data End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 5. "DATA_CRC_ERR,Data CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "DATA_TOUT_ERR,Data Timeout Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 3. "CMD_IDX_ERR,Command Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "CMD_END_BIT_ERR,Command End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "CMD_CRC_ERR,Command CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "CMD_TOUT_ERR,Command Timeout Error" "0,1"
|
|
line.word 0x4 "NORMAL_INT_STAT_EN_R,Normal Interrupt Status Enable Register"
|
|
bitfld.word 0x4 14. "CQE_EVENT_STAT_EN,CQE Event Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 13. "FX_EVENT_STAT_EN,FX Event Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 12. "RE_TUNE_EVENT_STAT_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x4 11. "INT_C_STAT_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x4 10. "INT_B_STAT_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x4 9. "INT_A_STAT_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x4 8. "CARD_INTERRUPT_STAT_EN,Card Interrupt Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 7. "CARD_REMOVAL_STAT_EN,Card Removal Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 6. "CARD_INSERTION_STAT_EN,Card Insertion Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 5. "BUF_RD_READY_STAT_EN,Buffer Read Ready Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 4. "BUF_WR_READY_STAT_EN,Buffer Write Ready Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 3. "DMA_INTERRUPT_STAT_EN,DMA Interrupt Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 2. "BGAP_EVENT_STAT_EN,Block Gap Event Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 1. "XFER_COMPLETE_STAT_EN,Transfer Complete Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 0. "CMD_COMPLETE_STAT_EN,Command Complete Status Enable" "0,1"
|
|
line.word 0x6 "ERROR_INT_STAT_EN_R,Error Interrupt Status Enable Register"
|
|
bitfld.word 0x6 15. "VENDOR_ERR_STAT_EN3,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x6 14. "VENDOR_ERR_STAT_EN2,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x6 13. "VENDOR_ERR_STAT_EN1,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x6 12. "BOOT_ACK_ERR_STAT_EN,Boot Acknowledgment Error (eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 11. "RESP_ERR_STAT_EN,Response Error Status Enable (SD Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 10. "TUNING_ERR_STAT_EN,Tuning Error Status Enable (UHS-I Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 9. "ADMA_ERR_STAT_EN,ADMA Error Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 8. "AUTO_CMD_ERR_STAT_EN,Auto CMD Error Status Enable (SD/eMMC Mode only)." "0,1"
|
|
newline
|
|
bitfld.word 0x6 7. "CUR_LMT_ERR_STAT_EN,Current Limit Error Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 6. "DATA_END_BIT_ERR_STAT_EN,Data End Bit Error Status Enable (SD/eMMC Mode only)." "0,1"
|
|
newline
|
|
bitfld.word 0x6 5. "DATA_CRC_ERR_STAT_EN,Data CRC Error Status Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 4. "DATA_TOUT_ERR_STAT_EN,Data Timeout Error Status Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 3. "CMD_IDX_ERR_STAT_EN,Command Index Error Status Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 2. "CMD_END_BIT_ERR_STAT_EN,Command End Bit Error Status Enable (SD/eMMC Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x6 1. "CMD_CRC_ERR_STAT_EN,ommand CRC Error Status Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 0. "CMD_TOUT_ERR_STAT_EN,Command Timeout Error Status Enable (SD/eMMC Mode" "0,1"
|
|
line.word 0x8 "NORMAL_INT_SIGNAL_EN_R,Normal Interrupt Signal Enable Register"
|
|
bitfld.word 0x8 14. "CQE_EVENT_SIGNAL_EN,Command Queuing Engine Event Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 13. "FX_EVENT_SIGNAL_EN,FX Event Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 12. "RE_TUNE_EVENT_SIGNAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x8 11. "INT_C_SIGNAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x8 10. "INT_B_SIGNAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x8 9. "INT_A_SIGNAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x8 8. "CARD_INTERRUPT_SIGNAL_EN,Card Interrupt Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 7. "CARD_REMOVAL_SIGNAL_EN,Card Removal Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 6. "CARD_INSERTION_SIGNAL_EN,Card Insertion Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 5. "BUF_RD_READY_SIGNAL_EN,Buffer Read Ready Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 4. "BUF_WR_READY_SIGNAL_EN,Buffer Write Ready Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 3. "DMA_INTERRUPT_SIGNAL_EN,DMA Interrupt Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 2. "BGAP_EVENT_SIGNAL_EN,Block Gap Event Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 1. "XFER_COMPLETE_SIGNAL_EN,Transfer Complete Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 0. "CMD_COMPLETE_SIGNAL_EN,Command Complete Signal Enable" "0,1"
|
|
line.word 0xA "ERROR_INT_SIGNAL_EN_R,Error Interrupt Signal Enable Register"
|
|
bitfld.word 0xA 15. "VENDOR_ERR_SIGNAL_EN3,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0xA 14. "VENDOR_ERR_SIGNAL_EN2,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0xA 13. "VENDOR_ERR_SIGNAL_EN1,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0xA 12. "BOOT_ACK_ERR_SIGNAL_EN,Boot Acknowledgment Error (eMMC Mode only)." "0,1"
|
|
newline
|
|
bitfld.word 0xA 11. "RESP_ERR_SIGNAL_EN,Response Error Signal Enable (SD Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 10. "TUNING_ERR_SIGNAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0xA 9. "ADMA_ERR_SIGNAL_EN,ADMA Error Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0xA 8. "AUTO_CMD_ERR_SIGNAL_EN,Auto CMD Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 7. "CUR_LMT_ERR_SIGNAL_EN,Current Limit Error Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0xA 6. "DATA_END_BIT_ERR_SIGNAL_EN,Data End Bit Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 5. "DATA_CRC_ERR_SIGNAL_EN,Data CRC Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 4. "DATA_TOUT_ERR_SIGNAL_EN,Data Timeout Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 3. "CMD_IDX_ERR_SIGNAL_EN,Command Index Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 2. "CMD_END_BIT_ERR_SIGNAL_EN,Command End Bit Error Signal Enable (SD/eMMC Mode" "0,1"
|
|
newline
|
|
bitfld.word 0xA 1. "CMD_CRC_ERR_SIGNAL_EN,Command CRC Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 0. "CMD_TOUT_ERR_SIGNAL_EN,Command Timeout Error Signal Enable (SD/eMMC Mode" "0,1"
|
|
rgroup.word 0x3C++0x1
|
|
line.word 0x0 "AUTO_CMD_STAT_R,Auto CMD Status Register"
|
|
bitfld.word 0x0 7. "CMD_NOT_ISSUED_AUTO_CMD12,Command Not Issued By Auto CMD12 Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "AUTO_CMD_RESP_ERR,Auto CMD Response Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "AUTO_CMD_IDX_ERR,Auto CMD Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "AUTO_CMD_EBIT_ERR,Auto CMD End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "AUTO_CMD_CRC_ERR,Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "AUTO_CMD_TOUT_ERR,Auto CMD Timeout Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "AUTO_CMD12_NOT_EXEC,Auto CMD12 Not Executed" "0,1"
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HOST_CTRL2_R,Host Control 2 Register"
|
|
bitfld.word 0x0 15. "PRESET_VAL_ENABLE,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 14. "ASYNC_INT_ENABLE,Asynchronous Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "ADDRESSING,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 12. "HOST_VER4_ENABLE,Host Version 4 Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "CMD23_ENABLE,CMD23 Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "ADMA2_LEN_MODE,ADMA2 Length Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "UHS2_IF_ENABLE,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "SAMPLE_CLK_SEL,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "EXEC_TUNING,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4.--5. "DRV_STRENGTH_SEL,Driver Strength Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 3. "SIGNALING_EN,1.8V Signaling Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0.--2. "UHS_MODE_SEL,N/A" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x40++0xF
|
|
line.long 0x0 "CAPABILITIES1_R,Capabilities 1 Register - 0 to 31"
|
|
bitfld.long 0x0 30.--31. "SLOT_TYPE_R,Slot Type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 29. "ASYNC_INT_SUPPORT,Asynchronous Interrupt Support (SD Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "SYS_ADDR_64_V3,64-bit System Address Support for V3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SYS_ADDR_64_V4,64-bit System Address Support for V4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "VOLT_18,Voltage Support 1.8V" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "VOLT_30,Voltage Support 3.0V" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "VOLT_33,Voltage Support 3.3V" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SUS_RES_SUPPORT,Suspense/Resume Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "SDMA_SUPPORT,SDMA Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "HIGH_SPEED_SUPPORT,High Speed Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ADMA2_SUPPORT,ADMA2 Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "EMBEDDED_8_BIT,8-bit Support for Embedded Device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "MAX_BLK_LEN,N/A" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "BASE_CLK_FREQ,Base Clock Frequency for SD clock"
|
|
newline
|
|
bitfld.long 0x0 7. "TOUT_CLK_UNIT,Timeout Clock Unit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TOUT_CLK_FREQ,Timeout Clock Frequency"
|
|
line.long 0x4 "CAPABILITIES2_R,Capabilities Register - 32 to 63"
|
|
bitfld.long 0x4 28. "VDD2_18V_SUPPORT,1.8V VDD2 Support" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "ADMA3_SUPPORT,ADMA3 Support" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "CLK_MUL,Clock Multiplier"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "RE_TUNING_MODES,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 13. "USE_TUNING_SDR50,Use Tuning for SDR50 (UHS-I only)" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "RETUNE_CNT,N/A"
|
|
newline
|
|
bitfld.long 0x4 6. "DRV_TYPED,Driver Type D Support (UHS-I only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DRV_TYPEC,Driver Type C Support (UHS-I only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DRV_TYPEA,Driver Type A Support (UHS-I only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "UHS2_SUPPORT,UHS-II Support (UHS-II only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DDR50_SUPPORT,DDR50 Support (UHS-I only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "SDR104_SUPPORT,SDR104 Support (UHS-I only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SDR50_SUPPORT,SDR50 Support (UHS-I only)" "0,1"
|
|
line.long 0x8 "CURR_CAPABILITIES1_R,Current Capabilities Register - 0 to 31"
|
|
hexmask.long.byte 0x8 16.--23. 1. "MAX_CUR_18V,Maximum Current for 1.8V"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "MAX_CUR_30V,Maximum Current for 3.0V"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "MAX_CUR_33V,Maximum Current for 3.3V"
|
|
line.long 0xC "CURR_CAPABILITIES2_R,Maximum Current Capabilities Register - 32 to 63"
|
|
hexmask.long.byte 0xC 0.--7. 1. "MAX_CUR_VDD2_18V,Maximum Current for 1.8V VDD2"
|
|
wgroup.word 0x50++0x1
|
|
line.word 0x0 "FORCE_AUTO_CMD_STAT_R,Force Event Register for Auto CMD Error Status register"
|
|
bitfld.word 0x0 7. "FORCE_CMD_NOT_ISSUED_AUTO_CMD12,Force Event for Command Not Issued By Auto CMD12 Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "FORCE_AUTO_CMD_RESP_ERR,Force Event for Auto CMD Response Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "FORCE_AUTO_CMD_IDX_ERR,Force Event for Auto CMD Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "FORCE_AUTO_CMD_EBIT_ERR,Force Event for Auto CMD End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "FORCE_AUTO_CMD_CRC_ERR,Force Event for Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "FORCE_AUTO_CMD_TOUT_ERR,Force Event for Auto CMD Timeout Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "FORCE_AUTO_CMD12_NOT_EXEC,Force Event for Auto CMD12 Not Executed" "0,1"
|
|
group.word 0x52++0x1
|
|
line.word 0x0 "FORCE_ERROR_INT_STAT_R,Force Event Register for Error Interrupt Status"
|
|
bitfld.word 0x0 15. "FORCE_VENDOR_ERR3,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 14. "FORCE_VENDOR_ERR2,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "FORCE_VENDOR_ERR1,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 12. "FORCE_BOOT_ACK_ERR,Force Event for Boot Ack error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "FORCE_RESP_ERR,Force Event for Response Error (SD Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FORCE_TUNING_ERR,Force Event for Tuning Error (UHS-I Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "FORCE_ADMA_ERR,Force Event for ADMA Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "FORCE_AUTO_CMD_ERR,Force Event for Auto CMD Error (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "FORCE_CUR_LMT_ERR,Force Event for Current Limit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FORCE_DATA_END_BIT_ERR,Force Event for Data End Bit Error (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "FORCE_DATA_CRC_ERR,Force Event for Data CRC Error (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "FORCE_DATA_TOUT_ERR,Force Event for Data Timeout Error (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "FORCE_CMD_IDX_ERR,Force Event for Command Index Error (SD/eMMC Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "FORCE_CMD_END_BIT_ERR,Force Event for Command End Bit Error (SD/eMMC Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "FORCE_CMD_CRC_ERR,Force Event for Command CRC Error (SD/eMMC Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "FORCE_CMD_TOUT_ERR,Force Event for Command Timeout Error (SD/eMMC Mode" "0,1"
|
|
rgroup.byte 0x54++0x0
|
|
line.byte 0x0 "ADMA_ERR_STAT_R,ADMA Error Status Register"
|
|
bitfld.byte 0x0 2. "ADMA_LEN_ERR,ADMA Length Mismatch Error States" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0.--1. "ADMA_ERR_STATES,ADMA Error States" "0,1,2,3"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "ADMA_SA_LOW_R,ADMA System Address Register - Low"
|
|
hexmask.long 0x0 0.--31. 1. "ADMA_SA_LOW,ADMA System Address"
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "ADMA_ID_LOW_R,ADMA3 Integrated Descriptor Address Register - Low"
|
|
hexmask.long 0x0 0.--31. 1. "ADMA_ID_LOW,ADMA Integrated Descriptor Address"
|
|
rgroup.word 0xFE++0x1
|
|
line.word 0x0 "HOST_CNTRL_VERS_R,Host Controller Version"
|
|
hexmask.word.byte 0x0 8.--15. 1. "VENDOR_VERSION_NUM,N/A"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "SPEC_VERSION_NUM,N/A"
|
|
rgroup.long 0x180++0x7
|
|
line.long 0x0 "CQVER,Command Queuing Version register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "EMMC_VER_MAJOR,This bit indicates the eMMC major version (1st digit left of"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "EMMC_VER_MINOR,This bit indicates the eMMC minor version (1st digit right of"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "EMMC_VER_SUFFIX,This bit indicates the eMMC version suffix (2nd digit right of"
|
|
line.long 0x4 "CQCAP,Command Queuing Capabilities register"
|
|
bitfld.long 0x4 28. "CRYPTO_SUPPORT,Crypto Support" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "ITCFMUL,N/A"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "ITCFVAL,Internal Timer Clock Frequency Value (ITCFVAL)"
|
|
group.long 0x188++0x1B
|
|
line.long 0x0 "CQCFG,Command Queuing Configuration register"
|
|
bitfld.long 0x0 12. "DCMD_EN,This bit indicates to the hardware whether the Task" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TASK_DESC_SIZE,Bit Value Description" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CR_GENERAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CQ_EN,Enable command queuing engine (CQE)." "0,1"
|
|
line.long 0x4 "CQCTL,Command Queuing Control register"
|
|
bitfld.long 0x4 8. "CLR_ALL_TASKS,Clear all tasks" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "HALT,Halt request and resume" "0,1"
|
|
line.long 0x8 "CQIS,Command Queuing Interrupt Status register"
|
|
bitfld.long 0x8 5. "ICCE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "GCE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "TCL,Task cleared interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "RED,Response error detected interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TCC,Task complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "HAC,Halt complete interrupt" "0,1"
|
|
line.long 0xC "CQISE,Command Queuing Interrupt Status Enable register"
|
|
bitfld.long 0xC 5. "ICCE_STE,Invalid Crypto Configuration Error interrupt status enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "GCE_STE,General Crypto Error interrupt status enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "TCL_STE,Task cleared interrupt status enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "RED_STE,Response error detected interrupt status enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TCC_STE,Task complete interrupt status enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "HAC_STE,Halt complete interrupt status enable" "0,1"
|
|
line.long 0x10 "CQISGE,Command Queuing Interrupt signal enable register"
|
|
bitfld.long 0x10 5. "ICCE_SGE,Invalid Crypto Configuration Error interrupt signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "GCE_SGE,General Crypto Error interrupt signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "TCL_SGE,Task cleared interrupt signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "RED_SGE,Response error detected interrupt signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "TCC_SGE,Task complete interrupt signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "HAC_SGE,Halt complete interrupt signal enable" "0,1"
|
|
line.long 0x14 "CQIC,Command Queuing Interrupt Coalescing register"
|
|
bitfld.long 0x14 31. "INTC_EN,Interrupt Coalescing Enable Bit" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 20. "INTC_STAT,Interrupt Coalescing Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 16. "INTC_RST,Counter and Timer Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x14 15. "INTC_TH_WEN,Interrupt Coalescing Counter Threshold Write Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--12. 1. "INTC_TH,Interrupt Coalescing Counter Threshold filed"
|
|
newline
|
|
bitfld.long 0x14 7. "TOUT_VAL_WEN,When software writes 1 to this bit the value TOUT_VAL is" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--6. 1. "TOUT_VAL,Interrupt Coalescing Timeout Value"
|
|
line.long 0x18 "CQTDLBA,Command Queuing Task Descriptor List Base Address register"
|
|
hexmask.long 0x18 0.--31. 1. "TDLBA,This register stores the LSB bits (31:0) of the byte address of"
|
|
group.long 0x1A8++0x7
|
|
line.long 0x0 "CQTDBR,Command Queuing DoorBell register"
|
|
hexmask.long 0x0 0.--31. 1. "DBR,The software configures TDLBA and TDLBAU and enable"
|
|
line.long 0x4 "CQTCN,Command Queuing TaskClear Notification register"
|
|
hexmask.long 0x4 0.--31. 1. "TCN,Task Completion Notification"
|
|
rgroup.long 0x1B0++0x7
|
|
line.long 0x0 "CQDQS,Device queue status register"
|
|
hexmask.long 0x0 0.--31. 1. "DQS,Device Queue Status"
|
|
line.long 0x4 "CQDPT,Device pending tasks register"
|
|
hexmask.long 0x4 0.--31. 1. "DPT,Device-Pending Tasks"
|
|
group.long 0x1B8++0x3
|
|
line.long 0x0 "CQTCLR,Command Queuing DoorBell register"
|
|
hexmask.long 0x0 0.--31. 1. "TCLR,Writing 1 to bit n of this register orders CQE to clear a task"
|
|
group.long 0x1C0++0x7
|
|
line.long 0x0 "CQSSC1,CQ Send Status Configuration 1 register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQSCMD_BLK_CNT,This field indicates when SQS CMD is sent while data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "SQSCMD_IDLE_TMR,This field configures the polling period to be used when"
|
|
line.long 0x4 "CQSSC2,CQ Send Status Configuration 2 register"
|
|
hexmask.long.word 0x4 0.--15. 1. "SQSCMD_RCA,This field provides CQE with the contents of the 16-bit RCA"
|
|
rgroup.long 0x1C8++0x3
|
|
line.long 0x0 "CQCRDCT,Command response for direct command register"
|
|
hexmask.long 0x0 0.--31. 1. "DCMD_RESP,This register contains the response of the command"
|
|
group.long 0x1D0++0x3
|
|
line.long 0x0 "CQRMEM,Command response mode error mask register"
|
|
hexmask.long 0x0 0.--31. 1. "RESP_ERR_MASK,The bits of this field are bit mapped to the device response."
|
|
rgroup.long 0x1D4++0xB
|
|
line.long 0x0 "CQTERRI,CQ Task Error Information register"
|
|
bitfld.long 0x0 31. "TRANS_ERR_FIELDS_VALID,This bit is updated when an error is detected while a data" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--28. 1. "TRANS_ERR_TASKID,This field captures the ID of the task that was executed and"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TRANS_ERR_CMD_INDX,This field captures the index of the command that was"
|
|
newline
|
|
bitfld.long 0x0 15. "RESP_ERR_FIELDS_VALID,This bit is updated when an error is detected while a" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "RESP_ERR_TASKID,This field captures the ID of the task which was executed on"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "RESP_ERR_CMD_INDX,This field captures the index of the command that was"
|
|
line.long 0x4 "CQCRI,CQ Command response index"
|
|
hexmask.long.byte 0x4 0.--5. 1. "CMD_RESP_INDX,Last Command Response index"
|
|
line.long 0x8 "CQCRA,CQ Command response argument register"
|
|
hexmask.long 0x8 0.--31. 1. "CMD_RESP_ARG,Last Command Response argument"
|
|
rgroup.long 0x500++0x7
|
|
line.long 0x0 "MSHC_VER_ID_R,MSHC version"
|
|
hexmask.long 0x0 0.--31. 1. "MSHC_VER_ID,Current release number"
|
|
line.long 0x4 "MSHC_VER_TYPE_R,MSHC version type"
|
|
hexmask.long 0x4 0.--31. 1. "MSHC_VER_TYPE,Current release type"
|
|
group.byte 0x508++0x0
|
|
line.byte 0x0 "MSHC_CTRL_R,MSHC Control register"
|
|
bitfld.byte 0x0 4. "SW_CG_DIS,Internal clock gating disable control" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "CMD_CONFLICT_CHECK,Command conflict check" "0,1"
|
|
group.byte 0x510++0x0
|
|
line.byte 0x0 "MBIU_CTRL_R,MBIU Control register"
|
|
bitfld.byte 0x0 3. "BURST_INCR16_EN,INCR16 Burst" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "BURST_INCR8_EN,INCR8 Burst" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "BURST_INCR4_EN,INCR4 Burst" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "UNDEFL_INCR_EN,Undefined INCR Burst" "0,1"
|
|
group.word 0x52C++0x3
|
|
line.word 0x0 "EMMC_CTRL_R,eMMC Control register"
|
|
bitfld.word 0x0 10. "CQE_PREFETCH_DISABLE,Enable or Disable CQE's PREFETCH feature" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "CQE_ALGO_SEL,Scheduler algorithm selected for execution" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "EMMC_RST_N_OE,Output Enable (OE) control for EMMC Device Reset signal (card_emmc_reset_n)." "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "EMMC_RST_N,EMMC Device Reset signal control." "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "DISABLE_DATA_CRC_CHK,Disable Data CRC Check" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "CARD_IS_EMMC,eMMC Card present" "0,1"
|
|
line.word 0x2 "BOOT_CTRL_R,eMMC Boot Control register"
|
|
hexmask.word.byte 0x2 12.--15. 1. "BOOT_TOUT_CNT,N/A"
|
|
newline
|
|
bitfld.word 0x2 8. "BOOT_ACK_ENABLE,Boot Acknowledge Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "VALIDATE_BOOT,Validate Mandatory Boot Enable bit" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "MAN_BOOT_EN,Mandatory Boot Enable" "0,1"
|
|
rgroup.long 0x530++0x3
|
|
line.long 0x0 "GP_IN_R,General Purpose Input register"
|
|
bitfld.long 0x0 0. "GP_IN,It reflects the value of gp_in ports." "0,1"
|
|
group.long 0x534++0x3
|
|
line.long 0x0 "GP_OUT_R,General Purpose Output register"
|
|
bitfld.long 0x0 8.--9. "CARD_CLOCK_IN_DLY,Delay CARD_CLOCK input internally to optimally sample CMD/DAT; set according to interface mode:" "0: SD Default Speed,1: SD SDR25,?,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CARD_CLOCK_OUT_DLY,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 5. "IO_VOLT_SEL_OE,Active high output enable for the IO voltage selection signal (io_volt_sel) controlled through HOST_CTRL_2.SIGNALING_EN:" "0: disable OE to the io_volt_sel output,1: enable OE to the io_volt_sel output"
|
|
newline
|
|
bitfld.long 0x0 4. "CARD_IF_PWR_EN_OE,Active high output enable for the card interface power enable output (card_if_pwr_en) controlled through PWR_CTRL_R.SD_BUS_PWR_VDD1:" "0: disable OE to the card_if_pwr_en output,1: enable OE to the card_if_pwr_en output"
|
|
newline
|
|
bitfld.long 0x0 3. "CARD_CLOCK_OE,Active high output enable for the card clock output (clk_card) which is gated by CLK_CTRL_R.SD_CLK_EN:" "0: disable OE to the clk_card output,1: enable OE to the clk_card output"
|
|
newline
|
|
bitfld.long 0x0 2. "LED_CTRL_OE,Active high output enable for the LED output signal (led_ctrl) controlled through HOST_CTRL1_R.LED_CTRL:" "0: disable OE associated with the led_ctrl output,1: enable OE associated with the led_ctrl output"
|
|
newline
|
|
bitfld.long 0x0 1. "CARD_MECH_WRITE_PROT_EN,card_mech_write_prot despite its name is an active low signal (per the SD Host Controller Standard spec it is officially called SDWP#). Consider that in the following:" "0: Force card_mech_write_prot input to 0 internally,1: Allow card_mech_write_prot to work normally per.."
|
|
newline
|
|
bitfld.long 0x0 0. "CARD_DETECT_EN,0: Force card_detect_n input to 0" "0: Force card_detect_n input to 0,1: Normal card_detect_n operation allowing card.."
|
|
tree.end
|
|
base ad:0x40470000
|
|
tree "WRAP (MMIO at SDHC wrapper level)"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Top level wrapper control"
|
|
bitfld.long 0x0 31. "ENABLE,IP Enable:" "0: IP disabled,1: IP enabled"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
base ad:0x40330000
|
|
elif (cpuis("CY8C6??4*")||cpuis("CY8C6??5*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??4*")||cpuis("CYB06??5*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??4*")||cpuis("CYS06??5*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
base ad:0x40320000
|
|
endif
|
|
tree "SMARTIO (Programmable IO Configuration)"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40330000 ad:0x40330100 ad:0x40330200 ad:0x40330300 ad:0x40330400 ad:0x40330500 ad:0x40330600 ad:0x40330700 ad:0x40330800 ad:0x40330900)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 31. "ENABLED,Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 25. "PIPELINE_EN,Enable for pipeline register:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "HLD_OVR,IO cell hold override functionality. In DeepSleep power mode the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep.." "0: The HSIOM controls the IO cell hold override..,1: The SMARTIO controls the IO cel hold override.."
|
|
hexmask.long.byte 0x0 8.--12. 1. "CLOCK_SRC,Clock ('clk_fabric') and reset ('rst_fabric_n') source selection:"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "BYPASS,Bypass of the programmable IO one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1' this field is used. When ENABLED is '0' this field is NOT used and SMARTIO fabric is always bypassed."
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "SYNC_CTL,Synchronization control register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CHIP_SYNC_EN,Synchronization of the chip input signals to 'clk_fabric' one bit for each input: CHIP_SYNC_EN[i] is for input i."
|
|
hexmask.long.byte 0x0 0.--7. 1. "IO_SYNC_EN,Synchronization of the IO pin input signals to 'clk_fabric' one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i."
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "LUT_SEL[$1],LUT component input selection"
|
|
hexmask.long.byte 0x0 16.--19. 1. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection:"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection:"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "LUT_CTL[$1],LUT component control register"
|
|
bitfld.long 0x0 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation:" "0: Combinatoral output,1: Combinatorial output,2: Sequential output,3: Register with asynchronous set and reset"
|
|
hexmask.long.byte 0x0 0.--7. 1. "LUT,LUT configuration. Depending on the LUT opcode LUT_OPC the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in tr1_in tr2_in the LUT configuration is used to determine the LUT output signal and the next sequential.."
|
|
repeat.end
|
|
group.long ($2+0xC0)++0x7
|
|
line.long 0x0 "DU_SEL,Data unit component input selection"
|
|
bitfld.long 0x0 28.--29. "DU_DATA1_SEL,Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL." "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "DU_DATA0_SEL,Data unit input data 'data0_in' source selection:" "0: Constant '0',1: chip_data[7:0],2: io_data_in[7:0],3: DATA"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "DU_TR2_SEL,Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "DU_TR1_SEL,Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DU_TR0_SEL,Data unit input signal 'tr0_in' source selection:"
|
|
line.long 0x4 "DU_CTL,Data unit component control register"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DU_OPC,Data unit opcode specifies the data unit operation:"
|
|
bitfld.long 0x4 0.--2. "DU_SIZE,Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g. if DU_SIZE is 7 the width is 8 bits." "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0xF0)++0x3
|
|
line.long 0x0 "DATA,Data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data unit input data source."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40330000
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40320000 ad:0x40320100 ad:0x40320200 ad:0x40320300 ad:0x40320400 ad:0x40320500 ad:0x40320600 ad:0x40320700 ad:0x40320800 ad:0x40320900)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 31. "ENABLED,Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 25. "PIPELINE_EN,Enable for pipeline register:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "HLD_OVR,IO cell hold override functionality. In DeepSleep power mode the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep.." "0: The HSIOM controls the IO cell hold override..,1: The SMARTIO controls the IO cel hold override.."
|
|
hexmask.long.byte 0x0 8.--12. 1. "CLOCK_SRC,Clock ('clk_fabric') and reset ('rst_fabric_n') source selection:"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "BYPASS,Bypass of the programmable IO one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1' this field is used. When ENABLED is '0' this field is NOT used and SMARTIO fabric is always bypassed."
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "SYNC_CTL,Synchronization control register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CHIP_SYNC_EN,Synchronization of the chip input signals to 'clk_fabric' one bit for each input: CHIP_SYNC_EN[i] is for input i."
|
|
hexmask.long.byte 0x0 0.--7. 1. "IO_SYNC_EN,Synchronization of the IO pin input signals to 'clk_fabric' one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i."
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "LUT_SEL[$1],LUT component input selection"
|
|
hexmask.long.byte 0x0 16.--19. 1. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection:"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection:"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "LUT_CTL[$1],LUT component control register"
|
|
bitfld.long 0x0 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation:" "0: Combinatoral output,1: Combinatorial output,2: Sequential output,3: Register with asynchronous set and reset"
|
|
hexmask.long.byte 0x0 0.--7. 1. "LUT,LUT configuration. Depending on the LUT opcode LUT_OPC the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in tr1_in tr2_in the LUT configuration is used to determine the LUT output signal and the next sequential.."
|
|
repeat.end
|
|
group.long ($2+0xC0)++0x7
|
|
line.long 0x0 "DU_SEL,Data unit component input selection"
|
|
bitfld.long 0x0 28.--29. "DU_DATA1_SEL,Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL." "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "DU_DATA0_SEL,Data unit input data 'data0_in' source selection:" "0: Constant '0',1: chip_data[7:0],2: io_data_in[7:0],3: DATA"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "DU_TR2_SEL,Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "DU_TR1_SEL,Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DU_TR0_SEL,Data unit input signal 'tr0_in' source selection:"
|
|
line.long 0x4 "DU_CTL,Data unit component control register"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DU_OPC,Data unit opcode specifies the data unit operation:"
|
|
bitfld.long 0x4 0.--2. "DU_SIZE,Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g. if DU_SIZE is 7 the width is 8 bits." "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0xF0)++0x3
|
|
line.long 0x0 "DATA,Data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data unit input data source."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40330000
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40320000 ad:0x40320100 ad:0x40320200 ad:0x40320300 ad:0x40320400 ad:0x40320500 ad:0x40320600 ad:0x40320700 ad:0x40320800 ad:0x40320900)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 31. "ENABLED,Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 25. "PIPELINE_EN,Enable for pipeline register:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "HLD_OVR,IO cell hold override functionality. In DeepSleep power mode the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep.." "0: The HSIOM controls the IO cell hold override..,1: The SMARTIO controls the IO cel hold override.."
|
|
hexmask.long.byte 0x0 8.--12. 1. "CLOCK_SRC,Clock ('clk_fabric') and reset ('rst_fabric_n') source selection:"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "BYPASS,Bypass of the programmable IO one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1' this field is used. When ENABLED is '0' this field is NOT used and SMARTIO fabric is always bypassed."
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "SYNC_CTL,Synchronization control register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CHIP_SYNC_EN,Synchronization of the chip input signals to 'clk_fabric' one bit for each input: CHIP_SYNC_EN[i] is for input i."
|
|
hexmask.long.byte 0x0 0.--7. 1. "IO_SYNC_EN,Synchronization of the IO pin input signals to 'clk_fabric' one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i."
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "LUT_SEL[$1],LUT component input selection"
|
|
hexmask.long.byte 0x0 16.--19. 1. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection:"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection:"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "LUT_CTL[$1],LUT component control register"
|
|
bitfld.long 0x0 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation:" "0: Combinatoral output,1: Combinatorial output,2: Sequential output,3: Register with asynchronous set and reset"
|
|
hexmask.long.byte 0x0 0.--7. 1. "LUT,LUT configuration. Depending on the LUT opcode LUT_OPC the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in tr1_in tr2_in the LUT configuration is used to determine the LUT output signal and the next sequential.."
|
|
repeat.end
|
|
group.long ($2+0xC0)++0x7
|
|
line.long 0x0 "DU_SEL,Data unit component input selection"
|
|
bitfld.long 0x0 28.--29. "DU_DATA1_SEL,Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL." "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "DU_DATA0_SEL,Data unit input data 'data0_in' source selection:" "0: Constant '0',1: chip_data[7:0],2: io_data_in[7:0],3: DATA"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "DU_TR2_SEL,Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "DU_TR1_SEL,Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DU_TR0_SEL,Data unit input signal 'tr0_in' source selection:"
|
|
line.long 0x4 "DU_CTL,Data unit component control register"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DU_OPC,Data unit opcode specifies the data unit operation:"
|
|
bitfld.long 0x4 0.--2. "DU_SIZE,Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g. if DU_SIZE is 7 the width is 8 bits." "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0xF0)++0x3
|
|
line.long 0x0 "DATA,Data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data unit input data source."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40330000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40320000 ad:0x40320100 ad:0x40320200 ad:0x40320300 ad:0x40320400 ad:0x40320500 ad:0x40320600 ad:0x40320700 ad:0x40320800 ad:0x40320900)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 31. "ENABLED,Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 25. "PIPELINE_EN,Enable for pipeline register:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "HLD_OVR,IO cell hold override functionality. In DeepSleep power mode the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep.." "0: The HSIOM controls the IO cell hold override..,1: The SMARTIO controls the IO cel hold override.."
|
|
hexmask.long.byte 0x0 8.--12. 1. "CLOCK_SRC,Clock ('clk_fabric') and reset ('rst_fabric_n') source selection:"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "BYPASS,Bypass of the programmable IO one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1' this field is used. When ENABLED is '0' this field is NOT used and SMARTIO fabric is always bypassed."
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "SYNC_CTL,Synchronization control register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CHIP_SYNC_EN,Synchronization of the chip input signals to 'clk_fabric' one bit for each input: CHIP_SYNC_EN[i] is for input i."
|
|
hexmask.long.byte 0x0 0.--7. 1. "IO_SYNC_EN,Synchronization of the IO pin input signals to 'clk_fabric' one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i."
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "LUT_SEL[$1],LUT component input selection"
|
|
hexmask.long.byte 0x0 16.--19. 1. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection:"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection:"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "LUT_CTL[$1],LUT component control register"
|
|
bitfld.long 0x0 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation:" "0: Combinatoral output,1: Combinatorial output,2: Sequential output,3: Register with asynchronous set and reset"
|
|
hexmask.long.byte 0x0 0.--7. 1. "LUT,LUT configuration. Depending on the LUT opcode LUT_OPC the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in tr1_in tr2_in the LUT configuration is used to determine the LUT output signal and the next sequential.."
|
|
repeat.end
|
|
group.long ($2+0xC0)++0x7
|
|
line.long 0x0 "DU_SEL,Data unit component input selection"
|
|
bitfld.long 0x0 28.--29. "DU_DATA1_SEL,Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL." "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "DU_DATA0_SEL,Data unit input data 'data0_in' source selection:" "0: Constant '0',1: chip_data[7:0],2: io_data_in[7:0],3: DATA"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "DU_TR2_SEL,Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "DU_TR1_SEL,Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DU_TR0_SEL,Data unit input signal 'tr0_in' source selection:"
|
|
line.long 0x4 "DU_CTL,Data unit component control register"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DU_OPC,Data unit opcode specifies the data unit operation:"
|
|
bitfld.long 0x4 0.--2. "DU_SIZE,Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g. if DU_SIZE is 7 the width is 8 bits." "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0xF0)++0x3
|
|
line.long 0x0 "DATA,Data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data unit input data source."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40330000
|
|
endif
|
|
tree.end
|
|
tree "SMIF (Serial Memory Interface)"
|
|
base ad:0x40420000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "BLOCK,Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. Note: the FIFOs can only be accessed in MMIO_MODE." "0: 0': Generate an AHB-Lite bus error. This option..,1: 1': Introduce wait states. This setting.."
|
|
newline
|
|
bitfld.long 0x0 16.--18. "DESELECT_DELAY,Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers:" "0: 1 interface clock cycle,1: 2 interface clock cycles,2: 3 interface clock cycles,3: 4 interface clock cycles,4: 5 interface clock cycles,5: 6 interface clock cycles,6: 7 interface clock cycles,7: 8 interface clock cycles"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CLOCK_IF_RX_SEL,Specifies device interface receiver clock 'clk_if_rx' source. MISO data is captured on the rising edge of 'clk_if_rx'." "0: 'spi_clk_out',1: !'spi_clk_out',2: 'spi_clk_in',3: !'spi_clk_in'"
|
|
newline
|
|
bitfld.long 0x0 0. "XIP_MODE,Mode of operation." "0: '0': MMIO mode. Individual MMIO accesses to TX..,1: 1': XIP mode. eXecute-In-Place mode: incoming.."
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "BUSY,Cache cryptography XIP device interface or any other logic busy in the IP:" "0: not busy,1: busy"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "TX_CMD_FIFO_STATUS,Transmitter command FIFO status"
|
|
bitfld.long 0x0 0.--2. "USED3,Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0 4]." "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x50++0x3
|
|
line.long 0x0 "TX_CMD_FIFO_WR,Transmitter command FIFO write"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "DATA20,Command data. The higher two bits DATA[19:18] specify the specific command"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "TX_DATA_FIFO_CTL,Transmitter data FIFO control"
|
|
bitfld.long 0x0 0.--2. "TRIGGER_LEVEL,Determines when the TX data FIFO 'tr_tx_req' trigger is activated (trigger activation requires MMIO_MODE the trigger is NOT activated in XIP_MODE):" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x0 "TX_DATA_FIFO_STATUS,Transmitter data FIFO status"
|
|
hexmask.long.byte 0x0 0.--3. 1. "USED4,Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0 8]."
|
|
wgroup.long 0x90++0xB
|
|
line.long 0x0 "TX_DATA_FIFO_WR1,Transmitter data FIFO write"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA0,TX data (written to TX data FIFO)."
|
|
line.long 0x4 "TX_DATA_FIFO_WR2,Transmitter data FIFO write"
|
|
hexmask.long.byte 0x4 8.--15. 1. "DATA1,TX data (written to TX data FIFO second byte)."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA0,TX data (written to TX data FIFO first byte)."
|
|
line.long 0x8 "TX_DATA_FIFO_WR4,Transmitter data FIFO write"
|
|
hexmask.long.byte 0x8 24.--31. 1. "DATA3,TX data (written to TX data FIFO fourth byte)."
|
|
newline
|
|
hexmask.long.byte 0x8 16.--23. 1. "DATA2,TX data (written to TX data FIFO third byte)."
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "DATA1,TX data (written to TX data FIFO second byte)."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "DATA0,TX data (written to TX data FIFO first byte)."
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "RX_DATA_FIFO_CTL,Receiver data FIFO control"
|
|
bitfld.long 0x0 0.--2. "TRIGGER_LEVEL,Determines when RX data FIFO 'tr_rx_req' trigger is activated (trigger activation requires MMIO_MODE the trigger is NOT activated in XIP_MODE):" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "RX_DATA_FIFO_STATUS,Receiver data FIFO status"
|
|
hexmask.long.byte 0x0 0.--3. 1. "USED4,Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0 8]."
|
|
rgroup.long 0xD0++0xB
|
|
line.long 0x0 "RX_DATA_FIFO_RD1,Receiver data FIFO read"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA0,RX data (read from RX data FIFO)."
|
|
line.long 0x4 "RX_DATA_FIFO_RD2,Receiver data FIFO read"
|
|
hexmask.long.byte 0x4 8.--15. 1. "DATA1,RX data (read from RX data FIFO second byte)."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA0,RX data (read from RX data FIFO first byte)."
|
|
line.long 0x8 "RX_DATA_FIFO_RD4,Receiver data FIFO read"
|
|
hexmask.long.byte 0x8 24.--31. 1. "DATA3,RX data (read from RX data FIFO fourth byte)."
|
|
newline
|
|
hexmask.long.byte 0x8 16.--23. 1. "DATA2,RX data (read from RX data FIFO third byte)."
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "DATA1,RX data (read from RX data FIFO second byte)."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "DATA0,RX data (read from RX data FIFO first byte)."
|
|
rgroup.long 0xE0++0x3
|
|
line.long 0x0 "RX_DATA_FIFO_RD1_SILENT,Receiver data FIFO silent read"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA0,RX data (read from RX data FIFO)."
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "SLOW_CA_CTL,Slow cache control"
|
|
bitfld.long 0x0 31. "ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "PREF_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "SET_ADDR,this is for debug purpose only and should be hidden to customers in technical document" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "WAY,this is for debug purpose only and should be hidden to customers in technical document" "0,1,2,3"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "SLOW_CA_CMD,Slow cache command"
|
|
bitfld.long 0x0 0. "INV,Cache and prefetch buffer invalidation." "0,1"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "FAST_CA_CTL,Fast cache control"
|
|
bitfld.long 0x0 31. "ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "PREF_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "SET_ADDR,this is for debug purpose only and should be hidden to customers in technical document" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "WAY,this is for debug purpose only and should be hidden to customers in technical document" "0,1,2,3"
|
|
group.long 0x188++0x3
|
|
line.long 0x0 "FAST_CA_CMD,Fast cache command"
|
|
bitfld.long 0x0 0. "INV,See SLOW_CA_CMD.INV." "0,1"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "CRYPTO_CMD,Cryptography Command"
|
|
bitfld.long 0x0 0. "START,SW sets this field to '1' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR). HW sets this field to '0' to indicate that the operation has completed. Once completed the result of the operation can be read from.." "0,1"
|
|
group.long 0x220++0xF
|
|
line.long 0x0 "CRYPTO_INPUT0,Cryptography input 0"
|
|
hexmask.long 0x0 0.--31. 1. "INPUT,Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0]."
|
|
line.long 0x4 "CRYPTO_INPUT1,Cryptography input 1"
|
|
hexmask.long 0x4 0.--31. 1. "INPUT,Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0]."
|
|
line.long 0x8 "CRYPTO_INPUT2,Cryptography input 2"
|
|
hexmask.long 0x8 0.--31. 1. "INPUT,Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0]."
|
|
line.long 0xC "CRYPTO_INPUT3,Cryptography input 3"
|
|
hexmask.long 0xC 0.--31. 1. "INPUT,Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0]."
|
|
wgroup.long 0x240++0xF
|
|
line.long 0x0 "CRYPTO_KEY0,Cryptography key 0"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0]."
|
|
line.long 0x4 "CRYPTO_KEY1,Cryptography key 1"
|
|
hexmask.long 0x4 0.--31. 1. "KEY,Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0]."
|
|
line.long 0x8 "CRYPTO_KEY2,Cryptography key 2"
|
|
hexmask.long 0x8 0.--31. 1. "KEY,Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0]."
|
|
line.long 0xC "CRYPTO_KEY3,Cryptography key 3"
|
|
hexmask.long 0xC 0.--31. 1. "KEY,Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0]."
|
|
group.long 0x260++0xF
|
|
line.long 0x0 "CRYPTO_OUTPUT0,Cryptography output 0"
|
|
hexmask.long 0x0 0.--31. 1. "OUTPUT,Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0]."
|
|
line.long 0x4 "CRYPTO_OUTPUT1,Cryptography output 1"
|
|
hexmask.long 0x4 0.--31. 1. "OUTPUT,Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0]."
|
|
line.long 0x8 "CRYPTO_OUTPUT2,Cryptography output 2"
|
|
hexmask.long 0x8 0.--31. 1. "OUTPUT,Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0]."
|
|
line.long 0xC "CRYPTO_OUTPUT3,Cryptography output 3"
|
|
hexmask.long 0xC 0.--31. 1. "OUTPUT,Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0]."
|
|
group.long 0x7C0++0xB
|
|
line.long 0x0 "INTR,Interrupt register"
|
|
bitfld.long 0x0 5. "RX_DATA_FIFO_UNDERFLOW,Activated in MMIO mode on an AHB-Lite read transfer from the RX data FIFO (RX_DATA_FIFO_RD1 RX_DATA_FIFO_RD2 RX_DATA_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TX_DATA_FIFO_OVERFLOW,Activated in MMIO mode on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1 TX_DATA_FIFO_WR2 TX_DATA_FIFO_WR4) with not enough free entries available." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TX_CMD_FIFO_OVERFLOW,Activated in MMIO mode on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "XIP_ALIGNMENT_ERROR,Activated in XIP mode if:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TR_RX_REQ,Activated in MMIO mode when a RX data FIFO trigger 'tr_rx_req' is activated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TR_TX_REQ,Activated in MMIO mode when a TX data FIFO trigger 'tr_tx_req' is activated." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set register"
|
|
bitfld.long 0x4 5. "RX_DATA_FIFO_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TX_DATA_FIFO_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TX_CMD_FIFO_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "XIP_ALIGNMENT_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TR_RX_REQ,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TR_TX_REQ,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 5. "RX_DATA_FIFO_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "TX_DATA_FIFO_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "TX_CMD_FIFO_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "XIP_ALIGNMENT_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TR_RX_REQ,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TR_TX_REQ,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0x7CC++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x0 5. "RX_DATA_FIFO_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TX_DATA_FIFO_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TX_CMD_FIFO_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "XIP_ALIGNMENT_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TR_RX_REQ,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TR_TX_REQ,Logical and of corresponding request and mask bits." "0,1"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??6*")||cpuis("CYS06??7*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40420800 ad:0x40420880 ad:0x40420900 ad:0x40420980)
|
|
tree "DEVICE[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,Device enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 16.--17. "DATA_SEL,Specifies the connection of the IP's data lines (spi_data[0] ... spi_data[7]) to the device's data lines (SI/IO0 SO/IO1 IO2 IO3 IO4 IO5 IO6 IO7):" "0: spi_data[0] = IO0,1: spi_data[2] = IO0,2: spi_data[4] = IO0,3: spi_data[6] = IO0"
|
|
bitfld.long 0x0 8. "CRYPTO_EN,Cryptography on read/write accesses:" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "WR_EN,Write enable:" "0: write transfers are not allowed to this device,1: write transfers are allowed to this device"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "ADDR,Device region base address"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR,Specifies the base address of the device region. If the device region is 2^m Bytes ADDR MUST be a multiple of 2^m."
|
|
line.long 0x4 "MASK,Device region mask"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "MASK,Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]."
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "ADDR_CTL,Address control"
|
|
bitfld.long 0x0 8. "DIV2,Specifies if the AHB-Lite bus transfer address is divided by 2 or not:" "0: No divide by 2,1: Divide by 2"
|
|
bitfld.long 0x0 0.--1. "SIZE2,Specifies the size of the XIP device address in Bytes:" "0: 1 Byte address,1: 2 Byte address,2: 3 Byte address,3: 4 Byte address"
|
|
group.long ($2+0x40)++0x13
|
|
line.long 0x0 "RD_CMD_CTL,Read command control"
|
|
bitfld.long 0x0 31. "PRESENT,Presence of command field:" "0: not present,1: present"
|
|
bitfld.long 0x0 16.--17. "WIDTH,Width of data transfer:" "0: 1 bit/cycle,1: 2 bits/cycle,2: 4 bits/cycle,3: 8 bits/cycle"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CODE,Command byte code."
|
|
line.long 0x4 "RD_ADDR_CTL,Read address control"
|
|
bitfld.long 0x4 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
line.long 0x8 "RD_MODE_CTL,Read mode control"
|
|
bitfld.long 0x8 31. "PRESENT,Presence of mode field:" "0: not present,1: present"
|
|
bitfld.long 0x8 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "CODE,Mode byte code."
|
|
line.long 0xC "RD_DUMMY_CTL,Read dummy control"
|
|
bitfld.long 0xC 31. "PRESENT,Presence of dummy cycles:" "0: not present,1: present"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIZE5,Number of dummy cycles (minus 1):"
|
|
line.long 0x10 "RD_DATA_CTL,Read data control"
|
|
bitfld.long 0x10 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "WR_CMD_CTL,Write command control"
|
|
bitfld.long 0x0 31. "PRESENT,Presence of command field:" "0: not present,1: present"
|
|
bitfld.long 0x0 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CODE,Command byte code."
|
|
line.long 0x4 "WR_ADDR_CTL,Write address control"
|
|
bitfld.long 0x4 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
line.long 0x8 "WR_MODE_CTL,Write mode control"
|
|
bitfld.long 0x8 31. "PRESENT,Presence of mode field:" "0: not present,1: present"
|
|
bitfld.long 0x8 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "CODE,Mode byte code."
|
|
line.long 0xC "WR_DUMMY_CTL,Write dummy control"
|
|
bitfld.long 0xC 31. "PRESENT,Presence of dummy cycles:" "0: not present,1: present"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIZE5,Number of dummy cycles (minus 1):"
|
|
line.long 0x10 "WR_DATA_CTL,Write data control"
|
|
bitfld.long 0x10 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40420000
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40420800 ad:0x40420880 ad:0x40420900)
|
|
tree "DEVICE[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,Device enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 16.--17. "DATA_SEL,Specifies the connection of the IP's data lines (spi_data[0] ... spi_data[7]) to the device's data lines (SI/IO0 SO/IO1 IO2 IO3 IO4 IO5 IO6 IO7):" "0: spi_data[0] = IO0,1: spi_data[2] = IO0,2: spi_data[4] = IO0,3: spi_data[6] = IO0"
|
|
bitfld.long 0x0 8. "CRYPTO_EN,Cryptography on read/write accesses:" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "WR_EN,Write enable:" "0: write transfers are not allowed to this device,1: write transfers are allowed to this device"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "ADDR,Device region base address"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR,Specifies the base address of the device region. If the device region is 2^m Bytes ADDR MUST be a multiple of 2^m."
|
|
line.long 0x4 "MASK,Device region mask"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "MASK,Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]."
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "ADDR_CTL,Address control"
|
|
bitfld.long 0x0 8. "DIV2,Specifies if the AHB-Lite bus transfer address is divided by 2 or not:" "0: No divide by 2,1: Divide by 2"
|
|
bitfld.long 0x0 0.--1. "SIZE2,Specifies the size of the XIP device address in Bytes:" "0: 1 Byte address,1: 2 Byte address,2: 3 Byte address,3: 4 Byte address"
|
|
group.long ($2+0x40)++0x13
|
|
line.long 0x0 "RD_CMD_CTL,Read command control"
|
|
bitfld.long 0x0 31. "PRESENT,Presence of command field:" "0: not present,1: present"
|
|
bitfld.long 0x0 16.--17. "WIDTH,Width of data transfer:" "0: 1 bit/cycle,1: 2 bits/cycle,2: 4 bits/cycle,3: 8 bits/cycle"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CODE,Command byte code."
|
|
line.long 0x4 "RD_ADDR_CTL,Read address control"
|
|
bitfld.long 0x4 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
line.long 0x8 "RD_MODE_CTL,Read mode control"
|
|
bitfld.long 0x8 31. "PRESENT,Presence of mode field:" "0: not present,1: present"
|
|
bitfld.long 0x8 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "CODE,Mode byte code."
|
|
line.long 0xC "RD_DUMMY_CTL,Read dummy control"
|
|
bitfld.long 0xC 31. "PRESENT,Presence of dummy cycles:" "0: not present,1: present"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIZE5,Number of dummy cycles (minus 1):"
|
|
line.long 0x10 "RD_DATA_CTL,Read data control"
|
|
bitfld.long 0x10 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "WR_CMD_CTL,Write command control"
|
|
bitfld.long 0x0 31. "PRESENT,Presence of command field:" "0: not present,1: present"
|
|
bitfld.long 0x0 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CODE,Command byte code."
|
|
line.long 0x4 "WR_ADDR_CTL,Write address control"
|
|
bitfld.long 0x4 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
line.long 0x8 "WR_MODE_CTL,Write mode control"
|
|
bitfld.long 0x8 31. "PRESENT,Presence of mode field:" "0: not present,1: present"
|
|
bitfld.long 0x8 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "CODE,Mode byte code."
|
|
line.long 0xC "WR_DUMMY_CTL,Write dummy control"
|
|
bitfld.long 0xC 31. "PRESENT,Presence of dummy cycles:" "0: not present,1: present"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIZE5,Number of dummy cycles (minus 1):"
|
|
line.long 0x10 "WR_DATA_CTL,Write data control"
|
|
bitfld.long 0x10 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40420000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40420800 ad:0x40420880 ad:0x40420900)
|
|
tree "DEVICE[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,Device enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 16.--17. "DATA_SEL,Specifies the connection of the IP's data lines (spi_data[0] ... spi_data[7]) to the device's data lines (SI/IO0 SO/IO1 IO2 IO3 IO4 IO5 IO6 IO7):" "0: spi_data[0] = IO0,1: spi_data[2] = IO0,2: spi_data[4] = IO0,3: spi_data[6] = IO0"
|
|
bitfld.long 0x0 8. "CRYPTO_EN,Cryptography on read/write accesses:" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "WR_EN,Write enable:" "0: write transfers are not allowed to this device,1: write transfers are allowed to this device"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "ADDR,Device region base address"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR,Specifies the base address of the device region. If the device region is 2^m Bytes ADDR MUST be a multiple of 2^m."
|
|
line.long 0x4 "MASK,Device region mask"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "MASK,Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]."
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "ADDR_CTL,Address control"
|
|
bitfld.long 0x0 8. "DIV2,Specifies if the AHB-Lite bus transfer address is divided by 2 or not:" "0: No divide by 2,1: Divide by 2"
|
|
bitfld.long 0x0 0.--1. "SIZE2,Specifies the size of the XIP device address in Bytes:" "0: 1 Byte address,1: 2 Byte address,2: 3 Byte address,3: 4 Byte address"
|
|
group.long ($2+0x40)++0x13
|
|
line.long 0x0 "RD_CMD_CTL,Read command control"
|
|
bitfld.long 0x0 31. "PRESENT,Presence of command field:" "0: not present,1: present"
|
|
bitfld.long 0x0 16.--17. "WIDTH,Width of data transfer:" "0: 1 bit/cycle,1: 2 bits/cycle,2: 4 bits/cycle,3: 8 bits/cycle"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CODE,Command byte code."
|
|
line.long 0x4 "RD_ADDR_CTL,Read address control"
|
|
bitfld.long 0x4 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
line.long 0x8 "RD_MODE_CTL,Read mode control"
|
|
bitfld.long 0x8 31. "PRESENT,Presence of mode field:" "0: not present,1: present"
|
|
bitfld.long 0x8 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "CODE,Mode byte code."
|
|
line.long 0xC "RD_DUMMY_CTL,Read dummy control"
|
|
bitfld.long 0xC 31. "PRESENT,Presence of dummy cycles:" "0: not present,1: present"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIZE5,Number of dummy cycles (minus 1):"
|
|
line.long 0x10 "RD_DATA_CTL,Read data control"
|
|
bitfld.long 0x10 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "WR_CMD_CTL,Write command control"
|
|
bitfld.long 0x0 31. "PRESENT,Presence of command field:" "0: not present,1: present"
|
|
bitfld.long 0x0 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CODE,Command byte code."
|
|
line.long 0x4 "WR_ADDR_CTL,Write address control"
|
|
bitfld.long 0x4 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
line.long 0x8 "WR_MODE_CTL,Write mode control"
|
|
bitfld.long 0x8 31. "PRESENT,Presence of mode field:" "0: not present,1: present"
|
|
bitfld.long 0x8 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "CODE,Mode byte code."
|
|
line.long 0xC "WR_DUMMY_CTL,Write dummy control"
|
|
bitfld.long 0xC 31. "PRESENT,Presence of dummy cycles:" "0: not present,1: present"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIZE5,Number of dummy cycles (minus 1):"
|
|
line.long 0x10 "WR_DATA_CTL,Write data control"
|
|
bitfld.long 0x10 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40420000
|
|
endif
|
|
tree.end
|
|
tree "SRSS (System Resources Subsystem)"
|
|
base ad:0x40260000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "PWR_CTL,Power Mode Control"
|
|
rbitfld.long 0x0 31. "ACT_REF_OK,Indicates that the normal mode of the Active Reference is ready." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "ACT_REF_DIS,Disables the Active Reference. Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference. When enabling the Active Reference use ACT_REF_OK indicator to know when it is ready. This.." "0: Active Reference is enabled,1: Active Reference is disabled"
|
|
newline
|
|
bitfld.long 0x0 29. "VREFBUF_DIS,Disable the 800mV voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "VREFBUF_LPMODE,Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1." "0: Voltage Reference Buffer operates in normal mode,1: Voltage Reference Buffer operates in low power.."
|
|
newline
|
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bitfld.long 0x0 27. "PLL_LS_BYPASS,Bypass level shifter inside the PLL." "0: Do not bypass the level shifter,1: Bypass the level shifter"
|
|
newline
|
|
bitfld.long 0x0 26. "BGREF_LPMODE,Control the power mode of the Bandgap Voltage and Current References. This applies to voltage and current generation and is different than the reference voltage buffer. The value in this register is ignored and normal mode is used until.." "0: Active Bandgap Voltage and Current Reference..,1: Active Bandgap Voltage and Current Reference.."
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|
newline
|
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bitfld.long 0x0 25. "PORBOD_LPMODE,Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE." "0: POR/BOD circuits operate in normal mode,1: POR/BOD circuits operate in low power mode"
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|
newline
|
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bitfld.long 0x0 24. "LINREG_LPMODE,Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE." "0: Linear Regulator operates in normal mode,1: Linear Regulator operates in low power mode"
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|
newline
|
|
bitfld.long 0x0 23. "LINREG_DIS,Disable the linear Core Regulator. This is only legal when the on-chip buck regulator supplies vccd but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE." "0: Linear regulator is on,1: Linear regulator is off"
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|
newline
|
|
bitfld.long 0x0 22. "NWELL_REG_DIS,Disable the Nwell regulator. This is only legal when the on-chip buck regulator supplies vccd but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE." "0: Nwell Regulator is on,1: Nwell Regulator is off"
|
|
newline
|
|
bitfld.long 0x0 21. "RET_REG_DIS,Disable the Retention regulator. This is only legal when the on-chip buck regulator supplies vccd but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE." "0: Retention Regulator is on,1: Retention Regulator is off"
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|
newline
|
|
bitfld.long 0x0 20. "DPSLP_REG_DIS,Disable the DeepSleep regulator. This is only legal when the on-chip buck regulator supplies vccd but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE." "0: DeepSleep Regulator is on,1: DeepSleep Regulator is off"
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|
newline
|
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rbitfld.long 0x0 19. "VREFBUF_OK,Indicates that the voltage reference buffer is ready. Due to synchronization delays it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "IREF_LPMODE,Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE." "0: Current reference generator operates in normal..,1: Current reference generator operates in low.."
|
|
newline
|
|
rbitfld.long 0x0 5. "LPM_READY,Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES/POR/BOD/HIBERNATE wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. This register.." "0: If a low power circuit operation is requested,1: Normal operation"
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|
newline
|
|
rbitfld.long 0x0 4. "DEBUG_SESSION,Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)" "0: No debug session active,1: Debug session is active. Power modes behave.."
|
|
newline
|
|
rbitfld.long 0x0 0.--1. "POWER_MODE,Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon." "0: System is resetting.,1: At least one CPU is running.,2: No CPUs are running. Peripherals may be running.,3: Main high-frequency clock is off; low speed.."
|
|
line.long 0x4 "PWR_HIBERNATE,HIBERNATE Mode Register"
|
|
bitfld.long 0x4 31. "HIBERNATE,Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a.." "0,1"
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|
newline
|
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bitfld.long 0x4 30. "HIBERNATE_DISABLE,Hibernate disable bit." "0: Normal operation,1: Further writes to this register are ignored"
|
|
newline
|
|
hexmask.long.byte 0x4 24.--27. 1. "MASK_HIBPIN,When set HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the wakeup pins."
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|
newline
|
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hexmask.long.byte 0x4 20.--23. 1. "POLARITY_HIBPIN,Each bit sets the active polarity of the corresponding wakeup pin."
|
|
newline
|
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bitfld.long 0x4 19. "MASK_HIBWDT,When set HIBERNATE will wakeup if WDT matches" "0,1"
|
|
newline
|
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bitfld.long 0x4 18. "MASK_HIBALARM,When set HIBERNATE will wakeup for a RTC interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "FREEZE,Firmware sets this bit to freeze the configuration mode and state of all GPIOs and SIOs in the system. When entering HIBERNATE mode the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This.." "0,1"
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|
newline
|
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hexmask.long.byte 0x4 8.--15. 1. "UNLOCK,This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect except as noted in the FREEZE description."
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|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "TOKEN,Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register."
|
|
line.long 0x8 "PWR_LVD_CTL,Low Voltage Detector (LVD) Configuration Register"
|
|
bitfld.long 0x8 7. "HVLVD1_EN,Enable HVLVD1 voltage monitor. When the LVD is enabled it takes 20us for it to settle. There is no hardware stabilization counter and it may falsely trigger during settling. It is recommended that firmware keep the interrupt masked for at.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "HVLVD1_SRCSEL,Source selection for HVLVD1" "0: Select VDDD,1: Select AMUXBUSA (VDDD branch),2: N/A,3: N/A,4: Select AMUXBUSB (VDDD branch),?,?,?"
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|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "HVLVD1_TRIPSEL,Threshold selection for HVLVD1. Disable the LVD (HVLVD1_EN=0) before changing the threshold."
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "PWR_BUCK_CTL,Buck Control Register"
|
|
bitfld.long 0x0 31. "BUCK_OUT1_EN,Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES/POR/BOD/HIBERNATE. The regulator takes up to 600us to charge the external capacitor. If there is.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "BUCK_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "BUCK_OUT1_SEL,N/A" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "PWR_BUCK_CTL2,Buck Control Register 2"
|
|
bitfld.long 0x4 31. "BUCK_OUT2_EN,Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging this will increase the.." "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "BUCK_OUT2_HW_SEL,Hardware control for vccbuck2 output. When this bit is set the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware it can directly control the enable signal for vccbuck2." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "BUCK_OUT2_SEL,Voltage output selection for vccbuck2 output. When increasing the voltage it can take up to 200us for the output voltage to settle. When decreasing the voltage the settling time depends on the load current." "0: 1,1: 1,2: 1,3: 1,4: 1,5: 1,6: 1,7: 1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "PWR_LVD_STATUS,Low Voltage Detector (LVD) Status Register"
|
|
bitfld.long 0x0 0. "HVLVD1_OK,HVLVD1 output." "0: below voltage threshold,1: above voltage threshold"
|
|
group.long 0x180++0xB
|
|
line.long 0x0 "WDT_CTL,Watchdog Counter Control Register"
|
|
bitfld.long 0x0 30.--31. "WDT_LOCK,Prohibits writing to WDT_* CLK_ILO_CONFIG CLK_SELECT.LFCLK_SEL and CLK_TRIM_ILO_CTL registers when not equal 0. Requires at least two different writes to unlock. A change in WDT_LOCK takes effect beginning with the next write cycle." "0: No effect,1: Clears bit 0,2: Clears bit 1,3: Sets both bits 0 and 1"
|
|
newline
|
|
bitfld.long 0x0 0. "WDT_EN,Enable this watchdog timer. This field is retained during Deep Sleep and Hibernate modes. Even though the default value is 1 in most cases the Cortex-M0+ executing the SROM code will change the value of this bit to 0. So effectively the user.." "0,1"
|
|
line.long 0x4 "WDT_CNT,Watchdog Counter Count Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "COUNTER,Current value of WDT Counter. The write feature of this register is for verification purposes has no synchronization and can only be applied when the WDT is off. When writing the value is updated immediately in the WDT counter but it will.."
|
|
line.long 0x8 "WDT_MATCH,Watchdog Counter Match Register"
|
|
hexmask.long.byte 0x8 16.--19. 1. "IGNORE_BITS,The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Up to 12 MSB can be ignored. Settings >12.."
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "MATCH,Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match)."
|
|
group.long 0x500++0x7
|
|
line.long 0x0 "CLK_SELECT,Clock selection register"
|
|
bitfld.long 0x0 15. "PUMP_ENABLE,Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE. To change the settings do the following:" "0,1"
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|
newline
|
|
bitfld.long 0x0 12.--14. "PUMP_DIV,Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source." "0: Transparent mode feed through selected clock..,1: Divide selected clock source by 2,2: Divide selected clock source by 4,3: Divide selected clock source by 8,4: Divide selected clock source by 16,?,?,?"
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|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "PUMP_SEL,Selects clock PATH<k> where k=PUMP_SEL. The output of this mux goes to the PUMP_DIV to make PUMPCLK Each product has a specific number of available clock paths. Selecting a path that is not implemented on a product will result in undefined.."
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|
newline
|
|
bitfld.long 0x0 0.--1. "LFCLK_SEL,Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK.." "0: ILO - Internal Low-speed Oscillator,1: WCO - Watch-Crystal Oscillator. Requires Backup..,2: ALTLF - Alternate Low-Frequency Clock.,3: PILO - Precision ILO. If present it works in.."
|
|
line.long 0x4 "CLK_TIMER_CTL,Timer Clock Control Register"
|
|
bitfld.long 0x4 31. "ENABLE,Enable for TIMERCLK." "0: TIMERCLK is off,1: TIMERCLK is enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "TIMER_DIV,Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TIMERCLK Allows for integer divisions in the range [1 256]. Do not change this setting while the timer is enabled."
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|
newline
|
|
bitfld.long 0x4 8.--9. "TIMER_HF0_DIV,Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle then no division is required (NO_DIV). Otherwise select a divide ratio of 2 4 or 8 before.." "0: Transparent mode feed through selected clock..,1: Divide HFCLK0 by 2.,2: Divide HFCLK0 by 4.,3: Divide HFCLK0 by 8."
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|
newline
|
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bitfld.long 0x4 0. "TIMER_SEL,Select source for TIMERCLK. The output of this mux can be further divided using TIMER_DIV." "0: IMO - Internal Main Oscillator,1: Select the output of the predivider configured.."
|
|
group.long 0x50C++0x13
|
|
line.long 0x0 "CLK_ILO_CONFIG,ILO Configuration"
|
|
bitfld.long 0x0 31. "ENABLE,Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. After enabling it takes at most two cycles to reach the accuracy spec." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ILO_BACKUP,If backup domain is present on this product this register indicates that ILO should stay enabled for use by backup domain during XRES HIBERNATE mode and through power-related resets like BOD on VDDD/VCCD. Writes to this field are ignored.." "0: ILO turns off at XRES/BOD event or HIBERNATE entry,1: ILO remains on if backup domain is present and.."
|
|
line.long 0x4 "CLK_IMO_CONFIG,IMO Configuration"
|
|
bitfld.long 0x4 31. "ENABLE,Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during HIBERNATE and XRES. It will automatically disable during DEEPSLEEP if DPSLP_ENABLE==0." "0,1"
|
|
line.long 0x8 "CLK_OUTPUT_FAST,Fast Clock Output Select Register"
|
|
hexmask.long.byte 0x8 24.--27. 1. "HFCLK_SEL1,Selects a HFCLK tree for use in fast clock output #1 logic"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "PATH_SEL1,Selects a clock path to use in fast clock output #1 logic. 0: FLL output"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "FAST_SEL1,Select signal for fast clock output #1"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "HFCLK_SEL0,Selects a HFCLK tree for use in fast clock output #0"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "PATH_SEL0,Selects a clock path to use in fast clock output #0 logic. 0: FLL output"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "FAST_SEL0,Select signal for fast clock output #0"
|
|
line.long 0xC "CLK_OUTPUT_SLOW,Slow Clock Output Select Register"
|
|
hexmask.long.byte 0xC 4.--7. 1. "SLOW_SEL1,Select signal for slow clock output #1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "SLOW_SEL0,Select signal for slow clock output #0"
|
|
line.long 0x10 "CLK_CAL_CNT1,Clock Calibration Counter 1"
|
|
rbitfld.long 0x10 31. "CAL_COUNTER_DONE,Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "CAL_COUNTER1,Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that.."
|
|
rgroup.long 0x520++0x3
|
|
line.long 0x0 "CLK_CAL_CNT2,Clock Calibration Counter 2"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CAL_COUNTER2,Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1 the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related.."
|
|
group.long 0x52C++0x3
|
|
line.long 0x0 "CLK_ECO_CONFIG,ECO Configuration Register"
|
|
bitfld.long 0x0 31. "ECO_EN,Master enable for ECO oscillator." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AGC_EN,Automatic Gain Control (AGC) enable. When set the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM. When low the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care when.." "0,1"
|
|
rgroup.long 0x530++0x3
|
|
line.long 0x0 "CLK_ECO_STATUS,ECO Status Register"
|
|
bitfld.long 0x0 1. "ECO_READY,Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled and it does not check the ECO output. It is recommended to also confirm ECO_OK==1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ECO_OK,Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec." "0,1"
|
|
group.long 0x53C++0x3
|
|
line.long 0x0 "CLK_PILO_CONFIG,Precision ILO Configuration Register"
|
|
bitfld.long 0x0 31. "PILO_EN,Enable PILO. When enabling PILO set PILO_EN=1 wait 1ms then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO clear PILO_EN=0 PILO_RESET_N=0 and PLO_CLK_EN=0 in the same write cycle." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "PILO_RESET_N,Reset the PILO. See PILO_EN field for required sequencing." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "PILO_CLK_EN,Enable the PILO clock output. See PILO_EN field for required sequencing." "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "PILO_FFREQ,Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz."
|
|
group.long 0x580++0x13
|
|
line.long 0x0 "CLK_FLL_CONFIG,FLL Configuration Register"
|
|
bitfld.long 0x0 31. "FLL_ENABLE,Master enable for FLL. The FLL requires firmware sequencing when enabling disabling and entering/exiting DEEPSLEEP." "0: Block is powered off,1: Block is powered on"
|
|
newline
|
|
bitfld.long 0x0 24. "FLL_OUTPUT_DIV,Control bits for Output divider. Set the divide value before enabling the FLL and do not change it while FLL is enabled." "0: no division,1: divide by 2"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--17. 1. "FLL_MULT,Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref)."
|
|
line.long 0x4 "CLK_FLL_CONFIG2,FLL Configuration Register 2"
|
|
hexmask.long.word 0x4 16.--24. 1. "LOCK_TOL,Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or to track a less accurate source. The tolerance should be set so that the FLL does.."
|
|
newline
|
|
hexmask.long.word 0x4 0.--12. 1. "FLL_REF_DIV,Control bits for reference divider. Set the divide value before enabling the FLL and do not change it while FLL is enabled."
|
|
line.long 0x8 "CLK_FLL_CONFIG3,FLL Configuration Register 3"
|
|
bitfld.long 0x8 28.--29. "BYPASS_SEL,Bypass mux located just after FLL output. See FLL_ENABLE description for instructions on how to use this field when enabling/disabling the FLL." "0: N/A,1: N/A,2: Select FLL reference input (bypass mode).,3: Select FLL output. Ignores lock indicator."
|
|
newline
|
|
hexmask.long.word 0x8 8.--20. 1. "SETTLING_COUNT,Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference.."
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "FLL_LF_PGAIN,FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "FLL_LF_IGAIN,FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN."
|
|
line.long 0xC "CLK_FLL_CONFIG4,FLL Configuration Register 4"
|
|
bitfld.long 0xC 31. "CCO_ENABLE,Enable the CCO. It is required to enable the CCO before using the FLL." "0: Block is powered off,1: Block is powered on"
|
|
newline
|
|
bitfld.long 0xC 30. "CCO_HW_UPDATE_DIS,Disable CCO frequency update by FLL hardware" "0: Hardware update of CCO settings is allowed,1: Hardware update of CCO settings is disabled"
|
|
newline
|
|
hexmask.long.word 0xC 16.--24. 1. "CCO_FREQ,CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range."
|
|
newline
|
|
bitfld.long 0xC 8.--10. "CCO_RANGE,Frequency range of CCO" "0: Target frequency is in range [48 64) MHz,1: Target frequency is in range [64 85) MHz,2: Target frequency is in range [85 113) MHz,3: Target frequency is in range [113 150) MHz,4: Target frequency is in range [150 200] MHz,?,?,?"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CCO_LIMIT,Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support)"
|
|
line.long 0x10 "CLK_FLL_STATUS,FLL Status Register"
|
|
rbitfld.long 0x10 2. "CCO_READY,This indicates that the CCO is internally settled and ready to use." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "UNLOCK_OCCURRED,N/A" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 0. "LOCKED,FLL Lock Indicator. LOCKED is high when FLL is within CLK_FLL_CONFIG2.LOCK_TOL. If FLL is outside LOCK_TOL LOCKED goes low. Note that this can happen during normal operation if FLL needs to recalculate due to a change in the reference clock .." "0,1"
|
|
group.long 0x700++0xB
|
|
line.long 0x0 "SRSS_INTR,SRSS Interrupt Register"
|
|
bitfld.long 0x0 5. "CLK_CAL,Clock calibration counter is done. This field is reset during DEEPSLEEP mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "HVLVD1,Interrupt for low voltage detector HVLVD1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WDT_MATCH,WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. W1C also feeds the watch dog. Missing 2 interrupts in a row will generate a reset. Due to internal synchronization it takes 2 SYSCLK cycles to update after a W1C." "0,1"
|
|
line.long 0x4 "SRSS_INTR_SET,SRSS Interrupt Set Register"
|
|
bitfld.long 0x4 5. "CLK_CAL,Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "HVLVD1,Set interrupt for low voltage detector HVLVD1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "WDT_MATCH,Set interrupt for low voltage detector WDT_MATCH" "0,1"
|
|
line.long 0x8 "SRSS_INTR_MASK,SRSS Interrupt Mask Register"
|
|
bitfld.long 0x8 5. "CLK_CAL,Mask for clock calibration done" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "HVLVD1,Mask for low voltage detector HVLVD1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "WDT_MATCH,Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. It will not however disable the WDT reset generation on 2 missed interrupts. When WDT resets the chip it also internally pends an interrupt that.." "0,1"
|
|
rgroup.long 0x70C++0x3
|
|
line.long 0x0 "SRSS_INTR_MASKED,SRSS Interrupt Masked Register"
|
|
bitfld.long 0x0 5. "CLK_CAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "HVLVD1,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WDT_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0x710++0x3
|
|
line.long 0x0 "SRSS_INTR_CFG,SRSS Interrupt Configuration Register"
|
|
bitfld.long 0x0 0.--1. "HVLVD1_EDGE_SEL,Sets which edge(s) will trigger an IRQ for HVLVD1" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
group.long 0x800++0x7
|
|
line.long 0x0 "RES_CAUSE,Reset Cause Observation Register"
|
|
bitfld.long 0x0 8. "RESET_MCWDT3,Multi-Counter Watchdog timer reset #3 has occurred since last power cycle. This hardware is not present in PSoC6 devices." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RESET_MCWDT2,Multi-Counter Watchdog timer reset #2 has occurred since last power cycle. This hardware is not present in PSoC6 devices." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RESET_MCWDT1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RESET_MCWDT0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RESET_SOFT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RESET_CSV_WCO_LOSS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RESET_DPSLP_FAULT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RESET_ACT_FAULT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RESET_WDT,N/A" "0,1"
|
|
line.long 0x4 "RES_CAUSE2,Reset Cause Observation Register 2"
|
|
hexmask.long.word 0x4 16.--31. 1. "RESET_CSV_HF_FREQ,Clock supervision logic requested a reset due to frequency error of high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero."
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "RESET_CSV_HF_LOSS,Clock supervision logic requested a reset due to loss of a high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero."
|
|
group.long 0x7F00++0xF
|
|
line.long 0x0 "PWR_TRIM_REF_CTL,Reference Trim Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "DPSLP_REF_ITRIM,DeepSleep current reference trim. This register is only reset by XRES/POR/BOD/HIBERNATE."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--24. 1. "DPSLP_REF_ABSTRIM,DeepSleep-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "DPSLP_REF_TCTRIM,DeepSleep-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE."
|
|
newline
|
|
bitfld.long 0x0 14. "ACT_REF_IBOOST,Active-Reference current boost. This register is only reset by XRES/POR/BOD/HIBERNATE." "0: normal operation,?"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "ACT_REF_ABSTRIM,Active-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE."
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "ACT_REF_ITRIM,Active-Reference current trim. This register is only reset by XRES/POR/BOD/HIBERNATE."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "ACT_REF_TCTRIM,Active-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE."
|
|
line.long 0x4 "PWR_TRIM_BODOVP_CTL,BOD/OVP Trim Register"
|
|
bitfld.long 0x4 17.--19. "LVPORBOD_ITRIM,LVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE." "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x4 14.--16. "LVPORBOD_OFSTRIM,LVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 10.--12. "LVPORBOD_TRIPSEL,LVPORBOD trip point selection. Monitors vccd. This register is only reset by XRES/POR/BOD/HIBERNATE." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 7.--9. "HVPORBOD_ITRIM,HVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "HVPORBOD_OFSTRIM,HVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "HVPORBOD_TRIPSEL,HVPORBOD trip point selection. Monitors vddd. This register is only reset by XRES/POR/BOD/HIBERNATE." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CLK_TRIM_CCO_CTL,CCO Trim Register"
|
|
bitfld.long 0x8 31. "ENABLE_CNT,Enables the automatic stabilization counter." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 24.--29. 1. "CCO_STABLE_CNT,Terminal count for the stabilization counter from CCO_ENABLE until stable."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "CCO_RCSTRIM,CCO reference current source trim."
|
|
line.long 0xC "CLK_TRIM_CCO_CTL2,CCO Trim Register 2"
|
|
hexmask.long.byte 0xC 20.--24. 1. "CCO_FCTRIM5,CCO frequency 5th range calibration"
|
|
newline
|
|
hexmask.long.byte 0xC 15.--19. 1. "CCO_FCTRIM4,CCO frequency 4th range calibration"
|
|
newline
|
|
hexmask.long.byte 0xC 10.--14. 1. "CCO_FCTRIM3,CCO frequency 3rd range calibration"
|
|
newline
|
|
hexmask.long.byte 0xC 5.--9. 1. "CCO_FCTRIM2,CCO frequency 2nd range calibration"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "CCO_FCTRIM1,CCO frequency 1st range calibration"
|
|
group.long 0x7F30++0x3
|
|
line.long 0x0 "PWR_TRIM_WAKE_CTL,Wakeup Trim Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WAKE_DELAY,Wakeup holdoff. Spec (fastest) wake time is achieved with a setting of 0. Additional delay can be added for debugging or workaround. The delay is counted by the IMO."
|
|
group.long 0xFF10++0x3
|
|
line.long 0x0 "PWR_TRIM_LVD_CTL,LVD Trim Register"
|
|
bitfld.long 0x0 4.--6. "HVLVD1_ITRIM,HVLVD1 current trim" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "HVLVD1_OFSTRIM,HVLVD1 offset trim" "0,1,2,3,4,5,6,7"
|
|
group.long 0xFF18++0x17
|
|
line.long 0x0 "CLK_TRIM_ILO_CTL,ILO Trim Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "ILO_FTRIM,ILO frequency trims. LSB step size is 1.5 percent (typical) of the frequency."
|
|
line.long 0x4 "PWR_TRIM_PWRSYS_CTL,Power System Trim Register"
|
|
bitfld.long 0x4 30.--31. "ACT_REG_BOOST,Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation but an application may limit its maximum current to less than that." "0: 50uA,1: 100uA,2: 150uA,3: 200uA"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "ACT_REG_TRIM,Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES/POR/BOD/HIBERNATE. Two voltages are supported: 0.9V and 1.1V. The codes for these are stored in SFLASH_LDO_0P9V_TRIM and.."
|
|
line.long 0x8 "CLK_TRIM_ECO_CTL,ECO Trim Register"
|
|
hexmask.long.byte 0x8 16.--21. 1. "ITRIM,Current Trim"
|
|
newline
|
|
bitfld.long 0x8 12.--13. "GTRIM,Gain Trim - Startup time" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "RTRIM,Feedback resistor Trim" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "FTRIM,Filter Trim - 3rd harmonic oscillation" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "ATRIM,Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal."
|
|
newline
|
|
bitfld.long 0x8 0.--2. "WDTRIM,Watch Dog Trim - Delta voltage below steady state level" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "CLK_TRIM_PILO_CTL,PILO Trim Register"
|
|
bitfld.long 0xC 28.--30. "PILO_VTDIFF_TRIM,Trim for VT-DIFF output (internal power supply)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "PILO_ISLOPE_TRIM,Trim for beta-multiplier current slope" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0xC 20.--24. 1. "PILO_RES_TRIM,Trim for beta-multiplier branch current"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "PILO_NBIAS_TRIM,Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 16.--17. "PILO_COMP_TRIM,Trim for comparator bias current." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 12.--14. "PILO_OSC_TRIM,Trim for current in oscillator block." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "PILO_CFREQ,Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz."
|
|
line.long 0x10 "CLK_TRIM_PILO_CTL2,PILO Trim Register 2"
|
|
hexmask.long.byte 0x10 16.--23. 1. "PILO_IREF_TRIM,Trim for current reference"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--12. 1. "PILO_IREFBM_TRIM,Trim for beta-multiplier current reference"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "PILO_VREF_TRIM,Trim for voltage reference"
|
|
line.long 0x14 "CLK_TRIM_PILO_CTL3,PILO Trim Register 3"
|
|
hexmask.long.word 0x14 0.--15. 1. "PILO_ENGOPT,Engineering options for PILO circuits"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "PWR_HIB_DATA[$1],HIBERNATE Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "HIB_DATA,Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "PWR_HIB_DATA[$1],HIBERNATE Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "HIB_DATA,Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 2. (list 0x0 0x1)(list ad:0x40260200 ad:0x40260240)
|
|
tree "MCWDT_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2+0x4)++0x1F
|
|
line.long 0x0 "MCWDT_CNTLOW,Multi-Counter Watchdog Sub-counters 0/1"
|
|
hexmask.long.word 0x0 16.--31. 1. "WDT_CTR1,Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. "WDT_CTR0,Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled."
|
|
line.long 0x4 "MCWDT_CNTHIGH,Multi-Counter Watchdog Sub-counter 2"
|
|
hexmask.long 0x4 0.--31. 1. "WDT_CTR2,Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled"
|
|
line.long 0x8 "MCWDT_MATCH,Multi-Counter Watchdog Counter Match Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "WDT_MATCH1,Match value for sub-counter 1 of this MCWDT"
|
|
hexmask.long.word 0x8 0.--15. 1. "WDT_MATCH0,Match value for sub-counter 0 of this MCWDT"
|
|
line.long 0xC "MCWDT_CONFIG,Multi-Counter Watchdog Counter Configuration"
|
|
hexmask.long.byte 0xC 24.--28. 1. "WDT_BITS2,Bit to observe for WDT_INT2:"
|
|
bitfld.long 0xC 16. "WDT_MODE2,Watchdog Counter 2 Mode." "0: Free running counter with no interrupt requests,1: Free running counter with interrupt request that.."
|
|
newline
|
|
bitfld.long 0xC 11. "WDT_CASCADE1_2,Cascade Watchdog Counters 1 2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters." "0: Independent counters,1: Cascaded counters"
|
|
bitfld.long 0xC 10. "WDT_CLEAR1,Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1)." "0: Free running counter,1: Clear on match"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "WDT_MODE1,Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1)." "0: Do nothing,1: Assert WDT_INTx,2: Assert WDT Reset,3: Assert WDT_INTx assert WDT Reset after 3rd.."
|
|
bitfld.long 0xC 3. "WDT_CASCADE0_1,Cascade Watchdog Counters 0 1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0." "0: Independent counters,1: Cascaded counters"
|
|
newline
|
|
bitfld.long 0xC 2. "WDT_CLEAR0,Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1)." "0: Free running counter,1: Clear on match"
|
|
bitfld.long 0xC 0.--1. "WDT_MODE0,Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0)." "0: Do nothing,1: Assert WDT_INTx,2: Assert WDT Reset,3: Assert WDT_INTx assert WDT Reset after 3rd.."
|
|
line.long 0x10 "MCWDT_CTL,Multi-Counter Watchdog Counter Control"
|
|
bitfld.long 0x10 19. "WDT_RESET2,Resets counter 2 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect." "0,1"
|
|
rbitfld.long 0x10 17. "WDT_ENABLED2,Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles." "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. "WDT_ENABLE2,Enable subcounter 2. May take up to 2 LFCLK cycles to take effect." "0: Counter is disabled,1: Counter is enabled"
|
|
bitfld.long 0x10 11. "WDT_RESET1,Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect." "0,1"
|
|
newline
|
|
rbitfld.long 0x10 9. "WDT_ENABLED1,Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles." "0,1"
|
|
bitfld.long 0x10 8. "WDT_ENABLE1,Enable subcounter 1. May take up to 2 LFCLK cycles to take effect." "0: Counter is disabled,1: Counter is enabled"
|
|
newline
|
|
bitfld.long 0x10 3. "WDT_RESET0,Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect." "0,1"
|
|
rbitfld.long 0x10 1. "WDT_ENABLED0,Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "WDT_ENABLE0,Enable subcounter 0. May take up to 2 LFCLK cycles to take effect." "0: Counter is disabled,1: Counter is enabled"
|
|
line.long 0x14 "MCWDT_INTR,Multi-Counter Watchdog Counter Interrupt Register"
|
|
bitfld.long 0x14 2. "MCWDT_INT2,MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3." "0,1"
|
|
bitfld.long 0x14 1. "MCWDT_INT1,MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "MCWDT_INT0,MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3." "0,1"
|
|
line.long 0x18 "MCWDT_INTR_SET,Multi-Counter Watchdog Counter Interrupt Set Register"
|
|
bitfld.long 0x18 2. "MCWDT_INT2,Set interrupt for MCWDT_INT2" "0,1"
|
|
bitfld.long 0x18 1. "MCWDT_INT1,Set interrupt for MCWDT_INT1" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "MCWDT_INT0,Set interrupt for MCWDT_INT0" "0,1"
|
|
line.long 0x1C "MCWDT_INTR_MASK,Multi-Counter Watchdog Counter Interrupt Mask Register"
|
|
bitfld.long 0x1C 2. "MCWDT_INT2,Interrupt Mask for sub-counter 2. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1." "0,1"
|
|
bitfld.long 0x1C 1. "MCWDT_INT1,Interrupt Mask for sub-counter 1. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "MCWDT_INT0,Interrupt Mask for sub-counter 0. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1." "0,1"
|
|
rgroup.long ($2+0x24)++0x3
|
|
line.long 0x0 "MCWDT_INTR_MASKED,Multi-Counter Watchdog Counter Interrupt Masked Register"
|
|
bitfld.long 0x0 2. "MCWDT_INT2,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 1. "MCWDT_INT1,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MCWDT_INT0,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long ($2+0x28)++0x3
|
|
line.long 0x0 "MCWDT_LOCK,Multi-Counter Watchdog Counter Lock Register"
|
|
bitfld.long 0x0 30.--31. "MCWDT_LOCK,Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock." "0: No effect,1: Clears bit 0,2: Clears bit 1,3: Sets both bits 0 and 1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40260000
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 2. (list 0x0 0x1)(list ad:0x40260200 ad:0x40260240)
|
|
tree "MCWDT_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2+0x4)++0x1F
|
|
line.long 0x0 "MCWDT_CNTLOW,Multi-Counter Watchdog Sub-counters 0/1"
|
|
hexmask.long.word 0x0 16.--31. 1. "WDT_CTR1,Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. "WDT_CTR0,Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled."
|
|
line.long 0x4 "MCWDT_CNTHIGH,Multi-Counter Watchdog Sub-counter 2"
|
|
hexmask.long 0x4 0.--31. 1. "WDT_CTR2,Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled"
|
|
line.long 0x8 "MCWDT_MATCH,Multi-Counter Watchdog Counter Match Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "WDT_MATCH1,Match value for sub-counter 1 of this MCWDT"
|
|
hexmask.long.word 0x8 0.--15. 1. "WDT_MATCH0,Match value for sub-counter 0 of this MCWDT"
|
|
line.long 0xC "MCWDT_CONFIG,Multi-Counter Watchdog Counter Configuration"
|
|
hexmask.long.byte 0xC 24.--28. 1. "WDT_BITS2,Bit to observe for WDT_INT2:"
|
|
bitfld.long 0xC 16. "WDT_MODE2,Watchdog Counter 2 Mode." "0: Free running counter with no interrupt requests,1: Free running counter with interrupt request that.."
|
|
newline
|
|
bitfld.long 0xC 11. "WDT_CASCADE1_2,Cascade Watchdog Counters 1 2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters." "0: Independent counters,1: Cascaded counters"
|
|
bitfld.long 0xC 10. "WDT_CLEAR1,Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1)." "0: Free running counter,1: Clear on match"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "WDT_MODE1,Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1)." "0: Do nothing,1: Assert WDT_INTx,2: Assert WDT Reset,3: Assert WDT_INTx assert WDT Reset after 3rd.."
|
|
bitfld.long 0xC 3. "WDT_CASCADE0_1,Cascade Watchdog Counters 0 1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0." "0: Independent counters,1: Cascaded counters"
|
|
newline
|
|
bitfld.long 0xC 2. "WDT_CLEAR0,Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1)." "0: Free running counter,1: Clear on match"
|
|
bitfld.long 0xC 0.--1. "WDT_MODE0,Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0)." "0: Do nothing,1: Assert WDT_INTx,2: Assert WDT Reset,3: Assert WDT_INTx assert WDT Reset after 3rd.."
|
|
line.long 0x10 "MCWDT_CTL,Multi-Counter Watchdog Counter Control"
|
|
bitfld.long 0x10 19. "WDT_RESET2,Resets counter 2 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect." "0,1"
|
|
rbitfld.long 0x10 17. "WDT_ENABLED2,Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles." "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. "WDT_ENABLE2,Enable subcounter 2. May take up to 2 LFCLK cycles to take effect." "0: Counter is disabled,1: Counter is enabled"
|
|
bitfld.long 0x10 11. "WDT_RESET1,Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect." "0,1"
|
|
newline
|
|
rbitfld.long 0x10 9. "WDT_ENABLED1,Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles." "0,1"
|
|
bitfld.long 0x10 8. "WDT_ENABLE1,Enable subcounter 1. May take up to 2 LFCLK cycles to take effect." "0: Counter is disabled,1: Counter is enabled"
|
|
newline
|
|
bitfld.long 0x10 3. "WDT_RESET0,Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect." "0,1"
|
|
rbitfld.long 0x10 1. "WDT_ENABLED0,Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "WDT_ENABLE0,Enable subcounter 0. May take up to 2 LFCLK cycles to take effect." "0: Counter is disabled,1: Counter is enabled"
|
|
line.long 0x14 "MCWDT_INTR,Multi-Counter Watchdog Counter Interrupt Register"
|
|
bitfld.long 0x14 2. "MCWDT_INT2,MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3." "0,1"
|
|
bitfld.long 0x14 1. "MCWDT_INT1,MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "MCWDT_INT0,MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3." "0,1"
|
|
line.long 0x18 "MCWDT_INTR_SET,Multi-Counter Watchdog Counter Interrupt Set Register"
|
|
bitfld.long 0x18 2. "MCWDT_INT2,Set interrupt for MCWDT_INT2" "0,1"
|
|
bitfld.long 0x18 1. "MCWDT_INT1,Set interrupt for MCWDT_INT1" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "MCWDT_INT0,Set interrupt for MCWDT_INT0" "0,1"
|
|
line.long 0x1C "MCWDT_INTR_MASK,Multi-Counter Watchdog Counter Interrupt Mask Register"
|
|
bitfld.long 0x1C 2. "MCWDT_INT2,Interrupt Mask for sub-counter 2. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1." "0,1"
|
|
bitfld.long 0x1C 1. "MCWDT_INT1,Interrupt Mask for sub-counter 1. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "MCWDT_INT0,Interrupt Mask for sub-counter 0. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1." "0,1"
|
|
rgroup.long ($2+0x24)++0x3
|
|
line.long 0x0 "MCWDT_INTR_MASKED,Multi-Counter Watchdog Counter Interrupt Masked Register"
|
|
bitfld.long 0x0 2. "MCWDT_INT2,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 1. "MCWDT_INT1,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MCWDT_INT0,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long ($2+0x28)++0x3
|
|
line.long 0x0 "MCWDT_LOCK,Multi-Counter Watchdog Counter Lock Register"
|
|
bitfld.long 0x0 30.--31. "MCWDT_LOCK,Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock." "0: No effect,1: Clears bit 0,2: Clears bit 1,3: Sets both bits 0 and 1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40260000
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x300)++0x3
|
|
line.long 0x0 "CLK_DSI_SELECT[$1],Clock DSI Select Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DSI_MUX,Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It.."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x300)++0x3
|
|
line.long 0x0 "CLK_DSI_SELECT[$1],Clock DSI Select Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DSI_MUX,Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It.."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x340)++0x3
|
|
line.long 0x0 "CLK_PATH_SELECT[$1],Clock Path Select Register"
|
|
bitfld.long 0x0 0.--2. "PATH_MUX,Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior." "0: IMO - Internal R/C Oscillator,1: EXTCLK - External Clock Pin,2: ECO - External-Crystal Oscillator,3: ALTHF - Alternate High-Frequency clock input..,4: DSI_MUX - Output of DSI mux for this path. Using..,?,?,?"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x340)++0x3
|
|
line.long 0x0 "CLK_PATH_SELECT[$1],Clock Path Select Register"
|
|
bitfld.long 0x0 0.--2. "PATH_MUX,Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior." "0: IMO - Internal R/C Oscillator,1: EXTCLK - External Clock Pin,2: ECO - External-Crystal Oscillator,3: ALTHF - Alternate High-Frequency clock input..,4: DSI_MUX - Output of DSI mux for this path. Using..,?,?,?"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x380)++0x3
|
|
line.long 0x0 "CLK_ROOT_SELECT[$1],Clock Root Select Register"
|
|
bitfld.long 0x0 31. "ENABLE,Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0 which cannot be disabled." "0,1"
|
|
bitfld.long 0x0 4.--5. "ROOT_DIV,Selects predivider value for this clock root and DSI input." "0: Transparent mode feed through selected clock..,1: Divide selected clock source by 2,2: Divide selected clock source by 4,3: Divide selected clock source by 8"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "ROOT_MUX,Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific) and the control and bypass mux selections of these are.."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x380)++0x3
|
|
line.long 0x0 "CLK_ROOT_SELECT[$1],Clock Root Select Register"
|
|
bitfld.long 0x0 31. "ENABLE,Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0 which cannot be disabled." "0,1"
|
|
bitfld.long 0x0 4.--5. "ROOT_DIV,Selects predivider value for this clock root and DSI input." "0: Transparent mode feed through selected clock..,1: Divide selected clock source by 2,2: Divide selected clock source by 4,3: Divide selected clock source by 8"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "ROOT_MUX,Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific) and the control and bypass mux selections of these are.."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x600)++0x3
|
|
line.long 0x0 "CLK_PLL_CONFIG[$1],PLL Configuration Register"
|
|
bitfld.long 0x0 31. "ENABLE,Master enable for PLL. Setup FEEDBACK_DIV REFERENCE_DIV and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL first deselect it using .BYPASS_SEL=PLL_REF wait at least six PLL clock cycles and then disable it with.." "0: Block is disabled,1: Block is enabled"
|
|
bitfld.long 0x0 28.--29. "BYPASS_SEL,Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running." "0: Automatic using lock indicator. When unlocked..,1: Same as AUTO,2: Select PLL reference input (bypass mode).,3: Select PLL output. Ignores lock indicator."
|
|
newline
|
|
bitfld.long 0x0 27. "PLL_LF_MODE,VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled." "0: VCO frequency is [200MHz,1: VCO frequency is [170MHz"
|
|
hexmask.long.byte 0x0 16.--20. 1. "OUTPUT_DIV,Control bits for Output divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "REFERENCE_DIV,Control bits for reference divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
hexmask.long.byte 0x0 0.--6. 1. "FEEDBACK_DIV,Control bits for feedback divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x600)++0x3
|
|
line.long 0x0 "CLK_PLL_CONFIG[$1],PLL Configuration Register"
|
|
bitfld.long 0x0 31. "ENABLE,Master enable for PLL. Setup FEEDBACK_DIV REFERENCE_DIV and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL first deselect it using .BYPASS_SEL=PLL_REF wait at least six PLL clock cycles and then disable it with.." "0: Block is disabled,1: Block is enabled"
|
|
bitfld.long 0x0 28.--29. "BYPASS_SEL,Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running." "0: Automatic using lock indicator. When unlocked..,1: Same as AUTO,2: Select PLL reference input (bypass mode).,3: Select PLL output. Ignores lock indicator."
|
|
newline
|
|
bitfld.long 0x0 27. "PLL_LF_MODE,VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled." "0: VCO frequency is [200MHz,1: VCO frequency is [170MHz"
|
|
hexmask.long.byte 0x0 16.--20. 1. "OUTPUT_DIV,Control bits for Output divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "REFERENCE_DIV,Control bits for reference divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
hexmask.long.byte 0x0 0.--6. 1. "FEEDBACK_DIV,Control bits for feedback divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x640)++0x3
|
|
line.long 0x0 "CLK_PLL_STATUS[$1],PLL Status Register"
|
|
bitfld.long 0x0 1. "UNLOCK_OCCURRED,This bit sets whenever the PLL Lock bit goes low and stays set until cleared by firmware." "0,1"
|
|
rbitfld.long 0x0 0. "LOCKED,PLL Lock Indicator" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x640)++0x3
|
|
line.long 0x0 "CLK_PLL_STATUS[$1],PLL Status Register"
|
|
bitfld.long 0x0 1. "UNLOCK_OCCURRED,This bit sets whenever the PLL Lock bit goes low and stays set until cleared by firmware." "0,1"
|
|
rbitfld.long 0x0 0. "LOCKED,PLL Lock Indicator" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "PWR_HIB_DATA[$1],HIBERNATE Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "HIB_DATA,Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 2. (list 0x0 0x1)(list ad:0x40260200 ad:0x40260240)
|
|
tree "MCWDT_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2+0x4)++0x1F
|
|
line.long 0x0 "MCWDT_CNTLOW,Multi-Counter Watchdog Sub-counters 0/1"
|
|
hexmask.long.word 0x0 16.--31. 1. "WDT_CTR1,Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. "WDT_CTR0,Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled."
|
|
line.long 0x4 "MCWDT_CNTHIGH,Multi-Counter Watchdog Sub-counter 2"
|
|
hexmask.long 0x4 0.--31. 1. "WDT_CTR2,Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled"
|
|
line.long 0x8 "MCWDT_MATCH,Multi-Counter Watchdog Counter Match Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "WDT_MATCH1,Match value for sub-counter 1 of this MCWDT"
|
|
hexmask.long.word 0x8 0.--15. 1. "WDT_MATCH0,Match value for sub-counter 0 of this MCWDT"
|
|
line.long 0xC "MCWDT_CONFIG,Multi-Counter Watchdog Counter Configuration"
|
|
hexmask.long.byte 0xC 24.--28. 1. "WDT_BITS2,Bit to observe for WDT_INT2:"
|
|
bitfld.long 0xC 16. "WDT_MODE2,Watchdog Counter 2 Mode." "0: Free running counter with no interrupt requests,1: Free running counter with interrupt request that.."
|
|
newline
|
|
bitfld.long 0xC 11. "WDT_CASCADE1_2,Cascade Watchdog Counters 1 2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters." "0: Independent counters,1: Cascaded counters"
|
|
bitfld.long 0xC 10. "WDT_CLEAR1,Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1)." "0: Free running counter,1: Clear on match"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "WDT_MODE1,Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1)." "0: Do nothing,1: Assert WDT_INTx,2: Assert WDT Reset,3: Assert WDT_INTx assert WDT Reset after 3rd.."
|
|
bitfld.long 0xC 3. "WDT_CASCADE0_1,Cascade Watchdog Counters 0 1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0." "0: Independent counters,1: Cascaded counters"
|
|
newline
|
|
bitfld.long 0xC 2. "WDT_CLEAR0,Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1)." "0: Free running counter,1: Clear on match"
|
|
bitfld.long 0xC 0.--1. "WDT_MODE0,Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0)." "0: Do nothing,1: Assert WDT_INTx,2: Assert WDT Reset,3: Assert WDT_INTx assert WDT Reset after 3rd.."
|
|
line.long 0x10 "MCWDT_CTL,Multi-Counter Watchdog Counter Control"
|
|
bitfld.long 0x10 19. "WDT_RESET2,Resets counter 2 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect." "0,1"
|
|
rbitfld.long 0x10 17. "WDT_ENABLED2,Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles." "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. "WDT_ENABLE2,Enable subcounter 2. May take up to 2 LFCLK cycles to take effect." "0: Counter is disabled,1: Counter is enabled"
|
|
bitfld.long 0x10 11. "WDT_RESET1,Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect." "0,1"
|
|
newline
|
|
rbitfld.long 0x10 9. "WDT_ENABLED1,Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles." "0,1"
|
|
bitfld.long 0x10 8. "WDT_ENABLE1,Enable subcounter 1. May take up to 2 LFCLK cycles to take effect." "0: Counter is disabled,1: Counter is enabled"
|
|
newline
|
|
bitfld.long 0x10 3. "WDT_RESET0,Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect." "0,1"
|
|
rbitfld.long 0x10 1. "WDT_ENABLED0,Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "WDT_ENABLE0,Enable subcounter 0. May take up to 2 LFCLK cycles to take effect." "0: Counter is disabled,1: Counter is enabled"
|
|
line.long 0x14 "MCWDT_INTR,Multi-Counter Watchdog Counter Interrupt Register"
|
|
bitfld.long 0x14 2. "MCWDT_INT2,MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3." "0,1"
|
|
bitfld.long 0x14 1. "MCWDT_INT1,MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "MCWDT_INT0,MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3." "0,1"
|
|
line.long 0x18 "MCWDT_INTR_SET,Multi-Counter Watchdog Counter Interrupt Set Register"
|
|
bitfld.long 0x18 2. "MCWDT_INT2,Set interrupt for MCWDT_INT2" "0,1"
|
|
bitfld.long 0x18 1. "MCWDT_INT1,Set interrupt for MCWDT_INT1" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "MCWDT_INT0,Set interrupt for MCWDT_INT0" "0,1"
|
|
line.long 0x1C "MCWDT_INTR_MASK,Multi-Counter Watchdog Counter Interrupt Mask Register"
|
|
bitfld.long 0x1C 2. "MCWDT_INT2,Interrupt Mask for sub-counter 2. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1." "0,1"
|
|
bitfld.long 0x1C 1. "MCWDT_INT1,Interrupt Mask for sub-counter 1. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "MCWDT_INT0,Interrupt Mask for sub-counter 0. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1." "0,1"
|
|
rgroup.long ($2+0x24)++0x3
|
|
line.long 0x0 "MCWDT_INTR_MASKED,Multi-Counter Watchdog Counter Interrupt Masked Register"
|
|
bitfld.long 0x0 2. "MCWDT_INT2,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 1. "MCWDT_INT1,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MCWDT_INT0,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long ($2+0x28)++0x3
|
|
line.long 0x0 "MCWDT_LOCK,Multi-Counter Watchdog Counter Lock Register"
|
|
bitfld.long 0x0 30.--31. "MCWDT_LOCK,Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock." "0: No effect,1: Clears bit 0,2: Clears bit 1,3: Sets both bits 0 and 1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40260000
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x300)++0x3
|
|
line.long 0x0 "CLK_DSI_SELECT[$1],Clock DSI Select Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DSI_MUX,Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It.."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x340)++0x3
|
|
line.long 0x0 "CLK_PATH_SELECT[$1],Clock Path Select Register"
|
|
bitfld.long 0x0 0.--2. "PATH_MUX,Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior." "0: IMO - Internal R/C Oscillator,1: EXTCLK - External Clock Pin,2: ECO - External-Crystal Oscillator,3: ALTHF - Alternate High-Frequency clock input..,4: DSI_MUX - Output of DSI mux for this path. Using..,?,?,?"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x380)++0x3
|
|
line.long 0x0 "CLK_ROOT_SELECT[$1],Clock Root Select Register"
|
|
bitfld.long 0x0 31. "ENABLE,Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0 which cannot be disabled." "0,1"
|
|
bitfld.long 0x0 4.--5. "ROOT_DIV,Selects predivider value for this clock root and DSI input." "0: Transparent mode feed through selected clock..,1: Divide selected clock source by 2,2: Divide selected clock source by 4,3: Divide selected clock source by 8"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "ROOT_MUX,Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific) and the control and bypass mux selections of these are.."
|
|
repeat.end
|
|
group.long 0x544++0x7
|
|
line.long 0x0 "CLK_MF_SELECT,Medium Frequency Clock Select Register"
|
|
bitfld.long 0x0 31. "ENABLE,Enable for MFCLK (clk_mf)." "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MFCLK_DIV,Divide selected clock source by (1+MFCLK_DIV). The output of this divider is MFCLK (clk_mf). Allows for integer divisions in the range [1 256]. Do not change this setting while ENABLE==1."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "MFCLK_SEL,Select source for MFCLK (clk_mf). Note that not all products support all clock sources. Selecting a clock source that is not supported results in undefined behavior." "0: MFO - medium frequency oscillator,?,?,?,?,?,?,?"
|
|
line.long 0x4 "CLK_MFO_CONFIG,MFO Configuration Register"
|
|
bitfld.long 0x4 31. "ENABLE,Enable for MFO." "0,1"
|
|
bitfld.long 0x4 30. "DPSLP_ENABLE,Enable for MFO during DEEPSLEEP. This bit is ignored when ENABLE==0. When ENABLE==1:" "0: MFO is automatically disabled during DEEPSLEEP..,1: MFO is kept enabled throughout DEEPSLEEP"
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x600)++0x3
|
|
line.long 0x0 "CLK_PLL_CONFIG[$1],PLL Configuration Register"
|
|
bitfld.long 0x0 31. "ENABLE,Master enable for PLL. Setup FEEDBACK_DIV REFERENCE_DIV and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL first deselect it using .BYPASS_SEL=PLL_REF wait at least six PLL clock cycles and then disable it with.." "0: Block is disabled,1: Block is enabled"
|
|
bitfld.long 0x0 28.--29. "BYPASS_SEL,Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running." "0: Automatic using lock indicator. When unlocked..,1: Same as AUTO,2: Select PLL reference input (bypass mode).,3: Select PLL output. Ignores lock indicator."
|
|
newline
|
|
bitfld.long 0x0 27. "PLL_LF_MODE,VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled." "0: VCO frequency is [200MHz,1: VCO frequency is [170MHz"
|
|
hexmask.long.byte 0x0 16.--20. 1. "OUTPUT_DIV,Control bits for Output divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "REFERENCE_DIV,Control bits for reference divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
hexmask.long.byte 0x0 0.--6. 1. "FEEDBACK_DIV,Control bits for feedback divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x640)++0x3
|
|
line.long 0x0 "CLK_PLL_STATUS[$1],PLL Status Register"
|
|
bitfld.long 0x0 1. "UNLOCK_OCCURRED,This bit sets whenever the PLL Lock bit goes low and stays set until cleared by firmware." "0,1"
|
|
rbitfld.long 0x0 0. "LOCKED,PLL Lock Indicator" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "PWR_HIB_DATA[$1],HIBERNATE Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "HIB_DATA,Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 2. (list 0x0 0x1)(list ad:0x40260200 ad:0x40260240)
|
|
tree "MCWDT_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2+0x4)++0x1F
|
|
line.long 0x0 "MCWDT_CNTLOW,Multi-Counter Watchdog Sub-counters 0/1"
|
|
hexmask.long.word 0x0 16.--31. 1. "WDT_CTR1,Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. "WDT_CTR0,Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled."
|
|
line.long 0x4 "MCWDT_CNTHIGH,Multi-Counter Watchdog Sub-counter 2"
|
|
hexmask.long 0x4 0.--31. 1. "WDT_CTR2,Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled"
|
|
line.long 0x8 "MCWDT_MATCH,Multi-Counter Watchdog Counter Match Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "WDT_MATCH1,Match value for sub-counter 1 of this MCWDT"
|
|
hexmask.long.word 0x8 0.--15. 1. "WDT_MATCH0,Match value for sub-counter 0 of this MCWDT"
|
|
line.long 0xC "MCWDT_CONFIG,Multi-Counter Watchdog Counter Configuration"
|
|
hexmask.long.byte 0xC 24.--28. 1. "WDT_BITS2,Bit to observe for WDT_INT2:"
|
|
bitfld.long 0xC 16. "WDT_MODE2,Watchdog Counter 2 Mode." "0: Free running counter with no interrupt requests,1: Free running counter with interrupt request that.."
|
|
newline
|
|
bitfld.long 0xC 11. "WDT_CASCADE1_2,Cascade Watchdog Counters 1 2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters." "0: Independent counters,1: Cascaded counters"
|
|
bitfld.long 0xC 10. "WDT_CLEAR1,Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1)." "0: Free running counter,1: Clear on match"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "WDT_MODE1,Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1)." "0: Do nothing,1: Assert WDT_INTx,2: Assert WDT Reset,3: Assert WDT_INTx assert WDT Reset after 3rd.."
|
|
bitfld.long 0xC 3. "WDT_CASCADE0_1,Cascade Watchdog Counters 0 1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0." "0: Independent counters,1: Cascaded counters"
|
|
newline
|
|
bitfld.long 0xC 2. "WDT_CLEAR0,Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1)." "0: Free running counter,1: Clear on match"
|
|
bitfld.long 0xC 0.--1. "WDT_MODE0,Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0)." "0: Do nothing,1: Assert WDT_INTx,2: Assert WDT Reset,3: Assert WDT_INTx assert WDT Reset after 3rd.."
|
|
line.long 0x10 "MCWDT_CTL,Multi-Counter Watchdog Counter Control"
|
|
bitfld.long 0x10 19. "WDT_RESET2,Resets counter 2 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect." "0,1"
|
|
rbitfld.long 0x10 17. "WDT_ENABLED2,Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles." "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. "WDT_ENABLE2,Enable subcounter 2. May take up to 2 LFCLK cycles to take effect." "0: Counter is disabled,1: Counter is enabled"
|
|
bitfld.long 0x10 11. "WDT_RESET1,Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect." "0,1"
|
|
newline
|
|
rbitfld.long 0x10 9. "WDT_ENABLED1,Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles." "0,1"
|
|
bitfld.long 0x10 8. "WDT_ENABLE1,Enable subcounter 1. May take up to 2 LFCLK cycles to take effect." "0: Counter is disabled,1: Counter is enabled"
|
|
newline
|
|
bitfld.long 0x10 3. "WDT_RESET0,Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect." "0,1"
|
|
rbitfld.long 0x10 1. "WDT_ENABLED0,Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "WDT_ENABLE0,Enable subcounter 0. May take up to 2 LFCLK cycles to take effect." "0: Counter is disabled,1: Counter is enabled"
|
|
line.long 0x14 "MCWDT_INTR,Multi-Counter Watchdog Counter Interrupt Register"
|
|
bitfld.long 0x14 2. "MCWDT_INT2,MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3." "0,1"
|
|
bitfld.long 0x14 1. "MCWDT_INT1,MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "MCWDT_INT0,MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3." "0,1"
|
|
line.long 0x18 "MCWDT_INTR_SET,Multi-Counter Watchdog Counter Interrupt Set Register"
|
|
bitfld.long 0x18 2. "MCWDT_INT2,Set interrupt for MCWDT_INT2" "0,1"
|
|
bitfld.long 0x18 1. "MCWDT_INT1,Set interrupt for MCWDT_INT1" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "MCWDT_INT0,Set interrupt for MCWDT_INT0" "0,1"
|
|
line.long 0x1C "MCWDT_INTR_MASK,Multi-Counter Watchdog Counter Interrupt Mask Register"
|
|
bitfld.long 0x1C 2. "MCWDT_INT2,Interrupt Mask for sub-counter 2. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1." "0,1"
|
|
bitfld.long 0x1C 1. "MCWDT_INT1,Interrupt Mask for sub-counter 1. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "MCWDT_INT0,Interrupt Mask for sub-counter 0. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1." "0,1"
|
|
rgroup.long ($2+0x24)++0x3
|
|
line.long 0x0 "MCWDT_INTR_MASKED,Multi-Counter Watchdog Counter Interrupt Masked Register"
|
|
bitfld.long 0x0 2. "MCWDT_INT2,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 1. "MCWDT_INT1,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MCWDT_INT0,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long ($2+0x28)++0x3
|
|
line.long 0x0 "MCWDT_LOCK,Multi-Counter Watchdog Counter Lock Register"
|
|
bitfld.long 0x0 30.--31. "MCWDT_LOCK,Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock." "0: No effect,1: Clears bit 0,2: Clears bit 1,3: Sets both bits 0 and 1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40260000
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x300)++0x3
|
|
line.long 0x0 "CLK_DSI_SELECT[$1],Clock DSI Select Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DSI_MUX,Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It.."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x340)++0x3
|
|
line.long 0x0 "CLK_PATH_SELECT[$1],Clock Path Select Register"
|
|
bitfld.long 0x0 0.--2. "PATH_MUX,Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior." "0: IMO - Internal R/C Oscillator,1: EXTCLK - External Clock Pin,2: ECO - External-Crystal Oscillator,3: ALTHF - Alternate High-Frequency clock input..,4: DSI_MUX - Output of DSI mux for this path. Using..,?,?,?"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x380)++0x3
|
|
line.long 0x0 "CLK_ROOT_SELECT[$1],Clock Root Select Register"
|
|
bitfld.long 0x0 31. "ENABLE,Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0 which cannot be disabled." "0,1"
|
|
bitfld.long 0x0 4.--5. "ROOT_DIV,Selects predivider value for this clock root and DSI input." "0: Transparent mode feed through selected clock..,1: Divide selected clock source by 2,2: Divide selected clock source by 4,3: Divide selected clock source by 8"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "ROOT_MUX,Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific) and the control and bypass mux selections of these are.."
|
|
repeat.end
|
|
group.long 0x544++0x7
|
|
line.long 0x0 "CLK_MF_SELECT,Medium Frequency Clock Select Register"
|
|
bitfld.long 0x0 31. "ENABLE,Enable for MFCLK (clk_mf)." "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MFCLK_DIV,Divide selected clock source by (1+MFCLK_DIV). The output of this divider is MFCLK (clk_mf). Allows for integer divisions in the range [1 256]. Do not change this setting while ENABLE==1."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "MFCLK_SEL,Select source for MFCLK (clk_mf). Note that not all products support all clock sources. Selecting a clock source that is not supported results in undefined behavior." "0: MFO - medium frequency oscillator,?,?,?,?,?,?,?"
|
|
line.long 0x4 "CLK_MFO_CONFIG,MFO Configuration Register"
|
|
bitfld.long 0x4 31. "ENABLE,Enable for MFO." "0,1"
|
|
bitfld.long 0x4 30. "DPSLP_ENABLE,Enable for MFO during DEEPSLEEP. This bit is ignored when ENABLE==0. When ENABLE==1:" "0: MFO is automatically disabled during DEEPSLEEP..,1: MFO is kept enabled throughout DEEPSLEEP"
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x600)++0x3
|
|
line.long 0x0 "CLK_PLL_CONFIG[$1],PLL Configuration Register"
|
|
bitfld.long 0x0 31. "ENABLE,Master enable for PLL. Setup FEEDBACK_DIV REFERENCE_DIV and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL first deselect it using .BYPASS_SEL=PLL_REF wait at least six PLL clock cycles and then disable it with.." "0: Block is disabled,1: Block is enabled"
|
|
bitfld.long 0x0 28.--29. "BYPASS_SEL,Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running." "0: Automatic using lock indicator. When unlocked..,1: Same as AUTO,2: Select PLL reference input (bypass mode).,3: Select PLL output. Ignores lock indicator."
|
|
newline
|
|
bitfld.long 0x0 27. "PLL_LF_MODE,VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled." "0: VCO frequency is [200MHz,1: VCO frequency is [170MHz"
|
|
hexmask.long.byte 0x0 16.--20. 1. "OUTPUT_DIV,Control bits for Output divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "REFERENCE_DIV,Control bits for reference divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
hexmask.long.byte 0x0 0.--6. 1. "FEEDBACK_DIV,Control bits for feedback divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x640)++0x3
|
|
line.long 0x0 "CLK_PLL_STATUS[$1],PLL Status Register"
|
|
bitfld.long 0x0 1. "UNLOCK_OCCURRED,This bit sets whenever the PLL Lock bit goes low and stays set until cleared by firmware." "0,1"
|
|
rbitfld.long 0x0 0. "LOCKED,PLL Lock Indicator" "0,1"
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
tree "TCPWM (Timer/Counter/PWM)"
|
|
base ad:0x0
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??6*")||cpuis("CYS06??7*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
tree "TCPWM0"
|
|
base ad:0x40380000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CTRL,TCPWM control register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER_ENABLED,Counter enables for counters 0 up to CNT_NR-1."
|
|
line.long 0x4 "CTRL_CLR,TCPWM control clear register"
|
|
hexmask.long 0x4 0.--31. 1. "COUNTER_ENABLED,Alias of CTRL that only allows disabling of counters. A write access:"
|
|
line.long 0x8 "CTRL_SET,TCPWM control set register"
|
|
hexmask.long 0x8 0.--31. 1. "COUNTER_ENABLED,Alias of CTRL that only allows enabling of counters. A write access:"
|
|
line.long 0xC "CMD_CAPTURE,TCPWM capture command register"
|
|
hexmask.long 0xC 0.--31. 1. "COUNTER_CAPTURE,Counters SW capture trigger. When written with '1' a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is.."
|
|
line.long 0x10 "CMD_RELOAD,TCPWM reload command register"
|
|
hexmask.long 0x10 0.--31. 1. "COUNTER_RELOAD,Counters SW reload trigger. For HW behavior see COUNTER_CAPTURE field."
|
|
line.long 0x14 "CMD_STOP,TCPWM stop command register"
|
|
hexmask.long 0x14 0.--31. 1. "COUNTER_STOP,Counters SW stop trigger. For HW behavior see COUNTER_CAPTURE field."
|
|
line.long 0x18 "CMD_START,TCPWM start command register"
|
|
hexmask.long 0x18 0.--31. 1. "COUNTER_START,Counters SW start trigger. For HW behavior see COUNTER_CAPTURE field."
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "INTR_CAUSE,TCPWM Counter interrupt cause register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER_INT,Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED the associated interrupt field is immediately set to '0'."
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40380100 ad:0x40380140 ad:0x40380180 ad:0x403801C0 ad:0x40380200 ad:0x40380240 ad:0x40380280 ad:0x403802C0 ad:0x40380300 ad:0x40380340 ad:0x40380380 ad:0x403803C0 ad:0x40380400 ad:0x40380440 ad:0x40380480 ad:0x403804C0)
|
|
tree "CNT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTRL,Counter control register"
|
|
bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,?,2: Capture mode,3: Quadrature encoding mode,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,?"
|
|
bitfld.long 0x0 20.--21. "QUADRATURE_MODE,In QUAD mode selects quadrature encoding mode (X1/X2/X4)." "0: X1 encoding (QUAD mode),1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),?"
|
|
newline
|
|
bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
|
|
bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit control field. In PWM_DT mode this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes the lower 3 bits of this field determine pre-scaling of the selected counter.."
|
|
bitfld.long 0x0 3. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0: kill event does NOT stop counter,1: kill event stops counter"
|
|
newline
|
|
bitfld.long 0x0 2. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0: asynchronous kill mode: the kill event only..,1: synchronous kill mode: the kill event disables.."
|
|
bitfld.long 0x0 1. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with and.."
|
|
newline
|
|
bitfld.long 0x0 0. "AUTO_RELOAD_CC,Specifies switching of the CC and buffered CC values. This field has a function in TIMER PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with an.."
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "STATUS,Counter status register"
|
|
bitfld.long 0x0 31. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion. In all other modes this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality."
|
|
newline
|
|
bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "COUNTER,Counter count register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
|
|
line.long 0x4 "CC,Counter compare/capture register"
|
|
hexmask.long 0x4 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
|
|
line.long 0x8 "CC_BUFF,Counter buffered compare/capture register"
|
|
hexmask.long 0x8 0.--31. 1. "CC,Additional buffer for counter CC register."
|
|
line.long 0xC "PERIOD,Counter period register"
|
|
hexmask.long 0xC 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
|
|
line.long 0x10 "PERIOD_BUFF,Counter buffered period register"
|
|
hexmask.long 0x10 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "TR_CTRL0,Counter trigger control register 0"
|
|
hexmask.long.byte 0x0 16.--19. 1. "START_SEL,Selects one of the 16 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
|
|
hexmask.long.byte 0x0 12.--15. 1. "STOP_SEL,Selects one of the 16 input triggers as a stop trigger. In PWM PWM_DT and PWM_PR modes this is the kill trigger. In these modes the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "RELOAD_SEL,Selects one of the 16 input triggers as a reload trigger. In QUAD mode this is the index or revolution pulse. In this mode it will update the counter with 0x8000 (counter midpoint)."
|
|
hexmask.long.byte 0x0 4.--7. 1. "COUNT_SEL,Selects one of the 16 input triggers as a count trigger. In QUAD mode this is the first phase (phi A). Default setting selects input trigger 1 which is always '1'."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CAPTURE_SEL,Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with.."
|
|
line.long 0x4 "TR_CTRL1,Counter trigger control register 1"
|
|
bitfld.long 0x4 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
bitfld.long 0x4 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
newline
|
|
bitfld.long 0x4 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
bitfld.long 0x4 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
newline
|
|
bitfld.long 0x4 0.--1. "CAPTURE_EDGE,A capture event will copy the counter value into the CC register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
line.long 0x8 "TR_CTRL2,Counter trigger control register 2"
|
|
bitfld.long 0x8 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
bitfld.long 0x8 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "CC_MATCH_MODE,Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
group.long ($2+0x30)++0xB
|
|
line.long 0x0 "INTR,Interrupt request register"
|
|
bitfld.long 0x0 1. "CC_MATCH,Counter matches CC register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x4 1. "CC_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 1. "CC_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 1. "CC_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 8. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17)(list ad:0x40380500 ad:0x40380540 ad:0x40380580 ad:0x403805C0 ad:0x40380600 ad:0x40380640 ad:0x40380680 ad:0x403806C0)
|
|
tree "CNT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTRL,Counter control register"
|
|
bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,?,2: Capture mode,3: Quadrature encoding mode,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,?"
|
|
bitfld.long 0x0 20.--21. "QUADRATURE_MODE,In QUAD mode selects quadrature encoding mode (X1/X2/X4)." "0: X1 encoding (QUAD mode),1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),?"
|
|
newline
|
|
bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
|
|
bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit control field. In PWM_DT mode this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes the lower 3 bits of this field determine pre-scaling of the selected counter.."
|
|
bitfld.long 0x0 3. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0: kill event does NOT stop counter,1: kill event stops counter"
|
|
newline
|
|
bitfld.long 0x0 2. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0: asynchronous kill mode: the kill event only..,1: synchronous kill mode: the kill event disables.."
|
|
bitfld.long 0x0 1. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with and.."
|
|
newline
|
|
bitfld.long 0x0 0. "AUTO_RELOAD_CC,Specifies switching of the CC and buffered CC values. This field has a function in TIMER PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with an.."
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "STATUS,Counter status register"
|
|
bitfld.long 0x0 31. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion. In all other modes this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality."
|
|
newline
|
|
bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "COUNTER,Counter count register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
|
|
line.long 0x4 "CC,Counter compare/capture register"
|
|
hexmask.long 0x4 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
|
|
line.long 0x8 "CC_BUFF,Counter buffered compare/capture register"
|
|
hexmask.long 0x8 0.--31. 1. "CC,Additional buffer for counter CC register."
|
|
line.long 0xC "PERIOD,Counter period register"
|
|
hexmask.long 0xC 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
|
|
line.long 0x10 "PERIOD_BUFF,Counter buffered period register"
|
|
hexmask.long 0x10 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "TR_CTRL0,Counter trigger control register 0"
|
|
hexmask.long.byte 0x0 16.--19. 1. "START_SEL,Selects one of the 16 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
|
|
hexmask.long.byte 0x0 12.--15. 1. "STOP_SEL,Selects one of the 16 input triggers as a stop trigger. In PWM PWM_DT and PWM_PR modes this is the kill trigger. In these modes the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "RELOAD_SEL,Selects one of the 16 input triggers as a reload trigger. In QUAD mode this is the index or revolution pulse. In this mode it will update the counter with 0x8000 (counter midpoint)."
|
|
hexmask.long.byte 0x0 4.--7. 1. "COUNT_SEL,Selects one of the 16 input triggers as a count trigger. In QUAD mode this is the first phase (phi A). Default setting selects input trigger 1 which is always '1'."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CAPTURE_SEL,Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with.."
|
|
line.long 0x4 "TR_CTRL1,Counter trigger control register 1"
|
|
bitfld.long 0x4 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
bitfld.long 0x4 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
newline
|
|
bitfld.long 0x4 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
bitfld.long 0x4 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
newline
|
|
bitfld.long 0x4 0.--1. "CAPTURE_EDGE,A capture event will copy the counter value into the CC register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
line.long 0x8 "TR_CTRL2,Counter trigger control register 2"
|
|
bitfld.long 0x8 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
bitfld.long 0x8 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "CC_MATCH_MODE,Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
group.long ($2+0x30)++0xB
|
|
line.long 0x0 "INTR,Interrupt request register"
|
|
bitfld.long 0x0 1. "CC_MATCH,Counter matches CC register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x4 1. "CC_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 1. "CC_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 1. "CC_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??6*")||cpuis("CYS06??7*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
tree "TCPWM1"
|
|
base ad:0x40390000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CTRL,TCPWM control register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER_ENABLED,Counter enables for counters 0 up to CNT_NR-1."
|
|
line.long 0x4 "CTRL_CLR,TCPWM control clear register"
|
|
hexmask.long 0x4 0.--31. 1. "COUNTER_ENABLED,Alias of CTRL that only allows disabling of counters. A write access:"
|
|
line.long 0x8 "CTRL_SET,TCPWM control set register"
|
|
hexmask.long 0x8 0.--31. 1. "COUNTER_ENABLED,Alias of CTRL that only allows enabling of counters. A write access:"
|
|
line.long 0xC "CMD_CAPTURE,TCPWM capture command register"
|
|
hexmask.long 0xC 0.--31. 1. "COUNTER_CAPTURE,Counters SW capture trigger. When written with '1' a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is.."
|
|
line.long 0x10 "CMD_RELOAD,TCPWM reload command register"
|
|
hexmask.long 0x10 0.--31. 1. "COUNTER_RELOAD,Counters SW reload trigger. For HW behavior see COUNTER_CAPTURE field."
|
|
line.long 0x14 "CMD_STOP,TCPWM stop command register"
|
|
hexmask.long 0x14 0.--31. 1. "COUNTER_STOP,Counters SW stop trigger. For HW behavior see COUNTER_CAPTURE field."
|
|
line.long 0x18 "CMD_START,TCPWM start command register"
|
|
hexmask.long 0x18 0.--31. 1. "COUNTER_START,Counters SW start trigger. For HW behavior see COUNTER_CAPTURE field."
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "INTR_CAUSE,TCPWM Counter interrupt cause register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER_INT,Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED the associated interrupt field is immediately set to '0'."
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40390100 ad:0x40390140 ad:0x40390180 ad:0x403901C0 ad:0x40390200 ad:0x40390240 ad:0x40390280 ad:0x403902C0 ad:0x40390300 ad:0x40390340 ad:0x40390380 ad:0x403903C0 ad:0x40390400 ad:0x40390440 ad:0x40390480 ad:0x403904C0)
|
|
tree "CNT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTRL,Counter control register"
|
|
bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,?,2: Capture mode,3: Quadrature encoding mode,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,?"
|
|
bitfld.long 0x0 20.--21. "QUADRATURE_MODE,In QUAD mode selects quadrature encoding mode (X1/X2/X4)." "0: X1 encoding (QUAD mode),1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),?"
|
|
newline
|
|
bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
|
|
bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit control field. In PWM_DT mode this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes the lower 3 bits of this field determine pre-scaling of the selected counter.."
|
|
bitfld.long 0x0 3. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0: kill event does NOT stop counter,1: kill event stops counter"
|
|
newline
|
|
bitfld.long 0x0 2. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0: asynchronous kill mode: the kill event only..,1: synchronous kill mode: the kill event disables.."
|
|
bitfld.long 0x0 1. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with and.."
|
|
newline
|
|
bitfld.long 0x0 0. "AUTO_RELOAD_CC,Specifies switching of the CC and buffered CC values. This field has a function in TIMER PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with an.."
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "STATUS,Counter status register"
|
|
bitfld.long 0x0 31. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion. In all other modes this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality."
|
|
newline
|
|
bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "COUNTER,Counter count register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
|
|
line.long 0x4 "CC,Counter compare/capture register"
|
|
hexmask.long 0x4 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
|
|
line.long 0x8 "CC_BUFF,Counter buffered compare/capture register"
|
|
hexmask.long 0x8 0.--31. 1. "CC,Additional buffer for counter CC register."
|
|
line.long 0xC "PERIOD,Counter period register"
|
|
hexmask.long 0xC 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
|
|
line.long 0x10 "PERIOD_BUFF,Counter buffered period register"
|
|
hexmask.long 0x10 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "TR_CTRL0,Counter trigger control register 0"
|
|
hexmask.long.byte 0x0 16.--19. 1. "START_SEL,Selects one of the 16 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
|
|
hexmask.long.byte 0x0 12.--15. 1. "STOP_SEL,Selects one of the 16 input triggers as a stop trigger. In PWM PWM_DT and PWM_PR modes this is the kill trigger. In these modes the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "RELOAD_SEL,Selects one of the 16 input triggers as a reload trigger. In QUAD mode this is the index or revolution pulse. In this mode it will update the counter with 0x8000 (counter midpoint)."
|
|
hexmask.long.byte 0x0 4.--7. 1. "COUNT_SEL,Selects one of the 16 input triggers as a count trigger. In QUAD mode this is the first phase (phi A). Default setting selects input trigger 1 which is always '1'."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CAPTURE_SEL,Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with.."
|
|
line.long 0x4 "TR_CTRL1,Counter trigger control register 1"
|
|
bitfld.long 0x4 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
bitfld.long 0x4 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
newline
|
|
bitfld.long 0x4 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
bitfld.long 0x4 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
newline
|
|
bitfld.long 0x4 0.--1. "CAPTURE_EDGE,A capture event will copy the counter value into the CC register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
line.long 0x8 "TR_CTRL2,Counter trigger control register 2"
|
|
bitfld.long 0x8 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
bitfld.long 0x8 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "CC_MATCH_MODE,Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
group.long ($2+0x30)++0xB
|
|
line.long 0x0 "INTR,Interrupt request register"
|
|
bitfld.long 0x0 1. "CC_MATCH,Counter matches CC register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x4 1. "CC_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 1. "CC_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 1. "CC_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 8. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17)(list ad:0x40390500 ad:0x40390540 ad:0x40390580 ad:0x403905C0 ad:0x40390600 ad:0x40390640 ad:0x40390680 ad:0x403906C0)
|
|
tree "CNT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTRL,Counter control register"
|
|
bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,?,2: Capture mode,3: Quadrature encoding mode,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,?"
|
|
bitfld.long 0x0 20.--21. "QUADRATURE_MODE,In QUAD mode selects quadrature encoding mode (X1/X2/X4)." "0: X1 encoding (QUAD mode),1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),?"
|
|
newline
|
|
bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
|
|
bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit control field. In PWM_DT mode this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes the lower 3 bits of this field determine pre-scaling of the selected counter.."
|
|
bitfld.long 0x0 3. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0: kill event does NOT stop counter,1: kill event stops counter"
|
|
newline
|
|
bitfld.long 0x0 2. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0: asynchronous kill mode: the kill event only..,1: synchronous kill mode: the kill event disables.."
|
|
bitfld.long 0x0 1. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with and.."
|
|
newline
|
|
bitfld.long 0x0 0. "AUTO_RELOAD_CC,Specifies switching of the CC and buffered CC values. This field has a function in TIMER PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with an.."
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "STATUS,Counter status register"
|
|
bitfld.long 0x0 31. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion. In all other modes this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality."
|
|
newline
|
|
bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "COUNTER,Counter count register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
|
|
line.long 0x4 "CC,Counter compare/capture register"
|
|
hexmask.long 0x4 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
|
|
line.long 0x8 "CC_BUFF,Counter buffered compare/capture register"
|
|
hexmask.long 0x8 0.--31. 1. "CC,Additional buffer for counter CC register."
|
|
line.long 0xC "PERIOD,Counter period register"
|
|
hexmask.long 0xC 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
|
|
line.long 0x10 "PERIOD_BUFF,Counter buffered period register"
|
|
hexmask.long 0x10 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "TR_CTRL0,Counter trigger control register 0"
|
|
hexmask.long.byte 0x0 16.--19. 1. "START_SEL,Selects one of the 16 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
|
|
hexmask.long.byte 0x0 12.--15. 1. "STOP_SEL,Selects one of the 16 input triggers as a stop trigger. In PWM PWM_DT and PWM_PR modes this is the kill trigger. In these modes the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "RELOAD_SEL,Selects one of the 16 input triggers as a reload trigger. In QUAD mode this is the index or revolution pulse. In this mode it will update the counter with 0x8000 (counter midpoint)."
|
|
hexmask.long.byte 0x0 4.--7. 1. "COUNT_SEL,Selects one of the 16 input triggers as a count trigger. In QUAD mode this is the first phase (phi A). Default setting selects input trigger 1 which is always '1'."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CAPTURE_SEL,Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with.."
|
|
line.long 0x4 "TR_CTRL1,Counter trigger control register 1"
|
|
bitfld.long 0x4 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
bitfld.long 0x4 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
newline
|
|
bitfld.long 0x4 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
bitfld.long 0x4 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
newline
|
|
bitfld.long 0x4 0.--1. "CAPTURE_EDGE,A capture event will copy the counter value into the CC register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
line.long 0x8 "TR_CTRL2,Counter trigger control register 2"
|
|
bitfld.long 0x8 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
bitfld.long 0x8 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "CC_MATCH_MODE,Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
group.long ($2+0x30)++0xB
|
|
line.long 0x0 "INTR,Interrupt request register"
|
|
bitfld.long 0x0 1. "CC_MATCH,Counter matches CC register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x4 1. "CC_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 1. "CC_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 1. "CC_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
tree "TCPWM0"
|
|
base ad:0x40380000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CTRL,TCPWM control register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER_ENABLED,Counter enables for counters 0 up to CNT_NR-1."
|
|
line.long 0x4 "CTRL_CLR,TCPWM control clear register"
|
|
hexmask.long 0x4 0.--31. 1. "COUNTER_ENABLED,Alias of CTRL that only allows disabling of counters. A write access:"
|
|
line.long 0x8 "CTRL_SET,TCPWM control set register"
|
|
hexmask.long 0x8 0.--31. 1. "COUNTER_ENABLED,Alias of CTRL that only allows enabling of counters. A write access:"
|
|
line.long 0xC "CMD_CAPTURE,TCPWM capture command register"
|
|
hexmask.long 0xC 0.--31. 1. "COUNTER_CAPTURE,Counters SW capture trigger. When written with '1' a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is.."
|
|
line.long 0x10 "CMD_RELOAD,TCPWM reload command register"
|
|
hexmask.long 0x10 0.--31. 1. "COUNTER_RELOAD,Counters SW reload trigger. For HW behavior see COUNTER_CAPTURE field."
|
|
line.long 0x14 "CMD_STOP,TCPWM stop command register"
|
|
hexmask.long 0x14 0.--31. 1. "COUNTER_STOP,Counters SW stop trigger. For HW behavior see COUNTER_CAPTURE field."
|
|
line.long 0x18 "CMD_START,TCPWM start command register"
|
|
hexmask.long 0x18 0.--31. 1. "COUNTER_START,Counters SW start trigger. For HW behavior see COUNTER_CAPTURE field."
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "INTR_CAUSE,TCPWM Counter interrupt cause register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER_INT,Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED the associated interrupt field is immediately set to '0'."
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40380100 ad:0x40380140 ad:0x40380180 ad:0x403801C0 ad:0x40380200 ad:0x40380240 ad:0x40380280 ad:0x403802C0)
|
|
tree "CNT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTRL,Counter control register"
|
|
bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,?,2: Capture mode,3: Quadrature encoding mode,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,?"
|
|
bitfld.long 0x0 20.--21. "QUADRATURE_MODE,In QUAD mode selects quadrature encoding mode (X1/X2/X4)." "0: X1 encoding (QUAD mode),1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),?"
|
|
newline
|
|
bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
|
|
bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit control field. In PWM_DT mode this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes the lower 3 bits of this field determine pre-scaling of the selected counter.."
|
|
bitfld.long 0x0 3. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0: kill event does NOT stop counter,1: kill event stops counter"
|
|
newline
|
|
bitfld.long 0x0 2. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0: asynchronous kill mode: the kill event only..,1: synchronous kill mode: the kill event disables.."
|
|
bitfld.long 0x0 1. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with and.."
|
|
newline
|
|
bitfld.long 0x0 0. "AUTO_RELOAD_CC,Specifies switching of the CC and buffered CC values. This field has a function in TIMER PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with an.."
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "STATUS,Counter status register"
|
|
bitfld.long 0x0 31. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion. In all other modes this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality."
|
|
newline
|
|
bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "COUNTER,Counter count register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
|
|
line.long 0x4 "CC,Counter compare/capture register"
|
|
hexmask.long 0x4 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
|
|
line.long 0x8 "CC_BUFF,Counter buffered compare/capture register"
|
|
hexmask.long 0x8 0.--31. 1. "CC,Additional buffer for counter CC register."
|
|
line.long 0xC "PERIOD,Counter period register"
|
|
hexmask.long 0xC 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
|
|
line.long 0x10 "PERIOD_BUFF,Counter buffered period register"
|
|
hexmask.long 0x10 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "TR_CTRL0,Counter trigger control register 0"
|
|
hexmask.long.byte 0x0 16.--19. 1. "START_SEL,Selects one of the 16 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
|
|
hexmask.long.byte 0x0 12.--15. 1. "STOP_SEL,Selects one of the 16 input triggers as a stop trigger. In PWM PWM_DT and PWM_PR modes this is the kill trigger. In these modes the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "RELOAD_SEL,Selects one of the 16 input triggers as a reload trigger. In QUAD mode this is the index or revolution pulse. In this mode it will update the counter with 0x8000 (counter midpoint)."
|
|
hexmask.long.byte 0x0 4.--7. 1. "COUNT_SEL,Selects one of the 16 input triggers as a count trigger. In QUAD mode this is the first phase (phi A). Default setting selects input trigger 1 which is always '1'."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CAPTURE_SEL,Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with.."
|
|
line.long 0x4 "TR_CTRL1,Counter trigger control register 1"
|
|
bitfld.long 0x4 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
bitfld.long 0x4 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
newline
|
|
bitfld.long 0x4 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
bitfld.long 0x4 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
newline
|
|
bitfld.long 0x4 0.--1. "CAPTURE_EDGE,A capture event will copy the counter value into the CC register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
line.long 0x8 "TR_CTRL2,Counter trigger control register 2"
|
|
bitfld.long 0x8 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
bitfld.long 0x8 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "CC_MATCH_MODE,Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
group.long ($2+0x30)++0xB
|
|
line.long 0x0 "INTR,Interrupt request register"
|
|
bitfld.long 0x0 1. "CC_MATCH,Counter matches CC register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x4 1. "CC_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 1. "CC_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 1. "CC_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
tree "TCPWM1"
|
|
base ad:0x40390000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CTRL,TCPWM control register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER_ENABLED,Counter enables for counters 0 up to CNT_NR-1."
|
|
line.long 0x4 "CTRL_CLR,TCPWM control clear register"
|
|
hexmask.long 0x4 0.--31. 1. "COUNTER_ENABLED,Alias of CTRL that only allows disabling of counters. A write access:"
|
|
line.long 0x8 "CTRL_SET,TCPWM control set register"
|
|
hexmask.long 0x8 0.--31. 1. "COUNTER_ENABLED,Alias of CTRL that only allows enabling of counters. A write access:"
|
|
line.long 0xC "CMD_CAPTURE,TCPWM capture command register"
|
|
hexmask.long 0xC 0.--31. 1. "COUNTER_CAPTURE,Counters SW capture trigger. When written with '1' a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is.."
|
|
line.long 0x10 "CMD_RELOAD,TCPWM reload command register"
|
|
hexmask.long 0x10 0.--31. 1. "COUNTER_RELOAD,Counters SW reload trigger. For HW behavior see COUNTER_CAPTURE field."
|
|
line.long 0x14 "CMD_STOP,TCPWM stop command register"
|
|
hexmask.long 0x14 0.--31. 1. "COUNTER_STOP,Counters SW stop trigger. For HW behavior see COUNTER_CAPTURE field."
|
|
line.long 0x18 "CMD_START,TCPWM start command register"
|
|
hexmask.long 0x18 0.--31. 1. "COUNTER_START,Counters SW start trigger. For HW behavior see COUNTER_CAPTURE field."
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "INTR_CAUSE,TCPWM Counter interrupt cause register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER_INT,Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED the associated interrupt field is immediately set to '0'."
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40390100 ad:0x40390140 ad:0x40390180 ad:0x403901C0 ad:0x40390200 ad:0x40390240 ad:0x40390280 ad:0x403902C0)
|
|
tree "CNT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTRL,Counter control register"
|
|
bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,?,2: Capture mode,3: Quadrature encoding mode,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,?"
|
|
bitfld.long 0x0 20.--21. "QUADRATURE_MODE,In QUAD mode selects quadrature encoding mode (X1/X2/X4)." "0: X1 encoding (QUAD mode),1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),?"
|
|
newline
|
|
bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
|
|
bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit control field. In PWM_DT mode this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes the lower 3 bits of this field determine pre-scaling of the selected counter.."
|
|
bitfld.long 0x0 3. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0: kill event does NOT stop counter,1: kill event stops counter"
|
|
newline
|
|
bitfld.long 0x0 2. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0: asynchronous kill mode: the kill event only..,1: synchronous kill mode: the kill event disables.."
|
|
bitfld.long 0x0 1. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with and.."
|
|
newline
|
|
bitfld.long 0x0 0. "AUTO_RELOAD_CC,Specifies switching of the CC and buffered CC values. This field has a function in TIMER PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with an.."
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "STATUS,Counter status register"
|
|
bitfld.long 0x0 31. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion. In all other modes this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality."
|
|
newline
|
|
bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "COUNTER,Counter count register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
|
|
line.long 0x4 "CC,Counter compare/capture register"
|
|
hexmask.long 0x4 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
|
|
line.long 0x8 "CC_BUFF,Counter buffered compare/capture register"
|
|
hexmask.long 0x8 0.--31. 1. "CC,Additional buffer for counter CC register."
|
|
line.long 0xC "PERIOD,Counter period register"
|
|
hexmask.long 0xC 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
|
|
line.long 0x10 "PERIOD_BUFF,Counter buffered period register"
|
|
hexmask.long 0x10 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "TR_CTRL0,Counter trigger control register 0"
|
|
hexmask.long.byte 0x0 16.--19. 1. "START_SEL,Selects one of the 16 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
|
|
hexmask.long.byte 0x0 12.--15. 1. "STOP_SEL,Selects one of the 16 input triggers as a stop trigger. In PWM PWM_DT and PWM_PR modes this is the kill trigger. In these modes the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "RELOAD_SEL,Selects one of the 16 input triggers as a reload trigger. In QUAD mode this is the index or revolution pulse. In this mode it will update the counter with 0x8000 (counter midpoint)."
|
|
hexmask.long.byte 0x0 4.--7. 1. "COUNT_SEL,Selects one of the 16 input triggers as a count trigger. In QUAD mode this is the first phase (phi A). Default setting selects input trigger 1 which is always '1'."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CAPTURE_SEL,Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with.."
|
|
line.long 0x4 "TR_CTRL1,Counter trigger control register 1"
|
|
bitfld.long 0x4 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
bitfld.long 0x4 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
newline
|
|
bitfld.long 0x4 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
bitfld.long 0x4 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
newline
|
|
bitfld.long 0x4 0.--1. "CAPTURE_EDGE,A capture event will copy the counter value into the CC register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
line.long 0x8 "TR_CTRL2,Counter trigger control register 2"
|
|
bitfld.long 0x8 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
bitfld.long 0x8 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "CC_MATCH_MODE,Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
group.long ($2+0x30)++0xB
|
|
line.long 0x0 "INTR,Interrupt request register"
|
|
bitfld.long 0x0 1. "CC_MATCH,Counter matches CC register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x4 1. "CC_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 1. "CC_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 1. "CC_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
tree "TCPWM0"
|
|
base ad:0x40380000
|
|
repeat 2. (list 0x0 0x1)(list ad:0x40380000 ad:0x40388000)
|
|
tree "GRP[$1]"
|
|
base $2
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x80 0x100 0x180 0x200 0x280 0x300 0x380)
|
|
tree "CNT[$1]"
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTRL,Counter control register"
|
|
bitfld.long 0x0 31. "ENABLED,Counter enable." "0: counter disabled,1: counter enabled"
|
|
newline
|
|
bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0: The counter operation continues in debug mode,1: The counter operation freezes in debug mode"
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|
newline
|
|
bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode."
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|
newline
|
|
bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
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|
newline
|
|
bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
|
|
newline
|
|
bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0: asynchronous kill mode: the kill event only..,1: synchronous kill mode: the kill event disables.."
|
|
newline
|
|
bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0: kill event does NOT stop counter,1: kill event stops counter"
|
|
newline
|
|
bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0: synchronous kill activation,1: immediate kill activation"
|
|
newline
|
|
bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0: compare match 1 event generation disabled when..,1: compare match 1 event generation enabled when.."
|
|
newline
|
|
bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0: compare match 1 event generation disabled when..,1: compare match 1 event generation enabled when.."
|
|
newline
|
|
bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0: compare match 0 event generation disabled when..,1: compare match 0 event generation enabled when.."
|
|
newline
|
|
bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0: compare match 0 event generation disabled when..,1: compare match 0 event generation enabled when.."
|
|
newline
|
|
bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0: never switch,1: switch on a terminal count event with and.."
|
|
newline
|
|
bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0: Captures on index,1: Captures when COUNTER equals 0 or 0xffff"
|
|
newline
|
|
bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with an.."
|
|
newline
|
|
bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with an.."
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
|
|
newline
|
|
bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "COUNTER,Counter count register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
|
|
group.long ($2+0x10)++0x23
|
|
line.long 0x0 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
|
|
line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register."
|
|
line.long 0x8 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
|
|
line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register."
|
|
line.long 0x10 "PERIOD,Counter period register"
|
|
hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
|
|
line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
|
|
hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
|
|
line.long 0x18 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
|
|
newline
|
|
bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
|
|
line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
|
|
newline
|
|
hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
|
|
newline
|
|
hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
|
|
group.long ($2+0x40)++0x17
|
|
line.long 0x0 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
|
|
line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
|
|
line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
|
|
line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
newline
|
|
bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
newline
|
|
bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
newline
|
|
bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
newline
|
|
bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
newline
|
|
bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
|
|
line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
|
|
bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
newline
|
|
bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
newline
|
|
bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
newline
|
|
bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
|
|
newline
|
|
bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
|
|
group.long ($2+0x70)++0xB
|
|
line.long 0x0 "INTR,Interrupt request register"
|
|
bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long ($2+0x7C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "USBFS (USB Host and Device Controller)"
|
|
base ad:0x403F0000
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??6*")||cpuis("CYS06??7*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
tree "USBDEV (USB Device)"
|
|
base ad:0x403F0000
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "CR0,USB control 0 Register"
|
|
bitfld.long 0x0 7. "USB_ENABLE,This bit enables the device to respond to USB traffic." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "DEVICE_ADDRESS,These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware.."
|
|
line.long 0x4 "CR1,USB control 1 Register"
|
|
bitfld.long 0x4 3. "RSVD_3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUS_ACTIVITY,The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ENABLE_LOCK,This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "REG_ENABLE,This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to.." "0,1"
|
|
line.long 0x8 "SIE_EP_INT_EN,USB SIE Data Endpoints Interrupt Enable Register"
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bitfld.long 0x8 7. "EP8_INTR_EN,Enables interrupt for EP8" "0,1"
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newline
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bitfld.long 0x8 6. "EP7_INTR_EN,Enables interrupt for EP7" "0,1"
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newline
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bitfld.long 0x8 5. "EP6_INTR_EN,Enables interrupt for EP6" "0,1"
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bitfld.long 0x8 4. "EP5_INTR_EN,Enables interrupt for EP5" "0,1"
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bitfld.long 0x8 3. "EP4_INTR_EN,Enables interrupt for EP4" "0,1"
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newline
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bitfld.long 0x8 2. "EP3_INTR_EN,Enables interrupt for EP3" "0,1"
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bitfld.long 0x8 1. "EP2_INTR_EN,Enables interrupt for EP2" "0,1"
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bitfld.long 0x8 0. "EP1_INTR_EN,Enables interrupt for EP1" "0,1"
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line.long 0xC "SIE_EP_INT_SR,USB SIE Data Endpoint Interrupt Status"
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bitfld.long 0xC 7. "EP8_INTR,Interrupt status for EP8" "0,1"
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newline
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bitfld.long 0xC 6. "EP7_INTR,Interrupt status for EP7" "0,1"
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newline
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bitfld.long 0xC 5. "EP6_INTR,Interrupt status for EP6" "0,1"
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bitfld.long 0xC 4. "EP5_INTR,Interrupt status for EP5" "0,1"
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bitfld.long 0xC 3. "EP4_INTR,Interrupt status for EP4" "0,1"
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newline
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bitfld.long 0xC 2. "EP3_INTR,Interrupt status for EP3" "0,1"
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bitfld.long 0xC 1. "EP2_INTR,Interrupt status for EP2" "0,1"
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newline
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bitfld.long 0xC 0. "EP1_INTR,Interrupt status for EP1" "0,1"
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line.long 0x10 "SIE_EP1_CNT0,Non-control endpoint count register"
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bitfld.long 0x10 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
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newline
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bitfld.long 0x10 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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newline
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bitfld.long 0x10 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
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line.long 0x14 "SIE_EP1_CNT1,Non-control endpoint count register"
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hexmask.long.byte 0x14 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
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line.long 0x18 "SIE_EP1_CR0,Non-control endpoint's control Register"
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bitfld.long 0x18 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
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bitfld.long 0x18 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
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bitfld.long 0x18 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
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newline
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bitfld.long 0x18 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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hexmask.long.byte 0x18 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
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group.long 0x40++0xB
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line.long 0x0 "USBIO_CR0,USBIO Control 0 Register"
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bitfld.long 0x0 7. "TEN,USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually" "0,1"
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bitfld.long 0x0 6. "TSE0,Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0." "0,1"
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bitfld.long 0x0 5. "TD,Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1." "0: Force USB K state (D+ is low D- is high).,1: Force USB J state (D+ is high D- is low)."
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rbitfld.long 0x0 0. "RD,Received Data. This read only bit gives the state of the USB differential receiver when IOMODE bit is '0' and USB doesn't transmit. This bit is valid if USB Device." "0: D+ < D- (K state),1: D+ > D- (J state)"
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line.long 0x4 "USBIO_CR2,USBIO control 2 Register"
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bitfld.long 0x4 7. "RSVD_7,N/A" "0,1"
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newline
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bitfld.long 0x4 6. "TEST_PKT,This bit enables the device to transmit a packet in response to an internally generated IN packet. When set one packet will be generated." "0,1"
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hexmask.long.byte 0x4 0.--5. 1. "RSVD_5_0,N/A"
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line.long 0x8 "USBIO_CR1,USBIO control 1 Register"
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bitfld.long 0x8 5. "IOMODE,This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins." "0,1"
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bitfld.long 0x8 2. "RSVD_2,N/A" "0,1"
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rbitfld.long 0x8 1. "DPO,This read only bit gives the state of the D+ pin when IOMODE bit is '0' and USB doesn't transmit." "0,1"
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newline
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rbitfld.long 0x8 0. "DMO,This read only bit gives the state of the D- pin when IOMODE bit is '0' and USB doesn't transmit." "0,1"
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group.long 0x50++0x3
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line.long 0x0 "DYN_RECONFIG,USB Dynamic reconfiguration register"
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rbitfld.long 0x0 4. "DYN_RECONFIG_RDY_STS,This bit indicates the ready status for the dynamic reconfiguration when set to 1 indicates the block is ready for reconfiguration." "0,1"
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newline
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bitfld.long 0x0 1.--3. "DYN_RECONFIG_EPNO,These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1." "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 0. "DYN_CONFIG_EN,This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1 indicates the reconfiguration required for selected EP." "0,1"
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rgroup.long 0x60++0x7
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line.long 0x0 "SOF0,Start Of Frame Register"
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hexmask.long.byte 0x0 0.--7. 1. "FRAME_NUMBER,It has the lower 8 bits [7:0] of the SOF frame number."
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line.long 0x4 "SOF1,Start Of Frame Register"
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bitfld.long 0x4 0.--2. "FRAME_NUMBER_MSB,It has the upper 3 bits [10:8] of the SOF frame number." "0,1,2,3,4,5,6,7"
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group.long 0x70++0xB
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line.long 0x0 "SIE_EP2_CNT0,Non-control endpoint count register"
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bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
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newline
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bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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newline
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bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
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line.long 0x4 "SIE_EP2_CNT1,Non-control endpoint count register"
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hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
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line.long 0x8 "SIE_EP2_CR0,Non-control endpoint's control Register"
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bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
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newline
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bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
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newline
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bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
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newline
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bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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newline
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hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
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rgroup.long 0x80++0x7
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line.long 0x0 "OSCLK_DR0,Oscillator lock data register 0"
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hexmask.long.byte 0x0 0.--7. 1. "ADDER,These bits return the lower 8 bits of the oscillator locking circuits adder output."
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line.long 0x4 "OSCLK_DR1,Oscillator lock data register 1"
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hexmask.long.byte 0x4 0.--6. 1. "ADDER_MSB,These bits return the upper 7 bits of the oscillator locking circuits adder output."
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group.long 0xA0++0x7
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line.long 0x0 "EP0_CR,Endpoint0 control Register"
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bitfld.long 0x0 7. "SETUP_RCVD,When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from.." "0,1"
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bitfld.long 0x0 6. "IN_RCVD,When set this bit indicates a valid IN packet has been received. This bit is updated to '1' after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN.." "0,1"
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newline
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bitfld.long 0x0 5. "OUT_RCVD,When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to '1' after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the.." "0,1"
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bitfld.long 0x0 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
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line.long 0x4 "EP0_CNT,Endpoint0 count Register"
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bitfld.long 0x4 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
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newline
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bitfld.long 0x4 6. "DATA_VALID,This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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hexmask.long.byte 0x4 0.--3. 1. "BYTE_COUNT,These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions.."
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group.long 0xB0++0xB
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line.long 0x0 "SIE_EP3_CNT0,Non-control endpoint count register"
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bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
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newline
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bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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newline
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bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
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line.long 0x4 "SIE_EP3_CNT1,Non-control endpoint count register"
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hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
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line.long 0x8 "SIE_EP3_CR0,Non-control endpoint's control Register"
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bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
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newline
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bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
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newline
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bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
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newline
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bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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newline
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hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
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group.long 0xF0++0xB
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line.long 0x0 "SIE_EP4_CNT0,Non-control endpoint count register"
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bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
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newline
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bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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newline
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bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
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line.long 0x4 "SIE_EP4_CNT1,Non-control endpoint count register"
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hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
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line.long 0x8 "SIE_EP4_CR0,Non-control endpoint's control Register"
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bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
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newline
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bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
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newline
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bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
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newline
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bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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newline
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hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
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group.long 0x130++0xB
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line.long 0x0 "SIE_EP5_CNT0,Non-control endpoint count register"
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bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
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newline
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bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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newline
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bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
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line.long 0x4 "SIE_EP5_CNT1,Non-control endpoint count register"
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hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
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line.long 0x8 "SIE_EP5_CR0,Non-control endpoint's control Register"
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bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
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newline
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bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
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newline
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bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
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newline
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bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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newline
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hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
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group.long 0x170++0xB
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line.long 0x0 "SIE_EP6_CNT0,Non-control endpoint count register"
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bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
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newline
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bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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newline
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bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
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line.long 0x4 "SIE_EP6_CNT1,Non-control endpoint count register"
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hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
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line.long 0x8 "SIE_EP6_CR0,Non-control endpoint's control Register"
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bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
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newline
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bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
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newline
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bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
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newline
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bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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newline
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hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
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group.long 0x1B0++0xB
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line.long 0x0 "SIE_EP7_CNT0,Non-control endpoint count register"
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bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
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newline
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bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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|
newline
|
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bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SIE_EP7_CNT1,Non-control endpoint count register"
|
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hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
|
line.long 0x8 "SIE_EP7_CR0,Non-control endpoint's control Register"
|
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bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
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|
newline
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bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
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|
newline
|
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bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
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|
newline
|
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bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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newline
|
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hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
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|
group.long 0x1F0++0xB
|
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line.long 0x0 "SIE_EP8_CNT0,Non-control endpoint count register"
|
|
bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
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newline
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bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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|
newline
|
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bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SIE_EP8_CNT1,Non-control endpoint count register"
|
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hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
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line.long 0x8 "SIE_EP8_CR0,Non-control endpoint's control Register"
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bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
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|
newline
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bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
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newline
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bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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newline
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hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
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group.long 0x200++0xB
|
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line.long 0x0 "ARB_EP1_CFG,Endpoint Configuration Register *1"
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bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
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newline
|
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bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
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newline
|
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bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
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newline
|
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bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
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line.long 0x4 "ARB_EP1_INT_EN,Endpoint Interrupt Enable Register *1"
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bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
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newline
|
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bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
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newline
|
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bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
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newline
|
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bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
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line.long 0x8 "ARB_EP1_SR,Endpoint Interrupt Enable Register *1"
|
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bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
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newline
|
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bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
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group.long 0x210++0x13
|
|
line.long 0x0 "ARB_RW1_WA,Endpoint Write Address value *1. *2"
|
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hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
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line.long 0x4 "ARB_RW1_WA_MSB,Endpoint Write Address value *1. *2"
|
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bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW1_RA,Endpoint Read Address value *1. *2"
|
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hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
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line.long 0xC "ARB_RW1_RA_MSB,Endpoint Read Address value *1. *2"
|
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bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
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line.long 0x10 "ARB_RW1_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
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group.long 0x230++0x3
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line.long 0x0 "BUF_SIZE,Dedicated Endpoint Buffer Size Register *1"
|
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hexmask.long.byte 0x0 4.--7. 1. "OUT_BUF,Buffer size for OUT Endpoints."
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "IN_BUF,Buffer size for IN Endpoints."
|
|
group.long 0x238++0x13
|
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line.long 0x0 "EP_ACTIVE,Endpoint Active Indication Register *1"
|
|
bitfld.long 0x0 7. "EP8_ACT,Indicates that Endpoint is currently active." "0,1"
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|
newline
|
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bitfld.long 0x0 6. "EP7_ACT,Indicates that Endpoint is currently active." "0,1"
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|
newline
|
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bitfld.long 0x0 5. "EP6_ACT,Indicates that Endpoint is currently active." "0,1"
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|
newline
|
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bitfld.long 0x0 4. "EP5_ACT,Indicates that Endpoint is currently active." "0,1"
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newline
|
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bitfld.long 0x0 3. "EP4_ACT,Indicates that Endpoint is currently active." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "EP3_ACT,Indicates that Endpoint is currently active." "0,1"
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newline
|
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bitfld.long 0x0 1. "EP2_ACT,Indicates that Endpoint is currently active." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "EP1_ACT,Indicates that Endpoint is currently active." "0,1"
|
|
line.long 0x4 "EP_TYPE,Endpoint Type (IN/OUT) Indication *1"
|
|
bitfld.long 0x4 7. "EP8_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
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|
newline
|
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bitfld.long 0x4 6. "EP7_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
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bitfld.long 0x4 5. "EP6_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
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bitfld.long 0x4 4. "EP5_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
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bitfld.long 0x4 3. "EP4_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
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bitfld.long 0x4 2. "EP3_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
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bitfld.long 0x4 1. "EP2_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
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bitfld.long 0x4 0. "EP1_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
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line.long 0x8 "ARB_EP2_CFG,Endpoint Configuration Register *1"
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bitfld.long 0x8 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
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newline
|
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bitfld.long 0x8 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
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|
newline
|
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bitfld.long 0x8 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0xC "ARB_EP2_INT_EN,Endpoint Interrupt Enable Register *1"
|
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bitfld.long 0xC 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
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bitfld.long 0xC 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0xC 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
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bitfld.long 0xC 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
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bitfld.long 0xC 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
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bitfld.long 0xC 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x10 "ARB_EP2_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x10 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x10 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x10 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x10 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x250++0x13
|
|
line.long 0x0 "ARB_RW2_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW2_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW2_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW2_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
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line.long 0x10 "ARB_RW2_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "ARB_CFG,Arbiter Configuration Register *1"
|
|
bitfld.long 0x0 7. "CFG_CMP,Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required." "0,1"
|
|
newline
|
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bitfld.long 0x0 5.--6. "DMA_CFG,DMA Access Configuration." "0: No DMA,1: Manual DMA,2: Auto DMA,?"
|
|
newline
|
|
bitfld.long 0x0 4. "AUTO_MEM,Enables Auto Memory Configuration. Manual memory configuration by default." "0,1"
|
|
line.long 0x4 "USB_CLK_EN,USB Block Clock Enable Register"
|
|
bitfld.long 0x4 0. "CSR_CLK_EN,Clock Enable for Core Logic clocked by AHB bus clock" "0,1"
|
|
line.long 0x8 "ARB_INT_EN,Arbiter Interrupt Enable *1"
|
|
bitfld.long 0x8 7. "EP8_INTR_EN,Enables interrupt for EP8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "EP7_INTR_EN,Enables interrupt for EP7" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "EP6_INTR_EN,Enables interrupt for EP6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EP5_INTR_EN,Enables interrupt for EP5" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "EP4_INTR_EN,Enables interrupt for EP4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "EP3_INTR_EN,Enables interrupt for EP3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "EP2_INTR_EN,Enables interrupt for EP2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "EP1_INTR_EN,Enables interrupt for EP1" "0,1"
|
|
rgroup.long 0x27C++0x3
|
|
line.long 0x0 "ARB_INT_SR,Arbiter Interrupt Status *1"
|
|
bitfld.long 0x0 7. "EP8_INTR,Interrupt status for EP8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EP7_INTR,Interrupt status for EP7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EP6_INTR,Interrupt status for EP6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EP5_INTR,Interrupt status for EP5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EP4_INTR,Interrupt status for EP4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EP3_INTR,Interrupt status for EP3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EP2_INTR,Interrupt status for EP2" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "EP1_INTR,Interrupt status for EP1" "0,1"
|
|
group.long 0x280++0xB
|
|
line.long 0x0 "ARB_EP3_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP3_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP3_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x290++0x13
|
|
line.long 0x0 "ARB_RW3_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW3_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW3_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW3_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW3_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x2B0++0x7
|
|
line.long 0x0 "CWA,Common Area Write Address *1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CWA,Write Address for Common Area"
|
|
line.long 0x4 "CWA_MSB,Endpoint Read Address value *1"
|
|
bitfld.long 0x4 0. "CWA_MSB,Write Address for Common Area" "0,1"
|
|
group.long 0x2C0++0xB
|
|
line.long 0x0 "ARB_EP4_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP4_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP4_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x2D0++0x13
|
|
line.long 0x0 "ARB_RW4_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW4_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW4_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW4_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW4_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x2F0++0x7
|
|
line.long 0x0 "DMA_THRES,DMA Burst / Threshold Configuration"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DMA_THS,DMA Threshold count"
|
|
line.long 0x4 "DMA_THRES_MSB,DMA Burst / Threshold Configuration"
|
|
bitfld.long 0x4 0. "DMA_THS_MSB,DMA Threshold count" "0,1"
|
|
group.long 0x300++0xB
|
|
line.long 0x0 "ARB_EP5_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP5_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP5_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x310++0x13
|
|
line.long 0x0 "ARB_RW5_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW5_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW5_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW5_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW5_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x330++0x3
|
|
line.long 0x0 "BUS_RST_CNT,Bus Reset Count Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "BUS_RST_CNT,Bus Reset Count Length"
|
|
group.long 0x340++0xB
|
|
line.long 0x0 "ARB_EP6_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP6_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP6_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x350++0x13
|
|
line.long 0x0 "ARB_RW6_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW6_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW6_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW6_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW6_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x380++0xB
|
|
line.long 0x0 "ARB_EP7_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP7_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP7_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x390++0x13
|
|
line.long 0x0 "ARB_RW7_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW7_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW7_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW7_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW7_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x3C0++0xB
|
|
line.long 0x0 "ARB_EP8_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP8_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP8_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x3D0++0x13
|
|
line.long 0x0 "ARB_RW8_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW8_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW8_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW8_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW8_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
repeat 512. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x400)++0x3
|
|
line.long 0x0 "MEM_DATA[$1],DATA"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
repeat.end
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "SOF16,Start Of Frame Register"
|
|
hexmask.long.word 0x0 0.--10. 1. "FRAME_NUMBER16,The frame number (11b)"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "OSCLK_DR16,Oscillator lock data register"
|
|
hexmask.long.word 0x0 0.--14. 1. "ADDER16,These bits return the oscillator locking circuits adder output."
|
|
group.long 0x1210++0x3
|
|
line.long 0x0 "ARB_RW1_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1218++0x3
|
|
line.long 0x0 "ARB_RW1_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x1220++0x3
|
|
line.long 0x0 "ARB_RW1_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x1250++0x3
|
|
line.long 0x0 "ARB_RW2_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1258++0x3
|
|
line.long 0x0 "ARB_RW2_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x1260++0x3
|
|
line.long 0x0 "ARB_RW2_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x1290++0x3
|
|
line.long 0x0 "ARB_RW3_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1298++0x3
|
|
line.long 0x0 "ARB_RW3_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x12A0++0x3
|
|
line.long 0x0 "ARB_RW3_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x12B0++0x3
|
|
line.long 0x0 "CWA16,Common Area Write Address"
|
|
hexmask.long.word 0x0 0.--8. 1. "CWA16,Write Address for Common Area"
|
|
group.long 0x12D0++0x3
|
|
line.long 0x0 "ARB_RW4_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x12D8++0x3
|
|
line.long 0x0 "ARB_RW4_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x12E0++0x3
|
|
line.long 0x0 "ARB_RW4_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x12F0++0x3
|
|
line.long 0x0 "DMA_THRES16,DMA Burst / Threshold Configuration"
|
|
hexmask.long.word 0x0 0.--8. 1. "DMA_THS16,DMA Threshold count"
|
|
group.long 0x1310++0x3
|
|
line.long 0x0 "ARB_RW5_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1318++0x3
|
|
line.long 0x0 "ARB_RW5_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x1320++0x3
|
|
line.long 0x0 "ARB_RW5_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x1350++0x3
|
|
line.long 0x0 "ARB_RW6_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1358++0x3
|
|
line.long 0x0 "ARB_RW6_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x1360++0x3
|
|
line.long 0x0 "ARB_RW6_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x1390++0x3
|
|
line.long 0x0 "ARB_RW7_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1398++0x3
|
|
line.long 0x0 "ARB_RW7_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x13A0++0x3
|
|
line.long 0x0 "ARB_RW7_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x13D0++0x3
|
|
line.long 0x0 "ARB_RW8_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x13D8++0x3
|
|
line.long 0x0 "ARB_RW8_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x13E0++0x3
|
|
line.long 0x0 "ARB_RW8_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
sif (cpuis("CY8C6??6*")||cpuis("CY8C6??7*")||cpuis("CYB06??6*")||cpuis("CYB06??7*")||cpuis("CYS06??6*")||cpuis("CYS06??7*"))
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "EP0_DR[$1],Control End point EP0 Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_BYTE,This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred."
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("CY8C6??8*")||cpuis("CY8C6??A*")||cpuis("CYB06??8*")||cpuis("CYB06??A*")||cpuis("CYS06??8*")||cpuis("CYS06??A*"))
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "EP0_DR[$1],Control End point EP0 Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_BYTE,This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred."
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??5*")||cpuis("CYB06??5*")||cpuis("CYS06??5*"))
|
|
tree "USBDEV (USB Device)"
|
|
base ad:0x403F0000
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "EP0_DR[$1],Control End point EP0 Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_BYTE,This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred."
|
|
repeat.end
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "CR0,USB control 0 Register"
|
|
bitfld.long 0x0 7. "USB_ENABLE,This bit enables the device to respond to USB traffic." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "DEVICE_ADDRESS,These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware.."
|
|
line.long 0x4 "CR1,USB control 1 Register"
|
|
bitfld.long 0x4 3. "RSVD_3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUS_ACTIVITY,The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ENABLE_LOCK,This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "REG_ENABLE,This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to.." "0,1"
|
|
line.long 0x8 "SIE_EP_INT_EN,USB SIE Data Endpoints Interrupt Enable Register"
|
|
bitfld.long 0x8 7. "EP8_INTR_EN,Enables interrupt for EP8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "EP7_INTR_EN,Enables interrupt for EP7" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "EP6_INTR_EN,Enables interrupt for EP6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EP5_INTR_EN,Enables interrupt for EP5" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "EP4_INTR_EN,Enables interrupt for EP4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "EP3_INTR_EN,Enables interrupt for EP3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "EP2_INTR_EN,Enables interrupt for EP2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "EP1_INTR_EN,Enables interrupt for EP1" "0,1"
|
|
line.long 0xC "SIE_EP_INT_SR,USB SIE Data Endpoint Interrupt Status"
|
|
bitfld.long 0xC 7. "EP8_INTR,Interrupt status for EP8" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "EP7_INTR,Interrupt status for EP7" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "EP6_INTR,Interrupt status for EP6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "EP5_INTR,Interrupt status for EP5" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "EP4_INTR,Interrupt status for EP4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "EP3_INTR,Interrupt status for EP3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "EP2_INTR,Interrupt status for EP2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "EP1_INTR,Interrupt status for EP1" "0,1"
|
|
line.long 0x10 "SIE_EP1_CNT0,Non-control endpoint count register"
|
|
bitfld.long 0x10 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
bitfld.long 0x10 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "SIE_EP1_CNT1,Non-control endpoint count register"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
|
line.long 0x18 "SIE_EP1_CR0,Non-control endpoint's control Register"
|
|
bitfld.long 0x18 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
hexmask.long.byte 0x18 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "USBIO_CR0,USBIO Control 0 Register"
|
|
bitfld.long 0x0 7. "TEN,USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TSE0,Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TD,Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1." "0: Force USB K state (D+ is low D- is high).,1: Force USB J state (D+ is high D- is low)."
|
|
newline
|
|
rbitfld.long 0x0 0. "RD,Received Data. This read only bit gives the state of the USB differential receiver when IOMODE bit is '0' and USB doesn't transmit. This bit is valid if USB Device." "0: D+ < D- (K state),1: D+ > D- (J state)"
|
|
line.long 0x4 "USBIO_CR2,USBIO control 2 Register"
|
|
bitfld.long 0x4 7. "RSVD_7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TEST_PKT,This bit enables the device to transmit a packet in response to an internally generated IN packet. When set one packet will be generated." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "RSVD_5_0,N/A"
|
|
line.long 0x8 "USBIO_CR1,USBIO control 1 Register"
|
|
bitfld.long 0x8 5. "IOMODE,This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "RSVD_2,N/A" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 1. "DPO,This read only bit gives the state of the D+ pin when IOMODE bit is '0' and USB doesn't transmit." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 0. "DMO,This read only bit gives the state of the D- pin when IOMODE bit is '0' and USB doesn't transmit." "0,1"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "DYN_RECONFIG,USB Dynamic reconfiguration register"
|
|
rbitfld.long 0x0 4. "DYN_RECONFIG_RDY_STS,This bit indicates the ready status for the dynamic reconfiguration when set to 1 indicates the block is ready for reconfiguration." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1.--3. "DYN_RECONFIG_EPNO,These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0. "DYN_CONFIG_EN,This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1 indicates the reconfiguration required for selected EP." "0,1"
|
|
rgroup.long 0x60++0x7
|
|
line.long 0x0 "SOF0,Start Of Frame Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FRAME_NUMBER,It has the lower 8 bits [7:0] of the SOF frame number."
|
|
line.long 0x4 "SOF1,Start Of Frame Register"
|
|
bitfld.long 0x4 0.--2. "FRAME_NUMBER_MSB,It has the upper 3 bits [10:8] of the SOF frame number." "0,1,2,3,4,5,6,7"
|
|
group.long 0x70++0xB
|
|
line.long 0x0 "SIE_EP2_CNT0,Non-control endpoint count register"
|
|
bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SIE_EP2_CNT1,Non-control endpoint count register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
|
line.long 0x8 "SIE_EP2_CR0,Non-control endpoint's control Register"
|
|
bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
rgroup.long 0x80++0x7
|
|
line.long 0x0 "OSCLK_DR0,Oscillator lock data register 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDER,These bits return the lower 8 bits of the oscillator locking circuits adder output."
|
|
line.long 0x4 "OSCLK_DR1,Oscillator lock data register 1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "ADDER_MSB,These bits return the upper 7 bits of the oscillator locking circuits adder output."
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "EP0_CR,Endpoint0 control Register"
|
|
bitfld.long 0x0 7. "SETUP_RCVD,When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "IN_RCVD,When set this bit indicates a valid IN packet has been received. This bit is updated to '1' after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUT_RCVD,When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to '1' after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
line.long 0x4 "EP0_CNT,Endpoint0 count Register"
|
|
bitfld.long 0x4 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "DATA_VALID,This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "BYTE_COUNT,These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions.."
|
|
group.long 0xB0++0xB
|
|
line.long 0x0 "SIE_EP3_CNT0,Non-control endpoint count register"
|
|
bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SIE_EP3_CNT1,Non-control endpoint count register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
|
line.long 0x8 "SIE_EP3_CR0,Non-control endpoint's control Register"
|
|
bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
group.long 0xF0++0xB
|
|
line.long 0x0 "SIE_EP4_CNT0,Non-control endpoint count register"
|
|
bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SIE_EP4_CNT1,Non-control endpoint count register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
|
line.long 0x8 "SIE_EP4_CR0,Non-control endpoint's control Register"
|
|
bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
group.long 0x130++0xB
|
|
line.long 0x0 "SIE_EP5_CNT0,Non-control endpoint count register"
|
|
bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SIE_EP5_CNT1,Non-control endpoint count register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
|
line.long 0x8 "SIE_EP5_CR0,Non-control endpoint's control Register"
|
|
bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
group.long 0x170++0xB
|
|
line.long 0x0 "SIE_EP6_CNT0,Non-control endpoint count register"
|
|
bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SIE_EP6_CNT1,Non-control endpoint count register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
|
line.long 0x8 "SIE_EP6_CR0,Non-control endpoint's control Register"
|
|
bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
group.long 0x1B0++0xB
|
|
line.long 0x0 "SIE_EP7_CNT0,Non-control endpoint count register"
|
|
bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SIE_EP7_CNT1,Non-control endpoint count register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
|
line.long 0x8 "SIE_EP7_CR0,Non-control endpoint's control Register"
|
|
bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
group.long 0x1F0++0xB
|
|
line.long 0x0 "SIE_EP8_CNT0,Non-control endpoint count register"
|
|
bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SIE_EP8_CNT1,Non-control endpoint count register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
|
line.long 0x8 "SIE_EP8_CR0,Non-control endpoint's control Register"
|
|
bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
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hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "ARB_EP1_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP1_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP1_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x210++0x13
|
|
line.long 0x0 "ARB_RW1_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW1_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW1_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW1_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW1_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x230++0x3
|
|
line.long 0x0 "BUF_SIZE,Dedicated Endpoint Buffer Size Register *1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "OUT_BUF,Buffer size for OUT Endpoints."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IN_BUF,Buffer size for IN Endpoints."
|
|
group.long 0x238++0x13
|
|
line.long 0x0 "EP_ACTIVE,Endpoint Active Indication Register *1"
|
|
bitfld.long 0x0 7. "EP8_ACT,Indicates that Endpoint is currently active." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EP7_ACT,Indicates that Endpoint is currently active." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EP6_ACT,Indicates that Endpoint is currently active." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EP5_ACT,Indicates that Endpoint is currently active." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EP4_ACT,Indicates that Endpoint is currently active." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EP3_ACT,Indicates that Endpoint is currently active." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EP2_ACT,Indicates that Endpoint is currently active." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EP1_ACT,Indicates that Endpoint is currently active." "0,1"
|
|
line.long 0x4 "EP_TYPE,Endpoint Type (IN/OUT) Indication *1"
|
|
bitfld.long 0x4 7. "EP8_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
|
bitfld.long 0x4 6. "EP7_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
|
bitfld.long 0x4 5. "EP6_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
|
bitfld.long 0x4 4. "EP5_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
|
bitfld.long 0x4 3. "EP4_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
|
bitfld.long 0x4 2. "EP3_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
|
bitfld.long 0x4 1. "EP2_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
|
bitfld.long 0x4 0. "EP1_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
line.long 0x8 "ARB_EP2_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x8 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x8 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0xC "ARB_EP2_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0xC 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x10 "ARB_EP2_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x10 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x250++0x13
|
|
line.long 0x0 "ARB_RW2_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW2_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW2_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW2_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW2_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "ARB_CFG,Arbiter Configuration Register *1"
|
|
bitfld.long 0x0 7. "CFG_CMP,Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5.--6. "DMA_CFG,DMA Access Configuration." "0: No DMA,1: Manual DMA,2: Auto DMA,?"
|
|
newline
|
|
bitfld.long 0x0 4. "AUTO_MEM,Enables Auto Memory Configuration. Manual memory configuration by default." "0,1"
|
|
line.long 0x4 "USB_CLK_EN,USB Block Clock Enable Register"
|
|
bitfld.long 0x4 0. "CSR_CLK_EN,Clock Enable for Core Logic clocked by AHB bus clock" "0,1"
|
|
line.long 0x8 "ARB_INT_EN,Arbiter Interrupt Enable *1"
|
|
bitfld.long 0x8 7. "EP8_INTR_EN,Enables interrupt for EP8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "EP7_INTR_EN,Enables interrupt for EP7" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "EP6_INTR_EN,Enables interrupt for EP6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EP5_INTR_EN,Enables interrupt for EP5" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "EP4_INTR_EN,Enables interrupt for EP4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "EP3_INTR_EN,Enables interrupt for EP3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "EP2_INTR_EN,Enables interrupt for EP2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "EP1_INTR_EN,Enables interrupt for EP1" "0,1"
|
|
rgroup.long 0x27C++0x3
|
|
line.long 0x0 "ARB_INT_SR,Arbiter Interrupt Status *1"
|
|
bitfld.long 0x0 7. "EP8_INTR,Interrupt status for EP8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EP7_INTR,Interrupt status for EP7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EP6_INTR,Interrupt status for EP6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EP5_INTR,Interrupt status for EP5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EP4_INTR,Interrupt status for EP4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EP3_INTR,Interrupt status for EP3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EP2_INTR,Interrupt status for EP2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EP1_INTR,Interrupt status for EP1" "0,1"
|
|
group.long 0x280++0xB
|
|
line.long 0x0 "ARB_EP3_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP3_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP3_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x290++0x13
|
|
line.long 0x0 "ARB_RW3_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW3_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW3_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW3_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW3_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x2B0++0x7
|
|
line.long 0x0 "CWA,Common Area Write Address *1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CWA,Write Address for Common Area"
|
|
line.long 0x4 "CWA_MSB,Endpoint Read Address value *1"
|
|
bitfld.long 0x4 0. "CWA_MSB,Write Address for Common Area" "0,1"
|
|
group.long 0x2C0++0xB
|
|
line.long 0x0 "ARB_EP4_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP4_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP4_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x2D0++0x13
|
|
line.long 0x0 "ARB_RW4_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW4_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW4_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW4_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW4_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x2F0++0x7
|
|
line.long 0x0 "DMA_THRES,DMA Burst / Threshold Configuration"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DMA_THS,DMA Threshold count"
|
|
line.long 0x4 "DMA_THRES_MSB,DMA Burst / Threshold Configuration"
|
|
bitfld.long 0x4 0. "DMA_THS_MSB,DMA Threshold count" "0,1"
|
|
group.long 0x300++0xB
|
|
line.long 0x0 "ARB_EP5_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP5_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP5_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x310++0x13
|
|
line.long 0x0 "ARB_RW5_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW5_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW5_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW5_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW5_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x330++0x3
|
|
line.long 0x0 "BUS_RST_CNT,Bus Reset Count Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "BUS_RST_CNT,Bus Reset Count Length"
|
|
group.long 0x340++0xB
|
|
line.long 0x0 "ARB_EP6_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP6_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP6_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x350++0x13
|
|
line.long 0x0 "ARB_RW6_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW6_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW6_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW6_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW6_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x380++0xB
|
|
line.long 0x0 "ARB_EP7_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP7_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP7_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x390++0x13
|
|
line.long 0x0 "ARB_RW7_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW7_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW7_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW7_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW7_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x3C0++0xB
|
|
line.long 0x0 "ARB_EP8_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP8_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP8_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x3D0++0x13
|
|
line.long 0x0 "ARB_RW8_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW8_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW8_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW8_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW8_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
repeat 512. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x400)++0x3
|
|
line.long 0x0 "MEM_DATA[$1],DATA"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
repeat.end
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "SOF16,Start Of Frame Register"
|
|
hexmask.long.word 0x0 0.--10. 1. "FRAME_NUMBER16,The frame number (11b)"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "OSCLK_DR16,Oscillator lock data register"
|
|
hexmask.long.word 0x0 0.--14. 1. "ADDER16,These bits return the oscillator locking circuits adder output."
|
|
group.long 0x1210++0x3
|
|
line.long 0x0 "ARB_RW1_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1218++0x3
|
|
line.long 0x0 "ARB_RW1_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x1220++0x3
|
|
line.long 0x0 "ARB_RW1_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x1250++0x3
|
|
line.long 0x0 "ARB_RW2_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1258++0x3
|
|
line.long 0x0 "ARB_RW2_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x1260++0x3
|
|
line.long 0x0 "ARB_RW2_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x1290++0x3
|
|
line.long 0x0 "ARB_RW3_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1298++0x3
|
|
line.long 0x0 "ARB_RW3_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x12A0++0x3
|
|
line.long 0x0 "ARB_RW3_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x12B0++0x3
|
|
line.long 0x0 "CWA16,Common Area Write Address"
|
|
hexmask.long.word 0x0 0.--8. 1. "CWA16,Write Address for Common Area"
|
|
group.long 0x12D0++0x3
|
|
line.long 0x0 "ARB_RW4_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x12D8++0x3
|
|
line.long 0x0 "ARB_RW4_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x12E0++0x3
|
|
line.long 0x0 "ARB_RW4_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x12F0++0x3
|
|
line.long 0x0 "DMA_THRES16,DMA Burst / Threshold Configuration"
|
|
hexmask.long.word 0x0 0.--8. 1. "DMA_THS16,DMA Threshold count"
|
|
group.long 0x1310++0x3
|
|
line.long 0x0 "ARB_RW5_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1318++0x3
|
|
line.long 0x0 "ARB_RW5_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x1320++0x3
|
|
line.long 0x0 "ARB_RW5_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x1350++0x3
|
|
line.long 0x0 "ARB_RW6_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1358++0x3
|
|
line.long 0x0 "ARB_RW6_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x1360++0x3
|
|
line.long 0x0 "ARB_RW6_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x1390++0x3
|
|
line.long 0x0 "ARB_RW7_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1398++0x3
|
|
line.long 0x0 "ARB_RW7_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x13A0++0x3
|
|
line.long 0x0 "ARB_RW7_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x13D0++0x3
|
|
line.long 0x0 "ARB_RW8_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x13D8++0x3
|
|
line.long 0x0 "ARB_RW8_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x13E0++0x3
|
|
line.long 0x0 "ARB_RW8_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CY8C6??4*")||cpuis("CYB06??4*")||cpuis("CYS06??4*"))
|
|
tree "USBDEV (USB Device)"
|
|
base ad:0x403F0000
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "EP0_DR[$1],Control End point EP0 Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_BYTE,This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred."
|
|
repeat.end
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "CR0,USB control 0 Register"
|
|
bitfld.long 0x0 7. "USB_ENABLE,This bit enables the device to respond to USB traffic." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "DEVICE_ADDRESS,These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware.."
|
|
line.long 0x4 "CR1,USB control 1 Register"
|
|
bitfld.long 0x4 3. "RSVD_3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUS_ACTIVITY,The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ENABLE_LOCK,This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "REG_ENABLE,This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to.." "0,1"
|
|
line.long 0x8 "SIE_EP_INT_EN,USB SIE Data Endpoints Interrupt Enable Register"
|
|
bitfld.long 0x8 7. "EP8_INTR_EN,Enables interrupt for EP8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "EP7_INTR_EN,Enables interrupt for EP7" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "EP6_INTR_EN,Enables interrupt for EP6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EP5_INTR_EN,Enables interrupt for EP5" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "EP4_INTR_EN,Enables interrupt for EP4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "EP3_INTR_EN,Enables interrupt for EP3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "EP2_INTR_EN,Enables interrupt for EP2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "EP1_INTR_EN,Enables interrupt for EP1" "0,1"
|
|
line.long 0xC "SIE_EP_INT_SR,USB SIE Data Endpoint Interrupt Status"
|
|
bitfld.long 0xC 7. "EP8_INTR,Interrupt status for EP8" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "EP7_INTR,Interrupt status for EP7" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "EP6_INTR,Interrupt status for EP6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "EP5_INTR,Interrupt status for EP5" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "EP4_INTR,Interrupt status for EP4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "EP3_INTR,Interrupt status for EP3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "EP2_INTR,Interrupt status for EP2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "EP1_INTR,Interrupt status for EP1" "0,1"
|
|
line.long 0x10 "SIE_EP1_CNT0,Non-control endpoint count register"
|
|
bitfld.long 0x10 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
bitfld.long 0x10 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "SIE_EP1_CNT1,Non-control endpoint count register"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
|
line.long 0x18 "SIE_EP1_CR0,Non-control endpoint's control Register"
|
|
bitfld.long 0x18 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
hexmask.long.byte 0x18 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "USBIO_CR0,USBIO Control 0 Register"
|
|
bitfld.long 0x0 7. "TEN,USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TSE0,Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TD,Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1." "0: Force USB K state (D+ is low D- is high).,1: Force USB J state (D+ is high D- is low)."
|
|
newline
|
|
rbitfld.long 0x0 0. "RD,Received Data. This read only bit gives the state of the USB differential receiver when IOMODE bit is '0' and USB doesn't transmit. This bit is valid if USB Device." "0: D+ < D- (K state),1: D+ > D- (J state)"
|
|
line.long 0x4 "USBIO_CR2,USBIO control 2 Register"
|
|
bitfld.long 0x4 7. "RSVD_7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TEST_PKT,This bit enables the device to transmit a packet in response to an internally generated IN packet. When set one packet will be generated." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "RSVD_5_0,N/A"
|
|
line.long 0x8 "USBIO_CR1,USBIO control 1 Register"
|
|
bitfld.long 0x8 5. "IOMODE,This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "RSVD_2,N/A" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 1. "DPO,This read only bit gives the state of the D+ pin when IOMODE bit is '0' and USB doesn't transmit." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 0. "DMO,This read only bit gives the state of the D- pin when IOMODE bit is '0' and USB doesn't transmit." "0,1"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "DYN_RECONFIG,USB Dynamic reconfiguration register"
|
|
rbitfld.long 0x0 4. "DYN_RECONFIG_RDY_STS,This bit indicates the ready status for the dynamic reconfiguration when set to 1 indicates the block is ready for reconfiguration." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1.--3. "DYN_RECONFIG_EPNO,These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0. "DYN_CONFIG_EN,This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1 indicates the reconfiguration required for selected EP." "0,1"
|
|
rgroup.long 0x60++0x7
|
|
line.long 0x0 "SOF0,Start Of Frame Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FRAME_NUMBER,It has the lower 8 bits [7:0] of the SOF frame number."
|
|
line.long 0x4 "SOF1,Start Of Frame Register"
|
|
bitfld.long 0x4 0.--2. "FRAME_NUMBER_MSB,It has the upper 3 bits [10:8] of the SOF frame number." "0,1,2,3,4,5,6,7"
|
|
group.long 0x70++0xB
|
|
line.long 0x0 "SIE_EP2_CNT0,Non-control endpoint count register"
|
|
bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SIE_EP2_CNT1,Non-control endpoint count register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
|
line.long 0x8 "SIE_EP2_CR0,Non-control endpoint's control Register"
|
|
bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
rgroup.long 0x80++0x7
|
|
line.long 0x0 "OSCLK_DR0,Oscillator lock data register 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDER,These bits return the lower 8 bits of the oscillator locking circuits adder output."
|
|
line.long 0x4 "OSCLK_DR1,Oscillator lock data register 1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "ADDER_MSB,These bits return the upper 7 bits of the oscillator locking circuits adder output."
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "EP0_CR,Endpoint0 control Register"
|
|
bitfld.long 0x0 7. "SETUP_RCVD,When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "IN_RCVD,When set this bit indicates a valid IN packet has been received. This bit is updated to '1' after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUT_RCVD,When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to '1' after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
line.long 0x4 "EP0_CNT,Endpoint0 count Register"
|
|
bitfld.long 0x4 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "DATA_VALID,This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "BYTE_COUNT,These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions.."
|
|
group.long 0xB0++0xB
|
|
line.long 0x0 "SIE_EP3_CNT0,Non-control endpoint count register"
|
|
bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SIE_EP3_CNT1,Non-control endpoint count register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
|
line.long 0x8 "SIE_EP3_CR0,Non-control endpoint's control Register"
|
|
bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
group.long 0xF0++0xB
|
|
line.long 0x0 "SIE_EP4_CNT0,Non-control endpoint count register"
|
|
bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SIE_EP4_CNT1,Non-control endpoint count register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
|
line.long 0x8 "SIE_EP4_CR0,Non-control endpoint's control Register"
|
|
bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
group.long 0x130++0xB
|
|
line.long 0x0 "SIE_EP5_CNT0,Non-control endpoint count register"
|
|
bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
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bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SIE_EP5_CNT1,Non-control endpoint count register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
|
line.long 0x8 "SIE_EP5_CR0,Non-control endpoint's control Register"
|
|
bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
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hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
group.long 0x170++0xB
|
|
line.long 0x0 "SIE_EP6_CNT0,Non-control endpoint count register"
|
|
bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
|
newline
|
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bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SIE_EP6_CNT1,Non-control endpoint count register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
|
line.long 0x8 "SIE_EP6_CR0,Non-control endpoint's control Register"
|
|
bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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|
newline
|
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hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
group.long 0x1B0++0xB
|
|
line.long 0x0 "SIE_EP7_CNT0,Non-control endpoint count register"
|
|
bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
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bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
|
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newline
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bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SIE_EP7_CNT1,Non-control endpoint count register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
|
line.long 0x8 "SIE_EP7_CR0,Non-control endpoint's control Register"
|
|
bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
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newline
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bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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newline
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hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
group.long 0x1F0++0xB
|
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line.long 0x0 "SIE_EP8_CNT0,Non-control endpoint count register"
|
|
bitfld.long 0x0 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "DATA_VALID,This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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newline
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bitfld.long 0x0 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SIE_EP8_CNT1,Non-control endpoint count register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."
|
|
line.long 0x8 "SIE_EP8_CR0,Non-control endpoint's control Register"
|
|
bitfld.long 0x8 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected. For an IN transaction this indicates a no response from HOST scenario. For an OUT transaction this represents an RxErr (PID" "0,1"
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|
newline
|
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bitfld.long 0x8 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register." "0: No ACK'd transactions since bit was last cleared.,1: Indicates a transaction ended with an ACK."
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|
newline
|
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hexmask.long.byte 0x8 0.--3. 1. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."
|
|
group.long 0x200++0xB
|
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line.long 0x0 "ARB_EP1_CFG,Endpoint Configuration Register *1"
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|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
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bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
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|
newline
|
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bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP1_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP1_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x210++0x13
|
|
line.long 0x0 "ARB_RW1_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW1_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW1_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW1_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW1_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x230++0x3
|
|
line.long 0x0 "BUF_SIZE,Dedicated Endpoint Buffer Size Register *1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "OUT_BUF,Buffer size for OUT Endpoints."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IN_BUF,Buffer size for IN Endpoints."
|
|
group.long 0x238++0x13
|
|
line.long 0x0 "EP_ACTIVE,Endpoint Active Indication Register *1"
|
|
bitfld.long 0x0 7. "EP8_ACT,Indicates that Endpoint is currently active." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EP7_ACT,Indicates that Endpoint is currently active." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EP6_ACT,Indicates that Endpoint is currently active." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EP5_ACT,Indicates that Endpoint is currently active." "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "EP4_ACT,Indicates that Endpoint is currently active." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EP3_ACT,Indicates that Endpoint is currently active." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EP2_ACT,Indicates that Endpoint is currently active." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EP1_ACT,Indicates that Endpoint is currently active." "0,1"
|
|
line.long 0x4 "EP_TYPE,Endpoint Type (IN/OUT) Indication *1"
|
|
bitfld.long 0x4 7. "EP8_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
|
bitfld.long 0x4 6. "EP7_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
|
bitfld.long 0x4 5. "EP6_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
|
bitfld.long 0x4 4. "EP5_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
|
bitfld.long 0x4 3. "EP4_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
|
bitfld.long 0x4 2. "EP3_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
|
bitfld.long 0x4 1. "EP2_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
newline
|
|
bitfld.long 0x4 0. "EP1_TYP,Endpoint Type Indication." "0: IN outpoint,1: OUT outpoint"
|
|
line.long 0x8 "ARB_EP2_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x8 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
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bitfld.long 0x8 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
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bitfld.long 0x8 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0xC "ARB_EP2_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0xC 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x10 "ARB_EP2_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x10 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x250++0x13
|
|
line.long 0x0 "ARB_RW2_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW2_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW2_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW2_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW2_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "ARB_CFG,Arbiter Configuration Register *1"
|
|
bitfld.long 0x0 7. "CFG_CMP,Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5.--6. "DMA_CFG,DMA Access Configuration." "0: No DMA,1: Manual DMA,2: Auto DMA,?"
|
|
newline
|
|
bitfld.long 0x0 4. "AUTO_MEM,Enables Auto Memory Configuration. Manual memory configuration by default." "0,1"
|
|
line.long 0x4 "USB_CLK_EN,USB Block Clock Enable Register"
|
|
bitfld.long 0x4 0. "CSR_CLK_EN,Clock Enable for Core Logic clocked by AHB bus clock" "0,1"
|
|
line.long 0x8 "ARB_INT_EN,Arbiter Interrupt Enable *1"
|
|
bitfld.long 0x8 7. "EP8_INTR_EN,Enables interrupt for EP8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "EP7_INTR_EN,Enables interrupt for EP7" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "EP6_INTR_EN,Enables interrupt for EP6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EP5_INTR_EN,Enables interrupt for EP5" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "EP4_INTR_EN,Enables interrupt for EP4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "EP3_INTR_EN,Enables interrupt for EP3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "EP2_INTR_EN,Enables interrupt for EP2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "EP1_INTR_EN,Enables interrupt for EP1" "0,1"
|
|
rgroup.long 0x27C++0x3
|
|
line.long 0x0 "ARB_INT_SR,Arbiter Interrupt Status *1"
|
|
bitfld.long 0x0 7. "EP8_INTR,Interrupt status for EP8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EP7_INTR,Interrupt status for EP7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EP6_INTR,Interrupt status for EP6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EP5_INTR,Interrupt status for EP5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EP4_INTR,Interrupt status for EP4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EP3_INTR,Interrupt status for EP3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EP2_INTR,Interrupt status for EP2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EP1_INTR,Interrupt status for EP1" "0,1"
|
|
group.long 0x280++0xB
|
|
line.long 0x0 "ARB_EP3_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP3_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP3_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x290++0x13
|
|
line.long 0x0 "ARB_RW3_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW3_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW3_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW3_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW3_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x2B0++0x7
|
|
line.long 0x0 "CWA,Common Area Write Address *1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CWA,Write Address for Common Area"
|
|
line.long 0x4 "CWA_MSB,Endpoint Read Address value *1"
|
|
bitfld.long 0x4 0. "CWA_MSB,Write Address for Common Area" "0,1"
|
|
group.long 0x2C0++0xB
|
|
line.long 0x0 "ARB_EP4_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP4_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP4_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x2D0++0x13
|
|
line.long 0x0 "ARB_RW4_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW4_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW4_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW4_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW4_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x2F0++0x7
|
|
line.long 0x0 "DMA_THRES,DMA Burst / Threshold Configuration"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DMA_THS,DMA Threshold count"
|
|
line.long 0x4 "DMA_THRES_MSB,DMA Burst / Threshold Configuration"
|
|
bitfld.long 0x4 0. "DMA_THS_MSB,DMA Threshold count" "0,1"
|
|
group.long 0x300++0xB
|
|
line.long 0x0 "ARB_EP5_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP5_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP5_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x310++0x13
|
|
line.long 0x0 "ARB_RW5_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW5_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW5_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW5_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW5_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x330++0x3
|
|
line.long 0x0 "BUS_RST_CNT,Bus Reset Count Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "BUS_RST_CNT,Bus Reset Count Length"
|
|
group.long 0x340++0xB
|
|
line.long 0x0 "ARB_EP6_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP6_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP6_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x350++0x13
|
|
line.long 0x0 "ARB_RW6_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW6_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW6_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW6_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW6_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x380++0xB
|
|
line.long 0x0 "ARB_EP7_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP7_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP7_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x390++0x13
|
|
line.long 0x0 "ARB_RW7_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW7_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW7_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW7_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW7_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x3C0++0xB
|
|
line.long 0x0 "ARB_EP8_CFG,Endpoint Configuration Register *1"
|
|
bitfld.long 0x0 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction." "0: Do not Reset Pointer; Krypton Backward..,1: Reset Pointer; recommended value for reduction.."
|
|
newline
|
|
bitfld.long 0x0 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass; CRC bytes will be written to..,1: CRC Bypass Set; CRC bytes will not be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1"
|
|
line.long 0x4 "ARB_EP8_INT_EN,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x4 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1"
|
|
line.long 0x8 "ARB_EP8_SR,Endpoint Interrupt Enable Register *1"
|
|
bitfld.long 0x8 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1"
|
|
group.long 0x3D0++0x13
|
|
line.long 0x0 "ARB_RW8_WA,Endpoint Write Address value *1. *2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WA,Write Address for EP"
|
|
line.long 0x4 "ARB_RW8_WA_MSB,Endpoint Write Address value *1. *2"
|
|
bitfld.long 0x4 0. "WA_MSB,Write Address for EP" "0,1"
|
|
line.long 0x8 "ARB_RW8_RA,Endpoint Read Address value *1. *2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RA,Read Address for EP"
|
|
line.long 0xC "ARB_RW8_RA_MSB,Endpoint Read Address value *1. *2"
|
|
bitfld.long 0xC 0. "RA_MSB,Read Address for EP" "0,1"
|
|
line.long 0x10 "ARB_RW8_DR,Endpoint Data Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
repeat 512. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x400)++0x3
|
|
line.long 0x0 "MEM_DATA[$1],DATA"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DR,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
repeat.end
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "SOF16,Start Of Frame Register"
|
|
hexmask.long.word 0x0 0.--10. 1. "FRAME_NUMBER16,The frame number (11b)"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "OSCLK_DR16,Oscillator lock data register"
|
|
hexmask.long.word 0x0 0.--14. 1. "ADDER16,These bits return the oscillator locking circuits adder output."
|
|
group.long 0x1210++0x3
|
|
line.long 0x0 "ARB_RW1_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1218++0x3
|
|
line.long 0x0 "ARB_RW1_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x1220++0x3
|
|
line.long 0x0 "ARB_RW1_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x1250++0x3
|
|
line.long 0x0 "ARB_RW2_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1258++0x3
|
|
line.long 0x0 "ARB_RW2_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x1260++0x3
|
|
line.long 0x0 "ARB_RW2_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x1290++0x3
|
|
line.long 0x0 "ARB_RW3_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1298++0x3
|
|
line.long 0x0 "ARB_RW3_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x12A0++0x3
|
|
line.long 0x0 "ARB_RW3_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x12B0++0x3
|
|
line.long 0x0 "CWA16,Common Area Write Address"
|
|
hexmask.long.word 0x0 0.--8. 1. "CWA16,Write Address for Common Area"
|
|
group.long 0x12D0++0x3
|
|
line.long 0x0 "ARB_RW4_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x12D8++0x3
|
|
line.long 0x0 "ARB_RW4_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x12E0++0x3
|
|
line.long 0x0 "ARB_RW4_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x12F0++0x3
|
|
line.long 0x0 "DMA_THRES16,DMA Burst / Threshold Configuration"
|
|
hexmask.long.word 0x0 0.--8. 1. "DMA_THS16,DMA Threshold count"
|
|
group.long 0x1310++0x3
|
|
line.long 0x0 "ARB_RW5_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1318++0x3
|
|
line.long 0x0 "ARB_RW5_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x1320++0x3
|
|
line.long 0x0 "ARB_RW5_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x1350++0x3
|
|
line.long 0x0 "ARB_RW6_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1358++0x3
|
|
line.long 0x0 "ARB_RW6_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x1360++0x3
|
|
line.long 0x0 "ARB_RW6_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x1390++0x3
|
|
line.long 0x0 "ARB_RW7_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x1398++0x3
|
|
line.long 0x0 "ARB_RW7_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x13A0++0x3
|
|
line.long 0x0 "ARB_RW7_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
group.long 0x13D0++0x3
|
|
line.long 0x0 "ARB_RW8_WA16,Endpoint Write Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "WA16,Write Address for EP"
|
|
group.long 0x13D8++0x3
|
|
line.long 0x0 "ARB_RW8_RA16,Endpoint Read Address value *3"
|
|
hexmask.long.word 0x0 0.--8. 1. "RA16,Read Address for EP"
|
|
group.long 0x13E0++0x3
|
|
line.long 0x0 "ARB_RW8_DR16,Endpoint Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR16,Data Register for EP ; This register is linked to the memory hence reset value is undefined"
|
|
tree.end
|
|
endif
|
|
tree "USBHOST (USB Host Controller)"
|
|
base ad:0x403F4000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "HOST_CTL0,Host Control 0 Register."
|
|
bitfld.long 0x0 31. "ENABLE,This bit enables the operation of this IP." "0: Disable USB Host,1: Enable USB Host"
|
|
bitfld.long 0x0 0. "HOST,This bit selects an operating mode of this IP." "0: USB Device,1: USB Host"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "HOST_CTL1,Host Control 1 Register."
|
|
bitfld.long 0x0 7. "RST,This bit resets the USB Host." "0: Normal operating mode,1: USB Host is reset"
|
|
bitfld.long 0x0 1. "USTP,This bit stops the clock for the USB Host operating unit. When this bit is '1' power consumption can be reduced by configuring this bit." "0: Normal operating mode,1: Stops the clock for the USB Host operating unit"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKSEL,This bit selects the operating clock of USB Host." "0: Low-speed clock,1: Full-speed clock"
|
|
group.long 0x100++0x23
|
|
line.long 0x0 "HOST_CTL2,Host Control 2 Register."
|
|
bitfld.long 0x0 6.--7. "TTEST,N/A" "0,1,2,3"
|
|
bitfld.long 0x0 5. "RSVD_5,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RSVD_4,N/A" "0,1"
|
|
bitfld.long 0x0 3. "ALIVE,This bit is used to specify the keep-alive function in the low-speed mode. If this bit it set to '1' while the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is '0' SE0 is output instead of SOF. This bit is only effective when the CLKSEL.." "0: SOF output,1: SE0 output"
|
|
newline
|
|
bitfld.long 0x0 2. "SOFSTEP,If this bit is set to '1' the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1' each time SOF is sent." "0: An interrupt occurred due to the HOST_HFCOMP..,1: An interrupt occurred"
|
|
bitfld.long 0x0 1. "CANCEL,When this bit is set to '1' if the target token is written to the Host Token Endpoint Register (HOST_TOKEN) in the EOF area (specified in the Host EOF Setup Register) its sending is canceled. When this bit is set to '0' token sending is not.." "0: Continues a token,1: Cancels a token"
|
|
newline
|
|
bitfld.long 0x0 0. "RETRY,If this bit is set to '1' the target token is retried if a NAK or error* occurs. Retry processing is performed after the time that is specified in the Host Retry Timer Setup Register (HOST_RTIMER)." "0: Doesn't retry token sending,1: Retries token sending"
|
|
line.long 0x4 "HOST_ERR,Host Error Status Register."
|
|
bitfld.long 0x4 7. "LSTSOF,If this bit is set to '1' it means that the SOF token can't be sent in the USB Host because other token is in process. When this bit is '0' it means that SOF token was sent with no error. Write '1' to clear a write of '0' is ignored." "0: SOF sent without error,1: SOF error detected"
|
|
bitfld.long 0x4 6. "RERR,When this bit is set to '1' it means that the received data exceeds the specified maximum number of packets in the USB Host. If a receive error is detected bit5 (TOUT) of this register is also set to '1'. When this bit is '0' it means that no.." "0: No receive error,1: Maximum packet receive error detected"
|
|
newline
|
|
bitfld.long 0x4 5. "TOUT,If this bit is set to '1' it means that no response is returned from the device within the specified time after a token has been sent in the USB Host. When this bit is '0' it means that no timeout is detected. Write '1' to clear a write of '0'.." "0: No timeout,1: Timeout has detected"
|
|
bitfld.long 0x4 4. "CRC,If this bit is set to '1' it means that a CRC error is detected in the USB Host. When this bit is '0' it means that no error is detected. If a CRC error is detected bit5 (TOUT) of this register is also set to '1'. Write '1' to clear a write of.." "0: No CRC error,1: CRC error detected"
|
|
newline
|
|
bitfld.long 0x4 3. "TGERR,If this bit is set to '1' it means that the data does not match the TGGL data. When this bit is '0' it means that no error is detected. Write '1' to clear a write of '0' is ignored." "0: No toggle error,1: Toggle error detected"
|
|
bitfld.long 0x4 2. "STUFF,If this bit is set to '1' it means that a bit stuffing error has been detected. When this bit is '0' it means that no error is detected. If a stuffing error is detected bit5 (TOUT) of this register is also set to '1'. Write '1' to clear a.." "0: No stuffing error,1: Stuffing error detected"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "HS,These flags indicate the status of a handshake packet to be sent or received." "0: Acknowledge Packet,1: Non-Acknowledge Packet,2: Stall Packet,3: Null Packet"
|
|
line.long 0x8 "HOST_STATUS,Host Status Register."
|
|
rbitfld.long 0x8 8. "HOST_ST,This bit shows whether the device is in USB Host mode. If the HOST bit of the Host Control Register (HOST_CTL0) is set to '1' this bit is set to '1'." "0: USB Device,1: USB Host"
|
|
rbitfld.long 0x8 7. "CLKSEL_ST,This bit shows whether it is full-speed or not. If the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is set to '1' this bit is set to '1'." "0: Low speed,1: Full speed"
|
|
newline
|
|
rbitfld.long 0x8 6. "RSTBUSY,This bit shows that USB Host is being reset internally. If the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1' this bit is set to '1'." "0: USB Host isn't being reset,1: USB Host is being reset"
|
|
rbitfld.long 0x8 5. "RSVD_5,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "URST,When this bit is set to '1' the USB bus is reset. This bit remains a '1' during USB bus resetting and changes to '0' when USB bus resetting is ended. If this bit is set to '0' the USB bus reset is complete" "0,1"
|
|
bitfld.long 0x8 3. "SOFBUSY,When a SOF token is sent using the Host Token Endpoint Register (HOST_TOKEN) this bit is set to '1' which means that the SOF timer is active. When this bit is '0' it means that the SOF timer is under suspension. To stop the active SOF timer .." "0: The SOF timer is stopped,1: The SOF timer is active"
|
|
newline
|
|
bitfld.long 0x8 2. "SUSP,If this bit is set to '1' the USB Host is placed into the suspend state. If this bit is set to '0' while it is '1' or the USB bus is placed into the k-state mode then suspend state is released and the RWIRQ bit of the Interrupt USB Host Register.." "?,1: Resume"
|
|
rbitfld.long 0x8 1. "TMODE,If this bit is '1' it means that the device is connected in the full-speed mode. When this bit is '0' it means that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status Register (HOST_STATUS) is.." "0: Low-speed,1: Full-speed"
|
|
newline
|
|
rbitfld.long 0x8 0. "CSTAT,When this bit is '1' it means that the device is connected. When this bit is '0' it means that the device is disconnected." "0: Device is disconnected,1: Device is connected"
|
|
line.long 0xC "HOST_FCOMP,Host SOF Interrupt Frame Compare Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "FRAMECOMP,These bits are used to specify the data to be compared with the low-order eight bits of a frame number when sending a SOF token."
|
|
line.long 0x10 "HOST_RTIMER,Host Retry Timer Setup Register"
|
|
hexmask.long.tbyte 0x10 0.--17. 1. "RTIMER,These bits are used to specify the retry time in this register. The retry timer is activated when token sending starts while the RETRY bit of Host Control 2 Register (HOST_CTL2) is '1'. The retry time is then decremented by one when a 1-bit.."
|
|
line.long 0x14 "HOST_ADDR,Host Address Register"
|
|
hexmask.long.byte 0x14 0.--6. 1. "ADDRESS,These bits are used to specify a token address."
|
|
line.long 0x18 "HOST_EOF,Host EOF Setup Register"
|
|
hexmask.long.word 0x18 0.--13. 1. "EOF,These bits are used to specify the time to disable token sending before transferring SOF. Specify the time with a margin which is longer than the one-packet length. The time unit is the 1-bit transfer time."
|
|
line.long 0x1C "HOST_FRAME,Host Frame Setup Register"
|
|
hexmask.long.word 0x1C 0.--10. 1. "FRAME,These bits are used to specify a frame number of SOF."
|
|
line.long 0x20 "HOST_TOKEN,Host Token Endpoint Register"
|
|
bitfld.long 0x20 8. "TGGL,This bit is used to set toggle data. Toggle data is sent depending on the setting of this bit. When receiving toggle data received toggle data is compared with the toggle data of this bit to verify whether or not an error occurs." "0: DATA0,1: DATA1"
|
|
bitfld.long 0x20 4.--6. "TKNEN,These bits send a token according to the current settings. After operation is complete the TKNEN bit is set to '000' and the CMPIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'." "0: Sends no data.,1: Sends SETUP token.,2: Sends IN token.,3: Sends OUT token.,4: Sends SOF token.,5: Sends Isochronous IN.,6: Sends Isochronous OUT.,7: N/A"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--3. 1. "ENDPT,These bits are used to specify an endpoint to send or receive data to or from the device."
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "HOST_EP1_CTL,Host Endpoint 1 Control Register"
|
|
bitfld.long 0x0 15. "BFINI,This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting therefore set the RST bit to '0'.." "0: Clears the initialization,1: Initializes the send/receive buffer"
|
|
bitfld.long 0x0 12. "DIR,This bit specifies the transfer direction the Endpoint support." "0: IN Endpoint,1: OUT Endpoint"
|
|
newline
|
|
bitfld.long 0x0 11. "DMAE,This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA.." "0: Releases the packet transfer mode,1: Sets the packet transfer mode"
|
|
bitfld.long 0x0 10. "NULLE,When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1) this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer." "0: Releases the NULL automatic transfer mode,1: Sets the NULL automatic transfer mode"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "PKS1,This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x100."
|
|
rgroup.long 0x404++0x3
|
|
line.long 0x0 "HOST_EP1_STATUS,Host Endpoint 1 Status Register"
|
|
bitfld.long 0x0 18. "RSVD_18,N/A" "0,1"
|
|
bitfld.long 0x0 17. "INI_ST,This bit shows that EP1 is initialized. If the init bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' and EP1 is initialized this bit is to '1'." "0: Not initiatialized,1: Initialized"
|
|
newline
|
|
bitfld.long 0x0 16. "VAL_DATA,This bit shows that there is valid data in the EP1 buffer." "0: Invalid data in the buffer,1: Valid data in the buffer"
|
|
hexmask.long.word 0x0 0.--8. 1. "SIZE1,These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP1 has finished."
|
|
group.long 0x408++0x7
|
|
line.long 0x0 "HOST_EP1_RW1_DR,Host Endpoint 1 Data 1-Byte Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BFDT8,Data Register for EP1 for 1-byte data"
|
|
line.long 0x4 "HOST_EP1_RW2_DR,Host Endpoint 1 Data 2-Byte Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "BFDT16,Data Register for EP1 for 2-byte data"
|
|
group.long 0x500++0x3
|
|
line.long 0x0 "HOST_EP2_CTL,Host Endpoint 2 Control Register"
|
|
bitfld.long 0x0 15. "BFINI,This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting therefore set the RST bit to '0'.." "0: Clears the initialization,1: Initializes the send/receive buffer"
|
|
bitfld.long 0x0 12. "DIR,This bit specifies the transfer direction the Endpoint support." "0: IN Endpoint,1: OUT Endpoint"
|
|
newline
|
|
bitfld.long 0x0 11. "DMAE,This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA.." "0: Releases the automatic buffer transfer mode,1: Sets the automatic buffer transfer mode"
|
|
bitfld.long 0x0 10. "NULLE,When a data transfer request in the OUT direction transmitted while packet transfer mode is set (DMAE = 1) this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer." "0: Releases the NULL automatic transfer mode,1: Sets the NULL automatic transfer mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "PKS2,This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x40."
|
|
rgroup.long 0x504++0x3
|
|
line.long 0x0 "HOST_EP2_STATUS,Host Endpoint 2 Status Register"
|
|
bitfld.long 0x0 18. "RSVD_18,N/A" "0,1"
|
|
bitfld.long 0x0 17. "INI_ST,This bit shows that EP2 is initialized. If the BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' and EP2 is initialized this bit is to '1'." "0: Not Initialized,1: Initialized"
|
|
newline
|
|
bitfld.long 0x0 16. "VAL_DATA,This bit shows that there is valid data in the EP2 buffer." "0: Invalid data in the buffer,1: Valid data in the buffer"
|
|
hexmask.long.byte 0x0 0.--6. 1. "SIZE2,These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP2 has finished."
|
|
group.long 0x508++0x7
|
|
line.long 0x0 "HOST_EP2_RW1_DR,Host Endpoint 2 Data 1-Byte Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BFDT8,Data Register for EP2 for 1-byte data."
|
|
line.long 0x4 "HOST_EP2_RW2_DR,Host Endpoint 2 Data 2-Byte Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "BFDT16,Data Register for EP2 for 2 byte data."
|
|
group.long 0x800++0x7
|
|
line.long 0x0 "HOST_LVL1_SEL,Host Interrupt Level 1 Selection Register"
|
|
bitfld.long 0x0 14.--15. "TCAN_SEL,These bits assign TCAN interrupt flag to selected interrupt signals." "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "RSVD_13_12,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "RWKIRQ_SEL,These bits assign RWKIRQ interrupt flag to selected interrupt signals." "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "URIRQ_SEL,These bits assign URIRQ interrupt flag to selected interrupt signals." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CMPIRQ_SEL,These bits assign URIRQ interrupt flag to selected interrupt signals." "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "CNNIRQ_SEL,These bits assign CNNIRQ interrupt flag to selected interrupt signals." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "DIRQ_SEL,These bits assign DIRQ interrupt flag to selected interrupt signals." "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SOFIRQ_SEL,These bits assign SOFIRQ interrupt flag to selected interrupt signals." "0: High priority interrupt,1: Medium priority interrupt,2: Low priority interrupt,3: N/A"
|
|
line.long 0x4 "HOST_LVL2_SEL,Host Interrupt Level 2 Selection Register"
|
|
bitfld.long 0x4 10.--11. "EP2_SPK_SEL,These bits assign EP2_SPK interrupt flag to selected interrupt signals." "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "EP2_DRQ_SEL,These bits assign EP2_DRQ interrupt flag to selected interrupt signals." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "EP1_SPK_SEL,These bits assign EP1_SPK interrupt flag to selected interrupt signals." "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "EP1_DRQ_SEL,These bits assign EP1_DRQ interrupt flag to selected interrupt signals." "0: High priority interrupt,1: Medium priority interrupt,2: Low priority interrupt,3: N/A"
|
|
rgroup.long 0x900++0xB
|
|
line.long 0x0 "INTR_USBHOST_CAUSE_HI,Interrupt USB Host Cause High Register"
|
|
bitfld.long 0x0 7. "TCAN_INT,TCAN interrupt" "0,1"
|
|
bitfld.long 0x0 6. "RSVD_6,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RWKIRQ_INT,RWKIRQ interrupt" "0,1"
|
|
bitfld.long 0x0 4. "URIRQ_INT,URIRQ interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CMPIRQ_INT,CMPIRQ interrupt" "0,1"
|
|
bitfld.long 0x0 2. "CNNIRQ_INT,CNNIRQ interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DIRQ_INT,DIRQ interrupt" "0,1"
|
|
bitfld.long 0x0 0. "SOFIRQ_INT,SOFIRQ interrupt" "0,1"
|
|
line.long 0x4 "INTR_USBHOST_CAUSE_MED,Interrupt USB Host Cause Medium Register"
|
|
bitfld.long 0x4 7. "TCAN_INT,TCAN interrupt" "0,1"
|
|
bitfld.long 0x4 6. "RSVD_6,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RWKIRQ_INT,RWKIRQ interrupt" "0,1"
|
|
bitfld.long 0x4 4. "URIRQ_INT,URIRQ interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CMPIRQ_INT,CMPIRQ interrupt" "0,1"
|
|
bitfld.long 0x4 2. "CNNIRQ_INT,CNNIRQ interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DIRQ_INT,DIRQ interrupt" "0,1"
|
|
bitfld.long 0x4 0. "SOFIRQ_INT,SOFIRQ interrupt" "0,1"
|
|
line.long 0x8 "INTR_USBHOST_CAUSE_LO,Interrupt USB Host Cause Low Register"
|
|
bitfld.long 0x8 7. "TCAN_INT,TCAN interrupt" "0,1"
|
|
bitfld.long 0x8 6. "RSVD_6,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "RWKIRQ_INT,RWKIRQ interrupt" "0,1"
|
|
bitfld.long 0x8 4. "URIRQ_INT,URIRQ interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CMPIRQ_INT,CMPIRQ interrupt" "0,1"
|
|
bitfld.long 0x8 2. "CNNIRQ_INT,CNNIRQ interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DIRQ_INT,DIRQ interrupt" "0,1"
|
|
bitfld.long 0x8 0. "SOFIRQ_INT,SOFIRQ interrupt" "0,1"
|
|
rgroup.long 0x920++0xB
|
|
line.long 0x0 "INTR_HOST_EP_CAUSE_HI,Interrupt USB Host Endpoint Cause High Register"
|
|
bitfld.long 0x0 5. "EP2SPK_INT,EP2SPK interrupt" "0,1"
|
|
bitfld.long 0x0 4. "EP2DRQ_INT,EP2DRQ interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "EP1SPK_INT,EP1SPK interrupt" "0,1"
|
|
bitfld.long 0x0 2. "EP1DRQ_INT,EP1DRQ interrupt" "0,1"
|
|
line.long 0x4 "INTR_HOST_EP_CAUSE_MED,Interrupt USB Host Endpoint Cause Medium Register"
|
|
bitfld.long 0x4 5. "EP2SPK_INT,EP2SPK interrupt" "0,1"
|
|
bitfld.long 0x4 4. "EP2DRQ_INT,EP2DRQ interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EP1SPK_INT,EP1SPK interrupt" "0,1"
|
|
bitfld.long 0x4 2. "EP1DRQ_INT,EP1DRQ interrupt" "0,1"
|
|
line.long 0x8 "INTR_HOST_EP_CAUSE_LO,Interrupt USB Host Endpoint Cause Low Register"
|
|
bitfld.long 0x8 5. "EP2SPK_INT,EP2SPK interrupt" "0,1"
|
|
bitfld.long 0x8 4. "EP2DRQ_INT,EP2DRQ interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "EP1SPK_INT,EP1SPK interrupt" "0,1"
|
|
bitfld.long 0x8 2. "EP1DRQ_INT,EP1DRQ interrupt" "0,1"
|
|
group.long 0x940++0xB
|
|
line.long 0x0 "INTR_USBHOST,Interrupt USB Host Register"
|
|
bitfld.long 0x0 7. "TCAN,If this bit is set to '1' it means that token sending is canceled based on the setting of the CANCEL bit of Host Control 2 Register (HOST_CTL2). When this bit is '0' it means that token sending is not canceled. Write '1' to clear a write of '0'.." "0: Does not cancel token sending,1: Cancels token sending"
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|
bitfld.long 0x0 6. "RSVD_6,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RWKIRQ,If this bit is set to '1' it means that remote Wake-up is ended. When this bit is '0' it has no meaning. Write '1' to clear a write of '0' is ignored." "0: Issues no interrupt request by restart,1: Issues an interrupt request by restart"
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|
bitfld.long 0x0 4. "URIRQ,If this bit is set to '1' it means that USB bus resetting is ended. When this bit is '0' it has no meaning. If this bit is written with '1' it is set to '0'. However if this bit is written with '0' its value is ignored." "0: Issues no interrupt request by USB bus resetting,1: Issues an interrupt request by USB bus resetting"
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|
newline
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bitfld.long 0x0 3. "CMPIRQ,If this bit is set to '1' it means that a token is completed. When this bit is '0' it has no meaning. Write '1' to clear a write of '0' is ignored." "0: Issues no interrupt request by token completion,1: Issues an interrupt request by token completion"
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|
bitfld.long 0x0 2. "CNNIRQ,If this bit is set to '1' it means that a device connection is detected. When this bit is '0' it has no meaning. Write '1' to clear a write of '0' is ignored." "0: Issues no interrupt request by detecting a..,1: Issues an interrupt request by detecting a.."
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newline
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bitfld.long 0x0 1. "DIRQ,If this bit is set to '1' it means that a device disconnection is detected. When this bit is '0' it has no meaning. Write '1' to clear a write of '0' is ignored." "0: Issues no interrupt request by detecting a..,1: Issues an interrupt request by detecting a.."
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|
bitfld.long 0x0 0. "SOFIRQ,If this bit is set to '1' it means that SOF token sending is started. When this bit is '0' it has no meaning. Write '1' to clear a write of '0' is ignored." "0: Does not issue an interrupt request by starting..,1: Issues an interrupt request by starting a SOF.."
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|
line.long 0x4 "INTR_USBHOST_SET,Interrupt USB Host Set Register"
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|
bitfld.long 0x4 7. "TCANS,This bit sets TCAN bit. If this bit is written to '1' TCAN is set to '1'. However if this bit is written with '0' its value is ignored." "0,1"
|
|
bitfld.long 0x4 6. "RSVD_6,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "RWKIRQS,This bit sets RWKIRQ bit. If this bit is written to '1' RWKIRQ is set to '1'. However if this bit is written with '0' its value is ignored." "0,1"
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|
bitfld.long 0x4 4. "URIRQS,This bit sets URIRQ bit. If this bit is written to '1' URIRQ is set to '1'. However if this bit is written with '0' its value is ignored." "0,1"
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|
newline
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bitfld.long 0x4 3. "CMPIRQS,This bit sets CMPIRQ bit. If this bit is written to '1' CMPIRQ is set to '1'. However if this bit is written with '0' its value is ignored." "0,1"
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bitfld.long 0x4 2. "CNNIRQS,This bit sets CNNIRQ bit. If this bit is written to '1' CNNIRQ is set to '1'. However if this bit is written with '0' its value is ignored." "0,1"
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|
newline
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bitfld.long 0x4 1. "DIRQS,This bit sets DIRQ bit. If this bit is written to '1' DIRQ is set to '1'. However if this bit is written with '0' its value is ignored." "0,1"
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bitfld.long 0x4 0. "SOFIRQS,This bit sets SOFIRQ bit. If this bit is written to '1' SOFIRQ is set to '1'. However if this bit is written with '0' its value is ignored." "0,1"
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|
line.long 0x8 "INTR_USBHOST_MASK,Interrupt USB Host Mask Register"
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|
bitfld.long 0x8 7. "TCANM,This bit masks the interrupt by TCAN flag." "0: Disables,1: Enables"
|
|
bitfld.long 0x8 6. "RSVD_6,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "RWKIRQM,This bit masks the interrupt by RWKIRQ flag." "0: Disables,1: Enables"
|
|
bitfld.long 0x8 4. "URIRQM,This bit masks the interrupt by URIRQ flag." "0: Disables,1: Enables"
|
|
newline
|
|
bitfld.long 0x8 3. "CMPIRQM,This bit masks the interrupt by CMPIRQ flag." "0: Disables,1: Enables"
|
|
bitfld.long 0x8 2. "CNNIRQM,This bit masks the interrupt by CNNIRQ flag." "0: Disables,1: Enables"
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|
newline
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bitfld.long 0x8 1. "DIRQM,This bit masks the interrupt by DIRQ flag." "0: Disables,1: Enables"
|
|
bitfld.long 0x8 0. "SOFIRQM,This bit masks the interrupt by SOF flag." "0: Disables,1: Enables"
|
|
rgroup.long 0x94C++0x3
|
|
line.long 0x0 "INTR_USBHOST_MASKED,Interrupt USB Host Masked Register"
|
|
bitfld.long 0x0 7. "TCANED,This bit indicates the interrupt by TCAN flag." "0: Doesn't request the interrupt by TCAN,1: Request the interrupt by TCAN"
|
|
bitfld.long 0x0 6. "RSVD_6,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RWKIRQED,This bit indicates the interrupt by RWKIRQ flag." "0: Doesn't request the interrupt by RWKIRQ,1: Request the interrupt by RWKIRQ"
|
|
bitfld.long 0x0 4. "URIRQED,This bit indicates the interrupt by URIRQ flag." "0: Doesn't request the interrupt by URIRQ,1: Request the interrupt by URIRQ"
|
|
newline
|
|
bitfld.long 0x0 3. "CMPIRQED,This bit indicates the interrupt by CMPIRQ flag." "0: Doesn't request the interrupt by CMPIRQ,1: Request the interrupt by CMPIRQ"
|
|
bitfld.long 0x0 2. "CNNIRQED,This bit indicates the interrupt by CNNIRQ flag." "0: Doesn't request the interrupt by CNNIRQ,1: Request the interrupt by CNNIRQ"
|
|
newline
|
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bitfld.long 0x0 1. "DIRQED,This bit indicates the interrupt by DIRQ flag." "0: Doesn't request the interrupt by DIRQ,1: Request the interrupt by DIRQ"
|
|
bitfld.long 0x0 0. "SOFIRQED,This bit indicates the interrupt by SOF flag." "0: Doesn't request the interrupt by SOF,1: Request the interrupt by SOF"
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|
group.long 0xA00++0xB
|
|
line.long 0x0 "INTR_HOST_EP,Interrupt USB Host Endpoint Register"
|
|
bitfld.long 0x0 5. "EP2SPK,This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS1 in the Host Endpoint 2 Control Register (HOST_EP2_CTL) when the data has been received successfully. This bit.." "0: Received data size satisfies the maximum packet..,1: Received data size does not satisfy the maximum.."
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bitfld.long 0x0 4. "EP2DRQ,This bit indicates that the EP2 packet transfer has normally ended and processing of the data is required. The DRQ bit is an interrupt cause and writing '0' is ignored. Clear the DRQ bit by writing '1'." "0: Clears the interrupt cause,1: Packet transfer normally ended"
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|
newline
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bitfld.long 0x0 3. "EP1SPK,This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 1 Control Register (HOST_EP1_CTL) when the data has been received successfully. This bit is.." "0: Received data size satisfies the maximum packet..,1: Received data size does not satisfy the maximum.."
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bitfld.long 0x0 2. "EP1DRQ,This bit indicates that the EP1 packet transfer has normally ended and processing of the data is required. The DRQ bit is an interrupt cause and writing '0' is ignored. Clear the DRQ bit by writing '1'." "0: Clears the interrupt cause,1: Packet transfer normally ended"
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|
line.long 0x4 "INTR_HOST_EP_SET,Interrupt USB Host Endpoint Set Register"
|
|
bitfld.long 0x4 5. "EP2SPKS,This bit sets EP2SPK bit. If this bit is written to '1' EP2SPK is set to '1'. However if this bit is written with '0' its value is ignored." "0,1"
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bitfld.long 0x4 4. "EP2DRQS,This bit sets EP2DRQ bit. If this bit is written to '1' EP2DRQ is set to '1'. However if this bit is written with '0' its value is ignored." "0,1"
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|
newline
|
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bitfld.long 0x4 3. "EP1SPKS,This bit sets EP1SPK bit. If this bit is written to '1' EP1SPK is set to '1'. However if this bit is written with '0' its value is ignored." "0,1"
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bitfld.long 0x4 2. "EP1DRQS,This bit sets EP1DRQ bit. If this bit is written to '1' EP1DRQ is set to '1'. However if this bit is written with '0' its value is ignored." "0,1"
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line.long 0x8 "INTR_HOST_EP_MASK,Interrupt USB Host Endpoint Mask Register"
|
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bitfld.long 0x8 5. "EP2SPKM,This bit masks the interrupt by EP2SPK flag." "0: Disables,1: Enables"
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bitfld.long 0x8 4. "EP2DRQM,This bit masks the interrupt by EP2DRQ flag." "0: Disables,1: Enables"
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|
newline
|
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bitfld.long 0x8 3. "EP1SPKM,This bit masks the interrupt by EP1SPK flag." "0: Disables,1: Enables"
|
|
bitfld.long 0x8 2. "EP1DRQM,This bit masks the interrupt by EP1DRQ flag." "0: Disables,1: Enables"
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|
rgroup.long 0xA0C++0x3
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line.long 0x0 "INTR_HOST_EP_MASKED,Interrupt USB Host Endpoint Masked Register"
|
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bitfld.long 0x0 5. "EP2SPKED,This bit indicates the interrupt by EP2SPK flag." "0: Doesn't request the interrupt by EP2SPK,1: Request the interrupt by EP2SPK"
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bitfld.long 0x0 4. "EP2DRQED,This bit indicates the interrupt by EP2DRQ flag." "0: Doesn't request the interrupt by EP2DRQ,1: Request the interrupt by EP2DRQ"
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|
newline
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bitfld.long 0x0 3. "EP1SPKED,This bit indicates the interrupt by EP1SPK flag." "0: Doesn't request the interrupt by EP1SPK,1: Request the interrupt by EP1SPK"
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bitfld.long 0x0 2. "EP1DRQED,This bit indicates the interrupt by EP1DRQ flag." "0: Doesn't request the interrupt by EP1DRQ,1: Request the interrupt by EP1DRQ"
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group.long 0xB00++0x3
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line.long 0x0 "HOST_DMA_ENBL,Host DMA Enable Register"
|
|
bitfld.long 0x0 3. "DM_EP2DRQE,This bit enables DMA Request by EP2DRQ." "0: Disable,1: Enable"
|
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bitfld.long 0x0 2. "DM_EP1DRQE,This bit enables DMA Request by EP1DRQ." "0: Disable,1: Enable"
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group.long 0xB20++0x3
|
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line.long 0x0 "HOST_EP1_BLK,Host Endpoint 1 Block Register"
|
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hexmask.long.word 0x0 16.--31. 1. "BLK_NUM,Set the total byte number for DMA transfer. If HOST_EP1_RW1_DR or HOST_EP1_RW2_DR is written the block number counter is decremented when DMAE='1'."
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group.long 0xB30++0x3
|
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line.long 0x0 "HOST_EP2_BLK,Host Endpoint 2 Block Register"
|
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hexmask.long.word 0x0 16.--31. 1. "BLK_NUM,Set the total byte number for DMA transfer. If HOST_EP2_RW1_DR or HOST_EP2_RW2_DR is written the block number counter is decremented when DMAE='1'."
|
|
tree.end
|
|
tree "USBLPM (USB Device LPM and PHY Test)"
|
|
base ad:0x403F2000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "POWER_CTL,Power Control Register"
|
|
bitfld.long 0x0 29. "ENABLE_DMO,Enables the signle ended receiver on D-." "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "ENABLE_DPO,Enables the single ended receiver on D+." "0,1"
|
|
newline
|
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bitfld.long 0x0 21. "DM_DOWN_EN,Enables the ~15k pull down on the DP." "0,1"
|
|
newline
|
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bitfld.long 0x0 20. "DM_BIG,Select the resister value if POWER_CTL.DM_EN='1'. This bit is valid in GPIO." "0: The resister value is from 900 to1575Ohmpull up..,1: The resister value is from 1425 to 3090Ohmpull.."
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newline
|
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bitfld.long 0x0 19. "DM_UP_EN,Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disabled in not GPIO." "0: Disable,1: Enable"
|
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newline
|
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bitfld.long 0x0 18. "DP_DOWN_EN,Enables the ~15k pull down on the DP." "0,1"
|
|
newline
|
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bitfld.long 0x0 17. "DP_BIG,Select the resister value if POWER_CTL.DP_EN='1'. This bit is valid in GPIO." "0: The resister value is from 900 to1575Ohmpull up..,1: The resister value is from 1425 to 3090Ohmpull.."
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|
newline
|
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bitfld.long 0x0 16. "DP_UP_EN,Enables the pull up on the DP." "0: Disable,1: Enable"
|
|
newline
|
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bitfld.long 0x0 2. "SUSPEND,Put PHY into Suspend mode. If the PHY is enabled this bit MUST be set before entering a low power mode (DeepSleep)." "0,1"
|
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group.long 0x8++0xB
|
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line.long 0x0 "USBIO_CTL,USB IO Control Register"
|
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bitfld.long 0x0 3.--5. "DM_M,The GPIO Drive Mode for DM IO pad." "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x0 0.--2. "DM_P,The GPIO Drive Mode for DP IO pad. This field only applies if USBIO_CR1.IOMODE =1. Data comes from the corresponding GPIO.DR register." "0: Mode 0: Output buffer off (high Z). Input buffer..,1: Mode 1: Output buffer off (high Z). Input buffer..,?,?,?,?,?,?"
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line.long 0x4 "FLOW_CTL,Flow Control Register"
|
|
bitfld.long 0x4 7. "EP8_ERR_RESP,End Point 8 error response" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "EP7_ERR_RESP,End Point 7 error response" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "EP6_ERR_RESP,End Point 6 error response" "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "EP5_ERR_RESP,End Point 5 error response" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "EP4_ERR_RESP,End Point 4 error response" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "EP3_ERR_RESP,End Point 3 error response" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "EP2_ERR_RESP,End Point 2 error response" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "EP1_ERR_RESP,End Point 1 error response" "0: do nothing,1: if this is an IN EP and an underflow occurs then.."
|
|
line.long 0x8 "LPM_CTL,LPM Control Register"
|
|
bitfld.long 0x8 4. "SUB_RESP,Enable a STALL response for all undefined SubPIDs i.e. other than LPM (0011b). If not enabled then there will be no response (Error) for the undefined SubPIDs." "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "NYET_EN,Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0)." "0: a LPM token will get an NAK response,1: a LPM token will get a NYET response"
|
|
newline
|
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bitfld.long 0x8 1. "LPM_ACK_RESP,LPM ACK response enable (if LPM_EN=1) to allow firmware to refuse a low power request" "0: a LPM token will get a NYET or NAK,1: a LPM token will get an ACK response and the.."
|
|
newline
|
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bitfld.long 0x8 0. "LPM_EN,LPM enable" "0: Disabled,1: Enable"
|
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rgroup.long 0x14++0x3
|
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line.long 0x0 "LPM_STAT,LPM Status register"
|
|
bitfld.long 0x0 4. "LPM_REMOTEWAKE,0: Device is prohibited from initiating a remote wake" "0: Device is prohibited from initiating a remote wake,1: Device is allow to wake the host"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "LPM_BESL,Best Effort Service Latency"
|
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group.long 0x20++0xB
|
|
line.long 0x0 "INTR_SIE,USB SOF. BUS RESET and EP0 Interrupt Status"
|
|
bitfld.long 0x0 4. "RESUME_INTR,Interrupt status for Resume" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "LPM_INTR,Interrupt status for LPM (Link Power Management L1 entry)" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EP0_INTR,Interrupt status for EP0" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "BUS_RESET_INTR,Interrupt status for BUS RESET" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "SOF_INTR,Interrupt status for USB SOF" "0,1"
|
|
line.long 0x4 "INTR_SIE_SET,USB SOF. BUS RESET and EP0 Interrupt Set"
|
|
bitfld.long 0x4 4. "RESUME_INTR_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "LPM_INTR_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "EP0_INTR_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "BUS_RESET_INTR_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "SOF_INTR_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_SIE_MASK,USB SOF. BUS RESET and EP0 Interrupt Mask"
|
|
bitfld.long 0x8 4. "RESUME_INTR_MASK,Set to 1 to enable interrupt corresponding to interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x8 3. "LPM_INTR_MASK,Set to 1 to enable interrupt corresponding to interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "EP0_INTR_MASK,Set to 1 to enable interrupt corresponding to interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "BUS_RESET_INTR_MASK,Set to 1 to enable interrupt corresponding to interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "SOF_INTR_MASK,Set to 1 to enable interrupt corresponding to interrupt request register" "0,1"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "INTR_SIE_MASKED,USB SOF. BUS RESET and EP0 Interrupt Masked"
|
|
bitfld.long 0x0 4. "RESUME_INTR_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "LPM_INTR_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EP0_INTR_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BUS_RESET_INTR_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "SOF_INTR_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "INTR_LVL_SEL,Select interrupt level for each interrupt source"
|
|
bitfld.long 0x0 30.--31. "EP8_LVL_SEL,EP8 Interrupt level select" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x0 28.--29. "EP7_LVL_SEL,EP7 Interrupt level select" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x0 26.--27. "EP6_LVL_SEL,EP6 Interrupt level select" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x0 24.--25. "EP5_LVL_SEL,EP5 Interrupt level select" "0,1,2,3"
|
|
newline
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bitfld.long 0x0 22.--23. "EP4_LVL_SEL,EP4 Interrupt level select" "0,1,2,3"
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bitfld.long 0x0 20.--21. "EP3_LVL_SEL,EP3 Interrupt level select" "0,1,2,3"
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bitfld.long 0x0 18.--19. "EP2_LVL_SEL,EP2 Interrupt level select" "0,1,2,3"
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bitfld.long 0x0 16.--17. "EP1_LVL_SEL,EP1 Interrupt level select" "0,1,2,3"
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bitfld.long 0x0 14.--15. "ARB_EP_LVL_SEL,Arbiter Endpoint Interrupt level select" "0,1,2,3"
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bitfld.long 0x0 8.--9. "RESUME_LVL_SEL,Resume Interrupt level select" "0,1,2,3"
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bitfld.long 0x0 6.--7. "LPM_LVL_SEL,LPM Interrupt level select" "0,1,2,3"
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bitfld.long 0x0 4.--5. "EP0_LVL_SEL,EP0 Interrupt level select" "0,1,2,3"
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bitfld.long 0x0 2.--3. "BUS_RESET_LVL_SEL,BUS RESET Interrupt level select" "0,1,2,3"
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bitfld.long 0x0 0.--1. "SOF_LVL_SEL,USB SOF Interrupt level select" "0: High priority interrupt,1: Medium priority interrupt,2: Low priority interrupt,3: illegal"
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rgroup.long 0x34++0xB
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line.long 0x0 "INTR_CAUSE_HI,High priority interrupt Cause register"
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bitfld.long 0x0 15. "EP8_INTR,EP8 Interrupt" "0,1"
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bitfld.long 0x0 14. "EP7_INTR,EP7 Interrupt" "0,1"
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bitfld.long 0x0 13. "EP6_INTR,EP6 Interrupt" "0,1"
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bitfld.long 0x0 12. "EP5_INTR,EP5 Interrupt" "0,1"
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bitfld.long 0x0 11. "EP4_INTR,EP4 Interrupt" "0,1"
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bitfld.long 0x0 10. "EP3_INTR,EP3 Interrupt" "0,1"
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bitfld.long 0x0 9. "EP2_INTR,EP2 Interrupt" "0,1"
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bitfld.long 0x0 8. "EP1_INTR,EP1 Interrupt" "0,1"
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bitfld.long 0x0 7. "ARB_EP_INTR,Arbiter Endpoint Interrupt" "0,1"
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bitfld.long 0x0 4. "RESUME_INTR,Resume Interrupt" "0,1"
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newline
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bitfld.long 0x0 3. "LPM_INTR,LPM Interrupt" "0,1"
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bitfld.long 0x0 2. "EP0_INTR,EP0 Interrupt" "0,1"
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bitfld.long 0x0 1. "BUS_RESET_INTR,BUS RESET Interrupt" "0,1"
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bitfld.long 0x0 0. "SOF_INTR,USB SOF Interrupt" "0,1"
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line.long 0x4 "INTR_CAUSE_MED,Medium priority interrupt Cause register"
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bitfld.long 0x4 15. "EP8_INTR,EP8 Interrupt" "0,1"
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newline
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bitfld.long 0x4 14. "EP7_INTR,EP7 Interrupt" "0,1"
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bitfld.long 0x4 13. "EP6_INTR,EP6 Interrupt" "0,1"
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bitfld.long 0x4 12. "EP5_INTR,EP5 Interrupt" "0,1"
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bitfld.long 0x4 11. "EP4_INTR,EP4 Interrupt" "0,1"
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bitfld.long 0x4 10. "EP3_INTR,EP3 Interrupt" "0,1"
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bitfld.long 0x4 9. "EP2_INTR,EP2 Interrupt" "0,1"
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bitfld.long 0x4 8. "EP1_INTR,EP1 Interrupt" "0,1"
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bitfld.long 0x4 7. "ARB_EP_INTR,Arbiter Endpoint Interrupt" "0,1"
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bitfld.long 0x4 4. "RESUME_INTR,Resume Interrupt" "0,1"
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bitfld.long 0x4 3. "LPM_INTR,LPM Interrupt" "0,1"
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bitfld.long 0x4 2. "EP0_INTR,EP0 Interrupt" "0,1"
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bitfld.long 0x4 1. "BUS_RESET_INTR,BUS RESET Interrupt" "0,1"
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bitfld.long 0x4 0. "SOF_INTR,USB SOF Interrupt" "0,1"
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line.long 0x8 "INTR_CAUSE_LO,Low priority interrupt Cause register"
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bitfld.long 0x8 15. "EP8_INTR,EP8 Interrupt" "0,1"
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newline
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bitfld.long 0x8 14. "EP7_INTR,EP7 Interrupt" "0,1"
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newline
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bitfld.long 0x8 13. "EP6_INTR,EP6 Interrupt" "0,1"
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bitfld.long 0x8 12. "EP5_INTR,EP5 Interrupt" "0,1"
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bitfld.long 0x8 11. "EP4_INTR,EP4 Interrupt" "0,1"
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newline
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bitfld.long 0x8 10. "EP3_INTR,EP3 Interrupt" "0,1"
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bitfld.long 0x8 9. "EP2_INTR,EP2 Interrupt" "0,1"
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bitfld.long 0x8 8. "EP1_INTR,EP1 Interrupt" "0,1"
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bitfld.long 0x8 7. "ARB_EP_INTR,Arbiter Endpoint Interrupt" "0,1"
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bitfld.long 0x8 4. "RESUME_INTR,Resume Interrupt" "0,1"
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newline
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bitfld.long 0x8 3. "LPM_INTR,LPM Interrupt" "0,1"
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bitfld.long 0x8 2. "EP0_INTR,EP0 Interrupt" "0,1"
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bitfld.long 0x8 1. "BUS_RESET_INTR,BUS RESET Interrupt" "0,1"
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bitfld.long 0x8 0. "SOF_INTR,USB SOF Interrupt" "0,1"
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group.long 0x70++0x3
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line.long 0x0 "DFT_CTL,DFT control"
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bitfld.long 0x0 3.--4. "DDFT_IN_SEL,DDFT input select signal" "0: Nothing connected output 0,1: GPIO input of DP,2: GPIO input of DM,?"
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newline
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bitfld.long 0x0 0.--2. "DDFT_OUT_SEL,DDFT output select signal" "0: Nothing connected output 0,1: Single Ended output of DP,2: Single Ended output of DM,3: Output Enable,4: Differential Receiver output,5: GPIO output of DP,6: GPIO output of DM,?"
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tree.end
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tree.end
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newline
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AUTOINDENT.OFF
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