10195 lines
1.3 MiB
10195 lines
1.3 MiB
; --------------------------------------------------------------------------------
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; @Title: M2A23 On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2025-06-02 NEJ
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; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
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; @Doc: Generated (TRACE32, build: 180251.), based on:
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; M2A23.svd (Ver. 1.0)
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; @Core: Cortex-M23
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; @Chip: M2A23YG5AC, M2A23LG5AC, M2A23SG5AC, M2A23YE5AC, M2A23LE5AC,
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; M2A23SE5AC, M2A23YD5AC, M2A23LD5AC, M2A23SD5AC
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; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perm2a23.per 19571 2025-06-03 12:05:43Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M23)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 29. " EXTEXCLALL ,LDREX and STREX instructions use the Global Exclusive Monitor" "Only on Shared regions,Always"
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newline
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group.long 0x10++0x03
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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newline
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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group.long 0x14++0x07
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line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x04 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " CURRENT ,Current counter value"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/o Main Extension,Reserved,Reserved,Reserved"
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newline
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xD20=Cortex-M23"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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group.long 0xD04++0x13
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET ,On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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newline
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bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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newline
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
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newline
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bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
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newline
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bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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newline
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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newline
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bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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newline
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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group.long 0xD1C++0x0B
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x00 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x04 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
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hexmask.long.byte 0x04 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
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hexmask.long.byte 0x04 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
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bitfld.long 0x08 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
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bitfld.long 0x08 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
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newline
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bitfld.long 0x08 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
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bitfld.long 0x08 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
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bitfld.long 0x08 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
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newline
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bitfld.long 0x08 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
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bitfld.long 0x08 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
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bitfld.long 0x08 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
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newline
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bitfld.long 0x08 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
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bitfld.long 0x08 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
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bitfld.long 0x08 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
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newline
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bitfld.long 0x08 8. " MONITORACT ,Monitor exception status" "Not active,Active"
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bitfld.long 0x08 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
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bitfld.long 0x08 5. " NMIACT ,NMI exception status" "Not active,Active"
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newline
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bitfld.long 0x08 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
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bitfld.long 0x08 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
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bitfld.long 0x08 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
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newline
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bitfld.long 0x08 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
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bitfld.long 0x08 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
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tree "Memory System"
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width 10.
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rgroup.long 0xD78++0x0B
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line.long 0x00 "CLIDR,Cache Level ID Register"
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bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
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bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
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bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
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textline " "
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bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
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line.long 0x04 "CTR,Cache Type Register"
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bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,?..."
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bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,?..."
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textline " "
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bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "CCSIDR,Cache Size ID Register"
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bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
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bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
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bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
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textline " "
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bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
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hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
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hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
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textline " "
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bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
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group.long 0xD84++0x03
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line.long 0x00 "CSSELR,Cache Size Selection Register"
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bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
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bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
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wgroup.long 0xF50++0x03
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line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
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wgroup.long 0xF58++0x23
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line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
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line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
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line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
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hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
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line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
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line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
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hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
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line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
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hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
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tree.end
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width 11.
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tree "CoreSight Identification Registers"
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rgroup.long 0xFE0++0x0F
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line.long 0x00 "DPIDR0,Peripheral ID0"
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hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
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line.long 0x04 "DPIDR1,Peripheral ID1"
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hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
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hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
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line.long 0x08 "DPIDR2,Peripheral ID2"
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hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
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bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
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hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
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line.long 0x0c "DPIDR3,Peripheral ID3"
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hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
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hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
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rgroup.long 0xFD0++0x03
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line.long 0x00 "PID4,Peripheral Identification Register 4"
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hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
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hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
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rgroup.long 0xFF0++0x0F
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line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
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hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
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line.long 0x04 "DCIDR1,Component ID1"
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hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
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hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
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line.long 0x08 "DCIDR2,Component ID2"
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hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
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line.long 0x0C "DCIDR3,Component ID3"
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hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
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tree.end
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width 0x0B
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,,,,4,,,,8,,,,,,,,16,?..."
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bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
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bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
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bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
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newline
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bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
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hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
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bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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newline
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
endif
|
|
tree.end
|
|
newline
|
|
group.long 0xDC0++0x07
|
|
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Memory attribute encoding for MPU regions with an AttrIndex of 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Memory attribute encoding for MPU regions with an AttrIndex of 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Memory attribute encoding for MPU regions with an AttrIndex of 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Memory attribute encoding for MPU regions with an AttrIndex of 0"
|
|
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " ATTR7 ,Memory attribute encoding for MPU regions with an AttrIndex of 7"
|
|
hexmask.long.byte 0x04 16.--23. 1. " ATTR6 ,Memory attribute encoding for MPU regions with an AttrIndex of 6"
|
|
hexmask.long.byte 0x04 8.--15. 1. " ATTR5 ,Memory attribute encoding for MPU regions with an AttrIndex of 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ATTR4 ,Memory attribute encoding for MPU regions with an AttrIndex of 4"
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Security Attribution Unit (SAU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SAU_CTRL,SAU Control Register"
|
|
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
|
|
rgroup.long 0xDD4++0x03
|
|
line.long 0x00 "SAU_TYPE,SAU Type Register"
|
|
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,,,,4,,,,8,?..."
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SAU_RNR,SAU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
|
|
tree.close "SAU regions"
|
|
if ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x0
|
|
group.long 0xDDC++0x03 "Region 0"
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x1
|
|
group.long 0xDDC++0x03 "Region 1"
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x2
|
|
group.long 0xDDC++0x03 "Region 2"
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x3
|
|
group.long 0xDDC++0x03 "Region 3"
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x4
|
|
group.long 0xDDC++0x03 "Region 4"
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x5
|
|
group.long 0xDDC++0x03 "Region 5"
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x6
|
|
group.long 0xDDC++0x03 "Region 6"
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x7
|
|
group.long 0xDDC++0x03 "Region 7"
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
endif
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hgroup.long 0xDDC++0x03 "Region 8 (not accessible)"
|
|
saveout 0xDD8 %l 0x8
|
|
hide.long 0x00 "SAU_RBAR8,SAU Region Base Address Register 8"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x8
|
|
hide.long 0x00 "SAU_RLAR8,SAU Region Limit Address Register 8"
|
|
hgroup.long 0xDDC++0x03 "Region 9 (not accessible)"
|
|
saveout 0xDD8 %l 0x9
|
|
hide.long 0x00 "SAU_RBAR9,SAU Region Base Address Register 9"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x9
|
|
hide.long 0x00 "SAU_RLAR9,SAU Region Limit Address Register 9"
|
|
hgroup.long 0xDDC++0x03 "Region 10 (not accessible)"
|
|
saveout 0xDD8 %l 0xA
|
|
hide.long 0x00 "SAU_RBAR10,SAU Region Base Address Register 10"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xA
|
|
hide.long 0x00 "SAU_RLAR10,SAU Region Limit Address Register 10"
|
|
hgroup.long 0xDDC++0x03 "Region 11 (not accessible)"
|
|
saveout 0xDD8 %l 0xB
|
|
hide.long 0x00 "SAU_RBAR11,SAU Region Base Address Register 11"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xB
|
|
hide.long 0x00 "SAU_RLAR11,SAU Region Limit Address Register 11"
|
|
hgroup.long 0xDDC++0x03 "Region 12 (not accessible)"
|
|
saveout 0xDD8 %l 0xC
|
|
hide.long 0x00 "SAU_RBAR12,SAU Region Base Address Register 12"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xC
|
|
hide.long 0x00 "SAU_RLAR12,SAU Region Limit Address Register 12"
|
|
hgroup.long 0xDDC++0x03 "Region 13 (not accessible)"
|
|
saveout 0xDD8 %l 0xD
|
|
hide.long 0x00 "SAU_RBAR13,SAU Region Base Address Register 13"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xD
|
|
hide.long 0x00 "SAU_RLAR13,SAU Region Limit Address Register 13"
|
|
hgroup.long 0xDDC++0x03 "Region 14 (not accessible)"
|
|
saveout 0xDD8 %l 0xE
|
|
hide.long 0x00 "SAU_RBAR14,SAU Region Base Address Register 14"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xE
|
|
hide.long 0x00 "SAU_RLAR14,SAU Region Limit Address Register 14"
|
|
hgroup.long 0xDDC++0x03 "Region 15 (not accessible)"
|
|
saveout 0xDD8 %l 0xF
|
|
hide.long 0x00 "SAU_RBAR15,SAU Region Base Address Register 15"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xF
|
|
hide.long 0x00 "SAU_RLAR15,SAU Region Limit Address Register 15"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-239,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 24.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x10C++0x03
|
|
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x118++0x03
|
|
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x11C++0x03
|
|
hide.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 24.
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 11.
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE0,Active Bit Register 0"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Target Non-Secure Registers"
|
|
width 13.
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
|
|
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
|
|
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
|
|
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
|
|
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
|
|
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
|
|
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x420++0x1F
|
|
line.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0xC "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x1C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
else
|
|
hgroup.long 0x420++0x1F
|
|
hide.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hide.long 0xC "IPR11,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR15,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x440++0x1F
|
|
line.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0xC "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x1C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
else
|
|
hgroup.long 0x440++0x1F
|
|
hide.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hide.long 0xC "IPR19,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR23,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x460++0x1F
|
|
line.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0xC "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x1C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
else
|
|
hgroup.long 0x460++0x1F
|
|
hide.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hide.long 0xC "IPR27,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR31,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x480++0x1F
|
|
line.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0xC "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x1C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
else
|
|
hgroup.long 0x480++0x1F
|
|
hide.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hide.long 0xC "IPR35,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR39,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x4A0++0x1F
|
|
line.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0x1C "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
else
|
|
hgroup.long 0x4A0++0x1F
|
|
hide.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xC "IPR43,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR47,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x4C0++0x1F
|
|
line.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0x1C "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
else
|
|
hgroup.long 0x4C0++0x1F
|
|
hide.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xC "IPR51,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR55,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x4E0++0x0F
|
|
line.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x4E0++0x0F
|
|
hide.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
width 13.
|
|
group.long 0xE04++0x07
|
|
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
|
|
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
|
|
textline " "
|
|
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
|
|
bitfld.long 0x04 17. " CDSKEY ,CDS write-enable key" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
|
|
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
|
|
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB8++0x03
|
|
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
rbitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
newline
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
tree "CoreSight Identification Registers"
|
|
width 12.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "FP_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "FP_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "FP_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "FP_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "FP_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "FP_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0C "FP_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 16.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
bitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,Base instruction overhead counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store overhead counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
endif
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
endif
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
endif
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)==0x1)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x4)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xC)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xF)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
endif
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION4,DWT Function Register 4"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)==0x1)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x4)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xC)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xF)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
endif
|
|
group.long (0x70+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION5,DWT Function Register 5"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)==0x1)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x4)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xC)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xF)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
endif
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION6,DWT Function Register 6"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)==0x1)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x4)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xC)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xF)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
endif
|
|
group.long (0x90+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION7,DWT Function Register 7"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)==0x1)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x4)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xC)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xF)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
endif
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION8,DWT Function Register 8"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)==0x1)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x4)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xC)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xF)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
endif
|
|
group.long (0xB0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION9,DWT Function Register 9"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)==0x1)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x4)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xC)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xF)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
endif
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION10,DWT Function Register 10"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)==0x1)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x4)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xC)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xF)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
endif
|
|
group.long (0xD0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION11,DWT Function Register 11"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)==0x1)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x4)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xC)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xF)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
endif
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION12,DWT Function Register 12"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)==0x1)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x4)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xC)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xF)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
endif
|
|
group.long (0xF0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION13,DWT Function Register 13"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)==0x1)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x4)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xC)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xF)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
endif
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION14,DWT Function Register 14"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)==0x1)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x4)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xC)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xF)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
endif
|
|
group.long (0x110+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION15,DWT Function Register 15"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
tree "CoreSight Identification Registers"
|
|
width 13.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DWT_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DWT_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "DWT_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ACMP (Analog Comparator Controller)"
|
|
base ad:0x40045000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "ACMP_CTL0,Analog Comparator 0 Control Register"
|
|
bitfld.long 0x0 30. "HYSBYPASS,Hysteresis Adjust Function Selection" "0: Enable adjust function,1: Bypass adjust function"
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|
bitfld.long 0x0 24.--25. "HYSSEL,Hysteresis Mode Selection" "0: Hysteresis is 0mV,?,?,?"
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newline
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bitfld.long 0x0 23. "ADCEN,ADC Request Enable Bit" "0: ADC Request Disabled,1: ADC Request Selected"
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bitfld.long 0x0 22. "PDMAEN,PDMA Request Enable Bit" "0: PDMA Request Disabled,1: PDMA Request Selected"
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newline
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bitfld.long 0x0 20.--21. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF0 will be set to 1 when comparator output edge condition is detected." "0: Rising edge or falling edge,1: Rising edge,?,?"
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bitfld.long 0x0 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode Selected"
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newline
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bitfld.long 0x0 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled"
|
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bitfld.long 0x0 16. "WKEN,Power-down Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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newline
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bitfld.long 0x0 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP0 output is sampled 1 consecutive PCLK,?,?,?,?,?,?"
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bitfld.long 0x0 12. "OUTSEL,Comparator Output Select" "0: Comparator 0 output to ACMP0_O pin is unfiltered..,1: Comparator 0 output to ACMP0_O pin is from.."
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newline
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bitfld.long 0x0 8.--10. "POSSEL,Comparator Positive Input Selection" "0: All positive input disabled,1: Input from ACMP0_P0,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "NEGSEL,Comparator Negative Input Selection" "0: All negative input disbaled,1: ACMP0_N0,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 3. "ACMPOINV,Comparator Output Inverse" "0: Comparator 0 output inverse Disabled,1: Comparator 0 output inverse Enabled"
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bitfld.long 0x0 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 0 interrupt Disabled,1: Comparator 0 interrupt Enabled. If WKEN.."
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newline
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bitfld.long 0x0 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 0 Disabled,1: Comparator 0 Enabled"
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line.long 0x4 "ACMP_CTL1,Analog Comparator 1 Control Register"
|
|
bitfld.long 0x4 24.--25. "HYSSEL,Hysteresis Mode Selection" "0: Hysteresis is 0mV,?,?,?"
|
|
bitfld.long 0x4 23. "ADCEN,ADC Request Enable Bit" "0: ADC Request Disabled,1: ADC Request Selected"
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newline
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bitfld.long 0x4 22. "PDMAEN,PDMA Request Enable Bit" "0: PDMA Request Disabled,1: PDMA Request Selected"
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bitfld.long 0x4 20.--21. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF0 will be set to 1 when comparator output edge condition is detected." "0: Rising edge or falling edge,1: Rising edge,?,?"
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newline
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bitfld.long 0x4 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode Selected"
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bitfld.long 0x4 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled"
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newline
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bitfld.long 0x4 16. "WKEN,Power-down Wakeup Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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bitfld.long 0x4 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP1 output is sampled 1 consecutive PCLK,?,?,?,?,?,?"
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newline
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bitfld.long 0x4 12. "OUTSEL,Comparator Output Select" "0: Comparator 1 output to ACMP1_O pin is unfiltered..,1: Comparator 1 output to ACMP1_O pin is from.."
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bitfld.long 0x4 8.--10. "POSSEL,Comparator Positive Input Selection" "0: All positive input disabled,1: Input from ACMP1_P0,?,?,?,?,?,?"
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newline
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bitfld.long 0x4 4.--6. "NEGSEL,Comparator Negative Input Selection" "0: All negative input disbaled,1: ACMP1_N0,?,?,?,?,?,?"
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bitfld.long 0x4 3. "ACMPOINV,Comparator Output Inverse Control" "0: Comparator 1 output inverse Disabled,1: Comparator 1 output inverse Enabled"
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newline
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bitfld.long 0x4 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 1 interrupt Disabled,1: Comparator 1 interrupt Enabled. If WKEN.."
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bitfld.long 0x4 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 1 Disabled,1: Comparator 1 Enabled"
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line.long 0x8 "ACMP_STATUS,Analog Comparator Status Register"
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bitfld.long 0x8 16. "ACMPWO,Comparator Window Output\nThis bit shows the output status of window compare mode" "0: The positive input voltage is outside the window,1: The positive input voltage is in the window"
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bitfld.long 0x8 13. "ACMPS1,Comparator 1 Status\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0." "0,1"
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newline
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bitfld.long 0x8 12. "ACMPS0,Comparator 0 Status \nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0." "0,1"
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bitfld.long 0x8 9. "WKIF1,Comparator 1 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP1 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0." "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
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newline
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bitfld.long 0x8 8. "WKIF0,Comparator 0 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP0 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0." "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
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bitfld.long 0x8 5. "ACMPO1,Comparator 1 Output\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0." "0,1"
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newline
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bitfld.long 0x8 4. "ACMPO0,Comparator 0 Output\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0." "0,1"
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bitfld.long 0x8 1. "ACMPIF1,Comparator 1 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[21:20]) is detected on comparator 1 output. This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.\nNote: Write 1 to clear.." "0,1"
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newline
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bitfld.long 0x8 0. "ACMPIF0,Comparator 0 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[21:20]) is detected on comparator 0 output. This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.\nNote: Write 1 to.." "0,1"
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line.long 0xC "ACMP_VREF,Analog Comparator Reference Voltage Control Register"
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bitfld.long 0xC 8. "CRVEN,CRV Function Enable Bit" "0: CRV function Disabled,1: CRV function Enabled"
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bitfld.long 0xC 6. "CRVSSEL,CRV Source Voltage Selection" "0: AVDD is selected as CRV source voltage,1: Internal VREF is selected as as CRV source voltage"
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newline
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hexmask.long.byte 0xC 0.--3. 1. "CRVCTL,Comparator Reference Voltage Setting"
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tree.end
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tree "ADC (Analog-to-Digital Converter)"
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base ad:0x40043000
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rgroup.long 0x0++0x3F
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line.long 0x0 "ADC_ADDR0,ADC Data Register 0"
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bitfld.long 0x0 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x0 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x4 "ADC_ADDR1,ADC Data Register 1"
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bitfld.long 0x4 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x4 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x4 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x8 "ADC_ADDR2,ADC Data Register 2"
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bitfld.long 0x8 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x8 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x8 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0xC "ADC_ADDR3,ADC Data Register 3"
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bitfld.long 0xC 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0xC 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0xC 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x10 "ADC_ADDR4,ADC Data Register 4"
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bitfld.long 0x10 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x10 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x10 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x14 "ADC_ADDR5,ADC Data Register 5"
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bitfld.long 0x14 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x14 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x14 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x18 "ADC_ADDR6,ADC Data Register 6"
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bitfld.long 0x18 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x18 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x18 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x1C "ADC_ADDR7,ADC Data Register 7"
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bitfld.long 0x1C 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x1C 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x1C 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x20 "ADC_ADDR8,ADC Data Register 8"
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bitfld.long 0x20 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x20 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x20 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
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line.long 0x24 "ADC_ADDR9,ADC Data Register 9"
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bitfld.long 0x24 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x24 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x24 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
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line.long 0x28 "ADC_ADDR10,ADC Data Register 10"
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bitfld.long 0x28 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x28 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x28 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
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line.long 0x2C "ADC_ADDR11,ADC Data Register 11"
|
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bitfld.long 0x2C 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x2C 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
|
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hexmask.long.word 0x2C 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
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line.long 0x30 "ADC_ADDR12,ADC Data Register 12"
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bitfld.long 0x30 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x30 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x30 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
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line.long 0x34 "ADC_ADDR13,ADC Data Register 13"
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bitfld.long 0x34 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x34 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x34 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
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line.long 0x38 "ADC_ADDR14,ADC Data Register 14"
|
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bitfld.long 0x38 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x38 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
|
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hexmask.long.word 0x38 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
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line.long 0x3C "ADC_ADDR15,ADC Data Register 15"
|
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bitfld.long 0x3C 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x3C 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x3C 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
rgroup.long 0x74++0xB
|
|
line.long 0x0 "ADC_ADDR29,ADC Data Register 29"
|
|
bitfld.long 0x0 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x0 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
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line.long 0x4 "ADC_ADDR30,ADC Data Register 30"
|
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bitfld.long 0x4 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x4 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x4 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0x8 "ADC_ADDR31,ADC Data Register 31"
|
|
bitfld.long 0x8 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x8 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x8 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
group.long 0x80++0x13
|
|
line.long 0x0 "ADC_ADCR,ADC Control Register"
|
|
bitfld.long 0x0 31. "DMOF,Differential Input Mode Output Format\nIf user enables differential input mode the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format)." "0: A/D Conversion result will be filled in RSLT at..,1: A/D Conversion result will be filled in RSLT at.."
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hexmask.long.byte 0x0 16.--23. 1. "EXTSMPT,ADC Internal Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend ADC sampling time after trigger source is.."
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newline
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hexmask.long.byte 0x0 12.--15. 1. "TRGS,Hardware Trigger Source\nEnable or disable triggering of A/D conversion by external STADC pin PWM trigger BPWM trigger Timer trigger and ACMP trigger. If external trigger is selected the ADST bit can be set to 1 by the selected hardware trigger.."
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bitfld.long 0x0 11. "ADST,A/D Conversion Start\nADST bit can be set to 1 from four sources: software external pin STADC PWM trigger and Timer trigger. ADST bit will be cleared to 0 by hardware automatically at the ends of Single mode and Single-cycle Scan mode. In.." "0: Conversion stops and A/D converter enters idle..,1: Conversion starts"
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bitfld.long 0x0 10. "DIFFEN,Differential Input Mode Control\nNote: In Differential Input mode only one pair of differential channel and ADC_CH0 needs to be enabled in ADC_ADCHER register. The conversion result will be placed to the corresponding data register of the.." "0: Single-end analog input mode,1: Differential analog input mode"
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bitfld.long 0x0 9. "PTEN,PDMA Transfer Enable Bit\nWhen A/D conversion is completed the converted data is loaded into ADC_ADDR0~15 ADC_ADDR29~ADC_ADDR30 registers. Software can enable this bit to generate a PDMA data transfer request." "0: PDMA data transfer Disabled,1: PDMA data transfer in ADC_ADDR0~15.."
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bitfld.long 0x0 6.--7. "TRGCOND,External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger. If edge trigger condition is selected the STADC pin must be kept.." "0: Low level,1: High level,?,?"
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bitfld.long 0x0 2.--3. "ADMD,A/D Converter Operation Mode Control\nNote 1: When changing the operation mode software should clear ADST bit first.\nNote 2: In Burst mode the A/D result data is always at ADC Data Register 0." "0: Single conversion,1: When changing the operation mode,2: In Burst mode,?"
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bitfld.long 0x0 1. "ADIE,A/D Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADIE bit is set to 1." "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled"
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bitfld.long 0x0 0. "ADEN,A/D Converter Enable Bit\nNote: Before starting A/D conversion function this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption." "0: A/D converter Disabled,1: A/D converter Enabled"
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line.long 0x4 "ADC_ADCHER,ADC Channel Enable Register"
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hexmask.long 0x4 0.--31. 1. "CHEN,Analog Input Channel Enable Control\nSet ADC_ADCHER[15:0] bits to enable the corresponding analog input channel 15 ~ 0. If DIFFEN (ADC_ADCR[10]) bit is set to 1 only the channel 0 needs to be enabled.\nBesides setting ADC_ADCHER[29] to.."
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line.long 0x8 "ADC_ADCMPR0,ADC Compare Register 0"
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hexmask.long.word 0x8 16.--27. 1. "CMPD,Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: CMPD bits should be filled in unsigned format (straight binary format)."
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bitfld.long 0x8 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only presented in ADC_ADCMPR0 register." "0: Compare Window Mode Disabled,1: Compare Window Mode Enabled"
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hexmask.long.byte 0x8 8.--11. 1. "CMPMATCNT,Compare Match Count"
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hexmask.long.byte 0x8 3.--7. 1. "CMPCH,Compare Channel Selection"
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bitfld.long 0x8 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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bitfld.long 0x8 1. "CMPIE,Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x8 0. "CMPEN,Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPD with specified channel conversion result when converted data is loaded into ADC_ADDRx register." "0: Compare function Disabled,1: Compare function Enabled"
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line.long 0xC "ADC_ADCMPR1,ADC Compare Register 1"
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hexmask.long.word 0xC 16.--27. 1. "CMPD,Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: CMPD bits should be filled in unsigned format (straight binary format)."
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bitfld.long 0xC 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only presented in ADC_ADCMPR0 register." "0: Compare Window Mode Disabled,1: Compare Window Mode Enabled"
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hexmask.long.byte 0xC 8.--11. 1. "CMPMATCNT,Compare Match Count"
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hexmask.long.byte 0xC 3.--7. 1. "CMPCH,Compare Channel Selection"
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bitfld.long 0xC 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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bitfld.long 0xC 1. "CMPIE,Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0xC 0. "CMPEN,Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPD with specified channel conversion result when converted data is loaded into ADC_ADDRx register." "0: Compare function Disabled,1: Compare function Enabled"
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line.long 0x10 "ADC_ADSR0,ADC Status Register0"
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hexmask.long.byte 0x10 27.--31. 1. "CHANNEL,Current Conversion Channel (Read Only)"
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rbitfld.long 0x10 16. "OVERRUNF,Overrun Flag (Read Only)\nIf any of OVERRUN (ADC_ADDRx[16]) is set this flag will be set to 1.\nNote: When ADC is in burst mode and the FIFO is overrun this flag will be set to 1." "0,1"
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rbitfld.long 0x10 8. "VALIDF,Data Valid Flag (Read Only)\nIf any of VALID (ADC_ADDRx[17]) is set this flag will be set to 1.\nNote: When ADC is in burst mode and any conversion result is valid this flag will be set to 1." "0,1"
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rbitfld.long 0x10 7. "BUSY,BUSY/IDLE (Read Only)\nThis bit is a mirror of ADST bit in ADC_ADCR register." "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
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bitfld.long 0x10 2. "CMPF1,Compare Flag 1\nWhen the A/D conversion result of the selected channel meets setting condition in ADC_ADCMPR1 register then this bit is set to 1; it is cleared by writing 1 to it" "0: Conversion result in ADC_ADDRx did not meet..,1: Conversion result in ADC_ADDRx met ADC_ADCMPR1.."
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bitfld.long 0x10 1. "CMPF0,Compare Flag 0\nWhen the A/D conversion result of the selected channel meets setting condition in ADC_ADCMPR0 register then this bit is set to 1. This bit is cleared by writing 1 to it." "0: Conversion result in ADC_ADDRx did not meet..,1: Conversion result in ADC_ADDRx met ADC_ADCMPR0.."
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bitfld.long 0x10 0. "ADF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit.\nADF bit is set to 1 at the following three conditions:\nWhen A/D conversion ends in Single mode.\nWhen A/D conversion ends on.." "0,1"
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rgroup.long 0x94++0x7
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line.long 0x0 "ADC_ADSR1,ADC Status Register1"
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hexmask.long 0x0 0.--31. 1. "VALID,Data Valid Flag (Read Only)\nVALID[31:29] VALID[15:0] are the mirror of the VALID bits in ADC_ADDR31[17] ~ ADC_ADDR29[17] ADC_ADDR15[17]~ ADC_ADDR0[17]. The other bits are reserved. \nNote: When ADC is in burst mode and any conversion result is.."
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line.long 0x4 "ADC_ADSR2,ADC Status Register2"
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hexmask.long 0x4 0.--31. 1. "OVERRUN,Overrun Flag (Read Only)\nOVERRUN[31:29] VALID[15:0] are the mirror of the OVERRUN bit in ADC_ADDR31[16] ~ADC_ADDR29[16] ADC_ADDR15[16] ~ ADC_ADDR0[16]. The other bits are reserved. \nNote: When ADC is in burst mode and the FIFO is overrun .."
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group.long 0x9C++0x3
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line.long 0x0 "ADC_ADTDCR,ADC Trigger Delay Control Register"
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hexmask.long.byte 0x0 0.--7. 1. "PTDT,PWM/BPWM Trigger Delay Time\nSet this field will delay ADC start conversion time after PWM or BPWM trigger.\nTrigger delay time is (4 * PTDT) * system clock.\nNote: Only one of PWM and BPWM can be triggered A/D conversion at the same time."
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rgroup.long 0x100++0x3
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line.long 0x0 "ADC_ADPDMA,ADC PDMA Current Transfer Data Register"
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hexmask.long.tbyte 0x0 0.--17. 1. "CURDAT,ADC PDMA Current Transfer Data Register (Read Only)\nWhen PDMA transferring reading this register can monitor current PDMA transfer data.\nThe current PDMA transfer data could be the content of ADC_ADDR0 ~ ADC_ADDR15 and ADC_ADDR29 ~ ADC_ADDR31.."
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group.long 0x104++0xB
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line.long 0x0 "ADC_ADCR1,ADC Control Register 1"
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bitfld.long 0x0 2. "FDETCHEN,Floating Detect Channel Enable Bit" "0: Floating Detect Channel Disabled,1: Floating Detect Channel Enabled"
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bitfld.long 0x0 1. "DISCHEN,Discharge Enable Bit\nNote: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enable." "0: Channel discharge Disabled,1: Channel discharge Enabled"
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bitfld.long 0x0 0. "PRECHEN,Precharge Enable Bit\nNote: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enable." "0: Channel precharge Disabled,1: Channel precharge Enabled"
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line.long 0x4 "ADC_CALCTL,ADC Calibration Control Register"
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bitfld.long 0x4 1. "CALIE,Calibration Interrupt Enable Bit" "0: Calibration interrupt Disabled,1: Calibration interrupt Enabled"
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bitfld.long 0x4 0. "CAL,Calibration Enable Bit\nNote: This bit is hardware auto cleared when calibration is done." "0: Calibration Disabled,1: Calibration Enabled"
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line.long 0x8 "ADC_CALSR,ADC Calibration Status Register"
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bitfld.long 0x8 0. "CALIF,Calibration Finish Interrupt Flag\nIf calibration is finished this flag will be set. It is cleared by writing 1 to it." "0,1"
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tree.end
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tree "BPWM (Basic PWM Generator and Capture Timer)"
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base ad:0x4005A000
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group.long 0x0++0x7
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line.long 0x0 "BPWM_CTL0,BPWM Control Register 0"
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bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects BPWM output,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled BPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x0 21. "IMMLDEN5,Immediately Load Enable Bit\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 20. "IMMLDEN4,Immediately Load Enable Bit\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 19. "IMMLDEN3,Immediately Load Enable Bit\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 18. "IMMLDEN2,Immediately Load Enable Bit\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 17. "IMMLDEN1,Immediately Load Enable Bit\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 16. "IMMLDEN0,Immediately Load Enable Bit\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 5. "CTRLD5,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 4. "CTRLD4,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 3. "CTRLD3,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 2. "CTRLD2,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 1. "CTRLD1,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 0. "CTRLD0,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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line.long 0x4 "BPWM_CTL1,BPWM Control Register 1"
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bitfld.long 0x4 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0\nEach bit n controls corresponding BPWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?"
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group.long 0x10++0x7
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line.long 0x0 "BPWM_CLKSRC,BPWM Clock Source Register"
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bitfld.long 0x0 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select" "0: BPWMx_CLK x denotes 0 or 3,1: TIMER0 overflow,?,?,?,?,?,?"
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line.long 0x4 "BPWM_CLKPSC,BPWM Clock Prescale Register"
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hexmask.long.word 0x4 0.--11. 1. "CLKPSC,BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1)."
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group.long 0x20++0x7
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line.long 0x0 "BPWM_CNTEN,BPWM Counter Enable Register"
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bitfld.long 0x0 0. "CNTEN0,BPWM Counter 0 Enable Bit" "0: BPWM Counter and clock prescaler stop running,1: BPWM Counter and clock prescaler start running"
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line.long 0x4 "BPWM_CNTCLR,BPWM Clear Counter Register"
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bitfld.long 0x4 0. "CNTCLR0,Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit BPWM counter to 0000H"
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group.long 0x30++0x3
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line.long 0x0 "BPWM_PERIOD,BPWM Period Register"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,BPWM Period Register\nUp Count mode: In this mode BPWM counter counts from 0 to PERIOD and restarts from 0.\nDown Count mode: In this mode BPWM counter counts from PERIOD to 0 and restarts from PERIOD."
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group.long 0x50++0x17
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line.long 0x0 "BPWM_CMPDAT0,BPWM Comparator Register 0"
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hexmask.long.word 0x0 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT is used to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x4 "BPWM_CMPDAT1,BPWM Comparator Register 1"
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hexmask.long.word 0x4 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT is used to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x8 "BPWM_CMPDAT2,BPWM Comparator Register 2"
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hexmask.long.word 0x8 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT is used to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0xC "BPWM_CMPDAT3,BPWM Comparator Register 3"
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hexmask.long.word 0xC 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT is used to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x10 "BPWM_CMPDAT4,BPWM Comparator Register 4"
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hexmask.long.word 0x10 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT is used to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x14 "BPWM_CMPDAT5,BPWM Comparator Register 5"
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hexmask.long.word 0x14 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT is used to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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rgroup.long 0x90++0x3
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line.long 0x0 "BPWM_CNT,BPWM Counter Register"
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bitfld.long 0x0 16. "DIRF,BPWM Direction Indicator Flag (Read Only)" "0: Counter is Down counting,1: Counter is Up counting"
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hexmask.long.word 0x0 0.--15. 1. "CNT,BPWM Data Register (Read Only)\nMonitor CNT to know the current value in 16-bit period counter."
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group.long 0xB0++0xF
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line.long 0x0 "BPWM_WGCTL0,BPWM Generation Register 0"
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bitfld.long 0x0 26.--27. "PRDPCTL5,BPWM Period Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 24.--25. "PRDPCTL4,BPWM Period Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 22.--23. "PRDPCTL3,BPWM Period Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 20.--21. "PRDPCTL2,BPWM Period Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 18.--19. "PRDPCTL1,BPWM Period Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 16.--17. "PRDPCTL0,BPWM Period Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 10.--11. "ZPCTL5,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 8.--9. "ZPCTL4,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 6.--7. "ZPCTL3,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 4.--5. "ZPCTL2,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 2.--3. "ZPCTL1,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 0.--1. "ZPCTL0,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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line.long 0x4 "BPWM_WGCTL1,BPWM Generation Register 1"
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bitfld.long 0x4 26.--27. "CMPDCTL5,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 24.--25. "CMPDCTL4,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 22.--23. "CMPDCTL3,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 20.--21. "CMPDCTL2,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 18.--19. "CMPDCTL1,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 16.--17. "CMPDCTL0,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 10.--11. "CMPUCTL5,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 8.--9. "CMPUCTL4,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 6.--7. "CMPUCTL3,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 4.--5. "CMPUCTL2,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 2.--3. "CMPUCTL1,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 0.--1. "CMPUCTL0,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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line.long 0x8 "BPWM_MSKEN,BPWM Mask Enable Register"
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bitfld.long 0x8 5. "MSKEN5,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 4. "MSKEN4,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 3. "MSKEN3,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 2. "MSKEN2,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 1. "MSKEN1,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 0. "MSKEN0,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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line.long 0xC "BPWM_MSK,BPWM Mask Data Register"
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bitfld.long 0xC 5. "MSKDAT5,BPWM Mask Data Bit\nThis data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 4. "MSKDAT4,BPWM Mask Data Bit\nThis data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 3. "MSKDAT3,BPWM Mask Data Bit\nThis data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 2. "MSKDAT2,BPWM Mask Data Bit\nThis data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 1. "MSKDAT1,BPWM Mask Data Bit\nThis data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 0. "MSKDAT0,BPWM Mask Data Bit\nThis data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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group.long 0xD4++0x7
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line.long 0x0 "BPWM_POLCTL,BPWM Pin Polar Inverse Register"
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bitfld.long 0x0 5. "PINV5,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 4. "PINV4,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 3. "PINV3,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 2. "PINV2,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 1. "PINV1,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 0. "PINV0,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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line.long 0x4 "BPWM_POEN,BPWM Output Enable Register"
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bitfld.long 0x4 5. "POEN5,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 4. "POEN4,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 3. "POEN3,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 2. "POEN2,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 1. "POEN1,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 0. "POEN0,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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group.long 0xE0++0x3
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line.long 0x0 "BPWM_INTEN,BPWM Interrupt Enable Register"
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bitfld.long 0x0 29. "CMPDIEN5,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 28. "CMPDIEN4,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 27. "CMPDIEN3,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 26. "CMPDIEN2,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 25. "CMPDIEN1,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 24. "CMPDIEN0,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 21. "CMPUIEN5,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 20. "CMPUIEN4,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 19. "CMPUIEN3,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 18. "CMPUIEN2,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 17. "CMPUIEN1,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 16. "CMPUIEN0,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 8. "PIEN0,BPWM Period Point Interrupt 0 Enable Bit\nNote: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x0 0. "ZIEN0,BPWM Zero Point Interrupt 0 Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0xE8++0x3
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line.long 0x0 "BPWM_INTSTS,BPWM Interrupt Flag Register"
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bitfld.long 0x0 29. "CMPDIF5,BPWM Compare Down Count Interrupt Flag\nEach bit controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.\nNote: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 28. "CMPDIF4,BPWM Compare Down Count Interrupt Flag\nEach bit controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.\nNote: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 27. "CMPDIF3,BPWM Compare Down Count Interrupt Flag\nEach bit controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.\nNote: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 26. "CMPDIF2,BPWM Compare Down Count Interrupt Flag\nEach bit controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.\nNote: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 25. "CMPDIF1,BPWM Compare Down Count Interrupt Flag\nEach bit controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.\nNote: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 24. "CMPDIF0,BPWM Compare Down Count Interrupt Flag\nEach bit controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.\nNote: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 21. "CMPUIF5,BPWM Compare Up Count Interrupt Flag\nEach bit controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.\nNote: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 20. "CMPUIF4,BPWM Compare Up Count Interrupt Flag\nEach bit controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.\nNote: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 19. "CMPUIF3,BPWM Compare Up Count Interrupt Flag\nEach bit controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.\nNote: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 18. "CMPUIF2,BPWM Compare Up Count Interrupt Flag\nEach bit controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.\nNote: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 17. "CMPUIF1,BPWM Compare Up Count Interrupt Flag\nEach bit controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.\nNote: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 16. "CMPUIF0,BPWM Compare Up Count Interrupt Flag\nEach bit controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.\nNote: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 8. "PIF0,BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0. Software can write 1 to clear this bit to 0." "0,1"
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bitfld.long 0x0 0. "ZIF0,BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches 0. Software can write 1 to clear this bit to 0." "0,1"
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group.long 0xF8++0x7
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line.long 0x0 "BPWM_ADCTS0,BPWM Trigger ADC Source Select Register 0"
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bitfld.long 0x0 31. "TRGEN3,BPWM_CH3 Trigger ADC Enable Bit" "0: BPWM_CH3 Trigger ADC function Disabled,1: BPWM_CH3 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 24.--27. 1. "TRGSEL3,BPWM_CH3 Trigger ADC Source Select\nOthers reserved."
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bitfld.long 0x0 23. "TRGEN2,BPWM_CH2 Trigger ADC Enable Bit" "0: BPWM_CH2 Trigger ADC function Disabled,1: BPWM_CH2 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 16.--19. 1. "TRGSEL2,BPWM_CH2 Trigger ADC Source Select\nOthers reserved"
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bitfld.long 0x0 15. "TRGEN1,BPWM_CH1 Trigger ADC Enable Bit" "0: BPWM_CH1 Trigger ADC function Disabled,1: BPWM_CH1 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 8.--11. 1. "TRGSEL1,BPWM_CH1 Trigger ADC Source Select\nOthers reserved"
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bitfld.long 0x0 7. "TRGEN0,BPWM_CH0 Trigger ADC Enable Bit" "0: BPWM_CH0 Trigger ADC function Disabled,1: BPWM_CH0 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 0.--3. 1. "TRGSEL0,BPWM_CH0 Trigger ADC Source Select\nOthers reserved"
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line.long 0x4 "BPWM_ADCTS1,BPWM Trigger ADC Source Select Register 1"
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bitfld.long 0x4 15. "TRGEN5,BPWM_CH5 Trigger ADC Enable Bit" "0: BPWM_CH5 Trigger ADC function Disabled,1: BPWM_CH5 Trigger ADC function Enabled"
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hexmask.long.byte 0x4 8.--11. 1. "TRGSEL5,BPWM_CH5 Trigger ADC Source Select\nOthers reserved"
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bitfld.long 0x4 7. "TRGEN4,BPWM_CH4 Trigger ADC Enable Bit" "0: BPWM_CH4 Trigger ADC function Disabled,1: BPWM_CH4 Trigger ADC function Enabled"
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hexmask.long.byte 0x4 0.--3. 1. "TRGSEL4,BPWM_CH4 Trigger ADC Source Select\nOthers reserved"
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group.long 0x110++0x3
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line.long 0x0 "BPWM_SSCTL,BPWM Synchronous Start Control Register"
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bitfld.long 0x0 8.--9. "SSRC,BPWM Synchronous Start Source Select" "0: Synchronous start source come from PWM0,?,?,?"
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bitfld.long 0x0 0. "SSEN0,BPWM Synchronous Start Function 0 Enable Bit\nWhen synchronous start function is enabled the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN)." "0: BPWM synchronous start function Disabled,1: BPWM synchronous start function Enabled"
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wgroup.long 0x114++0x3
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line.long 0x0 "BPWM_SSTRG,BPWM Synchronous Start Trigger Register"
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bitfld.long 0x0 0. "CNTSEN,BPWM Counter Synchronous Start Enable Bit (Write Only)\nBPMW counter synchronous enable function is used to make all BPWM channels start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit if correlated BPWM.." "0,1"
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group.long 0x120++0x3
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line.long 0x0 "BPWM_STATUS,BPWM Status Register"
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bitfld.long 0x0 21. "ADCTRG5,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 20. "ADCTRG4,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 19. "ADCTRG3,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 18. "ADCTRG2,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 17. "ADCTRG1,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 16. "ADCTRG0,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 0. "CNTMAXF0,Time-base Counter 0 Equal to 0xFFFF Latched Flag" "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value."
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group.long 0x200++0x7
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line.long 0x0 "BPWM_CAPINEN,BPWM Capture Input Enable Register"
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bitfld.long 0x0 5. "CAPINEN5,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 4. "CAPINEN4,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 3. "CAPINEN3,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 2. "CAPINEN2,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 1. "CAPINEN1,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 0. "CAPINEN0,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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line.long 0x4 "BPWM_CAPCTL,BPWM Capture Control Register"
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bitfld.long 0x4 29. "FCRLDEN5,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 28. "FCRLDEN4,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 27. "FCRLDEN3,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 26. "FCRLDEN2,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 25. "FCRLDEN1,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 24. "FCRLDEN0,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 21. "RCRLDEN5,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 20. "RCRLDEN4,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 19. "RCRLDEN3,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 18. "RCRLDEN2,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 17. "RCRLDEN1,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 16. "RCRLDEN0,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 13. "CAPINV5,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 12. "CAPINV4,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 11. "CAPINV3,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 10. "CAPINV2,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 9. "CAPINV1,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 8. "CAPINV0,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 5. "CAPEN5,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 4. "CAPEN4,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 3. "CAPEN3,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 2. "CAPEN2,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 1. "CAPEN1,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 0. "CAPEN0,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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rgroup.long 0x208++0x33
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line.long 0x0 "BPWM_CAPSTS,BPWM Capture Status Register"
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bitfld.long 0x0 13. "CFIFOV5,Capture Falling Interrupt Flag Overrun Status (Read Only)\nEach bit controls the corresponding BPWM channel n.\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. \nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 12. "CFIFOV4,Capture Falling Interrupt Flag Overrun Status (Read Only)\nEach bit controls the corresponding BPWM channel n.\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. \nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 11. "CFIFOV3,Capture Falling Interrupt Flag Overrun Status (Read Only)\nEach bit controls the corresponding BPWM channel n.\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. \nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 10. "CFIFOV2,Capture Falling Interrupt Flag Overrun Status (Read Only)\nEach bit controls the corresponding BPWM channel n.\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. \nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 9. "CFIFOV1,Capture Falling Interrupt Flag Overrun Status (Read Only)\nEach bit controls the corresponding BPWM channel n.\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. \nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 8. "CFIFOV0,Capture Falling Interrupt Flag Overrun Status (Read Only)\nEach bit controls the corresponding BPWM channel n.\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. \nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 5. "CRIFOV5,Capture Rising Interrupt Flag Overrun Status (Read Only)\nEach bit n controls the corresponding BPWM channel n.\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. \nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 4. "CRIFOV4,Capture Rising Interrupt Flag Overrun Status (Read Only)\nEach bit n controls the corresponding BPWM channel n.\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. \nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 3. "CRIFOV3,Capture Rising Interrupt Flag Overrun Status (Read Only)\nEach bit n controls the corresponding BPWM channel n.\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. \nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 2. "CRIFOV2,Capture Rising Interrupt Flag Overrun Status (Read Only)\nEach bit n controls the corresponding BPWM channel n.\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. \nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 1. "CRIFOV1,Capture Rising Interrupt Flag Overrun Status (Read Only)\nEach bit n controls the corresponding BPWM channel n.\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. \nNote: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 0. "CRIFOV0,Capture Rising Interrupt Flag Overrun Status (Read Only)\nEach bit n controls the corresponding BPWM channel n.\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. \nNote: This bit will be cleared automatically when.." "0,1"
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line.long 0x4 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0"
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hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x8 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0"
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hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0xC "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1"
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hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x10 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1"
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hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x14 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2"
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hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x18 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2"
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hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x1C "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3"
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hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x20 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3"
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hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x24 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4"
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hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x28 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4"
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hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x2C "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5"
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hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x30 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5"
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hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register."
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group.long 0x250++0x7
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line.long 0x0 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register"
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hexmask.long.byte 0x0 8.--13. 1. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n."
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hexmask.long.byte 0x0 0.--5. 1. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n."
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line.long 0x4 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register"
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bitfld.long 0x4 13. "CAPFIF5,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 12. "CAPFIF4,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 11. "CAPFIF3,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 10. "CAPFIF2,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 9. "CAPFIF1,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 8. "CAPFIF0,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 5. "CAPRIF5,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 4. "CAPRIF4,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 3. "CAPRIF3,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 2. "CAPRIF2,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 1. "CAPRIF1,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 0. "CAPRIF0,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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rgroup.long 0x304++0x3
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line.long 0x0 "BPWM_PBUF,BPWM PERIOD Buffer"
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hexmask.long.word 0x0 0.--15. 1. "PBUF,BPWM Period Buffer (Read Only)\nUsed as PERIOD active register."
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rgroup.long 0x31C++0x17
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line.long 0x0 "BPWM_CMPBUF0,BPWM CMPDAT 0 Buffer"
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hexmask.long.word 0x0 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMPDAT active register."
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line.long 0x4 "BPWM_CMPBUF1,BPWM CMPDAT 1 Buffer"
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hexmask.long.word 0x4 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMPDAT active register."
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line.long 0x8 "BPWM_CMPBUF2,BPWM CMPDAT 2 Buffer"
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hexmask.long.word 0x8 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMPDAT active register."
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line.long 0xC "BPWM_CMPBUF3,BPWM CMPDAT 3 Buffer"
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hexmask.long.word 0xC 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMPDAT active register."
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line.long 0x10 "BPWM_CMPBUF4,BPWM CMPDAT 4 Buffer"
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hexmask.long.word 0x10 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMPDAT active register."
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line.long 0x14 "BPWM_CMPBUF5,BPWM CMPDAT 5 Buffer"
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hexmask.long.word 0x14 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMPDAT active register."
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tree.end
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tree "CANFD (Controller Area Network with Flexible DataRate)"
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base ad:0x0
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tree "CANFD0"
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base ad:0x40020000
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rgroup.long 0xC++0xB
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line.long 0x0 "CANFD_DBTP,Data Bit Timing Prescaler Register (P*)"
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bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation Disabled,1: Transmitter Delay Compensation Enabled"
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hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
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hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
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hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
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hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data Re-Synchronization Jump Width"
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line.long 0x4 "CANFD_TEST,Test Register (P*)"
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bitfld.long 0x4 7. "RX,Receive Pin\nMonitors the actual value of pin CANx_RXD" "0: The CAN bus is dominant (CANx_RXD = 0),1: The CAN bus is recessive (CANx_RXD = 1)"
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bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CANx_TXD controlled by the CAN Core..,1: Sample Point can be monitored at pin CANx_TXD,?,?"
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bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0: Reset value Loop Back Mode Disabled,1: Loop Back Mode Enabled (refer to TEST Mode in.."
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line.long 0x8 "CANFD_RWD,RAM Watchdog (P*)"
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hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value \nActual Message RAM Watchdog Counter Value."
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hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration \nStart value of the Message RAM Watchdog Counter. With the reset value of 00 the counter is disabled."
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group.long 0x18++0x3
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line.long 0x0 "CANFD_CCCR,CC Control Register (Pp*)"
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bitfld.long 0x0 15. "NISO,Non ISO Operation\nIf this bit is set the CAN FD controller uses the CAN FD frame format as specied by the Bosch CAN FD Specication V1.0." "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
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bitfld.long 0x0 14. "TXP,Transmit Pause\nIf this bit is set the CAN FD controller pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (refer to Tx Handling section)." "0: Transmit pause Disabled,1: Transmit pause Enabled"
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bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering Disabled,1: Two consecutive dominant tq required to detect.."
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bitfld.long 0x0 12. "PXHD,Protocol Exception Handling Disable\nNote: When protocol exception handling is disabled the controller will transmit an error frame when it detects a protocol exception condition." "0: Protocol exception handling Enabled,1: Protocol exception handling Disabled"
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bitfld.long 0x0 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions Disabled,1: Bit rate switching for transmissions Enabled"
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bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0: FD operation Disabled,1: FD operation Enabled"
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bitfld.long 0x0 7. "TEST,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
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bitfld.long 0x0 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission Disabled"
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bitfld.long 0x0 5. "MON,Bus Monitoring Mode\nBit MON can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the Host at any time." "0: Bus Monitoring Mode Disabled,1: Bus Monitoring Mode Enabled"
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bitfld.long 0x0 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.."
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bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: The Controller may be set in power down by.."
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bitfld.long 0x0 2. "ASM,Restricted Operation Mode\nBit ASM can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the software at any time. This bit will be set automatically set to 1 when the Tx handler was not able to read data from the.." "0: Normal CAN operation,1: Restricted Operation Mode active"
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bitfld.long 0x0 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
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bitfld.long 0x0 0. "INIT,Initialization\nNote: Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been.." "0: Normal Operation,1: Initialization is started"
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rgroup.long 0x1C++0x13
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line.long 0x0 "CANFD_NBTP,Nominal Bit Timing Prescaler Register (P*)"
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hexmask.long.byte 0x0 25.--31. 1. "NSJW,Nominal Re-Synchronization Jump Width"
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hexmask.long.word 0x0 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler\nThe value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual.."
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hexmask.long.byte 0x0 8.--15. 1. "NTSEG1,Nominal Time Segment before Sample Point"
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hexmask.long.byte 0x0 0.--6. 1. "NTSEG2,Nominal Time Segment after Sample Point\nNote: With a CAN Core clock (cclk) of 8 MHz the reset value of 0x06000A03 configures the controller for a bit rate of 500 kBit/s."
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line.long 0x4 "CANFD_TSCC,Timestamp Counter Configuration (P*)"
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hexmask.long.byte 0x4 16.--19. 1. "TCP,Timestamp Counter Prescaler\nCongures the timestamp and timeout counters time unit in multiples of CAN bit times [ 1...16 ]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."
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bitfld.long 0x4 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,?,?"
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line.long 0x8 "CANFD_TSCV,Timestamp Counter Value (C*)"
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hexmask.long.word 0x8 0.--15. 1. "TSC,Timestamp Counter\nNote: A 'wrap around' is a change of the Timestamp Counter value from non-zero to 0 not caused by write access to CANFD_TSCV."
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line.long 0xC "CANFD_TOCC,Timeout Counter Configuration (P*)"
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hexmask.long.word 0xC 16.--31. 1. "TOP,Timeout Period\nStart value of the Timeout Counter (down-counter). Congures the Timeout Period."
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bitfld.long 0xC 1.--2. "TOS,Timeout Select\nWhen operating in Continuous mode a write to CANFD_TOCV presets the counter to the value congured by TOP (CANFD_TOCC[31:16]) and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs an empty FIFO.." "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,?,?"
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bitfld.long 0xC 0. "ETOC,Enable Timeout Counter\nNote: For use of timeout function with CAN FD refer to Timeout Counter section錯誤! 找不到參照來源。." "0: Timeout Counter Disabled,1: Timeout Counter Enabled"
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line.long 0x10 "CANFD_TOCV,Timeout Counter Value (C*)"
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hexmask.long.word 0x10 0.--15. 1. "TOC,Timeout Counter\nThe filed is decremented in multiples of CAN bit times [ 1...16 ] depending on the configuration of TCP (CANFD_TSCC[19:16]). When decremented to 0 interrupt flag TOO (CANFD_IR[18]) is set and the timeout counter is stopped. Start.."
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rgroup.long 0x40++0xB
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line.long 0x0 "CANFD_ECR,Error Counter Register (X*)"
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hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging\nThe counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached."
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bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter\nActual state of the Receive Error Counter values between 0 and 127."
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hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter\nActual state of the Transmit Error Counter values between 0 and 255.\nNote: When ASM (CANFD_CCCR[2]) is set the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected but CEL is still.."
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line.long 0x4 "CANFD_PSR,Protocol Status Register (XS*)"
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hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value\nPosition of the secondary sample point dened by the sum of the measured delay from CANx_TXD to CANx_RXD and TDCO (CANFD_TDCR[14:8]). The SSP position is in the data phase the number of minimum time quata.."
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bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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bitfld.long 0x4 13. "RFDF,Received a CAN FD Message\nThis bit is set independent of acceptance filtering.\nNote: Byte access: Reading byte 0 will reset RFDF reading bytes 3/2/1 has no impact." "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.."
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bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message\nThis bit is set together with RFDF independent of acceptance filtering.\nNote: Byte access: Reading byte 0 will reset RBRS reading bytes 3/2/1 has no impact." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set"
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bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message\nThis bit is set together with RFDF independent of acceptance filtering." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set"
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bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code\nType of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to 0 when a CAN FD format frame with its BRS flag set has been.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The CAN FD controller is not Bus_Off,1: The CAN FD controller is in Bus_Off state"
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bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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bitfld.long 0x4 5. "EP,Error Passive" "0: The CAN FD controller is in the Error_Active..,1: The CAN FD controller is in the Error_Passive.."
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bitfld.long 0x4 3.--4. "ACT,Activity\nMonitors the module's CAN communication state." "0: Synchronizing - node is synchronizing on CAN..,1: Idle - node is neither receiver nor transmitter,?,?"
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bitfld.long 0x4 0.--2. "LEC,Last Error Code\nThe LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error." "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,?,?,?,?,?,?"
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line.long 0x8 "CANFD_TDCR,Transmitter Delay Compensation Register (P*)"
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hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset\nOffset value dening the distance between the measured delay from CANx_TXD to CANx_RXD and the secondary sample point. Valid values are 0 to 127 mtq."
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hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length\nDenes the minimum value for the SSP position dominant edges on CANx_RXD that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when.."
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group.long 0x50++0xF
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line.long 0x0 "CANFD_IR,Interrupt Register"
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bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
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bitfld.long 0x0 28. "PED,Protocol Error in Data Phase\nNote: Data bit time is used." "0: No protocol error in data phase,1: Protocol error in data phase detected (DLEC.."
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newline
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bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase\nNote: Nominal bit time is used." "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
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bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY"
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newline
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bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
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bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
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newline
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bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
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bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred"
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newline
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bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer\nThe flag is set whenever a received message has been stored into a dedicated Rx Buffer." "0: No Rx Buffer updated,1: At least one received message stored into an Rx.."
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bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached"
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newline
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bitfld.long 0x0 17. "MRAF,Message RAM Access Failure\nThe flag is set when the Rx Handler\n• Has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering.." "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
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bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
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newline
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bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
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bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
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newline
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bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO ll level below watermark,1: Tx Event FIFO ll level reached watermark"
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bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element"
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newline
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bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
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bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
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newline
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bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed"
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bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received"
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newline
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bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
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bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
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newline
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bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 ll level below watermark,1: Rx FIFO 1 ll level reached watermark"
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bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
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newline
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bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
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bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
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newline
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bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 ll level below watermark,1: Rx FIFO 0 ll level reached watermark"
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bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
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line.long 0x4 "CANFD_IE,Interrupt Enable"
|
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bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
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bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
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bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
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bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
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bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
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bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
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bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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|
newline
|
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bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
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bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
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bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
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bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
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newline
|
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bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
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bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
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bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
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bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
line.long 0x8 "CANFD_ILS,Interrupt Line Select"
|
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bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
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bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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newline
|
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bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
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newline
|
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bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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newline
|
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bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
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newline
|
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bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
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bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
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newline
|
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bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
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newline
|
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bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
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newline
|
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bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
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bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
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newline
|
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bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
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newline
|
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bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
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bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
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newline
|
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bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
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bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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newline
|
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bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
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bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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newline
|
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bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
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bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
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newline
|
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bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
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line.long 0xC "CANFD_ILE,Interrupt Line Enable"
|
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bitfld.long 0xC 1. "ENT1,Enable Interrupt Line 1" "0: Interrupt line canfd_int1 Disabled,1: Interrupt line canfd_int1 Enabled"
|
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bitfld.long 0xC 0. "ENT0,Enable Interrupt Line 0" "0: Interrupt line canfd_int0 Disabled,1: Interrupt line canfd_int0 Enabled"
|
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rgroup.long 0x80++0xB
|
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line.long 0x0 "CANFD_GFC,Global Filter Configuration (P*)"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard\nDenes how received messages with 11-bit IDs that do not match any element of the filter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
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bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended\nDenes how received messages with 29-bit IDs that do not match any element of the filter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
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newline
|
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bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
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bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs"
|
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line.long 0x4 "CANFD_SIDFC,Standard ID Filter Configuration (P*)"
|
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hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
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hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address\nStart address of standard Message ID filter list (32-bit word address refer to 錯誤! 找不到參照來源。)."
|
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line.long 0x8 "CANFD_XIDFC,Extended ID Filter Configuration (P*)"
|
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hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
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hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address\nStart address of extended Message ID filter list (32-bit word address refer to 錯誤! 找不到參照來源。)."
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rgroup.long 0x90++0x7
|
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line.long 0x0 "CANFD_XIDAM,Extended ID AND Mask (P*)"
|
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hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask\nFor acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.."
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line.long 0x4 "CANFD_HPMS,High Priority Message Status"
|
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bitfld.long 0x4 15. "FLST,Filter List\nIndicates the filter list of the matching filter element." "0: Standard Filter List,1: Extended Filter List"
|
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hexmask.long.byte 0x4 8.--14. 1. "FIDX,Filter Index\nIndex of matching filter element. Range is 0 to LSS (CANFD_SIDFC[23:16]) - 1 or LSE (CANFD_XIDFC[22:16]) - 1"
|
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newline
|
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bitfld.long 0x4 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,?,?"
|
|
hexmask.long.byte 0x4 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x98++0x7
|
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line.long 0x0 "CANFD_NDAT1,New Data 1"
|
|
hexmask.long 0x0 0.--31. 1. "NDn,New Data\nThe register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
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line.long 0x4 "CANFD_NDAT2,New Data 2"
|
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hexmask.long 0x4 0.--31. 1. "NDn,New Data\nThe register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
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rgroup.long 0xA0++0x7
|
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line.long 0x0 "CANFD_RXF0C,Rx FIFO 0 Configuration (P*)"
|
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bitfld.long 0x0 31. "F0OM,FIFO 0 Operation Mode\nFIFO 0 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
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hexmask.long.byte 0x0 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
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newline
|
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hexmask.long.byte 0x0 16.--22. 1. "F0S,Rx FIFO 0 Size\nThe Rx FIFO 0 elements are indexed from 0 to F0S - 1"
|
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hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address\nStart address of Rx FIFO 0 in Message RAM (32-bit word address)."
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line.long 0x4 "CANFD_RXF0S,Rx FIFO 0 Status"
|
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bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "?,1: Rx FIFO 0 message lost also set after write.."
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bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
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newline
|
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hexmask.long.byte 0x4 16.--21. 1. "F0PI,Rx FIFO 0 Put Index\nRx FIFO 0 write index pointer range 0 to 63."
|
|
hexmask.long.byte 0x4 8.--13. 1. "F0GI,Rx FIFO 0 Get Index\nRx FIFO 0 read index pointer range 0 to 63."
|
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newline
|
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hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level\nNumber of elements stored in Rx FIFO 0 range 0 to 64"
|
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group.long 0xA8++0x3
|
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line.long 0x0 "CANFD_RXF0A,Rx FIFO 0 Acknowledge"
|
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hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index F0GI (CANFD_RXF0S[13:8]).."
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rgroup.long 0xAC++0xB
|
|
line.long 0x0 "CANFD_RXBC,Rx Buffer Configuration (P*)"
|
|
hexmask.long.word 0x0 2.--15. 1. "RBSA,Rx Buffer Start Address\nCongures the start address of the Rx Buffers section in the Message RAM (32-bit word address)."
|
|
line.long 0x4 "CANFD_RXF1C,Rx FIFO 1 Configuration (P*)"
|
|
bitfld.long 0x4 31. "F1OM,FIFO 1 Operation Mode\nFIFO 1 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
|
|
hexmask.long.byte 0x4 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
|
|
newline
|
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hexmask.long.byte 0x4 16.--22. 1. "F1S,Rx FIFO 1 Size\nThe Rx FIFO 1 elements are indexed from 0 to F1S - 1"
|
|
hexmask.long.word 0x4 2.--15. 1. "F1SA,Rx FIFO 1 Start Address\nStart address of Rx FIFO 1 in Message RAM (32-bit word address refer to 錯誤! 找不到參照來源。)."
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|
line.long 0x8 "CANFD_RXF1S,Rx FIFO 1 Status"
|
|
bitfld.long 0x8 25. "RF1L,Rx FIFO 1 Message Lost" "?,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x8 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
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hexmask.long.byte 0x8 16.--21. 1. "F1PI,Rx FIFO 1 Put Index\nRx FIFO 1 write index pointer range 0 to 63."
|
|
hexmask.long.byte 0x8 8.--13. 1. "F1GI,Rx FIFO 1 Get Index\nRx FIFO 1 read index pointer range 0 to 63."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level\nNumber of elements stored in Rx FIFO 1 range 0 to 64"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "CANFD_RXF1A,Rx FIFO 1 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index F1GI (CANFD_RXF1S[13:8]).."
|
|
rgroup.long 0xBC++0x13
|
|
line.long 0x0 "CANFD_RXESC,Rx Buffer / FIFO Element Size Configuration (P*)"
|
|
bitfld.long 0x0 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
|
|
bitfld.long 0x0 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
|
|
newline
|
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bitfld.long 0x0 0.--2. "F0DS,Rx FIFO 0 Data Field Size\nNote: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO only the number of bytes as configured by CANFD_RXESC are stored to the Rx Buffer.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
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|
line.long 0x4 "CANFD_TXBC,Tx Buffer Configuration (P*)"
|
|
bitfld.long 0x4 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
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hexmask.long.byte 0x4 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
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hexmask.long.byte 0x4 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
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hexmask.long.word 0x4 2.--15. 1. "TBSA,Tx Buffers Start Address\nStart address of Tx Buffers section in Message RAM (32-bit word address refer to 錯誤! 找不到參照來源。).\nNote: The sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous.."
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line.long 0x8 "CANFD_TXFQS,Tx FIFO/Queue Status"
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bitfld.long 0x8 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full"
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hexmask.long.byte 0x8 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index\nTx FIFO/Queue write index pointer range 0 to 31."
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hexmask.long.byte 0x8 8.--12. 1. "TFGI,Tx FIFO Get Index"
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hexmask.long.byte 0x8 0.--5. 1. "TFFL,Tx FIFO Free Level\nNote: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers.\nExample: For.."
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line.long 0xC "CANFD_TXESC,Tx Buffer Element Size Configuration (P*)"
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bitfld.long 0xC 0.--2. "TBDS,Tx Buffer Data Field Size\nNote: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TBDS (CANFD_TXESC[2:0]) the bytes not defined by the Tx Buffer are transmitted as 0xCC.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
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line.long 0x10 "CANFD_TXBRP,Tx Buffer Request Pending"
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hexmask.long 0x10 0.--31. 1. "TRPn,Transmission Request PendingEach Tx Buffer has its own Transmission Request Pending bit The bits are set via register CANFD_TXBAR The bits are reset after a requested transmission has completed or has been cancelled via register.."
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group.long 0xD0++0x7
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line.long 0x0 "CANFD_TXBAR,Tx Buffer Add Request"
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hexmask.long 0x0 0.--31. 1. "ARn,Add RequestEach Tx Buffer has its own Add Request bit Writing a 1 will set the corresponding Add Request bit; writing a 0 has no impact This enables the Host to set transmission requests for multiple Tx Buffers with one write to CANFD_TXBAR.."
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line.long 0x4 "CANFD_TXBCR,Tx Buffer Cancellation Request"
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hexmask.long 0x4 0.--31. 1. "CRn,Cancellation Request\nEach Tx Buffer has its own Cancellation Request bit. Writing a 1 will set the corresponding Cancellation Request bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one.."
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rgroup.long 0xD8++0x7
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line.long 0x0 "CANFD_TXBTO,Tx Buffer Transmission Occurred"
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hexmask.long 0x0 0.--31. 1. "TOn,Transmission Occurred\nEach Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to.."
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line.long 0x4 "CANFD_TXBCF,Tx Buffer Cancellation Finished"
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hexmask.long 0x4 0.--31. 1. "CFn,Cancellation Finished\nEach Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a cancellation was requested via CANFD_TXBCR. In case the corresponding CANFD_TXBRP bit was not set.."
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group.long 0xE0++0x7
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line.long 0x0 "CANFD_TXBTIE,Tx Buffer Transmission Interrupt Enable"
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hexmask.long 0x0 0.--31. 1. "TIEn,Transmission Interrupt Enable\nEach Tx Buffer has its own Transmission Interrupt Enable bit."
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line.long 0x4 "CANFD_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
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hexmask.long 0x4 0.--31. 1. "CFIEn,Cancellation Finished Interrupt Enable\nEach Tx Buffer has its own Cancellation Finished Interrupt Enable bit."
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rgroup.long 0xF0++0x7
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line.long 0x0 "CANFD_TXEFC,Tx Event FIFO Configuration (P*)"
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hexmask.long.byte 0x0 24.--29. 1. "EFWN,Event FIFO Watermark"
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hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size\nThe Tx Event FIFO elements are indexed from 0 to EFS - 1"
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hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address\nStart address of Tx Event FIFO in Message RAM (32-bit word address refer to 錯誤! 找不到參照來源。)."
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line.long 0x4 "CANFD_TXEFS,Tx Event FIFO Status"
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bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element Lost\nThis bit is a copy of interrupt flag TEFL (CANFD_IR[15]). When TEFL is reset this bit is also reset." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
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bitfld.long 0x4 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
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hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO Put Index\nTx Event FIFO write index pointer range 0 to 31"
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hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index\nTx Event FIFO read index pointer range 0 to 31"
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hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level\nNumber of elements stored in Tx Event FIFO range 0 to 32"
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group.long 0xF8++0x7
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line.long 0x0 "CANFD_TXEFA,Tx Event FIFO Acknowledge"
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hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index\nAfter the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index EFGI.."
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line.long 0x4 "CANFD_STSEL,Tx Rx Signal Type Selection Register"
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bitfld.long 0x4 8.--9. "RXSS,CAN Rx Signal Selection" "0: from CAN_Rx pin,1: from ACMP0 output,?,?"
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bitfld.long 0x4 4.--6. "TXLS,CAN TxL Signal Type" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 0.--2. "TXHS,CAN TxH Signal Type" "0,1,2,3,4,5,6,7"
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tree.end
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tree "CANFD1"
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base ad:0x40024000
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rgroup.long 0xC++0xB
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line.long 0x0 "CANFD_DBTP,Data Bit Timing Prescaler Register (P*)"
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bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation Disabled,1: Transmitter Delay Compensation Enabled"
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hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
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hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
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hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
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hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data Re-Synchronization Jump Width"
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line.long 0x4 "CANFD_TEST,Test Register (P*)"
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bitfld.long 0x4 7. "RX,Receive Pin\nMonitors the actual value of pin CANx_RXD" "0: The CAN bus is dominant (CANx_RXD = 0),1: The CAN bus is recessive (CANx_RXD = 1)"
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bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CANx_TXD controlled by the CAN Core..,1: Sample Point can be monitored at pin CANx_TXD,?,?"
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bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0: Reset value Loop Back Mode Disabled,1: Loop Back Mode Enabled (refer to TEST Mode in.."
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line.long 0x8 "CANFD_RWD,RAM Watchdog (P*)"
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hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value \nActual Message RAM Watchdog Counter Value."
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hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration \nStart value of the Message RAM Watchdog Counter. With the reset value of 00 the counter is disabled."
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group.long 0x18++0x3
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line.long 0x0 "CANFD_CCCR,CC Control Register (Pp*)"
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bitfld.long 0x0 15. "NISO,Non ISO Operation\nIf this bit is set the CAN FD controller uses the CAN FD frame format as specied by the Bosch CAN FD Specication V1.0." "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
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bitfld.long 0x0 14. "TXP,Transmit Pause\nIf this bit is set the CAN FD controller pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (refer to Tx Handling section)." "0: Transmit pause Disabled,1: Transmit pause Enabled"
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bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering Disabled,1: Two consecutive dominant tq required to detect.."
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bitfld.long 0x0 12. "PXHD,Protocol Exception Handling Disable\nNote: When protocol exception handling is disabled the controller will transmit an error frame when it detects a protocol exception condition." "0: Protocol exception handling Enabled,1: Protocol exception handling Disabled"
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bitfld.long 0x0 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions Disabled,1: Bit rate switching for transmissions Enabled"
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bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0: FD operation Disabled,1: FD operation Enabled"
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newline
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bitfld.long 0x0 7. "TEST,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
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bitfld.long 0x0 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission Disabled"
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bitfld.long 0x0 5. "MON,Bus Monitoring Mode\nBit MON can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the Host at any time." "0: Bus Monitoring Mode Disabled,1: Bus Monitoring Mode Enabled"
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bitfld.long 0x0 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.."
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newline
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bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: The Controller may be set in power down by.."
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bitfld.long 0x0 2. "ASM,Restricted Operation Mode\nBit ASM can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the software at any time. This bit will be set automatically set to 1 when the Tx handler was not able to read data from the.." "0: Normal CAN operation,1: Restricted Operation Mode active"
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newline
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bitfld.long 0x0 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
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bitfld.long 0x0 0. "INIT,Initialization\nNote: Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been.." "0: Normal Operation,1: Initialization is started"
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rgroup.long 0x1C++0x13
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line.long 0x0 "CANFD_NBTP,Nominal Bit Timing Prescaler Register (P*)"
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hexmask.long.byte 0x0 25.--31. 1. "NSJW,Nominal Re-Synchronization Jump Width"
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hexmask.long.word 0x0 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler\nThe value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual.."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "NTSEG1,Nominal Time Segment before Sample Point"
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hexmask.long.byte 0x0 0.--6. 1. "NTSEG2,Nominal Time Segment after Sample Point\nNote: With a CAN Core clock (cclk) of 8 MHz the reset value of 0x06000A03 configures the controller for a bit rate of 500 kBit/s."
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line.long 0x4 "CANFD_TSCC,Timestamp Counter Configuration (P*)"
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hexmask.long.byte 0x4 16.--19. 1. "TCP,Timestamp Counter Prescaler\nCongures the timestamp and timeout counters time unit in multiples of CAN bit times [ 1...16 ]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."
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bitfld.long 0x4 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,?,?"
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line.long 0x8 "CANFD_TSCV,Timestamp Counter Value (C*)"
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hexmask.long.word 0x8 0.--15. 1. "TSC,Timestamp Counter\nNote: A 'wrap around' is a change of the Timestamp Counter value from non-zero to 0 not caused by write access to CANFD_TSCV."
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line.long 0xC "CANFD_TOCC,Timeout Counter Configuration (P*)"
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hexmask.long.word 0xC 16.--31. 1. "TOP,Timeout Period\nStart value of the Timeout Counter (down-counter). Congures the Timeout Period."
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bitfld.long 0xC 1.--2. "TOS,Timeout Select\nWhen operating in Continuous mode a write to CANFD_TOCV presets the counter to the value congured by TOP (CANFD_TOCC[31:16]) and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs an empty FIFO.." "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,?,?"
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newline
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bitfld.long 0xC 0. "ETOC,Enable Timeout Counter\nNote: For use of timeout function with CAN FD refer to Timeout Counter section錯誤! 找不到參照來源。." "0: Timeout Counter Disabled,1: Timeout Counter Enabled"
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line.long 0x10 "CANFD_TOCV,Timeout Counter Value (C*)"
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hexmask.long.word 0x10 0.--15. 1. "TOC,Timeout Counter\nThe filed is decremented in multiples of CAN bit times [ 1...16 ] depending on the configuration of TCP (CANFD_TSCC[19:16]). When decremented to 0 interrupt flag TOO (CANFD_IR[18]) is set and the timeout counter is stopped. Start.."
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rgroup.long 0x40++0xB
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line.long 0x0 "CANFD_ECR,Error Counter Register (X*)"
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hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging\nThe counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached."
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bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
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newline
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter\nActual state of the Receive Error Counter values between 0 and 127."
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hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter\nActual state of the Transmit Error Counter values between 0 and 255.\nNote: When ASM (CANFD_CCCR[2]) is set the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected but CEL is still.."
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line.long 0x4 "CANFD_PSR,Protocol Status Register (XS*)"
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hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value\nPosition of the secondary sample point dened by the sum of the measured delay from CANx_TXD to CANx_RXD and TDCO (CANFD_TDCR[14:8]). The SSP position is in the data phase the number of minimum time quata.."
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bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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newline
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bitfld.long 0x4 13. "RFDF,Received a CAN FD Message\nThis bit is set independent of acceptance filtering.\nNote: Byte access: Reading byte 0 will reset RFDF reading bytes 3/2/1 has no impact." "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.."
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bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message\nThis bit is set together with RFDF independent of acceptance filtering.\nNote: Byte access: Reading byte 0 will reset RBRS reading bytes 3/2/1 has no impact." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set"
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newline
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bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message\nThis bit is set together with RFDF independent of acceptance filtering." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set"
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bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code\nType of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to 0 when a CAN FD format frame with its BRS flag set has been.." "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The CAN FD controller is not Bus_Off,1: The CAN FD controller is in Bus_Off state"
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bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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newline
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bitfld.long 0x4 5. "EP,Error Passive" "0: The CAN FD controller is in the Error_Active..,1: The CAN FD controller is in the Error_Passive.."
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bitfld.long 0x4 3.--4. "ACT,Activity\nMonitors the module's CAN communication state." "0: Synchronizing - node is synchronizing on CAN..,1: Idle - node is neither receiver nor transmitter,?,?"
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newline
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bitfld.long 0x4 0.--2. "LEC,Last Error Code\nThe LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error." "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,?,?,?,?,?,?"
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line.long 0x8 "CANFD_TDCR,Transmitter Delay Compensation Register (P*)"
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hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset\nOffset value dening the distance between the measured delay from CANx_TXD to CANx_RXD and the secondary sample point. Valid values are 0 to 127 mtq."
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hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length\nDenes the minimum value for the SSP position dominant edges on CANx_RXD that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when.."
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group.long 0x50++0xF
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line.long 0x0 "CANFD_IR,Interrupt Register"
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bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
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bitfld.long 0x0 28. "PED,Protocol Error in Data Phase\nNote: Data bit time is used." "0: No protocol error in data phase,1: Protocol error in data phase detected (DLEC.."
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newline
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bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase\nNote: Nominal bit time is used." "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
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bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY"
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newline
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bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
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bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
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newline
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bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
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bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred"
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newline
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bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer\nThe flag is set whenever a received message has been stored into a dedicated Rx Buffer." "0: No Rx Buffer updated,1: At least one received message stored into an Rx.."
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bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached"
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newline
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bitfld.long 0x0 17. "MRAF,Message RAM Access Failure\nThe flag is set when the Rx Handler\n• Has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering.." "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
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bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
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newline
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bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
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bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
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newline
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bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO ll level below watermark,1: Tx Event FIFO ll level reached watermark"
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bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element"
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newline
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bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
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bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
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newline
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bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed"
|
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bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received"
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newline
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bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
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bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
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newline
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bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 ll level below watermark,1: Rx FIFO 1 ll level reached watermark"
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bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
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newline
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bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
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bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
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newline
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bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 ll level below watermark,1: Rx FIFO 0 ll level reached watermark"
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bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
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line.long 0x4 "CANFD_IE,Interrupt Enable"
|
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bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
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bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
line.long 0x8 "CANFD_ILS,Interrupt Line Select"
|
|
bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
newline
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
newline
|
|
bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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|
newline
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bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
newline
|
|
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
newline
|
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bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
newline
|
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bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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|
newline
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bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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|
newline
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bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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|
newline
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bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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|
newline
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bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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|
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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newline
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bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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|
newline
|
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bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
newline
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bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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line.long 0xC "CANFD_ILE,Interrupt Line Enable"
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bitfld.long 0xC 1. "ENT1,Enable Interrupt Line 1" "0: Interrupt line canfd_int1 Disabled,1: Interrupt line canfd_int1 Enabled"
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bitfld.long 0xC 0. "ENT0,Enable Interrupt Line 0" "0: Interrupt line canfd_int0 Disabled,1: Interrupt line canfd_int0 Enabled"
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|
rgroup.long 0x80++0xB
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line.long 0x0 "CANFD_GFC,Global Filter Configuration (P*)"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard\nDenes how received messages with 11-bit IDs that do not match any element of the filter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
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|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended\nDenes how received messages with 29-bit IDs that do not match any element of the filter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
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|
newline
|
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bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
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bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs"
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line.long 0x4 "CANFD_SIDFC,Standard ID Filter Configuration (P*)"
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hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
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hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address\nStart address of standard Message ID filter list (32-bit word address refer to 錯誤! 找不到參照來源。)."
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line.long 0x8 "CANFD_XIDFC,Extended ID Filter Configuration (P*)"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
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hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address\nStart address of extended Message ID filter list (32-bit word address refer to 錯誤! 找不到參照來源。)."
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|
rgroup.long 0x90++0x7
|
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line.long 0x0 "CANFD_XIDAM,Extended ID AND Mask (P*)"
|
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hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask\nFor acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.."
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line.long 0x4 "CANFD_HPMS,High Priority Message Status"
|
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bitfld.long 0x4 15. "FLST,Filter List\nIndicates the filter list of the matching filter element." "0: Standard Filter List,1: Extended Filter List"
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hexmask.long.byte 0x4 8.--14. 1. "FIDX,Filter Index\nIndex of matching filter element. Range is 0 to LSS (CANFD_SIDFC[23:16]) - 1 or LSE (CANFD_XIDFC[22:16]) - 1"
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|
newline
|
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bitfld.long 0x4 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,?,?"
|
|
hexmask.long.byte 0x4 0.--5. 1. "BIDX,Buffer Index"
|
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group.long 0x98++0x7
|
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line.long 0x0 "CANFD_NDAT1,New Data 1"
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hexmask.long 0x0 0.--31. 1. "NDn,New Data\nThe register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
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line.long 0x4 "CANFD_NDAT2,New Data 2"
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hexmask.long 0x4 0.--31. 1. "NDn,New Data\nThe register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
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|
rgroup.long 0xA0++0x7
|
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line.long 0x0 "CANFD_RXF0C,Rx FIFO 0 Configuration (P*)"
|
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bitfld.long 0x0 31. "F0OM,FIFO 0 Operation Mode\nFIFO 0 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
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hexmask.long.byte 0x0 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
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|
newline
|
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hexmask.long.byte 0x0 16.--22. 1. "F0S,Rx FIFO 0 Size\nThe Rx FIFO 0 elements are indexed from 0 to F0S - 1"
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hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address\nStart address of Rx FIFO 0 in Message RAM (32-bit word address)."
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line.long 0x4 "CANFD_RXF0S,Rx FIFO 0 Status"
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bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "?,1: Rx FIFO 0 message lost also set after write.."
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|
bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
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|
newline
|
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hexmask.long.byte 0x4 16.--21. 1. "F0PI,Rx FIFO 0 Put Index\nRx FIFO 0 write index pointer range 0 to 63."
|
|
hexmask.long.byte 0x4 8.--13. 1. "F0GI,Rx FIFO 0 Get Index\nRx FIFO 0 read index pointer range 0 to 63."
|
|
newline
|
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hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level\nNumber of elements stored in Rx FIFO 0 range 0 to 64"
|
|
group.long 0xA8++0x3
|
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line.long 0x0 "CANFD_RXF0A,Rx FIFO 0 Acknowledge"
|
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hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index F0GI (CANFD_RXF0S[13:8]).."
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rgroup.long 0xAC++0xB
|
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line.long 0x0 "CANFD_RXBC,Rx Buffer Configuration (P*)"
|
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hexmask.long.word 0x0 2.--15. 1. "RBSA,Rx Buffer Start Address\nCongures the start address of the Rx Buffers section in the Message RAM (32-bit word address)."
|
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line.long 0x4 "CANFD_RXF1C,Rx FIFO 1 Configuration (P*)"
|
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bitfld.long 0x4 31. "F1OM,FIFO 1 Operation Mode\nFIFO 1 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
|
|
hexmask.long.byte 0x4 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "F1S,Rx FIFO 1 Size\nThe Rx FIFO 1 elements are indexed from 0 to F1S - 1"
|
|
hexmask.long.word 0x4 2.--15. 1. "F1SA,Rx FIFO 1 Start Address\nStart address of Rx FIFO 1 in Message RAM (32-bit word address refer to 錯誤! 找不到參照來源。)."
|
|
line.long 0x8 "CANFD_RXF1S,Rx FIFO 1 Status"
|
|
bitfld.long 0x8 25. "RF1L,Rx FIFO 1 Message Lost" "?,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x8 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "F1PI,Rx FIFO 1 Put Index\nRx FIFO 1 write index pointer range 0 to 63."
|
|
hexmask.long.byte 0x8 8.--13. 1. "F1GI,Rx FIFO 1 Get Index\nRx FIFO 1 read index pointer range 0 to 63."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level\nNumber of elements stored in Rx FIFO 1 range 0 to 64"
|
|
group.long 0xB8++0x3
|
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line.long 0x0 "CANFD_RXF1A,Rx FIFO 1 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index F1GI (CANFD_RXF1S[13:8]).."
|
|
rgroup.long 0xBC++0x13
|
|
line.long 0x0 "CANFD_RXESC,Rx Buffer / FIFO Element Size Configuration (P*)"
|
|
bitfld.long 0x0 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
|
|
bitfld.long 0x0 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "F0DS,Rx FIFO 0 Data Field Size\nNote: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO only the number of bytes as configured by CANFD_RXESC are stored to the Rx Buffer.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
|
|
line.long 0x4 "CANFD_TXBC,Tx Buffer Configuration (P*)"
|
|
bitfld.long 0x4 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
|
|
hexmask.long.byte 0x4 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x4 2.--15. 1. "TBSA,Tx Buffers Start Address\nStart address of Tx Buffers section in Message RAM (32-bit word address refer to 錯誤! 找不到參照來源。).\nNote: The sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous.."
|
|
line.long 0x8 "CANFD_TXFQS,Tx FIFO/Queue Status"
|
|
bitfld.long 0x8 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full"
|
|
hexmask.long.byte 0x8 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index\nTx FIFO/Queue write index pointer range 0 to 31."
|
|
newline
|
|
hexmask.long.byte 0x8 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x8 0.--5. 1. "TFFL,Tx FIFO Free Level\nNote: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers.\nExample: For.."
|
|
line.long 0xC "CANFD_TXESC,Tx Buffer Element Size Configuration (P*)"
|
|
bitfld.long 0xC 0.--2. "TBDS,Tx Buffer Data Field Size\nNote: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TBDS (CANFD_TXESC[2:0]) the bytes not defined by the Tx Buffer are transmitted as 0xCC.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
|
|
line.long 0x10 "CANFD_TXBRP,Tx Buffer Request Pending"
|
|
hexmask.long 0x10 0.--31. 1. "TRPn,Transmission Request PendingEach Tx Buffer has its own Transmission Request Pending bit The bits are set via register CANFD_TXBAR The bits are reset after a requested transmission has completed or has been cancelled via register.."
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "CANFD_TXBAR,Tx Buffer Add Request"
|
|
hexmask.long 0x0 0.--31. 1. "ARn,Add RequestEach Tx Buffer has its own Add Request bit Writing a 1 will set the corresponding Add Request bit; writing a 0 has no impact This enables the Host to set transmission requests for multiple Tx Buffers with one write to CANFD_TXBAR.."
|
|
line.long 0x4 "CANFD_TXBCR,Tx Buffer Cancellation Request"
|
|
hexmask.long 0x4 0.--31. 1. "CRn,Cancellation Request\nEach Tx Buffer has its own Cancellation Request bit. Writing a 1 will set the corresponding Cancellation Request bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one.."
|
|
rgroup.long 0xD8++0x7
|
|
line.long 0x0 "CANFD_TXBTO,Tx Buffer Transmission Occurred"
|
|
hexmask.long 0x0 0.--31. 1. "TOn,Transmission Occurred\nEach Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to.."
|
|
line.long 0x4 "CANFD_TXBCF,Tx Buffer Cancellation Finished"
|
|
hexmask.long 0x4 0.--31. 1. "CFn,Cancellation Finished\nEach Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a cancellation was requested via CANFD_TXBCR. In case the corresponding CANFD_TXBRP bit was not set.."
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "CANFD_TXBTIE,Tx Buffer Transmission Interrupt Enable"
|
|
hexmask.long 0x0 0.--31. 1. "TIEn,Transmission Interrupt Enable\nEach Tx Buffer has its own Transmission Interrupt Enable bit."
|
|
line.long 0x4 "CANFD_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
|
|
hexmask.long 0x4 0.--31. 1. "CFIEn,Cancellation Finished Interrupt Enable\nEach Tx Buffer has its own Cancellation Finished Interrupt Enable bit."
|
|
rgroup.long 0xF0++0x7
|
|
line.long 0x0 "CANFD_TXEFC,Tx Event FIFO Configuration (P*)"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWN,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size\nThe Tx Event FIFO elements are indexed from 0 to EFS - 1"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address\nStart address of Tx Event FIFO in Message RAM (32-bit word address refer to 錯誤! 找不到參照來源。)."
|
|
line.long 0x4 "CANFD_TXEFS,Tx Event FIFO Status"
|
|
bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element Lost\nThis bit is a copy of interrupt flag TEFL (CANFD_IR[15]). When TEFL is reset this bit is also reset." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
|
|
bitfld.long 0x4 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO Put Index\nTx Event FIFO write index pointer range 0 to 31"
|
|
hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index\nTx Event FIFO read index pointer range 0 to 31"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level\nNumber of elements stored in Tx Event FIFO range 0 to 32"
|
|
group.long 0xF8++0x7
|
|
line.long 0x0 "CANFD_TXEFA,Tx Event FIFO Acknowledge"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index\nAfter the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index EFGI.."
|
|
line.long 0x4 "CANFD_STSEL,Tx Rx Signal Type Selection Register"
|
|
bitfld.long 0x4 8.--9. "RXSS,CAN Rx Signal Selection" "0: from CAN_Rx pin,1: from ACMP0 output,?,?"
|
|
bitfld.long 0x4 4.--6. "TXLS,CAN TxL Signal Type" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "TXHS,CAN TxH Signal Type" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "CANFD2"
|
|
base ad:0x40028000
|
|
rgroup.long 0xC++0xB
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line.long 0x0 "CANFD_DBTP,Data Bit Timing Prescaler Register (P*)"
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bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation Disabled,1: Transmitter Delay Compensation Enabled"
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hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
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hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
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hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
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hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data Re-Synchronization Jump Width"
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line.long 0x4 "CANFD_TEST,Test Register (P*)"
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bitfld.long 0x4 7. "RX,Receive Pin\nMonitors the actual value of pin CANx_RXD" "0: The CAN bus is dominant (CANx_RXD = 0),1: The CAN bus is recessive (CANx_RXD = 1)"
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bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CANx_TXD controlled by the CAN Core..,1: Sample Point can be monitored at pin CANx_TXD,?,?"
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bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0: Reset value Loop Back Mode Disabled,1: Loop Back Mode Enabled (refer to TEST Mode in.."
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line.long 0x8 "CANFD_RWD,RAM Watchdog (P*)"
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hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value \nActual Message RAM Watchdog Counter Value."
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hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration \nStart value of the Message RAM Watchdog Counter. With the reset value of 00 the counter is disabled."
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group.long 0x18++0x3
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line.long 0x0 "CANFD_CCCR,CC Control Register (Pp*)"
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bitfld.long 0x0 15. "NISO,Non ISO Operation\nIf this bit is set the CAN FD controller uses the CAN FD frame format as specied by the Bosch CAN FD Specication V1.0." "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
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bitfld.long 0x0 14. "TXP,Transmit Pause\nIf this bit is set the CAN FD controller pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (refer to Tx Handling section)." "0: Transmit pause Disabled,1: Transmit pause Enabled"
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bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering Disabled,1: Two consecutive dominant tq required to detect.."
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bitfld.long 0x0 12. "PXHD,Protocol Exception Handling Disable\nNote: When protocol exception handling is disabled the controller will transmit an error frame when it detects a protocol exception condition." "0: Protocol exception handling Enabled,1: Protocol exception handling Disabled"
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bitfld.long 0x0 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions Disabled,1: Bit rate switching for transmissions Enabled"
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bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0: FD operation Disabled,1: FD operation Enabled"
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bitfld.long 0x0 7. "TEST,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
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bitfld.long 0x0 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission Disabled"
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bitfld.long 0x0 5. "MON,Bus Monitoring Mode\nBit MON can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the Host at any time." "0: Bus Monitoring Mode Disabled,1: Bus Monitoring Mode Enabled"
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bitfld.long 0x0 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.."
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bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: The Controller may be set in power down by.."
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bitfld.long 0x0 2. "ASM,Restricted Operation Mode\nBit ASM can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the software at any time. This bit will be set automatically set to 1 when the Tx handler was not able to read data from the.." "0: Normal CAN operation,1: Restricted Operation Mode active"
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bitfld.long 0x0 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
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bitfld.long 0x0 0. "INIT,Initialization\nNote: Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been.." "0: Normal Operation,1: Initialization is started"
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rgroup.long 0x1C++0x13
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line.long 0x0 "CANFD_NBTP,Nominal Bit Timing Prescaler Register (P*)"
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hexmask.long.byte 0x0 25.--31. 1. "NSJW,Nominal Re-Synchronization Jump Width"
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hexmask.long.word 0x0 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler\nThe value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual.."
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hexmask.long.byte 0x0 8.--15. 1. "NTSEG1,Nominal Time Segment before Sample Point"
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hexmask.long.byte 0x0 0.--6. 1. "NTSEG2,Nominal Time Segment after Sample Point\nNote: With a CAN Core clock (cclk) of 8 MHz the reset value of 0x06000A03 configures the controller for a bit rate of 500 kBit/s."
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line.long 0x4 "CANFD_TSCC,Timestamp Counter Configuration (P*)"
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hexmask.long.byte 0x4 16.--19. 1. "TCP,Timestamp Counter Prescaler\nCongures the timestamp and timeout counters time unit in multiples of CAN bit times [ 1...16 ]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."
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bitfld.long 0x4 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,?,?"
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line.long 0x8 "CANFD_TSCV,Timestamp Counter Value (C*)"
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hexmask.long.word 0x8 0.--15. 1. "TSC,Timestamp Counter\nNote: A 'wrap around' is a change of the Timestamp Counter value from non-zero to 0 not caused by write access to CANFD_TSCV."
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line.long 0xC "CANFD_TOCC,Timeout Counter Configuration (P*)"
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hexmask.long.word 0xC 16.--31. 1. "TOP,Timeout Period\nStart value of the Timeout Counter (down-counter). Congures the Timeout Period."
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bitfld.long 0xC 1.--2. "TOS,Timeout Select\nWhen operating in Continuous mode a write to CANFD_TOCV presets the counter to the value congured by TOP (CANFD_TOCC[31:16]) and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs an empty FIFO.." "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,?,?"
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bitfld.long 0xC 0. "ETOC,Enable Timeout Counter\nNote: For use of timeout function with CAN FD refer to Timeout Counter section錯誤! 找不到參照來源。." "0: Timeout Counter Disabled,1: Timeout Counter Enabled"
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line.long 0x10 "CANFD_TOCV,Timeout Counter Value (C*)"
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hexmask.long.word 0x10 0.--15. 1. "TOC,Timeout Counter\nThe filed is decremented in multiples of CAN bit times [ 1...16 ] depending on the configuration of TCP (CANFD_TSCC[19:16]). When decremented to 0 interrupt flag TOO (CANFD_IR[18]) is set and the timeout counter is stopped. Start.."
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rgroup.long 0x40++0xB
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line.long 0x0 "CANFD_ECR,Error Counter Register (X*)"
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hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging\nThe counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached."
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bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter\nActual state of the Receive Error Counter values between 0 and 127."
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hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter\nActual state of the Transmit Error Counter values between 0 and 255.\nNote: When ASM (CANFD_CCCR[2]) is set the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected but CEL is still.."
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line.long 0x4 "CANFD_PSR,Protocol Status Register (XS*)"
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hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value\nPosition of the secondary sample point dened by the sum of the measured delay from CANx_TXD to CANx_RXD and TDCO (CANFD_TDCR[14:8]). The SSP position is in the data phase the number of minimum time quata.."
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bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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bitfld.long 0x4 13. "RFDF,Received a CAN FD Message\nThis bit is set independent of acceptance filtering.\nNote: Byte access: Reading byte 0 will reset RFDF reading bytes 3/2/1 has no impact." "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.."
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bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message\nThis bit is set together with RFDF independent of acceptance filtering.\nNote: Byte access: Reading byte 0 will reset RBRS reading bytes 3/2/1 has no impact." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set"
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bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message\nThis bit is set together with RFDF independent of acceptance filtering." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set"
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bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code\nType of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to 0 when a CAN FD format frame with its BRS flag set has been.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The CAN FD controller is not Bus_Off,1: The CAN FD controller is in Bus_Off state"
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bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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bitfld.long 0x4 5. "EP,Error Passive" "0: The CAN FD controller is in the Error_Active..,1: The CAN FD controller is in the Error_Passive.."
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bitfld.long 0x4 3.--4. "ACT,Activity\nMonitors the module's CAN communication state." "0: Synchronizing - node is synchronizing on CAN..,1: Idle - node is neither receiver nor transmitter,?,?"
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bitfld.long 0x4 0.--2. "LEC,Last Error Code\nThe LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error." "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,?,?,?,?,?,?"
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line.long 0x8 "CANFD_TDCR,Transmitter Delay Compensation Register (P*)"
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hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset\nOffset value dening the distance between the measured delay from CANx_TXD to CANx_RXD and the secondary sample point. Valid values are 0 to 127 mtq."
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hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length\nDenes the minimum value for the SSP position dominant edges on CANx_RXD that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when.."
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group.long 0x50++0xF
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line.long 0x0 "CANFD_IR,Interrupt Register"
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bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
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bitfld.long 0x0 28. "PED,Protocol Error in Data Phase\nNote: Data bit time is used." "0: No protocol error in data phase,1: Protocol error in data phase detected (DLEC.."
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bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase\nNote: Nominal bit time is used." "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
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bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY"
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bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
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bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
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bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
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bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred"
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bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer\nThe flag is set whenever a received message has been stored into a dedicated Rx Buffer." "0: No Rx Buffer updated,1: At least one received message stored into an Rx.."
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bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached"
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bitfld.long 0x0 17. "MRAF,Message RAM Access Failure\nThe flag is set when the Rx Handler\n• Has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering.." "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
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bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
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bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
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bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
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bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO ll level below watermark,1: Tx Event FIFO ll level reached watermark"
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bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element"
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bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
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bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
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bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed"
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bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received"
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bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
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bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
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bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 ll level below watermark,1: Rx FIFO 1 ll level reached watermark"
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bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
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bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
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bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
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bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 ll level below watermark,1: Rx FIFO 0 ll level reached watermark"
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bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
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line.long 0x4 "CANFD_IE,Interrupt Enable"
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bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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line.long 0x8 "CANFD_ILS,Interrupt Line Select"
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bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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newline
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bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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newline
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bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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newline
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bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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newline
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bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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line.long 0xC "CANFD_ILE,Interrupt Line Enable"
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bitfld.long 0xC 1. "ENT1,Enable Interrupt Line 1" "0: Interrupt line canfd_int1 Disabled,1: Interrupt line canfd_int1 Enabled"
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bitfld.long 0xC 0. "ENT0,Enable Interrupt Line 0" "0: Interrupt line canfd_int0 Disabled,1: Interrupt line canfd_int0 Enabled"
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rgroup.long 0x80++0xB
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line.long 0x0 "CANFD_GFC,Global Filter Configuration (P*)"
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bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard\nDenes how received messages with 11-bit IDs that do not match any element of the filter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
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bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended\nDenes how received messages with 29-bit IDs that do not match any element of the filter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
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newline
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bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
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bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs"
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line.long 0x4 "CANFD_SIDFC,Standard ID Filter Configuration (P*)"
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hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
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hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address\nStart address of standard Message ID filter list (32-bit word address refer to 錯誤! 找不到參照來源。)."
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line.long 0x8 "CANFD_XIDFC,Extended ID Filter Configuration (P*)"
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hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
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hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address\nStart address of extended Message ID filter list (32-bit word address refer to 錯誤! 找不到參照來源。)."
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rgroup.long 0x90++0x7
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line.long 0x0 "CANFD_XIDAM,Extended ID AND Mask (P*)"
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hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask\nFor acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.."
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line.long 0x4 "CANFD_HPMS,High Priority Message Status"
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bitfld.long 0x4 15. "FLST,Filter List\nIndicates the filter list of the matching filter element." "0: Standard Filter List,1: Extended Filter List"
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hexmask.long.byte 0x4 8.--14. 1. "FIDX,Filter Index\nIndex of matching filter element. Range is 0 to LSS (CANFD_SIDFC[23:16]) - 1 or LSE (CANFD_XIDFC[22:16]) - 1"
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newline
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bitfld.long 0x4 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,?,?"
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hexmask.long.byte 0x4 0.--5. 1. "BIDX,Buffer Index"
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group.long 0x98++0x7
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line.long 0x0 "CANFD_NDAT1,New Data 1"
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hexmask.long 0x0 0.--31. 1. "NDn,New Data\nThe register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
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line.long 0x4 "CANFD_NDAT2,New Data 2"
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hexmask.long 0x4 0.--31. 1. "NDn,New Data\nThe register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
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rgroup.long 0xA0++0x7
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line.long 0x0 "CANFD_RXF0C,Rx FIFO 0 Configuration (P*)"
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bitfld.long 0x0 31. "F0OM,FIFO 0 Operation Mode\nFIFO 0 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
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hexmask.long.byte 0x0 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
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newline
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hexmask.long.byte 0x0 16.--22. 1. "F0S,Rx FIFO 0 Size\nThe Rx FIFO 0 elements are indexed from 0 to F0S - 1"
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hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address\nStart address of Rx FIFO 0 in Message RAM (32-bit word address)."
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line.long 0x4 "CANFD_RXF0S,Rx FIFO 0 Status"
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bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "?,1: Rx FIFO 0 message lost also set after write.."
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bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
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newline
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hexmask.long.byte 0x4 16.--21. 1. "F0PI,Rx FIFO 0 Put Index\nRx FIFO 0 write index pointer range 0 to 63."
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hexmask.long.byte 0x4 8.--13. 1. "F0GI,Rx FIFO 0 Get Index\nRx FIFO 0 read index pointer range 0 to 63."
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newline
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hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level\nNumber of elements stored in Rx FIFO 0 range 0 to 64"
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group.long 0xA8++0x3
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line.long 0x0 "CANFD_RXF0A,Rx FIFO 0 Acknowledge"
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hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index F0GI (CANFD_RXF0S[13:8]).."
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rgroup.long 0xAC++0xB
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line.long 0x0 "CANFD_RXBC,Rx Buffer Configuration (P*)"
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hexmask.long.word 0x0 2.--15. 1. "RBSA,Rx Buffer Start Address\nCongures the start address of the Rx Buffers section in the Message RAM (32-bit word address)."
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line.long 0x4 "CANFD_RXF1C,Rx FIFO 1 Configuration (P*)"
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bitfld.long 0x4 31. "F1OM,FIFO 1 Operation Mode\nFIFO 1 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
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hexmask.long.byte 0x4 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
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newline
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hexmask.long.byte 0x4 16.--22. 1. "F1S,Rx FIFO 1 Size\nThe Rx FIFO 1 elements are indexed from 0 to F1S - 1"
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hexmask.long.word 0x4 2.--15. 1. "F1SA,Rx FIFO 1 Start Address\nStart address of Rx FIFO 1 in Message RAM (32-bit word address refer to 錯誤! 找不到參照來源。)."
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line.long 0x8 "CANFD_RXF1S,Rx FIFO 1 Status"
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bitfld.long 0x8 25. "RF1L,Rx FIFO 1 Message Lost" "?,1: Rx FIFO 1 message lost also set after write.."
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bitfld.long 0x8 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
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newline
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hexmask.long.byte 0x8 16.--21. 1. "F1PI,Rx FIFO 1 Put Index\nRx FIFO 1 write index pointer range 0 to 63."
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hexmask.long.byte 0x8 8.--13. 1. "F1GI,Rx FIFO 1 Get Index\nRx FIFO 1 read index pointer range 0 to 63."
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newline
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hexmask.long.byte 0x8 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level\nNumber of elements stored in Rx FIFO 1 range 0 to 64"
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group.long 0xB8++0x3
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line.long 0x0 "CANFD_RXF1A,Rx FIFO 1 Acknowledge"
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hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index F1GI (CANFD_RXF1S[13:8]).."
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rgroup.long 0xBC++0x13
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line.long 0x0 "CANFD_RXESC,Rx Buffer / FIFO Element Size Configuration (P*)"
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bitfld.long 0x0 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 0.--2. "F0DS,Rx FIFO 0 Data Field Size\nNote: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO only the number of bytes as configured by CANFD_RXESC are stored to the Rx Buffer.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
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line.long 0x4 "CANFD_TXBC,Tx Buffer Configuration (P*)"
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bitfld.long 0x4 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
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hexmask.long.byte 0x4 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
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newline
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hexmask.long.byte 0x4 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
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hexmask.long.word 0x4 2.--15. 1. "TBSA,Tx Buffers Start Address\nStart address of Tx Buffers section in Message RAM (32-bit word address refer to 錯誤! 找不到參照來源。).\nNote: The sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous.."
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line.long 0x8 "CANFD_TXFQS,Tx FIFO/Queue Status"
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bitfld.long 0x8 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full"
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hexmask.long.byte 0x8 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index\nTx FIFO/Queue write index pointer range 0 to 31."
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newline
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hexmask.long.byte 0x8 8.--12. 1. "TFGI,Tx FIFO Get Index"
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hexmask.long.byte 0x8 0.--5. 1. "TFFL,Tx FIFO Free Level\nNote: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers.\nExample: For.."
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line.long 0xC "CANFD_TXESC,Tx Buffer Element Size Configuration (P*)"
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bitfld.long 0xC 0.--2. "TBDS,Tx Buffer Data Field Size\nNote: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TBDS (CANFD_TXESC[2:0]) the bytes not defined by the Tx Buffer are transmitted as 0xCC.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
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line.long 0x10 "CANFD_TXBRP,Tx Buffer Request Pending"
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hexmask.long 0x10 0.--31. 1. "TRPn,Transmission Request PendingEach Tx Buffer has its own Transmission Request Pending bit The bits are set via register CANFD_TXBAR The bits are reset after a requested transmission has completed or has been cancelled via register.."
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group.long 0xD0++0x7
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line.long 0x0 "CANFD_TXBAR,Tx Buffer Add Request"
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hexmask.long 0x0 0.--31. 1. "ARn,Add RequestEach Tx Buffer has its own Add Request bit Writing a 1 will set the corresponding Add Request bit; writing a 0 has no impact This enables the Host to set transmission requests for multiple Tx Buffers with one write to CANFD_TXBAR.."
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line.long 0x4 "CANFD_TXBCR,Tx Buffer Cancellation Request"
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hexmask.long 0x4 0.--31. 1. "CRn,Cancellation Request\nEach Tx Buffer has its own Cancellation Request bit. Writing a 1 will set the corresponding Cancellation Request bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one.."
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rgroup.long 0xD8++0x7
|
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line.long 0x0 "CANFD_TXBTO,Tx Buffer Transmission Occurred"
|
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hexmask.long 0x0 0.--31. 1. "TOn,Transmission Occurred\nEach Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to.."
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line.long 0x4 "CANFD_TXBCF,Tx Buffer Cancellation Finished"
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hexmask.long 0x4 0.--31. 1. "CFn,Cancellation Finished\nEach Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a cancellation was requested via CANFD_TXBCR. In case the corresponding CANFD_TXBRP bit was not set.."
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group.long 0xE0++0x7
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line.long 0x0 "CANFD_TXBTIE,Tx Buffer Transmission Interrupt Enable"
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hexmask.long 0x0 0.--31. 1. "TIEn,Transmission Interrupt Enable\nEach Tx Buffer has its own Transmission Interrupt Enable bit."
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line.long 0x4 "CANFD_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
|
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hexmask.long 0x4 0.--31. 1. "CFIEn,Cancellation Finished Interrupt Enable\nEach Tx Buffer has its own Cancellation Finished Interrupt Enable bit."
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rgroup.long 0xF0++0x7
|
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line.long 0x0 "CANFD_TXEFC,Tx Event FIFO Configuration (P*)"
|
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hexmask.long.byte 0x0 24.--29. 1. "EFWN,Event FIFO Watermark"
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hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size\nThe Tx Event FIFO elements are indexed from 0 to EFS - 1"
|
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newline
|
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hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address\nStart address of Tx Event FIFO in Message RAM (32-bit word address refer to 錯誤! 找不到參照來源。)."
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line.long 0x4 "CANFD_TXEFS,Tx Event FIFO Status"
|
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bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element Lost\nThis bit is a copy of interrupt flag TEFL (CANFD_IR[15]). When TEFL is reset this bit is also reset." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
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bitfld.long 0x4 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
|
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newline
|
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hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO Put Index\nTx Event FIFO write index pointer range 0 to 31"
|
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hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index\nTx Event FIFO read index pointer range 0 to 31"
|
|
newline
|
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hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level\nNumber of elements stored in Tx Event FIFO range 0 to 32"
|
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group.long 0xF8++0x7
|
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line.long 0x0 "CANFD_TXEFA,Tx Event FIFO Acknowledge"
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hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index\nAfter the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index EFGI.."
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line.long 0x4 "CANFD_STSEL,Tx Rx Signal Type Selection Register"
|
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bitfld.long 0x4 8.--9. "RXSS,CAN Rx Signal Selection" "0: from CAN_Rx pin,1: from ACMP0 output,?,?"
|
|
bitfld.long 0x4 4.--6. "TXLS,CAN TxL Signal Type" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x4 0.--2. "TXHS,CAN TxH Signal Type" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
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tree.end
|
|
tree "CLK (Clock Controller)"
|
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base ad:0x40000200
|
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group.long 0x0++0x27
|
|
line.long 0x0 "CLK_PWRCTL,System Power-down Control Register"
|
|
bitfld.long 0x0 31. "HXTMD,HXT Bypass Mode (Write Protect)\nNote 2: This bit is write protected. Refer to the SYS_REGCTL register." "0: HXT work as crystal mode. PF.2 and PF.3 are..,1: HXT works as external clock mode. PF.3 is.."
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bitfld.long 0x0 16.--17. "HIRCSTBS,HIRC Stable Count Select (Write Protect )\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: HIRC48M stable count is 1024 clocks,1: HIRC48M stable count is 512 clocks,?,?"
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newline
|
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bitfld.long 0x0 13.--15. "LXTGAIN,LXT Gain Control Bit (Write Protect)\nUser can select oscillator gain according to crystal external loading and operating temperature range. The greater gain value corresponding to stronger driving capability and higher power consumption.\nNote:.." "0: L0 mode (ESR=35K; CL =25pF),1: L1 mode (ESR=35K; CL =25pF),?,?,?,?,?,?"
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bitfld.long 0x0 10.--12. "HXTGAIN,HXT Gain Control Bit (Write Protect)\nGain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled crystal will consume more power than gain control off. \nNote: These bits are write.." "0: HXT frequency is from 4 MHz to 8 MHz,1: HXT frequency is from 8 MHz to 12 MHz,?,?,?,?,?,?"
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newline
|
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bitfld.long 0x0 7. "PDEN,System Power-down Enable (Write Protect)\nWhen this bit is set to 1 Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.\nWhen chip wakes up from Power-down mode this bit.." "0: Chip operating normally or chip in idle mode..,1: Chip waits CPU sleep command WFI and then enters.."
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|
bitfld.long 0x0 6. "PDWKIF,Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event' which indicates that resume from Power-down mode' \nThe flag is set if the BOD CLKFAIL EINT GPIO TMR WDT UART USCI I2C or ACMP wake-up occurred.\nNote 1: This bit.." "?,1: This bit can be cleared by software writing 1"
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|
newline
|
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bitfld.long 0x0 5. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote 1: The interrupt will occur when both PDWKIF and PDWKIEN are high.\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Power-down mode wake-up interrupt Disabled,1: The interrupt will occur when both PDWKIF and.."
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|
bitfld.long 0x0 3. "LIRCEN,LIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 38.4 kHz internal low speed RC oscillator (LIRC)..,1: 38.4 kHz internal low speed RC oscillator (LIRC).."
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newline
|
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bitfld.long 0x0 2. "HIRCEN,HIRC Enable Bit (Write Protect)\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: HIRC cannot be disabled if HCLK clock source is selected from HIRC or PLL (clock source from HIRC) or Flash ISP peripheral clock.." "0: 48 MHz internal high speed RC oscillator (HIRC)..,1: This bit is write protected"
|
|
bitfld.long 0x0 1. "LXTEN,LXT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 32.768 kHz External Low Speed Crystal (LXT)..,1: 32.768 kHz External Low Speed Crystal (LXT).."
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|
newline
|
|
bitfld.long 0x0 0. "HXTEN,HXT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 4~24 MHz External High Speed Crystal (HXT)..,1: 4~24 MHz External High Speed Crystal (HXT) Enabled"
|
|
line.long 0x4 "CLK_AHBCLK,AHB Devices Clock Enable Control Register"
|
|
bitfld.long 0x4 29. "GPIOFCKEN,General Purpose I/O PF Group Clock Enable Bit" "0: GPIO PF group clock Disabled,1: GPIO PF group clock Enabled"
|
|
bitfld.long 0x4 27. "GPIODCKEN,General Purpose I/O PD Group Clock Enable Bit" "0: GPIO PD group clock Disabled,1: GPIO PD group clock Enabled"
|
|
newline
|
|
bitfld.long 0x4 26. "GPIOCCKEN,General Purpose I/O PC Group Clock Enable Bit" "0: GPIO PC group clock Disabled,1: GPIO PC group clock Enabled"
|
|
bitfld.long 0x4 25. "GPIOBCKEN,General Purpose I/O PB Group Clock Enable Bit" "0: GPIO PB group clock Disabled,1: GPIO PB group clock Enabled"
|
|
newline
|
|
bitfld.long 0x4 24. "GPIOACKEN,General Purpose I/O PA Group Clock Enable Bit" "0: GPIO PA group clock Disabled,1: GPIO PA group clock Enabled"
|
|
bitfld.long 0x4 18. "CANRAM2EN,CANFD2 Message SRAM Clock Enable Bit" "0: CANFD2 Message SRAM clock Disabled,1: CANFD2 Message SRAM clock Enabled"
|
|
newline
|
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bitfld.long 0x4 17. "CANRAM1EN,CANFD1 Message SRAM Clock Enable Bit" "0: CANFD1 Message SRAM clock Disabled,1: CANFD1 Message SRAM clock Enabled"
|
|
bitfld.long 0x4 16. "CANRAM0EN,CANFD0 Message SRAM Clock Enable Bit" "0: CANFD0 Message SRAM clock Disabled,1: CANFD0 Message SRAM clock Enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "FMCIDLE,Flash Memory Controller Clock Enable Bit in IDLE Mode" "0: FMC peripheral clock Disabled when chip..,1: FMC peripheral clock Enabled when chip operating.."
|
|
bitfld.long 0x4 10. "CANFD2CKEN,CANFD2 Clock Enable Bit" "0: CANFD2 clock Disabled,1: CANFD2 clock Enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "CANFD1CKEN,CANFD1 Clock Enable Bit" "0: CANFD1 clock Disabled,1: CANFD1 clock Enabled"
|
|
bitfld.long 0x4 8. "CANFD0CKEN,CANFD0 Clock Enable Bit" "0: CANFD0 clock Disabled,1: CANFD0 clock Enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "CRCCKEN,CRC Generator Controller Clock Enable Bit" "0: CRC peripheral clock Disabled,1: CRC peripheral clock Enabled"
|
|
bitfld.long 0x4 4. "STCKEN,System Tick Clock Enable Bit" "0: System tick clock Disabled,1: System tick clock Enabled"
|
|
newline
|
|
bitfld.long 0x4 2. "ISPCKEN,Flash ISP Controller Clock Enable Bit" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled"
|
|
bitfld.long 0x4 1. "PDMA0CKEN,PDMA0 Controller Clock Enable Bit" "0: PDMA0 peripheral clock Disabled,1: PDMA0 peripheral clock Enabled"
|
|
line.long 0x8 "CLK_APBCLK0,APB Devices Clock Enable Control Register 0"
|
|
bitfld.long 0x8 30. "ACMP01CKEN,Analog Comparator 0/1 Clock Enable Bit" "0: Analog comparator 0/1 clock Disabled,1: Analog comparator 0/1 clock Enabled"
|
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bitfld.long 0x8 28. "ADC0CKEN,Analog-digital-converter 0 Clock Enable Bit" "0: ADC0 clock Disabled,1: ADC0 clock Enabled"
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bitfld.long 0x8 17. "UART1CKEN,UART1 Clock Enable Bit" "0: UART1 clock Disabled,1: UART1 clock Enabled"
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bitfld.long 0x8 16. "UART0CKEN,UART0 Clock Enable Bit" "0: UART0 clock Disabled,1: UART0 clock Enabled"
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bitfld.long 0x8 12. "SPI0CKEN,SPI0 Clock Enable Bit" "0: SPI0 Clock Disabled,1: SPI0 Clock Enabled"
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bitfld.long 0x8 8. "I2C0CKEN,I2C0 Clock Enable Bit" "0: I2C0 Clock Disabled,1: I2C0 Clock Enabled"
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bitfld.long 0x8 6. "CLKOCKEN,CLKO Clock Enable Bit" "0: CLKO Clock Disabled,1: CLKO Clock Enabled"
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bitfld.long 0x8 5. "TMR3CKEN,Timer3 Clock Enable Bit" "0: Timer3 Clock Disabled,1: Timer3 Clock Enabled"
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bitfld.long 0x8 4. "TMR2CKEN,Timer2 Clock Enable Bit" "0: Timer2 Clock Disabled,1: Timer2 Clock Enabled"
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bitfld.long 0x8 3. "TMR1CKEN,Timer1 Clock Enable Bit" "0: Timer1 Clock Disabled,1: Timer1 Clock Enabled"
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bitfld.long 0x8 2. "TMR0CKEN,Timer0 Clock Enable Bit" "0: Timer0 Clock Disabled,1: Timer0 Clock Enabled"
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bitfld.long 0x8 1. "WWDTCKEN,Window Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Window Watchdog timer clock Disabled,1: Window Watchdog timer clock Enabled"
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bitfld.long 0x8 0. "WDTCKEN,Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Watchdog Timer Clock Disabled,1: Watchdog Timer Clock Enabled"
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line.long 0xC "CLK_APBCLK1,APB Devices Clock Enable Control Register 1"
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bitfld.long 0xC 17. "LLSI1CKEN,LLSI1 Clock Enable Bit" "0: LLSI1 clock Disabled,1: LLSI1 clock Enabled"
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bitfld.long 0xC 16. "LLSI0CKEN,LLSI0 Clock Enable Bit" "0: LLSI0 clock Disabled,1: LLSI0 clock Enabled"
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bitfld.long 0xC 9. "USCI1CKEN,USCI1 Clock Enable Bit" "0: USCI1 clock Disabled,1: USCI1 clock Enabled"
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bitfld.long 0xC 8. "USCI0CKEN,USCI0 Clock Enable Bit" "0: USCI0 clock Disabled,1: USCI0 clock Enabled"
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bitfld.long 0xC 4. "BPWM0CKEN,BPWM0 Clock Enable Bit" "0: BPWM0 clock Disabled,1: BPWM0 clock Enabled"
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bitfld.long 0xC 0. "PWM0CKEN,PWM0 Clock Enable Bit" "0: PWM0 clock Disabled,1: PWM0 clock Enabled"
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line.long 0x10 "CLK_CLKSEL0,Clock Source Select Control Register 0"
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bitfld.long 0x10 28.--29. "CANFD2SEL,CANFD2 Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL/2,?,?"
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bitfld.long 0x10 26.--27. "CANFD1SEL,CANFD1 Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL/2,?,?"
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bitfld.long 0x10 24.--25. "CANFD0SEL,CANFD0 Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL/2,?,?"
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bitfld.long 0x10 3.--5. "STCLKSEL,Cortex-M23 SysTick Clock Source Selection (Write Protect)\nNote 2: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from HXT,1: Clock source from LXT,2: These bits are write protected,?,?,?,?,?"
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bitfld.long 0x10 0.--2. "HCLKSEL,HCLK Clock Source Selection (Write Protect)\nBefore clock switching the related clock sources (both pre-select and new-select) must be turned on.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from HXT,1: Clock source from LXT,?,?,?,?,?,?"
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line.long 0x14 "CLK_CLKSEL1,Clock Source Select Control Register 1"
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bitfld.long 0x14 20.--22. "TMR3SEL,TIMER3 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 16.--18. "TMR2SEL,TIMER2 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 12.--14. "TMR1SEL,TIMER1 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 8.--10. "TMR0SEL,TIMER0 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 4.--6. "CLKOSEL,Clock Divider Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 2.--3. "WWDTSEL,Window Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "?,?,?,?"
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bitfld.long 0x14 0.--1. "WDTSEL,Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Reserved.,1: Clock source from 32.768 kHz external low speed..,?,?"
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line.long 0x18 "CLK_CLKSEL2,Clock Source Select Control Register 2"
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bitfld.long 0x18 24.--25. "SPI0SEL,SPI0 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2 clock,?,?"
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bitfld.long 0x18 2.--3. "UART1SEL,UART1 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL clock,?,?"
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bitfld.long 0x18 0.--1. "UART0SEL,UART0 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL clock,?,?"
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line.long 0x1C "CLK_CLKSEL3,Clock Source Select Control Register 3"
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bitfld.long 0x1C 6. "BPWM0SEL,BPWM0 Clock Source Selection\nThe peripheral clock source of BPWM0 is defined by BPWM0SEL." "0: Clock source from PLL,1: Clock source from PCLK0"
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bitfld.long 0x1C 4. "PWM0SEL,PWM0 Clock Source Selection\nThe peripheral clock source of PWM0 is defined by PWM0SEL." "0: Clock source from PLL,1: Clock source from PCLK0"
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bitfld.long 0x1C 0.--1. "ADC0SEL,ADC0 Clock Source Selection" "0: Reserved.,1: Clock source from PLL,?,?"
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line.long 0x20 "CLK_CLKDIV0,Clock Divider Number Register 0"
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hexmask.long.byte 0x20 16.--23. 1. "ADC0DIV,ADC0 Clock Divide Number From ADC0 Clock Source"
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hexmask.long.byte 0x20 12.--15. 1. "UART1DIV,UART1 Clock Divide Number From UART1 Clock Source"
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hexmask.long.byte 0x20 8.--11. 1. "UART0DIV,UART0 Clock Divide Number From UART0 Clock Source"
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hexmask.long.byte 0x20 0.--3. 1. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source"
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line.long 0x24 "CLK_CLKDIV1,Clock Divider Number Register 1"
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hexmask.long.byte 0x24 8.--11. 1. "CANFD2DIV,CANFD2 Clock Divide Number From CANFD2 Clock Source"
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hexmask.long.byte 0x24 4.--7. 1. "CANFD1DIV,CANFD1 Clock Divide Number From CANFD1 Clock Source"
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hexmask.long.byte 0x24 0.--3. 1. "CANFD0DIV,CANFD0 Clock Divide Number From CANFD0 Clock Source"
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group.long 0x34++0x3
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line.long 0x0 "CLK_PCLKDIV,APB Clock Divider Register"
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bitfld.long 0x0 4.--6. "APB1DIV,APB1 Clock Divider\nAPB1 clock can be divided from HCLK." "0: PCLK1 frequency is HCLK,1: PCLK1 frequency is 1/2 HCLK,?,?,?,?,?,?"
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bitfld.long 0x0 0.--2. "APB0DIV,APB0 Clock Divider\nAPB0 clock can be divided from HCLK." "0: PCLK0 frequency is HCLK,1: PCLK0 frequency is 1/2 HCLK,?,?,?,?,?,?"
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group.long 0x40++0x3
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line.long 0x0 "CLK_PLLCTL,PLL Control Register"
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bitfld.long 0x0 23. "STBSEL,PLL Stable Counter Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: PLL stable time is 6144 PLL source clock..,1: PLL stable time is 12288 PLL source clock.."
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bitfld.long 0x0 19. "PLLSRC,PLL Source Clock Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: PLL source clock from external 4~24 MHz..,1: PLL source clock from 48 MHz internal high-speed.."
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bitfld.long 0x0 18. "OE,PLL FOUT Enable Control (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: PLL FOUT Enabled,1: PLL FOUT is fixed low"
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bitfld.long 0x0 17. "BP,PLL Bypass Control (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: PLL is in normal mode (default),1: PLL clock output is same as PLL input clock FIN"
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bitfld.long 0x0 16. "PD,Power-down Mode (Write Protect)\nIf set PDEN(CLK_PWRCTL[7]) bit to 1 the PLL will enter Power-down mode too.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: PLL is in normal mode,1: PLL is in Power-down mode (default)"
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bitfld.long 0x0 14.--15. "OUTDIV,PLL Output Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0,1,2,3"
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hexmask.long.byte 0x0 9.--13. 1. "INDIV,PLL Input Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
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hexmask.long.word 0x0 0.--8. 1. "FBDIV,PLL Feedback Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
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rgroup.long 0x50++0x3
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line.long 0x0 "CLK_STATUS,Clock Status Monitor Register"
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bitfld.long 0x0 7. "CLKSFAIL,Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source. If switch target clock is stable this bit will be set to 0. If switch target clock is not stable this bit will be set to 1.\nNote: After.." "0: Clock switching success,1: Clock switching failure"
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bitfld.long 0x0 4. "HIRCSTB,HIRC Clock Source Stable Flag (Read Only)" "0: HIRC clock is not stable or disabled,1: HIRC clock is stable and enabled"
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bitfld.long 0x0 3. "LIRCSTB,LIRC Clock Source Stable Flag (Read Only)" "0: 38.4 kHz internal low speed RC oscillator (LIRC)..,1: 38.4 kHz internal low speed RC oscillator (LIRC).."
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bitfld.long 0x0 2. "PLLSTB,Internal PLL Clock Source Stable Flag (Read Only)" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable and enabled"
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bitfld.long 0x0 1. "LXTSTB,LXT Clock Source Stable Flag (Read Only)" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.."
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bitfld.long 0x0 0. "HXTSTB,HXT Clock Source Stable Flag (Read Only)" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.."
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group.long 0x60++0x3
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line.long 0x0 "CLK_CLKOCTL,Clock Output Control Register"
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bitfld.long 0x0 5. "DIV1EN,Clock Output Divide One Enable Bit" "0: Clock Output will output clock with source..,1: Clock Output will output clock with source.."
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bitfld.long 0x0 4. "CLKOEN,Clock Output Enable Bit" "0: Clock Output function Disabled,1: Clock Output function Enabled"
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hexmask.long.byte 0x0 0.--3. 1. "FREQSEL,Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]."
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group.long 0x70++0x13
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line.long 0x0 "CLK_CLKDCTL,Clock Fail Detector Control Register"
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bitfld.long 0x0 17. "HXTFQIEN,HXT Clock Frequency Monitor Interrupt Enable Bit" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.."
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bitfld.long 0x0 16. "HXTFQDEN,HXT Clock Frequency Monitor Enable Bit" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.."
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bitfld.long 0x0 13. "LXTFIEN,LXT Clock Fail Interrupt Enable Bit" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.."
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bitfld.long 0x0 12. "LXTFDEN,LXT Clock Fail Detector Enable Bit" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.."
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bitfld.long 0x0 5. "HXTFIEN,HXT Clock Fail Interrupt Enable Bit" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.."
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bitfld.long 0x0 4. "HXTFDEN,HXT Clock Fail Detector Enable Bit" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.."
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line.long 0x4 "CLK_CLKDSTS,Clock Fail Detector Status Register"
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bitfld.long 0x4 8. "HXTFQIF,HXT Clock Frequency Monitor Interrupt Flag (Write Protect)\nNote 1: This bit can be cleared to 0 by software writing 1.\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 4~24 MHz external high speed crystal oscillator..,1: This bit can be cleared to 0 by software writing 1"
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bitfld.long 0x4 1. "LXTFIF,LXT Clock Fail Interrupt Flag (Write Protect)\nNote 1: This bit can be cleared to 0 by software writing 1. \nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 32.768 kHz external low speed crystal oscillator..,1: This bit can be cleared to 0 by software writing 1"
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bitfld.long 0x4 0. "HXTFIF,HXT Clock Fail Interrupt Flag (Write Protect)\nNote 1: This bit can be cleared to 0 by software writing 1.\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 4~24 MHz external high speed crystal oscillator..,1: This bit can be cleared to 0 by software writing 1"
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|
line.long 0x8 "CLK_CDUPB,Clock Frequency Detector Upper Boundary Register"
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hexmask.long.word 0x8 0.--10. 1. "UPERBD,HXT Clock Frequency Detector Upper Boundary\nThe bits define the high value of frequency monitor window.\nWhen HXT frequency monitor value higher than this register the HXT frequency detect fail interrupt flag will be set to 1.\nNote: The.."
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|
line.long 0xC "CLK_CDLOWB,Clock Frequency Detector Low Boundary Register"
|
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hexmask.long.word 0xC 0.--10. 1. "LOWERBD,HXT Clock Frequency Detector Low Boundary\nThe bits define the low value of frequency monitor window.\nWhen HXT frequency monitor value lower than this register the HXT frequency detect fail interrupt flag will be set to 1.\nNote: The frequency.."
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|
line.long 0x10 "CLK_STOPREQ,Clock Stop Request Register"
|
|
bitfld.long 0x10 2. "CANFD2REQ,CANFD2 Clock Stop Request" "0,1"
|
|
bitfld.long 0x10 1. "CANFD1REQ,CANFD1 Clock Stop Request" "0,1"
|
|
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|
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bitfld.long 0x10 0. "CANFD0REQ,CANFD0 Clock Stop Request" "0,1"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x0 "CLK_STOPACK,Clock Stop Acknowledge Register"
|
|
bitfld.long 0x0 2. "CANFD2ACK,CANFD2 Clock Stop Acknowledge (Read Only)" "0,1"
|
|
bitfld.long 0x0 1. "CANFD1ACK,CANFD1 Clock Stop Acknowledge (Read Only)" "0,1"
|
|
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|
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bitfld.long 0x0 0. "CANFD0ACK,CANFD0 Clock Stop Acknowledge (Read Only)" "0,1"
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check Controller)"
|
|
base ad:0x40031000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CRC_CTL,CRC Control Register"
|
|
bitfld.long 0x0 30.--31. "CRCMODE,CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode. \nNote: User must program the polynomial value in CRC_POLYNOMIAL register to specify \nthe polynomial used for CRC calculation." "0: CRC-16 Polynomial mode,1: CRC-8 Polynomial mode,?,?"
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bitfld.long 0x0 28.--29. "DATLEN,CPU Write Data Length\nThis field indicates the write data length.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode the valid data in CRC_DAT.." "0: Data length is 8-bit mode,1: Data length is 16-bit mode,?,?"
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bitfld.long 0x0 27. "CHKSFMT,Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register." "0: 1's complement for CRC checksum Disabled,1: 1's complement for CRC checksum Enabled"
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bitfld.long 0x0 26. "DATFMT,Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_DAT register." "0: 1's complement for CRC writes data in Disabled,1: 1's complement for CRC writes data in Enabled"
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bitfld.long 0x0 25. "CHKSREV,Checksum Bit Order Reverse\nThis bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.\nNote: If the checksum result is 0xDD7B0F2E the bit order reverse for CRC checksum is 0x74F0DEBB." "0: Bit order reverse for CRC checksum Disabled,1: Bit order reverse for CRC checksum Enabled"
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bitfld.long 0x0 24. "DATREV,Write Data Bit Order Reverse\nThis bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.\nNote: If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is 0x55DD33BB." "0: Bit order reversed for CRC write data in Disabled,1: Bit order reversed for CRC write data in Enabled.."
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bitfld.long 0x0 1. "CHKSINIT,Checksum Initialization (Write Only)\nNote: This bit will be cleared automatically." "0: No effect,1: Initial checksum value by auto reload CRC_SEED.."
|
|
bitfld.long 0x0 0. "CRCEN,CRC Channel Enable Bit" "0: No effect,1: CRC operation Enabled"
|
|
line.long 0x4 "CRC_DAT,CRC Write Data Register"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,CRC Write Data Bits\nUser can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits; if.."
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|
line.long 0x8 "CRC_SEED,CRC Seed Register"
|
|
hexmask.long 0x8 0.--31. 1. "SEED,CRC Seed Value\nThis field indicates the CRC seed value.\nNote: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after performing CHKSINIT (CRC_CTL[1])."
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|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CRC_CHECKSUM,CRC Checksum Register"
|
|
hexmask.long 0x0 0.--31. 1. "CHECKSUM,CRC Checksum Results\nThis field indicates the CRC checksum result."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CRC_POLYNOMIAL,CRC Polynomial Register"
|
|
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC Polynomial Value Results\nThis field indicates the value of CRC polynomial."
|
|
tree.end
|
|
tree "FMC (Flash Memory Controller)"
|
|
base ad:0x4000C000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "FMC_ISPCTL,ISP Control Register"
|
|
bitfld.long 0x0 24. "INTEN,ISP Interrupt Enabled Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. Before use ISP interrupt user needs to clear the INTFLAG(FMC_ISPSTS[8]) make sure interrupt happen at correct time." "0: ISP interrupt Disabled,1: ISP interrupt Enabled"
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|
bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\nAPROM writes to itself if APUEN is set to 0.\nLDROM writes to itself if LDUEN.." "0,1"
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bitfld.long 0x0 5. "LDUEN,LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: LDROM cannot be updated,1: LDROM can be updated"
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|
bitfld.long 0x0 4. "CFGUEN,CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: CONFIG cannot be updated,1: CONFIG can be updated"
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bitfld.long 0x0 3. "APUEN,APROM Update Enable Bit (Write Protect)\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in APROM"
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bitfld.long 0x0 2. "SPUEN,SPROM Update Enable Bit (Write Protect)\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: SPROM cannot be updated,1: SPROM can be updated"
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bitfld.long 0x0 1. "BS,Boot Selection (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM respectively. This bit also functions as chip booting status flag which can be used to check where chip booted from. This bit is initiated with the inversed.." "0: Booting from APROM,1: Booting from LDROM"
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|
bitfld.long 0x0 0. "ISPEN,ISP Enable Bit (Write Protect)\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: ISP function Disabled,1: ISP function Enabled"
|
|
line.long 0x4 "FMC_ISPADDR,ISP Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "ISPADDR,ISP Address\nThe M2A23 series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. \nFor CRC32 Checksum Calculation command this field is the Flash starting address for checksum calculation 512 bytes alignment.."
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|
line.long 0x8 "FMC_ISPDAT,ISP Data Register"
|
|
hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.\nWhen ISPFF is 1 in ISP read operation ISPDAT will be written to 0xFFFF_FFFF."
|
|
line.long 0xC "FMC_ISPCMD,ISP Command Register"
|
|
hexmask.long.byte 0xC 0.--6. 1. "CMD,ISP Command\nISP command table is shown below:"
|
|
line.long 0x10 "FMC_ISPTRG,ISP Trigger Control Register"
|
|
bitfld.long 0x10 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished." "0: ISP operation is finished,1: ISP is progressed.Note: This bit is.."
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rgroup.long 0x14++0x3
|
|
line.long 0x0 "FMC_DFBA,Data Flash Base Address"
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hexmask.long 0x0 0.--31. 1. "DFBA,Data Flash Base Address (Read Only)\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash is shared with APROM. The content of this register is loaded from CONFIG1."
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group.long 0x18++0x3
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line.long 0x0 "FMC_FTCTL,Flash Access Time Control Register"
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bitfld.long 0x0 9. "CACHEINV,Flash Cache Invalidation (Write Protect)\nNote 1: Write 1 to start cache invalidation. The value will be changed to 0 once the process is finished.\nNote 2: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: Flash Cache Invalidation finished (default),1: Write 1 to start cache invalidation"
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bitfld.long 0x0 4.--6. "FOM,Frequency Optimization Mode (Write Protect)\nThe M2A23 series support adjustable Flash access timing to optimize the Flash access cycles in different system working frequency.\nNote: These bits are write-protected. Refer to the SYS_REGLCTL register." "0: Frequency is less than or equal to 72 MHz,1: Frequency is less than or equal to 14 MHz,?,?,?,?,?,?"
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group.long 0x40++0x3
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line.long 0x0 "FMC_ISPSTS,ISP Status Register"
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bitfld.long 0x0 31. "SCODE,Security Code Active Flag\nThis bit is set to 1 by hardware when detecting SPROM secured code is active at Flash initialization or software writes 1 to this bit to make secured code active; this bit is only cleared by SPROM page erase operation." "0: SPROM secured code is inactive,1: SPROM secured code is active"
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rbitfld.long 0x0 30. "FBS,Flash Bank Select Indicator (Read Only)\nThis bit indicates which APROM address model is selected to boot." "0: Address model OP0 is selected to boot,1: Address model OP1 is selected to boot"
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hexmask.long.tbyte 0x0 9.--29. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory address {VECMAP[20:0] 9'h000} ~ {VECMAP[20:0] 9'h1FF} except SPROM.\nVECMAP [18:12] should be 0."
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bitfld.long 0x0 8. "INTFLAG,ISP Interrupt Flag\nThis bit needs to be cleared by writing 1 to it." "0: ISP Not Finished,1: ISP done or ISPFF set"
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bitfld.long 0x0 7. "ALLONE,Flash All-one Verification Flag \nThis bit is set by hardware if all of Flash bits are 1 and cleared if Flash bits are not all 1 after 'Run Flash All-One Verification' complete; this bit can also be cleared by writing 1." "0: Flash bits are not all 1 after 'Run Flash..,1: All of Flash bits are 1 after 'Run Flash All-One.."
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bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\nAPROM.." "0,1"
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rbitfld.long 0x0 5. "PGFF,Flash Program with Fast Verification Flag (Read Only)\nThis bit is set if data is mismatched at ISP programming verification. This bit is clear by performing ISP Flash erase or ISP read CID operation." "0: Flash Program is successful,1: Flash Program is failed. Program data is.."
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rbitfld.long 0x0 1.--2. "CBS,Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset or system reset is happened." "0: LDROM with IAP mode,1: LDROM without IAP mode,?,?"
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rbitfld.long 0x0 0. "ISPBUSY,ISP BUSY (Read Only)" "0: ISP operation is finished,1: ISP operation is busy"
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group.long 0x80++0xF
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line.long 0x0 "FMC_MPDAT0,ISP Data0 Register"
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hexmask.long 0x0 0.--31. 1. "ISPDAT0,ISP Data0\nThis register is the first 32-bit data for 32-bit/64-bit/multi-word programming and it is also the mirror of FMC_ISPDAT both registers keep the same data.\nWhen ISPFF is 1 in ISP read operation ISPDAT0 will be written to 0xFFFF_FFFF."
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line.long 0x4 "FMC_MPDAT1,ISP Data1 Register"
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hexmask.long 0x4 0.--31. 1. "ISPDAT1,ISP Data1\nThis register is the second 32-bit data for 64-bit/multi-word programming.\nWhen ISPFF is 1 in ISP read operation ISPDAT1 will be written to 0xFFFF_FFFF."
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line.long 0x8 "FMC_MPDAT2,ISP Data2 Register"
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hexmask.long 0x8 0.--31. 1. "ISPDAT2,ISP Data 2\nThis register is the third 32-bit data for multi-word programming."
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line.long 0xC "FMC_MPDAT3,ISP Data3 Register"
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hexmask.long 0xC 0.--31. 1. "ISPDAT3,ISP Data 3\nThis register is the fourth 32-bit data for multi-word programming."
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rgroup.long 0xC0++0x7
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line.long 0x0 "FMC_MPSTS,ISP Multi-program Status Register"
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bitfld.long 0x0 7. "D3,ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto cleared to 0 when the FMC_MPDAT3 data is programmed to Flash complete." "0: FMC_MPDAT3 register is empty or program to Flash..,1: FMC_MPDAT3 register has been written and not.."
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bitfld.long 0x0 6. "D2,ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto cleared to 0 when the FMC_MPDAT2 data is programmed to Flash complete." "0: FMC_MPDAT2 register is empty or program to Flash..,1: FMC_MPDAT2 register has been written and not.."
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bitfld.long 0x0 5. "D1,ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto cleared to 0 when the FMC_MPDAT1 data is programmed to Flash complete." "0: FMC_MPDAT1 register is empty or program to Flash..,1: FMC_MPDAT1 register has been written and not.."
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bitfld.long 0x0 4. "D0,ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto cleared to 0 when the FMC_MPDAT0 data is programmed to Flash complete." "0: FMC_MPDAT0 register is empty or program to Flash..,1: FMC_MPDAT0 register has been written and not.."
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bitfld.long 0x0 2. "ISPFF,ISP Fail Flag (Read Only)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\nAPROM writes.." "0,1"
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bitfld.long 0x0 1. "PPGO,ISP Multi-program Status (Read Only)" "0: ISP multi-word program operation is not active,1: ISP multi-word program operation is in progress"
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bitfld.long 0x0 0. "MPBUSY,ISP Multi-word Program Busy Flag (Read Only)\nThis bit is the mirror of ISPBUSY(FMC_ISPSTS[0])." "0: ISP Multi-Word program operation is finished,1: ISP Multi-Word program operation is progressed"
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line.long 0x4 "FMC_MPADDR,ISP Multi-program Address Register"
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hexmask.long 0x4 0.--31. 1. "MPADDR,ISP Multi-word Program Address (Read Only)\nMPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\nMPADDR will keep the final ISP address when ISP multi-word program is complete."
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group.long 0x110++0x3
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line.long 0x0 "FMC_APWPROT0,APROM Write Protect Register0"
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bitfld.long 0x0 31. "APPROEN31,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 30. "APPROEN30,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 29. "APPROEN29,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 28. "APPROEN28,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 27. "APPROEN27,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 26. "APPROEN26,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 25. "APPROEN25,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 24. "APPROEN24,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 23. "APPROEN23,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 22. "APPROEN22,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 21. "APPROEN21,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 20. "APPROEN20,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 19. "APPROEN19,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 18. "APPROEN18,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 17. "APPROEN17,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 16. "APPROEN16,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 15. "APPROEN15,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 14. "APPROEN14,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 13. "APPROEN13,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 12. "APPROEN12,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 11. "APPROEN11,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 10. "APPROEN10,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 9. "APPROEN9,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 8. "APPROEN8,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 7. "APPROEN7,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 6. "APPROEN6,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 5. "APPROEN5,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 4. "APPROEN4,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 3. "APPROEN3,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 2. "APPROEN2,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 1. "APPROEN1,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 0. "APPROEN0,APROM Protect Enable Bit\nThis bit indicates which APROM region is protected. The reset value is inverse of CONFIG8.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)." "0: APROM region n is not protected,1: APROM region n is protected"
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group.long 0x118++0x3
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line.long 0x0 "FMC_APWPKEEP,APROM Write Protect Keep Register"
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hexmask.long.word 0x0 0.--15. 1. "APWPKEEP0,APROM Write Protect Keep 0 \nNote 1: These bits reset value can be decided by CONFIG10.\nNote 2: APWPKEEP0 is equal to 0x55AA when APWPLVL1 or written 0x55AA to APWPKEEP0 in APWPLVL0."
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tree.end
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tree "GPIO (General Purpose I/Os)"
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base ad:0x40004000
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group.long 0x0++0xF
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line.long 0x0 "PA_MODE,PA I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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newline
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bitfld.long 0x0 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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line.long 0x4 "PA_DINOFF,PA Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PA_DOUT,PA Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PA_DATMSK,PA Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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rgroup.long 0x10++0x3
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line.long 0x0 "PA_PIN,PA Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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group.long 0x14++0x13
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line.long 0x0 "PA_DBEN,PA De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PA_INTTYPE,PA Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PA_INTEN,PA Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "RHIEN14,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "RHIEN13,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "RHIEN12,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "RHIEN11,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "RHIEN10,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "RHIEN9,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "RHIEN8,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "RHIEN7,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "RHIEN6,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "RHIEN5,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "RHIEN4,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "RHIEN3,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "RHIEN2,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "RHIEN1,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "RHIEN0,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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line.long 0xC "PA_INTSRC,PA Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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line.long 0x10 "PA_SMTEN,PA Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x30++0x7
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line.long 0x0 "PA_PUSEL,PA Pull-up Selection Register"
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bitfld.long 0x0 30.--31. "PUSEL15,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "PUSEL14,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "PUSEL12,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "PUSEL10,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "PUSEL8,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "PUSEL6,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "PUSEL4,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "PUSEL2,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "PUSEL0,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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line.long 0x4 "PA_DBCTL,PA Interrupt De-bounce Control Register"
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rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). It is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
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bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode\nNote 1: It is recommended to disable this bit to save system power if no special application concern.\nNote 2: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Edge detection circuit is active only if I/O pin..,1: It is recommended to disable this bit to save.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 38.4 kHz.."
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hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
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group.long 0x40++0xF
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line.long 0x0 "PB_MODE,PB I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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line.long 0x4 "PB_DINOFF,PB Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PB_DOUT,PB Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PB_DATMSK,PB Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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rgroup.long 0x50++0x3
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line.long 0x0 "PB_PIN,PB Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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group.long 0x54++0x13
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line.long 0x0 "PB_DBEN,PB De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PB_INTTYPE,PB Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PB_INTEN,PB Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "RHIEN14,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "RHIEN13,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "RHIEN12,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "RHIEN11,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "RHIEN10,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "RHIEN9,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "RHIEN8,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "RHIEN7,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "RHIEN6,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "RHIEN5,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "RHIEN4,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "RHIEN3,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "RHIEN2,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "RHIEN1,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "RHIEN0,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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line.long 0xC "PB_INTSRC,PB Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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line.long 0x10 "PB_SMTEN,PB Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x70++0x7
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line.long 0x0 "PB_PUSEL,PB Pull-up Selection Register"
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bitfld.long 0x0 30.--31. "PUSEL15,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "PUSEL14,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "PUSEL12,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "PUSEL10,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "PUSEL8,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "PUSEL6,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "PUSEL4,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "PUSEL2,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "PUSEL0,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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line.long 0x4 "PB_DBCTL,PB Interrupt De-bounce Control Register"
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rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). It is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
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bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode\nNote 1: It is recommended to disable this bit to save system power if no special application concern.\nNote 2: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Edge detection circuit is active only if I/O pin..,1: It is recommended to disable this bit to save.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 38.4 kHz.."
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hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
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group.long 0x80++0xF
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line.long 0x0 "PC_MODE,PC I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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line.long 0x4 "PC_DINOFF,PC Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PC_DOUT,PC Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PC_DATMSK,PC Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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rgroup.long 0x90++0x3
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line.long 0x0 "PC_PIN,PC Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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group.long 0x94++0x13
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line.long 0x0 "PC_DBEN,PC De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PC_INTTYPE,PC Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PC_INTEN,PC Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "RHIEN14,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "RHIEN13,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "RHIEN12,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "RHIEN11,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "RHIEN10,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "RHIEN9,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "RHIEN8,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "RHIEN7,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "RHIEN6,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "RHIEN5,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "RHIEN4,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "RHIEN3,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "RHIEN2,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "RHIEN1,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "RHIEN0,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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line.long 0xC "PC_INTSRC,PC Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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line.long 0x10 "PC_SMTEN,PC Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0xB0++0x7
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line.long 0x0 "PC_PUSEL,PC Pull-up Selection Register"
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bitfld.long 0x0 30.--31. "PUSEL15,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "PUSEL14,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "PUSEL12,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "PUSEL10,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "PUSEL8,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "PUSEL6,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "PUSEL4,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "PUSEL2,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "PUSEL0,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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line.long 0x4 "PC_DBCTL,PC Interrupt De-bounce Control Register"
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rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). It is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
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bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode\nNote 1: It is recommended to disable this bit to save system power if no special application concern.\nNote 2: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Edge detection circuit is active only if I/O pin..,1: It is recommended to disable this bit to save.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 38.4 kHz.."
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hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
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group.long 0xC0++0xF
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line.long 0x0 "PD_MODE,PD I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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line.long 0x4 "PD_DINOFF,PD Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PD_DOUT,PD Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PD_DATMSK,PD Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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rgroup.long 0xD0++0x3
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line.long 0x0 "PD_PIN,PD Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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group.long 0xD4++0x13
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line.long 0x0 "PD_DBEN,PD De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PD_INTTYPE,PD Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PD_INTEN,PD Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "RHIEN14,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "RHIEN13,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "RHIEN12,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "RHIEN11,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "RHIEN10,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "RHIEN9,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "RHIEN8,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "RHIEN7,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "RHIEN6,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "RHIEN5,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "RHIEN4,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "RHIEN3,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "RHIEN2,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "RHIEN1,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "RHIEN0,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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line.long 0xC "PD_INTSRC,PD Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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line.long 0x10 "PD_SMTEN,PD Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0xF0++0x7
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line.long 0x0 "PD_PUSEL,PD Pull-up Selection Register"
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bitfld.long 0x0 30.--31. "PUSEL15,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "PUSEL14,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "PUSEL12,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "PUSEL10,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "PUSEL8,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "PUSEL6,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "PUSEL4,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "PUSEL2,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "PUSEL0,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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line.long 0x4 "PD_DBCTL,PD Interrupt De-bounce Control Register"
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rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). It is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
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bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode\nNote 1: It is recommended to disable this bit to save system power if no special application concern.\nNote 2: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Edge detection circuit is active only if I/O pin..,1: It is recommended to disable this bit to save.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 38.4 kHz.."
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hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
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group.long 0x140++0xF
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line.long 0x0 "PF_MODE,PF I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: For more information about Px,?"
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line.long 0x4 "PF_DINOFF,PF Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PF_DOUT,PF Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PF_DATMSK,PF Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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rgroup.long 0x150++0x3
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line.long 0x0 "PF_PIN,PF Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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group.long 0x154++0x17
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line.long 0x0 "PF_DBEN,PF De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PF_INTTYPE,PF Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PF_INTEN,PF Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "RHIEN14,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "RHIEN13,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "RHIEN12,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "RHIEN11,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "RHIEN10,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "RHIEN9,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "RHIEN8,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "RHIEN7,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "RHIEN6,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "RHIEN5,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "RHIEN4,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "RHIEN3,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "RHIEN2,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "RHIEN1,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "RHIEN0,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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line.long 0xC "PF_INTSRC,PF Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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line.long 0x10 "PF_SMTEN,PF Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PF_SLEWCTL,PF High Slew Rate Control Register"
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group.long 0x170++0x7
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line.long 0x0 "PF_PUSEL,PF Pull-up Selection Register"
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bitfld.long 0x0 30.--31. "PUSEL15,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "PUSEL14,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "PUSEL12,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "PUSEL10,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "PUSEL8,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "PUSEL6,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "PUSEL4,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "PUSEL2,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "PUSEL0,Port A-F Pin[n] Pull-up Enable Bits\nDetermine each I/O Pull-up of Px.n pins.\nNote 1: The independent pull-up control register only valid when MODEn set as tri-state or open-drain mode.\nNote 2: For more information about Px.n please refer to.." "0: Px.n pull-up disable,1: The independent pull-up control register only..,2: For more information about Px,?"
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line.long 0x4 "PF_DBCTL,PF Interrupt De-bounce Control Register"
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rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). It is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
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bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode\nNote 1: It is recommended to disable this bit to save system power if no special application concern.\nNote 2: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Edge detection circuit is active only if I/O pin..,1: It is recommended to disable this bit to save.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 38.4 kHz.."
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hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
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group.long 0x450++0x17
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line.long 0x0 "INT0_INNF,INT0 Input Noise Filter Register"
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bitfld.long 0x0 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x0 0. "NFEN,Noise Filter Enable Bit" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
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line.long 0x4 "INT1_INNF,INT1 Input Noise Filter Register"
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bitfld.long 0x4 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x4 0. "NFEN,Noise Filter Enable Bit" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
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line.long 0x8 "INT2_INNF,INT2 Input Noise Filter Register"
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bitfld.long 0x8 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x8 0. "NFEN,Noise Filter Enable Bit" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
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line.long 0xC "INT3_INNF,INT3 Input Noise Filter Register"
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bitfld.long 0xC 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0xC 0. "NFEN,Noise Filter Enable Bit" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
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line.long 0x10 "INT4_INNF,INT4 Input Noise Filter Register"
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bitfld.long 0x10 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 0. "NFEN,Noise Filter Enable Bit" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
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line.long 0x14 "INT5_INNF,INT5 Input Noise Filter Register"
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bitfld.long 0x14 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x14 0. "NFEN,Noise Filter Enable Bit" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
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group.long 0x490++0x3
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line.long 0x0 "INT_EDETCTL,INT Edge Detect Control Register"
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bitfld.long 0x0 10.--11. "EDETCTL5,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enabled,?,?"
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bitfld.long 0x0 8.--9. "EDETCTL4,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enabled,?,?"
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bitfld.long 0x0 6.--7. "EDETCTL3,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enabled,?,?"
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bitfld.long 0x0 4.--5. "EDETCTL2,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enabled,?,?"
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bitfld.long 0x0 2.--3. "EDETCTL1,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enabled,?,?"
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bitfld.long 0x0 0.--1. "EDETCTL0,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enabled,?,?"
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group.long 0x498++0x7
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line.long 0x0 "INT_EDINTEN,INT Edge Detect Interrupt Enable Control Register"
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bitfld.long 0x0 5. "EDIEN5,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disabled,1: INTn Edge Detect Interrupt Enabled"
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bitfld.long 0x0 4. "EDIEN4,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disabled,1: INTn Edge Detect Interrupt Enabled"
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bitfld.long 0x0 3. "EDIEN3,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disabled,1: INTn Edge Detect Interrupt Enabled"
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bitfld.long 0x0 2. "EDIEN2,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disabled,1: INTn Edge Detect Interrupt Enabled"
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bitfld.long 0x0 1. "EDIEN1,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disabled,1: INTn Edge Detect Interrupt Enabled"
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bitfld.long 0x0 0. "EDIEN0,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disabled,1: INTn Edge Detect Interrupt Enabled"
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line.long 0x4 "INT_EDSTS,INT Edge Detect Interrupt Flag Register"
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bitfld.long 0x4 5. "EDIF5,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
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bitfld.long 0x4 4. "EDIF4,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
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bitfld.long 0x4 3. "EDIF3,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
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bitfld.long 0x4 2. "EDIF2,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
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bitfld.long 0x4 1. "EDIF1,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
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bitfld.long 0x4 0. "EDIF0,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
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group.long 0x800++0xFF
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line.long 0x0 "PA0_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x4 "PA1_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x8 "PA2_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xC "PA3_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x10 "PA4_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x14 "PA5_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x18 "PA6_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x1C "PA7_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x20 "PA8_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x24 "PA9_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x28 "PA10_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x2C "PA11_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x30 "PA12_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x30 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x34 "PA13_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x34 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x38 "PA14_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x38 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x3C "PA15_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x3C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x40 "PB0_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x40 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x44 "PB1_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x44 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x48 "PB2_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x48 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x4C "PB3_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x4C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x50 "PB4_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x50 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x54 "PB5_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x54 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x58 "PB6_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x58 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x5C "PB7_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x5C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x60 "PB8_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x60 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x64 "PB9_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x64 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x68 "PB10_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x68 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x6C "PB11_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x6C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x70 "PB12_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x70 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x74 "PB13_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x74 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x78 "PB14_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x78 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0x7C "PB15_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x7C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x80 "PC0_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x80 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x84 "PC1_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x84 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0x88 "PC2_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x88 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x8C "PC3_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x8C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x90 "PC4_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x90 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0x94 "PC5_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x94 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x98 "PC6_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x98 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x9C "PC7_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x9C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xA0 "PC8_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xA0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xA4 "PC9_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xA4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xA8 "PC10_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xA8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xAC "PC11_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xAC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xB0 "PC12_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xB0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xB4 "PC13_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xB4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xB8 "PC14_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xB8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0xBC "PC15_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xBC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0xC0 "PD0_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xC0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0xC4 "PD1_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xC4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0xC8 "PD2_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xC8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0xCC "PD3_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xCC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0xD0 "PD4_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xD0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xD4 "PD5_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xD4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xD8 "PD6_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xD8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xDC "PD7_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xDC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xE0 "PD8_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xE0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xE4 "PD9_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xE4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xE8 "PD10_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xE8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xEC "PD11_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xEC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xF0 "PD12_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xF0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xF4 "PD13_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xF4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xF8 "PD14_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xF8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xFC "PD15_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xFC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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group.long 0x940++0x3F
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line.long 0x0 "PF0_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x4 "PF1_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x8 "PF2_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xC "PF3_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x10 "PF4_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x14 "PF5_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x18 "PF6_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x1C "PF7_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x20 "PF8_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x24 "PF9_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x28 "PF10_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x2C "PF11_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x30 "PF12_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x30 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x34 "PF13_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x34 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x38 "PF14_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x38 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x3C "PF15_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x3C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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tree.end
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tree "I2C (Inter-Integrated Circuit Serial Interface Controller)"
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base ad:0x40080000
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group.long 0x0++0xB
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line.long 0x0 "I2C_CTL0,I2C Control Register 0"
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bitfld.long 0x0 15. "SARCIF,Slave Address Read Command Interrupt Flag\nThis bit is set by hardware when I2C receive address match read command.\nThis bit is cleared by write 1 to it." "0,1"
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bitfld.long 0x0 14. "DPCIF,Data Phase Count Interrupt Flag\nThis bit is set by hardware when I2C transfer bit count equal to DPBITSEL setting \nThis bit is cleared by write 1 to it." "0,1"
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newline
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bitfld.long 0x0 13. "SRCINTEN,Slave Read Command Interrupt Enable Bit" "0: Slave Read Command Interrupt Disabled,1: Slave Read Command Interrupt Enabled"
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bitfld.long 0x0 12. "DPCINTEN,Data Phase Count Interrupt Enable Bit" "0: Data Phase Count Interrupt Disabled,1: Data Phase Count Interrupt Enabled"
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newline
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bitfld.long 0x0 8.--9. "DPBITSEL,Data Phase Bit Count Select" "0: DPCIF never set by hardware,1: When I2C is transfer data and bit count equal to..,?,?"
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bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
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newline
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bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
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bitfld.long 0x0 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free. This bit will be cleared by hardware automatically." "0,1"
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bitfld.long 0x0 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1"
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bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this.." "0,1"
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bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1"
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line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0"
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hexmask.long.word 0x4 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x8 "I2C_DAT,I2C Data Register"
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hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port."
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rgroup.long 0xC++0x3
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line.long 0x0 "I2C_STATUS0,I2C Status Register 0"
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hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status"
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group.long 0x10++0x23
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line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
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hexmask.long.byte 0x0 12.--15. 1. "NFCNT,Noise Filter Count \nThe register bits control the input filter width. If the pulse width is narrower than the setting((3+N)*PCLK) it will be ignored.\n0 : filter width 3*PCLK \n1 : filter width 4*PCLK\nN : filter width (3+N)*PCKL\nNote: Filter.."
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hexmask.long.word 0x0 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of DIVIDER is 4."
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line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register"
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bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is extended 4 times." "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
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bitfld.long 0x4 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1"
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hexmask.long.word 0x8 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0xC "I2C_ADDR2,I2C Slave Address Register2"
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hexmask.long.word 0xC 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3"
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hexmask.long.word 0x10 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
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hexmask.long.word 0x14 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
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hexmask.long.word 0x18 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
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hexmask.long.word 0x1C 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
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hexmask.long.word 0x20 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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group.long 0x3C++0x23
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line.long 0x0 "I2C_WKCTL,I2C Wake-up Control Register"
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bitfld.long 0x0 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear user must reset I2C controller and.." "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
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bitfld.long 0x0 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
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line.long 0x4 "I2C_WKSTS,I2C Wake-up Status Register"
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bitfld.long 0x4 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit." "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x4 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.."
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bitfld.long 0x4 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_CTL1,I2C Control Register 1"
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bitfld.long 0x8 10. "SWITCHEN,SCL And SDA Pin Switch Enable Bit\nNote: Original pin configuration table is shown in Basic Configuration chapter." "0: IC use original pin configuration,1: IC switch SCL and SDA pin configuration"
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bitfld.long 0x8 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
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bitfld.long 0x8 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA transfer..,1: I2C SCL bus is stretched by hardware after PDMA.."
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bitfld.long 0x8 5. "TWOBUFEN,Two-level Buffer Enable Bit\nSet to enable the two-level buffer for I2C transmitted or received buffer. It is used to improve the performance of the I2C bus." "0: Two-level buffer Disabled,1: Two-level buffer Enabled"
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bitfld.long 0x8 4. "UDRIEN,I2C Under Run Interrupt Control Bit\nSetting UDRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is under run event happened in transmitted buffer." "0,1"
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bitfld.long 0x8 3. "OVRIEN,I2C over Run Interrupt Control Bit\nSetting OVRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is over run event in received buffer." "0,1"
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bitfld.long 0x8 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
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bitfld.long 0x8 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x8 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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line.long 0xC "I2C_STATUS1,I2C Status Register 1"
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rbitfld.long 0xC 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected." "0: The bus is IDLE (both SCL and SDA High),1: The bus is busy"
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bitfld.long 0xC 7. "UDR,I2C Under Run Status Bit\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 6. "OVR,I2C over Run Status Bit\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 5. "EMPTY,TWO-LEVEL BUFFER EMPTY\nThis bit is set when POINTER is equal to 0.\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 4. "FULL,TWO-LEVEL BUFFER FULL\nThis bit is set when POINTER is equal to 2\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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line.long 0x10 "I2C_TMCTL,I2C Timing Configure Control Register"
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hexmask.long.word 0x10 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode."
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hexmask.long.word 0x10 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs."
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line.long 0x14 "I2C_BUSCTL,I2C Bus Management Control Register"
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bitfld.long 0x14 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
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bitfld.long 0x14 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
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bitfld.long 0x14 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock cycle..,1: There is SI interrupt in the 9th clock cycle.."
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bitfld.long 0x14 10. "PECCLR,PEC Clear at Repeat Start\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation." "0: PEC calculation is cleared by 'Repeat Start'..,1: PEC calculation is cleared by 'Repeat Start'.."
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bitfld.long 0x14 9. "TIDLE,Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicate the current bus.." "0: BUSTOUT is used to calculate the clock low..,1: BUSTOUT is used to calculate the IDLE period in.."
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bitfld.long 0x14 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
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bitfld.long 0x14 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled the internal 14-bit counter is used to calculate the time out event of clock low condition." "0: The system management function Disabled,1: The system management function Enabled"
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bitfld.long 0x14 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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bitfld.long 0x14 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
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bitfld.long 0x14 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert Response..,1: Drive BM_ALERT pin low and Alert Response.."
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bitfld.long 0x14 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
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bitfld.long 0x14 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disable. When the address..,1: Device default address Enabled. When the address.."
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bitfld.long 0x14 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter power-down mode the bit should be enabled after wake-up if needed PEC calculation." "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
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bitfld.long 0x14 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data slave byte control mode must be enabled by setting the ACKMEN bit." "0: Slave byte control Disabled,1: Slave byte control Enabled. The 9th bit can.."
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line.long 0x18 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
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bitfld.long 0x18 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled. (The clock and.."
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bitfld.long 0x18 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
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bitfld.long 0x18 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCL low time-out interrupt Disabled.\nBus IDLE..,1: SCL low time-out interrupt Enabled.\nBus IDLE.."
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bitfld.long 0x18 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master it calculates the period from START to ACK\nFor Slave it calculates the period from START to STOP" "0: Cumulative clock low time-out detection Disabled,1: Cumulative clock low time-out detection Enabled"
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bitfld.long 0x18 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
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line.long 0x1C "I2C_BUSSTS,I2C Bus Management Status Register"
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bitfld.long 0x1C 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit." "0: PEC transmission/ receive is not finished when..,1: PEC transmission/ receive is finished when the.."
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bitfld.long 0x1C 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit." "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
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bitfld.long 0x1C 5. "BUSTO,Bus Time-out Status \nIn bus busy the bit indicates the total clock low time-out event occurred; otherwise it indicates the bus idle time-out event occurred.\nNote: Software can write 1 to clear this bit." "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
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bitfld.long 0x1C 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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bitfld.long 0x1C 3. "ALERT,SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit." "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is SMBALERT.."
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bitfld.long 0x1C 2. "PECERR,PEC Error in Reception \nNote: Software can write 1 to clear this bit." "0: PEC value equal the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
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bitfld.long 0x1C 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit." "0: Byte count transmission/ receive is not finished..,1: Byte count transmission/ receive is finished.."
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bitfld.long 0x1C 0. "BUSY,Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: Bus is IDLE (both SCL and SDA High),1: Bus is busy"
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line.long 0x20 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
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hexmask.long.word 0x20 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address command code and data frame."
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rgroup.long 0x60++0x3
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line.long 0x0 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
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hexmask.long.byte 0x0 0.--7. 1. "PECCRC,Packet Error Checking Byte Value"
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group.long 0x64++0x7
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line.long 0x0 "I2C_BUSTOUT,I2C Bus Management Timer Register"
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hexmask.long.byte 0x0 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCL low.\nNote: If the user wants to revise the value of BUSTOUT the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first when the.."
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line.long 0x4 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
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hexmask.long.byte 0x4 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT the TORSTEN bit shall be set to 1 and cleared to 0 first when the BUSEN is set."
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tree.end
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tree "LLSI (LED Light Strip Interface)"
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base ad:0x0
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tree "LLSI0"
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base ad:0x40094000
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group.long 0x0++0xF
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line.long 0x0 "LLSI_CTL,LLSI Control Register"
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bitfld.long 0x0 16.--17. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3"
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bitfld.long 0x0 12. "OFDEF,Output Format Define" "0: Output RGB format,1: Output GRB format"
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bitfld.long 0x0 8. "LLSIMODE,LLSI Mode Select" "0: Software mode,1: PDMA mode"
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bitfld.long 0x0 7. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit\nNote: This bit is only supported in software mode." "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x0 6. "FULINTEN,FIFO Full Interrupt Enable Bit\nNote: If this bit is enabled when the FULIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO full interrupt Disabled,1: FIFO full interrupt Enabled"
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bitfld.long 0x0 5. "EMPINTEN,FIFO Empty Interrupt Enable Bit\nNote: If this bit is enabled when the EMPIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO empty interrupt Disabled,1: FIFO empty interrupt Enabled"
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bitfld.long 0x0 4. "RSTCINTEN,Reset Command Interrupt Enable Bit\nNote: If this bit is enabled when the RSTCIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Reset command interrupt Disabled,1: Reset command interrupt Enabled"
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bitfld.long 0x0 3. "FENDINTEN,Frame End Interrupt Enable Bit\nNote: If this bit is enabled when the FENDIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Frame end interrupt Disabled,1: Frame end interrupt Enabled"
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bitfld.long 0x0 2. "UNDFLINTEN,Underflow Interrupt Enable Bit\nNote: If this bit is enabled when the UNDFLIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Underflow interrupt Disabled,1: Underflow interrupt Enabled"
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bitfld.long 0x0 1. "RSTCEN,Reset Command Function Enable Bit\nNote: If this bit is enabled when FIFO and shift register are both empty LLSI will send reset command out." "0: Reset command function Disabled,1: Reset command function Enabled"
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bitfld.long 0x0 0. "LLSIEN,LLSI Enable Bit" "0: LLSI Disabled,1: LLSI Enabled"
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line.long 0x4 "LLSI_RSTPERIOD,LLSI Reset Period Control Register"
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hexmask.long.word 0x4 0.--15. 1. "RSTPERIOD,Reset Command Period\nThis field is used to adjust the time of reset command."
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line.long 0x8 "LLSI_PERIOD,LLSI Period Control Register"
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hexmask.long.byte 0x8 0.--7. 1. "PERIOD,LLSI Period Register\nThis field is used to define data transfer time (TH+TL)."
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line.long 0xC "LLSI_DUTY,LLSI Duty Control Register"
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hexmask.long.byte 0xC 16.--23. 1. "T1H,T1H Data Register\nThis field is used to define the time of T1H."
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hexmask.long.byte 0xC 0.--7. 1. "T0H,T0H Data Register\nThis field is used to define the time of T0H."
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wgroup.long 0x10++0x3
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line.long 0x0 "LLSI_DATA,LLSI Data Register"
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hexmask.long 0x0 0.--31. 1. "DATA,Data Transmit Register \nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers."
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group.long 0x14++0xF
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line.long 0x0 "LLSI_PCNT,LLSI Pixel Count Register"
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hexmask.long.word 0x0 0.--11. 1. "PCNT,Pixel Count Register\nUser should write a frame size to this register before transfer.\nFor example if there are a total of 5 LED (5 pixels) in frame user should write 5 to this control register."
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line.long 0x4 "LLSI_CLKDIV,LLSI Clock Divider Register"
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hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,LLSI Clock Divider\nIt indicates the LLSI clock "
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line.long 0x8 "LLSI_STATUS,LLSI Status Register"
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bitfld.long 0x8 8. "LDT,Last Data Transmit" "0,1"
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bitfld.long 0x8 5. "FENDIF,Frame End Interrupt Flag\nThis bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.\nUser can use this flag to prepare data in.." "0,1"
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bitfld.long 0x8 4. "UNDFLIF,Under Flow Interrupt Flag\nEach transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.\nSoftware can write 1 to clear this bit." "0,1"
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|
bitfld.long 0x8 3. "TXTHIF,Transmit FIFO Threshold Interrupt Flag" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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|
newline
|
|
bitfld.long 0x8 2. "FULIF,FIFO Full Interrupt Flag" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
|
|
bitfld.long 0x8 1. "EMPIF,FIFO Empty Interrupt Flag" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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|
newline
|
|
bitfld.long 0x8 0. "RSTCIF,Reset Command Interrupt Flag\nThis bit indicates that LLSI has finished reset command transmission." "0,1"
|
|
line.long 0xC "LLSI_OCTL,LLSI Output Control Register"
|
|
bitfld.long 0xC 0. "IDOS,Idle Output Control" "0: Idle will output 0,1: Idle will output 1"
|
|
tree.end
|
|
tree "LLSI1"
|
|
base ad:0x40095000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "LLSI_CTL,LLSI Control Register"
|
|
bitfld.long 0x0 16.--17. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3"
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|
bitfld.long 0x0 12. "OFDEF,Output Format Define" "0: Output RGB format,1: Output GRB format"
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|
newline
|
|
bitfld.long 0x0 8. "LLSIMODE,LLSI Mode Select" "0: Software mode,1: PDMA mode"
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|
bitfld.long 0x0 7. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit\nNote: This bit is only supported in software mode." "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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|
newline
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bitfld.long 0x0 6. "FULINTEN,FIFO Full Interrupt Enable Bit\nNote: If this bit is enabled when the FULIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO full interrupt Disabled,1: FIFO full interrupt Enabled"
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bitfld.long 0x0 5. "EMPINTEN,FIFO Empty Interrupt Enable Bit\nNote: If this bit is enabled when the EMPIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO empty interrupt Disabled,1: FIFO empty interrupt Enabled"
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|
newline
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bitfld.long 0x0 4. "RSTCINTEN,Reset Command Interrupt Enable Bit\nNote: If this bit is enabled when the RSTCIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Reset command interrupt Disabled,1: Reset command interrupt Enabled"
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|
bitfld.long 0x0 3. "FENDINTEN,Frame End Interrupt Enable Bit\nNote: If this bit is enabled when the FENDIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Frame end interrupt Disabled,1: Frame end interrupt Enabled"
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|
newline
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bitfld.long 0x0 2. "UNDFLINTEN,Underflow Interrupt Enable Bit\nNote: If this bit is enabled when the UNDFLIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Underflow interrupt Disabled,1: Underflow interrupt Enabled"
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bitfld.long 0x0 1. "RSTCEN,Reset Command Function Enable Bit\nNote: If this bit is enabled when FIFO and shift register are both empty LLSI will send reset command out." "0: Reset command function Disabled,1: Reset command function Enabled"
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|
newline
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bitfld.long 0x0 0. "LLSIEN,LLSI Enable Bit" "0: LLSI Disabled,1: LLSI Enabled"
|
|
line.long 0x4 "LLSI_RSTPERIOD,LLSI Reset Period Control Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RSTPERIOD,Reset Command Period\nThis field is used to adjust the time of reset command."
|
|
line.long 0x8 "LLSI_PERIOD,LLSI Period Control Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PERIOD,LLSI Period Register\nThis field is used to define data transfer time (TH+TL)."
|
|
line.long 0xC "LLSI_DUTY,LLSI Duty Control Register"
|
|
hexmask.long.byte 0xC 16.--23. 1. "T1H,T1H Data Register\nThis field is used to define the time of T1H."
|
|
hexmask.long.byte 0xC 0.--7. 1. "T0H,T0H Data Register\nThis field is used to define the time of T0H."
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "LLSI_DATA,LLSI Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Transmit Register \nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers."
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "LLSI_PCNT,LLSI Pixel Count Register"
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|
hexmask.long.word 0x0 0.--11. 1. "PCNT,Pixel Count Register\nUser should write a frame size to this register before transfer.\nFor example if there are a total of 5 LED (5 pixels) in frame user should write 5 to this control register."
|
|
line.long 0x4 "LLSI_CLKDIV,LLSI Clock Divider Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,LLSI Clock Divider\nIt indicates the LLSI clock "
|
|
line.long 0x8 "LLSI_STATUS,LLSI Status Register"
|
|
bitfld.long 0x8 8. "LDT,Last Data Transmit" "0,1"
|
|
bitfld.long 0x8 5. "FENDIF,Frame End Interrupt Flag\nThis bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.\nUser can use this flag to prepare data in.." "0,1"
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|
newline
|
|
bitfld.long 0x8 4. "UNDFLIF,Under Flow Interrupt Flag\nEach transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.\nSoftware can write 1 to clear this bit." "0,1"
|
|
bitfld.long 0x8 3. "TXTHIF,Transmit FIFO Threshold Interrupt Flag" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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|
newline
|
|
bitfld.long 0x8 2. "FULIF,FIFO Full Interrupt Flag" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
|
|
bitfld.long 0x8 1. "EMPIF,FIFO Empty Interrupt Flag" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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|
newline
|
|
bitfld.long 0x8 0. "RSTCIF,Reset Command Interrupt Flag\nThis bit indicates that LLSI has finished reset command transmission." "0,1"
|
|
line.long 0xC "LLSI_OCTL,LLSI Output Control Register"
|
|
bitfld.long 0xC 0. "IDOS,Idle Output Control" "0: Idle will output 0,1: Idle will output 1"
|
|
tree.end
|
|
tree.end
|
|
tree "NMI (Non-Maskable Interrupt)"
|
|
base ad:0x40000300
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "NMIEN,NMI Source Interrupt Enable Register"
|
|
bitfld.long 0x0 15. "UART1INT,UART1 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: UART1 NMI source Disabled,1: UART1 NMI source Enabled"
|
|
bitfld.long 0x0 14. "UART0INT,UART0 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: UART0 NMI source Disabled,1: UART0 NMI source Enabled"
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|
newline
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|
bitfld.long 0x0 13. "EINT5,External Interrupt From INT5 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT5 pin NMI source..,1: External interrupt from INT5 pin NMI source.."
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|
bitfld.long 0x0 12. "EINT4,External Interrupt From INT4 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT4 pin NMI source..,1: External interrupt from INT4 pin NMI source.."
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newline
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bitfld.long 0x0 11. "EINT3,External Interrupt From INT3 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT3 pin NMI source..,1: External interrupt from INT3 pin NMI source.."
|
|
bitfld.long 0x0 10. "EINT2,External Interrupt From INT2 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT2 pin NMI source..,1: External interrupt from INT2 pin NMI source.."
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|
newline
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bitfld.long 0x0 9. "EINT1,External Interrupt From INT1 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT1 pin NMI source..,1: External interrupt from INT1 pin NMI source.."
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|
bitfld.long 0x0 8. "EINT0,External Interrupt From INT0 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT0 pin NMI source..,1: External interrupt from INT0 pin NMI source.."
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newline
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bitfld.long 0x0 4. "CLKFAIL,Clock Fail Detected Interrupt NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Clock fail detected interrupt NMI source Disabled,1: Clock fail detected interrupt NMI source Enabled"
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|
bitfld.long 0x0 3. "SRAMPERR,SRAM Parity Check Error NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: SRAM parity check error NMI source Disabled,1: SRAM parity check error NMI source Enabled"
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|
newline
|
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bitfld.long 0x0 2. "PWRWUINT,Power-down Mode Wake-up NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Power-down mode wake-up NMI source Disabled,1: Power-down mode wake-up NMI source Enabled"
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|
bitfld.long 0x0 1. "IRCINT,IRC TRIM NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: IRC TRIM NMI source Disabled,1: IRC TRIM NMI source Enabled"
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|
newline
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bitfld.long 0x0 0. "BODOUT,BOD NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: BOD NMI source Disabled,1: BOD NMI source Enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "NMISTS,NMI Source Interrupt Status Register"
|
|
bitfld.long 0x0 15. "UART1_INT,UART1 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
|
|
bitfld.long 0x0 14. "UART0_INT,UART0 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x0 13. "EINT5,External Interrupt From INT5 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT5 interrupt is..,1: External Interrupt from INT5 interrupt is asserted"
|
|
bitfld.long 0x0 12. "EINT4,External Interrupt From INT4 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT4 interrupt is..,1: External Interrupt from INT4 interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x0 11. "EINT3,External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT3 interrupt is..,1: External Interrupt from INT3 interrupt is asserted"
|
|
bitfld.long 0x0 10. "EINT2,External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT2 interrupt is..,1: External Interrupt from INT2 interrupt is asserted"
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|
newline
|
|
bitfld.long 0x0 9. "EINT1,External Interrupt From INT1 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT1 interrupt is..,1: External Interrupt from INT1 interrupt is asserted"
|
|
bitfld.long 0x0 8. "EINT0,External Interrupt From INT0 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT0 interrupt is..,1: External Interrupt from INT0 interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x0 4. "CLKFAIL,Clock Fail Detected Interrupt Flag (Read Only)" "0: Clock fail detected interrupt is deasserted,1: Clock fail detected interrupt is asserted"
|
|
bitfld.long 0x0 3. "SRAMPERR,SRAM ParityCheck Error Interrupt Flag (Read Only)" "0: SRAM parity check error interrupt is deasserted,1: SRAM parity check error interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x0 2. "PWRWUINT,Power-down Mode Wake-up Interrupt Flag (Read Only)" "0: Power-down mode wake-up interrupt is deasserted,1: Power-down mode wake-up interrupt is asserted"
|
|
bitfld.long 0x0 1. "IRCINT,IRC TRIM Interrupt Flag (Read Only)" "0: IRC TRIM interrupt is deasserted,1: IRC TRIM interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x0 0. "BODOUT,BOD Interrupt Flag (Read Only)" "0: BOD interrupt is deasserted,1: BOD interrupt is asserted"
|
|
tree.end
|
|
tree "NVIC (Nested Vectored Interrupt Controller)"
|
|
base ad:0xE000E100
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "NVIC_ISER0,IRQ0 ~ IRQ31 Set-enable Control Register"
|
|
hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0- NVIC_ISER1 registers enable interrupts and show which interrupts are enabled\nWrite Operation:"
|
|
line.long 0x4 "NVIC_ISER1,IRQ32 ~ IRQ63 Set-enable Control Register"
|
|
hexmask.long 0x4 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER1 registers enable interrupts and show which interrupts are enabled\nWrite Operation:"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "NVIC_ICER0,IRQ0 ~ IRQ31 Clear-enable Control Register"
|
|
hexmask.long 0x0 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0- NVIC_ICER1 registers disable interrupts and show which interrupts are enabled.\nWrite Operation:"
|
|
line.long 0x4 "NVIC_ICER1,IRQ32 ~ IRQ63 Clear-enable Control Register"
|
|
hexmask.long 0x4 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0- NVIC_ICER1 registers disable interrupts and show which interrupts are enabled.\nWrite Operation:"
|
|
group.long 0x100++0x7
|
|
line.long 0x0 "NVIC_ISPR0,IRQ0 ~ IRQ31 Set-pending Control Register"
|
|
hexmask.long 0x0 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0 registers force interrupts into the pending state and show which interrupts are pending\nWrite Operation:"
|
|
line.long 0x4 "NVIC_ISPR1,IRQ32 ~ IRQ63 Set-pending Control Register"
|
|
hexmask.long 0x4 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0- NVIC_ISPR1 registers force interrupts into the pending state and show which interrupts are pending\nWrite Operation:"
|
|
group.long 0x180++0x7
|
|
line.long 0x0 "NVIC_ICPR0,IRQ0 ~ IRQ31 Clear-pending Control Register"
|
|
hexmask.long 0x0 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0- NVIC_ICPR1 registers remove the pending state from interrupts and show which interrupts are pending\nWrite Operation:"
|
|
line.long 0x4 "NVIC_ICPR1,IRQ32 ~ IRQ63 Clear-pending Control Register"
|
|
hexmask.long 0x4 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0- NVIC_ICPR1 registers remove the pending state from interrupts and show which interrupts are pending\nWrite Operation:"
|
|
group.long 0x200++0x7
|
|
line.long 0x0 "NVIC_IABR0,IRQ0 ~ IRQ31 Active Bit Register"
|
|
hexmask.long 0x0 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0- NVIC_IABR1 registers indicate which interrupts are active."
|
|
line.long 0x4 "NVIC_IABR1,IRQ32 ~ IRQ63 Active Bit Register"
|
|
hexmask.long 0x4 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0- NVIC_IABR1 registers indicate which interrupts are active."
|
|
tree.end
|
|
tree "PDMA (Peripheral Direct Memory Access)"
|
|
base ad:0x40008000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "PDMAx_DSCTn_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
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|
newline
|
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bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
line.long 0x4 "PDMAx_DSCTn_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x4 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
|
|
line.long 0x8 "PDMAx_DSCTn_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x8 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
|
|
line.long 0xC "PDMAx_DSCTn_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0xC 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
|
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hexmask.long.word 0xC 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the next descriptor table is start.."
|
|
rgroup.long 0x100++0x3
|
|
line.long 0x0 "PDMAx_CURSCATn,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "PDMAx_CHCTL,PDMA Channel Control Register"
|
|
bitfld.long 0x0 0. "CHENn,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
wgroup.long 0x404++0x7
|
|
line.long 0x0 "PDMAx_PAUSE,PDMA Transfer Pause Control Register"
|
|
bitfld.long 0x0 0. "PAUSEn,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
line.long 0x4 "PDMAx_SWREQ,PDMA Software Request Register"
|
|
bitfld.long 0x4 0. "SWREQn,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMAx_TRGSTS register to know.."
|
|
rgroup.long 0x40C++0x3
|
|
line.long 0x0 "PDMAx_TRGSTS,PDMA Channel Request Status Register"
|
|
bitfld.long 0x0 0. "REQSTSn,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
group.long 0x410++0x3
|
|
line.long 0x0 "PDMAx_PRISET,PDMA Fixed Priority Setting Register"
|
|
bitfld.long 0x0 0. "FPRISETn,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
|
|
wgroup.long 0x414++0x3
|
|
line.long 0x0 "PDMAx_PRICLR,PDMA Fixed Priority Clear Register"
|
|
bitfld.long 0x0 0. "FPRICLRn,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
|
|
group.long 0x418++0x3
|
|
line.long 0x0 "PDMAx_INTEN,PDMA Interrupt Enable Register"
|
|
bitfld.long 0x0 5. "INTEN5,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
|
|
bitfld.long 0x0 4. "INTEN4,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
|
|
newline
|
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bitfld.long 0x0 3. "INTEN3,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
|
|
bitfld.long 0x0 2. "INTEN2,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
|
|
newline
|
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bitfld.long 0x0 1. "INTEN1,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
|
|
bitfld.long 0x0 0. "INTEN0,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "PDMAx_INTSTS,PDMA Interrupt Status Register"
|
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bitfld.long 0x0 2. "ALIGNF,Transfer Alignment Interrupt Flag (Read Only)" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x0 1. "TDIF,Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer." "0: Not finished yet,1: PDMA channel has finished transmission"
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bitfld.long 0x0 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag (Read Only)\nThis bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error." "0: No AHB bus ERROR response received,1: AHB bus ERROR response received"
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group.long 0x420++0xB
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line.long 0x0 "PDMAx_ABTSTS,PDMA Channel Read/Write Target Abort Flag Register"
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bitfld.long 0x0 5. "ABTIF5,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this bit." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x0 4. "ABTIF4,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this bit." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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newline
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bitfld.long 0x0 3. "ABTIF3,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this bit." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x0 2. "ABTIF2,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this bit." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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newline
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bitfld.long 0x0 1. "ABTIF1,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this bit." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x0 0. "ABTIF0,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this bit." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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line.long 0x4 "PDMAx_TDSTS,PDMA Channel Transfer Done Flag Register"
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bitfld.long 0x4 5. "TDIF5,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x4 4. "TDIF4,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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newline
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bitfld.long 0x4 3. "TDIF3,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x4 2. "TDIF2,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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newline
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bitfld.long 0x4 1. "TDIF1,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x4 0. "TDIF0,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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line.long 0x8 "PDMAx_ALIGN,PDMA Transfer Alignment Status Register"
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bitfld.long 0x8 5. "ALIGN5,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x8 4. "ALIGN4,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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newline
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bitfld.long 0x8 3. "ALIGN3,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x8 2. "ALIGN2,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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newline
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bitfld.long 0x8 1. "ALIGN1,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x8 0. "ALIGN0,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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rgroup.long 0x42C++0x3
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line.long 0x0 "PDMAx_TACTSTS,PDMA Transfer Active Flag Register"
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bitfld.long 0x0 5. "TXACTF5,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 4. "TXACTF4,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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newline
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bitfld.long 0x0 3. "TXACTF3,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 2. "TXACTF2,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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newline
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bitfld.long 0x0 1. "TXACTF1,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 0. "TXACTF0,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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group.long 0x43C++0x3
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line.long 0x0 "PDMAx_SCATBA,PDMA Scatter-gather Descriptor Table Base Address Register"
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hexmask.long.word 0x0 16.--31. 1. "SCATBA,PDMA Scatter-gather Descriptor Table Address\nIn Scatter-gather mode this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-gather mode."
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group.long 0x460++0x3
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line.long 0x0 "PDMAx_CHRST,PDMA Channel Reset Register"
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bitfld.long 0x0 5. "CH5RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 4. "CH4RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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newline
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bitfld.long 0x0 3. "CH3RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 2. "CH2RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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newline
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bitfld.long 0x0 1. "CH1RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 0. "CH0RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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group.long 0x480++0x7
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line.long 0x0 "PDMAx_REQSEL0_3,PDMA Request Source Select Register 0"
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hexmask.long.byte 0x0 24.--30. 1. "REQSRC3,Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x0 16.--22. 1. "REQSRC2,Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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newline
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hexmask.long.byte 0x0 8.--14. 1. "REQSRC1,Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x0 0.--6. 1. "REQSRC0,Channel 0 Request Source Selection\nThis filed defines which peripheral request source is connected to PDMA channel 0. User can configure the peripheral request source by setting REQSRC0.\nNote 1: A peripheral request source cannot be assigned to.."
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line.long 0x4 "PDMAx_REQSEL4_7,PDMA Request Source Select Register 1"
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hexmask.long.byte 0x4 8.--14. 1. "REQSRC5,Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x4 0.--6. 1. "REQSRC4,Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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tree.end
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tree "PWM (Pulse Width Modulation Generator and Capture Timer)"
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base ad:0x4005C000
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group.long 0x0++0x7
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line.long 0x0 "PWM_CTL0,PWM Control Register 0"
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bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled PWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disable,1: ICE debug mode counter halt Enable"
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bitfld.long 0x0 21. "IMMLDEN5,Immediately Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x0 20. "IMMLDEN4,Immediately Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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newline
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bitfld.long 0x0 19. "IMMLDEN3,Immediately Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x0 18. "IMMLDEN2,Immediately Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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newline
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bitfld.long 0x0 17. "IMMLDEN1,Immediately Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x0 16. "IMMLDEN0,Immediately Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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newline
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bitfld.long 0x0 5. "CTRLD5,Center Load Enable Bits\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 4. "CTRLD4,Center Load Enable Bits\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
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newline
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bitfld.long 0x0 3. "CTRLD3,Center Load Enable Bits\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 2. "CTRLD2,Center Load Enable Bits\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
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newline
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bitfld.long 0x0 1. "CTRLD1,Center Load Enable Bits\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 0. "CTRLD0,Center Load Enable Bits\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
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line.long 0x4 "PWM_CTL1,PWM Control Register 1"
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bitfld.long 0x4 24.--26. "OUTMODEn,PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function these bits must all set to the same mode." "0: PWM independent mode,1: PWM complementary mode,?,?,?,?,?,?"
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bitfld.long 0x4 8.--9. "CNTTYPE4,PWM Counter Behavior Type 4\nThe two bits control channel5 and channel4" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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newline
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bitfld.long 0x4 4.--5. "CNTTYPE2,PWM Counter Behavior Type 2\nThe two bits control channel3 and channel2" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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bitfld.long 0x4 0.--1. "CNTTYPE0,PWM Counter Behavior Type 0\nThe two bits control channel1 and channel0" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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group.long 0x10++0x17
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line.long 0x0 "PWM_CLKSRC,PWM Clock Source Register"
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bitfld.long 0x0 16.--18. "ECLKSRC4,PWM_CH45 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "ECLKSRC2,PWM_CH23 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 0.--2. "ECLKSRC0,PWM_CH01 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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line.long 0x4 "PWM_CLKPSC0_1,PWM Clock Prescale Register 0/1"
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hexmask.long.word 0x4 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
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line.long 0x8 "PWM_CLKPSC2_3,PWM Clock Prescale Register 2/3"
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hexmask.long.word 0x8 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
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line.long 0xC "PWM_CLKPSC4_5,PWM Clock Prescale Register 4/5"
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hexmask.long.word 0xC 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
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line.long 0x10 "PWM_CNTEN,PWM Counter Enable Register"
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bitfld.long 0x10 4. "CNTEN4,PWM Counter Enable Bit 4" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
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bitfld.long 0x10 2. "CNTEN2,PWM Counter Enable Bit 2" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
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newline
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bitfld.long 0x10 0. "CNTEN0,PWM Counter Enable Bit 0" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
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line.long 0x14 "PWM_CNTCLR,PWM Clear Counter Register"
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bitfld.long 0x14 4. "CNTCLR4,Clear PWM Counter Control Bit 4\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0000H"
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bitfld.long 0x14 2. "CNTCLR2,Clear PWM Counter Control Bit 2\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0000H"
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newline
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bitfld.long 0x14 0. "CNTCLR0,Clear PWM Counter Control Bit 0\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0000H"
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group.long 0x30++0x3
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line.long 0x0 "PWM_PERIOD0,PWM Period Register 0"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
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group.long 0x38++0x3
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line.long 0x0 "PWM_PERIOD2,PWM Period Register 2"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
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group.long 0x40++0x3
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line.long 0x0 "PWM_PERIOD4,PWM Period Register 4"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
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group.long 0x50++0x17
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line.long 0x0 "PWM_CMPDAT0,PWM Comparator Register 0"
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hexmask.long.word 0x0 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as.."
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line.long 0x4 "PWM_CMPDAT1,PWM Comparator Register 1"
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hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as.."
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line.long 0x8 "PWM_CMPDAT2,PWM Comparator Register 2"
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hexmask.long.word 0x8 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as.."
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line.long 0xC "PWM_CMPDAT3,PWM Comparator Register 3"
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hexmask.long.word 0xC 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as.."
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line.long 0x10 "PWM_CMPDAT4,PWM Comparator Register 4"
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hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as.."
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line.long 0x14 "PWM_CMPDAT5,PWM Comparator Register 5"
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hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as.."
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group.long 0x70++0xB
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line.long 0x0 "PWM_DTCTL0_1,PWM Dead-time Control Register 0/1"
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bitfld.long 0x0 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x0 16. "DTEN,Enable Dead-time Insertion for PWM Pair (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs of pin pair are complementary without any delay.\nNote: This.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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newline
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hexmask.long.word 0x0 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x4 "PWM_DTCTL2_3,PWM Dead-time Control Register 2/3"
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bitfld.long 0x4 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x4 16. "DTEN,Enable Dead-time Insertion for PWM Pair (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs of pin pair are complementary without any delay.\nNote: This.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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newline
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hexmask.long.word 0x4 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x8 "PWM_DTCTL4_5,PWM Dead-time Control Register 4/5"
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bitfld.long 0x8 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x8 16. "DTEN,Enable Dead-time Insertion for PWM Pair (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs of pin pair are complementary without any delay.\nNote: This.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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newline
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hexmask.long.word 0x8 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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rgroup.long 0x90++0x3
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line.long 0x0 "PWM_CNT0,PWM Counter Register 0"
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bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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rgroup.long 0x98++0x3
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line.long 0x0 "PWM_CNT2,PWM Counter Register 2"
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bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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rgroup.long 0xA0++0x3
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line.long 0x0 "PWM_CNT4,PWM Counter Register 4"
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bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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group.long 0xB0++0x2B
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line.long 0x0 "PWM_WGCTL0,PWM Generation Register 0"
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bitfld.long 0x0 26.--27. "PRDPCTL5,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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bitfld.long 0x0 24.--25. "PRDPCTL4,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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bitfld.long 0x0 22.--23. "PRDPCTL3,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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bitfld.long 0x0 20.--21. "PRDPCTL2,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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bitfld.long 0x0 18.--19. "PRDPCTL1,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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bitfld.long 0x0 16.--17. "PRDPCTL0,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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bitfld.long 0x0 10.--11. "ZPCTL5,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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bitfld.long 0x0 8.--9. "ZPCTL4,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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bitfld.long 0x0 6.--7. "ZPCTL3,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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bitfld.long 0x0 4.--5. "ZPCTL2,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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bitfld.long 0x0 2.--3. "ZPCTL1,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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bitfld.long 0x0 0.--1. "ZPCTL0,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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line.long 0x4 "PWM_WGCTL1,PWM Generation Register 1"
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bitfld.long 0x4 26.--27. "CMPDCTL5,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 24.--25. "CMPDCTL4,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 22.--23. "CMPDCTL3,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 20.--21. "CMPDCTL2,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 18.--19. "CMPDCTL1,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 16.--17. "CMPDCTL0,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 10.--11. "CMPUCTL5,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 8.--9. "CMPUCTL4,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 6.--7. "CMPUCTL3,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 4.--5. "CMPUCTL2,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 2.--3. "CMPUCTL1,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 0.--1. "CMPUCTL0,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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line.long 0x8 "PWM_MSKEN,PWM Mask Enable Register"
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bitfld.long 0x8 5. "MSKEN5,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 4. "MSKEN4,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 3. "MSKEN3,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 2. "MSKEN2,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 1. "MSKEN1,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 0. "MSKEN0,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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line.long 0xC "PWM_MSK,PWM Mask Data Register"
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bitfld.long 0xC 5. "MSKDAT5,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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bitfld.long 0xC 4. "MSKDAT4,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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bitfld.long 0xC 3. "MSKDAT3,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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bitfld.long 0xC 2. "MSKDAT2,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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bitfld.long 0xC 1. "MSKDAT1,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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bitfld.long 0xC 0. "MSKDAT0,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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line.long 0x10 "PWM_BNF,PWM Brake Noise Filter Register"
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bitfld.long 0x10 24. "BK1SRC,Brake 1 Pin Source Select\nFor PWM0 setting:" "0: Brake 1 pin source come from PWM0_BRAKE1.\nBrake..,1: Brake 1 pin source come from PWM1_BRAKE1.\nBrake.."
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bitfld.long 0x10 16. "BK0SRC,Brake 0 Pin Source Select\nFor PWM0 setting:" "0: Brake 0 pin source come from PWM0_BRAKE0.\nBrake..,1: Brake 0 pin source come from PWM1_BRAKE0.\nBrake.."
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bitfld.long 0x10 15. "BRK1PINV,Brake 1 Pin Inverse" "0: The state of pin PWMx_BRAKE1 is passed to the..,1: The inversed state of pin PWMx_BRAKE1 is passed.."
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bitfld.long 0x10 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 9.--11. "BRK1FSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 8. "BRK1NFEN,PWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 1 Disabled,1: Noise filter of PWM Brake 1 Enabled"
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bitfld.long 0x10 7. "BRK0PINV,Brake 0 Pin Inverse" "0: The state of pin PWMx_BRAKE0 is passed to the..,1: The inversed state of pin PWMx_BRAKE10 is passed.."
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bitfld.long 0x10 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 1.--3. "BRK0FSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 0. "BRK0NFEN,PWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 0 Disabled,1: Noise filter of PWM Brake 0 Enabled"
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line.long 0x14 "PWM_FAILBRK,PWM System Fail Brake Control Register"
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bitfld.long 0x14 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.."
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bitfld.long 0x14 2. "RAMBRKEN,SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0x14 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled"
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bitfld.long 0x14 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by CSS detection Disabled,1: Brake Function triggered by CSS detection Enabled"
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line.long 0x18 "PWM_BRKCTL0_1,PWM Brake Edge Detect Control Register 0/1"
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bitfld.long 0x18 28. "ADCLBEN,Enable ADC Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as level-detect brake source Disabled,1: ADCRM as level-detect brake source Enabled"
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bitfld.long 0x18 20. "ADCEBEN,Enable ADC Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as edge-detect brake source Disabled,1: ADCRM as edge-detect brake source Enabled"
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bitfld.long 0x18 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect or edge-detect..,1: PWM odd channel output tri-state when..,?,?"
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bitfld.long 0x18 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect or edge-detect..,1: PWM even channel output tri-state when..,?,?"
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bitfld.long 0x18 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x18 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x18 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x18 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x18 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x18 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x18 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
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bitfld.long 0x18 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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bitfld.long 0x18 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x18 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x1C "PWM_BRKCTL2_3,PWM Brake Edge Detect Control Register 2/3"
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bitfld.long 0x1C 28. "ADCLBEN,Enable ADC Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as level-detect brake source Disabled,1: ADCRM as level-detect brake source Enabled"
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bitfld.long 0x1C 20. "ADCEBEN,Enable ADC Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as edge-detect brake source Disabled,1: ADCRM as edge-detect brake source Enabled"
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bitfld.long 0x1C 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect or edge-detect..,1: PWM odd channel output tri-state when..,?,?"
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bitfld.long 0x1C 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect or edge-detect..,1: PWM even channel output tri-state when..,?,?"
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bitfld.long 0x1C 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x1C 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x1C 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x1C 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x1C 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x1C 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x1C 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
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bitfld.long 0x1C 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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bitfld.long 0x1C 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x1C 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x20 "PWM_BRKCTL4_5,PWM Brake Edge Detect Control Register 4/5"
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bitfld.long 0x20 28. "ADCLBEN,Enable ADC Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as level-detect brake source Disabled,1: ADCRM as level-detect brake source Enabled"
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bitfld.long 0x20 20. "ADCEBEN,Enable ADC Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as edge-detect brake source Disabled,1: ADCRM as edge-detect brake source Enabled"
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bitfld.long 0x20 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect or edge-detect..,1: PWM odd channel output tri-state when..,?,?"
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bitfld.long 0x20 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect or edge-detect..,1: PWM even channel output tri-state when..,?,?"
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bitfld.long 0x20 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x20 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x20 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x20 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x20 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x20 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x20 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
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bitfld.long 0x20 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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bitfld.long 0x20 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x20 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x24 "PWM_POLCTL,PWM Pin Polar Inverse Register"
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bitfld.long 0x24 5. "PINV5,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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bitfld.long 0x24 4. "PINV4,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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bitfld.long 0x24 3. "PINV3,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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bitfld.long 0x24 2. "PINV2,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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bitfld.long 0x24 1. "PINV1,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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bitfld.long 0x24 0. "PINV0,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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line.long 0x28 "PWM_POEN,PWM Output Enable Register"
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bitfld.long 0x28 5. "POEN5,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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bitfld.long 0x28 4. "POEN4,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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bitfld.long 0x28 3. "POEN3,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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bitfld.long 0x28 2. "POEN2,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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bitfld.long 0x28 1. "POEN1,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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bitfld.long 0x28 0. "POEN0,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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wgroup.long 0xDC++0x3
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line.long 0x0 "PWM_SWBRK,PWM Software Brake Control Register"
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bitfld.long 0x0 10. "BRKLTRG4,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 9. "BRKLTRG2,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 8. "BRKLTRG0,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 2. "BRKETRG4,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 1. "BRKETRG2,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 0. "BRKETRG0,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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group.long 0xE0++0xF
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line.long 0x0 "PWM_INTEN0,PWM Interrupt Enable Register 0"
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bitfld.long 0x0 29. "CMPDIEN5,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 28. "CMPDIEN4,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 27. "CMPDIEN3,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 26. "CMPDIEN2,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 25. "CMPDIEN1,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 24. "CMPDIEN0,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 21. "CMPUIEN5,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 20. "CMPUIEN4,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 19. "CMPUIEN3,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 18. "CMPUIEN2,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 17. "CMPUIEN1,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 16. "CMPUIEN0,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 12. "PIEN4,PWM Period Point Interrupt Enable Bit 4\nNote: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x0 10. "PIEN2,PWM Period Point Interrupt Enable Bit 2\nNote: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x0 8. "PIEN0,PWM Period Point Interrupt Enable Bit 0\nNote: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x0 4. "ZIEN4,PWM Zero Point Interrupt Enable Bit 4\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 2. "ZIEN2,PWM Zero Point Interrupt Enable Bit 2\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 0. "ZIEN0,PWM Zero Point Interrupt Enable Bit 0\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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line.long 0x4 "PWM_INTEN1,PWM Interrupt Enable Register 1"
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bitfld.long 0x4 10. "BRKLIEN4_5,PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
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bitfld.long 0x4 9. "BRKLIEN2_3,PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
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bitfld.long 0x4 8. "BRKLIEN0_1,PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
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bitfld.long 0x4 2. "BRKEIEN4_5,PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bitr is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5 Enabled"
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bitfld.long 0x4 1. "BRKEIEN2_3,PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3 Enabled"
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bitfld.long 0x4 0. "BRKEIEN0_1,PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1 Enabled"
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line.long 0x8 "PWM_INTSTS0,PWM Interrupt Flag Register 0"
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bitfld.long 0x8 29. "CMPDIF5,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x8 28. "CMPDIF4,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x8 27. "CMPDIF3,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x8 26. "CMPDIF2,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x8 25. "CMPDIF1,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x8 24. "CMPDIF0,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x8 21. "CMPUIF5,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 .." "0,1"
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bitfld.long 0x8 20. "CMPUIF4,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 .." "0,1"
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bitfld.long 0x8 19. "CMPUIF3,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 .." "0,1"
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bitfld.long 0x8 18. "CMPUIF2,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 .." "0,1"
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bitfld.long 0x8 17. "CMPUIF1,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 .." "0,1"
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bitfld.long 0x8 16. "CMPUIF0,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 .." "0,1"
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bitfld.long 0x8 12. "PIF4,PWM Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 10. "PIF2,PWM Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 8. "PIF0,PWM Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 4. "ZIF4,PWM Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 2. "ZIF2,PWM Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 0. "ZIF0,PWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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line.long 0xC "PWM_INTSTS1,PWM Interrupt Flag Register 1"
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rbitfld.long 0xC 29. "BRKLSTS5,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 28. "BRKLSTS4,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 27. "BRKLSTS3,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 26. "BRKLSTS2,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 25. "BRKLSTS1,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 24. "BRKLSTS0,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 21. "BRKESTS5,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 20. "BRKESTS4,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 19. "BRKESTS3,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 18. "BRKESTS2,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 17. "BRKESTS1,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 16. "BRKESTS0,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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bitfld.long 0xC 13. "BRKLIF5,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 12. "BRKLIF4,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 11. "BRKLIF3,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 10. "BRKLIF2,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 9. "BRKLIF1,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 8. "BRKLIF0,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 5. "BRKEIF5,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0xC 4. "BRKEIF4,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0xC 3. "BRKEIF3,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0xC 2. "BRKEIF2,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0xC 1. "BRKEIF1,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0xC 0. "BRKEIF0,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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group.long 0xF8++0x7
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line.long 0x0 "PWM_ADCTS0,PWM Trigger ADC Source Select Register 0"
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bitfld.long 0x0 31. "TRGEN3,PWM_CH3 Trigger ADC Enable Bit" "0: PWM_CH3 Trigger ADC function Disabled,1: PWM_CH3 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 24.--27. 1. "TRGSEL3,PWM_CH3 Trigger ADC Source Select"
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bitfld.long 0x0 23. "TRGEN2,PWM_CH2 Trigger ADC Enable Bit" "0: PWM_CH2 Trigger ADC function Disabled,1: PWM_CH2 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 16.--19. 1. "TRGSEL2,PWM_CH2 Trigger ADC Source Select"
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bitfld.long 0x0 15. "TRGEN1,PWM_CH1 Trigger ADC Enable Bit" "0: PWM_CH1 Trigger ADC function Disabled,1: PWM_CH1 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 8.--11. 1. "TRGSEL1,PWM_CH1 Trigger ADC Source Select"
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bitfld.long 0x0 7. "TRGEN0,PWM_CH0 Trigger ADC Enable Bit" "0: PWM_CH0 Trigger ADC function Disabled,1: PWM_CH0 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 0.--3. 1. "TRGSEL0,PWM_CH0 Trigger ADC Source Select"
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line.long 0x4 "PWM_ADCTS1,PWM Trigger ADC Source Select Register 1"
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bitfld.long 0x4 15. "TRGEN5,PWM_CH5 Trigger ADC Enable Bit" "0: PWM_CH5 Trigger ADC function Disabled,1: PWM_CH5 Trigger ADC function Enabled"
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hexmask.long.byte 0x4 8.--11. 1. "TRGSEL5,PWM_CH5 Trigger ADC Source Select"
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bitfld.long 0x4 7. "TRGEN4,PWM_CH4 Trigger ADC Enable Bit" "0: PWM_CH4 Trigger ADC function Disabled,1: PWM_CH4 Trigger ADC function Enabled"
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hexmask.long.byte 0x4 0.--3. 1. "TRGSEL4,PWM_CH4 Trigger ADC Source Select"
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group.long 0x110++0x3
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line.long 0x0 "PWM_SSCTL,PWM Synchronous Start Control Register"
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bitfld.long 0x0 8.--9. "SSRC,PWM Synchronous Start Source Select Bits" "0: Synchronous start source come from PWM0,?,?,?"
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bitfld.long 0x0 4. "SSEN4,PWM Synchronous Start Function Enable Bit 4\nWhen synchronous start function is enabled the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
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bitfld.long 0x0 2. "SSEN2,PWM Synchronous Start Function Enable Bit 2\nWhen synchronous start function is enabled the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
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bitfld.long 0x0 0. "SSEN0,PWM Synchronous Start Function Enable Bit 0\nWhen synchronous start function is enabled the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
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wgroup.long 0x114++0x3
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line.long 0x0 "PWM_SSTRG,PWM Synchronous Start Trigger Register"
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bitfld.long 0x0 0. "CNTSEN,PWM Counter Synchronous Start Enable (Write Only)\nPWM counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time." "0,1"
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group.long 0x120++0x3
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line.long 0x0 "PWM_STATUS,PWM Status Register"
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bitfld.long 0x0 21. "ADCTRG5,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
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bitfld.long 0x0 20. "ADCTRG4,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
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bitfld.long 0x0 19. "ADCTRG3,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
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bitfld.long 0x0 18. "ADCTRG2,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
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bitfld.long 0x0 17. "ADCTRG1,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
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bitfld.long 0x0 16. "ADCTRG0,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
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bitfld.long 0x0 4. "CNTMAX4,Time-base Counter 4 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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bitfld.long 0x0 2. "CNTMAX2,Time-base Counter 2 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.."
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bitfld.long 0x0 0. "CNTMAX0,Time-base Counter 0 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.."
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group.long 0x130++0x3
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line.long 0x0 "PWM_IFA0,PWM Interrupt Flag Accumulator Register 0"
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bitfld.long 0x0 31. "IFAEN,PWM_CHn Interrupt Flag Accumulator Enable Bits" "0: PWM_CHn interrupt flag accumulator Disabled,1: PWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x0 28.--29. "IFASEL,PWM_CHn Interrupt Flag Accumulator Source Select" "0: PWM_CHn zero point,1: PWM_CHn period in channel n,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM_CHn Accumulator Stop Mode Enable Bits" "0: PWM_CHn Stop Mode Disable,1: PWM_CHn Stop Mode Enable"
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hexmask.long.byte 0x0 0.--7. 1. "IFACNT,PWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of PWM_CHn period occurs to set bit IFAIFn to request the PWM period interrupt. PWM flag will be set in every IFACNT[15:0] times of PWM period."
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group.long 0x138++0x3
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line.long 0x0 "PWM_IFA2,PWM Interrupt Flag Accumulator Register 2"
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bitfld.long 0x0 31. "IFAEN,PWM_CHn Interrupt Flag Accumulator Enable Bits" "0: PWM_CHn interrupt flag accumulator Disabled,1: PWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x0 28.--29. "IFASEL,PWM_CHn Interrupt Flag Accumulator Source Select" "0: PWM_CHn zero point,1: PWM_CHn period in channel n,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM_CHn Accumulator Stop Mode Enable Bits" "0: PWM_CHn Stop Mode Disable,1: PWM_CHn Stop Mode Enable"
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hexmask.long.byte 0x0 0.--7. 1. "IFACNT,PWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of PWM_CHn period occurs to set bit IFAIFn to request the PWM period interrupt. PWM flag will be set in every IFACNT[15:0] times of PWM period."
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group.long 0x140++0x3
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line.long 0x0 "PWM_IFA4,PWM Interrupt Flag Accumulator Register 4"
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bitfld.long 0x0 31. "IFAEN,PWM_CHn Interrupt Flag Accumulator Enable Bits" "0: PWM_CHn interrupt flag accumulator Disabled,1: PWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x0 28.--29. "IFASEL,PWM_CHn Interrupt Flag Accumulator Source Select" "0: PWM_CHn zero point,1: PWM_CHn period in channel n,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM_CHn Accumulator Stop Mode Enable Bits" "0: PWM_CHn Stop Mode Disable,1: PWM_CHn Stop Mode Enable"
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hexmask.long.byte 0x0 0.--7. 1. "IFACNT,PWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of PWM_CHn period occurs to set bit IFAIFn to request the PWM period interrupt. PWM flag will be set in every IFACNT[15:0] times of PWM period."
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group.long 0x150++0xB
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line.long 0x0 "PWM_AINTSTS,PWM Accumulator Interrupt Flag Register"
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bitfld.long 0x0 4. "IFAIF4,PWM_CH4 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in PWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 2. "IFAIF2,PWM_CH2 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in PWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 0. "IFAIF0,PWM_CH0 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in PWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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line.long 0x4 "PWM_AINTEN,PWM Accumulator Interrupt Enable Register"
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bitfld.long 0x4 4. "IFAIEN4,PWM_CH4 Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 2. "IFAIEN2,PWM_CH2 Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 0. "IFAIEN0,PWM_CH0 Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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line.long 0x8 "PWM_APDMACTL,PWM Accumulator PDMA Control Register"
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bitfld.long 0x8 5. "APDMAEN5,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 4. "APDMAEN4,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 3. "APDMAEN3,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 2. "APDMAEN2,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 1. "APDMAEN1,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 0. "APDMAEN0,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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group.long 0x200++0x7
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line.long 0x0 "PWM_CAPINEN,PWM Capture Input Enable Register"
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bitfld.long 0x0 5. "CAPINEN5,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 4. "CAPINEN4,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 3. "CAPINEN3,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 2. "CAPINEN2,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 1. "CAPINEN1,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 0. "CAPINEN0,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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line.long 0x4 "PWM_CAPCTL,PWM Capture Control Register"
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bitfld.long 0x4 29. "FCRLDEN5,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 28. "FCRLDEN4,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 27. "FCRLDEN3,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 26. "FCRLDEN2,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 25. "FCRLDEN1,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 24. "FCRLDEN0,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 21. "RCRLDEN5,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 20. "RCRLDEN4,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 19. "RCRLDEN3,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 18. "RCRLDEN2,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 17. "RCRLDEN1,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 16. "RCRLDEN0,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 13. "CAPINV5,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 12. "CAPINV4,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 11. "CAPINV3,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 10. "CAPINV2,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 9. "CAPINV1,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 8. "CAPINV0,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 5. "CAPEN5,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 4. "CAPEN4,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 3. "CAPEN3,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 2. "CAPEN2,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 1. "CAPEN1,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 0. "CAPEN0,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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rgroup.long 0x208++0x33
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line.long 0x0 "PWM_CAPSTS,PWM Capture Status Register"
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bitfld.long 0x0 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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bitfld.long 0x0 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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bitfld.long 0x0 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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bitfld.long 0x0 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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bitfld.long 0x0 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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bitfld.long 0x0 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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line.long 0x4 "PWM_RCAPDAT0,PWM Rising Capture Data Register 0"
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hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x8 "PWM_FCAPDAT0,PWM Falling Capture Data Register 0"
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hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
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line.long 0xC "PWM_RCAPDAT1,PWM Rising Capture Data Register 1"
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hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x10 "PWM_FCAPDAT1,PWM Falling Capture Data Register 1"
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hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
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|
line.long 0x14 "PWM_RCAPDAT2,PWM Rising Capture Data Register 2"
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hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
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|
line.long 0x18 "PWM_FCAPDAT2,PWM Falling Capture Data Register 2"
|
|
hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x1C "PWM_RCAPDAT3,PWM Rising Capture Data Register 3"
|
|
hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x20 "PWM_FCAPDAT3,PWM Falling Capture Data Register 3"
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hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x24 "PWM_RCAPDAT4,PWM Rising Capture Data Register 4"
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|
hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x28 "PWM_FCAPDAT4,PWM Falling Capture Data Register 4"
|
|
hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x2C "PWM_RCAPDAT5,PWM Rising Capture Data Register 5"
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|
hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x30 "PWM_FCAPDAT5,PWM Falling Capture Data Register 5"
|
|
hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
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|
group.long 0x23C++0x3
|
|
line.long 0x0 "PWM_PDMACTL,PWM PDMA Control Register"
|
|
bitfld.long 0x0 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel4,1: Channel5"
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bitfld.long 0x0 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order \nNote: If the PDMA function is not supported this bit field will become invalid." "0: PWM_FCAPDAT4/5 is the first captured data to..,1: PWM_RCAPDAT4/5 is the first captured data to.."
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newline
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bitfld.long 0x0 17.--18. "CAPMOD4_5,Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Reserved.,1: PWM_RCAPDAT4/5,?,?"
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bitfld.long 0x0 16. "CHEN4_5,Channel 4/5 PDMA Enable Bit\nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.."
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newline
|
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bitfld.long 0x0 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel2,1: Channel3"
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bitfld.long 0x0 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order \nNote: If the PDMA function is not supported this bit field will become invalid." "0: PWM_FCAPDAT2/3 is the first captured data to..,1: PWM_RCAPDAT2/3 is the first captured data to.."
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newline
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bitfld.long 0x0 9.--10. "CAPMOD2_3,Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Reserved.,1: PWM_RCAPDAT2/3,?,?"
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bitfld.long 0x0 8. "CHEN2_3,Channel 2/3 PDMA Enable Bit\nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.."
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|
newline
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bitfld.long 0x0 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel0,1: Channel1"
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bitfld.long 0x0 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order \nNote: If the PDMA function is not supported this bit field will become invalid." "0: PWM_FCAPDAT0/1 is the first captured data to..,1: PWM_RCAPDAT0/1 is the first captured data to.."
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newline
|
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bitfld.long 0x0 1.--2. "CAPMOD0_1,Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Reserved.,1: PWM_RCAPDAT0/1,?,?"
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bitfld.long 0x0 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit\nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.."
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|
rgroup.long 0x240++0xB
|
|
line.long 0x0 "PWM_PDMACAP0_1,PWM Capture Channel 01 PDMA Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.\nNote: If the PDMA function is not supported this bit field will become invalid."
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line.long 0x4 "PWM_PDMACAP2_3,PWM Capture Channel 23 PDMA Register"
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hexmask.long.word 0x4 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.\nNote: If the PDMA function is not supported this bit field will become invalid."
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|
line.long 0x8 "PWM_PDMACAP4_5,PWM Capture Channel 45 PDMA Register"
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|
hexmask.long.word 0x8 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.\nNote: If the PDMA function is not supported this bit field will become invalid."
|
|
group.long 0x250++0x23
|
|
line.long 0x0 "PWM_CAPIEN,PWM Capture Interrupt Enable Register"
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|
bitfld.long 0x0 13. "CAPFIEN5,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 12. "CAPFIEN4,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 11. "CAPFIEN3,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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|
bitfld.long 0x0 10. "CAPFIEN2,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 9. "CAPFIEN1,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 8. "CAPFIEN0,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 5. "CAPRIEN5,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x0 4. "CAPRIEN4,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 3. "CAPRIEN3,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
|
|
bitfld.long 0x0 2. "CAPRIEN2,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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newline
|
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bitfld.long 0x0 1. "CAPRIEN1,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
|
|
bitfld.long 0x0 0. "CAPRIEN0,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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line.long 0x4 "PWM_CAPIF,PWM Capture Interrupt Flag Register"
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bitfld.long 0x4 13. "CFLIF5,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 12. "CFLIF4,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 11. "CFLIF3,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 10. "CFLIF2,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 9. "CFLIF1,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 8. "CFLIF0,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 5. "CRLIF5,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 4. "CRLIF4,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 3. "CRLIF3,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 2. "CRLIF2,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 1. "CRLIF1,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 0. "CRLIF0,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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line.long 0x8 "PWM_CAPNF0,PWM Capture Input Noise Filter Register 0"
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bitfld.long 0x8 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x8 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0xC "PWM_CAPNF1,PWM Capture Input Noise Filter Register 1"
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bitfld.long 0xC 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0xC 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x10 "PWM_CAPNF2,PWM Capture Input Noise Filter Register 2"
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bitfld.long 0x10 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
|
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bitfld.long 0x10 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x14 "PWM_CAPNF3,PWM Capture Input Noise Filter Register 3"
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bitfld.long 0x14 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
|
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bitfld.long 0x14 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
|
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line.long 0x18 "PWM_CAPNF4,PWM Capture Input Noise Filter Register 4"
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bitfld.long 0x18 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
|
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bitfld.long 0x18 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x1C "PWM_CAPNF5,PWM Capture Input Noise Filter Register 5"
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bitfld.long 0x1C 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
|
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bitfld.long 0x1C 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x20 "PWM_EXTETCTL0,PWM External Event Trigger Control Register 0"
|
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hexmask.long.byte 0x20 8.--11. 1. "EXTTRGS,External Trigger Selection"
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bitfld.long 0x20 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
|
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bitfld.long 0x20 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
|
|
group.long 0x278++0x3
|
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line.long 0x0 "PWM_EXTETCTL2,PWM External Event Trigger Control Register 2"
|
|
hexmask.long.byte 0x0 8.--11. 1. "EXTTRGS,External Trigger Selection"
|
|
bitfld.long 0x0 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
|
|
newline
|
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bitfld.long 0x0 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "PWM_EXTETCTL4,PWM External Event Trigger Control Register 4"
|
|
hexmask.long.byte 0x0 8.--11. 1. "EXTTRGS,External Trigger Selection"
|
|
bitfld.long 0x0 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
|
|
newline
|
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bitfld.long 0x0 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
|
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group.long 0x288++0x7
|
|
line.long 0x0 "PWM_SWEOFCTL,PWM Software Event Output Force Control Register"
|
|
bitfld.long 0x0 10.--11. "OUTACTS5,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
|
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bitfld.long 0x0 8.--9. "OUTACTS4,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
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newline
|
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bitfld.long 0x0 6.--7. "OUTACTS3,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
|
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bitfld.long 0x0 4.--5. "OUTACTS2,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
|
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newline
|
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bitfld.long 0x0 2.--3. "OUTACTS1,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
|
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bitfld.long 0x0 0.--1. "OUTACTS0,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
|
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line.long 0x4 "PWM_SWEOFTRG,PWM Software Event Output Force Trigger Register"
|
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bitfld.long 0x4 5. "SWETRG5,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x4 4. "SWETRG4,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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newline
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bitfld.long 0x4 3. "SWETRG3,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x4 2. "SWETRG2,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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newline
|
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bitfld.long 0x4 1. "SWETRG1,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x4 0. "SWETRG0,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
|
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rgroup.long 0x304++0x3
|
|
line.long 0x0 "PWM_PBUF0,PWM PERIOD0 Buffer"
|
|
hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
|
|
rgroup.long 0x30C++0x3
|
|
line.long 0x0 "PWM_PBUF2,PWM PERIOD2 Buffer"
|
|
hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
|
|
rgroup.long 0x314++0x3
|
|
line.long 0x0 "PWM_PBUF4,PWM PERIOD4 Buffer"
|
|
hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
|
|
rgroup.long 0x31C++0x17
|
|
line.long 0x0 "PWM_CMPBUF0,PWM CMPDAT0 Buffer"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
line.long 0x4 "PWM_CMPBUF1,PWM CMPDAT1 Buffer"
|
|
hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
line.long 0x8 "PWM_CMPBUF2,PWM CMPDAT2 Buffer"
|
|
hexmask.long.word 0x8 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
line.long 0xC "PWM_CMPBUF3,PWM CMPDAT3 Buffer"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
line.long 0x10 "PWM_CMPBUF4,PWM CMPDAT4 Buffer"
|
|
hexmask.long.word 0x10 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
line.long 0x14 "PWM_CMPBUF5,PWM CMPDAT5 Buffer"
|
|
hexmask.long.word 0x14 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
tree.end
|
|
tree "SCS (System Controller Space)"
|
|
base ad:0xE000E000
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "SYST_CTRL,SysTick Control and Status Register"
|
|
bitfld.long 0x0 16. "COUNTFLAG,System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register." "0,1"
|
|
bitfld.long 0x0 2. "CLKSRC,System Tick Clock Source Selection" "0: Clock source is the (optional) external..,1: Core clock used for SysTick"
|
|
newline
|
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bitfld.long 0x0 1. "TICKINT,System Tick Interrupt Enabled" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
|
|
bitfld.long 0x0 0. "ENABLE,System Tick Counter Enabled" "0: Counter Disabled,1: Counter will operate in a multi-shot manner"
|
|
line.long 0x4 "SYST_LOAD,SysTick Reload Value Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,System Tick Reload Value\nThe value to load into the Current Value register when the counter reaches 0."
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line.long 0x8 "SYST_VAL,SysTick Current Value Register"
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hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-Write Protect. The register is write-clear. A software write of any value will clear the.."
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group.long 0xD04++0xF
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line.long 0x0 "ICSR,Interrupt Control and State Register"
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bitfld.long 0x0 31. "NMIPENDSET,NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0." "0: No effect.\nNMI exception is not pending,1: Changes NMI exception state to pending.\nNMI.."
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bitfld.long 0x0 28. "PENDSVSET,PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending." "0: No effect.\nPendSV exception is not pending,1: Changes PendSV exception state to.."
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bitfld.long 0x0 27. "PENDSVCLR,PendSV Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDSV bit you must 'write 0 to PENDSVSET and write 1 to PENDSVRTC_CAL' at the same time." "0: No effect,1: Removes the pending state from the PendSV.."
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bitfld.long 0x0 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite Operation:" "0: No effect.\nSysTick exception is not pending,1: Changes SysTick exception state to.."
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bitfld.long 0x0 25. "PENDSTCLR,SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDST bit you must 'write 0 to PENDSTSET and write 1 to PENDSTRTC_CAL' at the same time." "0: No effect,1: Removes the pending state from the SysTick.."
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rbitfld.long 0x0 23. "ISRPREEMPT,Interrupt Preempt Bit (Read Only)\nIf set a pending exception will be serviced on exit from the debug halt state." "0,1"
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rbitfld.long 0x0 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults (Read Only)" "0: Interrupt not pending,1: Interrupt pending"
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hexmask.long.byte 0x0 12.--17. 1. "VECTPENDING,Number of the Highest Pended Exception\nIndicate the Exception Number of the Highest Priority Pending Enabled Exception\nThe value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers but not any effect of the.."
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bitfld.long 0x0 11. "RETTOBASE,Preempted Active Exceptions Indicator\nIndicate whether There are Preempted Active Exceptions" "0: there are preempted active exceptions to execute,1: there are no active exceptions or the.."
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hexmask.long.byte 0x0 0.--5. 1. "VECTACTIVE,Number of the Current Active Exception"
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line.long 0x4 "VTOR,Vector Table Offset Register"
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hexmask.long 0x4 7.--31. 1. "TBLOFF,Table Offset Bits\nThe vector table address for the selected Security state."
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line.long 0x8 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x8 16.--31. 1. "VECTORKEY,Register Access Key\nWhen writing this register this field should be 0x05FA otherwise the write action will be unpredictable.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of.."
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bitfld.long 0x8 15. "ENDIANNESS,Data Endianness" "0: Little-endian,1: Big-endian"
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bitfld.long 0x8 8.--10. "PRIGROUP,Interrupt Priority Grouping\nThis field determines the Split Of Group priority from subpriority " "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 2. "SYSRESETREQ,System Reset Request\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence." "0,1"
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bitfld.long 0x8 1. "VECTCLRACTIVE,Exception Active Status Clear Bit\nSetting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThis bit is write only and can only be written when the core is halted.\nNote: It is the debugger's.." "0,1"
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bitfld.long 0x8 0. "VECTRESET,Reserved." "0,1"
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line.long 0xC "SCR,System Control Register"
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bitfld.long 0xC 4. "SEVONPEND,Send Event on Pending\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE. If the processor is not waiting for an event the event is registered and affects the next WFE.\nThe processor also wakes.." "0: Only enabled interrupts or events can wake up..,1: Enabled events and all interrupts including.."
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bitfld.long 0xC 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection\nControl Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode." "0: Sleep,1: Deep sleep"
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bitfld.long 0xC 1. "SLEEPONEXIT,Sleep-on-exit Enable Control\nThis bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nNote: Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application." "0: Do not sleep when returning to Thread mode,1: Enter sleep or deep sleep on return from an ISR.."
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group.long 0xD18++0xB
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line.long 0x0 "SHPR1,System Handler Priority Register 1"
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hexmask.long.byte 0x0 16.--23. 1. "PRI_6,Priority of system handler 6 UsageFault"
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hexmask.long.byte 0x0 8.--15. 1. "PRI_5,Priority of system handler 5 BusFault"
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hexmask.long.byte 0x0 0.--7. 1. "PRI_4,Priority of system handler 4 MemManage"
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line.long 0x4 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x4 30.--31. "PRI_11,Priority of System Handler 11 - SVCall\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
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line.long 0x8 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x8 30.--31. "PRI_15,Priority of System Handler 15 - SysTick\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
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bitfld.long 0x8 22.--23. "PRI_14,Priority of System Handler 14 - PendSV\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
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tree.end
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tree "SPI (Serial Peripheral Interface)"
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base ad:0x40061000
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group.long 0x0++0x17
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line.long 0x0 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x0 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer" "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 15. "RXONLY,Receive-only Mode Enable Bit\nThis bit field is only available in Master mode. In receive-only mode SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status." "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x0 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer." "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX register is sent.."
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hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 4 bits and can up to 32 bits.\nNote: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore .."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.."
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bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
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bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode this device is ready to receive data when this bit is set to 1.\nNote: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
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line.long 0x4 "SPIx_CLKDIV,SPI Clock Divider Register"
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hexmask.long.word 0x4 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral.."
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line.long 0x8 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x8 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode the SPI controller can work with 3-wire interface including SPIx_CLK SPIx_MISO and SPIx_MOSI pins." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit" "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled.."
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bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)." "0: The slave selection signal SPIx_SS is active low,1: The slave selection signal SPIx_SS is active high"
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bitfld.long 0x8 0. "SS,Slave Selection Control\nIf AUTOSS bit is cleared to 0 " "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active state.\nSPIx_SS.."
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line.long 0xC "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote 1: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: In SPI Master mode with full duplex transfer"
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line.long 0x10 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x10 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 4~16.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 10. "SLVBERX,RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error" "0: Uncompleted RX data will be dropped from RX FIFO..,1: Uncompleted RX data will be written into RX FIFO.."
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bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
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bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt." "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\nNote 2: When TX underflow event occurs SPIx_MISO pin state will be determined by this setting even.." "0: The SPI data out is keep 0 if there is TX..,1: The TX underflow event occurs if there is no any.."
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bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit."
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line.long 0x14 "SPIx_STATUS,SPI Status Register"
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hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer."
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hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled this bit indicates the real status of SPI controller." "0: SPI controller Disabled,1: SPI controller Enabled"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0 and the SSLINE is 1 the SPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt was cleared or..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt was cleared or not..,1: Slave select active interrupt event occurred"
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bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)\nNote: By applications this SPI busy flag should be used with other status registers in SPIx_STATUS such as TXCNT RXCNT TXTHIF TXFULL TXEMPTY RXTHIF RXFULL RXEMPTY and UNITIF. Therefore the SPI transfer done events.." "0: SPI controller is in idle state,1: SPI controller is in busy state"
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rgroup.long 0x18++0x3
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line.long 0x0 "SPIx_STATUS2,SPI Status2 Register"
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hexmask.long.byte 0x0 24.--29. 1. "SLVBENUM,Effective Bit Number of Uncompleted RX data \nThis status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode.\nThis status register.."
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wgroup.long 0x20++0x3
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line.long 0x0 "SPIx_TX,SPI Data Transmit Register"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode.\nIn SPI mode if DWIDTH is set to.."
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rgroup.long 0x30++0x3
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line.long 0x0 "SPIx_RX,SPI Data Receive Register"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8]) is not set to 1 the receive FIFO buffers can be accessed.."
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tree.end
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tree "SYS (System Control Registers)"
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base ad:0x40000000
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rgroup.long 0x0++0x3
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line.long 0x0 "SYS_PDID,Part Device Identification Number Register"
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hexmask.long 0x0 0.--31. 1. "PDID,Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used."
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group.long 0x4++0xF
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line.long 0x0 "SYS_RSTSTS,System Reset Status Register"
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bitfld.long 0x0 8. "CPULKRF,CPU Lockup Reset Flag\nNote 1: Write 1 to clear this bit to 0.\nNote 2: When CPU lockup happened under ICE is connected This flag will set to 1 but chip will not reset." "0: No reset from CPU lockup happened,1: Write 1 to clear this bit to 0"
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bitfld.long 0x0 7. "CPURF,CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex- M23 Core and Flash Memory Controller (FMC).\nNote: Write to clear this bit to 0." "0: No reset from CPU,1: The Cortex-M23 Core and FMC are reset by.."
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bitfld.long 0x0 5. "SYSRF,System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the Cortex-M23 Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from Cortex-M23,1: The Cortex- M23 had issued the reset signal to.."
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bitfld.long 0x0 4. "BODRF,BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from BOD,1: The BOD had issued the reset signal to reset the.."
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bitfld.long 0x0 3. "LVRF,LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from LVR,1: LVR controller had issued the reset signal to.."
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bitfld.long 0x0 2. "WDTRF,WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\nNote 1: Write 1 to clear this bit to 0.\nNote 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit.." "0: No reset from watchdog timer or window watchdog..,1: Write 1 to clear this bit to 0"
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bitfld.long 0x0 1. "PINRF,NRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to reset.."
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bitfld.long 0x0 0. "PORF,POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from POR or CHIPRST,1: Power-on Reset (POR) or CHIPRST had issued the.."
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line.long 0x4 "SYS_IPRST0,Peripheral Reset Control Register 0"
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bitfld.long 0x4 10. "CANFD2RST,CANFD2 Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CANFD2. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: CANFD2 normal operation,1: CANFD2 reset"
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bitfld.long 0x4 9. "CANFD1RST,CANFD1 Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CANFD1. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: CANFD1 normal operation,1: CANFD1 reset"
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bitfld.long 0x4 8. "CANFD0RST,CANFD0 Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CANFD0. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: CANFD0 normal operation,1: CANFD0 reset"
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bitfld.long 0x4 7. "CRCRST,CRC Calculation Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the.." "0: CRC calculation controller normal operation,1: CRC calculation controller reset"
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bitfld.long 0x4 2. "PDMA0RST,PDMA0 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA0. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PDMA0 controller normal operation,1: PDMA0 controller reset"
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bitfld.long 0x4 1. "CPURST,Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC) and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to.." "0: Processor core normal operation,1: Processor core one-shot reset"
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bitfld.long 0x4 0. "CHIPRST,Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset all the.." "0: Chip normal operation,1: Chip one-shot reset"
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line.long 0x8 "SYS_IPRST1,Peripheral Reset Control Register 1"
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bitfld.long 0x8 30. "ACMP01RST,Analog Comparator 0/1 Controller Reset" "0: Analog Comparator 0/1 controller normal operation,1: Analog Comparator 0/1 controller reset"
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bitfld.long 0x8 28. "ADC0RST,ADC0 Controller Reset" "0: ADC0 controller normal operation,1: ADC0 controller reset"
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bitfld.long 0x8 17. "UART1RST,UART1 Controller Reset" "0: UART1 controller normal operation,1: UART1 controller reset"
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bitfld.long 0x8 16. "UART0RST,UART0 Controller Reset" "0: UART0 controller normal operation,1: UART0 controller reset"
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newline
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bitfld.long 0x8 12. "SPI0RST,SPI0 Reset" "0: SPI0 controller normal operation,1: SPI0 controller reset"
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bitfld.long 0x8 8. "I2C0RST,I2C0 Reset" "0: I2C0 controller normal operation,1: I2C0 controller reset"
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bitfld.long 0x8 7. "WWDTRST,WWDT Controller Reset" "0: WWDT controller normal operation,1: WWDT controller reset"
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bitfld.long 0x8 5. "TMR3RST,Timer3 Controller Reset" "0: Timer3 controller normal operation,1: Timer3 controller reset"
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bitfld.long 0x8 4. "TMR2RST,Timer2 Controller Reset" "0: Timer2 controller normal operation,1: Timer2 controller reset"
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bitfld.long 0x8 3. "TMR1RST,Timer1 Controller Reset" "0: Timer1 controller normal operation,1: Timer1 controller reset"
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bitfld.long 0x8 2. "TMR0RST,Timer0 Controller Reset" "0: Timer0 controller normal operation,1: Timer0 controller reset"
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bitfld.long 0x8 1. "GPIORST,GPIO Controller Reset" "0: GPIO controller normal operation,1: GPIO controller reset"
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line.long 0xC "SYS_IPRST2,Peripheral Reset Control Register 2"
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bitfld.long 0xC 17. "LLSI1RST,LLSI1 Controller Reset" "0: LLSI1 controller normal operation,1: LLSI1 controller reset"
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bitfld.long 0xC 16. "LLSI0RST,LLSI0 Controller Reset" "0: LLSI0 controller normal operation,1: LLSI0 controller reset"
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bitfld.long 0xC 9. "USCI1RST,USCI1 Controller Reset" "0: USCI1 controller normal operation,1: USCI1 controller reset"
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bitfld.long 0xC 8. "USCI0RST,USCI0 Controller Reset" "0: USCI0 controller normal operation,1: USCI0 controller reset"
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bitfld.long 0xC 4. "BPWM0RST,BPWM0 Controller Reset" "0: BPWM0 controller normal operation,1: BPWM0 controller reset"
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bitfld.long 0xC 0. "PWM0RST,PWM0 Controller Reset" "0: PWM0 controller normal operation,1: PWM0 controller reset"
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group.long 0x18++0x7
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line.long 0x0 "SYS_BODCTL,Brown-out Detector Control Register"
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bitfld.long 0x0 16.--17. "BODVL,Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by Flash controller user configuration register CBOV (CONFIG0 [22:21]).\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Brown-Out Detector threshold voltage is 2.3V,1: Brown-Out Detector threshold voltage is 2.7V,?,?"
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bitfld.long 0x0 12.--14. "LVRDGSEL,LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Without de-glitch function,1: 64 system clock (HCLK),?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "BODDGSEL,Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: BOD output is sampled by RC32K clock,1: 64 system clock (HCLK),?,?,?,?,?,?"
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bitfld.long 0x0 7. "LVREN,Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote 1: After enabling the bit the LVR function will be active with.." "0: Low Voltage Reset function Disabled,1: After enabling the bit"
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rbitfld.long 0x0 6. "BODOUT,Brown-out Detector Output Status (Read Only)\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0 BOD function disabled this bit always responds 0." "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1"
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bitfld.long 0x0 5. "BODLPM,Brown-out Detector Low Power Mode (Write Protect)\nNote 1: The BOD consumes about 100uA in normal mode the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote 2: This bit is write protected. Refer to the.." "0: BOD operate in normal mode (default),1: The BOD consumes about 100uA in normal mode"
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newline
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bitfld.long 0x0 4. "BODIF,Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0." "0: Brown-out Detector does not detect any voltage..,1: When Brown-out Detector detects the VDD is.."
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bitfld.long 0x0 3. "BODRSTEN,Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit .\nNote 1: \nWhile the Brown-out Detector function is enabled (BODEN high) and BOD reset function is.." "0: Brown-out 'INTERRUPT' function Enabled,1: \nWhile the Brown-out Detector function is enabled"
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newline
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bitfld.long 0x0 0. "BODEN,Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled"
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line.long 0x4 "SYS_IVSCTL,Internal Voltage Source Control Register"
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bitfld.long 0x4 2. "AVDDDIVEN,AVDD Divide 4 Enable Bit\nThis bit is used to enable/disable AVDD divide 4 function.\nNote: After this bit is set to 1 the value of AVDD divide 4 output voltage can be obtained from ADC conversion result." "0: AVDD divide 4 function Disabled (default),1: AVDD divide 4 function Enabled"
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bitfld.long 0x4 0. "VTEMPEN,Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1 the value of temperature sensor output can be obtained from ADC conversion result. Please refer to ADC function.." "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled"
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group.long 0x24++0x3
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line.long 0x0 "SYS_PORCTL,Power-On-reset Controller Register"
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hexmask.long.word 0x0 0.--15. 1. "POROFF,Power-on Reset Enable Bit (Write Protect)\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid.."
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group.long 0x30++0x1F
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line.long 0x0 "SYS_GPA_MFPL,GPIOA Low Byte Multiple Function Control Register"
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hexmask.long.byte 0x0 28.--31. 1. "PA7MFP,PA.7 Multi-function Pin Selection"
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hexmask.long.byte 0x0 24.--27. 1. "PA6MFP,PA.6 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x0 20.--23. 1. "PA5MFP,PA.5 Multi-function Pin Selection"
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hexmask.long.byte 0x0 16.--19. 1. "PA4MFP,PA.4 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x0 12.--15. 1. "PA3MFP,PA.3 Multi-function Pin Selection"
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hexmask.long.byte 0x0 8.--11. 1. "PA2MFP,PA.2 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "PA1MFP,PA.1 Multi-function Pin Selection"
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hexmask.long.byte 0x0 0.--3. 1. "PA0MFP,PA.0 Multi-function Pin Selection"
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line.long 0x4 "SYS_GPA_MFPH,GPIOA High Byte Multiple Function Control Register"
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hexmask.long.byte 0x4 28.--31. 1. "PA15MFP,PA.15 Multi-function Pin Selection"
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hexmask.long.byte 0x4 24.--27. 1. "PA14MFP,PA.14 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x4 20.--23. 1. "PA13MFP,PA.13 Multi-function Pin Selection"
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hexmask.long.byte 0x4 16.--19. 1. "PA12MFP,PA.12 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x4 12.--15. 1. "PA11MFP,PA.11 Multi-function Pin Selection"
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hexmask.long.byte 0x4 8.--11. 1. "PA10MFP,PA.10 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x4 4.--7. 1. "PA9MFP,PA.9 Multi-function Pin Selection"
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hexmask.long.byte 0x4 0.--3. 1. "PA8MFP,PA.8 Multi-function Pin Selection"
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line.long 0x8 "SYS_GPB_MFPL,GPIOB Low Byte Multiple Function Control Register"
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hexmask.long.byte 0x8 28.--31. 1. "PB7MFP,PB.7 Multi-function Pin Selection"
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hexmask.long.byte 0x8 24.--27. 1. "PB6MFP,PB.6 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x8 20.--23. 1. "PB5MFP,PB.5 Multi-function Pin Selection"
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hexmask.long.byte 0x8 16.--19. 1. "PB4MFP,PB.4 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x8 12.--15. 1. "PB3MFP,PB.3 Multi-function Pin Selection"
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hexmask.long.byte 0x8 8.--11. 1. "PB2MFP,PB.2 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x8 4.--7. 1. "PB1MFP,PB.1 Multi-function Pin Selection"
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hexmask.long.byte 0x8 0.--3. 1. "GPB0MFP,PB.0 Multi-function Pin Selection"
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line.long 0xC "SYS_GPB_MFPH,GPIOB High Byte Multiple Function Control Register"
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hexmask.long.byte 0xC 28.--31. 1. "PB15MFP,PB.15 Multi-function Pin Selection"
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hexmask.long.byte 0xC 24.--27. 1. "PB14MFP,PB.14 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0xC 20.--23. 1. "PB13MFP,PB.13 Multi-function Pin Selection"
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hexmask.long.byte 0xC 16.--19. 1. "PB12MFP,PB.12 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0xC 12.--15. 1. "PB11MFP,PB.11 Multi-function Pin Selection"
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hexmask.long.byte 0xC 8.--11. 1. "PB10MFP,PB.10 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0xC 4.--7. 1. "PB9MFP,PB.9 Multi-function Pin Selection"
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hexmask.long.byte 0xC 0.--3. 1. "PB8MFP,PB.8 Multi-function Pin Selection"
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line.long 0x10 "SYS_GPC_MFPL,GPIOC Low Byte Multiple Function Control Register"
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hexmask.long.byte 0x10 28.--31. 1. "PC7MFP,PC.7 Multi-function Pin Selection"
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hexmask.long.byte 0x10 24.--27. 1. "PC6MFP,PC.6 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x10 20.--23. 1. "PC5MFP,PC.5 Multi-function Pin Selection"
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hexmask.long.byte 0x10 16.--19. 1. "PC4MFP,PC.4 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x10 12.--15. 1. "PC3MFP,PC.3 Multi-function Pin Selection"
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hexmask.long.byte 0x10 8.--11. 1. "PC2MFP,PC.2 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x10 4.--7. 1. "PC1MFP,PC.1 Multi-function Pin Selection"
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hexmask.long.byte 0x10 0.--3. 1. "PC0MFP,PC.0 Multi-function Pin Selection"
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line.long 0x14 "SYS_GPC_MFPH,GPIOC High Byte Multiple Function Control Register"
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hexmask.long.byte 0x14 28.--31. 1. "PC15MFP,PC.15 Multi-function Pin Selection"
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hexmask.long.byte 0x14 24.--27. 1. "PC14MFP,PC.14 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x14 20.--23. 1. "PC13MFP,PC.13 Multi-function Pin Selection"
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hexmask.long.byte 0x14 16.--19. 1. "PC12MFP,PC.12 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x14 12.--15. 1. "PC11MFP,PC.11 Multi-function Pin Selection"
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hexmask.long.byte 0x14 8.--11. 1. "PC10MFP,PC.10 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x14 4.--7. 1. "PC9MFP,PC.9 Multi-function Pin Selection"
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hexmask.long.byte 0x14 0.--3. 1. "PC8MFP,PC.8 Multi-function Pin Selection"
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line.long 0x18 "SYS_GPD_MFPL,GPIOD Low Byte Multiple Function Control Register"
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hexmask.long.byte 0x18 28.--31. 1. "PD7MFP,PD.7 Multi-function Pin Selection"
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hexmask.long.byte 0x18 24.--27. 1. "PD6MFP,PD.6 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x18 20.--23. 1. "PD5MFP,PD.5 Multi-function Pin Selection"
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hexmask.long.byte 0x18 16.--19. 1. "PD4MFP,PD.4 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x18 12.--15. 1. "PD3MFP,PD.3 Multi-function Pin Selection"
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hexmask.long.byte 0x18 8.--11. 1. "PD2MFP,PD.2 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x18 4.--7. 1. "PD1MFP,PD.1 Multi-function Pin Selection"
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hexmask.long.byte 0x18 0.--3. 1. "PD0MFP,PD.0 Multi-function Pin Selection"
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line.long 0x1C "SYS_GPD_MFPH,GPIOD High Byte Multiple Function Control Register"
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hexmask.long.byte 0x1C 28.--31. 1. "PD15MFP,PD.15 Multi-function Pin Selection"
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hexmask.long.byte 0x1C 24.--27. 1. "PD14MFP,PD.14 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x1C 20.--23. 1. "PD13MFP,PD.13 Multi-function Pin Selection"
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hexmask.long.byte 0x1C 16.--19. 1. "PD12MFP,PD.12 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x1C 12.--15. 1. "PD11MFP,PD.11 Multi-function Pin Selection"
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hexmask.long.byte 0x1C 8.--11. 1. "PD10MFP,PD.10 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x1C 4.--7. 1. "PD9MFP,PD.9 Multi-function Pin Selection"
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hexmask.long.byte 0x1C 0.--3. 1. "PD8MFP,PD.8 Multi-function Pin Selection"
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group.long 0x58++0x7
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line.long 0x0 "SYS_GPF_MFPL,GPIOF Low Byte Multiple Function Control Register"
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hexmask.long.byte 0x0 28.--31. 1. "PF7MFP,PF.7 Multi-function Pin Selection"
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hexmask.long.byte 0x0 24.--27. 1. "PF6MFP,PF.6 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x0 20.--23. 1. "PF5MFP,PF.5 Multi-function Pin Selection"
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hexmask.long.byte 0x0 16.--19. 1. "PF4MFP,PF.4 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x0 12.--15. 1. "PF3MFP,PF.3 Multi-function Pin Selection"
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hexmask.long.byte 0x0 8.--11. 1. "PF2MFP,PF.2 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "PF1MFP,PF.1 Multi-function Pin Selection"
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hexmask.long.byte 0x0 0.--3. 1. "PF0MFP,PF.0 Multi-function Pin Selection"
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line.long 0x4 "SYS_GPF_MFPH,GPIOF High Byte Multiple Function Control Register"
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hexmask.long.byte 0x4 28.--31. 1. "PF15MFP,PF.15 Multi-function Pin Selection"
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hexmask.long.byte 0x4 24.--27. 1. "PF14MFP,PF.14 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x4 20.--23. 1. "PF13MFP,PF.13 Multi-function Pin Selection"
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hexmask.long.byte 0x4 16.--19. 1. "PF12MFP,PF.12 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x4 12.--15. 1. "PF11MFP,PF.11 Multi-function Pin Selection"
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hexmask.long.byte 0x4 8.--11. 1. "PF10MFP,PF.10 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x4 4.--7. 1. "PF9MFP,PF.9 Multi-function Pin Selection"
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hexmask.long.byte 0x4 0.--3. 1. "PF8MFP,PF.8 Multi-function Pin Selection"
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group.long 0x80++0xF
|
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line.long 0x0 "SYS_GPA_MFOS,GPIOA Multiple Function Output Select Register"
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bitfld.long 0x0 15. "MFOS15,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 14. "MFOS14,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x0 13. "MFOS13,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 12. "MFOS12,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x0 11. "MFOS11,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 10. "MFOS10,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x0 9. "MFOS9,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 8. "MFOS8,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x0 7. "MFOS7,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 6. "MFOS6,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x0 5. "MFOS5,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 4. "MFOS4,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 3. "MFOS3,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 2. "MFOS2,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 1. "MFOS1,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 0. "MFOS0,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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line.long 0x4 "SYS_GPB_MFOS,GPIOB Multiple Function Output Select Register"
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bitfld.long 0x4 15. "MFOS15,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x4 14. "MFOS14,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x4 13. "MFOS13,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x4 12. "MFOS12,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x4 11. "MFOS11,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x4 10. "MFOS10,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x4 9. "MFOS9,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x4 8. "MFOS8,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x4 7. "MFOS7,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x4 6. "MFOS6,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x4 5. "MFOS5,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x4 4. "MFOS4,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x4 3. "MFOS3,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x4 2. "MFOS2,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x4 1. "MFOS1,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x4 0. "MFOS0,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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line.long 0x8 "SYS_GPC_MFOS,GPIOC Multiple Function Output Select Register"
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bitfld.long 0x8 15. "MFOS15,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x8 14. "MFOS14,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x8 13. "MFOS13,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x8 12. "MFOS12,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x8 11. "MFOS11,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x8 10. "MFOS10,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x8 9. "MFOS9,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x8 8. "MFOS8,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x8 7. "MFOS7,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x8 6. "MFOS6,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x8 5. "MFOS5,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x8 4. "MFOS4,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x8 3. "MFOS3,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x8 2. "MFOS2,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x8 1. "MFOS1,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x8 0. "MFOS0,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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line.long 0xC "SYS_GPD_MFOS,GPIOD Multiple Function Output Select Register"
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bitfld.long 0xC 15. "MFOS15,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0xC 14. "MFOS14,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0xC 13. "MFOS13,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0xC 12. "MFOS12,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0xC 11. "MFOS11,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0xC 10. "MFOS10,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0xC 9. "MFOS9,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0xC 8. "MFOS8,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0xC 7. "MFOS7,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0xC 6. "MFOS6,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0xC 5. "MFOS5,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0xC 4. "MFOS4,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0xC 3. "MFOS3,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0xC 2. "MFOS2,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0xC 1. "MFOS1,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0xC 0. "MFOS0,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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group.long 0x94++0x3
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line.long 0x0 "SYS_GPF_MFOS,GPIOF Multiple Function Output Select Register"
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bitfld.long 0x0 15. "MFOS15,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 14. "MFOS14,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 13. "MFOS13,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 12. "MFOS12,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 11. "MFOS11,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 10. "MFOS10,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 9. "MFOS9,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 8. "MFOS8,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 7. "MFOS7,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 6. "MFOS6,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 5. "MFOS5,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 4. "MFOS4,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 3. "MFOS3,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 2. "MFOS2,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 1. "MFOS1,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x0 0. "MFOS0,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nNote: \nFor more information about Px.n please refer to the PIN CONFIGURATION chapter.\nIf MFOS is enabled then.." "0: Multiple funtion pin output mode type is unchanged,1: Multiple funtion pin output mode type is.."
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group.long 0xC0++0x7
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line.long 0x0 "SYS_SRAM_INTCTL,System SRAM Interrupt Enable Control Register"
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bitfld.long 0x0 0. "PERRIEN,SRAM Parity Check Error Interrupt Enable Bit" "0: SRAM parity check error interrupt Disabled,1: SRAM parity check error interrupt Enabled"
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line.long 0x4 "SYS_SRAM_STATUS,System SRAM Parity Error Status Register"
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bitfld.long 0x4 0. "PERRIF,SRAM Parity Check Error Flag\nThis bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0." "0: No System SRAM parity error,1: System SRAM parity error occur"
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rgroup.long 0xC8++0x3
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line.long 0x0 "SYS_SRAM_ERRADDR,System SRAM Parity Check Error Address Register"
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hexmask.long 0x0 0.--31. 1. "ERRADDR,System SRAM Parity Error Address (Read Only)\nThis register shows system SRAM parity error byte address."
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group.long 0xD0++0x3
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line.long 0x0 "SYS_SRAM_BISTCTL,System SRAM BIST Test Control Register"
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bitfld.long 0x0 3. "CANBIST,CAN SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for CAN SRAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: CAN SRAM BIST Disabled,1: CAN SRAM BIST Enabled"
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bitfld.long 0x0 2. "CRBIST,CACHE SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for CACHE SRAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: CACHE SRAM BIST Disabled,1: CACHE SRAM BIST Enabled"
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bitfld.long 0x0 1. "SRBIST1,System SRAM Bank1 BIST Enable Bit (Write Protect)\nThis bit enables BIST test for system SRAM bank1.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.." "0: System SRAM bank1 BIST Disabled,1: System SRAM bank1 BIST Enabled"
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bitfld.long 0x0 0. "SRBIST0,System SRAM Bank0 BIST Enable Bit (Write Protect)\nThis bit enables BIST test for system SRAM bank0.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: System SRAM bank0 BIST Disabled,1: System SRAM bank0 BIST Enabled"
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rgroup.long 0xD4++0x3
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line.long 0x0 "SYS_SRAM_BISTSTS,System SRAM BIST Test Status Register"
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bitfld.long 0x0 19. "CANBEND,CAN SRAM BIST Test Finish (Read Only)\nNote: When all of the CAN SRAM BIST finish this flag is 1." "0: CAN SRAM BIST is active,1: CAN SRAM BIST test finish"
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bitfld.long 0x0 18. "CRBEND,CACHE SRAM BIST Test Finish (Read Only)" "0: CACHE SRAM BIST is active,1: CACHE SRAM BIST test finish"
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bitfld.long 0x0 17. "SRBEND0,System SRAM Bank1 BIST Test Finish (Read Only)" "0: System SRAM Bank1 BIST active,1: System SRAM Bank1 BIST finish"
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bitfld.long 0x0 16. "SRBEND1,System SRAM Bank0 BIST Test Finish (Read Only)" "0: System SRAM bank0 BIST active,1: System SRAM bank0 BIST finish"
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bitfld.long 0x0 3. "CANBEF,CAN SRAM BIST Fail Flag (Read Only)\nNote: If any of the CAN SRAM macros BIST fail this flag is 1." "0: CAN SRAM BIST test pass,1: CAN SRAM BIST test fail"
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bitfld.long 0x0 2. "CRBEF,CACHE SRAM BIST Failed Flag (Read Only)" "0: CACHE SRAM BIST pass,1: CACHE SRAM BIST failed"
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bitfld.long 0x0 1. "SRBEF1,System SRAM Bank1 BIST Fail Flag (Read Only)" "0: System SRAM bank1 BIST test pass,1: System SRAM bank1 BIST test fail"
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bitfld.long 0x0 0. "SRBEF0,System SRAM Bank0 BIST Fail Flag (Read Only)" "0: System SRAM bank0 BIST test pass,1: System SRAM bank0 BIST test fail"
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group.long 0xF0++0xB
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line.long 0x0 "SYS_HIRCTRIMCTL,HIRC Trim Control Register"
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hexmask.long.byte 0x0 16.--20. 1. "BOUNDARY,Boundary Selection\nFill the boundary range from 0x1 to 0x1F 0x0 is reserved.\nNote: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enable."
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bitfld.long 0x0 10. "REFCKSEL,Reference Clock Selection\nNote: If there is no reference clock (LXT) when the rc_trim is enabled CLKERIF (SYS_HIRCTRIMSTS[2]) will be set to 1." "0: HIRC trim reference clock is from LXT (32.768 kHz),1: Reserved."
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bitfld.long 0x0 9. "BOUNDEN,Boundary Enable Bit" "0: Boundary function Disabled,1: Boundary function Enabled"
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bitfld.long 0x0 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.."
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bitfld.long 0x0 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,?,?"
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bitfld.long 0x0 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?"
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bitfld.long 0x0 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation if clock error detected with CESTOPEN is set to 1 or trim retry limitation count.." "0: Disable HIRC auto trim function,1: Enable HIRC auto trim function and trim HIRC to..,?,?"
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line.long 0x4 "SYS_HIRCTRIMIEN,HIRC Trim Interrupt Enable Register"
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bitfld.long 0x4 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERIF(SYS_HIRCTRIMSTS[2]) is set during auto trim operation an interrupt will.." "0: Disable CLKERIF(SYS_HIRCTRIMSTS[2]) status to..,1: Enable CLKERIF(SYS_HIRCTRIMSTS[2]) status to.."
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bitfld.long 0x4 1. "TFALIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTRIMCTL[1:0]).\nIf this.." "0: Disable TFAILIF(SYS_HIRCTRIMSTS[1]) status to..,1: Enable TFAILIF(SYS_HIRCTRIMSTS[1]) status to.."
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line.long 0x8 "SYS_HIRCTRIMSTS,HIRC Trim Interrupt Status Register"
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bitfld.long 0x8 3. "OVBDIF,Over Boundary Status\nWhen the over boundary function is set if there occurs the over boundary condition this flag will be set.\nNote: Write 1 to clear this flag." "0: Over boundary coundition did not occur,1: Over boundary coundition occurred"
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bitfld.long 0x8 2. "CLKERIF,Clock Error Interrupt Status\nWhen the frequency relation between reference clock and 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value this bit will be set and to be an indicate that clock frequency is.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy"
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bitfld.long 0x8 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set the auto trim operation stopped and FREQSEL(SYS_HIRCTRIMCTL[1:0]).." "0: Trim value update limitation count does not reach,1: Trim value update limitation count reached and.."
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bitfld.long 0x8 0. "FREQLOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt\nWrite 1 to clear this to 0. This bit will be set automatically if the frequecy is lock and the RC_TRIM is.." "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.."
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wgroup.long 0x100++0x3
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line.long 0x0 "SYS_REGLCTL,Register Lock Control Register"
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hexmask.long.byte 0x0 0.--7. 1. "REGLCTL,Register Lock Control Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h' '16h' '88h' to this field. After this sequence is.."
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group.long 0x1EC++0x3
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line.long 0x0 "SYS_PORDISAN,Analog POR Disable Control Register"
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hexmask.long.word 0x0 0.--15. 1. "POROFFAN,Power-on Reset Enable Bit (Write Protect)\nAfter powered on User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field.\nThe analog POR circuit will be active again when this field is set to another value or.."
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tree.end
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tree "TIMER (Timer Controller)"
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base ad:0x0
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tree "TMR01"
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base ad:0x40050000
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group.long 0x0++0xF
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line.long 0x0 "TIMER0_CTL,Timer0 Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
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bitfld.long 0x0 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
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line.long 0x4 "TIMER0_CMP,Timer0 Comparator Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT field .."
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line.long 0x8 "TIMER0_INTSTS,Timer0 Interrupt Status Register"
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bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
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line.long 0xC "TIMER0_CNT,Timer0 Data Register"
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rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.."
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hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value.."
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rgroup.long 0x10++0x3
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line.long 0x0 "TIMER0_CAP,Timer0 Capture Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the.."
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group.long 0x14++0xB
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line.long 0x0 "TIMER0_EXTCTL,Timer0 External Control Register"
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hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Set INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source."
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bitfld.long 0x0 16.--17. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external TMx..,1: Reserved.,?,?"
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bitfld.long 0x0 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1..,?,?,?,?,?,?"
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bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x0 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source." "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
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line.long 0x4 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register"
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rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clear corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
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bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer.." "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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line.long 0x8 "TIMER0_TRGCTL,Timer0 Trigger Control Register"
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bitfld.long 0x8 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x8 2. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered ADC conversion." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
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bitfld.long 0x8 1. "TRGPWM,Trigger PWM/BPWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM/BPWM counter clock source." "0: Timer interrupt trigger PWM/BPWM Disabled,1: Timer interrupt trigger PWM/BPWM Enabled"
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bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x24++0x3
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line.long 0x0 "TIMER0_CAPNF,Timer0 Capture Input Noise Filter Register"
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bitfld.long 0x0 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is ECLKx,1: Noise filter clock is ECLKx/2,?,?,?,?,?,?"
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bitfld.long 0x0 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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group.long 0x100++0xF
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line.long 0x0 "TIMER1_CTL,Timer1 Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
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bitfld.long 0x0 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
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line.long 0x4 "TIMER1_CMP,Timer1 Comparator Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT field .."
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line.long 0x8 "TIMER1_INTSTS,Timer1 Interrupt Status Register"
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bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
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line.long 0xC "TIMER1_CNT,Timer1 Data Register"
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rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.."
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hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value.."
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rgroup.long 0x110++0x3
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line.long 0x0 "TIMER1_CAP,Timer1 Capture Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the.."
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group.long 0x114++0xB
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line.long 0x0 "TIMER1_EXTCTL,Timer1 External Control Register"
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hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Set INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source."
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bitfld.long 0x0 16.--17. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external TMx..,1: Reserved.,?,?"
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bitfld.long 0x0 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1..,?,?,?,?,?,?"
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bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x0 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source." "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
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line.long 0x4 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register"
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rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clear corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
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bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer.." "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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line.long 0x8 "TIMER1_TRGCTL,Timer1 Trigger Control Register"
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bitfld.long 0x8 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x8 2. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered ADC conversion." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
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bitfld.long 0x8 1. "TRGPWM,Trigger PWM/BPWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM/BPWM counter clock source." "0: Timer interrupt trigger PWM/BPWM Disabled,1: Timer interrupt trigger PWM/BPWM Enabled"
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bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x124++0x3
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line.long 0x0 "TIMER1_CAPNF,Timer1 Capture Input Noise Filter Register"
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bitfld.long 0x0 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is ECLKx,1: Noise filter clock is ECLKx/2,?,?,?,?,?,?"
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bitfld.long 0x0 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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tree.end
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tree "TMR23"
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base ad:0x40051000
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group.long 0x0++0xF
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line.long 0x0 "TIMER2_CTL,Timer2 Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
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bitfld.long 0x0 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
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line.long 0x4 "TIMER2_CMP,Timer2 Comparator Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT field .."
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line.long 0x8 "TIMER2_INTSTS,Timer2 Interrupt Status Register"
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bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
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line.long 0xC "TIMER2_CNT,Timer2 Data Register"
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rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.."
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hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value.."
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rgroup.long 0x10++0x3
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line.long 0x0 "TIMER2_CAP,Timer2 Capture Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the.."
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group.long 0x14++0xB
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line.long 0x0 "TIMER2_EXTCTL,Timer2 External Control Register"
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hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Set INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source."
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bitfld.long 0x0 16.--17. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external TMx..,1: Reserved.,?,?"
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bitfld.long 0x0 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1..,?,?,?,?,?,?"
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bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x0 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source." "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
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line.long 0x4 "TIMER2_EINTSTS,Timer2 External Interrupt Status Register"
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rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clear corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
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bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer.." "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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line.long 0x8 "TIMER2_TRGCTL,Timer2 Trigger Control Register"
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bitfld.long 0x8 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x8 2. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered ADC conversion." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
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bitfld.long 0x8 1. "TRGPWM,Trigger PWM/BPWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM/BPWM counter clock source." "0: Timer interrupt trigger PWM/BPWM Disabled,1: Timer interrupt trigger PWM/BPWM Enabled"
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bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x24++0x3
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line.long 0x0 "TIMER2_CAPNF,Timer2 Capture Input Noise Filter Register"
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bitfld.long 0x0 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is ECLKx,1: Noise filter clock is ECLKx/2,?,?,?,?,?,?"
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bitfld.long 0x0 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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group.long 0x100++0xF
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line.long 0x0 "TIMER3_CTL,Timer3 Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
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bitfld.long 0x0 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
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line.long 0x4 "TIMER3_CMP,Timer3 Comparator Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT field .."
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line.long 0x8 "TIMER3_INTSTS,Timer3 Interrupt Status Register"
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bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
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line.long 0xC "TIMER3_CNT,Timer3 Data Register"
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rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.."
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hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value.."
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rgroup.long 0x110++0x3
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line.long 0x0 "TIMER3_CAP,Timer3 Capture Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the.."
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group.long 0x114++0xB
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line.long 0x0 "TIMER3_EXTCTL,Timer3 External Control Register"
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hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Set INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source."
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bitfld.long 0x0 16.--17. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external TMx..,1: Reserved.,?,?"
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bitfld.long 0x0 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1..,?,?,?,?,?,?"
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bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x0 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source." "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
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line.long 0x4 "TIMER3_EINTSTS,Timer3 External Interrupt Status Register"
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rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clear corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
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bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer.." "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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line.long 0x8 "TIMER3_TRGCTL,Timer3 Trigger Control Register"
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bitfld.long 0x8 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x8 2. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered ADC conversion." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
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bitfld.long 0x8 1. "TRGPWM,Trigger PWM/BPWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM/BPWM counter clock source." "0: Timer interrupt trigger PWM/BPWM Disabled,1: Timer interrupt trigger PWM/BPWM Enabled"
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bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x124++0x3
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line.long 0x0 "TIMER3_CAPNF,Timer3 Capture Input Noise Filter Register"
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bitfld.long 0x0 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is ECLKx,1: Noise filter clock is ECLKx/2,?,?,?,?,?,?"
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bitfld.long 0x0 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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tree.end
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tree.end
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tree "UART (Universal Asynchronous Receiver/Transmitter)"
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base ad:0x0
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tree "UART0"
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base ad:0x40070000
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group.long 0x0++0x57
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line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
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line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
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bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]) Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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line.long 0x8 "UART_FIFO,UART FIFO Control Register"
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
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bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled and an interrupt will be generated)."
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bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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line.long 0xC "UART_LINE,UART Line Control Register"
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bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0 the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
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bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
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line.long 0x10 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
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bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to 錯誤! 找不到參照來源。 and 錯誤! 找不到參照來源。 for UART function mode.\nNote 2: Refer to 錯誤! 找不到參照來源。.." "0: nRTS pin output is high level active,1: Refer to 錯誤! 找不到參照來源。 and.."
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
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line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
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rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
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line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
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rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 8 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
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rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 8 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
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hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 8 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
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rbitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag (Read Only)\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
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rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated."
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF (UART_LINSTS[0]) SLVHEF (UART_LINSTS[1]) SLVIDPEF (UART_LINSTS[2]) SLVHTOF (UART_LINSTS[4]) RTOUTF (UART_LINSTS[5]) BRKDETF (UART_LINSTS[8]) and BITEF (UART_LINSTS[9]) all are.." "0: None of SLVHDETF SLVHEF SLVIDPEF SLVHTOF RTOUTF..,1: At least one of SLVHDETF SLVHEF SLVIDPEF SLVHTOF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when LINWKF (UART_LINWKCTL[29]) TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: This bit can be cleared by writing '1' to it"
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rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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line.long 0x20 "UART_TOUT,UART Time-out Register"
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bitfld.long 0x20 31. "BITOMEN,Bus Idle Time-out Mode Enable Bit\nIf BITOMEN (UART_TOUT[31]) is enabled the reset conditions of the time-out counter and RXTOIF (UART_INTSTS[4]) will be changed to detect the bus idle.\nWhen BITOMEN (UART_TOUT[31]) is disabled the time-out.." "0: Bus idle time-out mode Disabled,1: Bus idle time-out mode Enabled"
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hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
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hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x24 30. "BRFDEN,Baud Rate Fractional Divider Enable Bit\nNote: This bit has effect only at baud rate mode 2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1)." "0: Baud Rate Fractional Divider Disabled,1: Baud Rate Fractional Divider Enabled"
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bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in 錯誤! 找不到參照來源。."
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hexmask.long.byte 0x24 16.--23. 1. "BRFD,Baud Rate Fractional Divider\nThis field is the fractional part of the baud rate divisor. \nWhen BRFDEN (UART_BAUD[30]) is set the Baud Rate Equation goes to UART_CLK / ((BRD+2) + (BRFD/256))."
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hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in 錯誤! 找不到參照來源。."
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line.long 0x28 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
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bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
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line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
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bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote: This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. \nNote:.." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
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line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
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bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
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line.long 0x34 "UART_LINCTL,UART LIN Control Register"
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hexmask.long.byte 0x34 24.--31. 1. "PID,LIN PID Bits\nIf the parity generated by hardware user fill ID0~ID5 (PID[29:24]) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field.\nNote 1: User can fill any 8-bit value to this.."
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bitfld.long 0x34 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?"
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bitfld.long 0x34 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1-bit time,1: The LIN break/sync delimiter length is 2-bit time,?,?"
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hexmask.long.byte 0x34 16.--19. 1. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote 1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]). User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL.."
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bitfld.long 0x34 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled"
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bitfld.long 0x34 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
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bitfld.long 0x34 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
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bitfld.long 0x34 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x34 8. "SENDH,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote 1: This bit is shadow bit of LINTXEN (UART_ALTCTL[7]);.." "0: Send LIN TX header Disabled,1: This bit is shadow bit of LINTXEN"
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bitfld.long 0x34 5. "RTOUTEN,LIN Response Time-out Detection Enable Bit" "0: LIN response time-out detection Disabled,1: LIN response time-out detection Enabled"
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bitfld.long 0x34 4. "MUTE,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 錯誤! 找不到參照來源。 (LIN slave mode)." "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x34 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit\nNote 2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode this bit should be kept cleared) \nNote 3: The control and interactions of this field are.." "0: UART_BAUD updated is written by software (if no..,1: UART_BAUD is updated at the next received.."
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bitfld.long 0x34 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote 2: When operation in Automatic Resynchronization mode the baud rate setting must be mode 2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1).\nNote 3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x34 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x34 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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line.long 0x38 "UART_LINSTS,UART LIN Status Register"
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bitfld.long 0x38 9. "BITEF,Bit Error Detect Status Flag \nAt TX transfer state hardware will monitor the bus state if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state BITEF (UART_LINSTS[9]) will be set." "0: Bit error not detected,1: Bit error detected"
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bitfld.long 0x38 8. "BRKDETF,LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software." "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x38 5. "RTOUTF,LIN Response Time-out Flag\nThis bit is set when no LIN response received and the time-out counter equal to or bigger than LINRTOIC (UART_LINRTOUT[23:0]). If LINIEN (UART_INTEN[8]) is enabled the LIN Bus Interrupt will be generated.\nNote: This.." "0: LIN response time-out not detected,1: LIN response time-out detected"
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bitfld.long 0x38 4. "SLVHTOF,LIN Slave Header Time-out Flag\nThis bit is set by hardware when a LIN header reception time-out is detected in LIN slave mode and be cleared by writing 1 to it. When this bit is set SLVHEF (UART_LINSTS[1]) will also be set." "0: LIN header time-out not detected,1: LIN header time-out detected"
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bitfld.long 0x38 3. "SLVSYNCF,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect user must reset the internal circuit to re-search new frame header by.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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bitfld.long 0x38 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct." "0: No active,1: Receipted frame ID parity is not correct"
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bitfld.long 0x38 1. "SLVHEF,LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)' 'frame error in.." "0: LIN header error not detected,1: LIN header error detected"
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bitfld.long 0x38 0. "SLVHDETF,LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote 3: When enable ID parity check IDPEN (UART_LINCTL[9]) if hardware detect complete header.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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line.long 0x3C "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x3C 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x3C 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8])."
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line.long 0x40 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x40 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
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bitfld.long 0x40 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x40 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x40 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x40 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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line.long 0x44 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x44 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
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bitfld.long 0x44 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x44 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
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bitfld.long 0x44 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x44 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
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line.long 0x48 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x48 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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line.long 0x4C "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
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hexmask.long.word 0x4C 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
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line.long 0x50 "UART_LINRTOUT,UART LIN Response Time-out Register"
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hexmask.long.tbyte 0x50 0.--23. 1. "LINRTOIC,LIN Response Time-out Comparator"
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line.long 0x54 "UART_LINWKCTL,UART LIN Wake-up Control Register"
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bitfld.long 0x54 29. "LINWKF,LIN Wake-up Flag\nThis bit is set if chip wake-up from power-down state by LIN wake-up.\nNote 1: If LINWKEN (UART_LINWKCTL[28]) is enabled the LIN wake-up event will cause this bit set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If LINWKEN"
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bitfld.long 0x54 28. "LINWKEN,LIN Wake-up Enable Bit\nNote: When the system is in Power-down mode LIN wake-up event will wake up system from Power-down mode." "0: LIN wake-up system function Disabled,1: LIN wake-up system function Enabled"
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bitfld.long 0x54 24. "SENDLINW,LIN Send Wake-up Enable Bit\nNote: When this bit is set the UART will send LIN wake-up automatically. When LIN wake-up transfer operation finished this bit will be cleared automatically." "0: Send LIN Wake-up Disabled,1: Send LIN Wake-up Enabled"
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hexmask.long.tbyte 0x54 0.--23. 1. "LINWKC,LIN Send Wake-up Signal Length Counter"
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tree.end
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tree "UART1"
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base ad:0x40071000
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group.long 0x0++0x33
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line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
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line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
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bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]) Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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line.long 0x8 "UART_FIFO,UART FIFO Control Register"
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
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bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled and an interrupt will be generated)."
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bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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line.long 0xC "UART_LINE,UART Line Control Register"
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bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0 the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
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bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
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line.long 0x10 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
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bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to 錯誤! 找不到參照來源。 and 錯誤! 找不到參照來源。 for UART function mode.\nNote 2: Refer to 錯誤! 找不到參照來源。.." "0: nRTS pin output is high level active,1: Refer to 錯誤! 找不到參照來源。 and.."
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
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line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
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rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
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line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
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rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 8 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
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rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 8 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
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hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 8 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
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rbitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag (Read Only)\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
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rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF (UART_LINSTS[0]) SLVHEF (UART_LINSTS[1]) SLVIDPEF (UART_LINSTS[2]) SLVHTOF (UART_LINSTS[4]) RTOUTF (UART_LINSTS[5]) BRKDETF (UART_LINSTS[8]) and BITEF (UART_LINSTS[9]) all are.." "0: None of SLVHDETF SLVHEF SLVIDPEF SLVHTOF RTOUTF..,1: At least one of SLVHDETF SLVHEF SLVIDPEF SLVHTOF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when LINWKF (UART_LINWKCTL[29]) TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: This bit can be cleared by writing '1' to it"
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rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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line.long 0x20 "UART_TOUT,UART Time-out Register"
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bitfld.long 0x20 31. "BITOMEN,Bus Idle Time-out Mode Enable Bit\nIf BITOMEN (UART_TOUT[31]) is enabled the reset conditions of the time-out counter and RXTOIF (UART_INTSTS[4]) will be changed to detect the bus idle.\nWhen BITOMEN (UART_TOUT[31]) is disabled the time-out.." "0: Bus idle time-out mode Disabled,1: Bus idle time-out mode Enabled"
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hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
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hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x24 30. "BRFDEN,Baud Rate Fractional Divider Enable Bit\nNote: This bit has effect only at baud rate mode 2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1)." "0: Baud Rate Fractional Divider Disabled,1: Baud Rate Fractional Divider Enabled"
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bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in 錯誤! 找不到參照來源。."
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hexmask.long.byte 0x24 16.--23. 1. "BRFD,Baud Rate Fractional Divider\nThis field is the fractional part of the baud rate divisor. \nWhen BRFDEN (UART_BAUD[30]) is set the Baud Rate Equation goes to UART_CLK / ((BRD+2) + (BRFD/256))."
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hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in 錯誤! 找不到參照來源。."
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line.long 0x28 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
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bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
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line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
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bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote: This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. \nNote:.." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
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line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
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bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
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group.long 0x3C++0x13
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line.long 0x0 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8])."
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line.long 0x4 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
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bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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line.long 0x8 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
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bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
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bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
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line.long 0xC "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0xC 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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line.long 0x10 "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
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hexmask.long.word 0x10 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
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tree.end
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tree.end
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tree "USCI (Universal Serial Control Interface)"
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base ad:0x0
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tree "UI2C (Inter-Integrated Circuit)"
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tree "UI2C0"
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base ad:0x400D0000
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group.long 0x0++0x3
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line.long 0x0 "UI2C_CTL,USCI Control Register"
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bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
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group.long 0x8++0x3
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line.long 0x0 "UI2C_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.byte 0x0 28.--31. 1. "NFCNT,Noise Filter Count \nThe register bits control the input filter width."
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hexmask.long.word 0x0 16.--25. 1. "CLKDIV,Clock Divider\nNote: The minimum value of DIVIDER is 9 for USCI_I2C."
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hexmask.long.byte 0x0 10.--14. 1. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value."
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bitfld.long 0x0 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
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bitfld.long 0x0 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x0 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled"
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bitfld.long 0x0 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,?,?"
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bitfld.long 0x0 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x0 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
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group.long 0x2C++0x3
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line.long 0x0 "UI2C_LINECTL,USCI Line Control Register"
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hexmask.long.byte 0x0 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI supports word length from 4 to 16 bits."
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bitfld.long 0x0 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x3
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line.long 0x0 "UI2C_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission."
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rgroup.long 0x34++0x3
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line.long 0x0 "UI2C_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol RXDAT[12:8] indicate the different transmission conditions which defined in I2C."
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group.long 0x44++0x23
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line.long 0x0 "UI2C_DEVADDR0,USCI Device Address Register 0"
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hexmask.long.word 0x0 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB the AA bits are compared to the bits DEVADDR [9:8] to check for address match where the X is R/W bit. Then.."
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line.long 0x4 "UI2C_DEVADDR1,USCI Device Address Register 1"
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB the AA bits are compared to the bits DEVADDR [9:8] to check for address match where the X is R/W bit. Then.."
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line.long 0x8 "UI2C_ADDRMSK0,USCI Device Address Mask Register 0"
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hexmask.long.word 0x8 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI supports multiple address recognition with two address mask register. When the bit in the address mask register is set to 1 it means the received corresponding address bit is don't-care. If the bit is set to 0 .."
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line.long 0xC "UI2C_ADDRMSK1,USCI Device Address Mask Register 1"
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hexmask.long.word 0xC 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI supports multiple address recognition with two address mask register. When the bit in the address mask register is set to 1 it means the received corresponding address bit is don't-care. If the bit is set to 0 .."
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line.long 0x10 "UI2C_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x10 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according to START signal,1: The chip is woken up according to address match"
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bitfld.long 0x10 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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line.long 0x14 "UI2C_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x14 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x18 "UI2C_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x18 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol Disabled,1: I2C Protocol Enabled"
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hexmask.long.word 0x18 16.--25. 1. "TOCNT,Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero.."
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bitfld.long 0x18 9. "MONEN,Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the.." "0: The monitor mode Disabled,1: The monitor mode Enabled"
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bitfld.long 0x18 8. "SCLOUTEN,SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt." "0: SCL output will be forced high due to open drain..,1: I2C module may act as a slave peripheral just.."
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bitfld.long 0x18 5. "PTRG,I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags.." "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch is active"
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bitfld.long 0x18 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function Disabled,1: Address match 10 bit function Enabled"
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bitfld.long 0x18 3. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free. This bit will be cleared by hardware automatically." "0,1"
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bitfld.long 0x18 2. "STO,I2C STOP Control" "0,1"
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bitfld.long 0x18 1. "AA,Assert Acknowledge Control" "0,1"
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bitfld.long 0x18 0. "GCFUNC,General Call Function\nNote: When ADDR10EN (UI2C_PROTCTL [4]) is set don't set this bit." "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x1C "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0x1C 6. "ACKIEN,Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master." "0: The acknowledge interrupt Disabled,1: The acknowledge interrupt Enabled"
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bitfld.long 0x1C 5. "ERRIEN,Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERRIF (UI2C_PROTSTS [12]))." "0: The error interrupt Disabled,1: The error interrupt Enabled"
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bitfld.long 0x1C 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected." "0: The arbitration lost interrupt Disabled,1: The arbitration lost interrupt Enabled"
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bitfld.long 0x1C 3. "NACKIEN,Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master." "0: The non-acknowledge interrupt Disabled,1: The non-acknowledge interrupt Enabled"
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bitfld.long 0x1C 2. "STORIEN,STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected." "0: The stop condition interrupt Disabled,1: The stop condition interrupt Enabled"
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bitfld.long 0x1C 1. "STARIEN,START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected." "0: The start condition interrupt Disabled,1: The start condition interrupt Enabled"
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bitfld.long 0x1C 0. "TOIEN,Time-out Interrupt Enable Bit\nIn I2C protocol this bit enables the interrupt generation in case of a time-out event." "0: The time-out interrupt Disabled,1: The time-out interrupt Enabled"
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line.long 0x20 "UI2C_PROTSTS,USCI Protocol Status Register"
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bitfld.long 0x20 19. "ERRARBLO,Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This.." "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.."
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bitfld.long 0x20 18. "BUSHANG,Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL.." "0: The bus is normal status for transmission,1: The bus is hang-up status for transmission"
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bitfld.long 0x20 17. "WRSTSWK,Read/Write Status Bit in Address Wake-up Frame" "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x20 16. "WKAKDONE,Wake-up Address Frame Acknowledge Bit Done\nNote: This bit cannot be released when WKUPIF is set." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.."
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bitfld.long 0x20 15. "SLAREAD,Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: A slave R/W bit is 1 has not been detected,1: A slave R/W bit is 1 has been detected"
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bitfld.long 0x20 14. "SLASEL,Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: The device is not selected as slave,1: The device is selected as slave"
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bitfld.long 0x20 13. "ACKIF,Acknowledge Received Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received"
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bitfld.long 0x20 12. "ERRIF,Error Interrupt Flag\nNote 1: This bit is cleared by software writing 1 into this bit.\nNote 2: This bit is set for slave mode and user must write 1 into STO register to the defined 'not addressed' slave mode." "0: An I2C error has not been detected,1: This bit is cleared by software writing 1 into.."
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bitfld.long 0x20 11. "ARBLOIF,Arbitration Lost Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: An arbitration has not been lost,1: An arbitration has been lost"
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bitfld.long 0x20 10. "NACKIF,Non - Acknowledge Received Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: A non-acknowledge has not been received,1: A non-acknowledge has been received"
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bitfld.long 0x20 9. "STORIF,Stop Condition Received Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: A stop condition has not yet been detected,1: A stop condition has been detected"
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bitfld.long 0x20 8. "STARIF,Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However this bit also indicates that a repeated start condition has been detected on slave.." "0: A start condition has not yet been detected,1: A start condition has been detected"
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bitfld.long 0x20 6. "ONBUSY,On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
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bitfld.long 0x20 5. "TOIF,Time-out Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred"
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group.long 0x8C++0x3
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line.long 0x0 "UI2C_TMCTL,I2C Timing Configure Control Register"
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hexmask.long.word 0x0 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode."
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hexmask.long.word 0x0 0.--8. 1. "STCTL,Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.."
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tree.end
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tree "UI2C1"
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base ad:0x400D1000
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group.long 0x0++0x3
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line.long 0x0 "UI2C_CTL,USCI Control Register"
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bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
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group.long 0x8++0x3
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line.long 0x0 "UI2C_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.byte 0x0 28.--31. 1. "NFCNT,Noise Filter Count \nThe register bits control the input filter width."
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hexmask.long.word 0x0 16.--25. 1. "CLKDIV,Clock Divider\nNote: The minimum value of DIVIDER is 9 for USCI_I2C."
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hexmask.long.byte 0x0 10.--14. 1. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value."
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bitfld.long 0x0 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
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bitfld.long 0x0 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x0 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled"
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bitfld.long 0x0 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,?,?"
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bitfld.long 0x0 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x0 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
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group.long 0x2C++0x3
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line.long 0x0 "UI2C_LINECTL,USCI Line Control Register"
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hexmask.long.byte 0x0 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI supports word length from 4 to 16 bits."
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bitfld.long 0x0 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x3
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line.long 0x0 "UI2C_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission."
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rgroup.long 0x34++0x3
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line.long 0x0 "UI2C_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol RXDAT[12:8] indicate the different transmission conditions which defined in I2C."
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group.long 0x44++0x23
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line.long 0x0 "UI2C_DEVADDR0,USCI Device Address Register 0"
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hexmask.long.word 0x0 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB the AA bits are compared to the bits DEVADDR [9:8] to check for address match where the X is R/W bit. Then.."
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line.long 0x4 "UI2C_DEVADDR1,USCI Device Address Register 1"
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB the AA bits are compared to the bits DEVADDR [9:8] to check for address match where the X is R/W bit. Then.."
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line.long 0x8 "UI2C_ADDRMSK0,USCI Device Address Mask Register 0"
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hexmask.long.word 0x8 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI supports multiple address recognition with two address mask register. When the bit in the address mask register is set to 1 it means the received corresponding address bit is don't-care. If the bit is set to 0 .."
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line.long 0xC "UI2C_ADDRMSK1,USCI Device Address Mask Register 1"
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hexmask.long.word 0xC 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI supports multiple address recognition with two address mask register. When the bit in the address mask register is set to 1 it means the received corresponding address bit is don't-care. If the bit is set to 0 .."
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line.long 0x10 "UI2C_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x10 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according to START signal,1: The chip is woken up according to address match"
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bitfld.long 0x10 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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line.long 0x14 "UI2C_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x14 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x18 "UI2C_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x18 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol Disabled,1: I2C Protocol Enabled"
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hexmask.long.word 0x18 16.--25. 1. "TOCNT,Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero.."
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bitfld.long 0x18 9. "MONEN,Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the.." "0: The monitor mode Disabled,1: The monitor mode Enabled"
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bitfld.long 0x18 8. "SCLOUTEN,SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt." "0: SCL output will be forced high due to open drain..,1: I2C module may act as a slave peripheral just.."
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bitfld.long 0x18 5. "PTRG,I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags.." "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch is active"
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bitfld.long 0x18 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function Disabled,1: Address match 10 bit function Enabled"
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bitfld.long 0x18 3. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free. This bit will be cleared by hardware automatically." "0,1"
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bitfld.long 0x18 2. "STO,I2C STOP Control" "0,1"
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bitfld.long 0x18 1. "AA,Assert Acknowledge Control" "0,1"
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bitfld.long 0x18 0. "GCFUNC,General Call Function\nNote: When ADDR10EN (UI2C_PROTCTL [4]) is set don't set this bit." "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x1C "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0x1C 6. "ACKIEN,Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master." "0: The acknowledge interrupt Disabled,1: The acknowledge interrupt Enabled"
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bitfld.long 0x1C 5. "ERRIEN,Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERRIF (UI2C_PROTSTS [12]))." "0: The error interrupt Disabled,1: The error interrupt Enabled"
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bitfld.long 0x1C 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected." "0: The arbitration lost interrupt Disabled,1: The arbitration lost interrupt Enabled"
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bitfld.long 0x1C 3. "NACKIEN,Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master." "0: The non-acknowledge interrupt Disabled,1: The non-acknowledge interrupt Enabled"
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newline
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bitfld.long 0x1C 2. "STORIEN,STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected." "0: The stop condition interrupt Disabled,1: The stop condition interrupt Enabled"
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bitfld.long 0x1C 1. "STARIEN,START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected." "0: The start condition interrupt Disabled,1: The start condition interrupt Enabled"
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newline
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bitfld.long 0x1C 0. "TOIEN,Time-out Interrupt Enable Bit\nIn I2C protocol this bit enables the interrupt generation in case of a time-out event." "0: The time-out interrupt Disabled,1: The time-out interrupt Enabled"
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line.long 0x20 "UI2C_PROTSTS,USCI Protocol Status Register"
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bitfld.long 0x20 19. "ERRARBLO,Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This.." "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.."
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bitfld.long 0x20 18. "BUSHANG,Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL.." "0: The bus is normal status for transmission,1: The bus is hang-up status for transmission"
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bitfld.long 0x20 17. "WRSTSWK,Read/Write Status Bit in Address Wake-up Frame" "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x20 16. "WKAKDONE,Wake-up Address Frame Acknowledge Bit Done\nNote: This bit cannot be released when WKUPIF is set." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.."
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bitfld.long 0x20 15. "SLAREAD,Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: A slave R/W bit is 1 has not been detected,1: A slave R/W bit is 1 has been detected"
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bitfld.long 0x20 14. "SLASEL,Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: The device is not selected as slave,1: The device is selected as slave"
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bitfld.long 0x20 13. "ACKIF,Acknowledge Received Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received"
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bitfld.long 0x20 12. "ERRIF,Error Interrupt Flag\nNote 1: This bit is cleared by software writing 1 into this bit.\nNote 2: This bit is set for slave mode and user must write 1 into STO register to the defined 'not addressed' slave mode." "0: An I2C error has not been detected,1: This bit is cleared by software writing 1 into.."
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bitfld.long 0x20 11. "ARBLOIF,Arbitration Lost Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: An arbitration has not been lost,1: An arbitration has been lost"
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bitfld.long 0x20 10. "NACKIF,Non - Acknowledge Received Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: A non-acknowledge has not been received,1: A non-acknowledge has been received"
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bitfld.long 0x20 9. "STORIF,Stop Condition Received Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: A stop condition has not yet been detected,1: A stop condition has been detected"
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bitfld.long 0x20 8. "STARIF,Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However this bit also indicates that a repeated start condition has been detected on slave.." "0: A start condition has not yet been detected,1: A start condition has been detected"
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bitfld.long 0x20 6. "ONBUSY,On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
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bitfld.long 0x20 5. "TOIF,Time-out Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred"
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group.long 0x8C++0x3
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line.long 0x0 "UI2C_TMCTL,I2C Timing Configure Control Register"
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hexmask.long.word 0x0 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode."
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hexmask.long.word 0x0 0.--8. 1. "STCTL,Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.."
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tree.end
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tree.end
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tree "USPI (Serial Peripheral Interface)"
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tree "USPI0"
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base ad:0x400D0000
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group.long 0x0++0xB
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line.long 0x0 "USPI_CTL,USCI Control Register"
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bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
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line.long 0x4 "USPI_INTEN,USCI Interrupt Enable Register"
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bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event." "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
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bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event." "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
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bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event." "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
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line.long 0x8 "USPI_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider"
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bitfld.long 0x8 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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newline
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bitfld.long 0x8 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Time measurement counter Disabled,1: Time measurement counter Enabled"
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bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor." "0: fDIV_CLK,1: fPROT_CLK,?,?"
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newline
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bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
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group.long 0x10++0x3
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line.long 0x0 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol it is suggested this bit should be set as 0." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x3
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line.long 0x0 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x7
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line.long 0x0 "USPI_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it is suggested this bit.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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line.long 0x4 "USPI_LINECTL,USCI Line Control Register"
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hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word.."
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bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol the control.." "0: No effect,1: The control signal will be inverted before its.."
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newline
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bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin." "0: Data output level is not inverted,1: Data output level is inverted"
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bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x3
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line.long 0x0 "USPI_TXDAT,USCI Transmit Data Register"
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bitfld.long 0x0 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode"
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hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field."
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rgroup.long 0x34++0x3
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line.long 0x0 "USPI_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer."
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group.long 0x38++0xB
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line.long 0x0 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x0 17. "RXRST,Receive Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the receive-related counters state machine.."
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bitfld.long 0x0 16. "TXRST,Transmit Reset" "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared. Should only be.."
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bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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newline
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bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared. Should only be.."
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bitfld.long 0x0 6. "TXUDRIEN,Slave Transmit Under-run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled"
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line.long 0x4 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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bitfld.long 0x4 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]) the corresponding interrupt request is activated. It is cleared by software writes 1.." "0: A transmit buffer under-run event has not been..,1: A transmit buffer under-run event has been.."
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bitfld.long 0x4 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
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bitfld.long 0x4 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for the.."
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bitfld.long 0x4 3. "RXOVIF,Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software writes 1 to.." "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been detected"
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bitfld.long 0x4 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
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bitfld.long 0x4 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
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line.long 0x8 "USPI_PDMACTL,USCI PDMA Control Register"
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bitfld.long 0x8 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
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bitfld.long 0x8 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x8 1. "TXPDMAEN,PDMA Transmit Channel Available\nNote 1: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable.." "0: Transmit PDMA function Disabled,1: In SPI Master mode with full duplex transfer"
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bitfld.long 0x8 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic. This bit.."
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group.long 0x54++0x13
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line.long 0x0 "USPI_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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line.long 0x4 "USPI_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "USPI_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x8 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled"
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bitfld.long 0x8 28. "TXUDRPOL,Transmit Under-run Data Polarity for Slave Only\nThis bit defines the transmitting data level when no data is available for transferring." "0: The output data level is 0 if TX under run event..,1: The output data level is 1 if TX under run event.."
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hexmask.long.word 0x8 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period for Slave Only\nIn Slave mode this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC USPI_BRGEN[5]) between the two edges of input SCLK will assert the.."
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bitfld.long 0x8 12.--14. "TSMSEL,Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8 8.--11. 1. "SUSPITV,Suspend Interval for Master Only\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of.."
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bitfld.long 0x8 6.--7. "SCLKMODE,Serial Bus Clock Mode\nThis bit field defines the SCLK idle status data transmit and data receive edge." "0: MODE0. The idle state of SPI clock is low level.,1: MODE1. The idle state of SPI clock is low level.,?,?"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable for Master Only" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.."
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bitfld.long 0x8 2. "SS,Slave Select Control for Master Only\nIf AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol the.." "0,1"
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bitfld.long 0x8 1. "SLV3WIRE,Slave 3-wire Mode Selection for Slave Only\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x8 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode"
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line.long 0xC "USPI_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0xC 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH.." "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0xC 2. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nIn SPI protocol this bit enables the interrupt generation in case of a Slave time-out event." "0: Slave time-out interrupt Disabled,1: Slave time-out interrupt Enabled"
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bitfld.long 0xC 1. "SSACTIEN,Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active." "0: Slave select active interrupt generation Disabled,1: Slave select active interrupt generation Enabled"
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bitfld.long 0xC 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive." "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation Enabled"
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line.long 0x10 "USPI_PROTSTS,USCI Protocol Status Register"
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rbitfld.long 0x10 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1. This bit indicates whether the.." "0: Slave transmit under-run event does not occur,1: Slave transmit under-run event occurs"
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rbitfld.long 0x10 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state"
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rbitfld.long 0x10 16. "SSLINE,Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x10 9. "SSACTIF,Slave Select Active Interrupt Flag for Slave Only\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high." "0: The slave select signal has not changed to active,1: The slave select signal has changed to active"
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bitfld.long 0x10 8. "SSINAIF,Slave Select Inactive Interrupt Flag for Slave Only\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high." "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive"
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bitfld.long 0x10 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag for Slave Only\nNote: It is cleared by software write 1 to this bit." "0: Slave bit count error event did not occur,1: Slave bit count error event occurred"
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bitfld.long 0x10 5. "SLVTOIF,Slave Time-out Interrupt Flag for Slave Only\nNote: It is cleared by software write 1 to this bit." "0: Slave time-out event did not occur,1: Slave time-out event occurred"
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bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit." "0: Receive end event did not occur,1: Receive end event occurred"
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bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit." "0: Receive start event did not occur,1: Receive start event occurred"
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bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit." "0: Transmit end event did not occur,1: Transmit end event occurred"
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bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit." "0: Transmit start event did not occur,1: Transmit start event occurred"
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tree.end
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tree "USPI1"
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base ad:0x400D1000
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group.long 0x0++0xB
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line.long 0x0 "USPI_CTL,USCI Control Register"
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bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
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line.long 0x4 "USPI_INTEN,USCI Interrupt Enable Register"
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bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event." "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
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bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event." "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
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bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event." "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
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line.long 0x8 "USPI_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider"
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bitfld.long 0x8 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x8 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Time measurement counter Disabled,1: Time measurement counter Enabled"
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bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor." "0: fDIV_CLK,1: fPROT_CLK,?,?"
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bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
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group.long 0x10++0x3
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line.long 0x0 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol it is suggested this bit should be set as 0." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x3
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line.long 0x0 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x7
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line.long 0x0 "USPI_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it is suggested this bit.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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line.long 0x4 "USPI_LINECTL,USCI Line Control Register"
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hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word.."
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bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol the control.." "0: No effect,1: The control signal will be inverted before its.."
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bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin." "0: Data output level is not inverted,1: Data output level is inverted"
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bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x3
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line.long 0x0 "USPI_TXDAT,USCI Transmit Data Register"
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bitfld.long 0x0 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode"
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hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field."
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rgroup.long 0x34++0x3
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line.long 0x0 "USPI_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer."
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group.long 0x38++0xB
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line.long 0x0 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x0 17. "RXRST,Receive Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the receive-related counters state machine.."
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bitfld.long 0x0 16. "TXRST,Transmit Reset" "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared. Should only be.."
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bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared. Should only be.."
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bitfld.long 0x0 6. "TXUDRIEN,Slave Transmit Under-run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled"
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line.long 0x4 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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bitfld.long 0x4 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]) the corresponding interrupt request is activated. It is cleared by software writes 1.." "0: A transmit buffer under-run event has not been..,1: A transmit buffer under-run event has been.."
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bitfld.long 0x4 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
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bitfld.long 0x4 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for the.."
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bitfld.long 0x4 3. "RXOVIF,Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software writes 1 to.." "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been detected"
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bitfld.long 0x4 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
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bitfld.long 0x4 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
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line.long 0x8 "USPI_PDMACTL,USCI PDMA Control Register"
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bitfld.long 0x8 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
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bitfld.long 0x8 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x8 1. "TXPDMAEN,PDMA Transmit Channel Available\nNote 1: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable.." "0: Transmit PDMA function Disabled,1: In SPI Master mode with full duplex transfer"
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bitfld.long 0x8 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic. This bit.."
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group.long 0x54++0x13
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line.long 0x0 "USPI_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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line.long 0x4 "USPI_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "USPI_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x8 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled"
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bitfld.long 0x8 28. "TXUDRPOL,Transmit Under-run Data Polarity for Slave Only\nThis bit defines the transmitting data level when no data is available for transferring." "0: The output data level is 0 if TX under run event..,1: The output data level is 1 if TX under run event.."
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hexmask.long.word 0x8 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period for Slave Only\nIn Slave mode this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC USPI_BRGEN[5]) between the two edges of input SCLK will assert the.."
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bitfld.long 0x8 12.--14. "TSMSEL,Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8 8.--11. 1. "SUSPITV,Suspend Interval for Master Only\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of.."
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bitfld.long 0x8 6.--7. "SCLKMODE,Serial Bus Clock Mode\nThis bit field defines the SCLK idle status data transmit and data receive edge." "0: MODE0. The idle state of SPI clock is low level.,1: MODE1. The idle state of SPI clock is low level.,?,?"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable for Master Only" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.."
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bitfld.long 0x8 2. "SS,Slave Select Control for Master Only\nIf AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol the.." "0,1"
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bitfld.long 0x8 1. "SLV3WIRE,Slave 3-wire Mode Selection for Slave Only\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x8 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode"
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line.long 0xC "USPI_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0xC 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH.." "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0xC 2. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nIn SPI protocol this bit enables the interrupt generation in case of a Slave time-out event." "0: Slave time-out interrupt Disabled,1: Slave time-out interrupt Enabled"
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bitfld.long 0xC 1. "SSACTIEN,Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active." "0: Slave select active interrupt generation Disabled,1: Slave select active interrupt generation Enabled"
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bitfld.long 0xC 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive." "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation Enabled"
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line.long 0x10 "USPI_PROTSTS,USCI Protocol Status Register"
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rbitfld.long 0x10 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1. This bit indicates whether the.." "0: Slave transmit under-run event does not occur,1: Slave transmit under-run event occurs"
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rbitfld.long 0x10 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state"
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rbitfld.long 0x10 16. "SSLINE,Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x10 9. "SSACTIF,Slave Select Active Interrupt Flag for Slave Only\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high." "0: The slave select signal has not changed to active,1: The slave select signal has changed to active"
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bitfld.long 0x10 8. "SSINAIF,Slave Select Inactive Interrupt Flag for Slave Only\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high." "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive"
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bitfld.long 0x10 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag for Slave Only\nNote: It is cleared by software write 1 to this bit." "0: Slave bit count error event did not occur,1: Slave bit count error event occurred"
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bitfld.long 0x10 5. "SLVTOIF,Slave Time-out Interrupt Flag for Slave Only\nNote: It is cleared by software write 1 to this bit." "0: Slave time-out event did not occur,1: Slave time-out event occurred"
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bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit." "0: Receive end event did not occur,1: Receive end event occurred"
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bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit." "0: Receive start event did not occur,1: Receive start event occurred"
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bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit." "0: Transmit end event did not occur,1: Transmit end event occurred"
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bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit." "0: Transmit start event did not occur,1: Transmit start event occurred"
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tree.end
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tree.end
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tree "UUART (Universal Asynchronous Receiver/Transmitter)"
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tree "UUART0"
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base ad:0x400D0000
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group.long 0x0++0xB
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line.long 0x0 "UUART_CTL,USCI Control Register"
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bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
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line.long 0x4 "UUART_INTEN,USCI Interrupt Enable Register"
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bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event." "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
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bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event." "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
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bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event." "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
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line.long 0x8 "UUART_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and.."
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hexmask.long.byte 0x8 10.--14. 1. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value."
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bitfld.long 0x8 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
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bitfld.long 0x8 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK"
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bitfld.long 0x8 4. "TMCNTEN,Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Timing measurement counter is Disabled,1: Timing measurement counter is Enabled"
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bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK is selected to fDIV_CLK,1: fSAMP_CLK is selected to fPROT_CLK,?,?"
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bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
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group.long 0x10++0x3
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line.long 0x0 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x0 3.--4. "EDGEDET,Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode it is suggested to set this bit field as 0x2." "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,?,?"
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bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x3
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line.long 0x0 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x7
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line.long 0x0 "UUART_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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line.long 0x4 "UUART_LINECTL,USCI Line Control Register"
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hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\nNote: In UART.."
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bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol the control signal means nRTS signal." "0: No effect,1: The control signal will be inverted before its.."
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bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin." "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of data.."
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bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x3
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line.long 0x0 "UUART_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission."
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rgroup.long 0x34++0x3
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line.long 0x0 "UUART_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])."
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group.long 0x38++0x3
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line.long 0x0 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x0 17. "RXRST,Receive Reset\nNote 1: It is cleared automatically after one PCLK cycle.\nNote 2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1." "0: No effect,1: It is cleared automatically after one PCLK cycle"
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bitfld.long 0x0 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared (filling level is.."
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bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared (filling level is.."
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rgroup.long 0x3C++0x3
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line.long 0x0 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
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bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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bitfld.long 0x0 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software.." "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.."
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bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
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bitfld.long 0x0 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
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group.long 0x40++0x3
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line.long 0x0 "UUART_PDMACTL,USCI PDMA Control Register"
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bitfld.long 0x0 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
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bitfld.long 0x0 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x0 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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bitfld.long 0x0 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic. This bit.."
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group.long 0x54++0x13
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line.long 0x0 "UUART_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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line.long 0x4 "UUART_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "UUART_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x8 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled"
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bitfld.long 0x8 30. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x8 29. "BCEN,Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled"
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bitfld.long 0x8 26. "STICKEN,Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information." "0: Stick parity Disabled,1: Stick parity Enabled"
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hexmask.long.word 0x8 16.--24. 1. "BRDETITV,Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN[5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data.."
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hexmask.long.byte 0x8 11.--14. 1. "WAKECNT,Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (START bit) when the device is wake-up from Power-down mode."
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bitfld.long 0x8 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled"
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bitfld.long 0x8 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled"
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bitfld.long 0x8 6. "ABREN,Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN[1]) is enabled)." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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bitfld.long 0x8 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled if the transmitted bytes in the TX buffer is empty the UART asserted nRTS signal automatically.\nNote 1: This bit is used for nRTS auto direction control for RS485.\nNote 2:.." "0: nRTS auto direction control Disabled,1: This bit is used for nRTS auto direction control.."
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bitfld.long 0x8 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x8 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x8 2. "EVENPARITY,Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x8 1. "PARITYEN,Parity Enable Bit\nThis bit defines the PARITY bit is enabled in an UART frame." "0: The PARITY bit Disabled,1: The PARITY bit Enabled"
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bitfld.long 0x8 0. "STOPB,STOP bits\nThis bit defines the number of STOP bits in an UART frame." "0: The number of STOP bits is 1,1: The number of STOP bits is 2"
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line.long 0xC "UUART_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0xC 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt." "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled"
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bitfld.long 0xC 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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line.long 0x10 "UUART_PROTSTS,USCI Protocol Status Register"
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rbitfld.long 0x10 17. "CTSLV,nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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rbitfld.long 0x10 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal." "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high"
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bitfld.long 0x10 11. "ABERRSTS,Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the.." "0: Auto-baud rate detect counter is not overrun,1: This bit is set at the same time of ABRDETIF"
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rbitfld.long 0x10 10. "RXBUSY,RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver." "0: The receiver is Idle,1: The receiver is BUSY"
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bitfld.long 0x10 9. "ABRDETIF,Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set the auto-baud rate interrupt will be generated. This bit can be set 4 times.." "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done"
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bitfld.long 0x10 7. "BREAK,Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP bits).\nNote:.." "0: No Break is generated,1: Break is generated in the receiver bus"
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bitfld.long 0x10 6. "FRMERR,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1'.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x10 5. "PARITYERR,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' among the BREAK FRMERR and PARITYERR bits." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A receive finish interrupt status has not occurred,1: A receive finish interrupt status has occurred"
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bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A receive start interrupt status has not occurred,1: A receive start interrupt status has occurred"
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newline
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bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A transmit end interrupt status has not occurred,1: A transmit end interrupt status has occurred"
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bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer." "0: A transmit start interrupt status has not occurred,1: It is cleared by software writing one into this.."
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tree.end
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tree "UUART1"
|
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base ad:0x400D1000
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group.long 0x0++0xB
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line.long 0x0 "UUART_CTL,USCI Control Register"
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bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
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line.long 0x4 "UUART_INTEN,USCI Interrupt Enable Register"
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bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event." "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
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bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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newline
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bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event." "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
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bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event." "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
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line.long 0x8 "UUART_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and.."
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hexmask.long.byte 0x8 10.--14. 1. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value."
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bitfld.long 0x8 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
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bitfld.long 0x8 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK"
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bitfld.long 0x8 4. "TMCNTEN,Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Timing measurement counter is Disabled,1: Timing measurement counter is Enabled"
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bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK is selected to fDIV_CLK,1: fSAMP_CLK is selected to fPROT_CLK,?,?"
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bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
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group.long 0x10++0x3
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line.long 0x0 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x0 3.--4. "EDGEDET,Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode it is suggested to set this bit field as 0x2." "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,?,?"
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bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x3
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line.long 0x0 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x7
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line.long 0x0 "UUART_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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line.long 0x4 "UUART_LINECTL,USCI Line Control Register"
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hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\nNote: In UART.."
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bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol the control signal means nRTS signal." "0: No effect,1: The control signal will be inverted before its.."
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bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin." "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of data.."
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bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x3
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line.long 0x0 "UUART_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission."
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rgroup.long 0x34++0x3
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line.long 0x0 "UUART_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])."
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group.long 0x38++0x3
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line.long 0x0 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x0 17. "RXRST,Receive Reset\nNote 1: It is cleared automatically after one PCLK cycle.\nNote 2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1." "0: No effect,1: It is cleared automatically after one PCLK cycle"
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bitfld.long 0x0 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared (filling level is.."
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bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared (filling level is.."
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rgroup.long 0x3C++0x3
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line.long 0x0 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
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bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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bitfld.long 0x0 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software.." "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.."
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bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
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bitfld.long 0x0 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
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group.long 0x40++0x3
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line.long 0x0 "UUART_PDMACTL,USCI PDMA Control Register"
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bitfld.long 0x0 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
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bitfld.long 0x0 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x0 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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bitfld.long 0x0 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic. This bit.."
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group.long 0x54++0x13
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line.long 0x0 "UUART_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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line.long 0x4 "UUART_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "UUART_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x8 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled"
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bitfld.long 0x8 30. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x8 29. "BCEN,Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled"
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bitfld.long 0x8 26. "STICKEN,Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information." "0: Stick parity Disabled,1: Stick parity Enabled"
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hexmask.long.word 0x8 16.--24. 1. "BRDETITV,Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN[5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data.."
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hexmask.long.byte 0x8 11.--14. 1. "WAKECNT,Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (START bit) when the device is wake-up from Power-down mode."
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bitfld.long 0x8 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled"
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bitfld.long 0x8 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled"
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bitfld.long 0x8 6. "ABREN,Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN[1]) is enabled)." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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bitfld.long 0x8 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled if the transmitted bytes in the TX buffer is empty the UART asserted nRTS signal automatically.\nNote 1: This bit is used for nRTS auto direction control for RS485.\nNote 2:.." "0: nRTS auto direction control Disabled,1: This bit is used for nRTS auto direction control.."
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bitfld.long 0x8 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x8 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x8 2. "EVENPARITY,Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x8 1. "PARITYEN,Parity Enable Bit\nThis bit defines the PARITY bit is enabled in an UART frame." "0: The PARITY bit Disabled,1: The PARITY bit Enabled"
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bitfld.long 0x8 0. "STOPB,STOP bits\nThis bit defines the number of STOP bits in an UART frame." "0: The number of STOP bits is 1,1: The number of STOP bits is 2"
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line.long 0xC "UUART_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0xC 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt." "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled"
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bitfld.long 0xC 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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line.long 0x10 "UUART_PROTSTS,USCI Protocol Status Register"
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rbitfld.long 0x10 17. "CTSLV,nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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rbitfld.long 0x10 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal." "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high"
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bitfld.long 0x10 11. "ABERRSTS,Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the.." "0: Auto-baud rate detect counter is not overrun,1: This bit is set at the same time of ABRDETIF"
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rbitfld.long 0x10 10. "RXBUSY,RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver." "0: The receiver is Idle,1: The receiver is BUSY"
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bitfld.long 0x10 9. "ABRDETIF,Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set the auto-baud rate interrupt will be generated. This bit can be set 4 times.." "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done"
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bitfld.long 0x10 7. "BREAK,Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP bits).\nNote:.." "0: No Break is generated,1: Break is generated in the receiver bus"
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bitfld.long 0x10 6. "FRMERR,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1'.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x10 5. "PARITYERR,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' among the BREAK FRMERR and PARITYERR bits." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A receive finish interrupt status has not occurred,1: A receive finish interrupt status has occurred"
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bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A receive start interrupt status has not occurred,1: A receive start interrupt status has occurred"
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bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A transmit end interrupt status has not occurred,1: A transmit end interrupt status has occurred"
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bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer." "0: A transmit start interrupt status has not occurred,1: It is cleared by software writing one into this.."
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tree.end
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tree.end
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tree.end
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tree "WDT (Watchdog Timer)"
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base ad:0x40040000
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group.long 0x0++0x7
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line.long 0x0 "WDT_CTL,WDT Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement affects WDT..,1: ICE debug mode acknowledgement Disabled"
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rbitfld.long 0x0 30. "SYNC,WDT Enable Control SYNC Flag Indicator (Read Only)\nIf user executes enable/disable WDTEN (WDT_CTL[7]) this flag can be indicated enable/disable WDTEN function is completed or not.\nNote: Performing enable or disable WDTEN bit needs 4 * WDT_CLK.." "0: Setting WDTEN bit is completed and WDT is ready,1: Setting WDTEN bit is synchronizing and not.."
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bitfld.long 0x0 29. "PDRSTCNT,Reset Counter When Entering Power Down Enable Bit" "0: WDT up counter will keep going no matter CPU..,1: Reset WDT up counter value to 0 when entering.."
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hexmask.long.byte 0x0 8.--11. 1. "TOUTSEL,WDT Time-out Interval Selection (Write Protect)\nThese four bits select the time-out interval period for the WDT.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register."
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bitfld.long 0x0 7. "WDTEN,WDT Enable Bit (Write Protect)\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111 this bit is forced as 1 and user cannot change.." "0: WDT Disabled (This action will reset the..,1: This bit is write protected"
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bitfld.long 0x0 6. "INTEN,WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
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bitfld.long 0x0 5. "WKF,WDT Time-out Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of WDT\nNote: This bit is cleared by writing 1 to it." "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if WDT.."
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bitfld.long 0x0 4. "WKEN,WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1 while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled the WDT time-out interrupt signal will.." "0: Wake-up trigger event Disabled if WDT time-out..,1: This bit is write protected"
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bitfld.long 0x0 3. "IF,WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to it." "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred"
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bitfld.long 0x0 2. "RSTF,WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it." "0: WDT time-out reset did not occur,1: WDT time-out reset occurred"
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bitfld.long 0x0 1. "RSTEN,WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected." "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled"
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line.long 0x4 "WDT_ALTCTL,WDT Alternative Control Register"
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bitfld.long 0x4 0.--1. "RSTDSEL,WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened user has a time named WDT Reset Delay Period to clear WDT counter by programming 0x5AA5 to prevent WDT time-out reset happened. User can select a suitable setting of RSTDSEL.." "0: WDT Reset Delay Period is 1026 * WDT_CLK,1: This bit is write protected,2: This register will be reset to 0 if WDT time-out..,?"
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wgroup.long 0x8++0x3
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line.long 0x0 "WDT_RSTCNT,WDT Reset Counter Register"
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hexmask.long 0x0 0.--31. 1. "RSTCNT,WDT Reset Counter Register\nWriting 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0.\nNote: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active."
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tree.end
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tree "WWDT (Window Watchdog Timer)"
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base ad:0x40096000
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wgroup.long 0x0++0x3
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line.long 0x0 "WWDT_RLDCNT,WWDT Reload Counter Register"
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hexmask.long 0x0 0.--31. 1. "RLDCNT,WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.."
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group.long 0x4++0x7
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line.long 0x0 "WWDT_CTL,WWDT Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit\nNote: WWDT down counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled"
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hexmask.long.byte 0x0 16.--21. 1. "CMPDAT,WWDT Window Compare\nSet this register to adjust the valid reload window. \nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If user writes WWDT_RLDCNT register when.."
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hexmask.long.byte 0x0 8.--11. 1. "PSCSEL,WWDT Counter Prescale Period Selection"
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bitfld.long 0x0 1. "INTEN,WWDT Interrupt Enable Bit\nIf this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU." "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled"
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bitfld.long 0x0 0. "WWDTEN,WWDT Enable Bit" "0: WWDT counter is stopped,1: WWDT counter starts counting"
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line.long 0x4 "WWDT_STATUS,WWDT Status Register"
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bitfld.long 0x4 1. "WWDTRF,WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it." "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred"
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bitfld.long 0x4 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: WWDT counter value matches CMPDAT"
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rgroup.long 0xC++0x3
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line.long 0x0 "WWDT_CNT,WWDT Counter Value Register"
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hexmask.long.byte 0x0 0.--5. 1. "CNTDAT,WWDT Counter Value\nCNTDAT will be updated continuously to monitor 6-bit WWDT down counter value."
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tree.end
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AUTOINDENT.OFF
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