2116 lines
122 KiB
Plaintext
2116 lines
122 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: CMS32L On-Chip Peripherals
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; @Props: Released
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; @Author: KRZ
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; @Changelog: 2025-02-03 KRZ
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; @Manufacturer: CMSEMICON - China Micro Semicon Co., Ltd.
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; @Doc: Generated (TRACE32, build: 176489.), based on:
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; CMS32L051.svd (Ver. 1.2)
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; @Core: Cortex-M0+
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; @Chip: CMS32L051LQ32, CMS32L051LQ48, CMS32L051QN20, CMS32L051QN24,
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; CMS32L051QN32, CMS32L051QN40, CMS32L051SS24, CMS32L051TS20
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; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; ARM Limited (ARM) is supplying this software for use with Cortex-M\n
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; processor based microcontroller, but can be equally used for other\n
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; suitable processor architectures. This file can be freely distributed.\n
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; Modifications to this file shall be clearly marked.\n
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; \n
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; THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
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; OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
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; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
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; ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
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; CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; --------------------------------------------------------------------------------
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; $Id: percms32l.per 19100 2025-02-24 14:34:34Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M0+)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC21=Cortex-M1"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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elif (CORENAME()=="CORTEXM0+")
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC60=Cortex-M0+"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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else
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC20=Cortex-M0"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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endif
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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|
textline " "
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textline " "
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|
endif
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|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
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group.long 0xD9C++0x03 "Region 2"
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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|
textline " "
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|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (A/D Converter)"
|
|
base ad:0x40045000
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "ADM0,A/D mode register 0"
|
|
bitfld.byte 0x0 7. "ADCS,A/D conversion operation control" "0,1"
|
|
bitfld.byte 0x0 3.--5. "FR,A/D conversion clock (fAD) select" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x0 0. "ADCE,A/D enable" "0,1"
|
|
group.byte 0x2++0x0
|
|
line.byte 0x0 "ADM1,A/D mode register 1"
|
|
bitfld.byte 0x0 7. "ADMD,A/D conversion channel select mode" "0: Select mode,1: Scan mode"
|
|
bitfld.byte 0x0 3. "ADSCM,A/D conversion mode" "0: Sequential conversion mode,1: One-shot conversion mode"
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "ADM2,A/D mode register 2"
|
|
bitfld.byte 0x0 6.--7. "ADREFP,Selection of the + side reference voltage of A/D converter" "0: Supplied from inside AVREF of A/D,?,?,?"
|
|
bitfld.byte 0x0 3. "ADRCK,the upper limit and lower limit conversion result values" "0,1"
|
|
bitfld.byte 0x0 1. "CHRDE,output CH number in A/D conversion result in Scan mode" "0,1"
|
|
group.byte 0x6++0x0
|
|
line.byte 0x0 "ADTRG,A/D mode register 2"
|
|
bitfld.byte 0x0 6.--7. "ADTMD,A/D conversion trigger mode" "0,1,2,3"
|
|
bitfld.byte 0x0 0.--1. "ADTRS,A/D hard trigger select" "0,1,2,3"
|
|
group.byte 0x8++0x0
|
|
line.byte 0x0 "ADS,Analog input channel specification register"
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "ADCR,12-bit A/D conversion result register"
|
|
group.byte 0xF++0x0
|
|
line.byte 0x0 "ADCRH,Higher 8-bit A/D conversion result register"
|
|
group.byte 0xB++0x0
|
|
line.byte 0x0 "ADUL,Conversion result comparison upper limit setting register"
|
|
group.byte 0xA++0x0
|
|
line.byte 0x0 "ADLL,Conversion result comparison lower limit setting register"
|
|
group.byte 0x15++0x0
|
|
line.byte 0x0 "ADSMPWAIT,A/D sampling wait control register"
|
|
tree.end
|
|
tree "BGR (Temperature Sensor)"
|
|
base ad:0x500660
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "VBG85,The A/D conversion value of VBGR at 85 degrees and 3.0V reference voltage"
|
|
line.long 0x4 "VBG25,The A/D conversion value of VBGR at 25 degrees and 3.0V reference voltage"
|
|
tree.end
|
|
tree "CGC (Clock Generation Circuit)"
|
|
base ad:0x40020400
|
|
group.byte 0x0++0x1
|
|
line.byte 0x0 "CMC,Clock operaton Mode Control Register"
|
|
bitfld.byte 0x0 7. "EXCLK,External Clock input mode" "0,1"
|
|
bitfld.byte 0x0 6. "OSCSEL,Main OSC Select" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "EXCLKS,External Clock input mode" "0,1"
|
|
bitfld.byte 0x0 4. "OSCSELS,Sub OSC Select" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1.--2. "AMPHS,Control of XT1 clock oscillation frequency" "0,1,2,3"
|
|
bitfld.byte 0x0 0. "AMPH,Control of X1 clock oscillation frequency" "0,1"
|
|
line.byte 0x1 "CSC,Clock operation Status Register"
|
|
bitfld.byte 0x1 7. "MSTOP,High-speed system clock operation control" "0: X1 oscillator operating or External clock from..,1: X1 oscillator stop or External clock from EXCLK.."
|
|
bitfld.byte 0x1 6. "XTSTOP,Subsystem clock operation control" "0: XT1 oscillator operating or External clock from..,1: XT1 oscillator stop or External clock from.."
|
|
newline
|
|
bitfld.byte 0x1 0. "HIOSTOP,High-speed on-chip oscillator clock operation control" "0: High-speed on-chip oscillator operating,1: High-speed on-chip oscillator stopped"
|
|
rgroup.byte 0x2++0x0
|
|
line.byte 0x0 "OSTC,Oscillation stabilization time counter status"
|
|
group.byte 0x3++0x1
|
|
line.byte 0x0 "OSTS,Oscillation stabilization time select register"
|
|
line.byte 0x1 "CKC,System clock control register"
|
|
rbitfld.byte 0x1 7. "CLS,Status of CPU/peripheral hardware clock (fCLK)" "0: Main system clock (fMAIN),1: Subsystem clock (fSUB)"
|
|
bitfld.byte 0x1 6. "CSS,Selection of CPU/peripheral hardware clock (fCLK)" "0: Main system clock (fMAIN),1: Subsystem clock (fSUB)"
|
|
newline
|
|
rbitfld.byte 0x1 5. "MCS,Status of Main system clock (fMAIN)" "0: High-speed on-chip oscillator clock (fIH),1: High-speed system clock (fMX)"
|
|
bitfld.byte 0x1 4. "MCM0,Main system clock (fMAIN) operation control" "0: Select the high-speed on-chip oscillator clock..,1: Select the high-speed system clock (fMX) as the.."
|
|
group.byte 0x20++0x0
|
|
line.byte 0x0 "PER0,Peripheral enable register 0"
|
|
bitfld.byte 0x0 7. "RTCEN,Control of the RTC input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 6. "IRDAEN,Control of the IRDA input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 5. "ADCEN,Control of the ADC input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 4. "IICA0EN,Control of the IICA0 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 3. "SCI1EN,Control of the SCI1 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 2. "SCI0EN,Control of the SCI0 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 1. "TM41EN,Control of the TM41 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 0. "TM40EN,Control of the TM40 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
group.byte 0x41A++0x0
|
|
line.byte 0x0 "PER1,Peripheral enable register 1"
|
|
bitfld.byte 0x0 7. "SPIEN,Control of the SPI input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 5. "PGACMPEN,Control of the PGACMP input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 3. "DMAEN,Control of the DMA input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 2. "EPWMEN,Control of the EPWM input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
group.byte 0x23++0x0
|
|
line.byte 0x0 "OSMC,Subsystem clock supply mode control register"
|
|
bitfld.byte 0x0 7. "RTCLPC,Setting in DEEPSLEEP mode or SLEEP mode while subsystem clock is selected as CPU clock" "0: Enables supply of subsystem clock to peripheral..,1: Stops supply of subsystem clock to peripheral.."
|
|
bitfld.byte 0x0 4. "WUTMMCK0,Selection of operation clock for real-time clock 15-bit interval timer" "0: The subsystem clock is selected as the..,1: The low-speed on-chip oscillator clock is.."
|
|
group.byte 0x5++0x2
|
|
line.byte 0x0 "LOSCSEL,LOCO Frequency Select register"
|
|
bitfld.byte 0x0 0. "LOSCSEL,LOCO Frequency Select" "0: LOCO's Frequency is 15K,1: LOCO's Frequency is 30K"
|
|
line.byte 0x1 "PRCR,LOSCSEL's Protect register"
|
|
line.byte 0x2 "SUBCKSEL,SubSystem Clock select register"
|
|
bitfld.byte 0x2 0. "SELLOSC,Select LOSC or SUBOSC" "0: Select SUBOSC as the SubSystem clock,1: Select LOSC as the SubSystem clock"
|
|
group.byte 0x1820++0x0
|
|
line.byte 0x0 "HOCODIV,High-speed on-chip oscillator frequency select register"
|
|
group.byte 0x1800++0x0
|
|
line.byte 0x0 "HIOTRM,High-speed on-chip oscillator trimming register"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "PMUKEY,Power Manager Key Register"
|
|
group.byte 0xA++0x0
|
|
line.byte 0x0 "PMUCTL,Power Manager Control Register"
|
|
group.byte 0xC++0x3
|
|
line.byte 0x0 "WDTCFG0,WDT Configeration 0 register"
|
|
line.byte 0x1 "WDTCFG1,WDT Configeration 1 register"
|
|
line.byte 0x2 "WDTCFG2,WDT Configeration 2 register"
|
|
line.byte 0x3 "WDTCFG3,WDT Configeration 3 register"
|
|
group.byte 0x2000++0x0
|
|
line.byte 0x0 "HOCOFC,High-speed on-chip oscillator frequency correction register"
|
|
bitfld.byte 0x0 7. "FCMD,High-speed on-chip oscillator frequency correction operation mode register" "0,1"
|
|
bitfld.byte 0x0 6. "FCIE,Oscillator stop detected operation selection register" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "FCST,Oscillator stop detected object selection register" "0,1"
|
|
tree.end
|
|
tree "CRC (General Purpose Cyclic Redundancy Check)"
|
|
base ad:0x400432F0
|
|
group.word 0xA++0x1
|
|
line.word 0x0 "CRCD,CRC data register"
|
|
group.byte 0xBC++0x0
|
|
line.byte 0x0 "CRCIN,CRC input register"
|
|
tree.end
|
|
tree "DBG (Debug Controller)"
|
|
base ad:0x4001B000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "DBGSTR,Debug status register"
|
|
bitfld.long 0x0 29. "CDBGPWRUPACK,DBG Power Up Acknowledgement" "0,1"
|
|
bitfld.long 0x0 28. "CDBGPWRUPREQ,DBG Power Up Request" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "DBGSTOPCR,Debug Stop Control register"
|
|
bitfld.long 0x0 24. "SWDIS,SWD Disable" "0,1"
|
|
bitfld.long 0x0 16. "RPERMSK,Mask RAM parity error in debug mode" "0,1"
|
|
bitfld.long 0x0 2. "RESMSK,Mask internal reset in debug mode" "0,1"
|
|
bitfld.long 0x0 1. "FRZEN1,Stop Communation family macros when cpu halted" "0,1"
|
|
bitfld.long 0x0 0. "FRZEN0,Stop Timer family macros when cpu halted" "0,1"
|
|
tree.end
|
|
tree "DMA (Enhanced DMA Controller)"
|
|
base ad:0x40005000
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "DMAEN$1,DMA activation enable register %s"
|
|
repeat.end
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "DMABAR,DMA base address register"
|
|
line.long 0x4 "IFPRCR,DMA Trigger Protect register"
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x10)++0x0
|
|
line.byte 0x0 "DMAIF$1,DMA Trigger enable register %s"
|
|
repeat.end
|
|
tree.end
|
|
tree "DMAVEC (DMA Vector and Control Data Area)"
|
|
base ad:0x20000000
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "VEC[$1],DMA vector area"
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x20000020 ad:0x20000030 ad:0x20000040 ad:0x20000050 ad:0x20000060 ad:0x20000070 ad:0x20000080 ad:0x20000090 ad:0x200000A0 ad:0x200000B0 ad:0x200000C0 ad:0x200000D0 ad:0x200000E0 ad:0x200000F0 ad:0x20000100 ad:0x20000110)
|
|
tree "CTRL[$1]"
|
|
base $2
|
|
group.word ($2)++0x7
|
|
line.word 0x0 "DMACR,DMA Control register"
|
|
bitfld.word 0x0 6.--7. "SZ,Transfer Data size selection" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.word 0x0 5. "RPTINT,Enabling/disabling repeat mode interrupts" "0: Interrupt generation disabled,1: Interrupt generation enabled"
|
|
bitfld.word 0x0 4. "CHNE,Enabling/disabling chain transfers" "0: Chain transfers disabled,1: Chain transfers enabled"
|
|
bitfld.word 0x0 3. "DAMOD,Destination address control" "0: Fixed,1: Incremented"
|
|
newline
|
|
bitfld.word 0x0 2. "SAMOD,Source address control" "0: Fixed,1: Incremented"
|
|
bitfld.word 0x0 1. "RPTSEL,Repeat area selection" "0: Transfer destination is the repeat area,1: Transfer source is the repeat area"
|
|
bitfld.word 0x0 0. "MODE,Transfer mode selection" "0: Normal mode,1: Repeat mode"
|
|
line.word 0x2 "DMBLS,DMA Block Size register"
|
|
line.word 0x4 "DMACT,DMA Transfer Count register"
|
|
line.word 0x6 "DMRLD,DMA Transfer Count Reload register"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "DMSAR,DMA Source Address register"
|
|
line.long 0x4 "DMDAR,DMA Destination Address register"
|
|
tree.end
|
|
repeat.end
|
|
repeat 8. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17)(list ad:0x20000120 ad:0x20000130 ad:0x20000140 ad:0x20000150 ad:0x20000160 ad:0x20000170 ad:0x20000180 ad:0x20000190)
|
|
tree "CTRL[$1]"
|
|
base $2
|
|
group.word ($2)++0x7
|
|
line.word 0x0 "DMACR,DMA Control register"
|
|
bitfld.word 0x0 6.--7. "SZ,Transfer Data size selection" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.word 0x0 5. "RPTINT,Enabling/disabling repeat mode interrupts" "0: Interrupt generation disabled,1: Interrupt generation enabled"
|
|
bitfld.word 0x0 4. "CHNE,Enabling/disabling chain transfers" "0: Chain transfers disabled,1: Chain transfers enabled"
|
|
bitfld.word 0x0 3. "DAMOD,Destination address control" "0: Fixed,1: Incremented"
|
|
newline
|
|
bitfld.word 0x0 2. "SAMOD,Source address control" "0: Fixed,1: Incremented"
|
|
bitfld.word 0x0 1. "RPTSEL,Repeat area selection" "0: Transfer destination is the repeat area,1: Transfer source is the repeat area"
|
|
bitfld.word 0x0 0. "MODE,Transfer mode selection" "0: Normal mode,1: Repeat mode"
|
|
line.word 0x2 "DMBLS,DMA Block Size register"
|
|
line.word 0x4 "DMACT,DMA Transfer Count register"
|
|
line.word 0x6 "DMRLD,DMA Transfer Count Reload register"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "DMSAR,DMA Source Address register"
|
|
line.long 0x4 "DMDAR,DMA Destination Address register"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "ELC (Event Link Controller)"
|
|
base ad:0x40043400
|
|
group.byte 0x0++0xE
|
|
line.byte 0x0 "ELSELR00,Event output destination select register 00"
|
|
line.byte 0x1 "ELSELR01,Event output destination select register 01"
|
|
line.byte 0x2 "ELSELR02,Event output destination select register 02"
|
|
line.byte 0x3 "ELSELR03,Event output destination select register 03"
|
|
line.byte 0x4 "ELSELR04,Event output destination select register 04"
|
|
line.byte 0x5 "ELSELR05,Event output destination select register 05"
|
|
line.byte 0x6 "ELSELR06,Event output destination select register 06"
|
|
line.byte 0x7 "ELSELR07,Event output destination select register 07"
|
|
line.byte 0x8 "ELSELR08,Event output destination select register 08"
|
|
line.byte 0x9 "ELSELR09,Event output destination select register 09"
|
|
line.byte 0xA "ELSELR10,Event output destination select register 10"
|
|
line.byte 0xB "ELSELR11,Event output destination select register 11"
|
|
line.byte 0xC "ELSELR12,Event output destination select register 12"
|
|
line.byte 0xD "ELSELR13,Event output destination select register 13"
|
|
line.byte 0xE "ELSELR14,Event output destination select register 14"
|
|
tree.end
|
|
tree "EPWM (Enhanced PWM Controller)"
|
|
base ad:0x40044400
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "EPWMSRC,Input source select register"
|
|
bitfld.word 0x0 0. "SRC0%s,Selsect the source clock of EPWM0%s" "0,1"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "EPWMCTL,EPWMO0n output control register"
|
|
bitfld.word 0x0 8. "IE0%s,EPWM0%s output inverted enable register" "0,1"
|
|
bitfld.word 0x0 0. "OE0%s,EPWM0%s output enable register" "0,1"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "EPWMSTL,EPWMO0n cutoff output level register"
|
|
bitfld.word 0x0 14. "IO7%s,EPWM07 output enable register" "0,1"
|
|
bitfld.word 0x0 12. "IO6%s,EPWM06 output enable register" "0,1"
|
|
bitfld.word 0x0 10. "IO5%s,EPWM05 output enable register" "0,1"
|
|
bitfld.word 0x0 8. "IO4%s,EPWM04 output enable register" "0,1"
|
|
bitfld.word 0x0 6. "IO3%s,EPWM03 output enable register" "0,1"
|
|
bitfld.word 0x0 4. "IO2%s,EPWM02 output enable register" "0,1"
|
|
bitfld.word 0x0 2. "IO1%s,EPWM01 output enable register" "0,1"
|
|
bitfld.word 0x0 0. "IO0%s,EPWM00 output enable register" "0,1"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "EPWMSTC,EPWMO0n cutoff control register"
|
|
bitfld.word 0x0 4. "REL_SEL,Cutoff release timing select register" "0,1"
|
|
bitfld.word 0x0 3. "HS_SEL,Output forced cutoff release mode selection" "0,1"
|
|
bitfld.word 0x0 2. "IN_EG,Output forced cutoff source edge/output forced cutoff release edge selection" "0,1"
|
|
bitfld.word 0x0 0. "SC_SEL%s,Cutoff source selection" "0,1"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "EPWMSTR,Status register"
|
|
bitfld.word 0x0 1. "SHTFLG,cutoff status register" "0,1"
|
|
bitfld.word 0x0 0. "HZCLR,software release cutoff register" "0,1"
|
|
tree.end
|
|
tree "FMC (Flash Memory Controller)"
|
|
base ad:0x40020000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "FLSTS,Flash status register"
|
|
bitfld.long 0x0 2. "EVF,Flash hardware verification error flag" "0,1"
|
|
bitfld.long 0x0 0. "OVF,Flash erase or write operaiton finish" "0,1"
|
|
line.long 0x4 "FLOPMD1,Flash operation mode register 1"
|
|
line.long 0x8 "FLOPMD2,Flash operation mode register 2"
|
|
line.long 0xC "FLERMD,Flash erase mode register"
|
|
line.long 0x10 "FLCERCNT,Flash chip erase control register"
|
|
line.long 0x14 "FLSERCNT,Flash sector erase control register"
|
|
line.long 0x18 "FLNVSCNT,Flash address setup time (Tnvs) control register"
|
|
line.long 0x1C "FLPROCNT,Flash program control register"
|
|
line.long 0x20 "FLPROT,Flash protect control register"
|
|
group.long 0x38++0x7
|
|
line.long 0x0 "FLPRVCNT,Flash program recovery time (Trcv) control register"
|
|
line.long 0x4 "FLERVCNT,Flash erase recovery time (Trcv) control register"
|
|
tree.end
|
|
tree "IICA (Standard Serial Interface)"
|
|
base ad:0x40041A30
|
|
group.byte 0x0++0x4
|
|
line.byte 0x0 "IICCTL00,IICA control register 0"
|
|
bitfld.byte 0x0 7. "IICE,I2C operation enable" "0,1"
|
|
bitfld.byte 0x0 6. "LREL,Exit from communications" "0,1"
|
|
bitfld.byte 0x0 5. "WREL,Wait cancellation" "0,1"
|
|
bitfld.byte 0x0 4. "SPIE,Enable generation of interrupt request when stop condition is detected" "0,1"
|
|
bitfld.byte 0x0 3. "WTIM,Control of wait and interrupt request generation" "0,1"
|
|
bitfld.byte 0x0 2. "ACKE,Acknowledgment control" "0,1"
|
|
bitfld.byte 0x0 1. "STT,Start condition trigger" "0,1"
|
|
bitfld.byte 0x0 0. "SPT,Stop condition trigger" "0,1"
|
|
line.byte 0x1 "IICCTL01,IICA control register 0"
|
|
bitfld.byte 0x1 7. "WUP,Control of address match wakeup" "0,1"
|
|
rbitfld.byte 0x1 5. "CLD,Detection of SCLAn pin level (valid only when IICEn = 1)" "0,1"
|
|
rbitfld.byte 0x1 4. "DAD,Detection of SDAAn pin level (valid only when IICEn = 1)" "0,1"
|
|
bitfld.byte 0x1 3. "SMC,Operation mode switching" "0,1"
|
|
bitfld.byte 0x1 2. "DFC,Digital filter operation control" "0,1"
|
|
bitfld.byte 0x1 0. "PRS,Operation clock (fMCK) contro" "0,1"
|
|
line.byte 0x2 "IICWL0,IICA low-level width setting register 0"
|
|
line.byte 0x3 "IICWH0,IICA high-level width setting register 0"
|
|
line.byte 0x4 "SVA0,Slave address register 0"
|
|
group.byte 0x120++0x0
|
|
line.byte 0x0 "IICA0,IICA shift register 0"
|
|
rgroup.byte 0x121++0x0
|
|
line.byte 0x0 "IICS0,IICA status register 0"
|
|
bitfld.byte 0x0 7. "MSTS,Master status check flag" "0,1"
|
|
bitfld.byte 0x0 6. "ALD,Detection of arbitration loss" "0,1"
|
|
bitfld.byte 0x0 5. "EXC,Detection of extension code reception" "0,1"
|
|
bitfld.byte 0x0 4. "COI,Detection of matching addresses" "0,1"
|
|
bitfld.byte 0x0 3. "TRC,Detection of transmit/receive status" "0,1"
|
|
bitfld.byte 0x0 2. "ACKD,Detection of acknowledge (ACK)" "0,1"
|
|
bitfld.byte 0x0 1. "STD,Detection of start condition" "0,1"
|
|
bitfld.byte 0x0 0. "SPD,Detection of stop condition" "0,1"
|
|
group.byte 0x122++0x0
|
|
line.byte 0x0 "IICF0,IICA flag register 0"
|
|
rbitfld.byte 0x0 7. "STCF,STT clear flag" "0,1"
|
|
rbitfld.byte 0x0 6. "IICBSY,I2C bus status flag" "0,1"
|
|
bitfld.byte 0x0 1. "STCEN,Initial start enable trigger" "0,1"
|
|
bitfld.byte 0x0 0. "IICRSV,Communication reservation function disable bit" "0,1"
|
|
tree.end
|
|
tree "INT (Interrupt Controller)"
|
|
base ad:0x40006000
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40006000 ad:0x40006004 ad:0x40006008 ad:0x4000600C ad:0x40006010 ad:0x40006014 ad:0x40006018 ad:0x4000601C ad:0x40006020 ad:0x40006024 ad:0x40006028 ad:0x4000602C ad:0x40006030 ad:0x40006034 ad:0x40006038 ad:0x4000603C)
|
|
tree "IF[$1]"
|
|
base $2
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "IFL,Interrupt flag register"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40006040 ad:0x40006044 ad:0x40006048 ad:0x4000604C ad:0x40006050 ad:0x40006054 ad:0x40006058 ad:0x4000605C ad:0x40006060 ad:0x40006064 ad:0x40006068 ad:0x4000606C ad:0x40006070 ad:0x40006074 ad:0x40006078 ad:0x4000607C)
|
|
tree "IF[$1]"
|
|
base $2
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "IFL,Interrupt flag register"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40006100 ad:0x40006104 ad:0x40006108 ad:0x4000610C ad:0x40006110 ad:0x40006114 ad:0x40006118 ad:0x4000611C ad:0x40006120 ad:0x40006124 ad:0x40006128 ad:0x4000612C ad:0x40006130 ad:0x40006134 ad:0x40006138 ad:0x4000613C)
|
|
tree "MK[$1]"
|
|
base $2
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "MKL,Interrupt mask register"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40006140 ad:0x40006144 ad:0x40006148 ad:0x4000614C ad:0x40006150 ad:0x40006154 ad:0x40006158 ad:0x4000615C ad:0x40006160 ad:0x40006164 ad:0x40006168 ad:0x4000616C ad:0x40006170 ad:0x40006174 ad:0x40006178 ad:0x4000617C)
|
|
tree "MK[$1]"
|
|
base $2
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "MKL,Interrupt mask register"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "INTM"
|
|
base ad:0x40045B38
|
|
group.byte 0x0++0x1
|
|
line.byte 0x0 "EGP0,External interrupt rising edge enable register"
|
|
bitfld.byte 0x0 3. "EGP3" "0,1"
|
|
bitfld.byte 0x0 2. "EGP2" "0,1"
|
|
bitfld.byte 0x0 1. "EGP1" "0,1"
|
|
bitfld.byte 0x0 0. "EGP0" "0,1"
|
|
line.byte 0x1 "EGN0,External interrupt falling edge enable register"
|
|
bitfld.byte 0x1 3. "EGN3" "0,1"
|
|
bitfld.byte 0x1 2. "EGN2" "0,1"
|
|
bitfld.byte 0x1 1. "EGN1" "0,1"
|
|
bitfld.byte 0x1 0. "EGN0" "0,1"
|
|
tree.end
|
|
tree "IRDA (Infrared Data Association)"
|
|
base ad:0x400440A0
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "IRCR,IrDA control register"
|
|
bitfld.long 0x0 7. "IRE,IrRxD enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "IRCKS,IrRxD clock selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "IRTXINV,IrRxD data polarity switching" "0,1"
|
|
bitfld.long 0x0 2. "IRRXINV,IrRxD data polarity switching" "0,1"
|
|
tree.end
|
|
tree "KEY (Key Interrupt)"
|
|
base ad:0x40044B30
|
|
group.byte 0x7++0x0
|
|
line.byte 0x0 "KRM,Key return mode register"
|
|
tree.end
|
|
tree "LVD (Voltage Detection Circuit)"
|
|
base ad:0x40020440
|
|
rgroup.byte 0x1++0x0
|
|
line.byte 0x0 "LVIM,Voltage detection register"
|
|
bitfld.byte 0x0 7. "LVISEN,Enable rewritting LVIS register" "0: Disabling of rewriting the LVIS register,1: Enabling of rewriting the LVIS register"
|
|
bitfld.byte 0x0 1. "LVIOMSK,Mask status flag of LVD output" "0: Mask of LVD output is invalid,1: Mask of LVD output is valid"
|
|
newline
|
|
bitfld.byte 0x0 0. "LVIF,Voltage detection flag" "0: Supply voltage (VDD) greater or equal to..,1: Supply voltage (VDD) less than detection voltage.."
|
|
group.byte 0x2++0x0
|
|
line.byte 0x0 "LVIS,Voltage detection level register"
|
|
bitfld.byte 0x0 7. "LVIMD,Operation mode of voltage detection" "0: interrupt mode,1: reset mode"
|
|
bitfld.byte 0x0 0. "LVILV,LVD detection level" "0: High-voltage detection level (VLVDH),1: Low-voltage detection level (VLVDL or VLVD)"
|
|
tree.end
|
|
tree "MISC (Miscellaneous Functions)"
|
|
base ad:0x40040470
|
|
group.byte 0x0++0x5
|
|
line.byte 0x0 "NFEN0,Noise filter enable register 0"
|
|
bitfld.byte 0x0 4. "SNFEN20,Enable noise filter of RxD2" "0,1"
|
|
bitfld.byte 0x0 2. "SNFEN10,Enable noise filter of RxD1" "0,1"
|
|
bitfld.byte 0x0 0. "SNFEN00,Enable noise filter of RxD0" "0,1"
|
|
line.byte 0x1 "NFEN1,Noise filter enable register 1"
|
|
bitfld.byte 0x1 3. "TNFEN03,Enable noise filter of TI03" "0,1"
|
|
bitfld.byte 0x1 2. "TNFEN02,Enable noise filter of TI02" "0,1"
|
|
bitfld.byte 0x1 1. "TNFEN01,Enable noise filter of TI01" "0,1"
|
|
bitfld.byte 0x1 0. "TNFEN00,Enable noise filter of TI00" "0,1"
|
|
line.byte 0x2 "NFEN2,Noise filter enable register 2"
|
|
bitfld.byte 0x2 3. "TNFEN13,Enable noise filter of TI13" "0,1"
|
|
bitfld.byte 0x2 2. "TNFEN12,Enable noise filter of TI12" "0,1"
|
|
bitfld.byte 0x2 1. "TNFEN11,Enable noise filter of TI11" "0,1"
|
|
bitfld.byte 0x2 0. "TNFEN10,Enable noise filter of TI10" "0,1"
|
|
line.byte 0x3 "ISC,Input switch control register"
|
|
bitfld.byte 0x3 7. "SSIE00,The slave select input (SS00) of SPI00 is valid" "0: The slave select input (SS00) pin is invalid,1: The slave select input (SS00) pin is valid"
|
|
line.byte 0x4 "TIOS0,Timer I/O select register 0"
|
|
line.byte 0x5 "TIOS1,Timer I/O select register 1"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "RTCCL,Real-time clock select register"
|
|
tree.end
|
|
tree "PCBZ (Clock Output/Buzzer Output Controller)"
|
|
base ad:0x40040FA0
|
|
group.byte 0x5++0x1
|
|
line.byte 0x0 "CKS0,Clock output select registers 0"
|
|
bitfld.byte 0x0 7. "PCLOE,PCLBUZn pin output enable" "0,1"
|
|
bitfld.byte 0x0 3. "CSEL,PCLBUZn output clock select" "0,1"
|
|
bitfld.byte 0x0 0.--2. "CCS,PCLBUZn output clock select" "0,1,2,3,4,5,6,7"
|
|
line.byte 0x1 "CKS1,Clock output select registers 1"
|
|
bitfld.byte 0x1 7. "PCLOE,PCLBUZn pin output enable" "0,1"
|
|
bitfld.byte 0x1 3. "CSEL,PCLBUZn output clock select" "0,1"
|
|
bitfld.byte 0x1 0.--2. "CCS,PCLBUZn output clock select" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "PORT (Pin-Port Function)"
|
|
base ad:0x40040000
|
|
group.byte 0x20++0x7
|
|
line.byte 0x0 "PM0,Port mode register 0"
|
|
line.byte 0x1 "PM1,Port mode register 1"
|
|
line.byte 0x2 "PM2,Port mode register 2"
|
|
line.byte 0x3 "PM3,Port mode register 3"
|
|
line.byte 0x4 "PM4,Port mode register 4"
|
|
line.byte 0x5 "PM5,Port mode register 5"
|
|
line.byte 0x6 "PM6,Port mode register 6"
|
|
line.byte 0x7 "PM7,Port mode register 7"
|
|
group.byte 0x2C++0x2
|
|
line.byte 0x0 "PM12,Port mode register 12"
|
|
line.byte 0x1 "PM13,Port mode register 13"
|
|
line.byte 0x2 "PM14,Port mode register 14"
|
|
group.byte 0x0++0x7
|
|
line.byte 0x0 "P0,Port register 0"
|
|
line.byte 0x1 "P1,Port register 1"
|
|
line.byte 0x2 "P2,Port register 2"
|
|
line.byte 0x3 "P3,Port register 3"
|
|
line.byte 0x4 "P4,Port register 4"
|
|
line.byte 0x5 "P5,Port register 5"
|
|
line.byte 0x6 "P6,Port register 6"
|
|
line.byte 0x7 "P7,Port register 7"
|
|
group.byte 0xC++0x2
|
|
line.byte 0x0 "P12,Port register 12"
|
|
line.byte 0x1 "P13,Port register 13"
|
|
line.byte 0x2 "P14,Port register 14"
|
|
group.byte 0x30++0x7
|
|
line.byte 0x0 "PU0,Pull-up resistor option register 0"
|
|
line.byte 0x1 "PU1,Pull-up resistor option register 1"
|
|
line.byte 0x2 "PU2,Pull-up resistor option register 2"
|
|
line.byte 0x3 "PU3,Pull-up resistor option register 3"
|
|
line.byte 0x4 "PU4,Pull-up resistor option register 4"
|
|
line.byte 0x5 "PU5,Pull-up resistor option register 5"
|
|
line.byte 0x6 "PU6,Pull-up resistor option register 6"
|
|
line.byte 0x7 "PU7,Pull-up resistor option register 7"
|
|
group.byte 0x3C++0x2
|
|
line.byte 0x0 "PU12,Pull-up resistor option register 12"
|
|
line.byte 0x1 "PU13,Pull-up resistor option register 13"
|
|
line.byte 0x2 "PU14,Pull-up resistor option register 14"
|
|
group.byte 0x40++0x3
|
|
line.byte 0x0 "PD0,Pull-down resistor option register 0"
|
|
line.byte 0x1 "PD1,Pull-down resistor option register 1"
|
|
line.byte 0x2 "PD2,Pull-down resistor option register 2"
|
|
line.byte 0x3 "PD3,Pull-down resistor option register 3"
|
|
group.byte 0x45++0x2
|
|
line.byte 0x0 "PD5,Pull-down resistor option register 5"
|
|
line.byte 0x1 "PD6,Pull-down resistor option register 6"
|
|
line.byte 0x2 "PD7,Pull-down resistor option register 7"
|
|
group.byte 0x4C++0x2
|
|
line.byte 0x0 "PD12,Pull-down resistor option register 12"
|
|
line.byte 0x1 "PD13,Pull-down resistor option register 13"
|
|
line.byte 0x2 "PD14,Pull-down resistor option register 14"
|
|
group.byte 0x50++0x7
|
|
line.byte 0x0 "POM0,Port output mode register 0"
|
|
line.byte 0x1 "POM1,Port output mode register 1"
|
|
line.byte 0x2 "POM2,Port output mode register 2"
|
|
line.byte 0x3 "POM3,Port output mode register 3"
|
|
line.byte 0x4 "POM4,Port output mode register 4"
|
|
line.byte 0x5 "POM5,Port output mode register 5"
|
|
line.byte 0x6 "POM6,Port output mode register 6"
|
|
line.byte 0x7 "POM7,Port output mode register 7"
|
|
group.byte 0x5C++0x2
|
|
line.byte 0x0 "POM12,Port output mode register 12"
|
|
line.byte 0x1 "POM13,Port output mode register 13"
|
|
line.byte 0x2 "POM14,Port output mode register 14"
|
|
group.byte 0x60++0x3
|
|
line.byte 0x0 "PMC0,Port mode control register 0"
|
|
line.byte 0x1 "PMC1,Port mode control register 1"
|
|
line.byte 0x2 "PMC2,Port mode control register 2"
|
|
line.byte 0x3 "PMC3,Port mode control register 3"
|
|
group.byte 0x65++0x2
|
|
line.byte 0x0 "PMC5,Port mode control register 5"
|
|
line.byte 0x1 "PMC6,Port mode control register 6"
|
|
line.byte 0x2 "PMC7,Port mode control register 7"
|
|
group.byte 0x6C++0x2
|
|
line.byte 0x0 "PMC12,Port mode control register 12"
|
|
line.byte 0x1 "PMC13,Port mode control register 13"
|
|
line.byte 0x2 "PMC14,Port mode control register 14"
|
|
group.byte 0x10++0x7
|
|
line.byte 0x0 "PSET0,Port set register 0"
|
|
line.byte 0x1 "PSET1,Port set register 1"
|
|
line.byte 0x2 "PSET2,Port set register 2"
|
|
line.byte 0x3 "PSET3,Port set register 3"
|
|
line.byte 0x4 "PSET4,Port set register 4"
|
|
line.byte 0x5 "PSET5,Port set register 5"
|
|
line.byte 0x6 "PSET6,Port set register 6"
|
|
line.byte 0x7 "PSET7,Port set register 7"
|
|
group.byte 0x1C++0x2
|
|
line.byte 0x0 "PSET12,Port set register 12"
|
|
line.byte 0x1 "PSET13,Port set register 13"
|
|
line.byte 0x2 "PSET14,Port set register 14"
|
|
group.byte 0x70++0x7
|
|
line.byte 0x0 "PCLR0,Port clear register 0"
|
|
line.byte 0x1 "PCLR1,Port clear register 1"
|
|
line.byte 0x2 "PCLR2,Port clear register 2"
|
|
line.byte 0x3 "PCLR3,Port clear register 3"
|
|
line.byte 0x4 "PCLR4,Port clear register 4"
|
|
line.byte 0x5 "PCLR5,Port clear register 5"
|
|
line.byte 0x6 "PCLR6,Port clear register 6"
|
|
line.byte 0x7 "PCLR7,Port clear register 7"
|
|
group.byte 0x7C++0x2
|
|
line.byte 0x0 "PCLR12,Port clear register 12"
|
|
line.byte 0x1 "PCLR13,Port clear register 13"
|
|
line.byte 0x2 "PCLR14,Port clear register 14"
|
|
group.byte 0x800++0x1
|
|
line.byte 0x0 "P00CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x0 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x1 "P01CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x1 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
group.byte 0x808++0x11
|
|
line.byte 0x0 "P10CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x0 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x1 "P11CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x1 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x2 "P12CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x2 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x3 "P13CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x3 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x4 "P14CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x4 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x5 "P15CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x5 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x6 "P16CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x6 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x7 "P17CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x7 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x8 "P20CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x8 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x9 "P21CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x9 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xA "P22CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xA 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xB "P23CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xB 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xC "P24CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xC 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xD "P25CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xD 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xE "P26CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xE 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xF "P27CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xF 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x10 "P30CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x10 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x11 "P31CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x11 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
group.byte 0x820++0x1
|
|
line.byte 0x0 "P40CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x0 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x1 "P41CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x1 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
group.byte 0x828++0x1
|
|
line.byte 0x0 "P50CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x0 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x1 "P51CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x1 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
group.byte 0x830++0x3
|
|
line.byte 0x0 "P60CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x0 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x1 "P61CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x1 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x2 "P62CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x2 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x3 "P63CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x3 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
group.byte 0x838++0x5
|
|
line.byte 0x0 "P70CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x0 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x1 "P71CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x1 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x2 "P72CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x2 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x3 "P73CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x3 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x4 "P74CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x4 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x5 "P75CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x5 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
group.byte 0x840++0x4
|
|
line.byte 0x0 "P120CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x0 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x1 "P121CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x1 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x2 "P122CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x2 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x3 "P123CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x3 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x4 "P124CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x4 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
group.byte 0x848++0x0
|
|
line.byte 0x0 "P130CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x0 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
group.byte 0x84E++0x2
|
|
line.byte 0x0 "P136CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x0 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x1 "P137CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x1 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x2 "P140CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x2 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
group.byte 0x856++0x1
|
|
line.byte 0x0 "P146CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x0 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x1 "P147CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x1 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
group.byte 0x860++0x8
|
|
line.byte 0x0 "TI10PCFG,TI10 alternate function pin configuration register"
|
|
hexmask.byte 0x0 0.--5. 1. "CFG"
|
|
line.byte 0x1 "TI11PCFG,TI11 alternate function pin configuration register"
|
|
hexmask.byte 0x1 0.--5. 1. "CFG"
|
|
line.byte 0x2 "TI12PCFG,TI12 alternate function pin configuration register"
|
|
hexmask.byte 0x2 0.--5. 1. "CFG"
|
|
line.byte 0x3 "TI13PCFG,TI13 alternate function pin configuration register"
|
|
hexmask.byte 0x3 0.--5. 1. "CFG"
|
|
line.byte 0x4 "INTP0PCFG,INTP0 alternate function pin configuration register"
|
|
hexmask.byte 0x4 0.--5. 1. "CFG"
|
|
line.byte 0x5 "INTP1PCFG,INTP1 alternate function pin configuration register"
|
|
hexmask.byte 0x5 0.--5. 1. "CFG"
|
|
line.byte 0x6 "INTP2PCFG,INTP2 alternate function pin configuration register"
|
|
hexmask.byte 0x6 0.--5. 1. "CFG"
|
|
line.byte 0x7 "INTP3PCFG,INTP3 alternate function pin configuration register"
|
|
hexmask.byte 0x7 0.--5. 1. "CFG"
|
|
line.byte 0x8 "SDI00PCFG,SDI00/RXD0/SDA00 alternate function pin configuration register"
|
|
hexmask.byte 0x8 0.--5. 1. "CFG"
|
|
group.long 0x868++0x3
|
|
line.long 0x0 "SDA00PCFG,SDI00/RXD0/SDA00 alternate function pin configuration register"
|
|
group.long 0x868++0x3
|
|
line.long 0x0 "RXD0PCFG,SDI00/RXD0/SDA00 alternate function pin configuration register"
|
|
group.byte 0x869++0x2
|
|
line.byte 0x0 "SCLKI00PCFG,SCLKI00 alternate function pin configuration register"
|
|
hexmask.byte 0x0 0.--5. 1. "CFG"
|
|
line.byte 0x1 "SS00PCFG,SS00 alternate function pin configuration register"
|
|
hexmask.byte 0x1 0.--5. 1. "CFG"
|
|
line.byte 0x2 "SDI20PCFG,SDI20/RXD2/IrRXD alternate function pin configuration register"
|
|
hexmask.byte 0x2 0.--5. 1. "CFG"
|
|
group.byte 0x86B++0x0
|
|
line.byte 0x0 "IRRXDPCFG,SDI20/RXD2/IrRXD alternate function pin configuration register"
|
|
group.byte 0x86B++0x1
|
|
line.byte 0x0 "RXD2PCFG,SDI20/RXD2/IrRXD alternate function pin configuration register"
|
|
line.byte 0x1 "SCLKI20PCFG,SCLKI20 alternate function pin configuration register"
|
|
hexmask.byte 0x1 0.--5. 1. "CFG"
|
|
group.byte 0x86F++0x0
|
|
line.byte 0x0 "RXD1PCFG,RXD1 alternate function pin configuration register"
|
|
hexmask.byte 0x0 0.--5. 1. "CFG"
|
|
group.byte 0x86F++0x0
|
|
line.byte 0x0 "SDA10PCFG,SDA10 alternate function pin configuration register"
|
|
group.byte 0x86F++0x0
|
|
line.byte 0x0 "SDI10PCFG,SDI10 alternate function pin configuration register"
|
|
group.byte 0x86D++0x1
|
|
line.byte 0x0 "SDAA0PCFG,SDAA0 alternate function pin configuration register"
|
|
hexmask.byte 0x0 0.--5. 1. "CFG"
|
|
line.byte 0x1 "SCLA0PCFG,SCLA0 alternate function pin configuration register"
|
|
hexmask.byte 0x1 0.--5. 1. "CFG"
|
|
group.byte 0x87B++0x0
|
|
line.byte 0x0 "PMS,Port mode select register"
|
|
group.byte 0x87E++0x0
|
|
line.byte 0x0 "SPIPCFG,SPI alternate function pins configuration register"
|
|
tree.end
|
|
tree "RST (Reset Function)"
|
|
base ad:0x40020420
|
|
rgroup.byte 0x20++0x0
|
|
line.byte 0x0 "RESF,Reset flag register"
|
|
bitfld.byte 0x0 7. "SYSRF,Internal reset request by system reset request(AIRCR.SYSRESETREQ)" "0: Internal reset request is not generated or the..,1: Internal reset request is generated."
|
|
bitfld.byte 0x0 4. "WDTRF,Internal reset request by watchdog timer(WDT)" "0: Internal reset request is not generated or the..,1: Internal reset request is generated."
|
|
newline
|
|
bitfld.byte 0x0 2. "RPERF,Internal reset request by RAM parity" "0: Internal reset request is not generated or the..,1: Internal reset request is generated."
|
|
bitfld.byte 0x0 1. "IAWRF,Internal reset request by illegal-memory access" "0: Internal reset request is not generated or the..,1: Internal reset request is generated."
|
|
newline
|
|
bitfld.byte 0x0 0. "LVIRF,Internal reset request by voltage detector" "0: Internal reset request is not generated or the..,1: Internal reset request is generated."
|
|
tree.end
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x40044F00
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "SUBCUD,Watch error correction register"
|
|
bitfld.word 0x0 15. "DEV,watch error correction timing" "0,1"
|
|
hexmask.word 0x0 0.--12. 1. "F,watch error correction value"
|
|
group.word 0x50++0x1
|
|
line.word 0x0 "ITMC,15-bit interval timer control register"
|
|
bitfld.word 0x0 15. "RINTE,15-bit interval timer operation control" "0,1"
|
|
hexmask.word 0x0 0.--14. 1. "ITCMP,15-bit interval timer compare value"
|
|
group.byte 0x52++0x6
|
|
line.byte 0x0 "SEC,Second count register"
|
|
line.byte 0x1 "MIN,Minute count register"
|
|
line.byte 0x2 "HOUR,Hour count register"
|
|
line.byte 0x3 "WEEK,Week count register"
|
|
line.byte 0x4 "DAY,Day count register"
|
|
line.byte 0x5 "MONTH,Month count register"
|
|
line.byte 0x6 "YEAR,Year count register"
|
|
group.byte 0x5A++0x4
|
|
line.byte 0x0 "ALARMWM,Alarm minute register"
|
|
line.byte 0x1 "ALARMWH,Alarm hour register"
|
|
line.byte 0x2 "ALARMWW,Alarm week register"
|
|
line.byte 0x3 "RTCC0,Real-time clock control register 0"
|
|
bitfld.byte 0x3 7. "RTCE,Real-time clock operation control" "0,1"
|
|
bitfld.byte 0x3 5. "RCLOE,RTC1HZ pin output enable" "0,1"
|
|
bitfld.byte 0x3 3. "AMPM,Selection of 12-/24-hour system" "0,1"
|
|
bitfld.byte 0x3 0.--2. "CT,Constant-period interrupt (INTRTC) selection" "0,1,2,3,4,5,6,7"
|
|
line.byte 0x4 "RTCC1,Real-time clock control register 1"
|
|
bitfld.byte 0x4 7. "WALE,Alarm operation control" "0,1"
|
|
bitfld.byte 0x4 6. "WALIE,Control of alarm interrupt (INTRTC) function operation" "0,1"
|
|
bitfld.byte 0x4 4. "WAFG,Alarm detection status flag" "0,1"
|
|
bitfld.byte 0x4 3. "RIFG,Constant-period interrupt status flag" "0,1"
|
|
bitfld.byte 0x4 1. "RWST,Wait status flag of real-time clock" "0,1"
|
|
bitfld.byte 0x4 0. "RWAIT,Wait control of real-time clock" "0,1"
|
|
tree.end
|
|
tree "SAF (High-Speed Cyclic Redundancy Check)"
|
|
base ad:0x40020100
|
|
group.byte 0x1710++0x0
|
|
line.byte 0x0 "CRC0CTL,Flash memory CRC control register"
|
|
bitfld.byte 0x0 7. "CRC0EN,Control of high-speed CRC operation" "0,1"
|
|
hexmask.byte 0x0 0.--6. 1. "FEA,High-speed CRC operation range"
|
|
group.word 0x1712++0x1
|
|
line.word 0x0 "PGCRCL,Flash memory CRC operation result register"
|
|
group.byte 0x232AC++0x0
|
|
line.byte 0x0 "CRCIN,CRC input register"
|
|
group.word 0x231FA++0x1
|
|
line.word 0x0 "CRCD,CRC data register"
|
|
group.byte 0x325++0x0
|
|
line.byte 0x0 "RPECTL,RAM parity error control register"
|
|
bitfld.byte 0x0 7. "RPERDIS,Disable RAM parity error reset" "0: Enable parity error reset,1: Disable parity error reset"
|
|
bitfld.byte 0x0 0. "RPEF,Parity error status flag" "0: No parity error has occurred,1: Parity error has occurred"
|
|
group.long 0x20378++0x3
|
|
line.long 0x0 "SFRGD,SFR guard control register"
|
|
tree.end
|
|
tree "SCI (Serial Communication Interface)"
|
|
base ad:0x0
|
|
rgroup.word 0x0++0x7
|
|
line.word 0x0 "SSR00,Serial status register mn"
|
|
bitfld.word 0x0 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
line.word 0x2 "SSR01,Serial status register mn"
|
|
bitfld.word 0x2 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
line.word 0x4 "SSR02,Serial status register mn"
|
|
bitfld.word 0x4 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x4 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x4 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x4 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x4 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
line.word 0x6 "SSR03,Serial status register mn"
|
|
bitfld.word 0x6 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x6 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x6 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x6 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x6 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
group.word 0x8++0x17
|
|
line.word 0x0 "SIR00,Serial flag clear trigger register mn"
|
|
bitfld.word 0x0 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x2 "SIR01,Serial flag clear trigger register mn"
|
|
bitfld.word 0x2 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x4 "SIR02,Serial flag clear trigger register mn"
|
|
bitfld.word 0x4 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x4 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x4 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x6 "SIR03,Serial flag clear trigger register mn"
|
|
bitfld.word 0x6 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x6 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x6 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x8 "SMR00,Serial mode register mn"
|
|
bitfld.word 0x8 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0x8 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x8 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0x8 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
hexmask.word.byte 0x8 0.--3. 1. "MD,Setting of operation mode of channel n"
|
|
line.word 0xA "SMR01,Serial mode register mn"
|
|
bitfld.word 0xA 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0xA 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0xA 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0xA 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
hexmask.word.byte 0xA 0.--3. 1. "MD,Setting of operation mode of channel n"
|
|
line.word 0xC "SMR02,Serial mode register mn"
|
|
bitfld.word 0xC 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0xC 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0xC 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0xC 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
hexmask.word.byte 0xC 0.--3. 1. "MD,Setting of operation mode of channel n"
|
|
line.word 0xE "SMR03,Serial mode register mn"
|
|
bitfld.word 0xE 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0xE 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0xE 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0xE 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
hexmask.word.byte 0xE 0.--3. 1. "MD,Setting of operation mode of channel n"
|
|
line.word 0x10 "SCR00,Serial communication operation setting register mn"
|
|
bitfld.word 0x10 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x10 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x10 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x10 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x10 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x10 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x10 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x10 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x10 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
line.word 0x12 "SCR01,Serial communication operation setting register mn"
|
|
bitfld.word 0x12 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x12 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x12 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x12 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x12 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x12 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x12 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x12 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x12 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
line.word 0x14 "SCR02,Serial communication operation setting register mn"
|
|
bitfld.word 0x14 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x14 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x14 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x14 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x14 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x14 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x14 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x14 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x14 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
line.word 0x16 "SCR03,Serial communication operation setting register mn"
|
|
bitfld.word 0x16 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x16 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x16 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x16 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x16 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x16 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x16 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x16 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x16 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
rgroup.word 0x20++0x1
|
|
line.word 0x0 "SE0,Serial channel enable status register m"
|
|
bitfld.word 0x0 3. "SE03,Indication of operation enable/stop status of channel 3" "0,1"
|
|
bitfld.word 0x0 2. "SE02,Indication of operation enable/stop status of channel 2" "0,1"
|
|
bitfld.word 0x0 1. "SE01,Indication of operation enable/stop status of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SE00,Indication of operation enable/stop status of channel 0" "0,1"
|
|
group.word 0x22++0x9
|
|
line.word 0x0 "SS0,Serial channel start register 0"
|
|
bitfld.word 0x0 3. "SS03,Operation start trigger of channel 3" "0,1"
|
|
bitfld.word 0x0 2. "SS02,Operation start trigger of channel 2" "0,1"
|
|
bitfld.word 0x0 1. "SS01,Operation start trigger of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SS00,Operation start trigger of channel 0" "0,1"
|
|
line.word 0x2 "ST0,Serial channel stop register 0"
|
|
bitfld.word 0x2 3. "ST03,Operation stop trigger of channel 3" "0,1"
|
|
bitfld.word 0x2 2. "ST02,Operation stop trigger of channel 2" "0,1"
|
|
bitfld.word 0x2 1. "ST01,Operation stop trigger of channel 1" "0,1"
|
|
bitfld.word 0x2 0. "ST00,Operation stop trigger of channel 0" "0,1"
|
|
line.word 0x4 "SPS0,Serial clock select register 0"
|
|
hexmask.word.byte 0x4 4.--7. 1. "PRS01,Prescaler 1"
|
|
hexmask.word.byte 0x4 0.--3. 1. "PRS00,Prescaler 0"
|
|
line.word 0x6 "SO0,Serial output register 0"
|
|
bitfld.word 0x6 11. "CKO03,Serial clock output of channel 3" "0,1"
|
|
bitfld.word 0x6 10. "CKO02,Serial clock output of channel 2" "0,1"
|
|
bitfld.word 0x6 9. "CKO01,Serial clock output of channel 1" "0,1"
|
|
bitfld.word 0x6 8. "CKO00,Serial clock output of channel 0" "0,1"
|
|
bitfld.word 0x6 3. "SO03,Serial data output of channel 3" "0,1"
|
|
bitfld.word 0x6 2. "SO02,Serial data output of channel 2" "0,1"
|
|
bitfld.word 0x6 1. "SO01,Serial data output of channel 1" "0,1"
|
|
bitfld.word 0x6 0. "SO00,Serial data output of channel 0" "0,1"
|
|
line.word 0x8 "SOE0,Serial output enable register 0"
|
|
bitfld.word 0x8 3. "SOE03,Serial output enable of channel 3" "0,1"
|
|
bitfld.word 0x8 2. "SOE02,Serial output enable of channel 2" "0,1"
|
|
bitfld.word 0x8 1. "SOE01,Serial output enable of channel 1" "0,1"
|
|
bitfld.word 0x8 0. "SOE00,Serial output enable of channel 0" "0,1"
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "SOL0,Serial output level register 0"
|
|
bitfld.word 0x0 2. "SOL02,Selects inversion of the level of the transmit data of channel n in UART mode" "0,1"
|
|
bitfld.word 0x0 0. "SOL00,Selects inversion of the level of the transmit data of channel n in UART mode" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x210)++0x1
|
|
line.word 0x0 "SDR0$1,Serial data register 0%s"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x244)++0x1
|
|
line.word 0x0 "SDR0$1,Serial data register 0%s"
|
|
repeat.end
|
|
group.byte 0x210++0x0
|
|
line.byte 0x0 "SIO00,SPI data register"
|
|
group.byte 0x212++0x0
|
|
line.byte 0x0 "SIO01,SPI data register"
|
|
group.byte 0x244++0x0
|
|
line.byte 0x0 "SIO10,SPI data register"
|
|
group.byte 0x246++0x0
|
|
line.byte 0x0 "SIO11,SPI data register"
|
|
group.byte 0x210++0x0
|
|
line.byte 0x0 "TXD0,UART transmit data register"
|
|
group.byte 0x212++0x0
|
|
line.byte 0x0 "RXD0,UART receive data register"
|
|
group.byte 0x244++0x0
|
|
line.byte 0x0 "TXD1,UART transmit data register"
|
|
group.byte 0x246++0x0
|
|
line.byte 0x0 "RXD1,UART receive data register"
|
|
rgroup.word 0x0++0x3
|
|
line.word 0x0 "SSR10,Serial status register mn"
|
|
bitfld.word 0x0 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
line.word 0x2 "SSR11,Serial status register mn"
|
|
bitfld.word 0x2 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
group.word 0x8++0x3
|
|
line.word 0x0 "SIR10,Serial flag clear trigger register mn"
|
|
bitfld.word 0x0 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x2 "SIR11,Serial flag clear trigger register mn"
|
|
bitfld.word 0x2 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "SMR10,Serial mode register mn"
|
|
bitfld.word 0x0 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0x0 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x0 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0x0 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "MD,Setting of operation mode of channel n"
|
|
line.word 0x2 "SMR11,Serial mode register mn"
|
|
bitfld.word 0x2 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0x2 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x2 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0x2 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
hexmask.word.byte 0x2 0.--3. 1. "MD,Setting of operation mode of channel n"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "SCR10,Serial communication operation setting register mn"
|
|
bitfld.word 0x0 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x0 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x0 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x0 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x0 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x0 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x0 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x0 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
line.word 0x2 "SCR11,Serial communication operation setting register mn"
|
|
bitfld.word 0x2 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x2 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x2 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x2 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x2 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x2 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x2 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x2 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
rgroup.word 0x20++0x1
|
|
line.word 0x0 "SE1,Serial channel enable status register 1"
|
|
bitfld.word 0x0 1. "SE11,Indication of operation enable/stop status of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SE10,Indication of operation enable/stop status of channel 0" "0,1"
|
|
group.word 0x22++0x9
|
|
line.word 0x0 "SS1,Serial channel start register 1"
|
|
bitfld.word 0x0 1. "SS11,Operation start trigger of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SS10,Operation start trigger of channel 0" "0,1"
|
|
line.word 0x2 "ST1,Serial channel stop register 1"
|
|
bitfld.word 0x2 1. "ST11,Operation stop trigger of channel 1" "0,1"
|
|
bitfld.word 0x2 0. "ST10,Operation stop trigger of channel 0" "0,1"
|
|
line.word 0x4 "SPS1,Serial clock select register 1"
|
|
hexmask.word.byte 0x4 4.--7. 1. "PRS11,Prescaler 1"
|
|
hexmask.word.byte 0x4 0.--3. 1. "PRS10,Prescaler 0"
|
|
line.word 0x6 "SO1,Serial output register 1"
|
|
bitfld.word 0x6 9. "CKO11,Serial clock output of channel 1" "0,1"
|
|
bitfld.word 0x6 8. "CKO10,Serial clock output of channel 0" "0,1"
|
|
bitfld.word 0x6 1. "SO11,Serial data output of channel 1" "0,1"
|
|
bitfld.word 0x6 0. "SO10,Serial data output of channel 0" "0,1"
|
|
line.word 0x8 "SOE1,Serial output enable register 1"
|
|
bitfld.word 0x8 1. "SOE11,Serial output enable of channel 1" "0,1"
|
|
bitfld.word 0x8 0. "SOE10,Serial output enable of channel 0" "0,1"
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "SOL1,Serial output level register 1"
|
|
bitfld.word 0x0 0. "SOL10,Selects inversion of the level of the transmit data of channel n in UART mode" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x208)++0x1
|
|
line.word 0x0 "SDR1$1,Serial data register 1%s"
|
|
repeat.end
|
|
group.byte 0x208++0x0
|
|
line.byte 0x0 "SIO20,SPI data register"
|
|
group.byte 0x20A++0x0
|
|
line.byte 0x0 "SIO21,SPI data register"
|
|
group.byte 0x208++0x0
|
|
line.byte 0x0 "TXD2,UART transmit data register"
|
|
group.byte 0x20A++0x0
|
|
line.byte 0x0 "RXD2,UART receive data register"
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x40042400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "SPIM,SPI mode control register"
|
|
bitfld.long 0x0 7. "SPIE,SPI operation enable" "0,1"
|
|
bitfld.long 0x0 6. "TRMD,Transfer and Receive mode" "0,1"
|
|
bitfld.long 0x0 5. "NSSE,NSS pin enable" "0,1"
|
|
bitfld.long 0x0 4. "DIR,MSB of LSB mode select" "0,1"
|
|
bitfld.long 0x0 3. "INTMD,interrupt source select" "0,1"
|
|
bitfld.long 0x0 2. "DLS,data length control" "0,1"
|
|
bitfld.long 0x0 1. "SDRIF,Receive buffer non-empty flag" "0,1"
|
|
bitfld.long 0x0 0. "SPTF,SPI transmission status flag" "0,1"
|
|
line.long 0x4 "SPIC,SPI control register"
|
|
bitfld.long 0x4 4. "CKP,Selection of clock phase for SPI" "0,1"
|
|
bitfld.long 0x4 3. "DAP,Selection of data phase for SPI" "0,1"
|
|
bitfld.long 0x4 0.--2. "CKS,Operation clock control" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "SDRO,Data buffer of transmission"
|
|
line.long 0xC "SDRI,Data buffer of reception"
|
|
tree.end
|
|
tree "TM (General Purpose Timer 4)"
|
|
base ad:0x0
|
|
tree "TM40"
|
|
base ad:0x40041D80
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
rgroup.word ($2)++0x1
|
|
line.word 0x0 "TCR0$1,Timer count register 0%s"
|
|
repeat.end
|
|
group.word 0x10++0x7
|
|
line.word 0x0 "TMR00,Timer mode register mn"
|
|
bitfld.word 0x0 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x0 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x0 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x0 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x2 "TMR01,Timer mode register mn"
|
|
bitfld.word 0x2 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x2 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x2 11. "SPLIT,Selection of 8 or 16-bit timer operation for channels 1 and 3" "0,1"
|
|
bitfld.word 0x2 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x2 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x4 "TMR02,Timer mode register mn"
|
|
bitfld.word 0x4 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x4 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x4 11. "MASTER,Selection between using channel n independently or simultaneously with another channel (as a slave or master)" "0,1"
|
|
bitfld.word 0x4 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x4 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x4 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x6 "TMR03,Timer mode register mn"
|
|
bitfld.word 0x6 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x6 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x6 11. "SPLIT,Selection of 8 or 16-bit timer operation for channels 1 and 3" "0,1"
|
|
bitfld.word 0x6 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x6 0.--3. 1. "MD,Operation mode of channel n"
|
|
rgroup.word 0x20++0x7
|
|
line.word 0x0 "TSR00,Timer status register mn"
|
|
bitfld.word 0x0 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x2 "TSR01,Timer status register mn"
|
|
bitfld.word 0x2 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x4 "TSR02,Timer status register mn"
|
|
bitfld.word 0x4 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x6 "TSR03,Timer status register mn"
|
|
bitfld.word 0x6 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
rgroup.word 0x30++0x1
|
|
line.word 0x0 "TE0,Timer channel enable status register m"
|
|
bitfld.word 0x0 11. "TEH03,Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 3 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x0 9. "TEH01,Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 1 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x0 3. "TE03,Indication of operation enable/stop status of channel 3" "0,1"
|
|
bitfld.word 0x0 2. "TE02,Indication of operation enable/stop status of channel 2" "0,1"
|
|
bitfld.word 0x0 1. "TE01,Indication of operation enable/stop status of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "TE00,Indication of operation enable/stop status of channel 0" "0,1"
|
|
group.word 0x32++0xD
|
|
line.word 0x0 "TS0,Timer channel start register 0"
|
|
bitfld.word 0x0 11. "TSH03,Trigger to enable operation (start operation) of the higher 8-bit timer when channel 3 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x0 9. "TSH01,Trigger to enable operation (start operation) of the higher 8-bit timer when channel 1 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x0 3. "TS03,Operation enable (start) trigger of channel 3" "0,1"
|
|
bitfld.word 0x0 2. "TS02,Operation enable (start) trigger of channel 2" "0,1"
|
|
bitfld.word 0x0 1. "TS01,Operation enable (start) trigger of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "TS00,Operation enable (start) trigger of channel 0" "0,1"
|
|
line.word 0x2 "TT0,Timer channel stop register 0"
|
|
bitfld.word 0x2 11. "TTH03,Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x2 9. "TTH01,Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x2 3. "TT03,Operation stop trigger of channel 3" "0,1"
|
|
bitfld.word 0x2 2. "TT02,Operation stop trigger of channel 2" "0,1"
|
|
bitfld.word 0x2 1. "TT01,Operation stop trigger of channel 1" "0,1"
|
|
bitfld.word 0x2 0. "TT00,Operation stop trigger of channel 0" "0,1"
|
|
line.word 0x4 "TPS0,Timer clock select register 0"
|
|
bitfld.word 0x4 12.--13. "PRS03,Prescaler 3" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "PRS02,Prescaler 2" "0,1,2,3"
|
|
hexmask.word.byte 0x4 4.--7. 1. "PRS01,Prescaler 1"
|
|
hexmask.word.byte 0x4 0.--3. 1. "PRS00,Prescaler 0"
|
|
line.word 0x6 "TO0,Timer output register 0"
|
|
bitfld.word 0x6 3. "TO03,Timer output of channel 3" "0,1"
|
|
bitfld.word 0x6 2. "TO02,Timer output of channel 2" "0,1"
|
|
bitfld.word 0x6 1. "TO01,Timer output of channel 1" "0,1"
|
|
bitfld.word 0x6 0. "TO00,Timer output of channel 0" "0,1"
|
|
line.word 0x8 "TOE0,Timer output enable register 0"
|
|
bitfld.word 0x8 3. "TOE03,Timer output enable of channel 3" "0,1"
|
|
bitfld.word 0x8 2. "TOE02,Timer output enable of channel 2" "0,1"
|
|
bitfld.word 0x8 1. "TOE01,Timer output enable of channel 1" "0,1"
|
|
bitfld.word 0x8 0. "TOE00,Timer output enable of channel 0" "0,1"
|
|
line.word 0xA "TOL0,Timer output level register 0"
|
|
bitfld.word 0xA 3. "TOL03,Control of timer output level of channel 3" "0,1"
|
|
bitfld.word 0xA 2. "TOL02,Control of timer output level of channel 2" "0,1"
|
|
bitfld.word 0xA 1. "TOL01,Control of timer output level of channel 1" "0,1"
|
|
line.word 0xC "TOM0,Timer output mode register 0"
|
|
bitfld.word 0xC 3. "TOM03,Control of timer output mode of channel 3" "0,1"
|
|
bitfld.word 0xC 2. "TOM02,Control of timer output mode of channel 2" "0,1"
|
|
bitfld.word 0xC 1. "TOM01,Control of timer output mode of channel 1" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x198)++0x1
|
|
line.word 0x0 "TDR0$1,Timer data register 0%s"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x1E4)++0x1
|
|
line.word 0x0 "TDR0$1,Timer data register 0%s"
|
|
repeat.end
|
|
group.byte 0x19A++0x1
|
|
line.byte 0x0 "TDR01L,Timer data lower register 01"
|
|
line.byte 0x1 "TDR01H,Timer data higher register 01"
|
|
group.byte 0x1E6++0x1
|
|
line.byte 0x0 "TDR03L,Timer data lower register 03"
|
|
line.byte 0x1 "TDR03H,Timer data higher register 03"
|
|
tree.end
|
|
tree "TM41"
|
|
base ad:0x40042180
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
rgroup.word ($2)++0x1
|
|
line.word 0x0 "TCR1$1,Timer count register 0%s"
|
|
repeat.end
|
|
group.word 0x10++0x7
|
|
line.word 0x0 "TMR10,Timer mode register mn"
|
|
bitfld.word 0x0 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x0 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x0 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x0 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x2 "TMR11,Timer mode register mn"
|
|
bitfld.word 0x2 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x2 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x2 11. "SPLIT,Selection of 8 or 16-bit timer operation for channels 1 and 3" "0,1"
|
|
bitfld.word 0x2 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x2 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x4 "TMR12,Timer mode register mn"
|
|
bitfld.word 0x4 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x4 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x4 11. "MASTER,Selection between using channel n independently or simultaneously with another channel (as a slave or master)" "0,1"
|
|
bitfld.word 0x4 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x4 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x4 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x6 "TMR13,Timer mode register mn"
|
|
bitfld.word 0x6 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x6 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x6 11. "SPLIT,Selection of 8 or 16-bit timer operation for channels 1 and 3" "0,1"
|
|
bitfld.word 0x6 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x6 0.--3. 1. "MD,Operation mode of channel n"
|
|
rgroup.word 0x20++0x7
|
|
line.word 0x0 "TSR10,Timer status register mn"
|
|
bitfld.word 0x0 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x2 "TSR11,Timer status register mn"
|
|
bitfld.word 0x2 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x4 "TSR12,Timer status register mn"
|
|
bitfld.word 0x4 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x6 "TSR13,Timer status register mn"
|
|
bitfld.word 0x6 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
rgroup.word 0x30++0x1
|
|
line.word 0x0 "TE1,Timer channel enable status register m"
|
|
bitfld.word 0x0 11. "TEH13,Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 3 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x0 9. "TEH11,Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 1 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x0 3. "TE13,Indication of operation enable/stop status of channel 3" "0,1"
|
|
bitfld.word 0x0 2. "TE12,Indication of operation enable/stop status of channel 2" "0,1"
|
|
bitfld.word 0x0 1. "TE11,Indication of operation enable/stop status of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "TE10,Indication of operation enable/stop status of channel 0" "0,1"
|
|
group.word 0x32++0xD
|
|
line.word 0x0 "TS1,Timer channel start register 0"
|
|
bitfld.word 0x0 11. "TSH13,Trigger to enable operation (start operation) of the higher 8-bit timer when channel 3 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x0 9. "TSH11,Trigger to enable operation (start operation) of the higher 8-bit timer when channel 1 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x0 3. "TS13,Operation enable (start) trigger of channel 3" "0,1"
|
|
bitfld.word 0x0 2. "TS12,Operation enable (start) trigger of channel 2" "0,1"
|
|
bitfld.word 0x0 1. "TS11,Operation enable (start) trigger of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "TS10,Operation enable (start) trigger of channel 0" "0,1"
|
|
line.word 0x2 "TT1,Timer channel stop register 0"
|
|
bitfld.word 0x2 11. "TTH13,Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x2 9. "TTH11,Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x2 3. "TT13,Operation stop trigger of channel 3" "0,1"
|
|
bitfld.word 0x2 2. "TT12,Operation stop trigger of channel 2" "0,1"
|
|
bitfld.word 0x2 1. "TT11,Operation stop trigger of channel 1" "0,1"
|
|
bitfld.word 0x2 0. "TT10,Operation stop trigger of channel 0" "0,1"
|
|
line.word 0x4 "TPS1,Timer clock select register 0"
|
|
bitfld.word 0x4 12.--13. "PRS13,Prescaler 3" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "PRS12,Prescaler 2" "0,1,2,3"
|
|
hexmask.word.byte 0x4 4.--7. 1. "PRS11,Prescaler 1"
|
|
hexmask.word.byte 0x4 0.--3. 1. "PRS10,Prescaler 0"
|
|
line.word 0x6 "TO1,Timer output register 0"
|
|
bitfld.word 0x6 3. "TO13,Timer output of channel 3" "0,1"
|
|
bitfld.word 0x6 2. "TO12,Timer output of channel 2" "0,1"
|
|
bitfld.word 0x6 1. "TO11,Timer output of channel 1" "0,1"
|
|
bitfld.word 0x6 0. "TO10,Timer output of channel 0" "0,1"
|
|
line.word 0x8 "TOE1,Timer output enable register 0"
|
|
bitfld.word 0x8 3. "TOE13,Timer output enable of channel 3" "0,1"
|
|
bitfld.word 0x8 2. "TOE12,Timer output enable of channel 2" "0,1"
|
|
bitfld.word 0x8 1. "TOE11,Timer output enable of channel 1" "0,1"
|
|
bitfld.word 0x8 0. "TOE10,Timer output enable of channel 0" "0,1"
|
|
line.word 0xA "TOL1,Timer output level register 0"
|
|
bitfld.word 0xA 3. "TOL13,Control of timer output level of channel 3" "0,1"
|
|
bitfld.word 0xA 2. "TOL12,Control of timer output level of channel 2" "0,1"
|
|
bitfld.word 0xA 1. "TOL11,Control of timer output level of channel 1" "0,1"
|
|
line.word 0xC "TOM1,Timer output mode register 0"
|
|
bitfld.word 0xC 3. "TOM13,Control of timer output mode of channel 3" "0,1"
|
|
bitfld.word 0xC 2. "TOM12,Control of timer output mode of channel 2" "0,1"
|
|
bitfld.word 0xC 1. "TOM11,Control of timer output mode of channel 1" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x198)++0x1
|
|
line.word 0x0 "TDR1$1,Timer data register 0%s"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x1E4)++0x1
|
|
line.word 0x0 "TDR1$1,Timer data register 0%s"
|
|
repeat.end
|
|
group.byte 0x19A++0x1
|
|
line.byte 0x0 "TDR11L,Timer data lower register 01"
|
|
line.byte 0x1 "TDR11H,Timer data higher register 01"
|
|
group.byte 0x1E6++0x1
|
|
line.byte 0x0 "TDR13L,Timer data lower register 03"
|
|
line.byte 0x1 "TDR13H,Timer data higher register 03"
|
|
tree.end
|
|
tree.end
|
|
tree "TSN (Temperature Sensor Calibration Data)"
|
|
base ad:0x500668
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "TSN85,The A/D conversion value of Temperature Sensor at 85 degrees and 3.0V reference voltage"
|
|
line.long 0x4 "TSN25,The A/D conversion value of Temperature Sensor at 25 degrees and 3.0V reference voltage"
|
|
tree.end
|
|
tree "UID (128-bit Unique ID)"
|
|
base ad:0x500894
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "UID$1,UID word %s"
|
|
repeat.end
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x40020404
|
|
group.byte 0x1++0x1
|
|
line.byte 0x0 "LOCKCTL,Lockup Watchdog timer enable register"
|
|
line.byte 0x1 "PRCR,Lockup Watchdog timer enable protect register"
|
|
group.byte 0xBFD++0x0
|
|
line.byte 0x0 "WDTE,Watchdog timer enable register"
|
|
tree.end
|
|
newline
|
|
AUTOINDENT.OFF
|