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Work/Src/Gen4_R-Car_Trace32/2_Trunk/perstm32wl3.per
woody 6daf21a46d add
2026-06-16 12:20:14 +09:00

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; --------------------------------------------------------------------------------
; @Title: STM32WL3 On-Chip Peripherals
; @Props: Released
; @Author: NEJ
; @Changelog: 2024-12-04 NEJ
; @Manufacturer: STM - ST Microelectronics N.V.
; @Doc: Generated (TRACE32, build: 174943.), based on: STM32WL33.svd (Ver. 1.0)
; @Core: Cortex-M0+
; @Chip: STM32WL33C8, STM32WL33CB, STM32WL33CC, STM32WL33K8,
; STM32WL33KB, STM32WL33KC
; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perstm32wl3.per 18692 2024-12-04 14:43:51Z kwisniewski $
AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M0+)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
textline " "
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
textline " "
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC21=Cortex-M1"
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
elif (CORENAME()=="CORTEXM0+")
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
textline " "
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
textline " "
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC60=Cortex-M0+"
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
else
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
textline " "
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
textline " "
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC20=Cortex-M0"
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
endif
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline " "
textline " "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "ADC (Analog/Digital Converter)"
base ad:0x41006000
rgroup.long 0x0++0x3
line.long 0x0 "VERSION_ID,VERSION_ID register"
hexmask.long.byte 0x0 0.--7. 1. "VERSION_ID,VERSION_ID[7:0]: version of the embedded IP."
group.long 0x4++0x7
line.long 0x0 "CONF,CONF register"
bitfld.long 0x0 21.--23. "SAMPLE_RATE_MSB,SAMPLE_RATE_MSB: Sample Rate MSB" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 19. "ADC_CONT_1V2,ADC_CONT_1V2: select the input sampling method:" "0: sampling only at conversion start,1: sampling starts at the end of conversion"
newline
bitfld.long 0x0 18. "BIT_INVERT_DIFF,BIT_INVERT_DIFF: invert bit to bit the ADC data output (1's complement) when a differential" "0: no inversion,1: enable the inversion"
bitfld.long 0x0 17. "BIT_INVERT_SN,BIT_INVERT_SN: invert bit to bit the ADC data output (1's complement) when a single" "0: no inversion,1: enable the inversion"
newline
bitfld.long 0x0 15. "OVR_DS_CFG,OVR_DS_CFG: Down Sampler overrun configuration:" "0: the previous data is kept,1: the previous data is lost"
bitfld.long 0x0 13. "DMA_DS_ENA,DMA_DS_EN: enable the DMA mode for the Down Sampler data path:" "0: DMA mode is disabled,1: DMA mode is enabled"
newline
bitfld.long 0x0 11.--12. "SAMPLE_RATE,SAMPLE_RATE[1:0]: conversion rate of ADC (F_ADC):" "0,1,2,3"
bitfld.long 0x0 9.--10. "SAMPLE_RATE_LSB,SAMPLE_RATE_LSB: Sample Rate LSB" "0,1,2,3"
newline
bitfld.long 0x0 6. "SMPS_SYNCHRO_ENA,SMPS_SYNCHRO_ENA: synchronize the ADC start conversion with a pulse generated by the" "0: SMPS synchronization is disabled for all ADC..,1: SMPS synchronization is enabled"
hexmask.long.byte 0x0 2.--5. 1. "SEQ_LEN,SEQ_LEN[3:0]: number of conversions in a regular sequence:"
newline
bitfld.long 0x0 1. "SEQUENCE,SEQUENCE: enable the sequence mode (active by default):" "0: sequence mode is disabled,1: sequence mode is enabled"
bitfld.long 0x0 0. "CONT,CONT: regular sequence runs continuously when ADC mode is enabled:" "0: enable the single conversion: when the sequence..,1: enable the continuous conversion: when the.."
line.long 0x4 "CTRL,CTRL register"
bitfld.long 0x4 4. "TEST_MODE,TEST_MODE: select the functional or the test mode of the ADC:" "0: functional mode,1: test mode"
bitfld.long 0x4 2. "STOP_OP_MODE,STOP_OP_MODE (1): stop the on-going OP_MODE (ADC mode Analog audio mode Full" "0: no effect,1: stop on-going ADC mode"
newline
bitfld.long 0x4 1. "START_CONV,START_CONV (1): generate a start pulse to initiate an ADC conversion:" "0: no effect,1: start the ADC conversion"
bitfld.long 0x4 0. "ADC_ON_OFF,ADC_ON_OFF:" "0: power off the ADC,1: power on the ADC"
group.long 0x14++0x3
line.long 0x0 "SWITCH,SWITCH register"
bitfld.long 0x0 14.--15. "SE_VIN_7,SE_VIN_7[1:0]: input voltage for VINP[3]" "0: Vinput = 1,1: reserved,?,?"
bitfld.long 0x0 12.--13. "SE_VIN_6,SE_VIN_6[1:0]: input voltage for VINP[2]" "0: Vinput = 1,1: reserved,?,?"
newline
bitfld.long 0x0 10.--11. "SE_VIN_5,SE_VIN_5[1:0]: input voltage for VINP[1]" "0: Vinput = 1,1: reserved,?,?"
bitfld.long 0x0 8.--9. "SE_VIN_4,SE_VIN_4[1:0]: input voltage for VINP[0]" "0: Vinput = 1,1: reserved,?,?"
newline
bitfld.long 0x0 6.--7. "SE_VIN_3,SE_VIN_3[1:0]: input voltage for VINM[3] / VINP[3]-VINM[3]" "0: Vinput = 1,1: reserved,?,?"
bitfld.long 0x0 4.--5. "SE_VIN_2,SE_VIN_2[1:0]: input voltage for VINM[2] / VINP[2]-VINM[2]" "0: Vinput = 1,1: reserved,?,?"
newline
bitfld.long 0x0 2.--3. "SE_VIN_1,SE_VIN_1[1:0]: input voltage for VINM[1] / VINP[1]-VINM[1]" "0: Vinput = 1,1: reserved,?,?"
bitfld.long 0x0 0.--1. "SE_VIN_0,SE_VIN_0[1:0]: input voltage for VINM[0] / VINP[0]-VINM[0]" "0: Vinput = 1,1: reserved,?,?"
group.long 0x1C++0x27
line.long 0x0 "DS_CONF,DS_CONF register"
bitfld.long 0x0 3.--5. "DS_WIDTH,DS_WIDTH[2:0]: program the Down Sampler width of data output (DSDTATA)" "0: DS_DATA output on 12-bit,1: DS_DATA output on 13-bit,?,?,?,?,?,?"
bitfld.long 0x0 0.--2. "DS_RATIO,DS_RATIO[2:0]: program the Down Sampler ratio (N factor)" "0: ratio = 1,1: ratio = 2,?,?,?,?,?,?"
line.long 0x4 "SEQ_1,SEQ_1 register"
hexmask.long.byte 0x4 28.--31. 1. "SEQ7,SEQ7[3:0]: channel number code for 8th conversion of the sequence."
hexmask.long.byte 0x4 24.--27. 1. "SEQ6,SEQ6[3:0]: channel number code for 7th conversion of the sequence."
newline
hexmask.long.byte 0x4 20.--23. 1. "SEQ5,SEQ5[3:0]: channel number code for 6th conversion of the sequence."
hexmask.long.byte 0x4 16.--19. 1. "SEQ4,SEQ4[3:0]: channel number code for 5th conversion of the sequence."
newline
hexmask.long.byte 0x4 12.--15. 1. "SEQ3,SEQ3[3:0]: channel number code for 4th conversion of the sequence."
hexmask.long.byte 0x4 8.--11. 1. "SEQ2,SEQ2[3:0]: channel number code for 3rd conversion of the sequence."
newline
hexmask.long.byte 0x4 4.--7. 1. "SEQ1,SEQ1[3:0]: channel number code for second conversion of the sequence."
hexmask.long.byte 0x4 0.--3. 1. "SEQ0,SEQ0[3:0]: channel number code for first conversion of the sequence"
line.long 0x8 "SEQ_2,SEQ_2 register"
hexmask.long.byte 0x8 28.--31. 1. "SEQ15,SEQ15[3:0]: channel number code for 16th conversion of the sequence."
hexmask.long.byte 0x8 24.--27. 1. "SEQ14,SEQ14[3:0]: channel number code for 15th conversion of the sequence."
newline
hexmask.long.byte 0x8 20.--23. 1. "SEQ13,SEQ13[3:0]: channel number code for 14th conversion of the sequence."
hexmask.long.byte 0x8 16.--19. 1. "SEQ12,SEQ12[3:0]: channel number code for 13th conversion of the sequence."
newline
hexmask.long.byte 0x8 12.--15. 1. "SEQ11,SEQ11[3:0]: channel number code for 12th conversion of the sequence."
hexmask.long.byte 0x8 8.--11. 1. "SEQ10,SEQ10[3:0]: channel number code for 11th conversion of the sequence."
newline
hexmask.long.byte 0x8 4.--7. 1. "SEQ9,SEQ9[3:0]: channel number code for 10th conversion of the sequence."
hexmask.long.byte 0x8 0.--3. 1. "SEQ8,SEQ8[3:0]: channel number code for 9th conversion of the sequence"
line.long 0xC "COMP_1,COMP_1 register"
hexmask.long.byte 0xC 12.--19. 1. "OFFSET1,OFFSET1[7:0]: first calibration point"
hexmask.long.word 0xC 0.--11. 1. "GAIN1,GAIN1[11:0]: first calibration point: gain AUXADC_GAIN_1V2[11:0]"
line.long 0x10 "COMP_2,COMP_2 register"
hexmask.long.byte 0x10 12.--19. 1. "OFFSET2,OFFSET2[7:0]: second calibration point"
hexmask.long.word 0x10 0.--11. 1. "GAIN2,GAIN2[11:0]: second calibration point: gain AUXADC_GAIN_1V2[11:0]"
line.long 0x14 "COMP_3,COMP_3 register"
hexmask.long.byte 0x14 12.--19. 1. "OFFSET3,OFFSET3[7:0]: third calibration point"
hexmask.long.word 0x14 0.--11. 1. "GAIN3,GAIN3[11:0]: third calibration point: gain AUXADC_GAIN_1V2[11:0]"
line.long 0x18 "COMP_4,COMP_4 register"
hexmask.long.byte 0x18 12.--19. 1. "OFFSET4,OFFSET4[7:0]: fourth calibration point"
hexmask.long.word 0x18 0.--11. 1. "GAIN4,GAIN4[11:0]: fourth calibration point: gain AUXADC_GAIN_1V2[11:0]"
line.long 0x1C "COMP_SEL,COMP_SEL register"
bitfld.long 0x1C 16.--17. "OFFSET_GAIN8,OFFSET_GAIN8[1:0]: gain / offset used in ADC differential mode with Vinput range = 3.6V:" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
bitfld.long 0x1C 14.--15. "OFFSET_GAIN7,OFFSET_GAIN7[1:0]: gain / offset used in ADC single positive mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
newline
bitfld.long 0x1C 12.--13. "OFFSET_GAIN6,OFFSET_GAIN6[1:0]: gain / offset used in ADC single negative mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
bitfld.long 0x1C 10.--11. "OFFSET_GAIN5,OFFSET_GAIN5[1:0]: gain / offset used in ADC differential mode with Vinput range = 2.4V:" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
newline
bitfld.long 0x1C 8.--9. "OFFSET_GAIN4,OFFSET_GAIN4[1:0]: gain / offset used in ADC single positive mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
bitfld.long 0x1C 6.--7. "OFFSET_GAIN3,OFFSET_GAIN3[1:0]: gain / offset used in ADC single negative mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
newline
bitfld.long 0x1C 4.--5. "OFFSET_GAIN2,OFFSET_GAIN2[1:0]: gain / offset used in ADC differential mode with Vinput range = 1.2V:" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
bitfld.long 0x1C 2.--3. "OFFSET_GAIN1,OFFSET_GAIN1[1:0]: gain / offset used in ADC single positive mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
newline
bitfld.long 0x1C 0.--1. "OFFSET_GAIN0,OFFSET_GAIN0[1:0]: gain / offset used in ADC single negative mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
line.long 0x20 "WD_TH,WD_TH register"
hexmask.long.word 0x20 16.--27. 1. "WD_HT,WD_HT[11:0]: analog watchdog high level threshold."
hexmask.long.word 0x20 0.--11. 1. "WD_LT,WD_LT[11:0]: analog watchdog low level threshold."
line.long 0x24 "WD_CONF,WD_CONF register"
hexmask.long.word 0x24 0.--15. 1. "AWD_CHX,AWD_CHX[15:0]: analog watchdog channel selection to define which input channel(s) need"
rgroup.long 0x44++0x3
line.long 0x0 "DS_DATAOUT,DS_DATAOUT register"
hexmask.long.word 0x0 0.--15. 1. "DS_DATA,DS_DATA[15:0]: contain the converted data at the output of the Down Sampler."
group.long 0x4C++0x7
line.long 0x0 "IRQ_STATUS,IRQ_STATUS register"
bitfld.long 0x0 5. "OVR_DS_IRQ,OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost)" "0: no effect,1: clear the interrupt"
bitfld.long 0x0 4. "AWD_IRQ,AWD_IRQ: set when an analog watchdog event occurs." "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x0 3. "EOS_IRQ,EOS_IRQ: set when a sequence of conversion is completed." "0: no effect,1: clear the interrupt"
bitfld.long 0x0 1. "EODS_IRQ,EODS_IRQ: set when the Down Sampler conversion is completed." "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x0 0. "EOC_IRQ,EOC_IRQ (Used in test mode only): set when the ADC conversion is completed." "0: no effect,1: clear the interrupt"
line.long 0x4 "IRQ_ENABLE,IRQ_ENABLE register"
bitfld.long 0x4 5. "OVR_DS_IRQ,OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost)" "0: no effect,1: clear the interrupt"
bitfld.long 0x4 4. "AWD_IRQ,AWD_IRQ: set when an analog watchdog event occurs." "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x4 3. "EOS_IRQ,EOS_IRQ: set when a sequence of conversion is completed." "0: no effect,1: clear the interrupt"
bitfld.long 0x4 1. "EODS_IRQ,EODS_IRQ: set when the Down Sampler conversion is completed." "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x4 0. "EOC_IRQ,EOC_IRQ (Used in test mode only): set when the ADC conversion is completed." "0: no effect,1: clear the interrupt"
group.long 0x60++0x7
line.long 0x0 "TEST_CONF,TEST_CONF register"
bitfld.long 0x0 22. "ADC_ENABLE,ADC_ENABLE:" "0: disable the ADC,1: enable the ADC"
bitfld.long 0x0 21. "ADC_RUN,ADC_RUN: Start/stop ADC conversion." "0: stop the ADC conversion,1: starts the ADC conversion"
newline
bitfld.long 0x0 18.--19. "SEL_VIN_TYPE,SEL_VIN_TYPE[1:0]: operation mode of the selected VIN" "0: ADC single negative input,1: ADC single positive input,?,?"
hexmask.long.word 0x0 0.--15. 1. "ADC_SWITCH_EN,ADC_SWITCH_EN[15:0]: enable individually each connection of the switching matrix at the"
line.long 0x4 "DTB_CONF,DTB_CONF register"
rbitfld.long 0x4 24.--26. "FSM_CUR_STATE,FSM_CUR_STATE[2:0]: show the last executed state by the state machine." "0: IDLE mode,1: Reserved,?,?,?,?,?,?"
hexmask.long.byte 0x4 16.--23. 1. "FSM_STATE,FSM_STATE[7:0]: show the state of the state machine."
newline
bitfld.long 0x4 10. "DTB_SER_SEL,DTB_SER_SEL: DTB serial output selection when ADC_DB_CONF[1:0]=3d" "0: pre down-sampler with offset compensation data,1: post down-sampler data"
bitfld.long 0x4 8.--9. "ADC_DTB_CONF,ADC_DTB_CONF[1:0]: configure the DTB output." "0: DTB bus is all 0,1: output the ADC_BUSY,?,?"
newline
hexmask.long.byte 0x4 0.--3. 1. "ADC_DBG_CONF,ADC_DBG_CONF[3:0]: use for debug purpose."
tree.end
tree "AES (AES Hardware Accelerator)"
base ad:0x48900000
group.long 0x0++0x3
line.long 0x0 "AES_CR,AES_CR register"
hexmask.long.byte 0x0 20.--23. 1. "NPBLB,NPBLB: Number of Padding Bytes in Last Block of payload."
bitfld.long 0x0 18. "KEYSIZE,KEYSIZE: Key Size selection." "0,1"
bitfld.long 0x0 16. "CHMOD_2,CHMOD[2]: Chaining mode selection bit [2]" "0,1"
bitfld.long 0x0 13.--14. "GCMPH,GCMPH[1:0]: GCM or CCM Phase selection" "0,1,2,3"
bitfld.long 0x0 12. "DMAOUTEN,DMAOUTEN: DMA Output Enable" "0,1"
bitfld.long 0x0 11. "DMAINEN,DMAINEN: DMA Input Enable" "0,1"
bitfld.long 0x0 10. "ERRIE,ERRIE: Error Interrupt Enable" "0,1"
bitfld.long 0x0 9. "CCFIE,CCFIE: CCF Flag Interrupt Enable" "0,1"
bitfld.long 0x0 8. "ERRC,ERRC: Error clear" "0,1"
bitfld.long 0x0 7. "CCFC,CCFC: Computation Complete Flag Clear" "0,1"
newline
bitfld.long 0x0 5.--6. "CHMOD_1_0,CHMOD[1:0]: AES Chaining Mode selection" "0,1,2,3"
bitfld.long 0x0 3.--4. "MODE,MODE[1:0]: AES operating mode" "0,1,2,3"
bitfld.long 0x0 1.--2. "DATATYPE,DATATYPE[1:0]: Data type selection" "0,1,2,3"
bitfld.long 0x0 0. "EN,EN: AES IP enable" "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "AES_SR,AES_SR register"
bitfld.long 0x0 3. "BUSY,BUSY: Busy flag" "0,1"
bitfld.long 0x0 2. "WRERR,WRERR: Write error flag" "0,1"
bitfld.long 0x0 1. "RDERR,RDERR: Read error flag" "0,1"
bitfld.long 0x0 0. "CCF,CCF: Computation complete flag" "0,1"
group.long 0x8++0x3
line.long 0x0 "AES_DINR,AES_DINR register"
hexmask.long 0x0 0.--31. 1. "DINR,DINR[x+31:x]: One of four 32-bit words of a 128-bit input data block being written into the peripheral"
rgroup.long 0xC++0x3
line.long 0x0 "AES_DOUTR,AES_DOUTR register"
hexmask.long 0x0 0.--31. 1. "DOUTR,DOUTR[x+31:x]: One of four 32-bit words of a 128-bit output data block being read from the"
group.long 0x10++0x1F
line.long 0x0 "AES_KEYR0,AES_KEYRx register"
hexmask.long 0x0 0.--31. 1. "KEY,KEY [((32*x)+31):((32*x)+0)]: Cryptographic key bits [((32*x)+31):((32*x)+0)]"
line.long 0x4 "AES_KEYR1,AES_KEYRx register"
hexmask.long 0x4 0.--31. 1. "KEY,KEY [((32*x)+31):((32*x)+0)]: Cryptographic key bits [((32*x)+31):((32*x)+0)]"
line.long 0x8 "AES_KEYR2,AES_KEYRx register"
hexmask.long 0x8 0.--31. 1. "KEY,KEY [((32*x)+31):((32*x)+0)]: Cryptographic key bits [((32*x)+31):((32*x)+0)]"
line.long 0xC "AES_KEYR3,AES_KEYRx register"
hexmask.long 0xC 0.--31. 1. "KEY,KEY [((32*x)+31):((32*x)+0)]: Cryptographic key bits [((32*x)+31):((32*x)+0)]"
line.long 0x10 "AES_IVR0,AES_IVRx register"
hexmask.long 0x10 0.--31. 1. "IVI,IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)])"
line.long 0x14 "AES_IVR1,AES_IVRx register"
hexmask.long 0x14 0.--31. 1. "IVI,IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)])"
line.long 0x18 "AES_IVR2,AES_IVRx register"
hexmask.long 0x18 0.--31. 1. "IVI,IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)])"
line.long 0x1C "AES_IVR3,AES_IVRx register"
hexmask.long 0x1C 0.--31. 1. "IVI,IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)])"
tree.end
tree "COMP (Comparator)"
base ad:0x40009000
group.long 0x0++0x3
line.long 0x0 "CSR,CSR register"
rbitfld.long 0x0 31. "LOCK,LOCK: COMP_CSR register lock bit" "0: COMP1_CSR[31:0] are read/write,1: COMP1_CSR[31:0] are read-only"
rbitfld.long 0x0 30. "VALUE,VALUE: Comparator output status bit" "0,1"
bitfld.long 0x0 23. "SCALEN,SCALEN: Voltage scaler enable bit" "0: scaler disable,1: scaler enable"
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bitfld.long 0x0 22. "BRGEN,BRGEN: Scaler bridge enable" "0: Scaler resistor bridge disable,1: Scaler resistor bridge enable"
bitfld.long 0x0 18.--20. "BLANKING,BLANKING[2:0]: Comparator blanking source selection bits" "0: No blanking,1: TIM2 OC4 selected as blanking source,?,?,?,?,?,?"
bitfld.long 0x0 16.--17. "HYST,HYST[1:0]: Comparator hysteresis selection bits" "0: No hysteresis,1: Low hysteresis,?,?"
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bitfld.long 0x0 15. "POLARITY,POLARITY: Comparator polarity selection bit" "0: Comparator output value not inverted,1: Comparator output value inverted"
bitfld.long 0x0 7.--8. "INPSEL,INPSEL[1:0]: Comparator input plus selection bit" "0: PA14,1: PB1,?,?"
bitfld.long 0x0 4.--6. "INMSEL,INMSEL: Comparator input minus selection bits" "0: 1/4 VREFINT,1: 1/2 VREFINT,?,?,?,?,?,?"
newline
bitfld.long 0x0 2.--3. "PWRMODE,PWRMODE[1:0]: Power Mode of the comparator" "0: High speed,?,?,?"
bitfld.long 0x0 0. "EN,EN: Comparator enable bit" "0: Comparator switched OFF,1: Comparator switched ON"
tree.end
tree "CRC (Cyclic Redundancy Check Calculation Unit)"
base ad:0x48200000
group.long 0x0++0xB
line.long 0x0 "CRC_DR,CRC_DR register"
hexmask.long 0x0 0.--31. 1. "DR,Data register bits."
line.long 0x4 "CRC_IDR,CRC_IDR register"
hexmask.long 0x4 0.--31. 1. "IDR"
line.long 0x8 "CRC_CR,CRC_CR register"
bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0,1"
bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0,1,2,3"
bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0,1,2,3"
bitfld.long 0x8 0. "RESET,RESET bit" "0,1"
group.long 0x10++0x7
line.long 0x0 "CRC_INIT,CRC_INIT register"
hexmask.long 0x0 0.--31. 1. "INIT,Programmable initial CRC value"
line.long 0x4 "CRC_POL,CRC_POL register"
hexmask.long 0x4 0.--31. 1. "POL,POL[31:0]: Programmable polynomial"
tree.end
tree "DAC (Digital to Analog Converter)"
base ad:0x40006000
group.long 0x0++0x3
line.long 0x0 "CR,CR register"
bitfld.long 0x0 16. "VCMON,VCMON: VCMBUFF power-up. This bit is set and cleared by software." "0: VCM BUFFER OFF,1: VCM BUFFER ON"
bitfld.long 0x0 15. "VCMEN,VCMEN: DAC channel output to VCM BUFFER enable. This bit is set and cleared by" "0: DAC channel output to VCM BUFFER disabled,1: DAC channel output to VCM BUFFER enabled"
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bitfld.long 0x0 14. "CMPEN,CMPEN: DAC channel output to COMP INMINUS enable. This bit is set and cleared by" "0: DAC channel output to COMP INMINUS disabled,1: DAC channel output to COMP INMINUS enabled"
bitfld.long 0x0 13. "DMAUDRIE,DMAUDRIE: DAC channel DMA Underrun Interrupt enable This bit is set and cleared by" "0: DAC channel DMA Underrun Interrupt disabled,1: DAC channel DMA Underrun Interrupt enabled"
newline
bitfld.long 0x0 12. "DMAEN,DMAEN: DAC channel DMA enable This bit is set and cleared by software." "0: DAC channel DMA mode disabled,1: DAC channel DMA mode enabled"
hexmask.long.byte 0x0 8.--11. 1. "MAMP,MAMP[3:0]: DAC channel mask amplitude selector These bits are written by software to"
newline
bitfld.long 0x0 6.--7. "WAVE,WAVE[1:0]: DAC channel noise/triangle wave generation enable These bits are set and" "0: wave generation disabled,1: Noise wave generation enabled,?,?"
bitfld.long 0x0 3.--5. "TSEL,TSEL[2:0]: DAC channel trigger selection These bits select the external event used to trigger" "0: Timer 16 TRGO event,1: PA8 pin event from SYSCFG,?,?,?,?,?,?"
newline
bitfld.long 0x0 2. "TEN,TEN: DAC channel trigger enable This bit is set and cleared by software to enable/disable" "0: DAC channel trigger disabled and data written..,1: DAC channel trigger enabled and data from the.."
bitfld.long 0x0 1. "BON,BON: DAC channel output buffer enable. This bit is set and cleared by software to" "0: DAC channel output buffer disabled,1: DAC channel output buffer enabled"
newline
bitfld.long 0x0 0. "EN,EN: DAC channel enable This bit is set and cleared by software to enable/disable DAC" "0: DAC channel disabled,1: DAC channel enabled"
wgroup.long 0x4++0x3
line.long 0x0 "SWTRIGR,SWTRIGR register"
bitfld.long 0x0 0. "SWTRIG,SWTRIG: DAC channel software trigger This bit is set by software to enable/disable the" "0: Software trigger disabled,1: Software trigger enabled"
group.long 0x10++0x3
line.long 0x0 "DHR,DHR register"
hexmask.long.byte 0x0 0.--5. 1. "DACDHR,DACDHR[5:0]: DAC channel 6-bit data These bits are written by software which"
rgroup.long 0x2C++0x3
line.long 0x0 "DOR,DOR register"
hexmask.long.byte 0x0 0.--5. 1. "DACDOR,DACDOR[5:0]: DAC channel data output These bits are read-only they contain data output"
group.long 0x34++0x3
line.long 0x0 "SR,SR register"
bitfld.long 0x0 13. "DMAUDR,DMAUDR: DAC channel DMA underrun flag This bit is set by hardware and cleared by" "0: No DMA underrun error condition occurred for DAC..,1: DMA underrun error condition occurred for DAC.."
tree.end
tree "DBGMCU (Debug Support)"
base ad:0x40008000
group.long 0x0++0xB
line.long 0x0 "CR,CR register"
bitfld.long 0x0 1. "DBG_STOP,Allow debug of the CPU in DEEPSTOP mode" "0: Normal operation,1: Automatic clock stop disabled"
bitfld.long 0x0 0. "DBG_SLEEP,Allow debug of the CPU in SLEEP mode" "0: Normal operation,1: Automatic clock stop disabled"
line.long 0x4 "DBG_APB0_FZ,DBG_APB0_FZ register"
bitfld.long 0x4 14. "DBG_IWDG_STOP,IWDG stop in the CPU debug" "0: Normal operation,1: Stop in debug"
bitfld.long 0x4 12. "DBG_RTC_STOP,RTC stop in CPU debug" "0: Normal operation,1: Stop in debug"
bitfld.long 0x4 1. "DBG_TIM16_STOP,TIM16 stop in the CPU debug" "0: Normal operation,1: Stop in debug"
newline
bitfld.long 0x4 0. "DBG_TIM2_STOP,TIM2 stop in the CPU debug" "0: Normal operation,1: Stop in debug"
line.long 0x8 "DBG_APB1_FZ,DBG_APB1_FZ register"
bitfld.long 0x8 23. "DBG_I2C2_STOP,I2C2 SMBUS timeout stop in CPU debug" "0: Normal operation,1: Stop in debug"
bitfld.long 0x8 21. "DBG_I2C1_STOP,I2C1 SMBUS timeout stop in CPU debug" "0: Normal operation,1: Stop in debug"
tree.end
tree "DMA (Direct Memory Access)"
base ad:0x48700000
rgroup.long 0x0++0x3
line.long 0x0 "DMA_ISR,DMA_ISR register"
bitfld.long 0x0 31. "TE1F8,TEIF8: Channel 8 transfer error flag.." "0: No transfer error,1: A transfer error"
bitfld.long 0x0 30. "HTIF8,HTIF8: Channel 8 half transfer flag" "0: No half transfer,1: A half transfer"
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bitfld.long 0x0 29. "TCIF8,TCIF8: Channel 8 transfer complete flag" "0: No transfer complete,1: A transfer complete"
bitfld.long 0x0 28. "GIF8,GIF8: Channel 8 global interrupt flag" "0: No TE,1: A TE"
newline
bitfld.long 0x0 27. "TE1F7,TEIF7: Channel 7 transfer error flag.." "0: No transfer error,1: A transfer error"
bitfld.long 0x0 26. "HTIF7,HTIF7: Channel 7 half transfer flag" "0: No half transfer,1: A half transfer"
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bitfld.long 0x0 25. "TCIF7,TCIF7: Channel 7 transfer complete flag" "0: No transfer complete,1: A transfer complete"
bitfld.long 0x0 24. "GIF7,GIF7: Channel 7 global interrupt flag" "0: No TE,1: A TE"
newline
bitfld.long 0x0 23. "TE1F6,TEIF6: Channel 6 transfer error flag.." "0: No transfer error,1: A transfer error"
bitfld.long 0x0 22. "HTIF6,HTIF6: Channel 6 half transfer flag" "0: No half transfer,1: A half transfer"
newline
bitfld.long 0x0 21. "TCIF6,TCIF6: Channel 6 transfer complete flag" "0: No transfer complete,1: A transfer complete"
bitfld.long 0x0 20. "GIF6,GIF6: Channel 6 global interrupt flag" "0: No TE,1: A TE"
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bitfld.long 0x0 19. "TE1F5,TEIF5: Channel 5 transfer error flag.." "0: No transfer error,1: A transfer error"
bitfld.long 0x0 18. "HTIF5,HTIF5: Channel 5 half transfer flag" "0: No half transfer,1: A half transfer"
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bitfld.long 0x0 17. "TCIF5,TCIF5: Channel 5 transfer complete flag" "0: No transfer complete,1: A transfer complete"
bitfld.long 0x0 16. "GIF5,GIF5: Channel 5 global interrupt flag" "0: No TE,1: A TE"
newline
bitfld.long 0x0 15. "TE1F4,TEIF4: Channel 4 transfer error flag.." "0: No transfer error,1: A transfer error"
bitfld.long 0x0 14. "HTIF4,HTIF4: Channel 4 half transfer flag" "0: No half transfer,1: A half transfer"
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bitfld.long 0x0 13. "TCIF4,TCIF4: Channel 4 transfer complete flag" "0: No transfer complete,1: A transfer complete"
bitfld.long 0x0 12. "GIF4,GIF4: Channel 4 global interrupt flag" "0: No TE,1: A TE"
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bitfld.long 0x0 11. "TE1F3,TEIF3: Channel 3 transfer error flag.." "0: No transfer error,1: A transfer error"
bitfld.long 0x0 10. "HTIF3,HTIF3: Channel 3 half transfer flag" "0: No half transfer,1: A half transfer"
newline
bitfld.long 0x0 9. "TCIF3,TCIF3: Channel 3 transfer complete flag" "0: No transfer complete,1: A transfer complete"
bitfld.long 0x0 8. "GIF3,GIF3: Channel 3 global interrupt flag" "0: No TE,1: A TE"
newline
bitfld.long 0x0 7. "TE1F2,TEIF2: Channel 2 transfer error flag.." "0: No transfer error,1: A transfer error"
bitfld.long 0x0 6. "HTIF2,HTIF2: Channel 2 half transfer flag" "0: No half transfer,1: A half transfer"
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bitfld.long 0x0 5. "TCIF2,TCIF2: Channel 2 transfer complete flag" "0: No transfer complete,1: A transfer complete"
bitfld.long 0x0 4. "GIF2,GIF2: Channel 2 global interrupt flag" "0: No TE,1: A TE"
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bitfld.long 0x0 3. "TE1F1,TEIF1: Channel 1 transfer error flag.." "0: No transfer error,1: A transfer error"
bitfld.long 0x0 2. "HTIF1,HTIF1: Channel 1 half transfer flag" "0: No half transfer,1: A half transfer"
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bitfld.long 0x0 1. "TCIF1,TCIF1: Channel 1 transfer complete flag" "0: No transfer complete,1: A transfer complete"
bitfld.long 0x0 0. "GIF1,GIF1: Channel 1 global interrupt flag" "0: No TE,1: A TE"
wgroup.long 0x4++0x3
line.long 0x0 "DMA_IFCR,DMA_IFCR register"
bitfld.long 0x0 31. "CTEIF8,CTEIF8: Channel 8 transfer error clear" "0: No effect,1: Clears the corresponding TEIF flag in the.."
bitfld.long 0x0 30. "CHTIF8,CHTIF8: Channel 8 half transfer clear" "0: No effect,1: Clears the corresponding HTIF flag in the.."
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bitfld.long 0x0 29. "CTCIF8,CTCIF8: Channel 8 transfer complete clear" "0: No effect,1: Clears the corresponding TCIF flag in the.."
bitfld.long 0x0 28. "CGIF8,CGIF8: Channel 8 global interrupt clear" "0: No effect,1: Clears the GIF"
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bitfld.long 0x0 27. "CTEIF7,CTEIF7: Channel 7 transfer error clear" "0: No effect,1: Clears the corresponding TEIF flag in the.."
bitfld.long 0x0 26. "CHTIF7,CHTIF7: Channel 7 half transfer clear" "0: No effect,1: Clears the corresponding HTIF flag in the.."
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bitfld.long 0x0 25. "CTCIF7,CTCIF7: Channel 7 transfer complete clear" "0: No effect,1: Clears the corresponding TCIF flag in the.."
bitfld.long 0x0 24. "CGIF7,CGIF7: Channel 7 global interrupt clear" "0: No effect,1: Clears the GIF"
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bitfld.long 0x0 23. "CTEIF6,CTEIF6: Channel 6 transfer error clear" "0: No effect,1: Clears the corresponding TEIF flag in the.."
bitfld.long 0x0 22. "CHTIF6,CHTIF6: Channel 6 half transfer clear" "0: No effect,1: Clears the corresponding HTIF flag in the.."
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bitfld.long 0x0 21. "CTCIF6,CTCIF6: Channel 6 transfer complete clear" "0: No effect,1: Clears the corresponding TCIF flag in the.."
bitfld.long 0x0 20. "CGIF6,CGIF6: Channel 6 global interrupt clear" "0: No effect,1: Clears the GIF"
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bitfld.long 0x0 19. "CTEIF5,CTEIF5: Channel 5 transfer error clear" "0: No effect,1: Clears the corresponding TEIF flag in the.."
bitfld.long 0x0 18. "CHTIF5,CHTIF5: Channel 5 half transfer clear" "0: No effect,1: Clears the corresponding HTIF flag in the.."
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bitfld.long 0x0 17. "CTCIF5,CTCIF5: Channel 5 transfer complete clear" "0: No effect,1: Clears the corresponding TCIF flag in the.."
bitfld.long 0x0 16. "CGIF5,CGIF5: Channel 5 global interrupt clear" "0: No effect,1: Clears the GIF"
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bitfld.long 0x0 15. "CTEIF4,CTEIF4: Channel 4 transfer error clear" "0: No effect,1: Clears the corresponding TEIF flag in the.."
bitfld.long 0x0 14. "CHTIF4,CHTIF4: Channel 4 half transfer clear" "0: No effect,1: Clears the corresponding HTIF flag in the.."
newline
bitfld.long 0x0 13. "CTCIF4,CTCIF4: Channel 4 transfer complete clear" "0: No effect,1: Clears the corresponding TCIF flag in the.."
bitfld.long 0x0 12. "CGIF4,CGIF4: Channel 4 global interrupt clear" "0: No effect,1: Clears the GIF"
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bitfld.long 0x0 11. "CTEIF3,CTEIF3: Channel 3 transfer error clear" "0: No effect,1: Clears the corresponding TEIF flag in the.."
bitfld.long 0x0 10. "CHTIF3,CHTIF3: Channel 3 half transfer clear" "0: No effect,1: Clears the corresponding HTIF flag in the.."
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bitfld.long 0x0 9. "CTCIF3,CTCIF3: Channel 3 transfer complete clear" "0: No effect,1: Clears the corresponding TCIF flag in the.."
bitfld.long 0x0 8. "CGIF3,CGIF3: Channel 3 global interrupt clear" "0: No effect,1: Clears the GIF"
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bitfld.long 0x0 7. "CTEIF2,CTEIF2: Channel 2 transfer error clear" "0: No effect,1: Clears the corresponding TEIF flag in the.."
bitfld.long 0x0 6. "CHTIF2,CHTIF2: Channel 2 half transfer clear" "0: No effect,1: Clears the corresponding HTIF flag in the.."
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bitfld.long 0x0 5. "CTCIF2,CTCIF2: Channel 2 transfer complete clear" "0: No effect,1: Clears the corresponding TCIF flag in the.."
bitfld.long 0x0 4. "CGIF2,CGIF2: Channel 2 global interrupt clear" "0: No effect,1: Clears the GIF"
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bitfld.long 0x0 3. "CTEIF1,CTEIF1: Channel 1 transfer error clear" "0: No effect,1: Clears the corresponding TEIF flag in the.."
bitfld.long 0x0 2. "CHTIF1,CHTIF1: Channel 1 half transfer clear" "0: No effect,1: Clears the corresponding HTIF flag in the.."
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bitfld.long 0x0 1. "CTCIF1,CTCIF1: Channel 1 transfer complete clear" "0: No effect,1: Clears the corresponding TCIF flag in the.."
bitfld.long 0x0 0. "CGIF1,CGIF1: Channel 1 global interrupt clear" "0: No effect,1: Clears the GIF"
group.long 0x8++0xF
line.long 0x0 "DMA_CCR1,DMA_CCRx register"
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM: Memory to memory mode" "0: Memory to memory mode disabled,1: Memory to memory mode enabled"
bitfld.long 0x0 12.--13. "PL,PL[1:0]: Channel priority level" "0: Low,1: Medium,?,?"
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bitfld.long 0x0 10.--11. "MSIZE,MSIZE[1:0]: Memory size" "0: 8-bits,1: 16-bits,?,?"
bitfld.long 0x0 8.--9. "PSIZE,PSIZE[1:0]: Peripheral size" "0: 8-bits,1: 16-bits,?,?"
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bitfld.long 0x0 7. "MINC,MINC: Memory increment mode" "0: Memory increment mode disabled,1: Memory increment mode enabled"
bitfld.long 0x0 6. "PINC,PINC: Peripheral increment mode" "0: Peripheral increment mode disabled,1: Peripheral increment mode enabled"
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bitfld.long 0x0 5. "CIRC,CIRC: Circular mode" "0: Circular mode disabled,1: Circular mode enabled"
bitfld.long 0x0 4. "DIR,DIR: Data transfer direction" "0: Read from peripheral,1: Read from memory"
newline
bitfld.long 0x0 3. "TEIE,TEIE: Transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled"
bitfld.long 0x0 2. "HTIE,HTIE: Half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled"
newline
bitfld.long 0x0 1. "TCIE,TCIE: Transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled"
bitfld.long 0x0 0. "EN,EN: Channel enable" "0: Channel disabled,1: Channel enabled"
line.long 0x4 "DMA_CNDTR1,DMA_CNDTRx register"
hexmask.long.word 0x4 0.--15. 1. "NDT,NDT[15:0]: Number of data to transfer"
line.long 0x8 "DMA_CPAR1,DMA_CPARx register"
hexmask.long 0x8 0.--31. 1. "PA,PA[31:0]: Peripheral address"
line.long 0xC "DMA_CMAR1,DMA_CMARx register"
hexmask.long 0xC 0.--31. 1. "MA,MA[31:0]: Memory address"
group.long 0x1C++0xF
line.long 0x0 "DMA_CCR2,DMA_CCRx register"
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM: Memory to memory mode" "0: Memory to memory mode disabled,1: Memory to memory mode enabled"
bitfld.long 0x0 12.--13. "PL,PL[1:0]: Channel priority level" "0: Low,1: Medium,?,?"
newline
bitfld.long 0x0 10.--11. "MSIZE,MSIZE[1:0]: Memory size" "0: 8-bits,1: 16-bits,?,?"
bitfld.long 0x0 8.--9. "PSIZE,PSIZE[1:0]: Peripheral size" "0: 8-bits,1: 16-bits,?,?"
newline
bitfld.long 0x0 7. "MINC,MINC: Memory increment mode" "0: Memory increment mode disabled,1: Memory increment mode enabled"
bitfld.long 0x0 6. "PINC,PINC: Peripheral increment mode" "0: Peripheral increment mode disabled,1: Peripheral increment mode enabled"
newline
bitfld.long 0x0 5. "CIRC,CIRC: Circular mode" "0: Circular mode disabled,1: Circular mode enabled"
bitfld.long 0x0 4. "DIR,DIR: Data transfer direction" "0: Read from peripheral,1: Read from memory"
newline
bitfld.long 0x0 3. "TEIE,TEIE: Transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled"
bitfld.long 0x0 2. "HTIE,HTIE: Half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled"
newline
bitfld.long 0x0 1. "TCIE,TCIE: Transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled"
bitfld.long 0x0 0. "EN,EN: Channel enable" "0: Channel disabled,1: Channel enabled"
line.long 0x4 "DMA_CNDTR2,DMA_CNDTRx register"
hexmask.long.word 0x4 0.--15. 1. "NDT,NDT[15:0]: Number of data to transfer"
line.long 0x8 "DMA_CPAR2,DMA_CPARx register"
hexmask.long 0x8 0.--31. 1. "PA,PA[31:0]: Peripheral address"
line.long 0xC "DMA_CMAR2,DMA_CMARx register"
hexmask.long 0xC 0.--31. 1. "MA,MA[31:0]: Memory address"
group.long 0x30++0xF
line.long 0x0 "DMA_CCR3,DMA_CCRx register"
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM: Memory to memory mode" "0: Memory to memory mode disabled,1: Memory to memory mode enabled"
bitfld.long 0x0 12.--13. "PL,PL[1:0]: Channel priority level" "0: Low,1: Medium,?,?"
newline
bitfld.long 0x0 10.--11. "MSIZE,MSIZE[1:0]: Memory size" "0: 8-bits,1: 16-bits,?,?"
bitfld.long 0x0 8.--9. "PSIZE,PSIZE[1:0]: Peripheral size" "0: 8-bits,1: 16-bits,?,?"
newline
bitfld.long 0x0 7. "MINC,MINC: Memory increment mode" "0: Memory increment mode disabled,1: Memory increment mode enabled"
bitfld.long 0x0 6. "PINC,PINC: Peripheral increment mode" "0: Peripheral increment mode disabled,1: Peripheral increment mode enabled"
newline
bitfld.long 0x0 5. "CIRC,CIRC: Circular mode" "0: Circular mode disabled,1: Circular mode enabled"
bitfld.long 0x0 4. "DIR,DIR: Data transfer direction" "0: Read from peripheral,1: Read from memory"
newline
bitfld.long 0x0 3. "TEIE,TEIE: Transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled"
bitfld.long 0x0 2. "HTIE,HTIE: Half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled"
newline
bitfld.long 0x0 1. "TCIE,TCIE: Transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled"
bitfld.long 0x0 0. "EN,EN: Channel enable" "0: Channel disabled,1: Channel enabled"
line.long 0x4 "DMA_CNDTR3,DMA_CNDTRx register"
hexmask.long.word 0x4 0.--15. 1. "NDT,NDT[15:0]: Number of data to transfer"
line.long 0x8 "DMA_CPAR3,DMA_CPARx register"
hexmask.long 0x8 0.--31. 1. "PA,PA[31:0]: Peripheral address"
line.long 0xC "DMA_CMAR3,DMA_CMARx register"
hexmask.long 0xC 0.--31. 1. "MA,MA[31:0]: Memory address"
group.long 0x44++0xF
line.long 0x0 "DMA_CCR4,DMA_CCRx register"
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM: Memory to memory mode" "0: Memory to memory mode disabled,1: Memory to memory mode enabled"
bitfld.long 0x0 12.--13. "PL,PL[1:0]: Channel priority level" "0: Low,1: Medium,?,?"
newline
bitfld.long 0x0 10.--11. "MSIZE,MSIZE[1:0]: Memory size" "0: 8-bits,1: 16-bits,?,?"
bitfld.long 0x0 8.--9. "PSIZE,PSIZE[1:0]: Peripheral size" "0: 8-bits,1: 16-bits,?,?"
newline
bitfld.long 0x0 7. "MINC,MINC: Memory increment mode" "0: Memory increment mode disabled,1: Memory increment mode enabled"
bitfld.long 0x0 6. "PINC,PINC: Peripheral increment mode" "0: Peripheral increment mode disabled,1: Peripheral increment mode enabled"
newline
bitfld.long 0x0 5. "CIRC,CIRC: Circular mode" "0: Circular mode disabled,1: Circular mode enabled"
bitfld.long 0x0 4. "DIR,DIR: Data transfer direction" "0: Read from peripheral,1: Read from memory"
newline
bitfld.long 0x0 3. "TEIE,TEIE: Transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled"
bitfld.long 0x0 2. "HTIE,HTIE: Half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled"
newline
bitfld.long 0x0 1. "TCIE,TCIE: Transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled"
bitfld.long 0x0 0. "EN,EN: Channel enable" "0: Channel disabled,1: Channel enabled"
line.long 0x4 "DMA_CNDTR4,DMA_CNDTRx register"
hexmask.long.word 0x4 0.--15. 1. "NDT,NDT[15:0]: Number of data to transfer"
line.long 0x8 "DMA_CPAR4,DMA_CPARx register"
hexmask.long 0x8 0.--31. 1. "PA,PA[31:0]: Peripheral address"
line.long 0xC "DMA_CMAR4,DMA_CMARx register"
hexmask.long 0xC 0.--31. 1. "MA,MA[31:0]: Memory address"
group.long 0x58++0xF
line.long 0x0 "DMA_CCR5,DMA_CCRx register"
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM: Memory to memory mode" "0: Memory to memory mode disabled,1: Memory to memory mode enabled"
bitfld.long 0x0 12.--13. "PL,PL[1:0]: Channel priority level" "0: Low,1: Medium,?,?"
newline
bitfld.long 0x0 10.--11. "MSIZE,MSIZE[1:0]: Memory size" "0: 8-bits,1: 16-bits,?,?"
bitfld.long 0x0 8.--9. "PSIZE,PSIZE[1:0]: Peripheral size" "0: 8-bits,1: 16-bits,?,?"
newline
bitfld.long 0x0 7. "MINC,MINC: Memory increment mode" "0: Memory increment mode disabled,1: Memory increment mode enabled"
bitfld.long 0x0 6. "PINC,PINC: Peripheral increment mode" "0: Peripheral increment mode disabled,1: Peripheral increment mode enabled"
newline
bitfld.long 0x0 5. "CIRC,CIRC: Circular mode" "0: Circular mode disabled,1: Circular mode enabled"
bitfld.long 0x0 4. "DIR,DIR: Data transfer direction" "0: Read from peripheral,1: Read from memory"
newline
bitfld.long 0x0 3. "TEIE,TEIE: Transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled"
bitfld.long 0x0 2. "HTIE,HTIE: Half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled"
newline
bitfld.long 0x0 1. "TCIE,TCIE: Transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled"
bitfld.long 0x0 0. "EN,EN: Channel enable" "0: Channel disabled,1: Channel enabled"
line.long 0x4 "DMA_CNDTR5,DMA_CNDTRx register"
hexmask.long.word 0x4 0.--15. 1. "NDT,NDT[15:0]: Number of data to transfer"
line.long 0x8 "DMA_CPAR5,DMA_CPARx register"
hexmask.long 0x8 0.--31. 1. "PA,PA[31:0]: Peripheral address"
line.long 0xC "DMA_CMAR5,DMA_CMARx register"
hexmask.long 0xC 0.--31. 1. "MA,MA[31:0]: Memory address"
group.long 0x6C++0xF
line.long 0x0 "DMA_CCR6,DMA_CCRx register"
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM: Memory to memory mode" "0: Memory to memory mode disabled,1: Memory to memory mode enabled"
bitfld.long 0x0 12.--13. "PL,PL[1:0]: Channel priority level" "0: Low,1: Medium,?,?"
newline
bitfld.long 0x0 10.--11. "MSIZE,MSIZE[1:0]: Memory size" "0: 8-bits,1: 16-bits,?,?"
bitfld.long 0x0 8.--9. "PSIZE,PSIZE[1:0]: Peripheral size" "0: 8-bits,1: 16-bits,?,?"
newline
bitfld.long 0x0 7. "MINC,MINC: Memory increment mode" "0: Memory increment mode disabled,1: Memory increment mode enabled"
bitfld.long 0x0 6. "PINC,PINC: Peripheral increment mode" "0: Peripheral increment mode disabled,1: Peripheral increment mode enabled"
newline
bitfld.long 0x0 5. "CIRC,CIRC: Circular mode" "0: Circular mode disabled,1: Circular mode enabled"
bitfld.long 0x0 4. "DIR,DIR: Data transfer direction" "0: Read from peripheral,1: Read from memory"
newline
bitfld.long 0x0 3. "TEIE,TEIE: Transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled"
bitfld.long 0x0 2. "HTIE,HTIE: Half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled"
newline
bitfld.long 0x0 1. "TCIE,TCIE: Transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled"
bitfld.long 0x0 0. "EN,EN: Channel enable" "0: Channel disabled,1: Channel enabled"
line.long 0x4 "DMA_CNDTR6,DMA_CNDTRx register"
hexmask.long.word 0x4 0.--15. 1. "NDT,NDT[15:0]: Number of data to transfer"
line.long 0x8 "DMA_CPAR6,DMA_CPARx register"
hexmask.long 0x8 0.--31. 1. "PA,PA[31:0]: Peripheral address"
line.long 0xC "DMA_CMAR6,DMA_CMARx register"
hexmask.long 0xC 0.--31. 1. "MA,MA[31:0]: Memory address"
group.long 0x80++0xF
line.long 0x0 "DMA_CCR7,DMA_CCRx register"
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM: Memory to memory mode" "0: Memory to memory mode disabled,1: Memory to memory mode enabled"
bitfld.long 0x0 12.--13. "PL,PL[1:0]: Channel priority level" "0: Low,1: Medium,?,?"
newline
bitfld.long 0x0 10.--11. "MSIZE,MSIZE[1:0]: Memory size" "0: 8-bits,1: 16-bits,?,?"
bitfld.long 0x0 8.--9. "PSIZE,PSIZE[1:0]: Peripheral size" "0: 8-bits,1: 16-bits,?,?"
newline
bitfld.long 0x0 7. "MINC,MINC: Memory increment mode" "0: Memory increment mode disabled,1: Memory increment mode enabled"
bitfld.long 0x0 6. "PINC,PINC: Peripheral increment mode" "0: Peripheral increment mode disabled,1: Peripheral increment mode enabled"
newline
bitfld.long 0x0 5. "CIRC,CIRC: Circular mode" "0: Circular mode disabled,1: Circular mode enabled"
bitfld.long 0x0 4. "DIR,DIR: Data transfer direction" "0: Read from peripheral,1: Read from memory"
newline
bitfld.long 0x0 3. "TEIE,TEIE: Transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled"
bitfld.long 0x0 2. "HTIE,HTIE: Half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled"
newline
bitfld.long 0x0 1. "TCIE,TCIE: Transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled"
bitfld.long 0x0 0. "EN,EN: Channel enable" "0: Channel disabled,1: Channel enabled"
line.long 0x4 "DMA_CNDTR7,DMA_CNDTRx register"
hexmask.long.word 0x4 0.--15. 1. "NDT,NDT[15:0]: Number of data to transfer"
line.long 0x8 "DMA_CPAR7,DMA_CPARx register"
hexmask.long 0x8 0.--31. 1. "PA,PA[31:0]: Peripheral address"
line.long 0xC "DMA_CMAR7,DMA_CMARx register"
hexmask.long 0xC 0.--31. 1. "MA,MA[31:0]: Memory address"
group.long 0x94++0xF
line.long 0x0 "DMA_CCR8,DMA_CCRx register"
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM: Memory to memory mode" "0: Memory to memory mode disabled,1: Memory to memory mode enabled"
bitfld.long 0x0 12.--13. "PL,PL[1:0]: Channel priority level" "0: Low,1: Medium,?,?"
newline
bitfld.long 0x0 10.--11. "MSIZE,MSIZE[1:0]: Memory size" "0: 8-bits,1: 16-bits,?,?"
bitfld.long 0x0 8.--9. "PSIZE,PSIZE[1:0]: Peripheral size" "0: 8-bits,1: 16-bits,?,?"
newline
bitfld.long 0x0 7. "MINC,MINC: Memory increment mode" "0: Memory increment mode disabled,1: Memory increment mode enabled"
bitfld.long 0x0 6. "PINC,PINC: Peripheral increment mode" "0: Peripheral increment mode disabled,1: Peripheral increment mode enabled"
newline
bitfld.long 0x0 5. "CIRC,CIRC: Circular mode" "0: Circular mode disabled,1: Circular mode enabled"
bitfld.long 0x0 4. "DIR,DIR: Data transfer direction" "0: Read from peripheral,1: Read from memory"
newline
bitfld.long 0x0 3. "TEIE,TEIE: Transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled"
bitfld.long 0x0 2. "HTIE,HTIE: Half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled"
newline
bitfld.long 0x0 1. "TCIE,TCIE: Transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled"
bitfld.long 0x0 0. "EN,EN: Channel enable" "0: Channel disabled,1: Channel enabled"
line.long 0x4 "DMA_CNDTR8,DMA_CNDTRx register"
hexmask.long.word 0x4 0.--15. 1. "NDT,NDT[15:0]: Number of data to transfer"
line.long 0x8 "DMA_CPAR8,DMA_CPARx register"
hexmask.long 0x8 0.--31. 1. "PA,PA[31:0]: Peripheral address"
line.long 0xC "DMA_CMAR8,DMA_CMARx register"
hexmask.long 0xC 0.--31. 1. "MA,MA[31:0]: Memory address"
tree.end
tree "DMAMUX (DMA Multiplexer)"
base ad:0x48800000
group.long 0x0++0x1F
line.long 0x0 "C0CR,CxCR register"
hexmask.long.byte 0x0 0.--4. 1. "DMAREQ_ID,DMAREQ_ID[4:0]: DMA REQuest IDentification"
line.long 0x4 "C1CR,CxCR register"
hexmask.long.byte 0x4 0.--4. 1. "DMAREQ_ID,DMAREQ_ID[4:0]: DMA REQuest IDentification"
line.long 0x8 "C2CR,CxCR register"
hexmask.long.byte 0x8 0.--4. 1. "DMAREQ_ID,DMAREQ_ID[4:0]: DMA REQuest IDentification"
line.long 0xC "C3CR,CxCR register"
hexmask.long.byte 0xC 0.--4. 1. "DMAREQ_ID,DMAREQ_ID[4:0]: DMA REQuest IDentification"
line.long 0x10 "C4CR,CxCR register"
hexmask.long.byte 0x10 0.--4. 1. "DMAREQ_ID,DMAREQ_ID[4:0]: DMA REQuest IDentification"
line.long 0x14 "C5CR,CxCR register"
hexmask.long.byte 0x14 0.--4. 1. "DMAREQ_ID,DMAREQ_ID[4:0]: DMA REQuest IDentification"
line.long 0x18 "C6CR,CxCR register"
hexmask.long.byte 0x18 0.--4. 1. "DMAREQ_ID,DMAREQ_ID[4:0]: DMA REQuest IDentification"
line.long 0x1C "C7CR,CxCR register"
hexmask.long.byte 0x1C 0.--4. 1. "DMAREQ_ID,DMAREQ_ID[4:0]: DMA REQuest IDentification"
tree.end
tree "FLASH_CTRL (Flash Controller)"
base ad:0x40001000
group.long 0x0++0x13
line.long 0x0 "COMMAND,COMMAND register"
hexmask.long.byte 0x0 0.--7. 1. "COMMAND,Macro commands for flash operations (may require DATA0...DATA3 to be set):"
line.long 0x4 "CONFIG,CONFIG register"
bitfld.long 0x4 6. "SLEEP_SM,Flash memory power-down mode enable in SLEEP mode" "0: When the device is in Sleep mode,1: When the device is in Sleep mode"
bitfld.long 0x4 4.--5. "WAIT_STATE,Add latency to flash read opeations:" "0: no latency,1: 1 clock cycle latency,?,?"
bitfld.long 0x4 2. "DIS_GROUP_WRITE,Burst write Control:" "0: burst write allowed,1: burst write forbidden"
newline
bitfld.long 0x4 1. "REMAP,CPU access routing (it supersedes PREMAP configuration):" "0: FLASH memory addressed,1: SRAM0 memory addressed"
line.long 0x8 "IRQSTAT,IRQSTAT register"
bitfld.long 0x8 5. "FNREADY_MIS,(1: clear 0: inactive) FNREADY_MIS flag" "0: inactive,1: clear"
bitfld.long 0x8 4. "READOK_MIS,(1: clear 0: inactive) READOK_MIS flag" "0: inactive,1: clear"
bitfld.long 0x8 3. "ILLCMD_MIS,(1: clear 0: inactive) ILLCMD_MIS flag" "0: inactive,1: clear"
newline
bitfld.long 0x8 2. "CMDBUSYERR_MIS,(1: clear 0: inactive) CMDBUSYERR_MIS flag" "0: inactive,1: clear"
bitfld.long 0x8 1. "CMDSTART_MIS,(1: clear 0: inactive) CMDSTART_MIS flag" "0: inactive,1: clear"
bitfld.long 0x8 0. "CMDDONE_MIS,(1: clear 0: inactive) CMDDONE_MIS flag" "0: inactive,1: clear"
line.long 0xC "IRQMASK,IRQMASK register"
bitfld.long 0xC 5. "FNREADYM,(1: mask 0: inactive) FNREADY_MIS mask" "0: inactive,1: mask"
bitfld.long 0xC 4. "READOKM,(1: mask 0: inactive) READOK_MIS mask" "0: inactive,1: mask"
bitfld.long 0xC 3. "ILLCMDM,(1: mask 0: inactive) ILLCMD_MIS mask" "0: inactive,1: mask"
newline
bitfld.long 0xC 2. "CMDBUSYERRM,(1: mask 0: inactive) CMDBUSYERR_MIS mask" "0: inactive,1: mask"
bitfld.long 0xC 1. "CMDSTARTM,(1: mask 0: inactive) CMDSTART_MIS mask" "0: inactive,1: mask"
bitfld.long 0xC 0. "CMDDONEM,(1: mask 0: inactive) CMDDONE_MIS mask" "0: inactive,1: mask"
line.long 0x10 "IRQRAW,IRQRAW register"
bitfld.long 0x10 5. "CMDSLEEPERR_RIS,(1: active 0: inactive) COMMAND issued while flash in sleep-mode (SLM=1)" "0: inactive,1: active"
bitfld.long 0x10 4. "READOK_RIS,(1: active 0: inactive) READ COMMAND completed successfully" "0: inactive,1: active"
bitfld.long 0x10 3. "ILLCMD_RIS,(1: active 0: inactive) Illegal command issued" "0: inactive,1: active"
newline
bitfld.long 0x10 2. "CMDBUSYERR_RIS,(1: active 0: inactive) COMMAND issued while flash busy" "0: inactive,1: active"
bitfld.long 0x10 1. "CMDSTART_RIS,(1: active 0: inactive) COMMAND sequence started" "0: inactive,1: active"
bitfld.long 0x10 0. "CMDDONE_RIS,(1: active 0: inactive) COMMAND sequence ended" "0: inactive,1: active"
rgroup.long 0x14++0x3
line.long 0x0 "SIZE,SIZE register"
bitfld.long 0x0 21.--22. "PACKAGE_SIZE,Package selection:" "0,1,2,3"
bitfld.long 0x0 20. "JTAG_DISABLE,Flash+JTAG protection (0: no JTAG protection - see FLASH_SECURE 1: Flash and JTAG protected)" "0: no JTAG protection,1: Flash and JTAG protected"
bitfld.long 0x0 19. "FLASH_SECURE,Flash memory protection (0: no key present 1: key present)" "0: no key present,1: key present"
newline
bitfld.long 0x0 17. "RAM_SIZE,RAM memory size selection:" "0: 16kb,1: 32kb"
hexmask.long.tbyte 0x0 0.--16. 1. "FLASH_SIZE,Maximum valid address for flash memory:"
group.long 0x18++0x3
line.long 0x0 "ADDRESS,ADDRESS register"
hexmask.long.word 0x0 6.--15. 1. "XADDR,Flash row address offset to be used with some COMMAND"
hexmask.long.byte 0x0 0.--5. 1. "YADDR,Flash column address offset to be used with some COMMAND"
rgroup.long 0x24++0x3
line.long 0x0 "LFSRVAL,LFSRVAL register"
hexmask.long 0x0 0.--31. 1. "LFSRVAL,Flash read data CRC signature"
group.long 0x34++0x7
line.long 0x0 "PAGEPROT0,PAGEPROT0 register"
hexmask.long.byte 0x0 24.--30. 1. "SEGOFFSET1,Second segment 7-bit page protection offset (first page number in protected segment)"
hexmask.long.byte 0x0 16.--22. 1. "SEGSIZE1,Second segment 7-bit page protection size (number of pages to protect in segment first page included)"
hexmask.long.byte 0x0 8.--14. 1. "SEGOFFSET0,First segment 7-bit page protection offset (first page number in protected segment)"
newline
hexmask.long.byte 0x0 0.--6. 1. "SEGSIZE0,First segment 7-bit page protection size (number of pages to protect in segment first page included)"
line.long 0x4 "PAGEPROT1,PAGEPROT1 register"
hexmask.long.byte 0x4 24.--30. 1. "SEGOFFSET3,Fourth segment 7-bit page protection offset (first page number in protected segment)"
hexmask.long.byte 0x4 16.--22. 1. "SEGSIZE3,Fourth segment 7-bit page protection size (number of pages to protect in segment first page included)"
hexmask.long.byte 0x4 8.--14. 1. "SEGOFFSET2,Third segment 7-bit page protection offset (first page number in protected segment)"
newline
hexmask.long.byte 0x4 0.--6. 1. "SEGSIZE2,Third segment 7-bit page protection size (number of pages to protect in segment first page included)"
group.long 0x40++0x17
line.long 0x0 "DATA0,DATA0 register"
hexmask.long 0x0 0.--31. 1. "DATA0,Value to be used as DATA for any COMMAND of type WRITE and compare value for MASSREAD"
line.long 0x4 "DATA1,DATA1 register"
hexmask.long 0x4 0.--31. 1. "DATA1,Value to be used as DATA for any COMMAND of type WRITE"
line.long 0x8 "DATA2,DATA2 register"
hexmask.long 0x8 0.--31. 1. "DATA2,Value to be used as DATA for any COMMAND of type WRITE"
line.long 0xC "DATA3,DATA3 register"
hexmask.long 0xC 0.--31. 1. "DATA3,Value to be used as DATA for any COMMAND of type WRITE"
line.long 0x10 "UNLOCK012,UNLOCK012 register"
hexmask.long 0x10 0.--31. 1. "UNLOCK012,(NOT TO BE DOCUMENTED) Remove read-write protection from IFR0 IFR1 IFR2 sectors"
line.long 0x14 "UNLOCK3,UNLOCK3 register"
hexmask.long 0x14 0.--31. 1. "UNLOCK3,(NOT TO BE DOCUMENTED) Remove read-write protection from IFR3 sector"
tree.end
tree "GPIO (General-Purpose I/Os)"
base ad:0x0
tree "GPIOA"
base ad:0x48000000
group.long 0x0++0xF
line.long 0x0 "MODER,MODER register"
bitfld.long 0x0 30.--31. "MODE15,MODE15[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 28.--29. "MODE14,MODE14[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "MODE13,MODE13[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 24.--25. "MODE12,MODE12[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "MODE11,MODE11[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 20.--21. "MODE10,MODE10[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "MODE9,MODE9[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 16.--17. "MODE8,MODE8[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "MODE7,MODE7[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,MODE6[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,MODE5[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,MODE4[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "MODE3,MODE3[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,MODE2[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "MODE1,MODE1[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,MODE0[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
line.long 0x4 "OTYPER,OTYPER register"
bitfld.long 0x4 15. "OT15,OT15: Port A configuration bits" "0,1"
bitfld.long 0x4 14. "OT14,OT14: Port A configuration bits" "0,1"
newline
bitfld.long 0x4 13. "OT13,OT13: Port A configuration bits" "0,1"
bitfld.long 0x4 12. "OT12,OT12: Port A configuration bits" "0,1"
newline
bitfld.long 0x4 11. "OT11,OT11: Port A configuration bits" "0,1"
bitfld.long 0x4 10. "OT10,OT10: Port A configuration bits" "0,1"
newline
bitfld.long 0x4 9. "OT9,OT9: Port A configuration bits" "0,1"
bitfld.long 0x4 8. "OT8,OT8: Port A configuration bits" "0,1"
newline
bitfld.long 0x4 7. "OT7,OT7: Port A configuration bits" "0,1"
bitfld.long 0x4 6. "OT6,OT6: Port A configuration bits" "0,1"
newline
bitfld.long 0x4 5. "OT5,OT5: Port A configuration bits" "0,1"
bitfld.long 0x4 4. "OT4,OT4: Port A configuration bits" "0,1"
newline
bitfld.long 0x4 3. "OT3,OT3: Port A configuration bits" "0,1"
bitfld.long 0x4 2. "OT2,OT2: Port A configuration bits" "0,1"
newline
bitfld.long 0x4 1. "OT1,OT1: Port A configuration bits" "0,1"
bitfld.long 0x4 0. "OT0,OT0: Port A configuration bits" "0,1"
line.long 0x8 "OSPEEDR,OSPEEDR register"
bitfld.long 0x8 30.--31. "OSPEED15,OSPEED15[1:0]: Port A configuration bits" "0,1,2,3"
bitfld.long 0x8 28.--29. "OSPEED14,OSPEED14[1:0]: Port A configuration bits" "0,1,2,3"
newline
bitfld.long 0x8 26.--27. "OSPEED13,OSPEED13[1:0]: Port A configuration bits" "0,1,2,3"
bitfld.long 0x8 24.--25. "OSPEED12,OSPEED12[1:0]: Port A configuration bits" "0,1,2,3"
newline
bitfld.long 0x8 22.--23. "OSPEED11,OSPEED11[1:0]: Port A configuration bits" "0,1,2,3"
bitfld.long 0x8 20.--21. "OSPEED10,OSPEED10[1:0]: Port A configuration bits" "0,1,2,3"
newline
bitfld.long 0x8 18.--19. "OSPEED9,OSPEED9[1:0]: Port A configuration bits" "0,1,2,3"
bitfld.long 0x8 16.--17. "OSPEED8,OSPEED8[1:0]: Port A configuration bits" "0,1,2,3"
newline
bitfld.long 0x8 14.--15. "OSPEED7,OSPEED7[1:0]: Port A configuration bits" "0,1,2,3"
bitfld.long 0x8 12.--13. "OSPEED6,OSPEED6[1:0]: Port A configuration bits" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "OSPEED5,OSPEED5[1:0]: Port A configuration bits" "0,1,2,3"
bitfld.long 0x8 8.--9. "OSPEED4,OSPEED4[1:0]: Port A configuration bits" "0,1,2,3"
newline
bitfld.long 0x8 6.--7. "OSPEED3,OSPEED3[1:0]: Port A configuration bits" "0,1,2,3"
bitfld.long 0x8 4.--5. "OSPEED2,OSPEED2[1:0]: Port A configuration bits" "0,1,2,3"
newline
bitfld.long 0x8 2.--3. "OSPEED1,OSPEED1[1:0]: Port A configuration bits" "0,1,2,3"
bitfld.long 0x8 0.--1. "OSPEED0,OSPEED0[1:0]: Port A configuration bits" "0,1,2,3"
line.long 0xC "PUPDR,PUPDR register"
bitfld.long 0xC 30.--31. "PUPD15,PUPD15: Port A configuration bits" "0,1,2,3"
bitfld.long 0xC 28.--29. "PUPD14,PUPD14: Port A configuration bits" "0,1,2,3"
newline
bitfld.long 0xC 26.--27. "PUPD13,PUPD13: Port A configuration bits" "0,1,2,3"
bitfld.long 0xC 24.--25. "PUPD12,PUPD12: Port A configuration bits" "0,1,2,3"
newline
bitfld.long 0xC 22.--23. "PUPD11,PUPD11: Port A configuration bits" "0,1,2,3"
bitfld.long 0xC 20.--21. "PUPD10,PUPD10: Port A configuration bits" "0,1,2,3"
newline
bitfld.long 0xC 18.--19. "PUPD9,PUPD9: Port A configuration bits" "0,1,2,3"
bitfld.long 0xC 16.--17. "PUPD8,PUPD8: Port A configuration bits" "0,1,2,3"
newline
bitfld.long 0xC 14.--15. "PUPD7,PUPD7: Port A configuration bits" "0,1,2,3"
bitfld.long 0xC 12.--13. "PUPD6,PUPD6: Port A configuration bits" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "PUPD5,PUPD5: Port A configuration bits" "0,1,2,3"
bitfld.long 0xC 8.--9. "PUPD4,PUPD4: Port A configuration bits" "0,1,2,3"
newline
bitfld.long 0xC 6.--7. "PUPD3,PUPD3: Port A configuration bits" "0,1,2,3"
bitfld.long 0xC 4.--5. "PUPD2,PUPD2: Port A configuration bits" "0,1,2,3"
newline
bitfld.long 0xC 2.--3. "PUPD1,PUPD1: Port A configuration bits" "0,1,2,3"
bitfld.long 0xC 0.--1. "PUPD0,PUPD0: Port A configuration bits" "0,1,2,3"
rgroup.long 0x10++0x3
line.long 0x0 "IDR,IDR register"
bitfld.long 0x0 15. "ID15,ID15: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 14. "ID14,ID14: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
newline
bitfld.long 0x0 13. "ID13,ID13: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 12. "ID12,ID12: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
newline
bitfld.long 0x0 11. "ID11,ID11: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 10. "ID10,ID10: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
newline
bitfld.long 0x0 9. "ID9,ID9: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 8. "ID8,ID8: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
newline
bitfld.long 0x0 7. "ID7,ID7: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 6. "ID6,ID6: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
newline
bitfld.long 0x0 5. "ID5,ID5: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 4. "ID4,ID4: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
newline
bitfld.long 0x0 3. "ID3,ID3: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 2. "ID2,ID2: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
newline
bitfld.long 0x0 1. "ID1,ID1: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 0. "ID0,ID0: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
group.long 0x14++0x3
line.long 0x0 "ODR,ODR register"
bitfld.long 0x0 15. "OD15,OD15: Port A output data bit" "0,1"
bitfld.long 0x0 14. "OD14,OD14: Port A output data bit" "0,1"
newline
bitfld.long 0x0 13. "OD13,OD13: Port A output data bit" "0,1"
bitfld.long 0x0 12. "OD12,OD12: Port A output data bit" "0,1"
newline
bitfld.long 0x0 11. "OD11,OD11: Port A output data bit" "0,1"
bitfld.long 0x0 10. "OD10,OD10: Port A output data bit" "0,1"
newline
bitfld.long 0x0 9. "OD9,OD9: Port A output data bit" "0,1"
bitfld.long 0x0 8. "OD8,OD8: Port A output data bit" "0,1"
newline
bitfld.long 0x0 7. "OD7,OD7: Port A output data bit" "0,1"
bitfld.long 0x0 6. "OD6,OD6: Port A output data bit" "0,1"
newline
bitfld.long 0x0 5. "OD5,OD5: Port A output data bit" "0,1"
bitfld.long 0x0 4. "OD4,OD4: Port A output data bit" "0,1"
newline
bitfld.long 0x0 3. "OD3,OD3: Port A output data bit" "0,1"
bitfld.long 0x0 2. "OD2,OD2: Port A output data bit" "0,1"
newline
bitfld.long 0x0 1. "OD1,OD1: Port A output data bit" "0,1"
bitfld.long 0x0 0. "OD0,OD0: Port A output data bit" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "BSRR,BSRR register"
bitfld.long 0x0 31. "BR15,BR15: Port A reset bit y" "0,1"
bitfld.long 0x0 30. "BR14,BR14: Port A reset bit y" "0,1"
newline
bitfld.long 0x0 29. "BR13,BR13: Port A reset bit y" "0,1"
bitfld.long 0x0 28. "BR12,BR12: Port A reset bit y" "0,1"
newline
bitfld.long 0x0 27. "BR11,BR11: Port A reset bit y" "0,1"
bitfld.long 0x0 26. "BR10,BR10: Port A reset bit y" "0,1"
newline
bitfld.long 0x0 25. "BR9,BR9: Port A reset bit y" "0,1"
bitfld.long 0x0 24. "BR8,BR8: Port A reset bit y" "0,1"
newline
bitfld.long 0x0 23. "BR7,BR7: Port A reset bit y" "0,1"
bitfld.long 0x0 22. "BR6,BR6: Port A reset bit y" "0,1"
newline
bitfld.long 0x0 21. "BR5,BR5: Port A reset bit y" "0,1"
bitfld.long 0x0 20. "BR4,BR4: Port A reset bit y" "0,1"
newline
bitfld.long 0x0 19. "BR3,BR3: Port A reset bit y" "0,1"
bitfld.long 0x0 18. "BR2,BR2: Port A reset bit y" "0,1"
newline
bitfld.long 0x0 17. "BR1,BR1: Port A reset bit y" "0,1"
bitfld.long 0x0 16. "BR0,BR0: Port A reset bit y" "0,1"
newline
bitfld.long 0x0 15. "BS15,BS15: Port A set bit y" "0,1"
bitfld.long 0x0 14. "BS14,BS14: Port A set bit y" "0,1"
newline
bitfld.long 0x0 13. "BS13,BS13: Port A set bit y" "0,1"
bitfld.long 0x0 12. "BS12,BS12: Port A set bit y" "0,1"
newline
bitfld.long 0x0 11. "BS11,BS11: Port A set bit y" "0,1"
bitfld.long 0x0 10. "BS10,BS10: Port A set bit y" "0,1"
newline
bitfld.long 0x0 9. "BS9,BS9: Port A set bit y" "0,1"
bitfld.long 0x0 8. "BS8,BS8: Port A set bit y" "0,1"
newline
bitfld.long 0x0 7. "BS7,BS7: Port A set bit y" "0,1"
bitfld.long 0x0 6. "BS6,BS6: Port A set bit y" "0,1"
newline
bitfld.long 0x0 5. "BS5,BS5: Port A set bit y" "0,1"
bitfld.long 0x0 4. "BS4,BS4: Port A set bit y" "0,1"
newline
bitfld.long 0x0 3. "BS3,BS3: Port A set bit y" "0,1"
bitfld.long 0x0 2. "BS2,BS2: Port A set bit y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 1. "BS1,BS1: Port A set bit y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 0. "BS0,BS0: Port A set bit y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
group.long 0x1C++0xB
line.long 0x0 "LCKR,LCKR register"
bitfld.long 0x0 16. "LCKK,LCKK: Lock key" "0,1"
bitfld.long 0x0 15. "LCK15,LCK15: Port A lock bit 15" "0,1"
newline
bitfld.long 0x0 14. "LCK14,LCK14: Port A lock bit 14" "0,1"
bitfld.long 0x0 13. "LCK13,LCK13: Port A lock bit 13" "0,1"
newline
bitfld.long 0x0 12. "LCK12,LCK12: Port A lock bit 12" "0,1"
bitfld.long 0x0 11. "LCK11,LCK11: Port A lock bit 11" "0,1"
newline
bitfld.long 0x0 10. "LCK10,LCK10: Port A lock bit 10" "0,1"
bitfld.long 0x0 9. "LCK9,LCK9: Port A lock bit 9" "0,1"
newline
bitfld.long 0x0 8. "LCK8,LCK8: Port A lock bit 8" "0,1"
bitfld.long 0x0 7. "LCK7,LCK7: Port A lock bit 7" "0,1"
newline
bitfld.long 0x0 6. "LCK6,LCK6: Port A lock bit 6" "0,1"
bitfld.long 0x0 5. "LCK5,LCK5: Port A lock bit 5" "0,1"
newline
bitfld.long 0x0 4. "LCK4,LCK4: Port A lock bit 4" "0,1"
bitfld.long 0x0 3. "LCK3,LCK3: Port A lock bit 3" "0,1"
newline
bitfld.long 0x0 2. "LCK2,LCK2: Port A lock bit 2" "0,1"
bitfld.long 0x0 1. "LCK1,LCK1: Port A lock bit 1" "0,1"
newline
bitfld.long 0x0 0. "LCK0,LCK0: Port A lock bit 0" "0,1"
line.long 0x4 "AFRL,AFRL register"
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,y[3:0]: Alternate function selection for port A pin y (y = 0..7)"
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,y[3:0]: Alternate function selection for port A pin y (y = 0..7)"
newline
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,y[3:0]: Alternate function selection for port A pin y (y = 0..7)"
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,y[3:0]: Alternate function selection for port A pin y (y = 0..7)"
newline
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,y[3:0]: Alternate function selection for port A pin y (y = 0..7)"
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,y[3:0]: Alternate function selection for port A pin y (y = 0..7)"
newline
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,y[3:0]: Alternate function selection for port A pin y (y = 0..7)"
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,y[3:0]: Alternate function selection for port A pin y (y = 0..7)"
line.long 0x8 "AFRH,AFRH register"
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,y[3:0]: Alternate function selection for port A pin y (y = 8..15)"
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,y[3:0]: Alternate function selection for port A pin y (y = 8..15)"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,y[3:0]: Alternate function selection for port A pin y (y = 8..15)"
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,y[3:0]: Alternate function selection for port A pin y (y = 8..15)"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,y[3:0]: Alternate function selection for port A pin y (y = 8..15)"
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,y[3:0]: Alternate function selection for port A pin y (y = 8..15)"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,y[3:0]: Alternate function selection for port A pin y (y = 8..15)"
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,y[3:0]: Alternate function selection for port A pin y (y = 8..15)"
wgroup.long 0x28++0x3
line.long 0x0 "BRR,BRR register"
bitfld.long 0x0 15. "BR15,BR15: Port A reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 14. "BR14,BR14: Port A reset bit y (y = 0..15)" "0,1"
newline
bitfld.long 0x0 13. "BR13,BR13: Port A reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 12. "BR12,BR12: Port A reset bit y (y = 0..15)" "0,1"
newline
bitfld.long 0x0 11. "BR11,BR11: Port A reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 10. "BR10,BR10: Port A reset bit y (y = 0..15)" "0,1"
newline
bitfld.long 0x0 9. "BR9,BR9: Port A reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 8. "BR8,BR8: Port A reset bit y (y = 0..15)" "0,1"
newline
bitfld.long 0x0 7. "BR7,BR7: Port A reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 6. "BR6,BR6: Port A reset bit y (y = 0..15)" "0,1"
newline
bitfld.long 0x0 5. "BR5,BR5: Port A reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 4. "BR4,BR4: Port A reset bit y (y = 0..15)" "0,1"
newline
bitfld.long 0x0 3. "BR3,BR3: Port A reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 2. "BR2,BR2: Port A reset bit y (y = 0..15)" "0,1"
newline
bitfld.long 0x0 1. "BR1,BR1: Port A reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 0. "BR0,BR0: Port A reset bit y (y = 0..15)" "0,1"
tree.end
tree "GPIOB"
base ad:0x48100000
group.long 0x0++0xF
line.long 0x0 "MODER,MODER register"
bitfld.long 0x0 30.--31. "MODE15,MODE15[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 28.--29. "MODE14,MODE14[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 26.--27. "MODE13,MODE13[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 24.--25. "MODE12,MODE12[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 22.--23. "MODE11,MODE11[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 20.--21. "MODE10,MODE10[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 18.--19. "MODE9,MODE9[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 16.--17. "MODE8,MODE8[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 14.--15. "MODE7,MODE7[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,MODE6[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,MODE5[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,MODE4[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,MODE3[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,MODE2[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 2.--3. "MODE1,MODE1[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,MODE0[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
line.long 0x4 "OTYPER,OTYPER register"
bitfld.long 0x4 15. "OT15,OT15: Port B configuration bits" "0,1"
bitfld.long 0x4 14. "OT14,OT14: Port B configuration bits" "0,1"
bitfld.long 0x4 13. "OT13,OT13: Port B configuration bits" "0,1"
bitfld.long 0x4 12. "OT12,OT12: Port B configuration bits" "0,1"
bitfld.long 0x4 11. "OT11,OT11: Port B configuration bits" "0,1"
bitfld.long 0x4 10. "OT10,OT10: Port B configuration bits" "0,1"
bitfld.long 0x4 9. "OT9,OT9: Port B configuration bits" "0,1"
bitfld.long 0x4 8. "OT8,OT8: Port B configuration bits" "0,1"
bitfld.long 0x4 7. "OT7,OT7: Port B configuration bits" "0,1"
bitfld.long 0x4 6. "OT6,OT6: Port B configuration bits" "0,1"
newline
bitfld.long 0x4 5. "OT5,OT5: Port B configuration bits" "0,1"
bitfld.long 0x4 4. "OT4,OT4: Port B configuration bits" "0,1"
bitfld.long 0x4 3. "OT3,OT3: Port B configuration bits" "0,1"
bitfld.long 0x4 2. "OT2,OT2: Port B configuration bits" "0,1"
bitfld.long 0x4 1. "OT1,OT1: Port B configuration bits" "0,1"
bitfld.long 0x4 0. "OT0,OT0: Port B configuration bits" "0,1"
line.long 0x8 "OSPEEDR,OSPEEDR register"
bitfld.long 0x8 30.--31. "OSPEED15,OSPEED15[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 28.--29. "OSPEED14,OSPEED14[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 26.--27. "OSPEED13,OSPEED13[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 24.--25. "OSPEED12,OSPEED12[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 22.--23. "OSPEED11,OSPEED11[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 20.--21. "OSPEED10,OSPEED10[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 18.--19. "OSPEED9,OSPEED9[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 16.--17. "OSPEED8,OSPEED8[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 14.--15. "OSPEED7,OSPEED7[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 12.--13. "OSPEED6,OSPEED6[1:0]: Port B configuration bits" "0,1,2,3"
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bitfld.long 0x8 10.--11. "OSPEED5,OSPEED5[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 8.--9. "OSPEED4,OSPEED4[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 6.--7. "OSPEED3,OSPEED3[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 4.--5. "OSPEED2,OSPEED2[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 2.--3. "OSPEED1,OSPEED1[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 0.--1. "OSPEED0,OSPEED0[1:0]: Port B configuration bits" "0,1,2,3"
line.long 0xC "PUPDR,PUPDR register"
bitfld.long 0xC 30.--31. "PUPD15,PUPD15: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 28.--29. "PUPD14,PUPD14: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 26.--27. "PUPD13,PUPD13: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 24.--25. "PUPD12,PUPD12: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 22.--23. "PUPD11,PUPD11: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 20.--21. "PUPD10,PUPD10: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 18.--19. "PUPD9,PUPD9: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 16.--17. "PUPD8,PUPD8: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 14.--15. "PUPD7,PUPD7: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 12.--13. "PUPD6,PUPD6: Port B configuration bits" "0,1,2,3"
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bitfld.long 0xC 10.--11. "PUPD5,PUPD5: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 8.--9. "PUPD4,PUPD4: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 6.--7. "PUPD3,PUPD3: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 4.--5. "PUPD2,PUPD2: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 2.--3. "PUPD1,PUPD1: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 0.--1. "PUPD0,PUPD0: Port B configuration bits" "0,1,2,3"
rgroup.long 0x10++0x3
line.long 0x0 "IDR,IDR register"
bitfld.long 0x0 15. "ID15,ID15: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 14. "ID14,ID14: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 13. "ID13,ID13: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 12. "ID12,ID12: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 11. "ID11,ID11: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 10. "ID10,ID10: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 9. "ID9,ID9: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 8. "ID8,ID8: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 7. "ID7,ID7: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 6. "ID6,ID6: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
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bitfld.long 0x0 5. "ID5,ID5: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 4. "ID4,ID4: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 3. "ID3,ID3: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 2. "ID2,ID2: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 1. "ID1,ID1: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 0. "ID0,ID0: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
group.long 0x14++0x3
line.long 0x0 "ODR,ODR register"
bitfld.long 0x0 15. "OD15,OD15: Port B output data bit" "0,1"
bitfld.long 0x0 14. "OD14,OD14: Port B output data bit" "0,1"
bitfld.long 0x0 13. "OD13,OD13: Port B output data bit" "0,1"
bitfld.long 0x0 12. "OD12,OD12: Port B output data bit" "0,1"
bitfld.long 0x0 11. "OD11,OD11: Port B output data bit" "0,1"
bitfld.long 0x0 10. "OD10,OD10: Port B output data bit" "0,1"
bitfld.long 0x0 9. "OD9,OD9: Port B output data bit" "0,1"
bitfld.long 0x0 8. "OD8,OD8: Port B output data bit" "0,1"
bitfld.long 0x0 7. "OD7,OD7: Port B output data bit" "0,1"
bitfld.long 0x0 6. "OD6,OD6: Port B output data bit" "0,1"
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bitfld.long 0x0 5. "OD5,OD5: Port B output data bit" "0,1"
bitfld.long 0x0 4. "OD4,OD4: Port B output data bit" "0,1"
bitfld.long 0x0 3. "OD3,OD3: Port B output data bit" "0,1"
bitfld.long 0x0 2. "OD2,OD2: Port B output data bit" "0,1"
bitfld.long 0x0 1. "OD1,OD1: Port B output data bit" "0,1"
bitfld.long 0x0 0. "OD0,OD0: Port B output data bit" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "BSRR,BSRR register"
bitfld.long 0x0 31. "BR15,BR15: Port B reset bit y" "0,1"
bitfld.long 0x0 30. "BR14,BR14: Port B reset bit y" "0,1"
bitfld.long 0x0 29. "BR13,BR13: Port B reset bit y" "0,1"
bitfld.long 0x0 28. "BR12,BR12: Port B reset bit y" "0,1"
bitfld.long 0x0 27. "BR11,BR11: Port B reset bit y" "0,1"
bitfld.long 0x0 26. "BR10,BR10: Port B reset bit y" "0,1"
bitfld.long 0x0 25. "BR9,BR9: Port B reset bit y" "0,1"
bitfld.long 0x0 24. "BR8,BR8: Port B reset bit y" "0,1"
bitfld.long 0x0 23. "BR7,BR7: Port B reset bit y" "0,1"
bitfld.long 0x0 22. "BR6,BR6: Port B reset bit y" "0,1"
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bitfld.long 0x0 21. "BR5,BR5: Port B reset bit y" "0,1"
bitfld.long 0x0 20. "BR4,BR4: Port B reset bit y" "0,1"
bitfld.long 0x0 19. "BR3,BR3: Port B reset bit y" "0,1"
bitfld.long 0x0 18. "BR2,BR2: Port B reset bit y" "0,1"
bitfld.long 0x0 17. "BR1,BR1: Port B reset bit y" "0,1"
bitfld.long 0x0 16. "BR0,BR0: Port B reset bit y" "0,1"
bitfld.long 0x0 15. "BS15,BS15: Port B set bit y" "0,1"
bitfld.long 0x0 14. "BS14,BS14: Port B set bit y" "0,1"
bitfld.long 0x0 13. "BS13,BS13: Port B set bit y" "0,1"
bitfld.long 0x0 12. "BS12,BS12: Port B set bit y" "0,1"
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bitfld.long 0x0 11. "BS11,BS11: Port B set bit y" "0,1"
bitfld.long 0x0 10. "BS10,BS10: Port B set bit y" "0,1"
bitfld.long 0x0 9. "BS9,BS9: Port B set bit y" "0,1"
bitfld.long 0x0 8. "BS8,BS8: Port B set bit y" "0,1"
bitfld.long 0x0 7. "BS7,BS7: Port B set bit y" "0,1"
bitfld.long 0x0 6. "BS6,BS6: Port B set bit y" "0,1"
bitfld.long 0x0 5. "BS5,BS5: Port B set bit y" "0,1"
bitfld.long 0x0 4. "BS4,BS4: Port B set bit y" "0,1"
bitfld.long 0x0 3. "BS3,BS3: Port B set bit y" "0,1"
bitfld.long 0x0 2. "BS2,BS2: Port B set bit y" "0,1"
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bitfld.long 0x0 1. "BS1,BS1: Port B set bit y" "0,1"
bitfld.long 0x0 0. "BS0,BS0: Port B set bit y" "0,1"
group.long 0x1C++0xB
line.long 0x0 "LCKR,LCKR register"
bitfld.long 0x0 16. "LCKK,LCKK: Lock key" "0,1"
bitfld.long 0x0 15. "LCK15,LCK15: Port B lock bit 15" "0,1"
bitfld.long 0x0 14. "LCK14,LCK14: Port B lock bit 14" "0,1"
bitfld.long 0x0 13. "LCK13,LCK13: Port B lock bit 13" "0,1"
bitfld.long 0x0 12. "LCK12,LCK12: Port B lock bit 12" "0,1"
bitfld.long 0x0 11. "LCK11,LCK11: Port B lock bit 11" "0,1"
bitfld.long 0x0 10. "LCK10,LCK10: Port B lock bit 10" "0,1"
bitfld.long 0x0 9. "LCK9,LCK9: Port B lock bit 9" "0,1"
bitfld.long 0x0 8. "LCK8,LCK8: Port B lock bit 8" "0,1"
bitfld.long 0x0 7. "LCK7,LCK7: Port B lock bit 7" "0,1"
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bitfld.long 0x0 6. "LCK6,LCK6: Port B lock bit 6" "0,1"
bitfld.long 0x0 5. "LCK5,LCK5: Port B lock bit 5" "0,1"
bitfld.long 0x0 4. "LCK4,LCK4: Port B lock bit 4" "0,1"
bitfld.long 0x0 3. "LCK3,LCK3: Port B lock bit 3" "0,1"
bitfld.long 0x0 2. "LCK2,LCK2: Port B lock bit 2" "0,1"
bitfld.long 0x0 1. "LCK1,LCK1: Port B lock bit 1" "0,1"
bitfld.long 0x0 0. "LCK0,LCK0: Port B lock bit 0" "0,1"
line.long 0x4 "AFRL,AFRL register"
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,y[3:0]: Alternate function selection for Port B pin y (y = 0..7)"
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,y[3:0]: Alternate function selection for Port B pin y (y = 0..7)"
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,y[3:0]: Alternate function selection for Port B pin y (y = 0..7)"
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,y[3:0]: Alternate function selection for Port B pin y (y = 0..7)"
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,y[3:0]: Alternate function selection for Port B pin y (y = 0..7)"
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,y[3:0]: Alternate function selection for Port B pin y (y = 0..7)"
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,y[3:0]: Alternate function selection for Port B pin y (y = 0..7)"
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,y[3:0]: Alternate function selection for Port B pin y (y = 0..7)"
line.long 0x8 "AFRH,AFRH register"
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,y[3:0]: Alternate function selection for Port B pin y (y = 8..15)"
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,y[3:0]: Alternate function selection for Port B pin y (y = 8..15)"
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,y[3:0]: Alternate function selection for Port B pin y (y = 8..15)"
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,y[3:0]: Alternate function selection for Port B pin y (y = 8..15)"
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,y[3:0]: Alternate function selection for Port B pin y (y = 8..15)"
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,y[3:0]: Alternate function selection for Port B pin y (y = 8..15)"
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,y[3:0]: Alternate function selection for Port B pin y (y = 8..15)"
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,y[3:0]: Alternate function selection for Port B pin y (y = 8..15)"
wgroup.long 0x28++0x3
line.long 0x0 "BRR,BRR register"
bitfld.long 0x0 15. "BR15,BR15: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 14. "BR14,BR14: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 13. "BR13,BR13: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 12. "BR12,BR12: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 11. "BR11,BR11: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 10. "BR10,BR10: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 9. "BR9,BR9: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 8. "BR8,BR8: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 7. "BR7,BR7: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 6. "BR6,BR6: Port B reset bit y (y = 0..15)" "0,1"
newline
bitfld.long 0x0 5. "BR5,BR5: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 4. "BR4,BR4: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 3. "BR3,BR3: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 2. "BR2,BR2: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 1. "BR1,BR1: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 0. "BR0,BR0: Port B reset bit y (y = 0..15)" "0,1"
tree.end
tree.end
tree "I2C (Inter-Integrated Circuit)"
base ad:0x0
tree "I2C1"
base ad:0x41000000
group.long 0x0++0x1B
line.long 0x0 "I2C_CR1,I2C_CR1 register"
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: SMBus Alert pin,1: SMBus Alert pin"
newline
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "0: Device default address disabled,1: Device default address enabled"
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0: Host address disabled,1: Host address enabled"
newline
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
newline
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
rbitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
newline
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
newline
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
newline
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt enable" "0: Stop detection,1: Stop detection"
newline
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge,1: Not acknowledge"
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match,1: Address match"
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bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive,1: Receive"
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit,1: Transmit"
newline
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
line.long 0x4 "I2C_CR2,I2C_CR2 register"
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer,1: PEC transmission/reception is requested"
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
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bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
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bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte,1: a NACK is sent after current received byte"
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation,1: Stop generation after current byte transfer"
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bitfld.long 0x4 13. "START,Start generation" "0: No Start generation,1: Restart/Start generation:"
bitfld.long 0x4 12. "HEAD10R,Ten bit (10-bit) address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
newline
bitfld.long 0x4 11. "ADD10,Ten-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer,1: Master requests a read transfer"
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hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address"
line.long 0x8 "I2C_OAR1,I2C_OAR1 register"
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled,1: Own address 1 enabled"
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address,1: Own address 1 is a 10-bit address"
newline
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address"
line.long 0xC "I2C_OAR2,I2C_OAR2 register"
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and dont care,?,?,?,?,?,?"
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hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
line.long 0x10 "I2C_TIMING,I2C_TIMING register"
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
newline
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
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hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
line.long 0x14 "I2C_TIMEOUT,I2C_TIMEOUT register"
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled"
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
newline
bitfld.long 0x14 15. "TIMEOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
newline
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
line.long 0x18 "I2C_ISR,I2C_ISR register"
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer,1: Read transfer"
newline
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
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rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag" "0,1"
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
newline
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
newline
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
newline
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
newline
rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1"
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
newline
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
newline
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
wgroup.long 0x1C++0x3
line.long 0x0 "I2C_ICR,I2C_ICR register"
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
newline
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
newline
bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear" "0,1"
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
newline
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
newline
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
rgroup.long 0x20++0x7
line.long 0x0 "I2C_PEC,I2C_PEC register"
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
line.long 0x4 "I2C_RXDR,I2C_RXDR register"
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Eight bit (8-bit) receive data"
group.long 0x28++0x3
line.long 0x0 "I2C_TXDR,I2C_TXDR register"
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Eight bits (8-bit) transmit data"
tree.end
tree "I2C2"
base ad:0x41001000
group.long 0x0++0x1B
line.long 0x0 "I2C_CR1,I2C_CR1 register"
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: SMBus Alert pin,1: SMBus Alert pin"
newline
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "0: Device default address disabled,1: Device default address enabled"
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0: Host address disabled,1: Host address enabled"
newline
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled,1: General call enabled"
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
newline
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
rbitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
newline
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
newline
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
newline
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt enable" "0: Stop detection,1: Stop detection"
newline
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge,1: Not acknowledge"
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match,1: Address match"
newline
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive,1: Receive"
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit,1: Transmit"
newline
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
line.long 0x4 "I2C_CR2,I2C_CR2 register"
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer,1: PEC transmission/reception is requested"
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
newline
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
newline
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte,1: a NACK is sent after current received byte"
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation,1: Stop generation after current byte transfer"
newline
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation,1: Restart/Start generation:"
bitfld.long 0x4 12. "HEAD10R,Ten bit (10-bit) address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
newline
bitfld.long 0x4 11. "ADD10,Ten-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer,1: Master requests a read transfer"
newline
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address"
line.long 0x8 "I2C_OAR1,I2C_OAR1 register"
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled,1: Own address 1 enabled"
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address,1: Own address 1 is a 10-bit address"
newline
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address"
line.long 0xC "I2C_OAR2,I2C_OAR2 register"
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled,1: Own address 2 enabled"
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and dont care,?,?,?,?,?,?"
newline
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
line.long 0x10 "I2C_TIMING,I2C_TIMING register"
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
newline
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
newline
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
line.long 0x14 "I2C_TIMEOUT,I2C_TIMEOUT register"
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled"
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
newline
bitfld.long 0x14 15. "TIMEOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
newline
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
line.long 0x18 "I2C_ISR,I2C_ISR register"
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer,1: Read transfer"
newline
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
newline
rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag" "0,1"
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
newline
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
newline
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
newline
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
newline
rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1"
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
newline
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
newline
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
wgroup.long 0x1C++0x3
line.long 0x0 "I2C_ICR,I2C_ICR register"
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
newline
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
newline
bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear" "0,1"
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
newline
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
newline
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
rgroup.long 0x20++0x7
line.long 0x0 "I2C_PEC,I2C_PEC register"
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
line.long 0x4 "I2C_RXDR,I2C_RXDR register"
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Eight bit (8-bit) receive data"
group.long 0x28++0x3
line.long 0x0 "I2C_TXDR,I2C_TXDR register"
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Eight bits (8-bit) transmit data"
tree.end
tree.end
tree "IWDG (Independent Watchdog)"
base ad:0x40003000
wgroup.long 0x0++0x3
line.long 0x0 "IWDG_KR,IWDG_KR register"
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value."
group.long 0x4++0x7
line.long 0x0 "IWDG_PR,IWDG_PR register"
bitfld.long 0x0 0.--2. "PR,Prescaler divider." "0: divider/4,1: divider/8,?,?,?,?,?,?"
line.long 0x4 "IWDG_RLR,IWDG_RLR register"
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value."
rgroup.long 0xC++0x3
line.long 0x0 "IWDG_SR,IWDG_SR register"
bitfld.long 0x0 2. "WVU,Watchdog counter window value update." "0,1"
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update." "0,1"
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update." "0,1"
group.long 0x10++0x3
line.long 0x0 "IWDG_WINR,IWDG_WINR register"
hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value."
tree.end
tree "LCD (Liquid Crystal Display Controller)"
base ad:0x40007000
group.long 0x0++0x7
line.long 0x0 "LCD_CR,LCD_CR register"
bitfld.long 0x0 8. "BUFEN,Voltage output buffer enable" "0,1"
bitfld.long 0x0 5.--6. "BIAS,Bias selector" "0,1,2,3"
bitfld.long 0x0 2.--4. "DUTY,Duty selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 1. "VSEL,Voltage source selection" "0,1"
bitfld.long 0x0 0. "LCDEN,LCD controller enable" "0,1"
line.long 0x4 "LCD_FCR,LCD_FCR register"
hexmask.long.byte 0x4 22.--25. 1. "PS,PS 16-bit prescaler"
hexmask.long.byte 0x4 18.--21. 1. "DIV,DIV clock divider"
bitfld.long 0x4 16.--17. "BLINK,Blink mode selection" "0,1,2,3"
bitfld.long 0x4 13.--15. "BLINKF,Blink frequency selection" "0: fLCD/8,?,?,?,?,?,?,?"
bitfld.long 0x4 10.--12. "CC,Contrast control" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 7.--9. "DEAD,Dead time duration" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 4.--6. "PON,Pulse ON duration" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 3. "UDDIE,Update display done interrupt enable" "0,1"
bitfld.long 0x4 1. "SOFIE,Start of frame interrupt enable" "0,1"
bitfld.long 0x4 0. "HD,High drive enable" "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "LCD_SR,LCD_SR register"
bitfld.long 0x0 5. "FCRSF,LCD Frame Control Register Synchronization flag" "0,1"
bitfld.long 0x0 4. "RDY,Ready flag" "0,1"
bitfld.long 0x0 3. "UDD,Update Display Done" "0,1"
bitfld.long 0x0 2. "UDR,Update display request" "0,1"
bitfld.long 0x0 1. "SOF,Start of frame flag" "0,1"
bitfld.long 0x0 0. "ENS,LCD enabled status" "0,1"
wgroup.long 0xC++0x3
line.long 0x0 "LCD_CLR,LCD_CLR register"
bitfld.long 0x0 3. "UDDC,Update display done clear" "0,1"
bitfld.long 0x0 1. "SOFC,Start of frame flag clear" "0,1"
group.long 0x14++0x3
line.long 0x0 "LCD_RAM_COM0,LCD_RAM_COMx register"
hexmask.long.word 0x0 0.--15. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
group.long 0x1C++0x3
line.long 0x0 "LCD_RAM_COM1,LCD_RAM_COMx register"
hexmask.long.word 0x0 0.--15. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
group.long 0x24++0x3
line.long 0x0 "LCD_RAM_COM2,LCD_RAM_COMx register"
hexmask.long.word 0x0 0.--15. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
group.long 0x2C++0x3
line.long 0x0 "LCD_RAM_COM3,LCD_RAM_COMx register"
hexmask.long.word 0x0 0.--15. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
group.long 0x34++0x3
line.long 0x0 "LCD_RAM_COM4,LCD_RAM_COMx register"
hexmask.long.word 0x0 0.--15. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
group.long 0x3C++0x3
line.long 0x0 "LCD_RAM_COM5,LCD_RAM_COMx register"
hexmask.long.word 0x0 0.--15. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
group.long 0x44++0x3
line.long 0x0 "LCD_RAM_COM6,LCD_RAM_COMx register"
hexmask.long.word 0x0 0.--15. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
group.long 0x4C++0x3
line.long 0x0 "LCD_RAM_COM7,LCD_RAM_COMx register"
hexmask.long.word 0x0 0.--15. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
tree.end
tree "LCSC (LC Sensor Controller)"
base ad:0x4000A000
group.long 0x0++0x13
line.long 0x0 "LCSC_CR0,LCSC_CR0 register"
bitfld.long 0x0 24.--26. "TICAP,Inter Capture Time" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 16.--21. 1. "TCAP,Capture Time"
hexmask.long.word 0x0 0.--13. 1. "TMEAS,Measurement Time"
line.long 0x4 "LCSC_CR1,LCSC_CR1 register"
hexmask.long.word 0x4 20.--30. 1. "TSTART_VCM,VCMBUFF Starting Time"
hexmask.long.word 0x4 10.--18. 1. "TREC_VCM,VCMBUFF Recovery Time"
hexmask.long.byte 0x4 0.--7. 1. "LCAB_DAMP_THRES,LCAB_DAMP_THRES[7:0]: Damping threshold for LCA and LCB"
line.long 0x8 "LCSC_CR2,LCSC_CR2 register"
hexmask.long.byte 0x8 8.--15. 1. "LCT_DAMP_THRES,Damping threshold for LCT"
hexmask.long.byte 0x8 0.--7. 1. "TAMP_PSC,Tamper measurement interval."
line.long 0xC "LCSC_PULSE_CR,LCSC_PULSE_CR register"
hexmask.long.byte 0xC 8.--11. 1. "LCT_PULSE_WIDTH,Low Pulse Width for LCT"
hexmask.long.byte 0xC 0.--3. 1. "LCAB_PULSE_WIDTH,Low Pulse Width for LCA and LCB"
line.long 0x10 "LCSC_ENR,LCSC_ENR register"
bitfld.long 0x10 31. "LCSC_EN,LCSC Enable" "0,1"
bitfld.long 0x10 3. "CNT_OFB_WKP_IE,LCAB Counter Out Of Bound wakeup enable" "0,1"
bitfld.long 0x10 2. "TAMP_IE,Tamper Interrupt and Wakeup Enable" "0,1"
bitfld.long 0x10 1. "ACLKWISE_IE,Anti Clock Wise Interrupt and Wakeup Enable" "0,1"
bitfld.long 0x10 0. "CLKWISE_IE,Clock Wise Interrupt and Wakeup Enable" "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "LCSC_WHEEL_SR,LCSC_WHEEL_SR register"
hexmask.long.word 0x0 16.--31. 1. "ACLKWISE,Number of Anti Clock Wise revolutions"
hexmask.long.word 0x0 0.--15. 1. "CLKWISE,Number of Clock Wise revolutions"
group.long 0x18++0x3
line.long 0x0 "LCSC_CONFR,LCSC_CONFR register"
hexmask.long.word 0x0 16.--31. 1. "ACLKWISE_THRES,Number of Anti Clock Wise revolutions target"
hexmask.long.word 0x0 0.--15. 1. "CLKWISE_THRES,Number of Clock Wise revolutions target"
rgroup.long 0x1C++0x7
line.long 0x0 "LCSC_COMP_CTN,LCSC_COMP_CTN register"
hexmask.long.byte 0x0 20.--27. 1. "CMP_LCT_CNT,LCT Comparator last damping count"
hexmask.long.byte 0x0 10.--17. 1. "CMP_LCB_CNT,LCB Comparator last damping count"
hexmask.long.byte 0x0 0.--7. 1. "CMP_LCA_CNT,LCA Comparator last damping count"
line.long 0x4 "LCSC_SR,LCSC_SR register"
bitfld.long 0x4 4.--5. "LAST_DIR,The last direction detected:" "0,1,2,3"
bitfld.long 0x4 2.--3. "ACLKWISE_STATE,The current state of the LCSC anti clockwise FSM:" "0,1,2,3"
bitfld.long 0x4 0.--1. "CLKWISE_STATE,The current state of the LCSC clockwise FSM:" "0,1,2,3"
group.long 0x24++0xB
line.long 0x0 "LCSC_STAT,LCSC_STAT register"
hexmask.long.byte 0x0 24.--31. 1. "MAX_LCAB_CNT_BOUND,The Maximum bound of CMP_LCA_COUNT "
hexmask.long.byte 0x0 16.--23. 1. "MIN_LCAB_CNT_BOUND,The Minimum bound of CMP_LCA_COUNT "
hexmask.long.byte 0x0 8.--15. 1. "MAX_LCAB_CNT,The Maximum of CMP_LCA_CNT CMP_LCB_CNT reached during"
hexmask.long.byte 0x0 0.--7. 1. "MIN_LCAB_CNT,The Minimum of CMP_LCA_CNT CMP_LCB_CNT reached during the"
line.long 0x4 "LCSC_TST_CFG,LCSC Test Configuration Register"
bitfld.long 0x4 1.--3. "TST_CFG,DTB output selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0. "TST_EN,Test Enable" "0,1"
line.long 0x8 "LCSC_ANATST_CFG,LCSC ANA Test Configuration Register"
bitfld.long 0x8 7. "DAC_PWDN,DAC power-down pin" "0,1"
bitfld.long 0x8 6. "DAC_PWDN_SEL,Selection of the signal to be used to supply the DAC in the LCSC Analog" "0,1"
bitfld.long 0x8 5. "COMP_PWDN,COMP power-down pin" "0,1"
bitfld.long 0x8 4. "COMP_PWDN_SEL,Selection of the signal to be used to supply the COMP in the LCSC" "0,1"
bitfld.long 0x8 3. "VCMBUFF_PWDN,VCMBUFF power-down pin" "0,1"
newline
bitfld.long 0x8 2. "VCMBUFF_PWDN_SEL,Selection of the signal to be used to supply the DAC in the LCSC" "0,1"
bitfld.long 0x8 1. "VCMBUFF_ENOUT,VCMBUFFER output buffer enable pin" "0,1"
bitfld.long 0x8 0. "VCMBUFF_ENOUT_SEL,Selection of the signal to be used to supply the DAC in the LCSC" "0,1"
rgroup.long 0x40++0x3
line.long 0x0 "LCSC_VER,LCSC_VER register"
hexmask.long.byte 0x0 12.--15. 1. "PROD,Used for major upgrades (new protocols support / new features)"
hexmask.long.byte 0x0 8.--11. 1. "VER,Version of the RFIP (to be used for cut upgrades)"
hexmask.long.byte 0x0 4.--7. 1. "REV,Revision of the RFIP to be used for metal fixes)"
group.long 0x44++0x3
line.long 0x0 "LCSC_ISR,LCSC_ISR register"
bitfld.long 0x0 3. "CNT_OFB_F,Out of Bound Counter Flag" "0,1"
bitfld.long 0x0 2. "TAMP_F,Tamper Flag" "0,1"
bitfld.long 0x0 1. "ACLKWISE_F,Anti Clock Wise Flag:" "0,1"
bitfld.long 0x0 0. "CLKWISE_F,Clock Wise Flag:" "0,1"
tree.end
tree "LPAWUR (Low Power Autonomous Wakeup Radio IP)"
base ad:0x49001000
group.long 0x0++0x17
line.long 0x0 "FRAME_CONFIG0,FRAME_CONFIG0 register"
hexmask.long.byte 0x0 21.--25. 1. "SLOW_CLK_CYCLE_PER_BIT_CNT,The number of expected slow clock cycle per each manchester coded bit."
hexmask.long.byte 0x0 16.--19. 1. "PAYLOAD_LENGTH,The number of data Bytes in the payload ( decoded )."
newline
hexmask.long.byte 0x0 10.--15. 1. "SYNC_THRESHOLD_COUNT,detection threshold when receivng the Frame sync ( Manchester encoded)."
bitfld.long 0x0 8. "SYNC_LENGTH,Frame sync pattern length ( Manchester encoded )." "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "PREAMBLE_THRESHOLD_COUNT,The number of transitions for preamble detection when receiving the manchester encoded preamble."
line.long 0x4 "FRAME_CONFIG1,FRAME_CONFIG1 register"
bitfld.long 0x4 18. "TREC_LOOP_ALGO_SEL,Timing recovery loop algorithm selection:" "0,1"
bitfld.long 0x4 17. "PREAMBLE_ENABLE,Preamble detection enable" "0,1"
newline
hexmask.long.byte 0x4 8.--15. 1. "FRAME_SYNC_COUNTER_TIMEOUT,The timeout in manchester encoded bits for the Frame Sync it represents the number of samples after which in case the frame sync is not detected a sync_error is raised."
hexmask.long.byte 0x4 4.--7. 1. "KP,kp gain value for the timing recovery loop."
newline
hexmask.long.byte 0x4 0.--3. 1. "KI,ki gain value for the timing recovery loop."
line.long 0x8 "FRAME_SYNC_CONFIG,FRAME_SYNC_CONFIG register"
hexmask.long.word 0x8 16.--31. 1. "FRAME_SYNC_PATTERN_H,The value of the frame sync pattern High word manchester encoded used only when the frame sync length is 32 bits (default 0x0000 )"
hexmask.long.word 0x8 0.--15. 1. "FRAME_SYNC_PATTERN_L,The value of the frame sync pattern Low word manchester encoded used when the frame sync length is 16 bit (default 0x9696 which represent a frame sync value of 0x99)"
line.long 0xC "RFIP_CONFIG,RFIP_CONFIG register"
bitfld.long 0xC 1.--2. "WAKEUP_LEVEL,- 00: the bit Sync has been detected" "0: the bit Sync has been detected,?,?,?"
bitfld.long 0xC 0. "LPAWUR_ENABLE,Enable (start) or Disable (stop) the LPAWUR feature (0: disabled by default)" "0: disabled by default,?"
line.long 0x10 "RF_CONFIG,RF_CONFIG register"
bitfld.long 0x10 21. "LPF3_CAL" "0,1"
bitfld.long 0x10 18.--20. "ED_ICAL,Current versus VBAT calibration for ED" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x10 14.--17. 1. "AGC_HIGH_LVL,AGC level (High) (default value: 0x4)"
bitfld.long 0x10 13. "ED_DC_CTRL,DC current subtraction enabling signal (default value: 0x1)" "0,1"
newline
bitfld.long 0x10 11.--12. "AGC_LOW_LVL,AGC level (Low) (default value: 0x2)" "0,1,2,3"
hexmask.long.byte 0x10 1.--4. 1. "CLKDIV,Calibrate 4kHz clock (programmable divider)"
newline
bitfld.long 0x10 0. "ED_SWITCH,- 0 : Normal operation (default)" "0: Normal operation,?"
line.long 0x14 "AGC_CONFIG,AGC_CONFIG register"
bitfld.long 0x14 3. "AGC_RESET_MODE,The AGC reset behavior when the AGC is working in ON or HOLD mode" "0,1"
bitfld.long 0x14 2. "AGC_HOLD_MODE,The behavior when the AGC is ON and is working in HOLD mode" "0,1"
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bitfld.long 0x14 0.--1. "AGC_MODE,Define the working mode of the AGC:" "0,1,2,3"
rgroup.long 0x1C++0x7
line.long 0x0 "PAYLOAD_0,PAYLOAD_0 register"
hexmask.long 0x0 0.--31. 1. "PAYLOAD_0,First part of the payload (Least significant Byte First)"
line.long 0x4 "PAYLOAD_1,PAYLOAD_1 register"
hexmask.long 0x4 0.--31. 1. "PAYLOAD_1,Second part of the payload (Least significant Byte First)"
tree.end
tree "LPUART (Low Power Universal Asynchronous Receiver/Transmitter)"
base ad:0x41005000
group.long 0x0++0xF
line.long 0x0 "CR1,CR1 register"
bitfld.long 0x0 31. "RXFFIE,RXFFIE :RXFIFO Full interrupt enable" "0,1"
bitfld.long 0x0 30. "TXFEIE,TXFEIE :TXFIFO empty interrupt enable" "0,1"
bitfld.long 0x0 29. "FIFOEN,FIFOEN :FIFO mode enable" "0,1"
bitfld.long 0x0 28. "M_1,Word length" "0: 1 Start bit,1: 1 Start bit"
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT[4:0]: Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT[4:0]: Driver Enable deassertion time"
bitfld.long 0x0 14. "CMIE,CMIE: Character match interrupt enable" "0,1"
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bitfld.long 0x0 13. "MME,MME: Mute mode enable" "0,1"
bitfld.long 0x0 12. "M_0,M0: Word length" "0,1"
bitfld.long 0x0 11. "WAKE,WAKE: Receiver wakeup method" "0,1"
bitfld.long 0x0 10. "PCE,PCE: Parity control enable" "0,1"
bitfld.long 0x0 9. "PS,PS: Parity selection" "0,1"
bitfld.long 0x0 8. "PEIE,PEIE: PE interrupt enable" "0,1"
bitfld.long 0x0 7. "TXEIE_TXFNFIE,TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable" "0,1"
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bitfld.long 0x0 6. "TCIE,TCIE: Transmission complete interrupt enable" "0,1"
bitfld.long 0x0 5. "RXNEIE_RXFNEIE,RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable" "0,1"
bitfld.long 0x0 4. "IDLEIE,IDLEIE: IDLE interrupt enable" "0,1"
bitfld.long 0x0 3. "TE,TE: Transmitter enable" "0,1"
bitfld.long 0x0 2. "RE,RE: Receiver enable" "0,1"
bitfld.long 0x0 1. "UESM,UESM: LPUART enable in Stop mode" "0,1"
bitfld.long 0x0 0. "UE,UE: USART enable" "0,1"
line.long 0x4 "CR2,CR2 register"
hexmask.long.byte 0x4 24.--31. 1. "ADD,ADD[7:0]: Address of the USART node"
bitfld.long 0x4 19. "MSBFIRST,MSBFIRST: Most significant bit first" "0,1"
bitfld.long 0x4 18. "DATAINV,DATAINV: Binary data inversion" "0: H,1: L"
bitfld.long 0x4 17. "TXINV,TXINV: TX pin active level inversion" "0,1"
bitfld.long 0x4 16. "RXINV,RXINV: RX pin active level inversion" "0,1"
bitfld.long 0x4 15. "SWAP,SWAP: Swap TX/RX pins" "0,1"
bitfld.long 0x4 12.--13. "STOP,STOP[1:0]: STOP bits" "0,1,2,3"
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bitfld.long 0x4 4. "ADDM7,ADDM7:7-bit Address Detection/4-bit Address Detection" "0,1"
line.long 0x8 "CR3,CR3 register"
bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG: TXFIFO threshold configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 28. "RXFTIE,RXFTIE: RXFIFO threshold interrupt enable" "0,1"
bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG: Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 23. "TXFTIE,TXFTIE: TXFIFO threshold interrupt enable" "0,1"
bitfld.long 0x8 22. "WUFIE,WUFIE: Wakeup from Stop mode interrupt enable" "0,1"
bitfld.long 0x8 20.--21. "WUS,WUS[1:0]: Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
bitfld.long 0x8 15. "DEP,DEP: Driver enable polarity selection" "0,1"
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bitfld.long 0x8 14. "DEM,DEM: Driver enable mode" "0,1"
bitfld.long 0x8 13. "DDRE,DDRE: DMA Disable on Reception Error" "0,1"
bitfld.long 0x8 12. "OVRDIS,OVRDIS: Overrun Disable" "0,1"
bitfld.long 0x8 10. "CTSIE,CTSIE: CTS interrupt enable" "0,1"
bitfld.long 0x8 9. "CTSE,CTSE: CTS enable" "0,1"
bitfld.long 0x8 8. "RTSE,RTSE: RTS enable" "0,1"
bitfld.long 0x8 7. "DMAT,DMAT: DMA enable transmitter" "0,1"
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bitfld.long 0x8 6. "DMAR,DMAR: DMA enable receiver" "0,1"
bitfld.long 0x8 3. "HDSEL,HDSEL: Half-duplex selection" "0,1"
bitfld.long 0x8 0. "EIE,EIE: Error interrupt enable" "0,1"
line.long 0xC "BRR,BRR register"
hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR[19:0]"
wgroup.long 0x18++0x3
line.long 0x0 "RQR,RQR register"
bitfld.long 0x0 4. "TXFRQ,TXFRQ: Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFRQ,RXFRQ: Receive data flush request" "0,1"
bitfld.long 0x0 2. "MMRQ,MMRQ: Mute mode request" "0,1"
bitfld.long 0x0 1. "SBKRQ,SBKRQ: Send break request" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "ISR,ISR register"
bitfld.long 0x0 27. "TXFT,TXFT: TXFIFO threshold flag" "0,1"
bitfld.long 0x0 26. "RXFT,RXFT: RXFIFO threshold flag" "0,1"
bitfld.long 0x0 24. "RXFF,RXFF: RXFIFO Full" "0,1"
bitfld.long 0x0 23. "TXFE,TXFE: TXFIFO Empty" "0,1"
bitfld.long 0x0 22. "REACK,REACK: Receive enable acknowledge flag" "0,1"
bitfld.long 0x0 21. "TEACK,TEACK: Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 20. "WUF,WUF: Wakeup from Stop mode flag" "0,1"
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bitfld.long 0x0 19. "RWU,RWU: Receiver wakeup from Mute mode" "0,1"
bitfld.long 0x0 18. "SBKF,SBKF: Send break flag" "0,1"
bitfld.long 0x0 17. "CMF,CMF: Character match flag" "0,1"
bitfld.long 0x0 16. "BUSY,BUSY: Busy flag" "0,1"
bitfld.long 0x0 10. "CTS,CTS: CTS flag" "0,1"
bitfld.long 0x0 9. "CTSIF,CTSIF: CTS interrupt flag" "0,1"
bitfld.long 0x0 7. "TXE_TXFNF,TXE/TXFNF: Transmit data register empty/TXFIFO not full" "0,1"
newline
bitfld.long 0x0 6. "TC,TC: Transmission complete" "0,1"
bitfld.long 0x0 5. "RXNE_RXFNE,RXNE/RXFNE:Read data register not empty/RXFIFO not empty" "0,1"
bitfld.long 0x0 4. "IDLE,IDLE: Idle line detected" "0,1"
bitfld.long 0x0 3. "ORE,ORE: Overrun error" "0,1"
bitfld.long 0x0 2. "NF,NF: START bit Noise detection flag" "0,1"
bitfld.long 0x0 1. "FE,FE: Framing error" "0,1"
bitfld.long 0x0 0. "PE,PE: Parity error" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "ICR,ICR register"
bitfld.long 0x0 20. "WUCF,WUCF: Wakeup from Stop mode clear flag" "0,1"
bitfld.long 0x0 17. "CMCF,CMCF: Character match clear flag" "0,1"
bitfld.long 0x0 9. "CTSCF,CTSCF: CTS clear flag" "0,1"
bitfld.long 0x0 6. "TCCF,TCCF: Transmission complete clear flag" "0,1"
bitfld.long 0x0 4. "IDLECF,IDLECF: Idle line detected clear flag" "0,1"
bitfld.long 0x0 3. "ORECF,ORECF: Overrun error clear flag" "0,1"
bitfld.long 0x0 2. "NECF,NECF: Noise detected clear flag" "0,1"
newline
bitfld.long 0x0 1. "FECF,FECF: Framing error clear flag" "0,1"
bitfld.long 0x0 0. "PECF,PECF: Parity error clear flag" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "RDR,RDR register"
hexmask.long.word 0x0 0.--8. 1. "RDR,RDR[8:0]: Receive data value"
group.long 0x28++0x7
line.long 0x0 "TDR,TDR register"
hexmask.long.word 0x0 0.--8. 1. "TDR,TDR[8:0]: Transmit data value"
line.long 0x4 "PRESC,PRESC register"
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER[3:0]: Clock prescaler"
tree.end
tree "MR_SUBG (Digital Radio IP for Sub-GHz RF)"
base ad:0x49000000
group.long 0x0++0x3B
line.long 0x0 "RF_FSM0_TIMEOUT,RF_FSM0_TIMEOUT register"
hexmask.long.byte 0x0 0.--7. 1. "ENA_RFREG_TIMER,Timeout for the RF regulator startup (duration in ENA_RF_REG state)"
line.long 0x4 "RF_FSM1_TIMEOUT,RF_FSM1_TIMEOUT register"
hexmask.long.byte 0x4 0.--7. 1. "SYNTH_SETUP_TIMER,Timeout management for the RF regulator to stabilize after RF PLL power on"
line.long 0x8 "RF_FSM2_TIMEOUT,RF_FSM2_TIMEOUT register"
hexmask.long.byte 0x8 0.--7. 1. "VCO_CALIB_LOCK_TIMER,Timeout for the RF PLL calibration + RF PLL lock (duration in CALIB_VCO+LOCKRXTX state)"
line.long 0xC "RF_FSM3_TIMEOUT,RF_FSM3_TIMEOUT register"
hexmask.long.byte 0xC 0.--7. 1. "VCO_LOCK_TIMER,Timeout for the RF PLL lock event when no calibration is requested (duration in LOCKRXTX state)"
line.long 0x10 "RF_FSM4_TIMEOUT,RF_FSM4_TIMEOUT register"
hexmask.long.byte 0x10 0.--7. 1. "EN_RX_TIMER,Timeout for the analog RX chain setup (duration in EN_RX state)"
line.long 0x14 "RF_FSM5_TIMEOUT,RF_FSM5_TIMEOUT register"
hexmask.long.byte 0x14 0.--7. 1. "EN_PA_TIMER,Timeout for the analog PA (DAC) setup (duration in EN_PA state)"
line.long 0x18 "RF_FSM6_TIMEOUT,RF_FSM6_TIMEOUT register"
hexmask.long.byte 0x18 0.--7. 1. "PA_DWN_ANA_TIMER,Timeout for the analog PA (DAC) ramp down (duration in PA_DWN_ANA state)"
line.long 0x1C "RF_FSM7_TIMEOUT,RF_FSM7_TIMEOUT register"
hexmask.long.byte 0x1C 0.--7. 1. "EN_LNA_TIMER,Timeout for the analog RX chain signals settlement once PGA precharge is shut down (duration in EN_LNA state)"
line.long 0x20 "AFC0_CONFIG,AFC0_CONFIG register"
hexmask.long.byte 0x20 4.--7. 1. "AFC_FAST_GAIN_LOG2,AFC loop gain in fast mode (2's log)"
hexmask.long.byte 0x20 0.--3. 1. "AFC_SLOW_GAIN_LOG2,AFC loop gain in slow mode (2's log)"
line.long 0x24 "AFC1_CONFIG,AFC1_CONFIG register"
hexmask.long.byte 0x24 0.--7. 1. "AFC_FAST_PERIOD,Length of the AFC fast period (in number of samples unit)"
line.long 0x28 "AFC2_CONFIG,AFC2_CONFIG register"
bitfld.long 0x28 7. "AFC_FREEZE_ON_SYNC,Freeze AFC correction upon SYNC word detection" "0,1"
bitfld.long 0x28 6. "AFC_EN,Enable AFC." "0,1"
bitfld.long 0x28 5. "AFC_MODE,Select AFC mode:" "0,1"
hexmask.long.byte 0x28 0.--4. 1. "AFC_PD_LEAKAGE,AFC Peak Detection leakage."
line.long 0x2C "AFC3_CONFIG,AFC3_CONFIG register"
bitfld.long 0x2C 6.--7. "AFC_REINIT_OPTION,Select the AFC reinitialization option:" "0,1,2,3"
hexmask.long.byte 0x2C 2.--5. 1. "AFC_TH_SIGN_PERM,Threshold of chech sign permanence mechanism."
bitfld.long 0x2C 1. "AFC_SIGN_PERM_CHECK,Enable the check of sign permanence of AFC corrected signal." "0,1"
bitfld.long 0x2C 0. "AFC_INIT_MODE,Control the initialization phase of the AFC and clock recovery algorithms:" "0,1"
line.long 0x30 "CLKREC_CTRL0,CLKREC_CTRL0 register"
bitfld.long 0x30 7. "PSTFLT_LEN,Control the length of the demodulator post-filter" "0,1"
bitfld.long 0x30 4.--6. "CLKREC_P_GAIN_FAST,Clock recovery fast loop gain (log2)" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x30 0.--3. 1. "CLKREC_I_GAIN_FAST,Integral fast gain for the clock recovery loop (PLL mode only)"
line.long 0x34 "CLKREC_CTRL1,CLKREC_CTRL1 register"
bitfld.long 0x34 7. "CLKREC_ALGO_SEL,Symbol timing recovery algorithm selection" "0,1"
bitfld.long 0x34 4.--6. "CLKREC_P_GAIN_SLOW,Clock recovery slow loop gain (log2)" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x34 0.--3. 1. "CLKREC_I_GAIN_SLOW,Integral slow gain for the clock recovery loop (PLL mode only)"
line.long 0x38 "DCREM_CTRL0,DCREM_CTRL0 register"
bitfld.long 0x38 7. "TRACK_GAIN,Filter gain in track mode for the DC removal block." "0,1"
hexmask.long.byte 0x38 0.--4. 1. "START_GAIN,Filter gain in start mode for the DC removal block."
group.long 0x40++0x27
line.long 0x0 "IQC_CTRL0,IQC_CTRL0 register"
hexmask.long.byte 0x0 4.--7. 1. "SLOW_GAIN,Gain of the correction loop in slow mode."
hexmask.long.byte 0x0 0.--3. 1. "FAST_GAIN,Gain of the correction loop in fast mode."
line.long 0x4 "IQC_CTRL1,IQC_CTRL1 register"
hexmask.long.byte 0x4 0.--7. 1. "QPD_ATTACK,Attack coefficient for QPD:"
line.long 0x8 "IQC_CTRL2,IQC_CTRL2 register"
hexmask.long.byte 0x8 0.--7. 1. "QPD_DECAY,Decay coefficient for QPD:"
line.long 0xC "IQC_CTRL3,IQC_CTRL3 register"
hexmask.long.byte 0xC 0.--3. 1. "FAST_TIME,Duration of the fast mode."
line.long 0x10 "AGC_ANA_ENG,AGC_ANA_ENG register"
bitfld.long 0x10 5.--7. "RFD_RX_PGA_AGCGAIN,Attenuation at PGA level by step of 6dB with binary code:" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 1.--4. 1. "RFD_RX_ATTEN_AGCGAIN,Attenuation at LNA level by step of 6dB with thermometric code:"
bitfld.long 0x10 0. "FORCE_AGC_GAINS,Select the mode for AGC analog part:" "0,1"
line.long 0x14 "AGC0_CTRL,AGC0_CTRL register"
bitfld.long 0x14 7. "AGC_EN,Enable the AGC" "0,1"
bitfld.long 0x14 6. "AGC_START_ONHOLD,Start the AGC with a hold phase." "0,1"
hexmask.long.byte 0x14 0.--5. 1. "AGC_HOLD_TIME,AGC hold time."
line.long 0x18 "AGC1_CTRL,AGC1_CTRL register"
hexmask.long.byte 0x18 4.--7. 1. "AGC_MAX_THR,Maximum signal threshold."
hexmask.long.byte 0x18 0.--3. 1. "AGC_MIN_THR,Minimum signal threshold."
line.long 0x1C "AGC2_CTRL,AGC2_CTRL register"
bitfld.long 0x1C 7. "AGC_HIGH_ATTEN_MODE,Enable the high attenuation mode." "0,1"
bitfld.long 0x1C 6. "AGC_FREEZE_ON_STEADY,Enable the autofreeze feature" "0,1"
bitfld.long 0x1C 5. "AGC_FREEZE_ON_SYNC,Enable the freeze on SYNC detection feature" "0,1"
bitfld.long 0x1C 4. "AGC_START_MAX_ATTEN,Start the AGC with maximum attenuation." "0,1"
hexmask.long.byte 0x1C 0.--3. 1. "AGC_MEAS_TIME,Measure time."
line.long 0x20 "AGC3_CTRL,AGC3_CTRL register"
hexmask.long.byte 0x20 4.--7. 1. "AGC_MAX_ATTEN,Maximum AGC attenuation."
hexmask.long.byte 0x20 0.--3. 1. "AGC_MIN_ATTEN,Minimum AGC attenuation."
line.long 0x24 "AGC4_CTRL,AGC4_CTRL register"
hexmask.long.byte 0x24 0.--3. 1. "AGC_FREEZE_THR,Signal threshold for the autofreeze feature."
rgroup.long 0xA0++0x3
line.long 0x0 "AGC_PGA_HWTRIM_OUT,AGC_PGA_HWTRIM_OUT register"
hexmask.long.byte 0x0 0.--3. 1. "AGC_HW_PGA_TRIM,AGC PGA calibration information loaded by HW from the SoC flash."
group.long 0xA8++0x3
line.long 0x0 "PA_REG,PA_REG register"
bitfld.long 0x0 3. "PA_DEGEN_ON,Enable a 'degeneration' mode which introduces a pre-distortion to linearize the power control curve." "0,1"
bitfld.long 0x0 0.--1. "CFG_FILT,FIR configuration:" "0,1,2,3"
rgroup.long 0xAC++0x3
line.long 0x0 "PA_HWTRIM_OUT,PA_HWTRIM_OUT register"
hexmask.long.byte 0x0 4.--7. 1. "PA_HW_DEGEN_TRIM,MSB part meaning:"
group.long 0xBC++0x3
line.long 0x0 "RSSI_FLT,RSSI_FLT register"
hexmask.long.byte 0x0 4.--7. 1. "RSSI_FLT,Gain of the RSSI filter"
hexmask.long.byte 0x0 0.--3. 1. "OOK_PEAK_DECAY,Peak decay control for OOK: 3 slow decay; 0 fast decay"
group.long 0xC8++0x3
line.long 0x0 "SYNTH2_ANA_ENG,SYNTH2_ANA_ENG register"
bitfld.long 0x0 3. "RFD_PLL_LD_WIN_ACC,Select the PLL lock detector window selection:" "0,1"
bitfld.long 0x0 0.--2. "RFD_PLL_VCO_ALC_AMP,Select the level of max VCO amplitude in amplitude level control loop." "0,1,2,3,4,5,6,7"
rgroup.long 0xE8++0x3
line.long 0x0 "RXADC_HWDELAYTRIM_OUT,RXADC_HWDELAYTRIM_OUT register"
bitfld.long 0x0 3.--5. "RXADC_HW_DELAYTRIM_Q,Control bits of the RX ADC loop delay for Q channel (from SoC Flash)." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0.--2. "RXADC_HW_DELAYTRIM_I,Control bits of the RX ADC loop delay for I channel (from SoC Flash)." "0,1,2,3,4,5,6,7"
rgroup.long 0xF4++0x3
line.long 0x0 "RX_AAF_HWTRIM_OUT,RX_AAF_HWTRIM_OUT register"
hexmask.long.byte 0x0 0.--3. 1. "AAF_HW_FCTRIM,AAF calibration information loaded by HW."
group.long 0x100++0x3
line.long 0x0 "SINGEN_ANA_ENG,SINGEN_ANA_ENG register"
bitfld.long 0x0 2. "RFD_SINGEN_LBE,This bit value is directly connected to the RFSUBG analog IP pin." "0,1"
bitfld.long 0x0 1. "RFD_SINGEN_DIV2_PUP,This bit value is directly connected to the RFSUBG analog IP pin." "0,1"
bitfld.long 0x0 0. "RFD_SINGEN_ENA,Enable SINGEN signal for the RFSUBGanalog IP." "0,1"
rgroup.long 0x108++0x3
line.long 0x0 "RF_INFO_OUT,RF_INFO_OUT register"
hexmask.long.byte 0x0 4.--7. 1. "RFSUBG_ID,Indicate the version of the analog RFSUBG IP embedded in the device"
hexmask.long.byte 0x0 0.--3. 1. "FQCY_BAND_ID,FQCY_BAND_ID[3:0]: Indicates the version of the RFSUBG IP embedded in the device"
group.long 0x124++0xB
line.long 0x0 "RF_FSM8_TIMEOUT,RF_FSM8_TIMEOUT register"
hexmask.long.byte 0x0 0.--7. 1. "SYNTH_PDWN_TIMER,Timeout management for the RF regulator to stabilize after PLL shut down"
line.long 0x4 "RF_FSM9_TIMEOUT,RF_FSM9_TIMEOUT register"
hexmask.long.byte 0x4 0.--7. 1. "END_RX_TIMER,Timeout management for the RF regulator to stabilize after analog RX chain shut down"
line.long 0x8 "RF_FSM10_TIMEOUT,RF_FSM10_TIMEOUT register"
hexmask.long.byte 0x8 0.--7. 1. "END_TX_TIMER,Timeout management for the RF regulator to stabilize after clock stops on the analog PA block"
group.long 0x144++0xB
line.long 0x0 "SUBG_DIG_CTRL0,SUBG_DIG_CTRL0 register"
bitfld.long 0x0 0. "FORCE_GPIO_OUTPUT,Option for the direct GPIO signal output" "0,1"
line.long 0x4 "RX_CHAIN_ENG,RX_CHAIN_ENG register"
bitfld.long 0x4 1. "PGA_PRECH_ENA,Option for PGA precharge during the EN_RX state of the Radio FSM:" "0,1"
bitfld.long 0x4 0. "LNA_ISOL_ENA,Option for LNA during the EN_RX state of the Radio FSM:" "0,1"
line.long 0x8 "DEMOD_DIG_ENG,DEMOD_DIG_ENG register"
bitfld.long 0x8 0.--2. "RX_BLANKING_LENGTH,Number of data samples at RX start for which the signal at the output of the channel filter is kept forced to zero:" "0,1,2,3,4,5,6,7"
tree.end
tree "PWRC (Power Controller)"
base ad:0x48500000
group.long 0x0++0x13
line.long 0x0 "CR1,CR1 register"
bitfld.long 0x0 8. "ENBORL,ENBORL: Enable BORL reset supervising during RUN mode." "0: No BORL is monitored during RUN mode,1: BORL is monitored during RUN mode"
newline
bitfld.long 0x0 6.--7. "SELBORH,SELBORH[1:0]: BORH selection of Vbor threshold" "0: BORH Level 1,1: BORH Level 2,?,?"
newline
bitfld.long 0x0 5. "ENBORH,ENBORH: enable BORH configuration" "0: BORH off,1: BORH is enabled"
newline
bitfld.long 0x0 4. "APC,APC Apply Pull-up and pull-down configuration from CPU" "0: the PUCRx and PDCRx are not used to control the..,1: the I/O pull-up and pull-down configurations.."
newline
bitfld.long 0x0 3. "IBIAS_RUN_STATE,IBIAS_RUN_STATE: Enable/Disable IBIAS during RUN mode when automatic mode is" "0: IBIAS control is disabled,1: IBIAS control is enabled"
newline
bitfld.long 0x0 2. "IBIAS_RUN_AUTO,IBIAS_RUN_AUTO: Enable automatic IBIAS control during RUN/DEEPSTOP mode." "0: IBIAS control is manual,1: IBIAS control is automatic"
newline
bitfld.long 0x0 1. "ENSDNBOR,ENSDNBOR: Enable BOR supply monitoring during shutdown mode." "0: the PD_ALL_SHUTDOWN signal is set during..,1: the PD_ALL_SHUTDOWN signal is not set during.."
newline
bitfld.long 0x0 0. "LPMS,LPMS Low Power Mode Selection" "0: Deep Stop mode,1: Shutdown mode"
line.long 0x4 "CR2,CR2 register"
rbitfld.long 0x4 14. "RFREGON_STATUS,RFREGON_STATUS: RF Regulator On Status" "0: RF Regulator is disabled,1: RF Regulator is enabled"
newline
rbitfld.long 0x4 13. "RFREGRDY,RFDREGRDY: RF Regulator Ready flag" "0: RF Regulator is not ready,1: RF Regulator is ready"
newline
bitfld.long 0x4 12. "RFREGBYP,RFREGBYP: RF Regulator Bypass Enable" "0: internally generated 1,1: LDO output connected to VSMPS"
newline
bitfld.long 0x4 11. "RFREGCEXT,RFREGCEXT: RF Regulator External Supply Bypass" "0: Internal supply only,1: External supply bypass capability"
newline
bitfld.long 0x4 10. "RFREGEN,RFREGEN: RF Regulator Enable" "0: Disable RF Regulator,1: Enable RF Regulator"
newline
bitfld.long 0x4 9. "ENTS,ENTS: Enable Temperature Sensor" "0: Temperature sensor is disabled,1: Temperature sensor is enabled"
newline
bitfld.long 0x4 8. "GPIORET,GPIORET: GPIO retention enable." "0: Release GPIO retention after deepstop,1: Enable GPIO Retention during deepstop"
newline
rbitfld.long 0x4 7. "LPREG_VH_STATUS,status LPREG VH (1.2v) during DEEPSTOP" "0: LPREG=1V during DEEPSTOP,1: LPREG=1"
newline
bitfld.long 0x4 6. "LPREG_FORCE_VH,force LPREG=1.2V during DEEPSTOP" "0: No Force,1: Force LPREG=1"
newline
bitfld.long 0x4 5. "RAMRET1,RAMRET1: RAM1 retention during low power mode" "0: RAM1 bank is disabled during low power mode,1: RAM1 bank is powered during low power mode"
newline
bitfld.long 0x4 4. "DBGRET,DBGRET: PA2 and PA3 retention enable after DEEPSTOP" "0: PA2,1: PA2"
newline
bitfld.long 0x4 1.--3. "PVDLS,PVDLS[2:0] Programmable Voltage Detector Level selection" "0: 2,1: 2,?,?,?,?,?,?"
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bitfld.long 0x4 0. "PVDE,PVDE Programmable Voltage Detector Enable" "0,1"
line.long 0x8 "IEWU,IEWU register"
bitfld.long 0x8 10. "EWLPAWUR,EWLPAWUR: Wakeup Bubble Enable" "0: LPAWUR wakeup disabled,1: LPAWUR wakeup enabled"
newline
bitfld.long 0x8 9. "EWMRSUBGHCPU,EWMRSUBGHCPU Wakeup MRSUBG Host CPU Enable" "0: MRSUBG Host CPU wakeup disabled,1: MRSUBG Host CPU wakeup enabled"
newline
bitfld.long 0x8 8. "EWMRSUBG,EWMRSUB Wakeup MRSUBG Enable" "0: MRSUBG wakeup disabled,1: MRSUBG wakeup enabled"
newline
bitfld.long 0x8 4. "EIWL4,EIWL4 Enable Internal Wakeup line LCSC" "0: wakeup disabled,1: wakeup enabled"
newline
bitfld.long 0x8 3. "EIWL3,EIWL3 Enable Internal Wakeup line COMP" "0: wakeup disabled,1: wakeup enabled"
newline
bitfld.long 0x8 2. "EIWL2,EIWL2 Enable Internal WakeUp line LCD" "0: wakeup disabled,1: wakeup enabled"
newline
bitfld.long 0x8 1. "EIWL1,EIWL1 Enable Internal WakeUp line RTC" "0: wakeup disabled,1: wakeup enabled"
newline
bitfld.long 0x8 0. "EIWL0,EWL0 Enable Internal WakeUp line LPUART" "0: wakeup disabled,1: wakeup enabled"
line.long 0xC "IWUP,IWUP register"
bitfld.long 0xC 10. "WLPAWURP,WLPAWURP: Wakeup polarity for wakeup LPAWUR event." "0: Detection of wakeup event on rising edge,1: Detection of wakeup event on falling edge"
newline
bitfld.long 0xC 9. "WMRSUBGHCPUP,WMRSUBGHCPUP: Wakeup polarity for internal wakeup MRSUBG Host CPU event" "0: Detection of wakeup event on rising edge,1: Detection of wakeup event on falling edge"
newline
bitfld.long 0xC 8. "WMRSUBGHP,WMRSUBGHP: Wakeup polarity for internal wakeup MRSUBG event" "0: Detection of wakeup event on rising edge,1: Detection of wakeup event on falling edge"
newline
bitfld.long 0xC 4. "IWUP4,IWUP4: Wakeup polarity for internal wakeup line 4 event (LCSC)." "0: Detection of wakeup event on rising edge,1: Detection of wakeup event on falling edge"
newline
bitfld.long 0xC 3. "IWUP3,IWUP3: Wakeup polarity for internal wakeup line 3 event (COMP)." "0: Detection of wakeup event on rising edge,1: Detection of wakeup event on falling edge"
newline
bitfld.long 0xC 2. "IWUP2,IWUP2: Wakeup polarity for internal wakeup line 2 event (LCD)." "0: Detection of wakeup event on rising edge,1: Detection of wakeup event on falling edge"
newline
bitfld.long 0xC 1. "IWUP1,IWUP1: Wakeup polarity for internal wakeup line 1 event (RTC)." "0: Detection of wakeup event on rising edge,1: Detection of wakeup event on falling edge"
newline
bitfld.long 0xC 0. "IWUP0,IWUP0: Wakeup polarity for internal wakeup line 0 event (LPUART)." "0: Detection of wakeup event on rising edge,1: Detection of wakeup event on falling edge"
line.long 0x10 "IWUF,IWUF register"
bitfld.long 0x10 10. "WLPAWURF,WLPAWURF Wakeup LPAWUR Flag (cf. user manual)" "0: No LPAWUR wakeup detected,1: LPAWUR wakeup detected"
newline
bitfld.long 0x10 9. "WMRSUBGHCPUF,WMRSUBGHCPUF Wakeup MRSUBG HOST CPU Flag (cf. user manual)" "0: No MRSUBG Host CPU wakeup detected,1: MRSUBG Host CPU wakeup detected"
newline
bitfld.long 0x10 8. "WMRSUBGF,WMRSUBGF Wakeup MRSUBG Flag" "0: No MRSUBG Wakeup detected,1: MRSUBG Wakeup detected"
newline
bitfld.long 0x10 4. "IWUF4,IWUF4: Internal wakeup flag (LCSC)." "0: no wakeup from LCSC occurred since last clear,1: a wakeup from LCSC occurred since last clear"
newline
bitfld.long 0x10 3. "IWUF3,IWUF3: Internal wakeup flag (COMP)." "0: no wakeup from COMP occurred since last clear,1: a wakeup from COMP occurred since last clear"
newline
bitfld.long 0x10 2. "IWUF2,IWUF2: Internal wakeup flag (LCD)." "0: no wakeup from LCD occurred since last clear,1: a wakeup from LCD occurred since last clear"
newline
bitfld.long 0x10 1. "IWUF1,IWUF1: Internal wakeup flag (RTC)." "0: no wakeup from RTC occurred since last clear,1: a wakeup from RTC occurred"
newline
bitfld.long 0x10 0. "IWUF0,IWUF0: Internal wakeup flag (LPUART)." "0: no wakeup from LPUART occurred since last clear,1: a wakeup from LPUART occurred since last clear"
rgroup.long 0x14++0x3
line.long 0x0 "SR2,SR2 register"
hexmask.long.byte 0x0 12.--15. 1. "IOBOOTVAL,Bit3: PA11 input value on VDD33 latched at POR"
newline
bitfld.long 0x0 11. "PVDO,PVDO: Power Voltage Detector Output" "0,1"
newline
bitfld.long 0x0 9. "REGMS,REGMS: Main regulator ready status." "0: The Main regulator is not ready,1: The Main regulator is ready"
newline
bitfld.long 0x0 8. "REGLPS,REGLPS: Regulator Low Power Started" "0: LP regulator is not ready,1: LP regulator is ready"
newline
hexmask.long.byte 0x0 4.--7. 1. "IOBOOTVAL2,Bit3: PB15 input value on VDD33 latched at POR"
newline
bitfld.long 0x0 2. "SMPSRDY,SMPSRDY: SMPS Ready Status" "0: SMPS regulator is not ready,1: SMPS regulator is ready"
newline
bitfld.long 0x0 1. "SMPSENR,SMPSENR: SMPS Enable Control Replica" "0,1"
newline
bitfld.long 0x0 0. "SMPSBYPR,SMPSBYPR: SMPS Force Bypass Control Replica" "0,1"
group.long 0x1C++0x1F
line.long 0x0 "CR5,CR5 register"
bitfld.long 0x0 15. "SMPS_BOF_DYN,SMPS_BOF_DYN: SMPS Bypass on the Fly dynamic" "0: disabled,1: SMPS Bypass on the fly dynamic is enabled"
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bitfld.long 0x0 13.--14. "SMPS_PRECH_CUR_SEL,SMPS_PRECH_CUR_SEL[1:0] Selection for SMPS PRECHARGE limit current" "0: 2,1: 5mA,?,?"
newline
bitfld.long 0x0 12. "CLKDETR_DISABLE,CLKDETR_DISABLE: disable SMPS clock detection" "0: SMPS clock detection enabled,1: SMPS clock detection disabled"
newline
bitfld.long 0x0 11. "SMPS_ENA_DCM,SMPS_ENA_DCM: enable discontinuous conduction mode" "0: disable,1: enable"
newline
bitfld.long 0x0 10. "NOSMPS,NOSMPS: No SMPS Mode" "0: No effect,1: SMPS is disabled"
newline
bitfld.long 0x0 9. "SMPSFBYP,SMPSFB Force SMPS Regulator in bypass mode" "0: no effect,1: SMPS is disabled and bypassed"
newline
bitfld.long 0x0 8. "SMPSLPOPEN,SMPSLPOPEN: In Low Power mode SMPS is in OPEN mode (instead of PRECHARGE mode)." "0: in Low Power mode,1: in Low Power mode"
newline
bitfld.long 0x0 7. "NOSMPS_BOF,NOSMPS_BOF: No SMPS Mode to be used in accordance to SMPS_BOF_STATIC =1" "0: No effect,1: SMPS is disabled"
newline
bitfld.long 0x0 6. "SMPS_BOF_STATIC,SMPS_BOF_STATIC: SMPS Bypass on the Fly static" "0: disabled,1: SMPS Bypass on the fly static is enabled"
newline
bitfld.long 0x0 4.--5. "SMPSBOMSEL,SMPSBOMSEL: SMPS BOM Selection:" "0: BOM1,1: BOM2,?,?"
newline
hexmask.long.byte 0x0 0.--3. 1. "SMPSLVL,SMPSLVL[3:0] SMPS Output Level Voltage Selection"
line.long 0x4 "PUCRA,PUCRA register"
hexmask.long.word 0x4 0.--15. 1. "PUA,PUA[x] : Pull Up Port A"
line.long 0x8 "PDCRA,PDCRA register"
hexmask.long.word 0x8 0.--15. 1. "PDA,PDA[x]: Pull Down Port A"
line.long 0xC "PUCRB,PUCRB register"
hexmask.long.word 0xC 0.--15. 1. "PUB,PUB[x] : Pull Up Port B"
line.long 0x10 "PDCRB,PDCRB register"
hexmask.long.word 0x10 0.--15. 1. "PDB,PDB[x]: Pull Down Port B"
line.long 0x14 "EWUA,EWUA register"
hexmask.long.word 0x14 0.--15. 1. "EWUA,EWUA[x] Enable WakeUp line PA[x]"
line.long 0x18 "WUPA,WUPA register"
hexmask.long.word 0x18 0.--15. 1. "WUPA,WUPA[x] Wake-up Line PA[x] Polarity"
line.long 0x1C "WUFA,WUFA register"
hexmask.long.word 0x1C 0.--15. 1. "WUFA,WUFA[x] WakeUp Flag PA[x]"
group.long 0x40++0x1B
line.long 0x0 "EWUB,EWUB register"
hexmask.long.word 0x0 0.--15. 1. "EWUB,EWUB[x] Enable WakeUp line PB[x]"
line.long 0x4 "WUPB,WUPB register"
hexmask.long.word 0x4 0.--15. 1. "WUPB,WUPB[x] Wake-up Line PB[x] Polarity"
line.long 0x8 "WUFB,WUFB register"
hexmask.long.word 0x8 0.--15. 1. "WUFB,WUFB[x] WakeUp Flag PB[x]"
line.long 0xC "SDWN_WUEN,SDWN_WUEN register"
bitfld.long 0xC 0. "WUEN,WUEN PB0 I/O WakeUp from shutdown Enable" "0: PB0 wakeup from shutdown disabled,1: PB0 wakeup from shutdown enabled"
line.long 0x10 "SDWN_WUPOL,SDWN_WUPOL register"
bitfld.long 0x10 0. "WUPOL,WUPOL PB0 I/O WakeUp from shutdown Polarity" "0: Detection on high level,1: Detection on low level"
line.long 0x14 "SDWN_WUF,SDWN_WUF register"
bitfld.long 0x14 0. "WUF,WUF PB0 I/O WakeUp from shutdown Flag" "0: Shutdown wakeup from PB0 not occurred,1: Shutdown wakeup from PB0 occurred"
line.long 0x18 "BOF_TUNE,BOF_TUNE register"
hexmask.long.byte 0x18 0.--3. 1. "BOF_TUNE,BOF_TUNE: selection of the Bypass on the Fly LDO output voltage."
group.long 0x84++0xB
line.long 0x0 "DBGR,DBGR register"
bitfld.long 0x0 13.--15. "DIS_PRECH,DIS_PRECH[2:0]: disable precharge during deepstop (debug)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8.--10. "KELVIN_TEST,KELVIN_TEST[2:0]: Enable TEST mode Kelvin for LDO_RF (Write protected by IFR3 key)" "0: 0mA,?,?,?,?,?,?,?"
newline
bitfld.long 0x0 7. "SMPSFRDY,SMPSFB Force ready check" "0: no effect,1: SMPS is disabled and bypassed"
newline
bitfld.long 0x0 0. "DEEPSTOP2,DEEPSTOP2 low power saving mode emulation enable" "0,1"
line.long 0x4 "EXTSRR,EXTSRR register"
bitfld.long 0x4 10. "RFPHASEF,RFPHASEF RFPHASE Flag" "0: RF IP does not require attention,1: RF IP awake and requesting system attention"
newline
bitfld.long 0x4 9. "DEEPSTOPF,DEEPSTOPF System DeepStop Flag" "0: System has not been in DEEPSTOP mode,1: System has been in DEEPSTOP mode"
line.long 0x8 "DBGSMPS,DBGSMPS register"
bitfld.long 0x8 14.--15. "BOF_CUR_SEL,BOF_CUR_SEL Bypass On the Fly current limitation" "0: 20mA,1: 40mA,?,?"
newline
bitfld.long 0x8 13. "ILIM_BOOST,ILIM_BOOST_3V3 SMPS current limitation Boost" "0: Max current = 110mA,1: Max current = 130mA"
newline
bitfld.long 0x8 12. "DIS_ILIM,DIS_ILIM_3V3 SMPS control signal" "0,1"
newline
bitfld.long 0x8 11. "TEST_OL,TEST_OL_3V3 SMPS control signal" "0,1"
newline
bitfld.long 0x8 10. "DIS_BIG_MOS,DIS_BIG_MOS_3V3 SMPS control signal" "0,1"
newline
bitfld.long 0x8 9. "CTLRES_RAMP,CTLRES_RAM_3V3 SMPS control signal" "0,1"
newline
bitfld.long 0x8 8. "TESTILIM,TESTILIM: SMPS TEST_ILIM_3V3 SMPS control signal" "0,1"
newline
bitfld.long 0x8 7. "NO_STUP,NO_STUP_3V3 SMPS control signal" "0,1"
newline
bitfld.long 0x8 6. "HOT_STUP,HOT_STUP_3V3 SMPS control signal" "0,1"
newline
bitfld.long 0x8 4.--5. "TESTKEL,TESTKEL: SMPS TEST_KEL_3V3[1:0] SMPS control signal" "0,1,2,3"
newline
hexmask.long.byte 0x8 0.--3. 1. "TESTDIG,TESTDIG: SMPS TEST_DIG_3V3[3:0] SMPS control signal"
rgroup.long 0x90++0x3
line.long 0x0 "TRIMR,TRIMR register"
bitfld.long 0x0 11.--13. "BOF_TRIM,BOF_TRIM[2:0]: Bypass On the Fly Output Voltage Trimming" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8.--10. "SMPS_TRIM,SMPS_TRIM[2:0]: SMPS Output Voltage Trimming" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 4.--7. 1. "TRIM_MR,TRIM_MR[3:0]: Main Regulator Voltage Trimming"
newline
bitfld.long 0x0 3. "SPARE" "0,1"
newline
bitfld.long 0x0 0.--2. "RFD_REG_TRIM,RFD_REG_TRIM[2:0]: RF LDO Trimming" "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x0 "ENGTRIM,ENGTRIM register"
bitfld.long 0x0 11.--13. "SMPS_TRIM,SMPS_TRIM: SMPS Output Voltage Trimming" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10. "SMPSTRIMEN,SMPSTRIMEN: trimming SMPS enabled" "0: trimming bit applied from OBL,1: trimming bit applied from ENGTRIM register"
newline
hexmask.long.byte 0x0 6.--9. 1. "TRIM_MR,TRIM_MR: Main Regulator Output Voltage Trimming"
newline
bitfld.long 0x0 5. "TRIMMREN,TRIMMREN: trimming MR enabled" "0: trimming bit applied from OBL,1: trimming bit applied from ENGTRIM register"
newline
bitfld.long 0x0 4. "SPARE" "0,1"
newline
bitfld.long 0x0 1.--3. "TRIM_RFDREG,TRIM_RFDREG: RF Regulator Trimming" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "TRIMRFDREGEN,TRIMRFDREGEN: trimming RFREG enabled" "0: trimming bit applied from OBL,1: trimming bit applied from ENGTRIM register"
rgroup.long 0x98++0x7
line.long 0x0 "DBG_STATUS_REG1,DBG_STATUS_REG1 register"
bitfld.long 0x0 8.--10. "FLASH_FSM_STATE,FLASH_FSM_STATE[2:0]: Indicates the current state of the FLASH FSM inside the PWRC:" "0: STATE1: FLASH POR,1: STATE2: FLASH PWRUP,?,?,?,?,?,?"
newline
bitfld.long 0x0 0.--2. "SMPS_FSM_STATE,SMPS_FSM_STATE[2:0]: Indicates the current state of the SMPS FSM inside the PWRC.:" "0: STARTUP,1: SMPS_REQ,?,?,?,?,?,?"
line.long 0x4 "DBG_STATUS_REG2,DBG_STATUS_REG2 register"
bitfld.long 0x4 8.--9. "RAM_FSM_STATE,RAM_FSM_STATE[1:0]: Indicates the current state of the RAM FSM inside the PWRC:" "0: POR,1: POWER UP,?,?"
newline
hexmask.long.byte 0x4 0.--3. 1. "PMU_FSM_STATE,PMU_FSM_STATE[3:0]: Indicates the current state of the PMU FSM inside the PWRC."
group.long 0xA0++0x3
line.long 0x0 "ENGTRIM2,ENGTRIM2 register"
bitfld.long 0x0 1.--3. "BOF_TRIM,SMPS_TRIM: SMPS Output Voltage Trimming" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "BOFTRIMEN,BOFTRIMEN: trimming BOF enabled" "0: trimming bit applied from OBL,1: trimming bit applied from ENGTRIM2 register"
tree.end
tree "RCC (Reset and Clock Controller)"
base ad:0x48400000
group.long 0x0++0x13
line.long 0x0 "CR,CR register"
rbitfld.long 0x0 17. "HSERDY,External High Speed Clock ready flag." "0: HSE oscillator not ready,1: HSE oscillator ready"
bitfld.long 0x0 16. "HSEON,External High Speed Clock enable." "0: HSE oscillator OFF,1: HSE oscillator ON"
newline
bitfld.long 0x0 15. "FMRAT,Force MRSUBG accurate clock ready status (for debug purpose)" "0: no effect,1: active_transmission is force to '1' whatever the.."
rbitfld.long 0x0 14. "HSIPLLRDY,Internal High Speed Clock PLL ready flag." "0: PLL is unlocked,1: PLL is locked"
newline
bitfld.long 0x0 13. "HSIPLLON,Internal High Speed Clock PLL enable" "0: PLL is OFF,1: PLL is ON"
bitfld.long 0x0 12. "HSEPLLBUFON,External High Speed Clock Buffer for PLL RF enable." "0: HSE PLL Buffer OFF,1: HSE PLL Buffer ON"
newline
rbitfld.long 0x0 10. "HSIRDY,Internal High Speed clock ready flag." "0: internal RC 64 MHz oscillator not ready,1: internal RC 64 MHz oscillator ready"
bitfld.long 0x0 7.--9. "LOCKDET_NSTOP,Lock detector Nstop value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6. "LSEBYP,External Low Speed Clock bypass." "0: LSE oscillator bypass OFF,1: LSE oscillator bypass ON"
rbitfld.long 0x0 5. "LSERDY,External Low Speed Clock ready flag." "0: LSE oscillator not ready,1: LSE oscillator ready"
newline
bitfld.long 0x0 4. "LSEON,External Low Speed Clock enable." "0: LSE oscillator OFF,1: LSE oscillator ON"
rbitfld.long 0x0 3. "LSIRDY,Internal Low Speed oscillator Ready" "0: LSI RC oscillator not ready,1: LSI RC oscillator ready"
newline
bitfld.long 0x0 2. "LSION,Internal Low Speed oscillator enable" "0: LSI RC oscillator OFF,1: LSI RC oscillator ON"
line.long 0x4 "ICSCR,ICSCR register"
hexmask.long.byte 0x4 24.--29. 1. "HSITRIM,High Speed Internal clock trimming."
bitfld.long 0x4 16.--18. "HSITRIMOFFSET,ICSCR[18:16] = HSITRIMOFFSET[2:0]: High Speed oscillator signed trimming offset" "0: 0,1: 1,?,?,?,?,?,?"
newline
hexmask.long.byte 0x4 2.--5. 1. "LSIBW,Trimming in test mode"
rbitfld.long 0x4 1. "LSITRIMOK,LSITRIMOK: Low Speed oscillator trimming OK" "0: LSI Bias trimming,1: LSI Bias trimming"
newline
bitfld.long 0x4 0. "LSITRIMEN,Low Speed oscillator trimming enable" "0: LSI oscillator Bias trimming disabled,1: LSI oscillator Bias trimming enabled"
line.long 0x8 "CFGR,CFGR register"
bitfld.long 0x8 29.--31. "CCOPRE,Configurable Clock Output Prescaler." "0: CCO clock is divided by 1,1: CCO clock is divided by 2,?,?,?,?,?,?"
bitfld.long 0x8 26.--28. "MCOSEL,Main Configurable Clock Output Selection." "0: MCO output disabled,1: system clock selected,?,?,?,?,?,?"
newline
bitfld.long 0x8 24.--25. "LCOSEL,Low speed Configurable Clock Output Selection." "0: LCO output disabled,1: not used,?,?"
bitfld.long 0x8 22.--23. "SPI3I2SCLKSEL,SPI3I2SCLKSEL: Selection of I2S clock for SPI3 IP." "0: 32 MHz peripheral clock,1: 16 MHz peripheral clock,?,?"
newline
bitfld.long 0x8 19. "LCOEN,LCOEN: LCO enable on PA10 also in deepstop." "0: LCO output on PA10 is disabled,1: LCO output on PA10 is enabled"
bitfld.long 0x8 17. "IOBOOSTEN,IOBOOSTEN: IO BOOSTER enable" "0: IO BOOSTER block is disabled,1: IO BOOSTER block is enabled"
newline
bitfld.long 0x8 15.--16. "CLKSLOWSEL,slow clock source selection" "0: '0',1: LSE oscillator clock used as slow clock,?,?"
bitfld.long 0x8 13. "LPUCLKSEL,LPUCLKSEL: Selection of LPUART clock" "0: 16 MHz peripheral clock,1: LSE clock"
newline
bitfld.long 0x8 12. "SMPSDIV,SMPS clock prescaling factor to generate 4MHz or 8MHz" "0: SMPS clock 8MHz,1: SMPS clock 4MHz"
rbitfld.long 0x8 8.--10. "CLKSYSDIV_STATUS,system clock frequency selection status" "0: div1,1: div2,?,?,?,?,?,?"
newline
bitfld.long 0x8 5.--7. "CLKSYSDIV,system clock frequency selection request" "0: div1,1: div2,?,?,?,?,?,?"
rbitfld.long 0x8 3. "HSESEL_STATUS,Clock source selection Status" "0: HSI clock source is selected,1: HSE clock source is selected"
newline
bitfld.long 0x8 2. "STOPHSI,Stop HSI clock source request" "0: HSI is enabled,1: disable HSI is requested"
bitfld.long 0x8 1. "HSESEL,Clock source selection request:" "0: HSI clock source is requested,1: HSE clock source is requested"
line.long 0xC "CSSWCR,CSSWCR register"
hexmask.long.byte 0xC 24.--29. 1. "HSITRIMSW,High Speed Internal clock trimming value to set by SW."
bitfld.long 0xC 23. "HSISWTRIMEN,High Speed oscillator trimming by SW enable" "0: HSI oscillator Bias trimming by SW disabled,1: HSI oscillator Bias trimming by SW enabled"
newline
bitfld.long 0xC 5.--6. "LSEDRV,Maximum Crystal gm for Low Speed External XO" "0: 0,1: 0,?,?"
hexmask.long.byte 0xC 1.--4. 1. "LSISWBW,Low Speed Internal clock trimming value to set by SW"
newline
bitfld.long 0xC 0. "LSISWTRIMEN,Low Speed oscillator trimming by SW enable" "0: LSI oscillator Bias trimming by SW disabled,1: LSI oscillator Bias trimming by SW enabled"
line.long 0x10 "KRMR,KRMR register"
hexmask.long.byte 0x10 1.--5. 1. "KRM,KRM[4:0] :SMPS clock dividing Ratio (CLK_SPMS_KRM frequency= CLK_ROOT frequency"
bitfld.long 0x10 0. "KRM_EN,KRM_EN: Variable rate multiplier Enable" "0: KRM is disabled,1: KRM is enabled"
group.long 0x18++0xB
line.long 0x0 "CIER,CIER register"
bitfld.long 0x0 13. "LCSCRSTIE,LCSCRSTIE: LCSC reset release interrupt enable." "0: LCSC reset release interrupt is disabled,1: LCSC reset release interrupt is enabled"
bitfld.long 0x0 10. "LCDRSTIE,LCDRSTIE: LCD reset end Interrupt Enable." "0: interrupt disabled,1: interrupt enabled"
newline
bitfld.long 0x0 9. "LPURSTIE,LPURSTIE: LPUART reset end Interrupt Enable." "0: interrupt disabled,1: interrupt enabled"
bitfld.long 0x0 8. "WDGRSTIE,WDGRSTIE: Watchdog reset end Interrupt Enable." "0: interrupt disabled,1: interrupt enabled"
newline
bitfld.long 0x0 7. "RTCRSTIE,RTCRSTIE: RTC reset end Interrupt Enable." "0: HSI PLL unlock detection interrupt disabled,1: HSI PLL unlock detection interrupt enabled"
bitfld.long 0x0 6. "HSIPLLUNLOCKDETIE,HSIPLLUNLOCKDETIE: HSI PLL unlock detection Interrupt Enable." "0: HSI PLL unlock detection interrupt disabled,1: HSI PLL unlock detection interrupt enabled"
newline
bitfld.long 0x0 5. "HSIPLLRDYIE,HSI PLL Ready Interrupt Enable." "0: HSI PLL ready interrupt disabled,1: HSI PLL ready interrupt enabled"
bitfld.long 0x0 4. "HSERDYIE,HSE Ready Interrupt Enable" "0: HSE ready interrupt disabled,1: HSE ready interrupt enabled"
newline
bitfld.long 0x0 3. "HSIRDYIE,HSI Ready Interrupt Enable." "0: HSI ready interrupt disabled,1: HSI ready interrupt enabled"
bitfld.long 0x0 1. "LSERDYIE,LSE Ready Interrupt Enable." "0: LSE ready interrupt disabled,1: LSE ready interrupt enabled"
newline
bitfld.long 0x0 0. "LSIRDYIE,LSI Ready Interrupt Enable." "0: LSI ready interrupt disabled,1: LSI ready interrupt enabled"
line.long 0x4 "CIFR,CIFR register"
bitfld.long 0x4 13. "LCSCRSTIF,LCSC reset end Interrupt Flag. Raised when reset is released on 32kHz clock" "0,1"
bitfld.long 0x4 10. "LCDRSTIF,LCD reset end Interrupt Flag. Raised when reset is released on 32kHz clock" "0,1"
newline
bitfld.long 0x4 9. "LPURSTIF,LPUART reset end Interrupt Flag. Raised when reset is released on 32kHz clock" "0,1"
bitfld.long 0x4 8. "WDGRSTIF,WDG reset end Interrupt Flag. Raised when reset is released on 32kHz clock" "0,1"
newline
bitfld.long 0x4 7. "RTCRSTIF,RTC reset end Interrupt Flag. Raised when reset is released on 32kHz clock" "0,1"
bitfld.long 0x4 6. "HSIPLLUNLOCKDETIF,HSIPLLUNLOCKDETIF: HSI PLL unlock detection Interrupt Flag." "0,1"
newline
bitfld.long 0x4 5. "HSIPLLRDYIF,HSI PLL Ready Interrupt Flag." "0: No clock ready interrupt caused by the HSI PLL64..,1: Clock ready interrupt caused by the HSI PLL64.."
bitfld.long 0x4 4. "HSERDYIF,HSE Ready Interrupt Flag." "0: No clock ready interrupt caused by the HSE..,1: Clock ready interrupt caused by the HSE oscillator"
newline
bitfld.long 0x4 3. "HSIRDYIF,HSI Ready Interrupt Flag." "0: No clock ready interrupt caused by the HSI..,1: Clock ready interrupt caused by the HSI oscillator"
bitfld.long 0x4 1. "LSERDYIF,LSE Ready Interrupt Flag." "0: No clock ready interrupt caused by the LSE..,1: Clock ready interrupt caused by the LSE oscillator"
newline
bitfld.long 0x4 0. "LSIRDYIF,LSI Ready Interrupt flag" "0: No clock ready interrupt caused by the internal..,1: Clock ready interrupt caused by the internal RC.."
line.long 0x8 "CSCMDR,CSCMDR register"
bitfld.long 0x8 7. "EOFSEQ_IRQ,End of Sequence flag" "0: No end of sequence event occured,1: End of sequece event occured"
bitfld.long 0x8 6. "EOFSEQ_IE,End of sequence Interrupt Enable." "0: End of sequence interrupt disabled,1: End of sequence interrupt enabled"
newline
rbitfld.long 0x8 4.--5. "STATUS,Status of clock switch sequence" "0: IDLE no switch requested,1: ONGOING clock frequency switch is ongoing,?,?"
bitfld.long 0x8 1.--3. "CLKSYSDIV_REQ,system clock frequency selection request" "0: div1,1: div2,?,?,?,?,?,?"
newline
bitfld.long 0x8 0. "REQUEST,Request for system clock switching" "0: To cancel an ongiong request,1: To update the system clock frequency"
group.long 0x30++0xB
line.long 0x0 "AHBRSTR,AHBRSTR register"
bitfld.long 0x0 20. "AESRST,AES reset" "0: IP is not under reset,1: IP is under reset"
bitfld.long 0x0 18. "RNGRST,RNG reset" "0: IP is not under reset,1: IP is under reset"
newline
bitfld.long 0x0 12. "CRCRST,CRC reset" "0: IP is not under reset,1: IP is under reset"
bitfld.long 0x0 3. "GPIOBRST,GPIOB reset" "0: IP is not under reset,1: IP is under reset"
newline
bitfld.long 0x0 2. "GPIOARST,GPIOA reset" "0: IP is not under reset,1: IP is under reset"
bitfld.long 0x0 0. "DMARST,DMA and DMAMUX reset" "0: IP is not under reset,1: IP is under reset"
line.long 0x4 "APB0RSTR,APB0RSTR register"
bitfld.long 0x4 15. "DBGMCURST,DBGMCURST: DBGMCU reset." "0: DBGMCU IP is not under reset,1: DBGMCU IP is under reset"
bitfld.long 0x4 14. "WDGRST,WDGRST: Watchdog reset." "0: Watchdog IP is not under reset,1: Watchdog IP is under reset"
newline
bitfld.long 0x4 13. "LCSCRST,LCSCRST: LCSC reset." "0: LCSC IP is not under reset,1: LCSC IP is under reset"
bitfld.long 0x4 12. "RTCRST,RTCRST: RTC reset." "0: RTC IP is not under reset,1: RTC IP is under reset"
newline
bitfld.long 0x4 11. "DACRST,DACRST: DAC reset." "0: DAC IP is not under reset,1: DAC IP is under reset"
bitfld.long 0x4 10. "COMPRST,COMPRST: COMP reset." "0: COMP IP is not under reset,1: COMP IP is under reset"
newline
bitfld.long 0x4 9. "LCDCRST,LCDCRST: LCD controller reset." "0: LCD controller IP is not under reset,1: LCD controller IP is under reset"
bitfld.long 0x4 8. "SYSCFGRST,SYSCFGRST: system controller reset." "0: system controller IP is not under reset,1: system controller IP is under reset"
newline
bitfld.long 0x4 1. "TIM16RST,TIM16RST: TIM16 reset." "0: TIM16 IP is not under reset,1: TIM16 IP is under reset"
bitfld.long 0x4 0. "TIM2RST,TIM2RST: TIM2 reset." "0: TIM2 IP is not under reset,1: TIM2 IP is under reset"
line.long 0x8 "APB1RSTR,APB1RSTR register"
bitfld.long 0x8 23. "I2C2RST,I2C2 reset" "0: IP is not under reset,1: IP is under reset"
bitfld.long 0x8 21. "I2C1RST,I2C1 reset" "0: IP is not under reset,1: IP is under reset"
newline
bitfld.long 0x8 14. "SPI3RST,SPI3 reset" "0: IP is not under reset,1: IP is under reset"
bitfld.long 0x8 10. "USARTRST,USART reset" "0: IP is not under reset,1: IP is under reset"
newline
bitfld.long 0x8 8. "LPUARTRST,LPUART reset" "0: IP is not under reset,1: IP is under reset"
bitfld.long 0x8 4. "ADCRST,ADC reset for Aux-ADC IP" "0: IP is not under reset,1: IP is under reset"
newline
bitfld.long 0x8 0. "SPI1RST,SPI1 reset" "0: IP is not under reset,1: IP is under reset"
group.long 0x40++0x3
line.long 0x0 "APB2RSTR,APB2RSTR register"
bitfld.long 0x0 3. "LPAWURRST,Bubble reset" "0: IP is not under reset,1: IP is under reset"
bitfld.long 0x0 0. "MRSUBGRST,Radio MRSUBG reset." "0: IP is not under reset,1: IP is under reset"
group.long 0x50++0xB
line.long 0x0 "AHBENR,AHBENR register"
bitfld.long 0x0 20. "AESEN,AESEN: AES clock enable." "0: AES IP is clock gated,1: AES IP is clocked"
bitfld.long 0x0 18. "RNGEN,RNG clock enable" "0: does not enable,1: enable"
newline
bitfld.long 0x0 12. "CRCEN,CRC enable" "0: does not enable,1: enable"
bitfld.long 0x0 3. "GPIOBEN,GPIOB enable. It must be enabled by default" "0,1"
newline
bitfld.long 0x0 2. "GPIOAEN,GPIOA enable. It must be enabled by default" "0,1"
bitfld.long 0x0 0. "DMAEN,DMA and DMAMUX enable" "0: does not enable,1: enable"
line.long 0x4 "APB0ENR,APB0ENR register"
bitfld.long 0x4 15. "DBGMCUEN,DBG MCU clock enable." "0: clock disable,1: clock enable"
bitfld.long 0x4 14. "WDGEN,Watchdog clock enable." "0: clock disable,1: clock enable"
newline
bitfld.long 0x4 13. "LCSCEN,LCSC clock enable." "0: clock disable,1: clock enable"
bitfld.long 0x4 12. "RTCEN,RTC clock enable" "0: clock disable,1: clock enable"
newline
bitfld.long 0x4 11. "DACEN,DAC clock enable" "0: clock disable,1: clock enable"
bitfld.long 0x4 10. "COMPEN,COMP clock enable" "0: clock disable,1: clock enable"
newline
bitfld.long 0x4 9. "LCDEN,LCD clock enable" "0: clock disable,1: clock enable"
bitfld.long 0x4 8. "SYSCFGEN,SYSTEM CONFIG clock enable" "0: clock disable,1: clock enable"
newline
bitfld.long 0x4 1. "TIM16EN,TIM16: Advanced Timer clock enable" "0: clock disable,1: clock enable"
bitfld.long 0x4 0. "TIM2EN,TIM2: Advanced Timer clock enable" "0: clock disable,1: clock enable"
line.long 0x8 "APB1ENR,APB1ENR register"
bitfld.long 0x8 23. "I2C2EN,I2C2 clock enable" "0: clock disable,1: clock enable"
bitfld.long 0x8 21. "I2C1EN,I2C1 clock enable" "0: clock disable,1: clock enable"
newline
bitfld.long 0x8 14. "SPI3EN,SPI3 clock enable" "0: clock disable,1: clock enable"
bitfld.long 0x8 10. "USARTEN,USART clock enable" "0: clock disable,1: clock enable"
newline
bitfld.long 0x8 8. "LPUARTEN,LPUART clock enable" "0: clock disable,1: clock enable"
bitfld.long 0x8 5. "ADCANAEN,ADC clock enable for Aux-ADC analog clock" "0: clock disable,1: clock enable"
newline
bitfld.long 0x8 4. "ADCDIGEN,AUXADC clock enable for Aux-ADC digital clock" "0: clock disable,1: clock enable"
bitfld.long 0x8 0. "SPI1EN,SPI1 clock enable" "0: clock disable,1: clock enable"
group.long 0x60++0x3
line.long 0x0 "APB2ENR,APB2ENR register"
bitfld.long 0x0 3. "LPAWUREN,Bubble clock enable" "0: clock disable,1: clock enable"
bitfld.long 0x0 0. "MRSUBGEN,MRSUBG clock enable." "0: clock disable,1: clock enable"
group.long 0x80++0x3
line.long 0x0 "DBGR,DBGR register"
bitfld.long 0x0 22. "FORCEXO48MREADY,FORCEXO48MREADY Force XO48M Ready input signal" "0: No effect,1: Force XOREADY=1"
bitfld.long 0x0 21. "DBGXOEXT,used for debug mode with HSE bypassed by FXTAL_IN clock and ZIV12 output used." "0: No effect,1: HSE bypassed by FXTAL_IN clock and ZIV12 output.."
newline
bitfld.long 0x0 20. "DBGBYPHSI,used for debug mode with HSI bypassed by HSE" "0: No effect,1: HSI bypassed HSE"
bitfld.long 0x0 19. "DBGHSIOFF,used for debug or test" "0: No effect,1: HSI forced off"
group.long 0x94++0x7
line.long 0x0 "CSR,CSR register"
rbitfld.long 0x0 30. "LOCKUPRSTF,LOCK UP reset flag from CM0" "0: No lockup reset occurred,1: lockup reset occurred"
rbitfld.long 0x0 29. "WDGRSTF,Watchdog reset flag" "0: No watchdog reset occurred,1: Watchdog reset occurred"
newline
rbitfld.long 0x0 28. "SFTRSTF,Software reset flag" "0: No software reset occurred,1: Software reset occurred"
rbitfld.long 0x0 27. "PORRSTF,POWER reset flag" "0: No POWER reset occurred,1: POWER reset occurred"
newline
rbitfld.long 0x0 26. "PADRSTF,SYSTEM reset flag" "0: No reset from pad occurred,1: Reset from pad occurred"
bitfld.long 0x0 23. "RMVF,Remove reset flag" "0: Nothing done,1: Reset the value of the reset flags"
line.long 0x4 "RFSWHSECR,RFSWHSECR register"
bitfld.long 0x4 16.--18. "AMPLTHRESH,RF-HSE Amplitude Control threshold" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 14.--15. "ISTARTUP,RF-HSE Startup current" "0,1,2,3"
newline
hexmask.long.byte 0x4 8.--13. 1. "SWXOTUNE,RF-HSE capacitor bank tuning value by SW"
bitfld.long 0x4 7. "SWXOTUNEEN,RF-HSE capacitor bank tuning by SW enable" "0,1"
newline
hexmask.long.byte 0x4 0.--6. 1. "GMC,GMC[6:5]: High speed external XO current control reference"
rgroup.long 0x9C++0x3
line.long 0x0 "RFHSECR,RFHSECR register"
bitfld.long 0x0 6. "AMPLREADY,RF-HSE Amplitude Control Ready output" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "XOTUNE,RF-HSE capacitor bank tuning"
group.long 0xA0++0xB
line.long 0x0 "AHBSMENR,AHBSMENR register"
bitfld.long 0x0 20. "AESSMEN,AES bus clock enable during Sleep mode bit" "0: AES bus clock disabled in Sleep mode,1: AES bus clock enabled in Sleep mode"
bitfld.long 0x0 18. "RNGSMEN,RNG bus clock enable during Sleep mode bit" "0: RNG bus clock disabled in Sleep mode,1: RNG bus clock enabled in Sleep mode"
newline
bitfld.long 0x0 12. "CRCSMEN,CRC clock enable during Sleep mode bit" "0: CRC clock disabled in Sleep mode,1: CRC clock enabled in Sleep mode"
bitfld.long 0x0 10. "SRAM1SMEN,SRAM1 clock enable during Sleep mode bit" "0: SRAM1 clock disabled in Sleep mode,1: SRAM1 clock enabled in Sleep mode"
newline
bitfld.long 0x0 9. "SRAM0SMEN,SRAM0 clock enable during Sleep mode bit" "0: SRAM0 clock disabled in Sleep mode,1: SRAM0 clock enabled in Sleep mode"
bitfld.long 0x0 3. "GPIOBSMEN,GPIOB clock enable during Sleep mode bit" "0: GPIOB clock disabled in Sleep mode,1: GPIOB clock enabled in Sleep mode"
newline
bitfld.long 0x0 2. "GPIOASMEN,GPIOA clock enable during Sleep mode bit" "0: GPIOA clock disabled in Sleep mode,1: GPIOA clock enabled in Sleep mode"
bitfld.long 0x0 1. "FLASHSMEN,Flash clocks enable during Flash Sleep PD and CPU Sleep mode bit" "0: Flash clocks are disabled in Flash Sleep PD* and..,1: Flash clocks are enabled in Sleep mode"
newline
bitfld.long 0x0 0. "DMASMEN,DMA clock enable during Sleep mode bit" "0: DMA clock disabled in Sleep mode,1: DMA clock enabled in Sleep mode"
line.long 0x4 "APB0SMENR,APB0SMENR register"
bitfld.long 0x4 15. "DBGMCUSMEN,DBGMCU clock enable during Sleep mode bit" "0: DBGMCU clock disabled in Sleep mode,1: DBGMCU clock enabled in Sleep mode"
bitfld.long 0x4 14. "WDGSMEN,WDG clock enable during Sleep mode bit" "0: WDG clock disabled in Sleep mode,1: WDG clock enabled in Sleep mode"
newline
bitfld.long 0x4 13. "LCSCSMEN,LCSC bus clock enable during Sleep mode bit" "0: LCSC bus clock disabled in Sleep mode,1: LCSC bus clock enabled in Sleep mode"
bitfld.long 0x4 12. "RTCSMEN,RTC bus clock enable during Sleep mode bit" "0: RTC bus clock disabled in Sleep mode,1: RTC bus clock enabled in Sleep mode"
newline
bitfld.long 0x4 11. "DACSMEN,DAC bus clock enable during Sleep mode bit" "0: DAC bus clock disabled in Sleep mode,1: DAC bus clock enabled in Sleep mode"
bitfld.long 0x4 10. "COMPSMEN,COMP bus clock enable during Sleep mode bit" "0: COMP bus clock disabled in Sleep mode,1: COMP bus clock enabled in Sleep mode"
newline
bitfld.long 0x4 9. "LCDCSMEN,LCDC bus clock enable during Sleep mode bit" "0: LCDC bus clock disabled in Sleep mode,1: LCDC bus clock enabled in Sleep mode"
bitfld.long 0x4 8. "SYSCFGSMEN,SYSCFG bus clock enable during Sleep mode bit" "0: SYSCFG bus clock disabled in Sleep mode,1: SYSCFG bus clock enabled in Sleep mode"
newline
bitfld.long 0x4 1. "TIM16SMEN,TIM16 bus clock enable during Sleep mode bit" "0: TIM16 bus clock disabled in Sleep mode,1: TIM16 bus clock enabled in Sleep mode"
bitfld.long 0x4 0. "TIM2SMEN,TIM2 bus clock enable during Sleep mode bit" "0: TIM2 bus clock disabled in Sleep mode,1: TIM2 bus clock enabled in Sleep mode"
line.long 0x8 "APB1SMENR,APB1SMENR register"
bitfld.long 0x8 23. "I2C2SMEN,I2C2 clock enable during Sleep mode bit" "0: I2C2 clock disabled in Sleep mode,1: I2C2 clock enabled in Sleep mode"
bitfld.long 0x8 21. "I2C1SMEN,I2C1 clock enable during Sleep mode bit" "0: I2C1 clock disabled in Sleep mode,1: I2C1 clock enabled in Sleep mode"
newline
bitfld.long 0x8 14. "SPI3SMEN,SPI3 bus clock enable during Sleep mode bit" "0: SPI3 bus clock disabled in Sleep mode,1: SPI3 bus clock enabled in Sleep mode"
bitfld.long 0x8 10. "USARTSMEN,USART bus clock enable during Sleep mode bit" "0: USART bus clock disabled in Sleep mode,1: USART bus clock enabled in Sleep mode"
newline
bitfld.long 0x8 8. "LPUARTSMEN,LPUART bus clock enable during Sleep mode bit" "0: LPUART bus clock disabled in Sleep mode,1: LPUART bus clock enabled in Sleep mode"
bitfld.long 0x8 4. "ADCDIGSMEN,ADCDIG bus clock enable during Sleep mode bit" "0: ADCDIG bus clock disabled in Sleep mode,1: ADCDIG bus clock enabled in Sleep mode"
newline
bitfld.long 0x8 0. "SPI1SMEN,SPI1 bus clock enable during Sleep mode bit" "0: SPI1 bus clock disabled in Sleep mode,1: SPI1 bus clock enabled in Sleep mode"
tree.end
tree "RNG (Random Number Generator)"
base ad:0x48600000
group.long 0x0++0x7
line.long 0x0 "RNG_CR,RNG_CR register"
bitfld.long 0x0 3. "TST_CLK,RNG Test Clock bit." "0,1"
bitfld.long 0x0 2. "RNG_DIS,RNG Disable bit." "0,1"
line.long 0x4 "RNG_SR,RNG_SR register"
bitfld.long 0x4 2. "FAULT,Fault Reveal bit." "0,1"
rbitfld.long 0x4 1. "REVCLK,RNGCLK Clock Reveal bit." "0,1"
rbitfld.long 0x4 0. "RNGRDY,New Random Value Ready." "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "RNG_VAL,RNG_VAL register"
hexmask.long.word 0x0 0.--15. 1. "RANDOM_VALUE,Random Value"
group.long 0x80++0x7
line.long 0x0 "RNG_TCR,RNG_TCR register"
bitfld.long 0x0 0. "TCR,Test-control register" "0,1"
line.long 0x4 "RNG_ITIP,RNG_ITIP register"
bitfld.long 0x4 0. "ITIP,Integration-test input register" "0,1"
rgroup.long 0xFE0++0x1F
line.long 0x0 "RNGPeriphID0,RNGPeriphID0 register"
hexmask.long.byte 0x0 0.--7. 1. "PartNumber0,These bits are read back as 0xE1"
line.long 0x4 "RNGPeriphID1,RNGPeriphID1 register"
hexmask.long.byte 0x4 4.--7. 1. "Designer0,These bits are read back as 0x00"
hexmask.long.byte 0x4 0.--3. 1. "PartNumber1,These bits are read back as 0x05"
line.long 0x8 "RNGPeriphID2,RNGPeriphID2 register"
hexmask.long.byte 0x8 4.--7. 1. "Revision,These bits are read back as 0x02"
hexmask.long.byte 0x8 0.--3. 1. "Designer1,These bits are read back as 0x08"
line.long 0xC "RNGPeriphID3,RNGPeriphID3 register"
hexmask.long.byte 0xC 0.--7. 1. "Configuration,These bits are read back as 0x00"
line.long 0x10 "RNGPCellID0,RNGPCellID0 register"
hexmask.long.byte 0x10 0.--7. 1. "RNGPCellID0,These bits are read back as 0x0D"
line.long 0x14 "RNGPCellID1,RNGPCellID1 register"
hexmask.long.byte 0x14 0.--7. 1. "RNGPCellID1,These bits are read back as 0xF0"
line.long 0x18 "RNGPCellID2,RNGPCellID2 register"
hexmask.long.byte 0x18 0.--7. 1. "RNGPCellID2,These bits are read back as 0x05"
line.long 0x1C "RNGPCellID3,RNGPCellID3 register"
hexmask.long.byte 0x1C 0.--7. 1. "RNGPCellID3,These bits are read back as 0xB1"
tree.end
tree "RTC (Real Time Clock)"
base ad:0x40004000
group.long 0x0++0x17
line.long 0x0 "RTC_TR,RTC_TR register"
bitfld.long 0x0 22. "PM,AM/PM notation." "0: AM or 24-hour format,1: PM"
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
line.long 0x4 "RTC_DR,RTC_DR register"
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format."
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format."
newline
bitfld.long 0x4 13.--15. "WDU,Week day units" "0: forbidden,1: Monday,?,?,?,?,?,?"
bitfld.long 0x4 12. "MT,Month tens in BCD format." "0,1"
newline
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format."
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format." "0,1,2,3"
newline
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format."
line.long 0x8 "RTC_CR,RTC_CR register"
bitfld.long 0x8 24. "ITSE,Timestamp on internal event enable" "0: Internal event timestamp disable,1: Internal event timestamp enable"
bitfld.long 0x8 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled"
newline
bitfld.long 0x8 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,?,?"
bitfld.long 0x8 20. "POL,Output polarity" "0: The pin is high when ALRAF/WUTF is asserted,1: The pin is low when ALRAF/WUTF is asserted"
newline
bitfld.long 0x8 19. "COSEL,Calibration output selection" "0: Calibration output is 512 Hz,1: Calibration output is 1 Hz"
bitfld.long 0x8 18. "BKP,Backup" "0,1"
newline
bitfld.long 0x8 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time"
bitfld.long 0x8 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time"
newline
bitfld.long 0x8 15. "TSIE,Time-stamp interrupt enable" "0: Time-stamp Interrupt disable,1: Time-stamp Interrupt enable"
bitfld.long 0x8 14. "WUTIE,Wakeup timer interrupt enable" "0: Wakeup timer interrupt disabled,1: Wakeup timer interrupt enabled"
newline
bitfld.long 0x8 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled"
bitfld.long 0x8 11. "TSE,Timestamp enable" "0: Timestamp disable,1: Timestamp enable"
newline
bitfld.long 0x8 10. "WUTE,Wakeup timer enable" "0: Wakeup timer disabled,1: Wakeup timer enabled"
bitfld.long 0x8 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled"
newline
bitfld.long 0x8 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format"
bitfld.long 0x8 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values,1: Calendar values"
newline
bitfld.long 0x8 3. "TSEDGE,Time-stamp event active edge" "0: RTC_TS input rising edge generates a time-stamp..,1: RTC_TS input falling edge generates a time-stamp.."
bitfld.long 0x8 0.--2. "WUCKSEL,Wakeup clock selection" "0: RTC/16 clock is selected,1: RTC/8 clock is selected,?,?,?,?,?,?"
line.long 0xC "RTC_ISR,RTC_ISR register"
bitfld.long 0xC 17. "ITSF,Internal time-stamp flag" "0,1"
bitfld.long 0xC 16. "RECALPF,Recalibration pending Flag" "0,1"
newline
bitfld.long 0xC 13. "TAMP1F,RTC_TAMP1 detection flag" "0,1"
bitfld.long 0xC 12. "TSOVF,This flag is set by hardware when a time-stamp event occurs while TSF is already set." "0,1"
newline
bitfld.long 0xC 11. "TSF,This flag is set by hardware when a time-stamp event occurs." "0,1"
bitfld.long 0xC 10. "WUTF,Wakeup timer flag" "0,1"
newline
bitfld.long 0xC 8. "ALRAF,Alarm A flag" "0,1"
bitfld.long 0xC 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.."
newline
bitfld.long 0xC 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed"
bitfld.long 0xC 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized"
newline
bitfld.long 0xC 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized"
bitfld.long 0xC 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending"
newline
bitfld.long 0xC 2. "WUTWF,Wakeup timer write flag" "0: Wakeup timer configuration update not allowed,1: Wakeup timer configuration update allowed"
bitfld.long 0xC 0. "ALRAWF,Alarm A write flag" "0: Alarm A update not allowed,1: Alarm A update allowed"
line.long 0x10 "RTC_PRER,RTC_PRER register"
hexmask.long.byte 0x10 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor"
hexmask.long.word 0x10 0.--14. 1. "PREDIV_S,Synchronous prescaler factor"
line.long 0x14 "RTC_WUTR,RTC_WUTR register"
hexmask.long.word 0x14 0.--15. 1. "WUT,Wakeup auto-reload value bits"
group.long 0x1C++0x3
line.long 0x0 "RTC_ALRMAR,RTC_ALRMAR register"
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day dont care in Alarm A comparison"
bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day"
newline
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format." "0,1,2,3"
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format."
newline
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours dont care in Alarm A comparison"
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
newline
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
newline
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes dont care in Alarm A comparison"
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds dont care in Alarm A comparison"
newline
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
wgroup.long 0x24++0x3
line.long 0x0 "RTC_WPR,RTC_WPR register"
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
rgroup.long 0x28++0x3
line.long 0x0 "RTC_SSR,RTC_SSR register"
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
wgroup.long 0x2C++0x3
line.long 0x0 "RTC_SHIFTR,RTC_SHIFTR register"
bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar"
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
group.long 0x30++0x7
line.long 0x0 "RTC_TSTR,RTC_TSTR register"
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
line.long 0x4 "RTC_TSDR,RTC_TSDR register"
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 12. "MT,Month tens in BCD format." "0,1"
newline
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format."
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format." "0,1,2,3"
newline
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format."
rgroup.long 0x38++0x3
line.long 0x0 "RTC_TSSSR,RTC_TSSSR register"
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
group.long 0x3C++0xB
line.long 0x0 "RTC_CALR,RTC_CALR register"
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5 ppm" "0: No RTCCLK pulses are added,1: One RTCCLK pulse is effectively inserted every.."
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "0,1"
newline
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "0,1"
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
line.long 0x4 "RTC_TAMPCR,RTC_TAMPCR register"
bitfld.long 0x4 18. "TAMP1MF,Tamper 1 mask flag" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event"
bitfld.long 0x4 17. "TAMP1NOERASE,Tamper 1 no erase" "0: Tamper 1 event erases the backup registers,1: Tamper 1 event does not erase the backup registers"
newline
bitfld.long 0x4 16. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt is disabled if TAMPIE = 0,1: Tamper 1 interrupt enabled"
bitfld.long 0x4 15. "TAMPPUDIS,RTC_TAMPx pull-up disable" "0: Precharge RTC_TAMPx pins before sampling,1: Disable precharge of RTC_TAMPx pins"
newline
bitfld.long 0x4 13.--14. "TAMPPRCH,RTC_TAMPx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles"
bitfld.long 0x4 11.--12. "TAMPFLT,RTC_TAMPx filter count" "0: Tamper event is activated on edge of RTC_TAMPx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.."
newline
bitfld.long 0x4 8.--10. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768,1: RTCCLK / 16384,2: RTCCLK / 8192,3: RTCCLK / 4096,4: RTCCLK / 2048,5: RTCCLK / 1024,6: RTCCLK / 512,7: RTCCLK / 256"
bitfld.long 0x4 7. "TAMPTS,Activate timestamp on tamper detection event" "0: Tamper detection event does not cause a..,1: Save timestamp on tamper detection event"
newline
bitfld.long 0x4 2. "TAMPIE,Tamper interrupt enable" "0: Tamper interrupt disabled,1: Tamper interrupt enabled"
bitfld.long 0x4 1. "TAMP1TRG,Active level for RTC_TAMP1 input" "0: RTC_TAMP1 input rising edge triggers a tamper..,1: RTC_TAMP1 input falling edge triggers a tamper.."
newline
bitfld.long 0x4 0. "TAMP1E,RTC_TAMP1 input detection enable" "0: RTC_TAMP1 detection disabled,1: RTC_TAMP1 detection enabled"
line.long 0x8 "RTC_ALRMASSR,RTC_ALRMASSR register"
hexmask.long.byte 0x8 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
hexmask.long.word 0x8 0.--14. 1. "SS,Sub seconds value"
group.long 0x4C++0xB
line.long 0x0 "RTC_OR,RTC_OR register"
bitfld.long 0x0 1. "RTC_OUT_RMP,RTC_OUT remap" "0: RTC_ALARM is output on PA9,1: RTC_CALIB is output on PA9 and RTC_ALARM is.."
bitfld.long 0x0 0. "ALARMOUTTYPE,RTC_ALARM on PA8 output type" "0: RTC_ALARM when mapped on PA8 is open-drain output,1: RTC_ALARM when mapped on PA8 is push-pull output"
line.long 0x4 "RTC_BKP0R,RTC_BKPxR register"
hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers."
line.long 0x8 "RTC_BKP1R,RTC_BKPxR register"
hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers."
tree.end
tree "SPI (Serial Peripheral Interface/Inter IC Sound)"
base ad:0x0
tree "SPI1"
base ad:0x41002000
group.long 0x0++0x13
line.long 0x0 "SPI_SSPCR1,SPI_SSPCR1 register"
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode enable. This bit enables half-duplex communication using" "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled,1: Output enabled"
newline
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation Enabled"
bitfld.long 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer,1: Next transmit value is from Tx CRC register"
newline
bitfld.long 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
bitfld.long 0x0 10. "RXONLY,Receive only mode enabled." "0: Full duplex,1: Output disabled"
newline
bitfld.long 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
newline
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
bitfld.long 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
newline
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,?,?,?,?,?,?"
bitfld.long 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
newline
bitfld.long 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
bitfld.long 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
line.long 0x4 "SPI_SSPCR2,SPI_SSPCR2 register"
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
newline
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
newline
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked"
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked"
newline
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
bitfld.long 0x4 4. "FRF,Frame format" "0: SPI Motorola mode,?"
newline
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
bitfld.long 0x4 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
newline
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
line.long 0x8 "SPI_SSPSR,SPI_SSPSR register"
rbitfld.long 0x8 11.--12. "FTLVL,FIFO Transmission Level" "0: FIFO empty,1: 1/4 FIFO,?,?"
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,?,?"
newline
rbitfld.long 0x8 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
rbitfld.long 0x8 7. "BSY,Busy flag" "0: SPI,1: SPI"
newline
rbitfld.long 0x8 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
rbitfld.long 0x8 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
newline
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPIx_RXCRCR value,1: CRC value received does not match the.."
rbitfld.long 0x8 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
newline
rbitfld.long 0x8 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0: No more empty space in Tx buffer,1: At least one empty space in Tx buffer"
newline
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
line.long 0xC "SPI_SSPDR,SPI_SSPDR register"
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
line.long 0x10 "SPI_SSPCRCPR,SPI_SSPCRCPR register"
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
rgroup.long 0x14++0x7
line.long 0x0 "SPI_SSPRXCRCR,SPI_SSPRXCRCR register"
hexmask.long.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
line.long 0x4 "SPI_SSPTXCRCR,SPI_SSPTXCRCR register"
bitfld.long 0x4 0. "TXCRC,Tx CRC register" "0,1"
tree.end
tree "SPI3"
base ad:0x41007000
group.long 0x0++0x13
line.long 0x0 "SPI_SSPCR1,SPI_SSPCR1 register"
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode enable. This bit enables half-duplex communication using" "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled,1: Output enabled"
newline
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation Enabled"
bitfld.long 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer,1: Next transmit value is from Tx CRC register"
newline
bitfld.long 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
bitfld.long 0x0 10. "RXONLY,Receive only mode enabled." "0: Full duplex,1: Output disabled"
newline
bitfld.long 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
newline
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
bitfld.long 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
newline
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,?,?,?,?,?,?"
bitfld.long 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
newline
bitfld.long 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
bitfld.long 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
line.long 0x4 "SPI_SSPCR2,SPI_SSPCR2 register"
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
newline
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
newline
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked"
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked"
newline
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
bitfld.long 0x4 4. "FRF,Frame format" "0: SPI Motorola mode,?"
newline
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
bitfld.long 0x4 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
newline
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
line.long 0x8 "SPI_SSPSR,SPI_SSPSR register"
rbitfld.long 0x8 11.--12. "FTLVL,FIFO Transmission Level" "0: FIFO empty,1: 1/4 FIFO,?,?"
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,?,?"
newline
rbitfld.long 0x8 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
rbitfld.long 0x8 7. "BSY,Busy flag" "0: SPI,1: SPI"
newline
rbitfld.long 0x8 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
rbitfld.long 0x8 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
newline
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPIx_RXCRCR value,1: CRC value received does not match the.."
rbitfld.long 0x8 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
newline
rbitfld.long 0x8 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0: No more empty space in Tx buffer,1: At least one empty space in Tx buffer"
newline
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
line.long 0xC "SPI_SSPDR,SPI_SSPDR register"
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
line.long 0x10 "SPI_SSPCRCPR,SPI_SSPCRCPR register"
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
rgroup.long 0x14++0x7
line.long 0x0 "SPI_SSPRXCRCR,SPI_SSPRXCRCR register"
hexmask.long.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
line.long 0x4 "SPI_SSPTXCRCR,SPI_SSPTXCRCR register"
bitfld.long 0x4 0. "TXCRC,Tx CRC register" "0,1"
group.long 0x1C++0x7
line.long 0x0 "SPI2S_I2SCFGR,SPI2S_I2SCFGR register"
bitfld.long 0x0 12. "ASTREN,Asynchronous start enable." "0: The Asynchronous start is disabled. When the I2S..,1: The Asynchronous start is enabled. When the I2S.."
bitfld.long 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
newline
bitfld.long 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
bitfld.long 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave,1: Slave,?,?"
newline
bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
bitfld.long 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard,?,?"
newline
bitfld.long 0x0 3. "CKPOL,Steady state clock polarity" "0: I2S clock steady state is low level,1: I2S clock steady state is high level"
bitfld.long 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,?,?"
newline
bitfld.long 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
line.long 0x4 "SPI2S_I2SPR,SPI2S_I2SPR register"
bitfld.long 0x4 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
bitfld.long 0x4 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is ="
newline
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,I2S linear prescaler"
tree.end
tree.end
tree "SUBG (Sub-GHz Radio IP)"
base ad:0x0
tree "DYNAMIC (Dynamic Registers)"
base ad:0x49000500
group.long 0x0++0x2B
line.long 0x0 "PCKTLEN_CONFIG,PCKTLEN_CONFIG register"
hexmask.long.word 0x0 0.--15. 1. "PCKTLEN,This bit field has different meanings/usages:"
line.long 0x4 "MOD0_CONFIG,MOD0_CONFIG register"
bitfld.long 0x4 31. "PA_CLKON_LOCKONTX,Enable the clock on analog PA in LOCKONTX state" "0,1"
newline
bitfld.long 0x4 26. "BT_SEL,Select BT value for GFSK" "0,1"
newline
bitfld.long 0x4 24.--25. "CONST_MAP,Also known as FOUR_GFSK_CONST_MAP" "0,1,2,3"
newline
bitfld.long 0x4 20.--22. "MOD_TYPE,Select the modulation type" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 16.--19. 1. "DATARATE_E,The exponent of the specified data rate (default: 38."
newline
hexmask.long.word 0x4 0.--15. 1. "DATARATE_M,The mantissa of the specified data rate (default: 38."
line.long 0x8 "MOD1_CONFIG,MOD1_CONFIG register"
hexmask.long.byte 0x8 20.--23. 1. "CHFLT_E,Exponent of the channel filter BW (default: 100 kHz)"
newline
hexmask.long.byte 0x8 16.--19. 1. "CHFLT_M,Mantissa of the channel filter BW (default: 100 kHz)"
newline
hexmask.long.byte 0x8 8.--11. 1. "FDEV_E,Exponent of the frequency deviation (default: 28."
newline
hexmask.long.byte 0x8 0.--7. 1. "FDEV_M,Mantissa of the frequency deviation (default: 28."
line.long 0xC "SNYTH_FREQ,SNYTH_FREQ register"
bitfld.long 0xC 30. "BS,Synthesizer band selector i." "0,1"
newline
hexmask.long.byte 0xC 20.--27. 1. "SYNTH_INT,PLL integer divide factor (default: 868 MHz XTAL: 48 MHz)"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "SYNTH_FRAC,Fractional part of the PLL fractional divide factor (default: 868 MHz XTAL: 48 MHz)"
line.long 0x10 "VCO_CAL_CONFIG,VCO_CAL_CONFIG register"
bitfld.long 0x10 31. "VCO_CALIB_REQ,Define if the Radio FSM must launch a VCO calibration request after VCO start-up" "0,1"
newline
bitfld.long 0x10 23. "VCO_CALFREQ_EXT_SEL,Select the mode to provide an external VCO frequency calibration value through VCO_CALFREQ_EXT bit field" "0,1"
newline
hexmask.long.byte 0x10 16.--22. 1. "VCO_CALFREQ_EXT,VCO Cbank frequency calibration word."
newline
bitfld.long 0x10 15. "VCO_CALAMP_EXT_SEL,Select the mode to provide an external VCO amplitude calibration value through VCO_CALAMP_EXT bit field" "0,1"
newline
hexmask.long.word 0x10 0.--13. 1. "VCO_CALAMP_EXT,VCO magnitude calibration word in thermometric code"
line.long 0x14 "RX_TIMER,RX_TIMER register"
bitfld.long 0x14 31. "RX_OR_nAND_SELECT,Select logical OR or logcial AND to apply on CS/PQI/SQI timeout mask" "0,1"
newline
bitfld.long 0x14 30. "RX_SQI_TIMEOUT_MASK,- 0: SYNC valid flag does not contribute to timeout disabling" "0: SYNC valid flag does not contribute to timeout..,?"
newline
bitfld.long 0x14 29. "RX_PQI_TIMEOUT_MASK,- 0: PREAMBLE valid flag does not contribute to timeout disabling" "0: PREAMBLE valid flag does not contribute to..,?"
newline
bitfld.long 0x14 28. "RX_CS_TIMEOUT_MASK,- 0: CS flag does not contribute to timeout disabling" "0: CS flag does not contribute to timeout disabling,?"
newline
hexmask.long.tbyte 0x14 0.--22. 1. "RX_TIMEOUT,RX timer timeout (relative duration in interpolated absolute time unit)"
line.long 0x18 "DATABUFFER_THR,DATABUFFER_THR register"
hexmask.long.word 0x18 16.--31. 1. "TX_ALMOST_EMPTY_THR,Almost Empty threshold for TX Data Buffers."
newline
hexmask.long.word 0x18 0.--15. 1. "RX_ALMOST_FULL_THR,Almost Full threshold for RX Data Buffers"
line.long 0x1C "RFSEQ_IRQ_ENABLE,RFSEQ_IRQ_ENABLE register"
bitfld.long 0x1C 31. "AGC_CALIB_DONE_E,Enable interrupt on AGC_CALIB_DONE_F flag" "0,1"
newline
bitfld.long 0x1C 30. "SAFEASK_CALIB_DONE_E,Enable interrupt on SAFEASK_CALIB_DONE_F flag" "0,1"
newline
bitfld.long 0x1C 28. "RRM_CMD_END_E,Enable interrupt on RRM_CMD_END_F flag" "0,1"
newline
bitfld.long 0x1C 27. "RRM_CMD_START_E,Enable interrupt on RRM_CMD_END_F flag" "0,1"
newline
bitfld.long 0x1C 26. "SEQ_E,Enable interrupt on SEQ_F flag" "0,1"
newline
bitfld.long 0x1C 24. "HW_ANA_FAILURE_E,Enable interrupt on HW_ANA_FAILURE_F flag" "0,1"
newline
bitfld.long 0x1C 22. "AHB_ACCESS_ERROR_E,Enable interrupt on AHB_ACCESS_ERROR_F flag" "0,1"
newline
bitfld.long 0x1C 21. "TX_ALMOST_EMPTY_1_E,Enable interrupt on TX_ALMOST_EMPTY_1_F flag" "0,1"
newline
bitfld.long 0x1C 20. "TX_ALMOST_EMPTY_0_E,Enable interrupt on TX_ALMOST_EMPTY_0_F flag" "0,1"
newline
bitfld.long 0x1C 19. "RX_ALMOST_FULL_1_E,Enable interrupt on RX_ALMOST_FULL_1_F flag" "0,1"
newline
bitfld.long 0x1C 18. "RX_ALMOST_FULL_0_E,Enable interrupt on RX_ALMOST_FULL_0_F flag" "0,1"
newline
bitfld.long 0x1C 17. "DATABUFFER1_USED_E,Enable interrupt on DATABUFFER1_USED_F flag" "0,1"
newline
bitfld.long 0x1C 16. "DATABUFFER0_USED_E,Enable interrupt on DATABUFFER0_USED_F flag" "0,1"
newline
bitfld.long 0x1C 14. "SYNC_VALID_E,Enable interrupt on SYNC_VALID_F flag" "0,1"
newline
bitfld.long 0x1C 13. "PREAMBLE_VALID_E,Enable interrupt on PREAMBLE_VALID_F flag" "0,1"
newline
bitfld.long 0x1C 12. "CS_E,Enable interrupt on CS_F flag" "0,1"
newline
bitfld.long 0x1C 9. "COMMAND_REJECTED_E,Enable interrupt on COMMAND_REJECTED flag" "0,1"
newline
bitfld.long 0x1C 8. "SABORT_DONE_E,Enable interrupt on SABORT command treated and done flag" "0,1"
newline
bitfld.long 0x1C 7. "RXTIMER_STOP_CDT_E,Enable interrupt on RXTIMER_STOP_CDT_F flag" "0,1"
newline
bitfld.long 0x1C 4. "FAST_RX_TERM_E,Enable interrupt on FAST_RX_TERM_F flag" "0,1"
newline
bitfld.long 0x1C 3. "RX_CRC_ERROR_E,Enable interrupt on RX_CRC_ERROR_F flag" "0,1"
newline
bitfld.long 0x1C 2. "RX_TIMEOUT_E,Enable interrupt on RX_TIMEOUT_F flag" "0,1"
newline
bitfld.long 0x1C 1. "RX_OK_E,Enable interrupt on RX_OK_F flag" "0,1"
newline
bitfld.long 0x1C 0. "TX_DONE_E,Enable interrupt on TX_DONE_F flag" "0,1"
line.long 0x20 "ADDITIONAL_CTRL,ADDITIONAL_CTRL register"
bitfld.long 0x20 31. "AS_ENABLE,Enable the antenna switching feature." "0,1"
newline
bitfld.long 0x20 20.--22. "TIME_CAPTURESEL,Select the trigger event to capture the interpolated absolute time in the TIME_CAPTURE[31:0] register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 16.--17. "PA_FC,Power control bandwidth selection according data rate" "0,1,2,3"
newline
hexmask.long.byte 0x20 8.--15. 1. "CH_SPACING,Channel spacing."
newline
hexmask.long.byte 0x20 0.--7. 1. "CH_NUM,Channel number."
line.long 0x24 "FAST_RX_TIMER,FAST_RX_TIMER register"
bitfld.long 0x24 8. "FAST_CS_TERM_EN,Enable the Fast RX Termination feature" "0,1"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAST_RX_TIMEOUT,Fast RX termination timer value (corresponding to the delay to measure the RSSI and to let the HW check CS flag information)"
line.long 0x28 "COMMAND,COMMAND register"
bitfld.long 0x28 26. "BACK2LOCKON,Request to the Radio FSM to stay in LOCKON state when exiting a RX or a TX" "0,1"
newline
bitfld.long 0x28 25. "BACK2ACTIVE,Select the default/return state for the Radio FSM to be ACTIVE2" "0,1"
newline
hexmask.long.byte 0x28 0.--3. 1. "COMMAND_ID,Opcode coresponding to a command:"
tree.end
tree "MISC (Miscellanous Registers)"
base ad:0x49000700
rgroup.long 0x0++0x3
line.long 0x0 "RFIP_VERSION,RFIP_VERSION register"
hexmask.long.byte 0x0 12.--15. 1. "PRODUCT,Used for major upgrades (new protocols support / new features)"
hexmask.long.byte 0x0 8.--11. 1. "VERSION,Version of the MR_SubG (to be used for cut upgrades)"
hexmask.long.byte 0x0 4.--7. 1. "REVISION,Revision of the MR_SubG (to be used for metal fixes)"
wgroup.long 0x4++0x3
line.long 0x0 "RRM_UDRA_CTRL,RRM_UDRA_CTRL register"
bitfld.long 0x0 0. "RRM_CMD_REQ,Action bit: write 1 to request a RRM-UDRA command." "0,1"
group.long 0x8++0x3
line.long 0x0 "SEQUENCER_CTRL,SEQUENCER_CTRL register"
bitfld.long 0x0 1. "DISABLE_SEQ,Enable/disable the Sequencer" "0,1"
bitfld.long 0x0 0. "GEN_SEQ_TRIGGER,Action bit: write 1 to generate a trigger event on Sequencer." "0,1"
rgroup.long 0xC++0x7
line.long 0x0 "ABSOLUTE_TIME,ABSOLUTE_TIME register"
hexmask.long 0x0 0.--31. 1. "ABSOLUTE_TIME,Indicate the interpolated absolute."
line.long 0x4 "SCM_COUNTER_VAL,SCM_COUNTER_VAL register"
hexmask.long.word 0x4 0.--14. 1. "SCM_COUNTER_CURRVAL,Slow Clock Measurement: number of 16 MHz clock cycles contained in 32 slow clock periods."
group.long 0x14++0x7
line.long 0x0 "SCM_MIN_MAX,SCM_MIN_MAX register"
bitfld.long 0x0 31. "CLEAR_MIN_MAX,Write 1' to clear the SCM_COUNTER_MINVAL and SCM_COUNTER_MAXVAL bit fields." "0,1"
hexmask.long.word 0x0 16.--30. 1. "SCM_COUNTER_MAXVAL,Slow Clock Measurement: maximum SCM_COUNTER value seen since the counter is ON and since last clear request."
hexmask.long.word 0x0 0.--14. 1. "SCM_COUNTER_MINVAL,Slow Clock Measurement: minimum SCM_COUNTER value seen since the counter is ON and since last clear request."
line.long 0x4 "WAKEUP_IRQ_STATUS,WAKEUP_IRQ_STATUS register"
bitfld.long 0x4 1. "RFIP_WAKEUP_F,Set when the interpolated absolute time matches the RFIP_WAKEUPTIME while WAKEUP_CTRL." "0,1"
bitfld.long 0x4 0. "CPU_WAKEUP_F,Set when the interpolated absolute time matches the CPU_WAKEUPTIME while WAKEUP_CTRL." "0,1"
tree.end
tree "READ_ONLY (Read-Only Registers)"
base ad:0x49000600
group.long 0x0++0x7
line.long 0x0 "RFSEQ_IRQ_STATUS,RFSEQ_IRQ_STATUS register"
bitfld.long 0x0 31. "AGC_CALIB_DONE_F,Valid RSSI value available in the RSSI_RUNNING bit field flag." "0,1"
bitfld.long 0x0 30. "SAFEASK_CALIB_DONE_F,End of Safe-ASK PA calibration flag." "0,1"
bitfld.long 0x0 28. "RRM_CMD_END_F,RRM-UDRA command list execution ended flag." "0,1"
bitfld.long 0x0 27. "RRM_CMD_START_F,RRM-UDRA command list execution started flag." "0,1"
newline
bitfld.long 0x0 26. "SEQ_F,Sequencer completion flag." "0,1"
bitfld.long 0x0 24. "HW_ANA_FAILURE_F,Analog HW failure flag (PLL lock / unlock error calibration error)" "0,1"
bitfld.long 0x0 22. "AHB_ACCESS_ERROR_F,An AHB transfer issue occurred for one of the AHB masters (RRM Data Buffer Manager Sequencer)." "0,1"
bitfld.long 0x0 21. "TX_ALMOST_EMPTY_1_F,Data Buffer1 used (read during a TX) up to programmed thresold flag" "0,1"
newline
bitfld.long 0x0 20. "TX_ALMOST_EMPTY_0_F,Data Buffer0 used (read during a TX) up to programmed thresold flag" "0,1"
bitfld.long 0x0 19. "RX_ALMOST_FULL_1_F,Data Buffer1 used (written during a RX) up to programmed thresold flag" "0,1"
bitfld.long 0x0 18. "RX_ALMOST_FULL_0_F,Data Buffer0 used (written during a RX) up to programmed thresold flag" "0,1"
bitfld.long 0x0 17. "DATABUFFER1_USED_F,Data Buffer 1 fully read in TX or fully written in RX flag" "0,1"
newline
bitfld.long 0x0 16. "DATABUFFER0_USED_F,Data Buffer 0 fully read in TX or fully written in RX flag" "0,1"
bitfld.long 0x0 14. "SYNC_VALID_F,Valid SYNC word detection flag." "0,1"
bitfld.long 0x0 13. "PREAMBLE_VALID_F,Valid PREAMBLE detection flag." "0,1"
bitfld.long 0x0 12. "CS_F,Carrier Sense (RSSI over threshold) flag" "0,1"
newline
bitfld.long 0x0 9. "COMMAND_REJECTED_F,Command rejection flag." "0,1"
bitfld.long 0x0 8. "SABORT_DONE_F,SABORT command treated and done flag" "0,1"
bitfld.long 0x0 7. "RXTIMER_STOP_CDT_F,Enable interrupt on RXTIMER_STOP_CDT_F flag" "0,1"
bitfld.long 0x0 4. "FAST_RX_TERM_F,Fast RX Termination flag" "0,1"
newline
bitfld.long 0x0 3. "RX_CRC_FRROR_F,Reception with CRC error flag" "0,1"
bitfld.long 0x0 2. "RX_TIMEOUT_F,Reception timeout flag" "0,1"
bitfld.long 0x0 1. "RX_OK_F,Reception ended and OK flag" "0,1"
bitfld.long 0x0 0. "TX_DONE_F,Transmission done flag" "0,1"
line.long 0x4 "RFSEQ_STATUS_DETAIL,RFSEQ_STATUS_DETAIL register"
bitfld.long 0x4 15. "SEQ_COMPLETE_F,The Sequencer has ended the last defined SeqAction properly( NextAction math or null pointer)" "0,1"
bitfld.long 0x4 14. "SEQ_ACTIONTIMEOUT_F,The Sequencer has ended because the current SeqAction reached its ActionTimeout." "0,1"
bitfld.long 0x4 11. "PLL_CALAMP_ERROR_F,VCO amplitude calibration error flag" "0,1"
bitfld.long 0x4 10. "PLL_CALFREQ_ERROR_F,VCO frequency calibration error flag" "0,1"
newline
bitfld.long 0x4 9. "PLL_UNLOCK_F,PLL unlock event flag" "0,1"
bitfld.long 0x4 8. "PLL_LOCK_FAIL_F,PLL lock fail status flag" "0,1"
bitfld.long 0x4 5. "DBM_FIFO_ERROR_F,Data Buffer Manager internal FIFO overflow/underflow flag." "0,1"
rgroup.long 0x8++0x2F
line.long 0x0 "RADIO_FSM_INFO,RADIO_FSM_INFO register"
hexmask.long.byte 0x0 0.--4. 1. "RADIO_FSM_STATE,State of the Radio FSM"
line.long 0x4 "RX_INDICATOR,RX_INDICATOR register"
bitfld.long 0x4 31. "ANT_SELECT,Currently selected antenna" "0,1"
hexmask.long.byte 0x4 24.--27. 1. "AGC_WORD,AGC word of the received packet."
hexmask.long.word 0x4 12.--20. 1. "RSSI_LEVEL_RUN,Continuous level of the output of the measured RSSI value"
hexmask.long.word 0x4 0.--8. 1. "RSSI_LEVEL_ON_SYNC,RSSI level captured at the end of the SYNC word detection of the received packet."
line.long 0x8 "RX_INFO_REG,RX_INFO_REG register"
hexmask.long.word 0x8 0.--15. 1. "RX_PCKTLEN_OUT,Indicates received packet length in bytes:"
line.long 0xC "RX_CRC_REG,RX_CRC_REG register"
hexmask.long 0xC 0.--31. 1. "RX_CRC_OUT,CRC field of the received packet (read-only info)"
line.long 0x10 "QI_INFO,QI_INFO register"
hexmask.long.byte 0x10 16.--23. 1. "AFC_CORRECTION,AFC value frozen at sync reception."
bitfld.long 0x10 14. "SQI_SEC,Indicate if measured SQI refers to SYNC word or secondary SYNC word" "0,1"
hexmask.long.byte 0x10 8.--13. 1. "SQI_INFO,SYNC Quality Indicator (SQI) value of the received packet."
hexmask.long.byte 0x10 0.--7. 1. "PQI_INFO,Preamble Quality Indicator (PQI) value of the received packet."
line.long 0x14 "DATABUFFER_INFO,DATABUFFER_INFO register"
bitfld.long 0x14 31. "CURRENT_DATABUFFER,Indicates which Data Buffer is currently used by the HW" "0,1"
hexmask.long.word 0x14 16.--30. 1. "NB_DATABUFFER_USED,Provides the number of data buffers which have been fully used"
hexmask.long.word 0x14 0.--15. 1. "CURRENT_DATABUFFER_COUNT,Indicates the number of bytes used in the last used DATA BUFFER."
line.long 0x18 "TIME_CAPTURE,TIME_CAPTURE register"
hexmask.long 0x18 0.--31. 1. "TIME_CAPTURE,Interpolated absolute time value captured on specific programmable event through TIME_CAPTURESEL[2:0] bit field."
line.long 0x1C "IQC_CORRECTION_OUT,IQC_CORRECTION_OUT register"
hexmask.long.tbyte 0x1C 0.--23. 1. "IQC_CORRECT_OUT,Final correction value output from IQC (compensation engine)."
line.long 0x20 "PA_SAFEASK_OUT,PA_SAFEASK_OUT register"
hexmask.long.byte 0x20 0.--7. 1. "PA_CODEMAX,Safe ASK level (provided after a CALIB_SAFEASK command) indicating the maximum PA Power to program before reaching ohmic saturation."
line.long 0x24 "VCO_CALIB_OUT,VCO_CALIB_OUT register"
hexmask.long.word 0x24 8.--21. 1. "VCO_CALAMP_OUT,VCO amplitude calibration value currently output by the VCO calibration block (and applied on the VCO when ON)"
hexmask.long.byte 0x24 0.--6. 1. "VCO_CALFREQ_OUT,VCO frequency calibration value currently output by the VCO calibration block (and applied on the VCO when ON)"
line.long 0x28 "SEQ_INFO,SEQ_INFO register"
hexmask.long.byte 0x28 0.--4. 1. "SEQ_FSM_STATE,Current state of the Sequencer"
line.long 0x2C "SEQ_EVENT_STATUS,SEQ_EVENT_STATUS register"
hexmask.long 0x2C 0.--31. 1. "SEQ_EVENT_STATUS,Current value of the seq_event_status used by the Sequencer for next action mask comparison."
tree.end
tree "RETAINED (Reatined Registers)"
base ad:0x49000780
rgroup.long 0x0++0x3
line.long 0x0 "RFIP_WAKEUPTIME,RFIP_WAKEUPTIME register"
hexmask.long 0x0 0.--31. 1. "RFIP_WAKEUPTIME,(Absolute) Target time to wakeup the RFIP."
group.long 0x4++0xF
line.long 0x0 "CPU_WAKEUPTIME,CPU_WAKEUPTIME register"
hexmask.long 0x0 1.--31. 1. "CPU_WAKEUPTIME,(Absolute) Target time to wakeup the CPU."
line.long 0x4 "WAKEUP_CTRL,WAKEUP_CTRL register"
rbitfld.long 0x4 31. "RFIP_WAKEUP_EN,Indicates if the wakeup timer has to wakeup the SoC (match on RFIP_WAKEUPTIME[31:4] bit field only) + trigger an event on the Sequencer and set the RFIP_WAKEUP_F in the WAKEUP_IRQ_STATUS Misc register when match on RFIP_WAKEUPTIME[31:0].." "0,1"
bitfld.long 0x4 30. "CPU_WAKEUP_EN,Indicates if the wakeup timer has to wakeup the SoC (match on CPU_WAKEUPTIME[31:4] bit field only) + set the CPU_WAKEUP_F in the WAKEUP_IRQ_STATUS Misc register when match on CPU_WAKEUPTIME[31:0] occurs." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "SOC_WAKEUP_OFFSET,Delay to be considered by the Wakeup block to anticipate the wakeup request to the PWRC of the SoC versus the target to wakeup the RFIP (or the CPU)."
line.long 0x8 "RRM_CMDLIST_PTR,RRM_CMDLIST_PTR register"
bitfld.long 0x8 31. "CMDLIST_PTR_VALID,Indicate if a command list has to be executed or not" "0,1"
hexmask.long.word 0x8 0.--15. 1. "CMDLIST_PTR_OFFSET,Contain the offset versus the SoC RAM base address where to find the RRM-UDRA command list entry point."
line.long 0xC "SEQ_GLOBALTABLE_PTR,SEQ_GLOBALTABLE_PTR register"
hexmask.long.word 0xC 0.--15. 1. "SEQ_GLOBALTABLE_PTR,Contain the offset versus the SoC RAM base address of the GlobalConfiguration RAM table entry point."
tree.end
tree "STATIC (Static Registers)"
base ad:0x49000400
group.long 0x0++0x3B
line.long 0x0 "PCKT_CONFIG,PCKT_CONFIG register"
bitfld.long 0x0 30.--31. "POSTAMBLE_SEQ,Packet postamble control: postamble bit sequence selection" "0,1,2,3"
hexmask.long.byte 0x0 24.--29. 1. "POSTAMBLE_LENGTH,Length of the POSTAMBLE in pair of bits (0 to 126 bits)"
bitfld.long 0x0 22.--23. "PREAMBLE_SEQ,Select the PREAMBLE pattern to be applied" "0,1,2,3"
hexmask.long.word 0x0 12.--21. 1. "PREAMBLE_LENGTH,Length of the PREAMBLE in pairs of bits (0 to 2046)"
newline
bitfld.long 0x0 11. "FIX_VAR_LEN,Select the length mode" "0,1"
bitfld.long 0x0 10. "LEN_WIDTH,Indicates if the LENGTH field is defined on 1 byte or 2 bytes" "0,1"
bitfld.long 0x0 9. "SYNC_PRESENT,Indicate if a SYNC word is present on the frame or not (null length)" "0,1"
hexmask.long.byte 0x0 4.--8. 1. "SYNC_LEN,Length of the SYNC (and secondary) SYNC word in 1-bit granularity"
newline
bitfld.long 0x0 3. "SECONDARY_SYNC_SEL,In TX mode: this bit selects which synchro word is sent on the frame between SYNC and SEC_SYNC" "0,1"
bitfld.long 0x0 0.--2. "CRC_MODE,CRC type (0 8 16 16 802." "0,1,2,3,4,5,6,7"
line.long 0x4 "SYNC,SYNC register"
hexmask.long 0x4 0.--31. 1. "SYNC,Synchro word."
line.long 0x8 "SEC_SYNC,SEC_SYNC register"
hexmask.long 0x8 0.--31. 1. "SEC_SYNC,Secondary Synchro word."
line.long 0xC "CRC_INIT,CRC_INIT register"
hexmask.long 0xC 0.--31. 1. "CRC_INIT_VAL,CRC intialization value"
line.long 0x10 "PCKT_CTRL,PCKT_CTRL register"
bitfld.long 0x10 31. "FORCE_2FSK_SYNC_MODE,Force SYNC word to be formatted as a 2-(G)FSK bit steam instead of 4-(G)FSK" "0,1"
bitfld.long 0x10 29. "PN_SEL,Select the Pseudo Random Binary Sequence (PRBS) polynomial to apply when the selected transmission mode is PN mode (TX_MODE = '11')" "0,1"
bitfld.long 0x10 28. "MOD_INTERP_EN,Enable frequency interpolator (for 2-GFSK and 4-GFSK)" "0,1"
bitfld.long 0x10 27. "FCS_TYPE_4G,FCS type value in header field for 802." "0,1"
newline
bitfld.long 0x10 26. "FEC_TYPE_4G,FEC type for 802." "0,1"
bitfld.long 0x10 25. "INT_EN_4G,This field is used as Interleaving enable for 802." "0,1"
bitfld.long 0x10 24. "MANCHESTER_TYPE,Select the Manchester encoding polarity" "0,1"
bitfld.long 0x10 21.--22. "CODING_SEL,Coding / decoding selection" "0,1,2,3"
newline
hexmask.long.word 0x10 12.--20. 1. "WHIT_INIT,Whitening initialization value."
bitfld.long 0x10 11. "WHIT_EN,Whitening enable" "0,1"
bitfld.long 0x10 10. "WHIT_BF_FEC,Whitening before FEC feature" "0,1"
bitfld.long 0x10 7.--8. "TX_MODE,TX mode" "0,1,2,3"
newline
bitfld.long 0x10 4.--6. "RX_MODE,RX mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 3. "FOUR_FSK_SYM_SWAP,Invert bit to symbol mapping for 4-(G)FSK" "0,1"
bitfld.long 0x10 2. "BYTE_SWAP,Invert MSB-LSB transmission order (bitendianess)" "0,1"
bitfld.long 0x10 0. "PCKT_FORMAT,Packet format" "0,1"
line.long 0x14 "DATABUFFER0_PTR,DATABUFFER0_PTR register"
hexmask.long 0x14 2.--31. 1. "DATABUFFER0_PTR,Start address to be used by the Data Buffer0"
line.long 0x18 "DATABUFFER1_PTR,DATABUFFER1_PTR register"
hexmask.long 0x18 2.--31. 1. "DATABUFFER1_PTR,Start address to be used by the Data Buffer1"
line.long 0x1C "DATABUFFER_SIZE,DATABUFFER_SIZE register"
hexmask.long.word 0x1C 0.--15. 1. "DATABUFFER_SIZE,Size of the Data Buffers (Data Buffer0 and Data Buffer1) expressed in byte unit."
line.long 0x20 "PA_LEVEL_3_0,PA_LEVEL_3_0 register"
hexmask.long.byte 0x20 24.--31. 1. "PA_LEVEL3,Output power level for fourth step"
hexmask.long.byte 0x20 16.--23. 1. "PA_LEVEL2,Output power level for third step"
hexmask.long.byte 0x20 8.--15. 1. "PA_LEVEL1,Output power level for second step"
hexmask.long.byte 0x20 0.--7. 1. "PA_LEVEL0,Output power level for first step"
line.long 0x24 "PA_LEVEL_7_4,PA_LEVEL_7_4 register"
hexmask.long.byte 0x24 24.--31. 1. "PA_LEVEL7,Output power level for eighth step"
hexmask.long.byte 0x24 16.--23. 1. "PA_LEVEL6,Output power level for seventh step"
hexmask.long.byte 0x24 8.--15. 1. "PA_LEVEL5,Output power level for sixth step"
hexmask.long.byte 0x24 0.--7. 1. "PA_LEVEL4,Output power level for fifth step"
line.long 0x28 "PA_CONFIG,PA_CONFIG register"
bitfld.long 0x28 14. "PA_RAMP_ENABLE,Enable the power ramping" "0,1"
bitfld.long 0x28 13. "LIN_NLOG,Enable/disable the linear-to- log conversion of the PA code output from Safe-ASK calibrator" "0,1"
bitfld.long 0x28 10.--11. "PA_MODE,Configure the Power Amplifier (PA) mode" "0,1,2,3"
bitfld.long 0x28 8.--9. "PA_DRV_MODE,Select the PA topology" "0,1,2,3"
newline
bitfld.long 0x28 7. "ASK_OOK_EN,Enable the generation of the internal TXDATA signal provided to the FIR." "0,1"
bitfld.long 0x28 6. "PA_INTERP_EN,Enable power level interpolator." "0,1"
bitfld.long 0x28 2.--4. "PA_LEVEL_MAX_INDEX,Final level for power ramping (i." "0,1,2,3,4,5,6,7"
bitfld.long 0x28 0.--1. "PA_RAMP_STEP_WIDTH,Step width (unit: 1/8 of bit period)." "0,1,2,3"
line.long 0x2C "IF_CTRL,IF_CTRL register"
bitfld.long 0x2C 31. "IF_MODE,Select the cutoff frequency of the AAF for the analog RFSUBG IP" "0,1"
hexmask.long.word 0x2C 16.--28. 1. "IF_OFFSET_ANA,Intermediate frequency setting for the synthesizer configuration (default: 300 kHz)."
hexmask.long.word 0x2C 0.--12. 1. "IF_OFFSET_DIG,Intermediate frequency setting for the digital shift-to-baseband circuits (default: 300 kHz)"
line.long 0x30 "AS_QI_CTRL,AS_QI_CTRL register"
bitfld.long 0x30 31. "AS_CS_BLANKING,Blank received data if signal is below the CS threshold" "0,1"
bitfld.long 0x30 28.--30. "AS_MEAS_TIME,Select the RSSI measurement duration during Antenna switching procedure" "0,1,2,3,4,5,6,7"
bitfld.long 0x30 26.--27. "AS_EQU_CTRL,ISI cancellation equalizer" "0,1,2,3"
bitfld.long 0x30 16.--18. "SQI_THR,SQI threshold defining the precision requested to detect the SYNC word." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 15. "SQI_EN,SQI enable" "0,1"
bitfld.long 0x30 13.--14. "CS_MODE,Carrier Sense mode selection" "0,1,2,3"
hexmask.long.byte 0x30 9.--12. 1. "PQI_THR,PQI threshold (if 0 then )."
hexmask.long.word 0x30 0.--8. 1. "RSSI_THR,Signal detect threshold in 1 dB resolution."
line.long 0x34 "IQC_CONFIG,IQC_CONFIG register"
bitfld.long 0x34 31. "IQC_ENABLE,Enable IQC" "0,1"
bitfld.long 0x34 30. "REUSE_CORRECTION,Reuse last correction value" "0,1"
bitfld.long 0x34 29. "LOAD_IQC_INIT,Action bit to load the IQC_CORRECT_IN[23:0] bit field in the recirculation register when this bit is written to 1." "0,1"
hexmask.long.tbyte 0x34 0.--23. 1. "IQC_CORRECT_IN,Correction value Input for the IQ compensation engine (to be used as starting point or when the engine is disabled)."
line.long 0x38 "DSSS_CTRL,DSSS_CTRL register"
hexmask.long.byte 0x38 10.--15. 1. "ACQ_THR,DSSS acquisition threshold"
bitfld.long 0x38 8.--9. "ACQ_HITS,DSSS acquisition hits" "0,1,2,3"
bitfld.long 0x38 7. "DSSS_EN,DSSS mode enable" "0,1"
bitfld.long 0x38 4.--6. "SPREADING_EXP,DSSS spreading exponent" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x38 0.--3. 1. "ACQ_WINDOW,DSSS acquisition window"
tree.end
tree.end
tree "SWITCHABLE (LPAWUR Switchable)"
base ad:0x49001040
rgroup.long 0x0++0x3
line.long 0x0 "RFIP_VERSION,RFIP_VERSION register"
hexmask.long.byte 0x0 12.--15. 1. "PRODUCT,Used for major upgrades (new protocols support / new features)"
hexmask.long.byte 0x0 8.--11. 1. "VERSION,Version of the RFIP (to be used for cut upgrades)"
hexmask.long.byte 0x0 4.--7. 1. "REVISION,Revision of the RFIP to be used for metal fixes)"
group.long 0x4++0x7
line.long 0x0 "IRQ_ENABLE,IRQ_ENABLE register"
bitfld.long 0x0 3. "FRAME_VALID_E,Frame ( payload + CRC) received wthout error (the CRC has been checked and is matching with the received CRC)." "0,1"
bitfld.long 0x0 2. "FRAME_COMPLETE_E,Frame ( payload + CRC) received the content of the PAYLOAD_X registers is valid." "0,1"
bitfld.long 0x0 1. "FRAME_SYNC_COMPLETE_E,Frame Sync has been detected the content of the PAYLOAD_X registers is not yet valid." "0,1"
bitfld.long 0x0 0. "BIT_SYNC_DETECTED_E,Preamble has been detected the content of the PAYLOAD_X registers is not yet valid." "0,1"
line.long 0x4 "STATUS,STATUS register"
bitfld.long 0x4 30.--31. "ERROR_F,- 11 : CRC error" "0,1,2,3"
bitfld.long 0x4 3. "FRAME_VALID_F,Frame ( payload + CRC) received wthout error (the CRC has been checked and is matching with the received CRC)." "0,1"
bitfld.long 0x4 2. "FRAME_COMPLETE_F,Frame ( payload + CRC) received the content of the PAYLOAD_X registers is valid." "0,1"
bitfld.long 0x4 1. "FRAME_SYNC_COMPLETE_F,Frame Sync has been detected the content of the PAYLOAD_X registers is not yet valid." "0,1"
bitfld.long 0x4 0. "BIT_SYNC_DETECTED_F,Preamble has been detected the content of the PAYLOAD_X registers is not yet valid." "0,1"
tree.end
tree "SYSCFG (System Controller)"
base ad:0x40000000
rgroup.long 0x0++0x7
line.long 0x0 "DIE_ID,DIE_ID register"
hexmask.long.byte 0x0 8.--11. 1. "PRODUCT,Product version."
newline
hexmask.long.byte 0x0 4.--7. 1. "VERSION,Cut version"
newline
hexmask.long.byte 0x0 0.--3. 1. "REVISION,Cut revision (metal fix)"
line.long 0x4 "JTAG_ID,JTAG_ID register"
hexmask.long.byte 0x4 28.--31. 1. "VERSION_NUMBER,Version"
newline
hexmask.long.word 0x4 12.--27. 1. "PART_NUMBER,Part number"
newline
hexmask.long.word 0x4 1.--11. 1. "MANUF_ID,Manufacturer ID"
group.long 0x8++0x37
line.long 0x0 "I2C_FMP_CTRL,I2C_FMP_CTRL register"
bitfld.long 0x0 9. "I2C2_PA14_FMP,I2C2_PA14_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SDA on PA14 I/O." "0: PA14 pin operated in standard mode,1: FM+ mode is enabled on PA14 pin"
newline
bitfld.long 0x0 8. "I2C2_PA13_FMP,I2C2_PA13_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SCL on PA13 I/O." "0: PA13 pin operated in standard mode,1: FM+ mode is enabled on PA13 pin"
newline
bitfld.long 0x0 7. "I2C2_PA7_FMP,I2C2_PA7_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SDA on PA7 I/O." "0: PA7 pin operated in standard mode,1: FM+ mode is enabled on PA7 pin"
newline
bitfld.long 0x0 6. "I2C2_PA6_FMP,I2C2_PA6_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SCL on PA6 I/O." "0: PA6 pin operated in standard mode,1: FM+ mode is enabled on PA6 pin"
newline
bitfld.long 0x0 5. "I2C1_PB11_FMP,I2C1_PB11_FMP: I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB11 I/O." "0: PB11 pin operated in standard mode,1: FM+ mode is enabled on PB11 pin"
newline
bitfld.long 0x0 4. "I2C1_PB10_FMP,I2C1_PB10_FMP: I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB10 I/O." "0: PB10 pin operated in standard mode,1: FM+ mode is enabled on PB10 pin"
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bitfld.long 0x0 3. "I2C1_PB7_FMP,I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB7 I/O." "0: PB7 pin operated in standard mode,1: FM+ mode is enabled on PB7 pin"
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bitfld.long 0x0 2. "I2C1_PB6_FMP,I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB6 I/O." "0: PB6 pin operated in standard mode,1: FM+ mode is enabled on PB6 pin"
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bitfld.long 0x0 1. "I2C1_PA1_FMP,I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PA1 I/O." "0: PA1 pin operated in standard mode,1: FM+ mode is enabled on PA1 pin"
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bitfld.long 0x0 0. "I2C1_PA0_FMP,I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PA0 I/O." "0: PA0 pin operated in standard mode,1: FM+ mode is enabled on PA0 pin"
line.long 0x4 "IO_DTR,IO_DTR register"
bitfld.long 0x4 31. "PB15_DT,PB15_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
newline
bitfld.long 0x4 30. "PB14_DT,PB14_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 29. "PB13_DT,PB13_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 28. "PB12_DT,PB12_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 27. "PB11_DT,PB11_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 26. "PB10_DT,PB10_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 25. "PB9_DT,PB9_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 24. "PB8_DT,PB8_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 23. "PB7_DT,PB7_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 22. "PB6_DT,PB6_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 21. "PB5_DT,PB5_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 20. "PB4_DT,PB4_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 19. "PB3_DT,PB3_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 18. "PB2_DT,PB2_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 17. "PB1_DT,PB1_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 16. "PB0_DT,PB0_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 15. "PA15_DT,PA15_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
newline
bitfld.long 0x4 14. "PA14_DT,PA14_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 13. "PA13_DT,PA13_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 12. "PA12_DT,PA12_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 11. "PA11_DT,PA11_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 10. "PA10_DT,PA10_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 9. "PA9_DT,PA9_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 8. "PA8_DT,PA8_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
newline
bitfld.long 0x4 7. "PA7_DT,PA7_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 6. "PA6_DT,PA6_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
newline
bitfld.long 0x4 5. "PA5_DT,PA5_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
newline
bitfld.long 0x4 4. "PA4_DT,PA4_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
newline
bitfld.long 0x4 3. "PA3_DT,PA3_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 2. "PA2_DT,PA2_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 1. "PA1_DT,PA1_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
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bitfld.long 0x4 0. "PA0_DT,PA0_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
line.long 0x8 "IO_IBER,IO_IBER register"
bitfld.long 0x8 31. "PB15_IBE,PB15_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
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bitfld.long 0x8 30. "PB14_IBE,PB14_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
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bitfld.long 0x8 29. "PB13_IBE,PB13_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
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bitfld.long 0x8 28. "PB12_IBE,PB12_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
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bitfld.long 0x8 27. "PB11_IBE,PB11_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
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bitfld.long 0x8 26. "PB10_IBE,PB10_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
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bitfld.long 0x8 25. "PB9_IBE,PB9_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 24. "PB8_IBE,PB8_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 23. "PB7_IBE,PB7_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 22. "PB6_IBE,PB6_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 21. "PB5_IBE,PB5_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 20. "PB4_IBE,PB4_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 19. "PB3_IBE,PB3_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 18. "PB2_IBE,PB2_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 17. "PB1_IBE,PB1_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 16. "PB0_IBE,PB0_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 15. "PA15_IBE,PA15_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 14. "PA14_IBE,PA14_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 13. "PA13_IBE,PA13_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 12. "PA12_IBE,PA12_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 11. "PA11_IBE,PA11_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 10. "PA10_IBE,PA10_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 9. "PA9_IBE,PA9_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 8. "PA8_IBE,PA8_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 7. "PA7_IBE,PA7_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 6. "PA6_IBE,PA6_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 5. "PA5_IBE,PA5_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 4. "PA4_IBE,PA4_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 3. "PA3_IBE,PA3_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 2. "PA2_IBE,PA2_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 1. "PA1_IBE,PA1_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 0. "PA0_IBE,PA0_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
line.long 0xC "IO_IEVR,IO_IEVR register"
bitfld.long 0xC 31. "PB15_IEV,PB15_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 30. "PB14_IEV,PB14_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 29. "PB13_IEV,PB13_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 28. "PB12_IEV,PB12_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 27. "PB11_IEV,PB11_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 26. "PB10_IEV,PB10_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 25. "PB9_IEV,PB9_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 24. "PB8_IEV,PB8_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 23. "PB7_IEV,PB7_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 22. "PB6_IEV,PB6_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 21. "PB5_IEV,PB5_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 20. "PB4_IEV,PB4_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
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bitfld.long 0xC 19. "PB3_IEV,PB3_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
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bitfld.long 0xC 18. "PB2_IEV,PB2_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 17. "PB1_IEV,PB1_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 16. "PB0_IEV,PB0_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 15. "PA15_IEV,PA15_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 14. "PA14_IEV,PA14_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 13. "PA13_IEV,PA13_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 12. "PA12_IEV,PA12_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 11. "PA11_IEV,PA11_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 10. "PA10_IEV,PA10_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 9. "PA9_IEV,PA9_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 8. "PA8_IEV,PA8_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 7. "PA7_IEV,PA7_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 6. "PA6_IEV,PA6_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 5. "PA5_IEV,PA5_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 4. "PA4_IEV,PA4_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 3. "PA3_IEV,PA3_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 2. "PA2_IEV,PA2_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 1. "PA1_IEV,PA1_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 0. "PA0_IEV,PA0_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
line.long 0x10 "IO_IER,IO_IER register"
bitfld.long 0x10 31. "PB15_IE,PB15_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 30. "PB14_IE,PB14_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 29. "PB13_IE,PB13_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 28. "PB12_IE,PB12_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 27. "PB11_IE,PB11_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 26. "PB10_IE,PB10_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 25. "PB9_IE,PB9_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 24. "PB8_IE,PB8_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 23. "PB7_IE,PB7_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 22. "PB6_IE,PB6_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 21. "PB5_IE,PB5_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 20. "PB4_IE,PB4_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 19. "PB3_IE,PB3_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 18. "PB2_IE,PB2_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 17. "PB1_IE,PB1_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 16. "PB0_IE,PB0_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 15. "PA15_IE,PA15_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 14. "PA14_IE,PA14_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x10 13. "PA13_IE,PA13_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x10 12. "PA12_IE,PA12_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x10 11. "PA11_IE,PA11_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x10 10. "PA10_IE,PA10_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x10 9. "PA9_IE,PA9_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x10 8. "PA8_IE,PA8_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x10 7. "PA7_IE,PA7_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x10 6. "PA6_IE,PA6_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x10 5. "PA5_IE,PA5_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x10 4. "PA4_IE,PA4_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x10 3. "PA3_IE,PA3_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x10 2. "PA2_IE,PA2_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x10 1. "PA1_IE,PA1_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
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bitfld.long 0x10 0. "PA0_IE,PA0_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
line.long 0x14 "IO_ISCR,IO_ISCR register"
bitfld.long 0x14 31. "PB15_ISC,PB15_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 30. "PB14_ISC,PB14_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 29. "PB13_ISC,PB13_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 28. "PB12_ISC,PB12_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 27. "PB11_ISC,PB11_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 26. "PB10_ISC,PB10_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 25. "PB9_ISC,PB9_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 24. "PB8_ISC,PB8_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 23. "PB7_ISC,PB7_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 22. "PB6_ISC,PB6_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 21. "PB5_ISC,PB5_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 20. "PB4_ISC,PB4_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 19. "PB3_ISC,PB3_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 18. "PB2_ISC,PB2_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 17. "PB1_ISC,PB1_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 16. "PB0_ISC,PB0_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 15. "PA15_ISC,PA15_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 14. "PA14_ISC,PA14_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 13. "PA13_ISC,PA13_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 12. "PA12_ISC,PA12_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 11. "PA11_ISC,PA11_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 10. "PA10_ISC,PA10_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 9. "PA9_ISC,PA9_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 8. "PA8_ISC,PA8_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 7. "PA7_ISC,PA7_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 6. "PA6_ISC,PA6_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 5. "PA5_ISC,PA5_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 4. "PA4_ISC,PA4_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 3. "PA3_ISC,PA3_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 2. "PA2_ISC,PA2_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 1. "PA1_ISC,PA1_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
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bitfld.long 0x14 0. "PA0_ISC,PA0_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
line.long 0x18 "PWRC_IER,PWRC_IER register"
bitfld.long 0x18 2. "WKUP_IE,WKUP_IE: Power Controller Wakeup event interrupt enable." "0: Interrupt on wakeup event seen by the PWRC is..,1: Interrupt on wakeup event seen by the PWRC is.."
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bitfld.long 0x18 1. "PVD_IE,PVD_IE: Programmable Voltage Detector interrupt enable." "0: PVD interrupt is disabled,1: PVD interrupt is enabled"
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bitfld.long 0x18 0. "BORH_IE,BORH_IE: BORH interrupt enable." "0: BORH interrupt is disabled,1: BORH interrupt is enabled"
line.long 0x1C "PWRC_ISCR,PWRC_ISCR register"
bitfld.long 0x1C 2. "WKUP_ISC,WKUP_ISC: Indicates the Power Controller receives a Wakeup event." "0: no pending interrupt,1: Wakeup event on PWRC occurred / interrupt occurred"
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bitfld.long 0x1C 1. "PVD_ISC,PVD_ISC: Programmable Voltage Detector status." "0: no pending interrupt,1: voltage went under programmed threshold /.."
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bitfld.long 0x1C 0. "BORH_ISC,BORH_ISC: BORH interrupt status." "0: no pending interrupt,1: voltage went under BORH threshold / interrupt.."
line.long 0x20 "GPIO_SWA_CTRL,GPIO_SWA_CTRL register"
bitfld.long 0x20 0. "ATB1_nPVD,ATB1_nPVD: select the analog feature on PB14 between ATB1 and PVD when the PB14 I/O" "0: PVD external voltage feature is selected,1: ATB1 feature is selected"
line.long 0x24 "INTAI_DTR,INTAI_DTR register"
bitfld.long 0x24 5. "RFIP_BUSY_STATUS_DT,RFIP_BUSY_STATUS_DT: detection type on RFIP_BUSY_STATUS signal:" "0: detection on edge,1: detection on level"
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bitfld.long 0x24 4. "COMP_DT,COMP_DT: detection type on COMP_OUT (after COMP_POL selection) signal:" "0: detection on edge,1: detection on level"
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bitfld.long 0x24 1. "RX_DT,RX_DT: detection type on RX_SEQUENCE signal:" "0: detection on edge,1: detection on level"
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bitfld.long 0x24 0. "TX_DT,TX_DT: detection type on TX_SEQUENCE signal:" "0: detection on edge,1: detection on level"
line.long 0x28 "INTAI_IBER,INTAI_IBER register"
bitfld.long 0x28 5. "RFIP_BUSY_STATUS_IBE,RFIP_BUSY_STATUS_IBE: interrupt edge register on RFIP_BUSY_STATUS signal:" "0: detection on single edge,1: detection on both edges"
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bitfld.long 0x28 4. "COMP_IBE,COMP_IBE: interrupt edge register on COMP_OUT signal:" "0: detection on single edge,1: detection on both edges"
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bitfld.long 0x28 1. "RX_IBE,RX_IBE: interrupt edge register on RX_SEQUENCE signal:" "0: detection on single edge,1: detection on both edges"
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bitfld.long 0x28 0. "TX_IBE,TX_IBE: interrupt edge register on TX_SEQUENCE signal:" "0: detection on single edge,1: detection on both edges"
line.long 0x2C "INTAI_IEVR,INTAI_IEVR register"
bitfld.long 0x2C 5. "RFIP_BUSY_STATUS_IEV,RFIP_BUSY_STATUS_IEV: interrupt polarity event on RFIP_BUSY_STATUS signal:" "0: detection on falling edge / low level,1: detection on rising edge / high level"
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bitfld.long 0x2C 4. "COMP_IEV,COMP_IEV: interrupt polarity event on COMP_OUT signal:" "0: detection on falling edge / low level,1: detection on rising edge / high level"
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bitfld.long 0x2C 1. "RX_IEV,RX_IEV: interrupt polarity event on RX_SEQUENCE signal:" "0: detection on falling edge / low level,1: detection on rising edge / high level"
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bitfld.long 0x2C 0. "TX_IEV,TX_IEV: interrupt polarity event on TX_SEQUENCE signal:" "0: detection on falling edge / low level,1: detection on rising edge / high level"
line.long 0x30 "INTAI_IER,INTAI_IER register"
bitfld.long 0x30 5. "RFIP_BUSY_STATUS_IE,RFIP_BUSY_STATUS_IE: interrupt enable on RFIP_BUSY_STATUS signal:" "0: RFIP_BUSY_STATUS interrupt is disabled,1: RFIP_BUSY_STATUS interrupt is enabled"
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bitfld.long 0x30 4. "COMP_IE,COMP_IE: interrupt enable on COMP_OUT signal:" "0: COMP_OUT interrupt is disabled,1: COMP_OUT interrupt is enabled"
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bitfld.long 0x30 1. "RX_IE,RX_IE: interrupt enable on RX_SEQUENCE signal:" "0: RX_SEQUENCE interrupt is disabled,1: RX_SEQUENCE interrupt is enabled"
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bitfld.long 0x30 0. "TX_IE,TX_IE: interrupt enable on TX_SEQUENCE signal:" "0: TX_SEQUENCE interrupt is disabled,1: TX_SEQUENCE interrupt is enabled"
line.long 0x34 "INTAI_ISCR,INTAI_ISCR register"
bitfld.long 0x34 5. "RFIP_BUSY_STATUS_ISC,RFIP_BUSY_STATUS_ISC: interrupt status on RFIP_BUSY_STATUS (can be a rising or a" "0: no activity on RFIP_BUSY_STATUS detected,1: activity on RFIP_BUSY_STATUS occurred"
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bitfld.long 0x34 4. "COMP_ISC,COMP_ISC: interrupt status on COMP_OUT (can be a rising or a falling edge depending on" "0: no activity on COMP_OUT detected,1: activity on COMP_OUT occurred"
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rbitfld.long 0x34 3. "RX_ISEDGE,RX_ISEDGE: interrupt edge status on RX_SEQUENCE signal:" "0: falling edge on RX_SEQUENCE detected,1: rising edge on RX_SEQUENCE detected"
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rbitfld.long 0x34 2. "TX_ISEDGE,TX_ISEDGE: interrupt edge status on TX_SEQUENCE signal:" "0: falling edge on TX_SEQUENCE detected,1: rising edge on TX_SEQUENCE detected"
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bitfld.long 0x34 1. "RX_ISC,RX_ISC: interrupt status on RX_SEQUENCE signal (can be a rising or a falling edge" "0: no activity on RX_SEQUENCE detected,1: activity on RX_SEQUENCE occurred"
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bitfld.long 0x34 0. "TX_ISC,TX_ISC:interrupt status on TX_SEQUENCE signal (can be a rising or a falling edge" "0: no activity on TX_SEQUENCE detected,1: activity on TX_SEQUENCE occurred"
rgroup.long 0x40++0x3
line.long 0x0 "SYSCFG_SR1,SYSCFG_SR1 register"
bitfld.long 0x0 5. "RFIP_BUSY_STATUS,RFIP_BUSY_STATUS: MR_SUBG BUSY status:" "0: MR_SUBG is not busy,1: MR_SUBG is busy"
group.long 0x44++0x3
line.long 0x0 "RF_DTB_CONFIG,RF_DTB_CONFIG register"
bitfld.long 0x0 0.--1. "RF_DTB_CONFIG,Controlling AF7 extended mode:" "0: MR_SUBG DTB default configuration,1: MR_SUBG DTB shuffled configuration,?,?"
tree.end
tree "TIM (General-Purpose Timer)"
base ad:0x0
tree "TIM2"
base ad:0x40002000
group.long 0x0++0x13
line.long 0x0 "CR1,CR1 register"
bitfld.long 0x0 11. "UIF_REMAP,UIFREMAP: UIF status bit remapping" "0: No remapping,1: Remapping enabled"
bitfld.long 0x0 8.--9. "CKD,CKD[1:0]: Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,?,?"
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bitfld.long 0x0 7. "ARPE,ARPE: Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
bitfld.long 0x0 5.--6. "CMS,CMS[1:0]: Center-aligned mode selection" "0: Edge-aligned mode,1: Center-aligned mode 1,?,?"
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bitfld.long 0x0 4. "DIR,DIR: Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
bitfld.long 0x0 3. "OPM,OPM: One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event"
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bitfld.long 0x0 2. "URS,URS: Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
bitfld.long 0x0 1. "UDIS,UDIS: Update disable" "0: UEV enabled,1: UEV disabled"
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bitfld.long 0x0 0. "CEN,CEN: Counter enable" "0: Counter disabled,1: Counter enabled"
line.long 0x4 "CR2,CR2 register"
bitfld.long 0x4 7. "TI1S,TI1S: TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1"
bitfld.long 0x4 4.--6. "MMS,MMS[2:0]: Master mode selection" "0: Reset,1: Enable,?,?,?,?,?,?"
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bitfld.long 0x4 3. "CCDS,CCDS: Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
line.long 0x8 "SMCR,SMCR register"
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection. See TS_2_0_ description" "0,1,2,3"
bitfld.long 0x8 16. "SMS_3,SMS[3]: Slave mode selection - bit 3" "0,1"
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bitfld.long 0x8 15. "ETP,ETP: External trigger polarity" "0: ETR is non-inverted,1: ETR is inverted"
bitfld.long 0x8 14. "ECE,ECE: External clock enable" "0: External clock mode 2 disabled,1: Setting the ECE bit has the same effect as.."
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bitfld.long 0x8 12.--13. "ETPS,ETPS[1:0]: External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,?,?"
hexmask.long.byte 0x8 8.--11. 1. "ETF,ETF[3:0]: External trigger filter"
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bitfld.long 0x8 7. "MSM,MSM: Master/Slave mode" "0: No action,1: The effect of an event on the trigger input"
bitfld.long 0x8 4.--6. "TS_2_0,TS[4:0]: Trigger selection" "0: Internal Trigger 0,1: Internal Trigger 1,?,?,?,?,?,?"
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bitfld.long 0x8 3. "OCCS,OCCS: OCREF clear selection" "0: OCREF_CLR_INT is connected to the OCREF_CLR input,1: OCREF_CLR_INT is connected to ETRF"
bitfld.long 0x8 0.--2. "SMS_2_0,SMS: Slave mode selection" "0: Slave mode disabled,1: Encoder mode 1,?,?,?,?,?,?"
line.long 0xC "DIER,DIER register"
bitfld.long 0xC 14. "TDE,TDE: Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
bitfld.long 0xC 12. "CC4DE,CC4DE: Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled"
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bitfld.long 0xC 11. "CC3DE,CC3DE: Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled"
bitfld.long 0xC 10. "CC2DE,CC2DE: Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
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bitfld.long 0xC 9. "CC1DE,CC1DE: Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
bitfld.long 0xC 8. "UDE,UDE: Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
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bitfld.long 0xC 6. "TIE,TIE: Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
bitfld.long 0xC 4. "CC4IE,CC4IE: Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled"
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bitfld.long 0xC 3. "CC3IE,CC3IE: Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled"
bitfld.long 0xC 2. "CC2IE,CC2IE: Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
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bitfld.long 0xC 1. "CC1IE,CC1IE: Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
bitfld.long 0xC 0. "UIE,UIE: Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
line.long 0x10 "SR,SR register"
bitfld.long 0x10 12. "CC4OF,CC4OF: Capture/Compare 4 overcapture flag" "0,1"
bitfld.long 0x10 11. "CC3OF,CC3OF: Capture/Compare 3 overcapture flag" "0,1"
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bitfld.long 0x10 10. "CC2OF,CC2OF: Capture/Compare 2 overcapture flag" "0,1"
bitfld.long 0x10 9. "CC1OF,CC1OF: Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
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bitfld.long 0x10 6. "TIF,TIF: Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending"
bitfld.long 0x10 4. "CC4IF,CC4IF: Capture/Compare 4 interrupt flag" "0,1"
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bitfld.long 0x10 3. "CC3IF,CC3IF: Capture/Compare 3 interrupt flag" "0,1"
bitfld.long 0x10 2. "CC2IF,CC2IF: Capture/Compare 2 interrupt flag" "0,1"
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bitfld.long 0x10 1. "CC1IF,CC1IF: Capture/Compare 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in TIMx_CCR1.."
bitfld.long 0x10 0. "UIF,UIF: Update interrupt flag" "0: No update occurred,1: Update interrupt pending"
wgroup.long 0x14++0x3
line.long 0x0 "EGR,EGR register"
bitfld.long 0x0 6. "TG,TG: Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register"
bitfld.long 0x0 4. "CC4G,CC4G: Capture/Compare 4 generation" "0,1"
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bitfld.long 0x0 3. "CC3G,CC3G: Capture/Compare 3 generation" "0,1"
bitfld.long 0x0 2. "CC2G,CC2G: Capture/Compare 2 generation" "0,1"
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bitfld.long 0x0 1. "CC1G,CC1G: Capture/Compare 1 generation" "0: No action,1: "
bitfld.long 0x0 0. "UG,UG: Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
group.long 0x18++0x3
line.long 0x0 "CCMR1,CCMR1 register"
bitfld.long 0x0 24. "OC2M_3,OC2M[3]: Output Compare 2 mode (bit 3)" "0,1"
bitfld.long 0x0 16. "OC1M_3,OC1M[3]: Output Compare 1 mode (bit 3)" "0,1"
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bitfld.long 0x0 15. "OC2CE,OC2CE: Output Compare 2 clear enable" "0,1"
bitfld.long 0x0 12.--14. "OC2M_2_0,OC2M[2:0]: Output Compare 2 mode" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 11. "OC2PE,OC2PE: Output Compare 2 preload enable" "0,1"
bitfld.long 0x0 10. "OC2FE,OC2FE: Output Compare 2 fast enable" "0,1"
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bitfld.long 0x0 8.--9. "CC2S,CC2S[1:0]: Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input,?,?"
bitfld.long 0x0 7. "OC1CE,OC1CE: Output Compare 1 Clear Enable" "0: OC1Ref is not affected by the ETRF Input,1: OC1Ref is cleared as soon as a High level is.."
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bitfld.long 0x0 4.--6. "OC1M_2_0,OC1M: Output Compare 1 mode" "0: Frozen,1: These bits can not be modified as long as LOCK..,2: In PWM mode,?,?,?,?,?"
bitfld.long 0x0 3. "OC1PE,OC1PE: Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled,1: These bits can not be modified as long as LOCK.."
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bitfld.long 0x0 2. "OC1FE,OC1FE: Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
bitfld.long 0x0 0.--1. "CC1S,CC1S: Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input,?,?"
group.long 0x18++0x7
line.long 0x0 "CCMR1_in,CCMR1_in register"
hexmask.long.byte 0x0 12.--15. 1. "IC2F,IC2F: Input capture 2 filter"
bitfld.long 0x0 10.--11. "IC2PSC,IC2PSC[1:0]: Input capture 2 prescaler" "0,1,2,3"
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bitfld.long 0x0 8.--9. "CC2S,CC2S: Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input,?,?"
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Bits 7:4 IC1F[3:0]: Input capture 1 filter"
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bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC: Input capture 1 prescaler" "0: no prescaler,1: capture is done once every 2 events,?,?"
bitfld.long 0x0 0.--1. "CC1S,CC1S: Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input,?,?"
line.long 0x4 "CCMR2,CCMR2 register"
bitfld.long 0x4 24. "OC4M_3,OC4M[3]: Output Compare 4 mode (bit 3)" "0,1"
bitfld.long 0x4 16. "OC3M_3,OC3M[3]: Output Compare 3 mode (bit 3)" "0,1"
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bitfld.long 0x4 15. "OC4CE,OC4CE: Output Compare 4 clear enable" "0,1"
bitfld.long 0x4 12.--14. "OC4M_2_0,OC4M[2:0]: Output Compare 4 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 11. "OC4PE,OC4PE: Output Compare 4 preload enable" "0,1"
bitfld.long 0x4 10. "OC4FE,OC4FE: Output Compare 4 fast enable" "0,1"
newline
bitfld.long 0x4 8.--9. "CC4S,CC4S: Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input,?,?"
bitfld.long 0x4 7. "OC3CE,OC3CE: Output compare 3 clear enable" "0,1"
newline
bitfld.long 0x4 4.--6. "OC3M_2_0,OC3M: Output compare 3 mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "OC3PE,OC3PE: Output compare 3 preload enable" "0,1"
newline
bitfld.long 0x4 2. "OC3FE,OC3FE: Output compare 3 fast enable" "0,1"
bitfld.long 0x4 0.--1. "CC3S,CC3S: Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input,?,?"
group.long 0x1C++0x27
line.long 0x0 "CCMR2_in,CCMR2_in register"
hexmask.long.byte 0x0 12.--15. 1. "IC4F,IC4F: Input capture 4 filter"
bitfld.long 0x0 10.--11. "IC4PSC,IC4PSC: Input capture 4 prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CC4S,CC4S: Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input,?,?"
hexmask.long.byte 0x0 4.--7. 1. "IC3F,IC3F: Input capture 3 filter"
newline
bitfld.long 0x0 2.--3. "IC3PSC,IC3PSC: Input capture 3 prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CC3S,CC3S: Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input,?,?"
line.long 0x4 "CCER,CCER register"
bitfld.long 0x4 15. "CC4NP,CC4NP: Capture/Compare 4 Complementary output Polarity." "0,1"
bitfld.long 0x4 13. "CC4P,CC4P: Capture/Compare 4 output polarity" "0,1"
newline
bitfld.long 0x4 12. "CC4E,CC4E: Capture/Compare 4 output enable" "0,1"
bitfld.long 0x4 11. "CC3NP,CC3NP: Capture/Compare 3 Complementary output Polarity." "0,1"
newline
bitfld.long 0x4 9. "CC3P,CC3P: Capture/Compare 3 output polarity" "0,1"
bitfld.long 0x4 8. "CC3E,CC3E: Capture/Compare 3 output enable" "0,1"
newline
bitfld.long 0x4 7. "CC2NP,CC2NP: Capture/Compare 2 Complementary output Polarity." "0,1"
bitfld.long 0x4 5. "CC2P,CC2P: Capture/Compare 2 output polarity" "0,1"
newline
bitfld.long 0x4 4. "CC2E,CC2E: Capture/Compare 2 output enable" "0,1"
bitfld.long 0x4 3. "CC1NP,CC1NP: Capture/Compare 1 Complementary output Polarity." "0: OC1N active high.,1: OC1N active low."
newline
bitfld.long 0x4 1. "CC1P,CC1P: Capture/Compare 1 output polarity" "0: Non-inverted/rising edge,1: Inverted/falling edge"
bitfld.long 0x4 0. "CC1E,CC1E: Capture/Compare 1 output enable" "0: Capture disabled,1: Capture enabled"
line.long 0x8 "CNT,CNT register"
rbitfld.long 0x8 31. "UIF_CPY,UIFCPY: UIF Copy" "0,1"
hexmask.long.word 0x8 0.--15. 1. "CNT,CNT[15:0]: Counter value"
line.long 0xC "PSC,PSC register"
hexmask.long.word 0xC 0.--15. 1. "PSC,PSC[15:0]: Prescaler value"
line.long 0x10 "ARR,ARR register"
hexmask.long.word 0x10 0.--15. 1. "ARR,ARR[15:0]: Prescaler value"
line.long 0x14 "RCR,RCR register"
hexmask.long.byte 0x14 0.--7. 1. "REP,REP[7:0]: Repetition counter value"
line.long 0x18 "CCR1,CCR1 register"
hexmask.long.word 0x18 0.--15. 1. "CCR1,CCR1[15:0]: Capture/Compare 1 value"
line.long 0x1C "CCR2,CCR2 register"
hexmask.long.word 0x1C 0.--15. 1. "CCR2,CCR2[15:0]: Capture/Compare 2 value"
line.long 0x20 "CCR3,CCR3 register"
hexmask.long.word 0x20 0.--15. 1. "CCR3,CCR3[15:0]: Capture/Compare 3 value"
line.long 0x24 "CCR4,CCR4 register"
hexmask.long.word 0x24 0.--15. 1. "CCR4,CCR4[15:0]: Capture/Compare 4 value"
group.long 0x48++0xB
line.long 0x0 "DCR,DCR register"
hexmask.long.byte 0x0 8.--12. 1. "DBL,DBL[4:0]: DMA burst length"
hexmask.long.byte 0x0 0.--4. 1. "DBA,DBA[4:0]: DMA base address"
line.long 0x4 "DMAR,DMAR register"
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMAB[15:0]: DMA register for burst accesses"
line.long 0x8 "OR1,OR1 register"
bitfld.long 0x8 2. "TI4_RMP,TI4_RMP: Input capture 4 remap" "0: TIM2 input capture 4 is connected to I/O,1: TIM2 input capture 4 is connected to COMP1-OUT"
bitfld.long 0x8 1. "OR1_1,This field is not used in Blue51. Not available in IUM" "0,1"
newline
bitfld.long 0x8 0. "ETR_RMP,ETR_RMP: ETR remapping capability" "0: TIMx_ETR is not connected to ADC AWD,1: TIMx_ETR is connected to ADC AWD"
group.long 0x60++0x3
line.long 0x0 "AF1,AF1 register"
bitfld.long 0x0 17. "ETR_SEL_3,ETRSEL[2:0]: External trigger source selection" "0,1"
bitfld.long 0x0 14.--16. "ETR_SEL,ETRSEL[2:0]: External trigger source selection" "0: TIMx External trigger legacy mode,1: TIMx External trigger source select COMP1_OUT,?,?,?,?,?,?"
group.long 0x68++0x3
line.long 0x0 "TISEL,TISEL register"
hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4SEL[3:0]: selects TI4[0] to TI4[15] input"
hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3SEL[3:0]: selects TI3[0] to TI3[15] input"
newline
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2SEL[3:0]: selects TI2[0] to TI2[15] input"
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL[3:0]: selects TI1[0] to TI1[15] input"
tree.end
tree "TIM16"
base ad:0x40005000
group.long 0x0++0x13
line.long 0x0 "CR1,CR1 register"
bitfld.long 0x0 11. "UIF_REMAP,UIFREMAP: UIF status bit remapping" "0: No remapping,1: Remapping enabled"
bitfld.long 0x0 8.--9. "CKD,CKD[1:0]: Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,?,?"
newline
bitfld.long 0x0 7. "ARPE,ARPE: Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
bitfld.long 0x0 3. "OPM,OPM: One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event"
newline
bitfld.long 0x0 2. "URS,URS: Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
bitfld.long 0x0 1. "UDIS,UDIS: Update disable" "0: UEV enabled,1: UEV disabled"
newline
bitfld.long 0x0 0. "CEN,CEN: Counter enable" "0: Counter disabled,1: Counter enabled"
line.long 0x4 "CR2,CR2 register"
bitfld.long 0x4 9. "OIS1N,OIS1N: Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
bitfld.long 0x4 8. "OIS1,OIS1: Output Idle state 1 (OC1 output)" "0: OC1=0,1: OC1=1"
newline
bitfld.long 0x4 7. "TI1S,TI1S: TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: Reserved"
bitfld.long 0x4 4.--6. "MMS,MMS[2:0]: Master mode selection" "0: Reset,1: Enable,?,?,?,?,?,?"
newline
bitfld.long 0x4 3. "CCDS,CCDS: Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
bitfld.long 0x4 2. "CCUS,CCUS: Capture/compare control update selection" "0: When capture/compare control bits are preloaded,1: When capture/compare control bits are preloaded"
newline
bitfld.long 0x4 0. "CCPC,CCPC: Capture/compare preloaded control" "0: CCxE,1: CCxE"
line.long 0x8 "SMCR,SMCR register"
bitfld.long 0x8 20.--21. "TS_4_3,TS[4:0]: Trigger selection. See TS_LSB description" "0,1,2,3"
bitfld.long 0x8 16. "SMS_3,SMS[3:0]: Slave mode selection. See SMS_LSB description" "0,1"
newline
bitfld.long 0x8 7. "MSM,MSM: Master/slave mode" "0: No action,1: The effect of an event on the trigger input"
bitfld.long 0x8 4.--6. "TS_2_0,TS[4:0]: Trigger selection" "0: Internal Trigger 0,1: Internal Trigger 1,?,?,?,?,?,?"
newline
bitfld.long 0x8 0.--2. "SMS_2_0,SMS[3:0]: Slave mode selection" "0,1,2,3,4,5,6,7"
line.long 0xC "DIER,DIER register"
bitfld.long 0xC 15. "BDE,BDE: Break DMA request Enable." "0: Break DMA request disabled,1: Break DMA request enabled"
bitfld.long 0xC 14. "TDE,TDE: Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
newline
bitfld.long 0xC 13. "CCUDE,CCUDE: CC-Update DMA request Enable." "0: CC-Update DMA request disabled,1: CC-Update DMA request enabled"
bitfld.long 0xC 9. "CC1DE,CC1DE: Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
newline
bitfld.long 0xC 8. "UDE,UDE: Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
bitfld.long 0xC 7. "BIE,BIE: Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
newline
bitfld.long 0xC 6. "TIE,TIE: Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
bitfld.long 0xC 5. "COMIE,COMIE: COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
newline
bitfld.long 0xC 1. "CC1IE,CC1IE: Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
bitfld.long 0xC 0. "UIE,UIE: Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
line.long 0x10 "SR,SR register"
bitfld.long 0x10 9. "CC1OF,CC1OF: Capture_Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
bitfld.long 0x10 7. "BIF,BIF: Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
newline
bitfld.long 0x10 6. "TIF,TIF: Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending"
bitfld.long 0x10 5. "COMIF,COMIF: COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
newline
bitfld.long 0x10 1. "CC1IF,CC1IF: Capture/Compare 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in TIMx_CCR1.."
bitfld.long 0x10 0. "UIF,UIF: Update interrupt flag" "0: No update occurred,1: Update interrupt pending"
wgroup.long 0x14++0x3
line.long 0x0 "EGR,EGR register"
bitfld.long 0x0 7. "BG,BG: Break generation" "0: No action,1: A break event is generated"
bitfld.long 0x0 6. "TG,TG: Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register"
newline
bitfld.long 0x0 5. "COMG,COMG: Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set"
bitfld.long 0x0 1. "CC1G,CC1G: Capture/Compare 1 generation" "0: No action,1: "
newline
bitfld.long 0x0 0. "UG,UG: Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
group.long 0x18++0x3
line.long 0x0 "CCMR1,CCMR1 register"
bitfld.long 0x0 16. "OC1M_3,OC1M[3]: Output Compare 1 mode (bit 3)" "0,1"
bitfld.long 0x0 7. "OC1CE,OC1CE: Output Compare 1 Clear Enable." "0: OC1REF is not affected by the ocref_clr_int signal,1: OC1REF is cleared as soon as a high level is.."
newline
bitfld.long 0x0 4.--6. "OC1M_2_0,OC1M[2:0]: Output Compare 1 mode (bits 2 to 0)" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "OC1PE,OC1PE: Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled,1: These bits can not be modified as long as LOCK.."
newline
bitfld.long 0x0 2. "OC1FE,OC1FE: Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
bitfld.long 0x0 0.--1. "CC1S,CC1S: Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input,?,?"
group.long 0x18++0x3
line.long 0x0 "CCMR1_in,CCMR1_in register"
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Bits 7:4 IC1F[3:0]: Input capture 1 filter"
bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC: Input capture 1 prescaler" "0: no prescaler,1: capture is done once every 2 events,?,?"
newline
bitfld.long 0x0 0.--1. "CC1S,CC1S: Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input,?,?"
group.long 0x20++0x17
line.long 0x0 "CCER,CCER register"
bitfld.long 0x0 3. "CC1NP,CC1NP: Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
bitfld.long 0x0 2. "CC1NE,CC1NE: Capture/Compare 1 complementary output enable" "0: Off,1: On"
newline
bitfld.long 0x0 1. "CC1P,CC1P: Capture/Compare 1 output polarity" "0: Non-inverted/rising edge,1: Inverted/falling edge"
bitfld.long 0x0 0. "CC1E,CC1E: Capture/Compare 1 output enable" "0: Capture disabled,1: Capture enabled"
line.long 0x4 "CNT,CNT register"
rbitfld.long 0x4 31. "UIF_CPY,UIFCPY: UIF Copy" "0,1"
hexmask.long.word 0x4 0.--15. 1. "CNT,CNT[15:0]: Counter value"
line.long 0x8 "PSC,PSC register"
hexmask.long.word 0x8 0.--15. 1. "PSC,PSC[15:0]: Prescaler value"
line.long 0xC "ARR,ARR register"
hexmask.long.word 0xC 0.--15. 1. "ARR,ARR[15:0]: Prescaler value"
line.long 0x10 "RCR,RCR register"
hexmask.long.byte 0x10 0.--7. 1. "REP,REP[7:0]: Repetition counter value"
line.long 0x14 "CCR1,CCR1 register"
hexmask.long.word 0x14 0.--15. 1. "CCR,CCR1[15:0]: Capture/Compare 1 value"
group.long 0x44++0xF
line.long 0x0 "BDTR,BDTR register"
bitfld.long 0x0 28. "BKBID,BKBID: Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
bitfld.long 0x0 26. "BKDSRM,BKDSRM: Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
newline
bitfld.long 0x0 15. "MOE,MOE: Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
bitfld.long 0x0 14. "AOE,AOE: Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
newline
bitfld.long 0x0 13. "BKP,BKP: Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
bitfld.long 0x0 12. "BKE,BKE: Break enable" "0: Break inputs (BRK) disabled,?"
newline
bitfld.long 0x0 11. "OSSR,OSSR: Off-state selection for Run mode" "0: When inactive,1: When inactive"
bitfld.long 0x0 10. "OSSI,OSSI: Off-state selection for Idle mode" "0: When inactive,1: When inactive"
newline
bitfld.long 0x0 8.--9. "LOCK,LOCK[1:0]: Lock configuration" "0: LOCK OFF,1: DTG bits in TIMx_BDTR register,2: LOCK Level 1 + CC Polarity bits,3: LOCK Level 2 + CC Control bits"
hexmask.long.byte 0x0 0.--7. 1. "DTG,DTG[7:0]: Dead-time generator setup"
line.long 0x4 "DCR,DCR register"
hexmask.long.byte 0x4 8.--12. 1. "DBL,DBL[4:0]: DMA burst length"
hexmask.long.byte 0x4 0.--4. 1. "DBA,DBA[4:0]: DMA base address"
line.long 0x8 "DMAR,DMAR register"
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMAB[15:0]: DMA register for burst accesses"
line.long 0xC "OR1,OR1 register"
bitfld.long 0xC 1.--2. "TI1_RMP,TI1_RMP[1:0]: Timer 16 input 1 connection" "0: TIM16 TI1 is connected to GPIO,1: TIM16 TI1 is connected to LCO,?,?"
bitfld.long 0xC 0. "OR1_0,Not used in Blue51. Not available in IUM" "0,1"
group.long 0x60++0x3
line.long 0x0 "AF1,AF1 register"
bitfld.long 0x0 10. "BKCMP1P,BKCMP1P: BRK COMP1 input polarity." "0: COMP1 input is active low,1: COMP1 input is active high"
bitfld.long 0x0 9. "BKINP,BKINP: BRK BKIN input polarity." "0: BKIN input is active low,1: BKIN input is active high"
newline
bitfld.long 0x0 1. "BKCMP1E,BKCMP1E: BRK COMP1 enable." "0: COMP1 input disabled,1: COMP1 input enabled"
bitfld.long 0x0 0. "BKINE,BKINE: BRK BKIN enable." "0: BKIN input disabled,1: BKIN input enabled"
group.long 0x68++0x3
line.long 0x0 "TISEL,TISEL register"
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL[3:0]: selects TI1[0] to TI1[15] input"
tree.end
tree.end
tree "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"
base ad:0x41004000
group.long 0x0++0x17
line.long 0x0 "CR1,CR1 register"
bitfld.long 0x0 31. "RXFFIE,RXFFIE :RXFIFO Full interrupt enable" "0,1"
bitfld.long 0x0 30. "TXFEIE,TXFEIE :TXFIFO empty interrupt enable" "0,1"
newline
bitfld.long 0x0 29. "FIFOEN,FIFOEN :FIFO mode enable" "0,1"
bitfld.long 0x0 28. "M_1,Word length" "0: 1 Start bit,1: 1 Start bit"
newline
bitfld.long 0x0 27. "EOBIE,EOBIE: End of Block interrupt enable" "0: Interrupt is inhibited,1: A USART interrupt is generated when the EOBF.."
bitfld.long 0x0 26. "RTOIE,RTOIE: Receiver timeout interrupt enable" "0,1"
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT[4:0]: Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT[4:0]: Driver Enable deassertion time"
newline
bitfld.long 0x0 15. "OVER8,OVER8: Oversampling mode" "0,1"
bitfld.long 0x0 14. "CMIE,CMIE: Character match interrupt enable" "0,1"
newline
bitfld.long 0x0 13. "MME,MME: Mute mode enable" "0,1"
bitfld.long 0x0 12. "M_0,M0: Word length" "0,1"
newline
bitfld.long 0x0 11. "WAKE,WAKE: Receiver wakeup method" "0,1"
bitfld.long 0x0 10. "PCE,PCE: Parity control enable" "0,1"
newline
bitfld.long 0x0 9. "PS,PS: Parity selection" "0,1"
bitfld.long 0x0 8. "PEIE,PEIE: PE interrupt enable" "0,1"
newline
bitfld.long 0x0 7. "TXEIE_TXFNFIE,TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable" "0,1"
bitfld.long 0x0 6. "TCIE,TCIE: Transmission complete interrupt enable" "0,1"
newline
bitfld.long 0x0 5. "RXNEIE_RXFNEIE,RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable" "0,1"
bitfld.long 0x0 4. "IDLEIE,IDLEIE: IDLE interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "TE,TE: Transmitter enable" "0,1"
bitfld.long 0x0 2. "RE,RE: Receiver enable" "0,1"
newline
bitfld.long 0x0 0. "UE,UE: USART enable" "0,1"
line.long 0x4 "CR2,CR2 register"
hexmask.long.byte 0x4 24.--31. 1. "ADD,ADD[7:0]: Address of the USART node"
bitfld.long 0x4 23. "RTOEN,RTOEN: Receiver timeout enable" "0,1"
newline
bitfld.long 0x4 21.--22. "ABRMOD,ABRMOD[1:0]: Auto baud rate mode" "?,1: Frame = Start10xxxxxx,?,?"
bitfld.long 0x4 20. "ABREN,ABREN: Auto baud rate enable" "0,1"
newline
bitfld.long 0x4 19. "MSBFIRST,MSBFIRST: Most significant bit first" "0,1"
bitfld.long 0x4 18. "DATAINV,DATAINV: Binary data inversion" "0: H,1: L"
newline
bitfld.long 0x4 17. "TXINV,TXINV: TX pin active level inversion" "0,1"
bitfld.long 0x4 16. "RXINV,RXINV: RX pin active level inversion" "0,1"
newline
bitfld.long 0x4 15. "SWAP,SWAP: Swap TX/RX pins" "0,1"
bitfld.long 0x4 14. "LINEN,LINEN: LIN mode enable" "0,1"
newline
bitfld.long 0x4 12.--13. "STOP,STOP[1:0]: STOP bits" "0,1,2,3"
bitfld.long 0x4 11. "CLKEN,CLKEN: Clock enable" "0,1"
newline
bitfld.long 0x4 10. "CPOL,CPOL: Clock polarity" "0,1"
bitfld.long 0x4 9. "CPHA,CPHA: Clock phase" "0,1"
newline
bitfld.long 0x4 8. "LBCL,LBCL: Last bit clock pulse" "0,1"
bitfld.long 0x4 6. "LBDIE,LBDIE: LIN break detection interrupt enable" "0,1"
newline
bitfld.long 0x4 5. "LBDL,LBDL: LIN break detection length" "0,1"
bitfld.long 0x4 4. "ADDM7,ADDM7:7-bit Address Detection/4-bit Address Detection" "0,1"
newline
bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1"
bitfld.long 0x4 0. "SLVEN,SLVEN: Synchronous Slave mode enable" "0,1"
line.long 0x8 "CR3,CR3 register"
bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG: TXFIFO threshold configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 28. "RXFTIE,RXFTIE: RXFIFO threshold interrupt enable" "0,1"
newline
bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG: Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 24. "TCBGTIE,TCBGTIE: Transmission Complete before guard time interrupt enable" "0,1"
newline
bitfld.long 0x8 23. "TXFTIE,TXFTIE: TXFIFO threshold interrupt enable" "0,1"
bitfld.long 0x8 17.--19. "SCARCNT,SCARCNT[2:0]: Smartcard auto-retry count" "?,?,?,?,?,?,?,7: number of automatic retransmission attempts"
newline
bitfld.long 0x8 15. "DEP,DEP: Driver enable polarity selection" "0,1"
bitfld.long 0x8 14. "DEM,DEM: Driver enable mode" "0,1"
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bitfld.long 0x8 13. "DDRE,DDRE: DMA Disable on Reception Error" "0,1"
bitfld.long 0x8 12. "OVRDIS,OVRDIS: Overrun Disable" "0,1"
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bitfld.long 0x8 11. "ONEBIT,ONEBIT: One sample bit method enable" "0,1"
bitfld.long 0x8 10. "CTSIE,CTSIE: CTS interrupt enable" "0,1"
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bitfld.long 0x8 9. "CTSE,CTSE: CTS enable" "0,1"
bitfld.long 0x8 8. "RTSE,RTSE: RTS enable" "0,1"
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bitfld.long 0x8 7. "DMAT,DMAT: DMA enable transmitter" "0,1"
bitfld.long 0x8 6. "DMAR,DMAR: DMA enable receiver" "0,1"
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bitfld.long 0x8 5. "SCEN,SCEN: Smartcard mode enable" "0,1"
bitfld.long 0x8 4. "NACK,NACK: Smartcard NACK enable" "0,1"
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bitfld.long 0x8 3. "HDSEL,HDSEL: Half-duplex selection" "0,1"
bitfld.long 0x8 2. "IRLP,IRLP: IrDA low-power" "0,1"
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bitfld.long 0x8 1. "IREN,IREN: IrDA mode enable" "0,1"
bitfld.long 0x8 0. "EIE,EIE: Error interrupt enable" "0,1"
line.long 0xC "BRR,BRR register"
hexmask.long.word 0xC 0.--15. 1. "BRR,BRR[15:4]"
line.long 0x10 "GTPR,GTPR register"
hexmask.long.byte 0x10 8.--15. 1. "GT,GT[7:0]: Guard time value"
hexmask.long.byte 0x10 0.--7. 1. "PSC,PSC[7:0]: Prescaler value"
line.long 0x14 "RTOR,RTOR register"
hexmask.long.byte 0x14 24.--31. 1. "BLEN,BLEN[7:0]: Block Length"
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,RTO[23:0]: Receiver timeout value"
wgroup.long 0x18++0x3
line.long 0x0 "RQR,RQR register"
bitfld.long 0x0 4. "TXFRQ,TXFRQ: Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFRQ,RXFRQ: Receive data flush request" "0,1"
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bitfld.long 0x0 2. "MMRQ,MMRQ: Mute mode request" "0,1"
bitfld.long 0x0 1. "SBKRQ,SBKRQ: Send break request" "0,1"
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bitfld.long 0x0 0. "ABRRQ,ABRRQ: Auto baud rate request" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "ISR,ISR register"
bitfld.long 0x0 27. "TXFT,TXFT: TXFIFO threshold flag" "0,1"
bitfld.long 0x0 26. "RXFT,RXFT: RXFIFO threshold flag" "0,1"
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bitfld.long 0x0 25. "TCBGT,TCBGT: Transmission complete before guard time flagl" "0,1"
bitfld.long 0x0 24. "RXFF,RXFF: RXFIFO Full" "0,1"
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bitfld.long 0x0 23. "TXFE,TXFE: TXFIFO Empty" "0,1"
bitfld.long 0x0 22. "REACK,REACK: Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,TEACK: Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 19. "RWU,RWU: Receiver wakeup from Mute mode" "0,1"
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bitfld.long 0x0 18. "SBKF,SBKF: Send break flag" "0,1"
bitfld.long 0x0 17. "CMF,CMF: Character match flag" "0,1"
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bitfld.long 0x0 16. "BUSY,BUSY: Busy flag" "0,1"
bitfld.long 0x0 15. "ABRF,ABRF: Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,ABRE: Auto baud rate error" "0,1"
bitfld.long 0x0 13. "UDR,UDR: SPI slave underrun error flag" "0,1"
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bitfld.long 0x0 12. "EOBF,EOBF: End of block flag" "0,1"
bitfld.long 0x0 11. "RTOF,RTOF: Receiver timeout" "0,1"
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bitfld.long 0x0 10. "CTS,CTS: CTS flag" "0,1"
bitfld.long 0x0 9. "CTSIF,CTSIF: CTS interrupt flag" "0,1"
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bitfld.long 0x0 8. "LBDF,LBDF: LIN break detection flag" "0,1"
bitfld.long 0x0 7. "TXE_TXFNF,TXE/TXFNF: Transmit data register empty/TXFIFO not full" "0,1"
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bitfld.long 0x0 6. "TC,TC: Transmission complete" "0,1"
bitfld.long 0x0 5. "RXNE_RXFNE,RXNE/RXFNE:Read data register not empty/RXFIFO not empty" "0,1"
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bitfld.long 0x0 4. "IDLE,IDLE: Idle line detected" "0,1"
bitfld.long 0x0 3. "ORE,ORE: Overrun error" "0,1"
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bitfld.long 0x0 2. "NF,NF: START bit Noise detection flag" "0,1"
bitfld.long 0x0 1. "FE,FE: Framing error" "0,1"
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bitfld.long 0x0 0. "PE,PE: Parity error" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "ICR,ICR register"
bitfld.long 0x0 17. "CMCF,CMCF: Character match clear flag" "0,1"
bitfld.long 0x0 13. "UDRCF,UDRCF:SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,EOBCF: End of block clear flag" "0,1"
bitfld.long 0x0 11. "RTOCF,RTOCF: Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTSCF: CTS clear flag" "0,1"
bitfld.long 0x0 8. "LBDCF,LBDCF: LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,TCBGTCF: Transmission complete before Guard time clear flag" "0,1"
bitfld.long 0x0 6. "TCCF,TCCF: Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFECF: TXFIFO empty clear flag" "0,1"
bitfld.long 0x0 4. "IDLECF,IDLECF: Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,ORECF: Overrun error clear flag" "0,1"
bitfld.long 0x0 2. "NECF,NECF: Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,FECF: Framing error clear flag" "0,1"
bitfld.long 0x0 0. "PECF,PECF: Parity error clear flag" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "RDR,RDR register"
hexmask.long.word 0x0 0.--8. 1. "RDR,RDR[8:0]: Receive data value"
group.long 0x28++0x7
line.long 0x0 "TDR,TDR register"
hexmask.long.word 0x0 0.--8. 1. "TDR,TDR[8:0]: Transmit data value"
line.long 0x4 "PRESC,PRESC register"
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER[3:0]: Clock prescaler"
tree.end
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AUTOINDENT.OFF
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